1 // SPDX-License-Identifier: GPL-2.0-only 2 /* Copyright(c) 2020 Intel Corporation. All rights reserved. */ 3 #include <linux/unaligned.h> 4 #include <linux/io-64-nonatomic-lo-hi.h> 5 #include <linux/moduleparam.h> 6 #include <linux/module.h> 7 #include <linux/delay.h> 8 #include <linux/sizes.h> 9 #include <linux/mutex.h> 10 #include <linux/list.h> 11 #include <linux/pci.h> 12 #include <linux/aer.h> 13 #include <linux/io.h> 14 #include <cxl/pci.h> 15 #include <cxl/mailbox.h> 16 #include "cxlmem.h" 17 #include "cxlpci.h" 18 #include "cxl.h" 19 #include "pmu.h" 20 21 /** 22 * DOC: cxl pci 23 * 24 * This implements the PCI exclusive functionality for a CXL device as it is 25 * defined by the Compute Express Link specification. CXL devices may surface 26 * certain functionality even if it isn't CXL enabled. While this driver is 27 * focused around the PCI specific aspects of a CXL device, it binds to the 28 * specific CXL memory device class code, and therefore the implementation of 29 * cxl_pci is focused around CXL memory devices. 30 * 31 * The driver has several responsibilities, mainly: 32 * - Create the memX device and register on the CXL bus. 33 * - Enumerate device's register interface and map them. 34 * - Registers nvdimm bridge device with cxl_core. 35 * - Registers a CXL mailbox with cxl_core. 36 */ 37 38 #define cxl_doorbell_busy(cxlds) \ 39 (readl((cxlds)->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET) & \ 40 CXLDEV_MBOX_CTRL_DOORBELL) 41 42 /* CXL 2.0 - 8.2.8.4 */ 43 #define CXL_MAILBOX_TIMEOUT_MS (2 * HZ) 44 45 /* 46 * CXL 2.0 ECN "Add Mailbox Ready Time" defines a capability field to 47 * dictate how long to wait for the mailbox to become ready. The new 48 * field allows the device to tell software the amount of time to wait 49 * before mailbox ready. This field per the spec theoretically allows 50 * for up to 255 seconds. 255 seconds is unreasonably long, its longer 51 * than the maximum SATA port link recovery wait. Default to 60 seconds 52 * until someone builds a CXL device that needs more time in practice. 53 */ 54 static unsigned short mbox_ready_timeout = 60; 55 module_param(mbox_ready_timeout, ushort, 0644); 56 MODULE_PARM_DESC(mbox_ready_timeout, "seconds to wait for mailbox ready"); 57 58 static int cxl_pci_mbox_wait_for_doorbell(struct cxl_dev_state *cxlds) 59 { 60 const unsigned long start = jiffies; 61 unsigned long end = start; 62 63 while (cxl_doorbell_busy(cxlds)) { 64 end = jiffies; 65 66 if (time_after(end, start + CXL_MAILBOX_TIMEOUT_MS)) { 67 /* Check again in case preempted before timeout test */ 68 if (!cxl_doorbell_busy(cxlds)) 69 break; 70 return -ETIMEDOUT; 71 } 72 cpu_relax(); 73 } 74 75 dev_dbg(cxlds->dev, "Doorbell wait took %dms", 76 jiffies_to_msecs(end) - jiffies_to_msecs(start)); 77 return 0; 78 } 79 80 #define cxl_err(dev, status, msg) \ 81 dev_err_ratelimited(dev, msg ", device state %s%s\n", \ 82 status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ 83 status & CXLMDEV_FW_HALT ? " firmware-halt" : "") 84 85 #define cxl_cmd_err(dev, cmd, status, msg) \ 86 dev_err_ratelimited(dev, msg " (opcode: %#x), device state %s%s\n", \ 87 (cmd)->opcode, \ 88 status & CXLMDEV_DEV_FATAL ? " fatal" : "", \ 89 status & CXLMDEV_FW_HALT ? " firmware-halt" : "") 90 91 /* 92 * Threaded irq dev_id's must be globally unique. cxl_dev_id provides a unique 93 * wrapper object for each irq within the same cxlds. 94 */ 95 struct cxl_dev_id { 96 struct cxl_dev_state *cxlds; 97 }; 98 99 static int cxl_request_irq(struct cxl_dev_state *cxlds, int irq, 100 irq_handler_t thread_fn) 101 { 102 struct device *dev = cxlds->dev; 103 struct cxl_dev_id *dev_id; 104 105 dev_id = devm_kzalloc(dev, sizeof(*dev_id), GFP_KERNEL); 106 if (!dev_id) 107 return -ENOMEM; 108 dev_id->cxlds = cxlds; 109 110 return devm_request_threaded_irq(dev, irq, NULL, thread_fn, 111 IRQF_SHARED | IRQF_ONESHOT, NULL, 112 dev_id); 113 } 114 115 static bool cxl_mbox_background_complete(struct cxl_dev_state *cxlds) 116 { 117 u64 reg; 118 119 reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 120 return FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_PCT_MASK, reg) == 100; 121 } 122 123 static irqreturn_t cxl_pci_mbox_irq(int irq, void *id) 124 { 125 u64 reg; 126 u16 opcode; 127 struct cxl_dev_id *dev_id = id; 128 struct cxl_dev_state *cxlds = dev_id->cxlds; 129 struct cxl_mailbox *cxl_mbox = &cxlds->cxl_mbox; 130 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 131 132 if (!cxl_mbox_background_complete(cxlds)) 133 return IRQ_NONE; 134 135 reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 136 opcode = FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_OPCODE_MASK, reg); 137 if (opcode == CXL_MBOX_OP_SANITIZE) { 138 mutex_lock(&cxl_mbox->mbox_mutex); 139 if (mds->security.sanitize_node) 140 mod_delayed_work(system_percpu_wq, &mds->security.poll_dwork, 0); 141 mutex_unlock(&cxl_mbox->mbox_mutex); 142 } else { 143 /* short-circuit the wait in __cxl_pci_mbox_send_cmd() */ 144 rcuwait_wake_up(&cxl_mbox->mbox_wait); 145 } 146 147 return IRQ_HANDLED; 148 } 149 150 /* 151 * Sanitization operation polling mode. 152 */ 153 static void cxl_mbox_sanitize_work(struct work_struct *work) 154 { 155 struct cxl_memdev_state *mds = 156 container_of(work, typeof(*mds), security.poll_dwork.work); 157 struct cxl_dev_state *cxlds = &mds->cxlds; 158 struct cxl_mailbox *cxl_mbox = &cxlds->cxl_mbox; 159 160 mutex_lock(&cxl_mbox->mbox_mutex); 161 if (cxl_mbox_background_complete(cxlds)) { 162 mds->security.poll_tmo_secs = 0; 163 if (mds->security.sanitize_node) 164 sysfs_notify_dirent(mds->security.sanitize_node); 165 mds->security.sanitize_active = false; 166 167 dev_dbg(cxlds->dev, "Sanitization operation ended\n"); 168 } else { 169 int timeout = mds->security.poll_tmo_secs + 10; 170 171 mds->security.poll_tmo_secs = min(15 * 60, timeout); 172 schedule_delayed_work(&mds->security.poll_dwork, timeout * HZ); 173 } 174 mutex_unlock(&cxl_mbox->mbox_mutex); 175 } 176 177 /** 178 * __cxl_pci_mbox_send_cmd() - Execute a mailbox command 179 * @cxl_mbox: CXL mailbox context 180 * @mbox_cmd: Command to send to the memory device. 181 * 182 * Context: Any context. Expects mbox_mutex to be held. 183 * Return: -ETIMEDOUT if timeout occurred waiting for completion. 0 on success. 184 * Caller should check the return code in @mbox_cmd to make sure it 185 * succeeded. 186 * 187 * This is a generic form of the CXL mailbox send command thus only using the 188 * registers defined by the mailbox capability ID - CXL 2.0 8.2.8.4. Memory 189 * devices, and perhaps other types of CXL devices may have further information 190 * available upon error conditions. Driver facilities wishing to send mailbox 191 * commands should use the wrapper command. 192 * 193 * The CXL spec allows for up to two mailboxes. The intention is for the primary 194 * mailbox to be OS controlled and the secondary mailbox to be used by system 195 * firmware. This allows the OS and firmware to communicate with the device and 196 * not need to coordinate with each other. The driver only uses the primary 197 * mailbox. 198 */ 199 static int __cxl_pci_mbox_send_cmd(struct cxl_mailbox *cxl_mbox, 200 struct cxl_mbox_cmd *mbox_cmd) 201 { 202 struct cxl_dev_state *cxlds = mbox_to_cxlds(cxl_mbox); 203 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 204 void __iomem *payload = cxlds->regs.mbox + CXLDEV_MBOX_PAYLOAD_OFFSET; 205 struct device *dev = cxlds->dev; 206 u64 cmd_reg, status_reg; 207 size_t out_len; 208 int rc; 209 210 lockdep_assert_held(&cxl_mbox->mbox_mutex); 211 212 /* 213 * Here are the steps from 8.2.8.4 of the CXL 2.0 spec. 214 * 1. Caller reads MB Control Register to verify doorbell is clear 215 * 2. Caller writes Command Register 216 * 3. Caller writes Command Payload Registers if input payload is non-empty 217 * 4. Caller writes MB Control Register to set doorbell 218 * 5. Caller either polls for doorbell to be clear or waits for interrupt if configured 219 * 6. Caller reads MB Status Register to fetch Return code 220 * 7. If command successful, Caller reads Command Register to get Payload Length 221 * 8. If output payload is non-empty, host reads Command Payload Registers 222 * 223 * Hardware is free to do whatever it wants before the doorbell is rung, 224 * and isn't allowed to change anything after it clears the doorbell. As 225 * such, steps 2 and 3 can happen in any order, and steps 6, 7, 8 can 226 * also happen in any order (though some orders might not make sense). 227 */ 228 229 /* #1 */ 230 if (cxl_doorbell_busy(cxlds)) { 231 u64 md_status = 232 readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 233 234 cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, 235 "mailbox queue busy"); 236 return -EBUSY; 237 } 238 239 /* 240 * With sanitize polling, hardware might be done and the poller still 241 * not be in sync. Ensure no new command comes in until so. Keep the 242 * hardware semantics and only allow device health status. 243 */ 244 if (mds->security.poll_tmo_secs > 0) { 245 if (mbox_cmd->opcode != CXL_MBOX_OP_GET_HEALTH_INFO) 246 return -EBUSY; 247 } 248 249 cmd_reg = FIELD_PREP(CXLDEV_MBOX_CMD_COMMAND_OPCODE_MASK, 250 mbox_cmd->opcode); 251 if (mbox_cmd->size_in) { 252 if (WARN_ON(!mbox_cmd->payload_in)) 253 return -EINVAL; 254 255 cmd_reg |= FIELD_PREP(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, 256 mbox_cmd->size_in); 257 memcpy_toio(payload, mbox_cmd->payload_in, mbox_cmd->size_in); 258 } 259 260 /* #2, #3 */ 261 writeq(cmd_reg, cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); 262 263 /* #4 */ 264 dev_dbg(dev, "Sending command: 0x%04x\n", mbox_cmd->opcode); 265 writel(CXLDEV_MBOX_CTRL_DOORBELL, 266 cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 267 268 /* #5 */ 269 rc = cxl_pci_mbox_wait_for_doorbell(cxlds); 270 if (rc == -ETIMEDOUT) { 271 u64 md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 272 273 cxl_cmd_err(cxlds->dev, mbox_cmd, md_status, "mailbox timeout"); 274 return rc; 275 } 276 277 /* #6 */ 278 status_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_STATUS_OFFSET); 279 mbox_cmd->return_code = 280 FIELD_GET(CXLDEV_MBOX_STATUS_RET_CODE_MASK, status_reg); 281 282 /* 283 * Handle the background command in a synchronous manner. 284 * 285 * All other mailbox commands will serialize/queue on the mbox_mutex, 286 * which we currently hold. Furthermore this also guarantees that 287 * cxl_mbox_background_complete() checks are safe amongst each other, 288 * in that no new bg operation can occur in between. 289 * 290 * Background operations are timesliced in accordance with the nature 291 * of the command. In the event of timeout, the mailbox state is 292 * indeterminate until the next successful command submission and the 293 * driver can get back in sync with the hardware state. 294 */ 295 if (mbox_cmd->return_code == CXL_MBOX_CMD_RC_BACKGROUND) { 296 u64 bg_status_reg; 297 int i, timeout; 298 299 /* 300 * Sanitization is a special case which monopolizes the device 301 * and cannot be timesliced. Handle asynchronously instead, 302 * and allow userspace to poll(2) for completion. 303 */ 304 if (mbox_cmd->opcode == CXL_MBOX_OP_SANITIZE) { 305 if (mds->security.sanitize_active) 306 return -EBUSY; 307 308 /* give first timeout a second */ 309 timeout = 1; 310 mds->security.poll_tmo_secs = timeout; 311 mds->security.sanitize_active = true; 312 schedule_delayed_work(&mds->security.poll_dwork, 313 timeout * HZ); 314 dev_dbg(dev, "Sanitization operation started\n"); 315 goto success; 316 } 317 318 dev_dbg(dev, "Mailbox background operation (0x%04x) started\n", 319 mbox_cmd->opcode); 320 321 timeout = mbox_cmd->poll_interval_ms; 322 for (i = 0; i < mbox_cmd->poll_count; i++) { 323 if (rcuwait_wait_event_timeout(&cxl_mbox->mbox_wait, 324 cxl_mbox_background_complete(cxlds), 325 TASK_UNINTERRUPTIBLE, 326 msecs_to_jiffies(timeout)) > 0) 327 break; 328 } 329 330 if (!cxl_mbox_background_complete(cxlds)) { 331 dev_err(dev, "timeout waiting for background (%d ms)\n", 332 timeout * mbox_cmd->poll_count); 333 return -ETIMEDOUT; 334 } 335 336 bg_status_reg = readq(cxlds->regs.mbox + 337 CXLDEV_MBOX_BG_CMD_STATUS_OFFSET); 338 mbox_cmd->return_code = 339 FIELD_GET(CXLDEV_MBOX_BG_CMD_COMMAND_RC_MASK, 340 bg_status_reg); 341 dev_dbg(dev, 342 "Mailbox background operation (0x%04x) completed\n", 343 mbox_cmd->opcode); 344 } 345 346 if (mbox_cmd->return_code != CXL_MBOX_CMD_RC_SUCCESS) { 347 dev_dbg(dev, "Mailbox operation had an error: %s\n", 348 cxl_mbox_cmd_rc2str(mbox_cmd)); 349 return 0; /* completed but caller must check return_code */ 350 } 351 352 success: 353 /* #7 */ 354 cmd_reg = readq(cxlds->regs.mbox + CXLDEV_MBOX_CMD_OFFSET); 355 out_len = FIELD_GET(CXLDEV_MBOX_CMD_PAYLOAD_LENGTH_MASK, cmd_reg); 356 357 /* #8 */ 358 if (out_len && mbox_cmd->payload_out) { 359 /* 360 * Sanitize the copy. If hardware misbehaves, out_len per the 361 * spec can actually be greater than the max allowed size (21 362 * bits available but spec defined 1M max). The caller also may 363 * have requested less data than the hardware supplied even 364 * within spec. 365 */ 366 size_t n; 367 368 n = min3(mbox_cmd->size_out, cxl_mbox->payload_size, out_len); 369 memcpy_fromio(mbox_cmd->payload_out, payload, n); 370 mbox_cmd->size_out = n; 371 } else { 372 mbox_cmd->size_out = 0; 373 } 374 375 return 0; 376 } 377 378 static int cxl_pci_mbox_send(struct cxl_mailbox *cxl_mbox, 379 struct cxl_mbox_cmd *cmd) 380 { 381 int rc; 382 383 mutex_lock(&cxl_mbox->mbox_mutex); 384 rc = __cxl_pci_mbox_send_cmd(cxl_mbox, cmd); 385 mutex_unlock(&cxl_mbox->mbox_mutex); 386 387 return rc; 388 } 389 390 static int cxl_pci_setup_mailbox(struct cxl_memdev_state *mds, bool irq_avail) 391 { 392 struct cxl_dev_state *cxlds = &mds->cxlds; 393 struct cxl_mailbox *cxl_mbox = &cxlds->cxl_mbox; 394 const int cap = readl(cxlds->regs.mbox + CXLDEV_MBOX_CAPS_OFFSET); 395 struct device *dev = cxlds->dev; 396 unsigned long timeout; 397 int irq, msgnum; 398 u64 md_status; 399 u32 ctrl; 400 401 timeout = jiffies + mbox_ready_timeout * HZ; 402 do { 403 md_status = readq(cxlds->regs.memdev + CXLMDEV_STATUS_OFFSET); 404 if (md_status & CXLMDEV_MBOX_IF_READY) 405 break; 406 if (msleep_interruptible(100)) 407 break; 408 } while (!time_after(jiffies, timeout)); 409 410 if (!(md_status & CXLMDEV_MBOX_IF_READY)) { 411 cxl_err(dev, md_status, "timeout awaiting mailbox ready"); 412 return -ETIMEDOUT; 413 } 414 415 /* 416 * A command may be in flight from a previous driver instance, 417 * think kexec, do one doorbell wait so that 418 * __cxl_pci_mbox_send_cmd() can assume that it is the only 419 * source for future doorbell busy events. 420 */ 421 if (cxl_pci_mbox_wait_for_doorbell(cxlds) != 0) { 422 cxl_err(dev, md_status, "timeout awaiting mailbox idle"); 423 return -ETIMEDOUT; 424 } 425 426 cxl_mbox->mbox_send = cxl_pci_mbox_send; 427 cxl_mbox->payload_size = 428 1 << FIELD_GET(CXLDEV_MBOX_CAP_PAYLOAD_SIZE_MASK, cap); 429 430 /* 431 * CXL 2.0 8.2.8.4.3 Mailbox Capabilities Register 432 * 433 * If the size is too small, mandatory commands will not work and so 434 * there's no point in going forward. If the size is too large, there's 435 * no harm is soft limiting it. 436 */ 437 cxl_mbox->payload_size = min_t(size_t, cxl_mbox->payload_size, SZ_1M); 438 if (cxl_mbox->payload_size < 256) { 439 dev_err(dev, "Mailbox is too small (%zub)", 440 cxl_mbox->payload_size); 441 return -ENXIO; 442 } 443 444 dev_dbg(dev, "Mailbox payload sized %zu", cxl_mbox->payload_size); 445 446 INIT_DELAYED_WORK(&mds->security.poll_dwork, cxl_mbox_sanitize_work); 447 448 /* background command interrupts are optional */ 449 if (!(cap & CXLDEV_MBOX_CAP_BG_CMD_IRQ) || !irq_avail) 450 return 0; 451 452 msgnum = FIELD_GET(CXLDEV_MBOX_CAP_IRQ_MSGNUM_MASK, cap); 453 irq = pci_irq_vector(to_pci_dev(cxlds->dev), msgnum); 454 if (irq < 0) 455 return 0; 456 457 if (cxl_request_irq(cxlds, irq, cxl_pci_mbox_irq)) 458 return 0; 459 460 dev_dbg(cxlds->dev, "Mailbox interrupts enabled\n"); 461 /* enable background command mbox irq support */ 462 ctrl = readl(cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 463 ctrl |= CXLDEV_MBOX_CTRL_BG_CMD_IRQ; 464 writel(ctrl, cxlds->regs.mbox + CXLDEV_MBOX_CTRL_OFFSET); 465 466 return 0; 467 } 468 469 static void free_event_buf(void *buf) 470 { 471 kvfree(buf); 472 } 473 474 /* 475 * There is a single buffer for reading event logs from the mailbox. All logs 476 * share this buffer protected by the mds->event_log_lock. 477 */ 478 static int cxl_mem_alloc_event_buf(struct cxl_memdev_state *mds) 479 { 480 struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox; 481 struct cxl_get_event_payload *buf; 482 483 buf = kvmalloc(cxl_mbox->payload_size, GFP_KERNEL); 484 if (!buf) 485 return -ENOMEM; 486 mds->event.buf = buf; 487 488 return devm_add_action_or_reset(mds->cxlds.dev, free_event_buf, buf); 489 } 490 491 static bool cxl_alloc_irq_vectors(struct pci_dev *pdev) 492 { 493 int nvecs; 494 495 /* 496 * Per CXL 3.0 3.1.1 CXL.io Endpoint a function on a CXL device must 497 * not generate INTx messages if that function participates in 498 * CXL.cache or CXL.mem. 499 * 500 * Additionally pci_alloc_irq_vectors() handles calling 501 * pci_free_irq_vectors() automatically despite not being called 502 * pcim_*. See pci_setup_msi_context(). 503 */ 504 nvecs = pci_alloc_irq_vectors(pdev, 1, CXL_PCI_DEFAULT_MAX_VECTORS, 505 PCI_IRQ_MSIX | PCI_IRQ_MSI); 506 if (nvecs < 1) { 507 dev_dbg(&pdev->dev, "Failed to alloc irq vectors: %d\n", nvecs); 508 return false; 509 } 510 return true; 511 } 512 513 /* Event logs the driver drains: standard logs when native_cxl */ 514 static u32 cxl_event_drain_mask(struct pci_host_bridge *host_bridge) 515 { 516 if (host_bridge->native_cxl_error) 517 return CXLDEV_EVENT_STATUS_STANDARD_LOGS; 518 return 0; 519 } 520 521 static irqreturn_t cxl_event_thread(int irq, void *id) 522 { 523 struct cxl_dev_id *dev_id = id; 524 struct cxl_dev_state *cxlds = dev_id->cxlds; 525 struct cxl_memdev_state *mds = to_cxl_memdev_state(cxlds); 526 struct pci_host_bridge *host_bridge = 527 pci_find_host_bridge(to_pci_dev(cxlds->dev)->bus); 528 u32 mask = cxl_event_drain_mask(host_bridge); 529 bool handled = false; 530 u32 status; 531 532 do { 533 /* 534 * CXL 3.0 8.2.8.3.1: The lower 32 bits are the status; 535 * ignore the reserved upper 32 bits 536 */ 537 status = readl(cxlds->regs.status + CXLDEV_DEV_EVENT_STATUS_OFFSET); 538 /* Ignore logs unknown to the driver or owned by BIOS */ 539 status &= mask; 540 if (!status) 541 break; 542 543 handled = true; 544 cxl_mem_get_event_records(mds, status); 545 cond_resched(); 546 } while (status); 547 548 return handled ? IRQ_HANDLED : IRQ_NONE; 549 } 550 551 static int cxl_event_req_irq(struct cxl_dev_state *cxlds, u8 setting) 552 { 553 struct pci_dev *pdev = to_pci_dev(cxlds->dev); 554 int irq; 555 556 if (FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting) != CXL_INT_MSI_MSIX) 557 return -ENXIO; 558 559 irq = pci_irq_vector(pdev, 560 FIELD_GET(CXLDEV_EVENT_INT_MSGNUM_MASK, setting)); 561 if (irq < 0) 562 return irq; 563 564 return cxl_request_irq(cxlds, irq, cxl_event_thread); 565 } 566 567 static int cxl_event_get_int_policy(struct cxl_memdev_state *mds, 568 struct cxl_event_interrupt_policy *policy, 569 size_t *policy_size) 570 { 571 struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox; 572 struct cxl_mbox_cmd mbox_cmd = { 573 .opcode = CXL_MBOX_OP_GET_EVT_INT_POLICY, 574 .payload_out = policy, 575 .size_out = sizeof(*policy), 576 /* CXL 2.0 firmware omits dcd_settings; accept the shorter reply */ 577 .min_out = CXL_EVENT_INT_POLICY_BASE_SIZE, 578 }; 579 int rc; 580 581 rc = cxl_internal_send_cmd(cxl_mbox, &mbox_cmd); 582 if (rc < 0) { 583 dev_err(mds->cxlds.dev, 584 "Failed to get event interrupt policy : %d", rc); 585 return rc; 586 } 587 588 if (policy_size) 589 *policy_size = mbox_cmd.size_out; 590 return rc; 591 } 592 593 static int cxl_event_set_int_policy(struct cxl_memdev_state *mds, 594 struct cxl_event_interrupt_policy *policy, 595 size_t policy_size) 596 { 597 struct cxl_mailbox *cxl_mbox = &mds->cxlds.cxl_mbox; 598 struct cxl_mbox_cmd mbox_cmd = { 599 .opcode = CXL_MBOX_OP_SET_EVT_INT_POLICY, 600 .payload_in = policy, 601 .size_in = policy_size, 602 }; 603 int rc; 604 605 rc = cxl_internal_send_cmd(cxl_mbox, &mbox_cmd); 606 if (rc < 0) 607 dev_err(mds->cxlds.dev, "Failed to set event interrupt policy : %d", 608 rc); 609 return rc; 610 } 611 612 static int cxl_event_config_msgnums(struct cxl_memdev_state *mds, 613 struct cxl_event_interrupt_policy *policy, 614 bool native_cxl, size_t policy_size) 615 { 616 int rc; 617 618 /* memory event policy is left if FW has control */ 619 if (native_cxl) { 620 *policy = (struct cxl_event_interrupt_policy) { 621 .info_settings = CXL_INT_MSI_MSIX, 622 .warn_settings = CXL_INT_MSI_MSIX, 623 .failure_settings = CXL_INT_MSI_MSIX, 624 .fatal_settings = CXL_INT_MSI_MSIX, 625 .dcd_settings = 0, 626 }; 627 } 628 629 /* 630 * A CXL 3.0+ device can carry dcd_settings field without DCD command 631 * support, so size the request by the device's policy_size and only 632 * enable the DCD interrupt when DCD commands are supported. 633 */ 634 if (cxl_dcd_supported(mds)) 635 policy->dcd_settings = CXL_INT_MSI_MSIX; 636 637 rc = cxl_event_set_int_policy(mds, policy, policy_size); 638 if (rc) 639 return rc; 640 641 /* Retrieve final interrupt settings */ 642 return cxl_event_get_int_policy(mds, policy, NULL); 643 } 644 645 static int cxl_event_irqsetup(struct cxl_memdev_state *mds, 646 struct cxl_event_interrupt_policy *policy) 647 { 648 struct cxl_dev_state *cxlds = &mds->cxlds; 649 int rc; 650 651 rc = cxl_event_req_irq(cxlds, policy->info_settings); 652 if (rc) { 653 dev_err(cxlds->dev, "Failed to get interrupt for event Info log\n"); 654 return rc; 655 } 656 657 rc = cxl_event_req_irq(cxlds, policy->warn_settings); 658 if (rc) { 659 dev_err(cxlds->dev, "Failed to get interrupt for event Warn log\n"); 660 return rc; 661 } 662 663 rc = cxl_event_req_irq(cxlds, policy->failure_settings); 664 if (rc) { 665 dev_err(cxlds->dev, "Failed to get interrupt for event Failure log\n"); 666 return rc; 667 } 668 669 rc = cxl_event_req_irq(cxlds, policy->fatal_settings); 670 if (rc) { 671 dev_err(cxlds->dev, "Failed to get interrupt for event Fatal log\n"); 672 return rc; 673 } 674 675 return 0; 676 } 677 678 static int cxl_irqsetup(struct cxl_memdev_state *mds, 679 struct cxl_event_interrupt_policy *policy, 680 bool native_cxl, size_t policy_size) 681 { 682 struct cxl_dev_state *cxlds = &mds->cxlds; 683 int rc; 684 685 if (native_cxl) { 686 rc = cxl_event_irqsetup(mds, policy); 687 if (rc) 688 return rc; 689 } 690 691 if (cxl_dcd_supported(mds)) { 692 rc = cxl_event_req_irq(cxlds, policy->dcd_settings); 693 if (rc) { 694 dev_err(cxlds->dev, "Failed to get interrupt for DCD event log\n"); 695 cxl_disable_dcd(mds); 696 /* No handler will service the DCD vector; tell the device */ 697 policy->dcd_settings = CXL_INT_NONE; 698 rc = cxl_event_set_int_policy(mds, policy, policy_size); 699 if (rc) 700 dev_warn(cxlds->dev, 701 "DCD disabled but its interrupt policy could not be cleared: %d\n", 702 rc); 703 } 704 } 705 706 return 0; 707 } 708 709 static bool cxl_event_int_is_fw(u8 setting) 710 { 711 u8 mode = FIELD_GET(CXLDEV_EVENT_INT_MODE_MASK, setting); 712 713 return mode == CXL_INT_FW; 714 } 715 716 static bool cxl_event_fw_owns_mem_logs(struct cxl_event_interrupt_policy *policy) 717 { 718 return cxl_event_int_is_fw(policy->info_settings) || 719 cxl_event_int_is_fw(policy->warn_settings) || 720 cxl_event_int_is_fw(policy->failure_settings) || 721 cxl_event_int_is_fw(policy->fatal_settings); 722 } 723 724 static int cxl_event_config(struct pci_host_bridge *host_bridge, 725 struct cxl_memdev_state *mds, bool irq_avail) 726 { 727 struct cxl_event_interrupt_policy policy = { 0 }; 728 bool native_cxl = host_bridge->native_cxl_error; 729 size_t policy_size; 730 u32 mask; 731 int rc; 732 733 /* 734 * When BIOS maintains CXL error reporting control, it will process 735 * event records. Only one agent can do so. 736 * 737 * If BIOS has control of events and DCD is not supported skip event 738 * configuration. 739 */ 740 if (!native_cxl && !cxl_dcd_supported(mds)) 741 return 0; 742 743 if (!irq_avail) { 744 dev_info(mds->cxlds.dev, "No interrupt support, disable event processing.\n"); 745 if (cxl_dcd_supported(mds)) { 746 dev_info(mds->cxlds.dev, "DCD requires interrupts, disable DCD\n"); 747 cxl_disable_dcd(mds); 748 } 749 return 0; 750 } 751 752 rc = cxl_event_get_int_policy(mds, &policy, &policy_size); 753 if (rc) 754 goto err; 755 756 /* 757 * dcd_settings cannot be sent to a device whose policy is too short 758 * to hold it, so the device would never accept the setting 759 * cxl_irqsetup() arms the DCD interrupt with. 760 */ 761 if (cxl_dcd_supported(mds) && policy_size < sizeof(policy)) { 762 dev_warn(mds->cxlds.dev, 763 "DCD supported but interrupt policy is only %zu bytes\n", 764 policy_size); 765 cxl_disable_dcd(mds); 766 /* DCD was the only reason to be here */ 767 if (!native_cxl) 768 return 0; 769 } 770 771 if (native_cxl && cxl_event_fw_owns_mem_logs(&policy)) { 772 dev_err(mds->cxlds.dev, 773 "FW still in control of Event Logs despite _OSC settings\n"); 774 return -EBUSY; 775 } 776 777 rc = cxl_event_config_msgnums(mds, &policy, native_cxl, policy_size); 778 if (rc) 779 goto err; 780 781 rc = cxl_mem_alloc_event_buf(mds); 782 if (rc) 783 return rc; 784 785 rc = cxl_irqsetup(mds, &policy, native_cxl, policy_size); 786 if (rc) 787 return rc; 788 789 mask = cxl_event_drain_mask(host_bridge); 790 if (mask) 791 cxl_mem_get_event_records(mds, mask); 792 793 dev_dbg(mds->cxlds.dev, "Event config : %s DCD %s\n", 794 native_cxl ? "OS" : "BIOS", 795 cxl_dcd_supported(mds) ? "supported" : "not supported"); 796 797 return 0; 798 799 err: 800 /* 801 * Failed to Get/Set interrupt policy for DCD while BIOS owns the 802 * other logs. Disable DCD and continue. 803 */ 804 if (!native_cxl) { 805 dev_warn(mds->cxlds.dev, 806 "Event interrupt policy failed (%d), disabling DCD\n", rc); 807 cxl_disable_dcd(mds); 808 return 0; 809 } 810 return rc; 811 } 812 813 static int cxl_pci_type3_init_mailbox(struct cxl_dev_state *cxlds) 814 { 815 int rc; 816 817 rc = cxl_mailbox_init(&cxlds->cxl_mbox, cxlds->dev); 818 if (rc) 819 return rc; 820 821 return 0; 822 } 823 824 static ssize_t rcd_pcie_cap_emit(struct device *dev, u16 offset, char *buf, size_t width) 825 { 826 struct cxl_dev_state *cxlds = dev_get_drvdata(dev); 827 struct cxl_memdev *cxlmd = cxlds->cxlmd; 828 struct device *root_dev; 829 struct cxl_dport *dport; 830 struct cxl_port *root __free(put_cxl_port) = 831 cxl_mem_find_port(cxlmd); 832 833 if (!root) 834 return -ENXIO; 835 836 root_dev = cxl_port_dport_host(root); 837 if (!root_dev) 838 return -ENXIO; 839 840 guard(device)(root_dev); 841 if (!root_dev->driver) 842 return -ENXIO; 843 844 dport = cxl_mem_find_dport(cxlmd, root); 845 if (!dport || !dport->regs.rcd_pcie_cap) 846 return -ENXIO; 847 848 switch (width) { 849 case 2: 850 return sysfs_emit(buf, "%#x\n", 851 readw(dport->regs.rcd_pcie_cap + offset)); 852 case 4: 853 return sysfs_emit(buf, "%#x\n", 854 readl(dport->regs.rcd_pcie_cap + offset)); 855 default: 856 return -EINVAL; 857 } 858 } 859 860 static ssize_t rcd_link_cap_show(struct device *dev, 861 struct device_attribute *attr, char *buf) 862 { 863 return rcd_pcie_cap_emit(dev, PCI_EXP_LNKCAP, buf, sizeof(u32)); 864 } 865 static DEVICE_ATTR_RO(rcd_link_cap); 866 867 static ssize_t rcd_link_ctrl_show(struct device *dev, 868 struct device_attribute *attr, char *buf) 869 { 870 return rcd_pcie_cap_emit(dev, PCI_EXP_LNKCTL, buf, sizeof(u16)); 871 } 872 static DEVICE_ATTR_RO(rcd_link_ctrl); 873 874 static ssize_t rcd_link_status_show(struct device *dev, 875 struct device_attribute *attr, char *buf) 876 { 877 return rcd_pcie_cap_emit(dev, PCI_EXP_LNKSTA, buf, sizeof(u16)); 878 } 879 static DEVICE_ATTR_RO(rcd_link_status); 880 881 static struct attribute *cxl_rcd_attrs[] = { 882 &dev_attr_rcd_link_cap.attr, 883 &dev_attr_rcd_link_ctrl.attr, 884 &dev_attr_rcd_link_status.attr, 885 NULL 886 }; 887 888 static umode_t cxl_rcd_visible(struct kobject *kobj, struct attribute *a, int n) 889 { 890 struct device *dev = kobj_to_dev(kobj); 891 struct pci_dev *pdev = to_pci_dev(dev); 892 893 if (is_cxl_restricted(pdev)) 894 return a->mode; 895 896 return 0; 897 } 898 899 static struct attribute_group cxl_rcd_group = { 900 .attrs = cxl_rcd_attrs, 901 .is_visible = cxl_rcd_visible, 902 }; 903 __ATTRIBUTE_GROUPS(cxl_rcd); 904 905 static int cxl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *id) 906 { 907 struct pci_host_bridge *host_bridge = pci_find_host_bridge(pdev->bus); 908 struct cxl_dpa_info range_info = { 0 }; 909 struct cxl_memdev_state *mds; 910 struct cxl_dev_state *cxlds; 911 struct cxl_register_map map; 912 struct cxl_memdev *cxlmd; 913 int rc, pmu_count; 914 unsigned int i; 915 bool irq_avail; 916 u16 dvsec; 917 918 rc = pcim_enable_device(pdev); 919 if (rc) 920 return rc; 921 pci_set_master(pdev); 922 923 dvsec = pci_find_dvsec_capability(pdev, PCI_VENDOR_ID_CXL, 924 PCI_DVSEC_CXL_DEVICE); 925 if (!dvsec) 926 pci_warn(pdev, "Device DVSEC not present, skip CXL.mem init\n"); 927 928 mds = cxl_memdev_state_create(&pdev->dev, pci_get_dsn(pdev), dvsec); 929 if (IS_ERR(mds)) 930 return PTR_ERR(mds); 931 cxlds = &mds->cxlds; 932 pci_set_drvdata(pdev, cxlds); 933 934 cxlds->rcd = is_cxl_restricted(pdev); 935 936 rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_MEMDEV, &map); 937 if (rc) 938 return rc; 939 940 rc = cxl_map_device_regs(&map, &cxlds->regs); 941 if (rc) 942 return rc; 943 944 /* 945 * If the component registers can't be found, the cxl_pci driver may 946 * still be useful for management functions so don't return an error. 947 */ 948 rc = cxl_pci_setup_regs(pdev, CXL_REGLOC_RBI_COMPONENT, 949 &cxlds->reg_map); 950 if (rc) { 951 if (rc == -EPROBE_DEFER) 952 return rc; 953 dev_warn(&pdev->dev, "No component registers (%d)\n", rc); 954 } else if (!cxlds->reg_map.component_map.ras.valid) { 955 dev_dbg(&pdev->dev, "RAS registers not found\n"); 956 } 957 958 rc = cxl_pci_type3_init_mailbox(cxlds); 959 if (rc) 960 return rc; 961 962 rc = cxl_await_media_ready(cxlds); 963 if (rc == 0) 964 cxlds->media_ready = true; 965 else 966 dev_warn(&pdev->dev, "Media not active (%d)\n", rc); 967 968 irq_avail = cxl_alloc_irq_vectors(pdev); 969 970 rc = cxl_pci_setup_mailbox(mds, irq_avail); 971 if (rc) 972 return rc; 973 974 rc = cxl_enumerate_cmds(mds); 975 if (rc) 976 return rc; 977 978 rc = cxl_set_timestamp(mds); 979 if (rc) 980 return rc; 981 982 rc = cxl_poison_state_init(mds); 983 if (rc) 984 return rc; 985 986 rc = cxl_dev_state_identify(mds); 987 if (rc) 988 return rc; 989 990 rc = cxl_mem_dpa_fetch(mds, &range_info); 991 if (rc) 992 return rc; 993 994 if (cxl_dcd_supported(mds)) { 995 rc = cxl_configure_dcd(mds, &range_info); 996 if (rc) 997 cxl_disable_dcd(mds); 998 } 999 1000 rc = cxl_dpa_setup(cxlds, &range_info); 1001 if (rc) 1002 return rc; 1003 1004 rc = devm_cxl_setup_features(cxlds); 1005 if (rc) 1006 dev_dbg(&pdev->dev, "No CXL Features discovered\n"); 1007 1008 cxlmd = devm_cxl_add_classdev(cxlds); 1009 if (IS_ERR(cxlmd)) 1010 return PTR_ERR(cxlmd); 1011 1012 rc = devm_cxl_setup_fw_upload(&pdev->dev, mds); 1013 if (rc) 1014 return rc; 1015 1016 rc = devm_cxl_sanitize_setup_notifier(&pdev->dev, cxlmd); 1017 if (rc) 1018 return rc; 1019 1020 rc = devm_cxl_setup_fwctl(&pdev->dev, cxlmd); 1021 if (rc) 1022 dev_dbg(&pdev->dev, "No CXL FWCTL setup\n"); 1023 1024 rc = cxl_event_config(host_bridge, mds, irq_avail); 1025 if (rc) 1026 return rc; 1027 1028 pmu_count = cxl_count_regblock(pdev, CXL_REGLOC_RBI_PMU); 1029 if (pmu_count < 0) 1030 return pmu_count; 1031 1032 for (i = 0; i < pmu_count; i++) { 1033 struct cxl_pmu_regs pmu_regs; 1034 1035 rc = cxl_find_regblock_instance(pdev, CXL_REGLOC_RBI_PMU, &map, i); 1036 if (rc) { 1037 dev_dbg(&pdev->dev, "Could not find PMU regblock\n"); 1038 break; 1039 } 1040 1041 rc = cxl_map_pmu_regs(&map, &pmu_regs); 1042 if (rc) { 1043 dev_dbg(&pdev->dev, "Could not map PMU regs\n"); 1044 break; 1045 } 1046 1047 rc = devm_cxl_pmu_add(cxlds->dev, &pmu_regs, cxlmd->id, i, CXL_PMU_MEMDEV); 1048 if (rc) { 1049 dev_dbg(&pdev->dev, "Could not add PMU instance\n"); 1050 break; 1051 } 1052 } 1053 1054 pci_save_state(pdev); 1055 1056 /* A missing PMU is not fatal, the memdev is still usable */ 1057 return 0; 1058 } 1059 1060 static const struct pci_device_id cxl_mem_pci_tbl[] = { 1061 /* PCI class code for CXL.mem Type-3 Devices */ 1062 { PCI_DEVICE_CLASS((PCI_CLASS_MEMORY_CXL << 8 | CXL_MEMORY_PROGIF), ~0)}, 1063 { /* terminate list */ }, 1064 }; 1065 MODULE_DEVICE_TABLE(pci, cxl_mem_pci_tbl); 1066 1067 static pci_ers_result_t cxl_slot_reset(struct pci_dev *pdev) 1068 { 1069 struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 1070 struct cxl_memdev *cxlmd = cxlds->cxlmd; 1071 struct device *dev = &cxlmd->dev; 1072 1073 dev_info(&pdev->dev, "%s: restart CXL.mem after slot reset\n", 1074 dev_name(dev)); 1075 pci_restore_state(pdev); 1076 if (device_attach(dev) <= 0) 1077 return PCI_ERS_RESULT_DISCONNECT; 1078 return PCI_ERS_RESULT_RECOVERED; 1079 } 1080 1081 static void cxl_error_resume(struct pci_dev *pdev) 1082 { 1083 struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 1084 struct cxl_memdev *cxlmd = cxlds->cxlmd; 1085 struct device *dev = &cxlmd->dev; 1086 1087 dev_info(&pdev->dev, "%s: error resume %s\n", dev_name(dev), 1088 dev->driver ? "successful" : "failed"); 1089 } 1090 1091 static int cxl_endpoint_decoder_clear_reset_flags(struct device *dev, void *data) 1092 { 1093 struct cxl_endpoint_decoder *cxled; 1094 1095 if (!is_endpoint_decoder(dev)) 1096 return 0; 1097 1098 cxled = to_cxl_endpoint_decoder(dev); 1099 cxled->cxld.flags &= ~CXL_DECODER_F_RESET_MASK; 1100 1101 return 0; 1102 } 1103 1104 static void cxl_reset_done(struct pci_dev *pdev) 1105 { 1106 struct cxl_dev_state *cxlds = pci_get_drvdata(pdev); 1107 struct cxl_memdev *cxlmd = cxlds->cxlmd; 1108 struct device *dev = &pdev->dev; 1109 1110 /* 1111 * FLR does not expect to touch the HDM decoders and related 1112 * registers. SBR, however, will wipe all device configurations. 1113 * Issue a warning if there was an active decoder before the reset 1114 * that no longer exists. 1115 */ 1116 guard(device)(&cxlmd->dev); 1117 if (!cxlmd->dev.driver) 1118 return; 1119 1120 if (cxlmd->endpoint && 1121 cxl_endpoint_decoder_reset_detected(cxlmd->endpoint)) { 1122 device_for_each_child(&cxlmd->endpoint->dev, NULL, 1123 cxl_endpoint_decoder_clear_reset_flags); 1124 1125 dev_crit(dev, "SBR happened without memory regions removal.\n"); 1126 dev_crit(dev, "System may be unstable if regions hosted system memory.\n"); 1127 add_taint(TAINT_USER, LOCKDEP_STILL_OK); 1128 } 1129 } 1130 1131 static const struct pci_error_handlers cxl_error_handlers = { 1132 .error_detected = cxl_error_detected, 1133 .slot_reset = cxl_slot_reset, 1134 .resume = cxl_error_resume, 1135 .cor_error_detected = cxl_cor_error_detected, 1136 .reset_done = cxl_reset_done, 1137 }; 1138 1139 static struct pci_driver cxl_pci_driver = { 1140 .name = KBUILD_MODNAME, 1141 .id_table = cxl_mem_pci_tbl, 1142 .probe = cxl_pci_probe, 1143 .err_handler = &cxl_error_handlers, 1144 .dev_groups = cxl_rcd_groups, 1145 .driver = { 1146 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1147 }, 1148 }; 1149 1150 #define CXL_EVENT_HDR_FLAGS_REC_SEVERITY GENMASK(1, 0) 1151 static void cxl_handle_cper_event(enum cxl_event_type ev_type, 1152 struct cxl_cper_event_rec *rec) 1153 { 1154 struct cper_cxl_event_devid *device_id = &rec->hdr.device_id; 1155 struct pci_dev *pdev __free(pci_dev_put) = NULL; 1156 enum cxl_event_log_type log_type; 1157 struct cxl_dev_state *cxlds; 1158 unsigned int devfn; 1159 u32 hdr_flags; 1160 1161 pr_debug("CPER event %d for device %u:%u:%u.%u\n", ev_type, 1162 device_id->segment_num, device_id->bus_num, 1163 device_id->device_num, device_id->func_num); 1164 1165 devfn = PCI_DEVFN(device_id->device_num, device_id->func_num); 1166 pdev = pci_get_domain_bus_and_slot(device_id->segment_num, 1167 device_id->bus_num, devfn); 1168 if (!pdev) 1169 return; 1170 1171 guard(device)(&pdev->dev); 1172 if (pdev->driver != &cxl_pci_driver) 1173 return; 1174 1175 cxlds = pci_get_drvdata(pdev); 1176 if (!cxlds) 1177 return; 1178 1179 /* Fabricate a log type */ 1180 hdr_flags = get_unaligned_le24(rec->event.generic.hdr.flags); 1181 log_type = FIELD_GET(CXL_EVENT_HDR_FLAGS_REC_SEVERITY, hdr_flags); 1182 1183 cxl_event_trace_record(cxlds->cxlmd, log_type, ev_type, 1184 &uuid_null, &rec->event); 1185 } 1186 1187 static void cxl_cper_work_fn(struct work_struct *work) 1188 { 1189 struct cxl_cper_work_data wd; 1190 1191 while (cxl_cper_kfifo_get(&wd)) 1192 cxl_handle_cper_event(wd.event_type, &wd.rec); 1193 } 1194 static DECLARE_WORK(cxl_cper_work, cxl_cper_work_fn); 1195 1196 static int __init cxl_pci_driver_init(void) 1197 { 1198 int rc; 1199 1200 rc = pci_register_driver(&cxl_pci_driver); 1201 if (rc) 1202 return rc; 1203 1204 rc = cxl_cper_register_work(&cxl_cper_work); 1205 if (rc) 1206 pci_unregister_driver(&cxl_pci_driver); 1207 1208 return rc; 1209 } 1210 1211 static void __exit cxl_pci_driver_exit(void) 1212 { 1213 cxl_cper_unregister_work(&cxl_cper_work); 1214 pci_unregister_driver(&cxl_pci_driver); 1215 } 1216 1217 module_init(cxl_pci_driver_init); 1218 module_exit(cxl_pci_driver_exit); 1219 MODULE_DESCRIPTION("CXL: PCI manageability"); 1220 MODULE_LICENSE("GPL v2"); 1221 MODULE_IMPORT_NS("CXL"); 1222