1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * R-Car MIPI DSI Encoder
4 *
5 * Copyright (C) 2020 Renesas Electronics Corporation
6 */
7
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/io.h>
12 #include <linux/iopoll.h>
13 #include <linux/math64.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_graph.h>
17 #include <linux/platform_device.h>
18 #include <linux/reset.h>
19 #include <linux/slab.h>
20
21 #include <drm/drm_atomic.h>
22 #include <drm/drm_atomic_helper.h>
23 #include <drm/drm_bridge.h>
24 #include <drm/drm_mipi_dsi.h>
25 #include <drm/drm_of.h>
26 #include <drm/drm_panel.h>
27 #include <drm/drm_probe_helper.h>
28
29 #include "rcar_mipi_dsi.h"
30 #include "rcar_mipi_dsi_regs.h"
31
32 #define MHZ(v) ((u32)((v) * 1000000U))
33
34 enum rcar_mipi_dsi_hw_model {
35 RCAR_DSI_V3U,
36 RCAR_DSI_V4H,
37 };
38
39 struct rcar_mipi_dsi_device_info {
40 enum rcar_mipi_dsi_hw_model model;
41
42 const struct dsi_clk_config *clk_cfg;
43
44 u8 clockset2_m_offset;
45
46 u8 n_min;
47 u8 n_max;
48 u8 n_mul;
49 unsigned long fpfd_min;
50 unsigned long fpfd_max;
51 u16 m_min;
52 u16 m_max;
53 unsigned long fout_min;
54 unsigned long fout_max;
55 };
56
57 struct rcar_mipi_dsi {
58 struct device *dev;
59 const struct rcar_mipi_dsi_device_info *info;
60 struct reset_control *rstc;
61
62 struct mipi_dsi_host host;
63 struct drm_bridge bridge;
64 struct drm_bridge *next_bridge;
65 struct drm_connector connector;
66
67 void __iomem *mmio;
68 struct {
69 struct clk *mod;
70 struct clk *pll;
71 struct clk *dsi;
72 } clocks;
73
74 enum mipi_dsi_pixel_format format;
75 unsigned long mode_flags;
76 unsigned int num_data_lanes;
77 unsigned int lanes;
78 };
79
80 struct dsi_setup_info {
81 unsigned long hsfreq;
82 u16 hsfreqrange;
83
84 unsigned long fout;
85 u16 m;
86 u16 n;
87 u16 vclk_divider;
88 const struct dsi_clk_config *clkset;
89 };
90
91 static inline struct rcar_mipi_dsi *
bridge_to_rcar_mipi_dsi(struct drm_bridge * bridge)92 bridge_to_rcar_mipi_dsi(struct drm_bridge *bridge)
93 {
94 return container_of(bridge, struct rcar_mipi_dsi, bridge);
95 }
96
97 static inline struct rcar_mipi_dsi *
host_to_rcar_mipi_dsi(struct mipi_dsi_host * host)98 host_to_rcar_mipi_dsi(struct mipi_dsi_host *host)
99 {
100 return container_of(host, struct rcar_mipi_dsi, host);
101 }
102
103 static const u32 hsfreqrange_table[][2] = {
104 { MHZ(80), 0x00 }, { MHZ(90), 0x10 }, { MHZ(100), 0x20 },
105 { MHZ(110), 0x30 }, { MHZ(120), 0x01 }, { MHZ(130), 0x11 },
106 { MHZ(140), 0x21 }, { MHZ(150), 0x31 }, { MHZ(160), 0x02 },
107 { MHZ(170), 0x12 }, { MHZ(180), 0x22 }, { MHZ(190), 0x32 },
108 { MHZ(205), 0x03 }, { MHZ(220), 0x13 }, { MHZ(235), 0x23 },
109 { MHZ(250), 0x33 }, { MHZ(275), 0x04 }, { MHZ(300), 0x14 },
110 { MHZ(325), 0x25 }, { MHZ(350), 0x35 }, { MHZ(400), 0x05 },
111 { MHZ(450), 0x16 }, { MHZ(500), 0x26 }, { MHZ(550), 0x37 },
112 { MHZ(600), 0x07 }, { MHZ(650), 0x18 }, { MHZ(700), 0x28 },
113 { MHZ(750), 0x39 }, { MHZ(800), 0x09 }, { MHZ(850), 0x19 },
114 { MHZ(900), 0x29 }, { MHZ(950), 0x3a }, { MHZ(1000), 0x0a },
115 { MHZ(1050), 0x1a }, { MHZ(1100), 0x2a }, { MHZ(1150), 0x3b },
116 { MHZ(1200), 0x0b }, { MHZ(1250), 0x1b }, { MHZ(1300), 0x2b },
117 { MHZ(1350), 0x3c }, { MHZ(1400), 0x0c }, { MHZ(1450), 0x1c },
118 { MHZ(1500), 0x2c }, { MHZ(1550), 0x3d }, { MHZ(1600), 0x0d },
119 { MHZ(1650), 0x1d }, { MHZ(1700), 0x2e }, { MHZ(1750), 0x3e },
120 { MHZ(1800), 0x0e }, { MHZ(1850), 0x1e }, { MHZ(1900), 0x2f },
121 { MHZ(1950), 0x3f }, { MHZ(2000), 0x0f }, { MHZ(2050), 0x40 },
122 { MHZ(2100), 0x41 }, { MHZ(2150), 0x42 }, { MHZ(2200), 0x43 },
123 { MHZ(2250), 0x44 }, { MHZ(2300), 0x45 }, { MHZ(2350), 0x46 },
124 { MHZ(2400), 0x47 }, { MHZ(2450), 0x48 }, { MHZ(2500), 0x49 },
125 { /* sentinel */ },
126 };
127
128 struct dsi_clk_config {
129 u32 min_freq;
130 u32 max_freq;
131 u8 vco_cntrl;
132 u8 cpbias_cntrl;
133 u8 gmp_cntrl;
134 u8 int_cntrl;
135 u8 prop_cntrl;
136 };
137
138 static const struct dsi_clk_config dsi_clk_cfg_v3u[] = {
139 { MHZ(40), MHZ(55), 0x3f, 0x10, 0x01, 0x00, 0x0b },
140 { MHZ(52.5), MHZ(80), 0x39, 0x10, 0x01, 0x00, 0x0b },
141 { MHZ(80), MHZ(110), 0x2f, 0x10, 0x01, 0x00, 0x0b },
142 { MHZ(105), MHZ(160), 0x29, 0x10, 0x01, 0x00, 0x0b },
143 { MHZ(160), MHZ(220), 0x1f, 0x10, 0x01, 0x00, 0x0b },
144 { MHZ(210), MHZ(320), 0x19, 0x10, 0x01, 0x00, 0x0b },
145 { MHZ(320), MHZ(440), 0x0f, 0x10, 0x01, 0x00, 0x0b },
146 { MHZ(420), MHZ(660), 0x09, 0x10, 0x01, 0x00, 0x0b },
147 { MHZ(630), MHZ(1149), 0x03, 0x10, 0x01, 0x00, 0x0b },
148 { MHZ(1100), MHZ(1152), 0x01, 0x10, 0x01, 0x00, 0x0b },
149 { MHZ(1150), MHZ(1250), 0x01, 0x10, 0x01, 0x00, 0x0c },
150 { /* sentinel */ },
151 };
152
153 static const struct dsi_clk_config dsi_clk_cfg_v4h[] = {
154 { MHZ(40), MHZ(45.31), 0x2b, 0x00, 0x00, 0x08, 0x0a },
155 { MHZ(45.31), MHZ(54.66), 0x28, 0x00, 0x00, 0x08, 0x0a },
156 { MHZ(54.66), MHZ(62.5), 0x28, 0x00, 0x00, 0x08, 0x0a },
157 { MHZ(62.5), MHZ(75), 0x27, 0x00, 0x00, 0x08, 0x0a },
158 { MHZ(75), MHZ(90.63), 0x23, 0x00, 0x00, 0x08, 0x0a },
159 { MHZ(90.63), MHZ(109.37), 0x20, 0x00, 0x00, 0x08, 0x0a },
160 { MHZ(109.37), MHZ(125), 0x20, 0x00, 0x00, 0x08, 0x0a },
161 { MHZ(125), MHZ(150), 0x1f, 0x00, 0x00, 0x08, 0x0a },
162 { MHZ(150), MHZ(181.25), 0x1b, 0x00, 0x00, 0x08, 0x0a },
163 { MHZ(181.25), MHZ(218.75), 0x18, 0x00, 0x00, 0x08, 0x0a },
164 { MHZ(218.75), MHZ(250), 0x18, 0x00, 0x00, 0x08, 0x0a },
165 { MHZ(250), MHZ(300), 0x17, 0x00, 0x00, 0x08, 0x0a },
166 { MHZ(300), MHZ(362.5), 0x13, 0x00, 0x00, 0x08, 0x0a },
167 { MHZ(362.5), MHZ(455.48), 0x10, 0x00, 0x00, 0x08, 0x0a },
168 { MHZ(455.48), MHZ(500), 0x10, 0x00, 0x00, 0x08, 0x0a },
169 { MHZ(500), MHZ(600), 0x0f, 0x00, 0x00, 0x08, 0x0a },
170 { MHZ(600), MHZ(725), 0x0b, 0x00, 0x00, 0x08, 0x0a },
171 { MHZ(725), MHZ(875), 0x08, 0x00, 0x00, 0x08, 0x0a },
172 { MHZ(875), MHZ(1000), 0x08, 0x00, 0x00, 0x08, 0x0a },
173 { MHZ(1000), MHZ(1200), 0x07, 0x00, 0x00, 0x08, 0x0a },
174 { MHZ(1200), MHZ(1250), 0x03, 0x00, 0x00, 0x08, 0x0a },
175 { /* sentinel */ },
176 };
177
rcar_mipi_dsi_write(struct rcar_mipi_dsi * dsi,u32 reg,u32 data)178 static void rcar_mipi_dsi_write(struct rcar_mipi_dsi *dsi, u32 reg, u32 data)
179 {
180 iowrite32(data, dsi->mmio + reg);
181 }
182
rcar_mipi_dsi_read(struct rcar_mipi_dsi * dsi,u32 reg)183 static u32 rcar_mipi_dsi_read(struct rcar_mipi_dsi *dsi, u32 reg)
184 {
185 return ioread32(dsi->mmio + reg);
186 }
187
rcar_mipi_dsi_clr(struct rcar_mipi_dsi * dsi,u32 reg,u32 clr)188 static void rcar_mipi_dsi_clr(struct rcar_mipi_dsi *dsi, u32 reg, u32 clr)
189 {
190 rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) & ~clr);
191 }
192
rcar_mipi_dsi_set(struct rcar_mipi_dsi * dsi,u32 reg,u32 set)193 static void rcar_mipi_dsi_set(struct rcar_mipi_dsi *dsi, u32 reg, u32 set)
194 {
195 rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) | set);
196 }
197
rcar_mipi_dsi_write_phtw(struct rcar_mipi_dsi * dsi,u32 phtw)198 static int rcar_mipi_dsi_write_phtw(struct rcar_mipi_dsi *dsi, u32 phtw)
199 {
200 u32 status;
201 int ret;
202
203 rcar_mipi_dsi_write(dsi, PHTW, phtw);
204
205 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
206 !(status & (PHTW_DWEN | PHTW_CWEN)),
207 2000, 10000, false, dsi, PHTW);
208 if (ret < 0) {
209 dev_err(dsi->dev, "PHY test interface write timeout (0x%08x)\n",
210 phtw);
211 return ret;
212 }
213
214 return ret;
215 }
216
rcar_mipi_dsi_write_phtw_arr(struct rcar_mipi_dsi * dsi,const u32 * phtw,unsigned int size)217 static int rcar_mipi_dsi_write_phtw_arr(struct rcar_mipi_dsi *dsi,
218 const u32 *phtw, unsigned int size)
219 {
220 for (unsigned int i = 0; i < size; i++) {
221 int ret = rcar_mipi_dsi_write_phtw(dsi, phtw[i]);
222
223 if (ret < 0)
224 return ret;
225 }
226
227 return 0;
228 }
229
230 #define WRITE_PHTW(...) \
231 ({ \
232 static const u32 phtw[] = { __VA_ARGS__ }; \
233 int ret; \
234 ret = rcar_mipi_dsi_write_phtw_arr(dsi, phtw, \
235 ARRAY_SIZE(phtw)); \
236 ret; \
237 })
238
rcar_mipi_dsi_init_phtw_v3u(struct rcar_mipi_dsi * dsi)239 static int rcar_mipi_dsi_init_phtw_v3u(struct rcar_mipi_dsi *dsi)
240 {
241 return WRITE_PHTW(0x01020114, 0x01600115, 0x01030116, 0x0102011d,
242 0x011101a4, 0x018601a4, 0x014201a0, 0x010001a3,
243 0x0101011f);
244 }
245
rcar_mipi_dsi_post_init_phtw_v3u(struct rcar_mipi_dsi * dsi)246 static int rcar_mipi_dsi_post_init_phtw_v3u(struct rcar_mipi_dsi *dsi)
247 {
248 return WRITE_PHTW(0x010c0130, 0x010c0140, 0x010c0150, 0x010c0180,
249 0x010c0190, 0x010a0160, 0x010a0170, 0x01800164,
250 0x01800174);
251 }
252
rcar_mipi_dsi_init_phtw_v4h(struct rcar_mipi_dsi * dsi,const struct dsi_setup_info * setup_info)253 static int rcar_mipi_dsi_init_phtw_v4h(struct rcar_mipi_dsi *dsi,
254 const struct dsi_setup_info *setup_info)
255 {
256 int ret;
257
258 if (setup_info->hsfreq < MHZ(450)) {
259 ret = WRITE_PHTW(0x01010100, 0x011b01ac);
260 if (ret)
261 return ret;
262 }
263
264 ret = WRITE_PHTW(0x01010100, 0x01030173, 0x01000174, 0x01500175,
265 0x01030176, 0x01040166, 0x010201ad);
266 if (ret)
267 return ret;
268
269 if (setup_info->hsfreq <= MHZ(1000))
270 ret = WRITE_PHTW(0x01020100, 0x01910170, 0x01020171,
271 0x01110172);
272 else if (setup_info->hsfreq <= MHZ(1500))
273 ret = WRITE_PHTW(0x01020100, 0x01980170, 0x01030171,
274 0x01100172);
275 else if (setup_info->hsfreq <= MHZ(2500))
276 ret = WRITE_PHTW(0x01020100, 0x0144016b, 0x01000172);
277 else
278 return -EINVAL;
279
280 if (ret)
281 return ret;
282
283 if (dsi->lanes <= 1) {
284 ret = WRITE_PHTW(0x01070100, 0x010e010b);
285 if (ret)
286 return ret;
287 }
288
289 if (dsi->lanes <= 2) {
290 ret = WRITE_PHTW(0x01090100, 0x010e010b);
291 if (ret)
292 return ret;
293 }
294
295 if (dsi->lanes <= 3) {
296 ret = WRITE_PHTW(0x010b0100, 0x010e010b);
297 if (ret)
298 return ret;
299 }
300
301 if (setup_info->hsfreq <= MHZ(1500)) {
302 ret = WRITE_PHTW(0x01010100, 0x01c0016e);
303 if (ret)
304 return ret;
305 }
306
307 return 0;
308 }
309
310 static int
rcar_mipi_dsi_post_init_phtw_v4h(struct rcar_mipi_dsi * dsi,const struct dsi_setup_info * setup_info)311 rcar_mipi_dsi_post_init_phtw_v4h(struct rcar_mipi_dsi *dsi,
312 const struct dsi_setup_info *setup_info)
313 {
314 u32 status;
315 int ret;
316
317 if (setup_info->hsfreq <= MHZ(1500)) {
318 WRITE_PHTW(0x01020100, 0x00000180);
319
320 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
321 status & PHTR_TESTDOUT_TEST,
322 2000, 10000, false, dsi, PHTR);
323 if (ret < 0) {
324 dev_err(dsi->dev, "failed to test PHTR\n");
325 return ret;
326 }
327
328 WRITE_PHTW(0x01010100, 0x0100016e);
329 }
330
331 return 0;
332 }
333
334 /* -----------------------------------------------------------------------------
335 * Hardware Setup
336 */
337
rcar_mipi_dsi_pll_calc(struct rcar_mipi_dsi * dsi,unsigned long fin_rate,unsigned long fout_target,struct dsi_setup_info * setup_info)338 static void rcar_mipi_dsi_pll_calc(struct rcar_mipi_dsi *dsi,
339 unsigned long fin_rate,
340 unsigned long fout_target,
341 struct dsi_setup_info *setup_info)
342 {
343 unsigned int best_err = -1;
344 const struct rcar_mipi_dsi_device_info *info = dsi->info;
345
346 for (unsigned int n = info->n_min; n <= info->n_max; n++) {
347 unsigned long fpfd;
348
349 fpfd = fin_rate / n;
350
351 if (fpfd < info->fpfd_min || fpfd > info->fpfd_max)
352 continue;
353
354 for (unsigned int m = info->m_min; m <= info->m_max; m++) {
355 unsigned int err;
356 u64 fout;
357
358 fout = div64_u64((u64)fpfd * m, dsi->info->n_mul);
359
360 if (fout < info->fout_min || fout > info->fout_max)
361 continue;
362
363 fout = div64_u64(fout, setup_info->vclk_divider);
364
365 if (fout < setup_info->clkset->min_freq ||
366 fout > setup_info->clkset->max_freq)
367 continue;
368
369 err = abs((long)(fout - fout_target) * 10000 /
370 (long)fout_target);
371 if (err < best_err) {
372 setup_info->m = m;
373 setup_info->n = n;
374 setup_info->fout = (unsigned long)fout;
375 best_err = err;
376
377 if (err == 0)
378 return;
379 }
380 }
381 }
382 }
383
rcar_mipi_dsi_parameters_calc(struct rcar_mipi_dsi * dsi,struct clk * clk,unsigned long target,struct dsi_setup_info * setup_info)384 static void rcar_mipi_dsi_parameters_calc(struct rcar_mipi_dsi *dsi,
385 struct clk *clk, unsigned long target,
386 struct dsi_setup_info *setup_info)
387 {
388
389 const struct dsi_clk_config *clk_cfg;
390 unsigned long fout_target;
391 unsigned long fin_rate;
392 unsigned int i;
393 unsigned int err;
394
395 /*
396 * Calculate Fout = dot clock * ColorDepth / (2 * Lane Count)
397 * The range out Fout is [40 - 1250] Mhz
398 */
399 fout_target = target * mipi_dsi_pixel_format_to_bpp(dsi->format)
400 / (2 * dsi->lanes);
401 if (fout_target < MHZ(40) || fout_target > MHZ(1250))
402 return;
403
404 /* Find PLL settings */
405 for (clk_cfg = dsi->info->clk_cfg; clk_cfg->min_freq != 0; clk_cfg++) {
406 if (fout_target > clk_cfg->min_freq &&
407 fout_target <= clk_cfg->max_freq) {
408 setup_info->clkset = clk_cfg;
409 break;
410 }
411 }
412
413 fin_rate = clk_get_rate(clk);
414
415 switch (dsi->info->model) {
416 case RCAR_DSI_V3U:
417 default:
418 setup_info->vclk_divider = 1 << ((clk_cfg->vco_cntrl >> 4) & 0x3);
419 break;
420
421 case RCAR_DSI_V4H:
422 setup_info->vclk_divider = 1 << (((clk_cfg->vco_cntrl >> 3) & 0x7) + 1);
423 break;
424 }
425
426 rcar_mipi_dsi_pll_calc(dsi, fin_rate, fout_target, setup_info);
427
428 /* Find hsfreqrange */
429 setup_info->hsfreq = setup_info->fout * 2;
430 for (i = 0; i < ARRAY_SIZE(hsfreqrange_table); i++) {
431 if (hsfreqrange_table[i][0] >= setup_info->hsfreq) {
432 setup_info->hsfreqrange = hsfreqrange_table[i][1];
433 break;
434 }
435 }
436
437 err = abs((long)(setup_info->fout - fout_target) * 10000 / (long)fout_target);
438
439 dev_dbg(dsi->dev,
440 "Fout = %u * %lu / (%u * %u * %u) = %lu (target %lu Hz, error %d.%02u%%)\n",
441 setup_info->m, fin_rate, dsi->info->n_mul, setup_info->n,
442 setup_info->vclk_divider, setup_info->fout, fout_target,
443 err / 100, err % 100);
444
445 dev_dbg(dsi->dev,
446 "vco_cntrl = 0x%x\tprop_cntrl = 0x%x\thsfreqrange = 0x%x\n",
447 clk_cfg->vco_cntrl, clk_cfg->prop_cntrl,
448 setup_info->hsfreqrange);
449 }
450
rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi * dsi,const struct drm_display_mode * mode)451 static void rcar_mipi_dsi_set_display_timing(struct rcar_mipi_dsi *dsi,
452 const struct drm_display_mode *mode)
453 {
454 u32 setr;
455 u32 vprmset0r;
456 u32 vprmset1r;
457 u32 vprmset2r;
458 u32 vprmset3r;
459 u32 vprmset4r;
460
461 /* Configuration for Pixel Stream and Packet Header */
462 switch (mipi_dsi_pixel_format_to_bpp(dsi->format)) {
463 case 24:
464 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB24);
465 break;
466 case 18:
467 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB18);
468 break;
469 case 16:
470 rcar_mipi_dsi_write(dsi, TXVMPSPHSETR, TXVMPSPHSETR_DT_RGB16);
471 break;
472 default:
473 dev_warn(dsi->dev, "unsupported format");
474 return;
475 }
476
477 /* Configuration for Blanking sequence and Input Pixel */
478 setr = TXVMSETR_PIXWDTH | TXVMSETR_VSTPM;
479
480 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) {
481 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE))
482 setr |= TXVMSETR_SYNSEQ_EVENTS;
483 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP))
484 setr |= TXVMSETR_HFPBPEN;
485 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP))
486 setr |= TXVMSETR_HBPBPEN;
487 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA))
488 setr |= TXVMSETR_HSABPEN;
489 }
490
491 rcar_mipi_dsi_write(dsi, TXVMSETR, setr);
492
493 /* Configuration for Video Parameters, input is always RGB888 */
494 vprmset0r = TXVMVPRMSET0R_BPP_24;
495 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC))
496 vprmset0r |= TXVMVPRMSET0R_VSPOL_LOW;
497 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC))
498 vprmset0r |= TXVMVPRMSET0R_HSPOL_LOW;
499
500 vprmset1r = TXVMVPRMSET1R_VACTIVE(mode->vdisplay)
501 | TXVMVPRMSET1R_VSA(mode->vsync_end - mode->vsync_start);
502
503 vprmset2r = TXVMVPRMSET2R_VFP(mode->vsync_start - mode->vdisplay)
504 | TXVMVPRMSET2R_VBP(mode->vtotal - mode->vsync_end);
505
506 vprmset3r = TXVMVPRMSET3R_HACTIVE(mode->hdisplay)
507 | TXVMVPRMSET3R_HSA(mode->hsync_end - mode->hsync_start);
508
509 vprmset4r = TXVMVPRMSET4R_HFP(mode->hsync_start - mode->hdisplay)
510 | TXVMVPRMSET4R_HBP(mode->htotal - mode->hsync_end);
511
512 rcar_mipi_dsi_write(dsi, TXVMVPRMSET0R, vprmset0r);
513 rcar_mipi_dsi_write(dsi, TXVMVPRMSET1R, vprmset1r);
514 rcar_mipi_dsi_write(dsi, TXVMVPRMSET2R, vprmset2r);
515 rcar_mipi_dsi_write(dsi, TXVMVPRMSET3R, vprmset3r);
516 rcar_mipi_dsi_write(dsi, TXVMVPRMSET4R, vprmset4r);
517 }
518
rcar_mipi_dsi_startup(struct rcar_mipi_dsi * dsi,const struct drm_display_mode * mode)519 static int rcar_mipi_dsi_startup(struct rcar_mipi_dsi *dsi,
520 const struct drm_display_mode *mode)
521 {
522 struct dsi_setup_info setup_info = {};
523 unsigned int timeout;
524 int ret;
525 int dsi_format;
526 u32 phy_setup;
527 u32 clockset2, clockset3;
528 u32 ppisetr;
529 u32 vclkset;
530
531 /* Checking valid format */
532 dsi_format = mipi_dsi_pixel_format_to_bpp(dsi->format);
533 if (dsi_format < 0) {
534 dev_warn(dsi->dev, "invalid format");
535 return -EINVAL;
536 }
537
538 /* Parameters Calculation */
539 rcar_mipi_dsi_parameters_calc(dsi, dsi->clocks.pll,
540 mode->clock * 1000, &setup_info);
541
542 /* LPCLK enable */
543 rcar_mipi_dsi_set(dsi, LPCLKSET, LPCLKSET_CKEN);
544
545 /* CFGCLK enabled */
546 rcar_mipi_dsi_set(dsi, CFGCLKSET, CFGCLKSET_CKEN);
547
548 rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ);
549 rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
550
551 rcar_mipi_dsi_set(dsi, PHTC, PHTC_TESTCLR);
552 rcar_mipi_dsi_clr(dsi, PHTC, PHTC_TESTCLR);
553
554 /* PHY setting */
555 phy_setup = rcar_mipi_dsi_read(dsi, PHYSETUP);
556 phy_setup &= ~PHYSETUP_HSFREQRANGE_MASK;
557 phy_setup |= PHYSETUP_HSFREQRANGE(setup_info.hsfreqrange);
558 rcar_mipi_dsi_write(dsi, PHYSETUP, phy_setup);
559
560 switch (dsi->info->model) {
561 case RCAR_DSI_V3U:
562 default:
563 ret = rcar_mipi_dsi_init_phtw_v3u(dsi);
564 if (ret < 0)
565 return ret;
566 break;
567
568 case RCAR_DSI_V4H:
569 ret = rcar_mipi_dsi_init_phtw_v4h(dsi, &setup_info);
570 if (ret < 0)
571 return ret;
572 break;
573 }
574
575 /* PLL Clock Setting */
576 rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
577 rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
578 rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_SHADOW_CLEAR);
579
580 clockset2 = CLOCKSET2_M(setup_info.m - dsi->info->clockset2_m_offset)
581 | CLOCKSET2_N(setup_info.n - 1)
582 | CLOCKSET2_VCO_CNTRL(setup_info.clkset->vco_cntrl);
583 clockset3 = CLOCKSET3_PROP_CNTRL(setup_info.clkset->prop_cntrl)
584 | CLOCKSET3_INT_CNTRL(setup_info.clkset->int_cntrl)
585 | CLOCKSET3_CPBIAS_CNTRL(setup_info.clkset->cpbias_cntrl)
586 | CLOCKSET3_GMP_CNTRL(setup_info.clkset->gmp_cntrl);
587 rcar_mipi_dsi_write(dsi, CLOCKSET2, clockset2);
588 rcar_mipi_dsi_write(dsi, CLOCKSET3, clockset3);
589
590 rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
591 rcar_mipi_dsi_set(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
592 udelay(10);
593 rcar_mipi_dsi_clr(dsi, CLOCKSET1, CLOCKSET1_UPDATEPLL);
594
595 rcar_mipi_dsi_clr(dsi, TXSETR, TXSETR_LANECNT_MASK);
596 rcar_mipi_dsi_set(dsi, TXSETR, dsi->lanes - 1);
597
598 ppisetr = ((BIT(dsi->lanes) - 1) & PPISETR_DLEN_MASK) | PPISETR_CLEN;
599 rcar_mipi_dsi_write(dsi, PPISETR, ppisetr);
600
601 rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
602 rcar_mipi_dsi_set(dsi, PHYSETUP, PHYSETUP_RSTZ);
603 usleep_range(400, 500);
604
605 /* Checking PPI clock status register */
606 for (timeout = 10; timeout > 0; --timeout) {
607 if ((rcar_mipi_dsi_read(dsi, PPICLSR) & PPICLSR_STPST) &&
608 (rcar_mipi_dsi_read(dsi, PPIDLSR) & PPIDLSR_STPST) &&
609 (rcar_mipi_dsi_read(dsi, CLOCKSET1) & CLOCKSET1_LOCK_PHY))
610 break;
611
612 usleep_range(1000, 2000);
613 }
614
615 if (!timeout) {
616 dev_err(dsi->dev, "failed to enable PPI clock\n");
617 return -ETIMEDOUT;
618 }
619
620 switch (dsi->info->model) {
621 case RCAR_DSI_V3U:
622 default:
623 ret = rcar_mipi_dsi_post_init_phtw_v3u(dsi);
624 if (ret < 0)
625 return ret;
626 break;
627
628 case RCAR_DSI_V4H:
629 ret = rcar_mipi_dsi_post_init_phtw_v4h(dsi, &setup_info);
630 if (ret < 0)
631 return ret;
632 break;
633 }
634
635 /* Enable DOT clock */
636 vclkset = VCLKSET_CKEN;
637 rcar_mipi_dsi_write(dsi, VCLKSET, vclkset);
638
639 /* Output is always RGB, never YCbCr */
640 if (dsi_format == 24)
641 vclkset |= VCLKSET_BPP_24;
642 else if (dsi_format == 18)
643 vclkset |= VCLKSET_BPP_18;
644 else if (dsi_format == 16)
645 vclkset |= VCLKSET_BPP_16;
646 else {
647 dev_warn(dsi->dev, "unsupported format");
648 return -EINVAL;
649 }
650
651 vclkset |= VCLKSET_LANE(dsi->lanes - 1);
652
653 switch (dsi->info->model) {
654 case RCAR_DSI_V3U:
655 default:
656 vclkset |= VCLKSET_DIV_V3U(__ffs(setup_info.vclk_divider));
657 break;
658
659 case RCAR_DSI_V4H:
660 vclkset |= VCLKSET_DIV_V4H(__ffs(setup_info.vclk_divider) - 1);
661 break;
662 }
663
664 rcar_mipi_dsi_write(dsi, VCLKSET, vclkset);
665
666 /* After setting VCLKSET register, enable VCLKEN */
667 rcar_mipi_dsi_set(dsi, VCLKEN, VCLKEN_CKEN);
668
669 dev_dbg(dsi->dev, "DSI device is started\n");
670
671 return 0;
672 }
673
rcar_mipi_dsi_shutdown(struct rcar_mipi_dsi * dsi)674 static void rcar_mipi_dsi_shutdown(struct rcar_mipi_dsi *dsi)
675 {
676 /* Disable VCLKEN */
677 rcar_mipi_dsi_write(dsi, VCLKSET, 0);
678
679 /* Disable DOT clock */
680 rcar_mipi_dsi_write(dsi, VCLKSET, 0);
681
682 rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_RSTZ);
683 rcar_mipi_dsi_clr(dsi, PHYSETUP, PHYSETUP_SHUTDOWNZ);
684
685 /* CFGCLK disable */
686 rcar_mipi_dsi_clr(dsi, CFGCLKSET, CFGCLKSET_CKEN);
687
688 /* LPCLK disable */
689 rcar_mipi_dsi_clr(dsi, LPCLKSET, LPCLKSET_CKEN);
690
691 dev_dbg(dsi->dev, "DSI device is shutdown\n");
692 }
693
rcar_mipi_dsi_clk_enable(struct rcar_mipi_dsi * dsi)694 static int rcar_mipi_dsi_clk_enable(struct rcar_mipi_dsi *dsi)
695 {
696 int ret;
697
698 reset_control_deassert(dsi->rstc);
699
700 ret = clk_prepare_enable(dsi->clocks.mod);
701 if (ret < 0)
702 goto err_reset;
703
704 ret = clk_prepare_enable(dsi->clocks.dsi);
705 if (ret < 0)
706 goto err_clock;
707
708 return 0;
709
710 err_clock:
711 clk_disable_unprepare(dsi->clocks.mod);
712 err_reset:
713 reset_control_assert(dsi->rstc);
714 return ret;
715 }
716
rcar_mipi_dsi_clk_disable(struct rcar_mipi_dsi * dsi)717 static void rcar_mipi_dsi_clk_disable(struct rcar_mipi_dsi *dsi)
718 {
719 clk_disable_unprepare(dsi->clocks.dsi);
720 clk_disable_unprepare(dsi->clocks.mod);
721
722 reset_control_assert(dsi->rstc);
723 }
724
rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi * dsi)725 static int rcar_mipi_dsi_start_hs_clock(struct rcar_mipi_dsi *dsi)
726 {
727 /*
728 * In HW manual, we need to check TxDDRClkHS-Q Stable? but it dont
729 * write how to check. So we skip this check in this patch
730 */
731 u32 status;
732 int ret;
733
734 /* Start HS clock. */
735 rcar_mipi_dsi_set(dsi, PPICLCR, PPICLCR_TXREQHS);
736
737 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
738 status & PPICLSR_TOHS,
739 2000, 10000, false, dsi, PPICLSR);
740 if (ret < 0) {
741 dev_err(dsi->dev, "failed to enable HS clock\n");
742 return ret;
743 }
744
745 rcar_mipi_dsi_set(dsi, PPICLSCR, PPICLSCR_TOHS);
746
747 return 0;
748 }
749
rcar_mipi_dsi_start_video(struct rcar_mipi_dsi * dsi)750 static int rcar_mipi_dsi_start_video(struct rcar_mipi_dsi *dsi)
751 {
752 u32 status;
753 int ret;
754
755 /* Wait for the link to be ready. */
756 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
757 !(status & (LINKSR_LPBUSY | LINKSR_HSBUSY)),
758 2000, 10000, false, dsi, LINKSR);
759 if (ret < 0) {
760 dev_err(dsi->dev, "Link failed to become ready\n");
761 return ret;
762 }
763
764 /* De-assert video FIFO clear. */
765 rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_VFCLR);
766
767 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
768 status & TXVMSR_VFRDY,
769 2000, 10000, false, dsi, TXVMSR);
770 if (ret < 0) {
771 dev_err(dsi->dev, "Failed to de-assert video FIFO clear\n");
772 return ret;
773 }
774
775 /* Enable transmission in video mode. */
776 rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_EN_VIDEO);
777
778 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
779 status & TXVMSR_RDY,
780 2000, 10000, false, dsi, TXVMSR);
781 if (ret < 0) {
782 dev_err(dsi->dev, "Failed to enable video transmission\n");
783 return ret;
784 }
785
786 return 0;
787 }
788
rcar_mipi_dsi_stop_video(struct rcar_mipi_dsi * dsi)789 static void rcar_mipi_dsi_stop_video(struct rcar_mipi_dsi *dsi)
790 {
791 u32 status;
792 int ret;
793
794 /* Disable transmission in video mode. */
795 rcar_mipi_dsi_clr(dsi, TXVMCR, TXVMCR_EN_VIDEO);
796
797 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
798 !(status & TXVMSR_ACT),
799 2000, 100000, false, dsi, TXVMSR);
800 if (ret < 0) {
801 dev_err(dsi->dev, "Failed to disable video transmission\n");
802 return;
803 }
804
805 /* Assert video FIFO clear. */
806 rcar_mipi_dsi_set(dsi, TXVMCR, TXVMCR_VFCLR);
807
808 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
809 !(status & TXVMSR_VFRDY),
810 2000, 100000, false, dsi, TXVMSR);
811 if (ret < 0) {
812 dev_err(dsi->dev, "Failed to assert video FIFO clear\n");
813 return;
814 }
815 }
816
817 /* -----------------------------------------------------------------------------
818 * Bridge
819 */
820
rcar_mipi_dsi_attach(struct drm_bridge * bridge,struct drm_encoder * encoder,enum drm_bridge_attach_flags flags)821 static int rcar_mipi_dsi_attach(struct drm_bridge *bridge,
822 struct drm_encoder *encoder,
823 enum drm_bridge_attach_flags flags)
824 {
825 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
826
827 return drm_bridge_attach(encoder, dsi->next_bridge, bridge,
828 flags);
829 }
830
rcar_mipi_dsi_atomic_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)831 static void rcar_mipi_dsi_atomic_enable(struct drm_bridge *bridge,
832 struct drm_atomic_state *state)
833 {
834 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
835
836 rcar_mipi_dsi_start_video(dsi);
837 }
838
rcar_mipi_dsi_atomic_disable(struct drm_bridge * bridge,struct drm_atomic_state * state)839 static void rcar_mipi_dsi_atomic_disable(struct drm_bridge *bridge,
840 struct drm_atomic_state *state)
841 {
842 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
843
844 rcar_mipi_dsi_stop_video(dsi);
845 }
846
rcar_mipi_dsi_pclk_enable(struct drm_bridge * bridge,struct drm_atomic_state * state)847 void rcar_mipi_dsi_pclk_enable(struct drm_bridge *bridge,
848 struct drm_atomic_state *state)
849 {
850 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
851 const struct drm_display_mode *mode;
852 struct drm_connector *connector;
853 struct drm_crtc *crtc;
854 int ret;
855
856 connector = drm_atomic_get_new_connector_for_encoder(state,
857 bridge->encoder);
858 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc;
859 mode = &drm_atomic_get_new_crtc_state(state, crtc)->adjusted_mode;
860
861 ret = rcar_mipi_dsi_clk_enable(dsi);
862 if (ret < 0) {
863 dev_err(dsi->dev, "failed to enable DSI clocks\n");
864 return;
865 }
866
867 ret = rcar_mipi_dsi_startup(dsi, mode);
868 if (ret < 0)
869 goto err_dsi_startup;
870
871 rcar_mipi_dsi_set_display_timing(dsi, mode);
872
873 ret = rcar_mipi_dsi_start_hs_clock(dsi);
874 if (ret < 0)
875 goto err_dsi_start_hs;
876
877 return;
878
879 err_dsi_start_hs:
880 rcar_mipi_dsi_shutdown(dsi);
881 err_dsi_startup:
882 rcar_mipi_dsi_clk_disable(dsi);
883 }
884 EXPORT_SYMBOL_GPL(rcar_mipi_dsi_pclk_enable);
885
rcar_mipi_dsi_pclk_disable(struct drm_bridge * bridge)886 void rcar_mipi_dsi_pclk_disable(struct drm_bridge *bridge)
887 {
888 struct rcar_mipi_dsi *dsi = bridge_to_rcar_mipi_dsi(bridge);
889
890 rcar_mipi_dsi_shutdown(dsi);
891 rcar_mipi_dsi_clk_disable(dsi);
892 }
893 EXPORT_SYMBOL_GPL(rcar_mipi_dsi_pclk_disable);
894
895 static enum drm_mode_status
rcar_mipi_dsi_bridge_mode_valid(struct drm_bridge * bridge,const struct drm_display_info * info,const struct drm_display_mode * mode)896 rcar_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge,
897 const struct drm_display_info *info,
898 const struct drm_display_mode *mode)
899 {
900 if (mode->clock > 297000)
901 return MODE_CLOCK_HIGH;
902
903 return MODE_OK;
904 }
905
906 static const struct drm_bridge_funcs rcar_mipi_dsi_bridge_ops = {
907 .attach = rcar_mipi_dsi_attach,
908 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
909 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
910 .atomic_reset = drm_atomic_helper_bridge_reset,
911 .atomic_enable = rcar_mipi_dsi_atomic_enable,
912 .atomic_disable = rcar_mipi_dsi_atomic_disable,
913 .mode_valid = rcar_mipi_dsi_bridge_mode_valid,
914 };
915
916 /* -----------------------------------------------------------------------------
917 * Host setting
918 */
919
rcar_mipi_dsi_host_attach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)920 static int rcar_mipi_dsi_host_attach(struct mipi_dsi_host *host,
921 struct mipi_dsi_device *device)
922 {
923 struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
924 int ret;
925
926 if (device->lanes > dsi->num_data_lanes)
927 return -EINVAL;
928
929 dsi->lanes = device->lanes;
930 dsi->format = device->format;
931 dsi->mode_flags = device->mode_flags;
932
933 dsi->next_bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node,
934 1, 0);
935 if (IS_ERR(dsi->next_bridge)) {
936 ret = PTR_ERR(dsi->next_bridge);
937 dev_err(dsi->dev, "failed to get next bridge: %d\n", ret);
938 return ret;
939 }
940
941 /* Initialize the DRM bridge. */
942 dsi->bridge.of_node = dsi->dev->of_node;
943 drm_bridge_add(&dsi->bridge);
944
945 return 0;
946 }
947
rcar_mipi_dsi_host_detach(struct mipi_dsi_host * host,struct mipi_dsi_device * device)948 static int rcar_mipi_dsi_host_detach(struct mipi_dsi_host *host,
949 struct mipi_dsi_device *device)
950 {
951 struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
952
953 drm_bridge_remove(&dsi->bridge);
954
955 return 0;
956 }
957
rcar_mipi_dsi_host_tx_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg,bool is_rx_xfer)958 static ssize_t rcar_mipi_dsi_host_tx_transfer(struct mipi_dsi_host *host,
959 const struct mipi_dsi_msg *msg,
960 bool is_rx_xfer)
961 {
962 const bool is_tx_long = mipi_dsi_packet_format_is_long(msg->type);
963 struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
964 struct mipi_dsi_packet packet;
965 u8 payload[16] = { 0 };
966 u32 status;
967 int ret;
968
969 ret = mipi_dsi_create_packet(&packet, msg);
970 if (ret)
971 return ret;
972
973 /* Configure LP or HS command transfer. */
974 rcar_mipi_dsi_write(dsi, TXCMSETR, (msg->flags & MIPI_DSI_MSG_USE_LPM) ?
975 TXCMSETR_SPDTYP : 0);
976
977 /* Register access mode for RX transfer. */
978 if (is_rx_xfer)
979 rcar_mipi_dsi_write(dsi, RXPSETR, 0);
980
981 /* Do not use IRQ, poll for completion, the completion is quick. */
982 rcar_mipi_dsi_write(dsi, TXCMIER, 0);
983
984 /*
985 * Send the header:
986 * header[0] = Virtual Channel + Data Type
987 * header[1] = Word Count LSB (LP) or first param (SP)
988 * header[2] = Word Count MSB (LP) or second param (SP)
989 */
990 rcar_mipi_dsi_write(dsi, TXCMPHDR,
991 (is_tx_long ? TXCMPHDR_FMT : 0) |
992 TXCMPHDR_VC(msg->channel) |
993 TXCMPHDR_DT(msg->type) |
994 TXCMPHDR_DATA1(packet.header[2]) |
995 TXCMPHDR_DATA0(packet.header[1]));
996
997 if (is_tx_long) {
998 memcpy(payload, packet.payload,
999 min(msg->tx_len, sizeof(payload)));
1000
1001 rcar_mipi_dsi_write(dsi, TXCMPPD0R,
1002 (payload[3] << 24) | (payload[2] << 16) |
1003 (payload[1] << 8) | payload[0]);
1004 rcar_mipi_dsi_write(dsi, TXCMPPD1R,
1005 (payload[7] << 24) | (payload[6] << 16) |
1006 (payload[5] << 8) | payload[4]);
1007 rcar_mipi_dsi_write(dsi, TXCMPPD2R,
1008 (payload[11] << 24) | (payload[10] << 16) |
1009 (payload[9] << 8) | payload[8]);
1010 rcar_mipi_dsi_write(dsi, TXCMPPD3R,
1011 (payload[15] << 24) | (payload[14] << 16) |
1012 (payload[13] << 8) | payload[12]);
1013 }
1014
1015 /* Start the transfer, RX with BTA, TX without BTA. */
1016 if (is_rx_xfer) {
1017 rcar_mipi_dsi_write(dsi, TXCMCR, TXCMCR_BTAREQ);
1018
1019 /* Wait until the transmission, BTA, reception completed. */
1020 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
1021 (status & RXPSR_BTAREQEND),
1022 2000, 50000, false, dsi, RXPSR);
1023 } else {
1024 rcar_mipi_dsi_write(dsi, TXCMCR, TXCMCR_TXREQ);
1025
1026 /* Wait until the transmission completed. */
1027 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
1028 (status & TXCMSR_TXREQEND),
1029 2000, 50000, false, dsi, TXCMSR);
1030 }
1031
1032 if (ret < 0) {
1033 dev_err(dsi->dev, "Command transfer timeout (0x%08x)\n",
1034 status);
1035 return ret;
1036 }
1037
1038 return packet.size;
1039 }
1040
rcar_mipi_dsi_host_rx_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1041 static ssize_t rcar_mipi_dsi_host_rx_transfer(struct mipi_dsi_host *host,
1042 const struct mipi_dsi_msg *msg)
1043 {
1044 struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
1045 u8 *rx_buf = (u8 *)(msg->rx_buf);
1046 u32 reg, data, status, wc;
1047 int i, ret;
1048
1049 /* RX transfer received data validation and parsing starts here. */
1050 reg = rcar_mipi_dsi_read(dsi, TOSR);
1051 if (reg & TOSR_TATO) { /* Turn-Around TimeOut. */
1052 /* Clear TATO Turn-Around TimeOut bit. */
1053 rcar_mipi_dsi_write(dsi, TOSR, TOSR_TATO);
1054 return -ETIMEDOUT;
1055 }
1056
1057 reg = rcar_mipi_dsi_read(dsi, RXPSR);
1058
1059 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) {
1060 /* Transfer with zero-length RX. */
1061 if (!(reg & RXPSR_RCVACK)) {
1062 /* No ACK on RX response received. */
1063 return -EINVAL;
1064 }
1065 } else {
1066 /* Transfer with non-zero-length RX. */
1067 if (!(reg & RXPSR_RCVRESP)) {
1068 /* No packet header of RX response received. */
1069 return -EINVAL;
1070 }
1071
1072 if (reg & (RXPSR_CRCERR | RXPSR_WCERR | RXPSR_AXIERR | RXPSR_OVRERR)) {
1073 /* Incorrect response payload. */
1074 return -ENODATA;
1075 }
1076
1077 data = rcar_mipi_dsi_read(dsi, RXPHDR);
1078 if (data & RXPHDR_FMT) { /* Long Packet Response. */
1079 /* Read Long Packet Response length from packet header. */
1080 wc = data & 0xffff;
1081 if (wc > msg->rx_len) {
1082 dev_warn(dsi->dev,
1083 "Long Packet Response longer than RX buffer (%d), limited to %zu Bytes\n",
1084 wc, msg->rx_len);
1085 wc = msg->rx_len;
1086 }
1087
1088 if (wc > 16) {
1089 dev_warn(dsi->dev,
1090 "Long Packet Response too long (%d), limited to 16 Bytes\n",
1091 wc);
1092 wc = 16;
1093 }
1094
1095 for (i = 0; i < msg->rx_len; i++) {
1096 if (!(i % 4))
1097 data = rcar_mipi_dsi_read(dsi, RXPPD0R + i);
1098
1099 rx_buf[i] = data & 0xff;
1100 data >>= 8;
1101 }
1102 } else { /* Short Packet Response. */
1103 if (msg->rx_len >= 1)
1104 rx_buf[0] = data & 0xff;
1105 if (msg->rx_len >= 2)
1106 rx_buf[1] = (data >> 8) & 0xff;
1107 if (msg->rx_len >= 3) {
1108 dev_warn(dsi->dev,
1109 "Expected Short Packet Response too long (%zu), limited to 2 Bytes\n",
1110 msg->rx_len);
1111 }
1112 }
1113 }
1114
1115 if (reg & RXPSR_RCVAKE) {
1116 /* Acknowledge and Error report received. */
1117 return -EFAULT;
1118 }
1119
1120 /* Wait until the bus handover to host processor completed. */
1121 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
1122 !(status & PPIDL0SR_DIR),
1123 2000, 50000, false, dsi, PPIDL0SR);
1124 if (ret < 0) {
1125 dev_err(dsi->dev, "Command RX DIR timeout (0x%08x)\n", status);
1126 return ret;
1127 }
1128
1129 /* Wait until the data lane is in LP11 stop state. */
1130 ret = read_poll_timeout(rcar_mipi_dsi_read, status,
1131 status & PPIDL0SR_STPST,
1132 2000, 50000, false, dsi, PPIDL0SR);
1133 if (ret < 0) {
1134 dev_err(dsi->dev, "Command RX STPST timeout (0x%08x)\n", status);
1135 return ret;
1136 }
1137
1138 return 0;
1139 }
1140
rcar_mipi_dsi_host_transfer(struct mipi_dsi_host * host,const struct mipi_dsi_msg * msg)1141 static ssize_t rcar_mipi_dsi_host_transfer(struct mipi_dsi_host *host,
1142 const struct mipi_dsi_msg *msg)
1143 {
1144 const bool is_rx_xfer = (msg->flags & MIPI_DSI_MSG_REQ_ACK) || msg->rx_len;
1145 struct rcar_mipi_dsi *dsi = host_to_rcar_mipi_dsi(host);
1146 int ret;
1147
1148 if (msg->tx_len > 16 || msg->rx_len > 16) {
1149 /* ToDo: Implement Memory on AXI bus command mode. */
1150 dev_warn(dsi->dev,
1151 "Register-based command mode supports only up to 16 Bytes long payload\n");
1152 return -EOPNOTSUPP;
1153 }
1154
1155 ret = rcar_mipi_dsi_host_tx_transfer(host, msg, is_rx_xfer);
1156
1157 /* If TX transfer succeeded and this transfer has RX part. */
1158 if (ret >= 0 && is_rx_xfer) {
1159 ret = rcar_mipi_dsi_host_rx_transfer(host, msg);
1160 if (ret)
1161 return ret;
1162
1163 ret = msg->rx_len;
1164 }
1165
1166 /*
1167 * Wait a bit between commands, otherwise panels based on ILI9881C
1168 * TCON may fail to correctly receive all commands sent to them.
1169 * Until we can actually test with another DSI device, keep the
1170 * delay here, but eventually this delay might have to be moved
1171 * into the ILI9881C panel driver.
1172 */
1173 usleep_range(1000, 2000);
1174
1175 /* Clear the completion interrupt. */
1176 if (!msg->rx_len)
1177 rcar_mipi_dsi_write(dsi, TXCMSR, TXCMSR_TXREQEND);
1178
1179 return ret;
1180 }
1181
1182 static const struct mipi_dsi_host_ops rcar_mipi_dsi_host_ops = {
1183 .attach = rcar_mipi_dsi_host_attach,
1184 .detach = rcar_mipi_dsi_host_detach,
1185 .transfer = rcar_mipi_dsi_host_transfer
1186 };
1187
1188 /* -----------------------------------------------------------------------------
1189 * Probe & Remove
1190 */
1191
rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi * dsi)1192 static int rcar_mipi_dsi_parse_dt(struct rcar_mipi_dsi *dsi)
1193 {
1194 int ret;
1195
1196 ret = drm_of_get_data_lanes_count_ep(dsi->dev->of_node, 1, 0, 1, 4);
1197 if (ret < 0) {
1198 dev_err(dsi->dev, "missing or invalid data-lanes property\n");
1199 return ret;
1200 }
1201
1202 dsi->num_data_lanes = ret;
1203 return 0;
1204 }
1205
rcar_mipi_dsi_get_clock(struct rcar_mipi_dsi * dsi,const char * name,bool optional)1206 static struct clk *rcar_mipi_dsi_get_clock(struct rcar_mipi_dsi *dsi,
1207 const char *name,
1208 bool optional)
1209 {
1210 struct clk *clk;
1211
1212 clk = devm_clk_get(dsi->dev, name);
1213 if (!IS_ERR(clk))
1214 return clk;
1215
1216 if (PTR_ERR(clk) == -ENOENT && optional)
1217 return NULL;
1218
1219 dev_err_probe(dsi->dev, PTR_ERR(clk), "failed to get %s clock\n",
1220 name ? name : "module");
1221
1222 return clk;
1223 }
1224
rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi * dsi)1225 static int rcar_mipi_dsi_get_clocks(struct rcar_mipi_dsi *dsi)
1226 {
1227 dsi->clocks.mod = rcar_mipi_dsi_get_clock(dsi, NULL, false);
1228 if (IS_ERR(dsi->clocks.mod))
1229 return PTR_ERR(dsi->clocks.mod);
1230
1231 dsi->clocks.pll = rcar_mipi_dsi_get_clock(dsi, "pll", true);
1232 if (IS_ERR(dsi->clocks.pll))
1233 return PTR_ERR(dsi->clocks.pll);
1234
1235 dsi->clocks.dsi = rcar_mipi_dsi_get_clock(dsi, "dsi", true);
1236 if (IS_ERR(dsi->clocks.dsi))
1237 return PTR_ERR(dsi->clocks.dsi);
1238
1239 if (!dsi->clocks.pll && !dsi->clocks.dsi) {
1240 dev_err(dsi->dev, "no input clock (pll, dsi)\n");
1241 return -EINVAL;
1242 }
1243
1244 return 0;
1245 }
1246
rcar_mipi_dsi_probe(struct platform_device * pdev)1247 static int rcar_mipi_dsi_probe(struct platform_device *pdev)
1248 {
1249 struct rcar_mipi_dsi *dsi;
1250 int ret;
1251
1252 dsi = devm_drm_bridge_alloc(&pdev->dev, struct rcar_mipi_dsi, bridge,
1253 &rcar_mipi_dsi_bridge_ops);
1254 if (IS_ERR(dsi))
1255 return PTR_ERR(dsi);
1256
1257 platform_set_drvdata(pdev, dsi);
1258
1259 dsi->dev = &pdev->dev;
1260 dsi->info = of_device_get_match_data(&pdev->dev);
1261
1262 ret = rcar_mipi_dsi_parse_dt(dsi);
1263 if (ret < 0)
1264 return ret;
1265
1266 /* Acquire resources. */
1267 dsi->mmio = devm_platform_ioremap_resource(pdev, 0);
1268 if (IS_ERR(dsi->mmio))
1269 return PTR_ERR(dsi->mmio);
1270
1271 ret = rcar_mipi_dsi_get_clocks(dsi);
1272 if (ret < 0)
1273 return ret;
1274
1275 dsi->rstc = devm_reset_control_get(dsi->dev, NULL);
1276 if (IS_ERR(dsi->rstc)) {
1277 dev_err(dsi->dev, "failed to get cpg reset\n");
1278 return PTR_ERR(dsi->rstc);
1279 }
1280
1281 /* Initialize the DSI host. */
1282 dsi->host.dev = dsi->dev;
1283 dsi->host.ops = &rcar_mipi_dsi_host_ops;
1284 ret = mipi_dsi_host_register(&dsi->host);
1285 if (ret < 0)
1286 return ret;
1287
1288 return 0;
1289 }
1290
rcar_mipi_dsi_remove(struct platform_device * pdev)1291 static void rcar_mipi_dsi_remove(struct platform_device *pdev)
1292 {
1293 struct rcar_mipi_dsi *dsi = platform_get_drvdata(pdev);
1294
1295 mipi_dsi_host_unregister(&dsi->host);
1296 }
1297
1298 static const struct rcar_mipi_dsi_device_info v3u_data = {
1299 .model = RCAR_DSI_V3U,
1300 .clk_cfg = dsi_clk_cfg_v3u,
1301 .clockset2_m_offset = 2,
1302 .n_min = 3,
1303 .n_max = 8,
1304 .n_mul = 1,
1305 .fpfd_min = MHZ(2),
1306 .fpfd_max = MHZ(8),
1307 .m_min = 64,
1308 .m_max = 625,
1309 .fout_min = MHZ(320),
1310 .fout_max = MHZ(1250),
1311 };
1312
1313 static const struct rcar_mipi_dsi_device_info v4h_data = {
1314 .model = RCAR_DSI_V4H,
1315 .clk_cfg = dsi_clk_cfg_v4h,
1316 .clockset2_m_offset = 0,
1317 .n_min = 1,
1318 .n_max = 8,
1319 .n_mul = 2,
1320 .fpfd_min = MHZ(8),
1321 .fpfd_max = MHZ(24),
1322 .m_min = 167,
1323 .m_max = 1000,
1324 .fout_min = MHZ(2000),
1325 .fout_max = MHZ(4000),
1326 };
1327
1328 static const struct of_device_id rcar_mipi_dsi_of_table[] = {
1329 { .compatible = "renesas,r8a779a0-dsi-csi2-tx", .data = &v3u_data },
1330 { .compatible = "renesas,r8a779g0-dsi-csi2-tx", .data = &v4h_data },
1331 /* DSI in r8a779h0 is identical to r8a779g0 */
1332 { .compatible = "renesas,r8a779h0-dsi-csi2-tx", .data = &v4h_data },
1333 { }
1334 };
1335
1336 MODULE_DEVICE_TABLE(of, rcar_mipi_dsi_of_table);
1337
1338 static struct platform_driver rcar_mipi_dsi_platform_driver = {
1339 .probe = rcar_mipi_dsi_probe,
1340 .remove = rcar_mipi_dsi_remove,
1341 .driver = {
1342 .name = "rcar-mipi-dsi",
1343 .of_match_table = rcar_mipi_dsi_of_table,
1344 },
1345 };
1346
1347 module_platform_driver(rcar_mipi_dsi_platform_driver);
1348
1349 MODULE_DESCRIPTION("Renesas R-Car MIPI DSI Encoder Driver");
1350 MODULE_LICENSE("GPL");
1351