1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * R-Car Display Unit Mode Setting
4 *
5 * Copyright (C) 2013-2015 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10 #include <drm/drm_atomic.h>
11 #include <drm/drm_atomic_helper.h>
12 #include <drm/drm_crtc.h>
13 #include <drm/drm_device.h>
14 #include <drm/drm_framebuffer.h>
15 #include <drm/drm_gem_dma_helper.h>
16 #include <drm/drm_gem_framebuffer_helper.h>
17 #include <drm/drm_managed.h>
18 #include <drm/drm_probe_helper.h>
19 #include <drm/drm_vblank.h>
20
21 #include <linux/device.h>
22 #include <linux/dma-buf.h>
23 #include <linux/of.h>
24 #include <linux/of_graph.h>
25 #include <linux/of_platform.h>
26 #include <linux/platform_device.h>
27 #include <linux/wait.h>
28
29 #include "rcar_du_crtc.h"
30 #include "rcar_du_drv.h"
31 #include "rcar_du_encoder.h"
32 #include "rcar_du_kms.h"
33 #include "rcar_du_regs.h"
34 #include "rcar_du_vsp.h"
35 #include "rcar_du_writeback.h"
36
37 /* -----------------------------------------------------------------------------
38 * Format helpers
39 */
40
41 static const struct rcar_du_format_info rcar_du_format_infos[] = {
42 {
43 .fourcc = DRM_FORMAT_RGB565,
44 .v4l2 = V4L2_PIX_FMT_RGB565,
45 .bpp = 16,
46 .planes = 1,
47 .hsub = 1,
48 .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
49 .edf = PnDDCR4_EDF_NONE,
50 }, {
51 .fourcc = DRM_FORMAT_ARGB1555,
52 .v4l2 = V4L2_PIX_FMT_ARGB555,
53 .bpp = 16,
54 .planes = 1,
55 .hsub = 1,
56 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
57 .edf = PnDDCR4_EDF_NONE,
58 }, {
59 .fourcc = DRM_FORMAT_XRGB1555,
60 .v4l2 = V4L2_PIX_FMT_XRGB555,
61 .bpp = 16,
62 .planes = 1,
63 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_ARGB,
64 .edf = PnDDCR4_EDF_NONE,
65 }, {
66 .fourcc = DRM_FORMAT_XRGB8888,
67 .v4l2 = V4L2_PIX_FMT_XBGR32,
68 .bpp = 32,
69 .planes = 1,
70 .hsub = 1,
71 .pnmr = PnMR_SPIM_TP | PnMR_DDDF_16BPP,
72 .edf = PnDDCR4_EDF_RGB888,
73 }, {
74 .fourcc = DRM_FORMAT_ARGB8888,
75 .v4l2 = V4L2_PIX_FMT_ABGR32,
76 .bpp = 32,
77 .planes = 1,
78 .hsub = 1,
79 .pnmr = PnMR_SPIM_ALP | PnMR_DDDF_16BPP,
80 .edf = PnDDCR4_EDF_ARGB8888,
81 }, {
82 .fourcc = DRM_FORMAT_UYVY,
83 .v4l2 = V4L2_PIX_FMT_UYVY,
84 .bpp = 16,
85 .planes = 1,
86 .hsub = 2,
87 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
88 .edf = PnDDCR4_EDF_NONE,
89 }, {
90 .fourcc = DRM_FORMAT_YUYV,
91 .v4l2 = V4L2_PIX_FMT_YUYV,
92 .bpp = 16,
93 .planes = 1,
94 .hsub = 2,
95 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
96 .edf = PnDDCR4_EDF_NONE,
97 }, {
98 .fourcc = DRM_FORMAT_NV12,
99 .v4l2 = V4L2_PIX_FMT_NV12M,
100 .bpp = 12,
101 .planes = 2,
102 .hsub = 2,
103 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
104 .edf = PnDDCR4_EDF_NONE,
105 }, {
106 .fourcc = DRM_FORMAT_NV21,
107 .v4l2 = V4L2_PIX_FMT_NV21M,
108 .bpp = 12,
109 .planes = 2,
110 .hsub = 2,
111 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
112 .edf = PnDDCR4_EDF_NONE,
113 }, {
114 .fourcc = DRM_FORMAT_NV16,
115 .v4l2 = V4L2_PIX_FMT_NV16M,
116 .bpp = 16,
117 .planes = 2,
118 .hsub = 2,
119 .pnmr = PnMR_SPIM_TP_OFF | PnMR_DDDF_YC,
120 .edf = PnDDCR4_EDF_NONE,
121 },
122 /*
123 * The following formats are not supported on Gen2 and thus have no
124 * associated .pnmr or .edf settings.
125 */
126 {
127 .fourcc = DRM_FORMAT_RGB332,
128 .v4l2 = V4L2_PIX_FMT_RGB332,
129 .bpp = 8,
130 .planes = 1,
131 .hsub = 1,
132 }, {
133 .fourcc = DRM_FORMAT_ARGB4444,
134 .v4l2 = V4L2_PIX_FMT_ARGB444,
135 .bpp = 16,
136 .planes = 1,
137 .hsub = 1,
138 }, {
139 .fourcc = DRM_FORMAT_XRGB4444,
140 .v4l2 = V4L2_PIX_FMT_XRGB444,
141 .bpp = 16,
142 .planes = 1,
143 .hsub = 1,
144 }, {
145 .fourcc = DRM_FORMAT_RGBA4444,
146 .v4l2 = V4L2_PIX_FMT_RGBA444,
147 .bpp = 16,
148 .planes = 1,
149 .hsub = 1,
150 }, {
151 .fourcc = DRM_FORMAT_RGBX4444,
152 .v4l2 = V4L2_PIX_FMT_RGBX444,
153 .bpp = 16,
154 .planes = 1,
155 .hsub = 1,
156 }, {
157 .fourcc = DRM_FORMAT_ABGR4444,
158 .v4l2 = V4L2_PIX_FMT_ABGR444,
159 .bpp = 16,
160 .planes = 1,
161 .hsub = 1,
162 }, {
163 .fourcc = DRM_FORMAT_XBGR4444,
164 .v4l2 = V4L2_PIX_FMT_XBGR444,
165 .bpp = 16,
166 .planes = 1,
167 .hsub = 1,
168 }, {
169 .fourcc = DRM_FORMAT_BGRA4444,
170 .v4l2 = V4L2_PIX_FMT_BGRA444,
171 .bpp = 16,
172 .planes = 1,
173 .hsub = 1,
174 }, {
175 .fourcc = DRM_FORMAT_BGRX4444,
176 .v4l2 = V4L2_PIX_FMT_BGRX444,
177 .bpp = 16,
178 .planes = 1,
179 .hsub = 1,
180 }, {
181 .fourcc = DRM_FORMAT_RGBA5551,
182 .v4l2 = V4L2_PIX_FMT_RGBA555,
183 .bpp = 16,
184 .planes = 1,
185 .hsub = 1,
186 }, {
187 .fourcc = DRM_FORMAT_RGBX5551,
188 .v4l2 = V4L2_PIX_FMT_RGBX555,
189 .bpp = 16,
190 .planes = 1,
191 .hsub = 1,
192 }, {
193 .fourcc = DRM_FORMAT_ABGR1555,
194 .v4l2 = V4L2_PIX_FMT_ABGR555,
195 .bpp = 16,
196 .planes = 1,
197 .hsub = 1,
198 }, {
199 .fourcc = DRM_FORMAT_XBGR1555,
200 .v4l2 = V4L2_PIX_FMT_XBGR555,
201 .bpp = 16,
202 .planes = 1,
203 .hsub = 1,
204 }, {
205 .fourcc = DRM_FORMAT_BGRA5551,
206 .v4l2 = V4L2_PIX_FMT_BGRA555,
207 .bpp = 16,
208 .planes = 1,
209 .hsub = 1,
210 }, {
211 .fourcc = DRM_FORMAT_BGRX5551,
212 .v4l2 = V4L2_PIX_FMT_BGRX555,
213 .bpp = 16,
214 .planes = 1,
215 .hsub = 1,
216 }, {
217 .fourcc = DRM_FORMAT_BGR888,
218 .v4l2 = V4L2_PIX_FMT_RGB24,
219 .bpp = 24,
220 .planes = 1,
221 .hsub = 1,
222 }, {
223 .fourcc = DRM_FORMAT_RGB888,
224 .v4l2 = V4L2_PIX_FMT_BGR24,
225 .bpp = 24,
226 .planes = 1,
227 .hsub = 1,
228 }, {
229 .fourcc = DRM_FORMAT_RGBA8888,
230 .v4l2 = V4L2_PIX_FMT_BGRA32,
231 .bpp = 32,
232 .planes = 1,
233 .hsub = 1,
234 }, {
235 .fourcc = DRM_FORMAT_RGBX8888,
236 .v4l2 = V4L2_PIX_FMT_BGRX32,
237 .bpp = 32,
238 .planes = 1,
239 .hsub = 1,
240 }, {
241 .fourcc = DRM_FORMAT_ABGR8888,
242 .v4l2 = V4L2_PIX_FMT_RGBA32,
243 .bpp = 32,
244 .planes = 1,
245 .hsub = 1,
246 }, {
247 .fourcc = DRM_FORMAT_XBGR8888,
248 .v4l2 = V4L2_PIX_FMT_RGBX32,
249 .bpp = 32,
250 .planes = 1,
251 .hsub = 1,
252 }, {
253 .fourcc = DRM_FORMAT_BGRA8888,
254 .v4l2 = V4L2_PIX_FMT_ARGB32,
255 .bpp = 32,
256 .planes = 1,
257 .hsub = 1,
258 }, {
259 .fourcc = DRM_FORMAT_BGRX8888,
260 .v4l2 = V4L2_PIX_FMT_XRGB32,
261 .bpp = 32,
262 .planes = 1,
263 .hsub = 1,
264 }, {
265 .fourcc = DRM_FORMAT_RGBX1010102,
266 .v4l2 = V4L2_PIX_FMT_RGBX1010102,
267 .bpp = 32,
268 .planes = 1,
269 .hsub = 1,
270 }, {
271 .fourcc = DRM_FORMAT_RGBA1010102,
272 .v4l2 = V4L2_PIX_FMT_RGBA1010102,
273 .bpp = 32,
274 .planes = 1,
275 .hsub = 1,
276 }, {
277 .fourcc = DRM_FORMAT_ARGB2101010,
278 .v4l2 = V4L2_PIX_FMT_ARGB2101010,
279 .bpp = 32,
280 .planes = 1,
281 .hsub = 1,
282 }, {
283 .fourcc = DRM_FORMAT_YVYU,
284 .v4l2 = V4L2_PIX_FMT_YVYU,
285 .bpp = 16,
286 .planes = 1,
287 .hsub = 2,
288 }, {
289 .fourcc = DRM_FORMAT_NV61,
290 .v4l2 = V4L2_PIX_FMT_NV61M,
291 .bpp = 16,
292 .planes = 2,
293 .hsub = 2,
294 }, {
295 .fourcc = DRM_FORMAT_YUV420,
296 .v4l2 = V4L2_PIX_FMT_YUV420M,
297 .bpp = 12,
298 .planes = 3,
299 .hsub = 2,
300 }, {
301 .fourcc = DRM_FORMAT_YVU420,
302 .v4l2 = V4L2_PIX_FMT_YVU420M,
303 .bpp = 12,
304 .planes = 3,
305 .hsub = 2,
306 }, {
307 .fourcc = DRM_FORMAT_YUV422,
308 .v4l2 = V4L2_PIX_FMT_YUV422M,
309 .bpp = 16,
310 .planes = 3,
311 .hsub = 2,
312 }, {
313 .fourcc = DRM_FORMAT_YVU422,
314 .v4l2 = V4L2_PIX_FMT_YVU422M,
315 .bpp = 16,
316 .planes = 3,
317 .hsub = 2,
318 }, {
319 .fourcc = DRM_FORMAT_YUV444,
320 .v4l2 = V4L2_PIX_FMT_YUV444M,
321 .bpp = 24,
322 .planes = 3,
323 .hsub = 1,
324 }, {
325 .fourcc = DRM_FORMAT_YVU444,
326 .v4l2 = V4L2_PIX_FMT_YVU444M,
327 .bpp = 24,
328 .planes = 3,
329 .hsub = 1,
330 }, {
331 .fourcc = DRM_FORMAT_Y210,
332 .v4l2 = V4L2_PIX_FMT_Y210,
333 .bpp = 32,
334 .planes = 1,
335 .hsub = 2,
336 }, {
337 .fourcc = DRM_FORMAT_Y212,
338 .v4l2 = V4L2_PIX_FMT_Y212,
339 .bpp = 32,
340 .planes = 1,
341 .hsub = 2,
342 },
343 };
344
rcar_du_format_info(u32 fourcc)345 const struct rcar_du_format_info *rcar_du_format_info(u32 fourcc)
346 {
347 unsigned int i;
348
349 for (i = 0; i < ARRAY_SIZE(rcar_du_format_infos); ++i) {
350 if (rcar_du_format_infos[i].fourcc == fourcc)
351 return &rcar_du_format_infos[i];
352 }
353
354 return NULL;
355 }
356
357 /* -----------------------------------------------------------------------------
358 * Frame buffer
359 */
360
361 static const struct drm_gem_object_funcs rcar_du_gem_funcs = {
362 .free = drm_gem_dma_object_free,
363 .print_info = drm_gem_dma_object_print_info,
364 .get_sg_table = drm_gem_dma_object_get_sg_table,
365 .vmap = drm_gem_dma_object_vmap,
366 .mmap = drm_gem_dma_object_mmap,
367 .vm_ops = &drm_gem_dma_vm_ops,
368 };
369
rcar_du_gem_prime_import_sg_table(struct drm_device * dev,struct dma_buf_attachment * attach,struct sg_table * sgt)370 struct drm_gem_object *rcar_du_gem_prime_import_sg_table(struct drm_device *dev,
371 struct dma_buf_attachment *attach,
372 struct sg_table *sgt)
373 {
374 struct rcar_du_device *rcdu = to_rcar_du_device(dev);
375 struct drm_gem_dma_object *dma_obj;
376 struct drm_gem_object *gem_obj;
377 int ret;
378
379 if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
380 return drm_gem_dma_prime_import_sg_table(dev, attach, sgt);
381
382 /* Create a DMA GEM buffer. */
383 dma_obj = kzalloc(sizeof(*dma_obj), GFP_KERNEL);
384 if (!dma_obj)
385 return ERR_PTR(-ENOMEM);
386
387 gem_obj = &dma_obj->base;
388 gem_obj->funcs = &rcar_du_gem_funcs;
389
390 drm_gem_private_object_init(dev, gem_obj, attach->dmabuf->size);
391 dma_obj->map_noncoherent = false;
392
393 ret = drm_gem_create_mmap_offset(gem_obj);
394 if (ret) {
395 drm_gem_object_release(gem_obj);
396 kfree(dma_obj);
397 return ERR_PTR(ret);
398 }
399
400 dma_obj->dma_addr = 0;
401 dma_obj->sgt = sgt;
402
403 return gem_obj;
404 }
405
rcar_du_dumb_create(struct drm_file * file,struct drm_device * dev,struct drm_mode_create_dumb * args)406 int rcar_du_dumb_create(struct drm_file *file, struct drm_device *dev,
407 struct drm_mode_create_dumb *args)
408 {
409 struct rcar_du_device *rcdu = to_rcar_du_device(dev);
410 unsigned int min_pitch = DIV_ROUND_UP(args->width * args->bpp, 8);
411 unsigned int align;
412
413 /*
414 * The R8A7779 DU requires a 16 pixels pitch alignment as documented,
415 * but the R8A7790 DU seems to require a 128 bytes pitch alignment.
416 */
417 if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
418 align = 128;
419 else
420 align = 16 * args->bpp / 8;
421
422 args->pitch = roundup(min_pitch, align);
423
424 return drm_gem_dma_dumb_create_internal(file, dev, args);
425 }
426
427 static struct drm_framebuffer *
rcar_du_fb_create(struct drm_device * dev,struct drm_file * file_priv,const struct drm_format_info * info,const struct drm_mode_fb_cmd2 * mode_cmd)428 rcar_du_fb_create(struct drm_device *dev, struct drm_file *file_priv,
429 const struct drm_format_info *info,
430 const struct drm_mode_fb_cmd2 *mode_cmd)
431 {
432 struct rcar_du_device *rcdu = to_rcar_du_device(dev);
433 const struct rcar_du_format_info *format;
434 unsigned int chroma_pitch;
435 unsigned int max_pitch;
436 unsigned int align;
437 unsigned int i;
438
439 format = rcar_du_format_info(mode_cmd->pixel_format);
440 if (format == NULL) {
441 dev_dbg(dev->dev, "unsupported pixel format %p4cc\n",
442 &mode_cmd->pixel_format);
443 return ERR_PTR(-EINVAL);
444 }
445
446 if (rcdu->info->gen < 3) {
447 /*
448 * On Gen2 the DU limits the pitch to 4095 pixels and requires
449 * buffers to be aligned to a 16 pixels boundary (or 128 bytes
450 * on some platforms).
451 */
452 unsigned int bpp = format->planes == 1 ? format->bpp / 8 : 1;
453
454 max_pitch = 4095 * bpp;
455
456 if (rcar_du_needs(rcdu, RCAR_DU_QUIRK_ALIGN_128B))
457 align = 128;
458 else
459 align = 16 * bpp;
460 } else {
461 /*
462 * On Gen3 the memory interface is handled by the VSP that
463 * limits the pitch to 65535 bytes and has no alignment
464 * constraint.
465 */
466 max_pitch = 65535;
467 align = 1;
468 }
469
470 if (mode_cmd->pitches[0] & (align - 1) ||
471 mode_cmd->pitches[0] > max_pitch) {
472 dev_dbg(dev->dev, "invalid pitch value %u\n",
473 mode_cmd->pitches[0]);
474 return ERR_PTR(-EINVAL);
475 }
476
477 /*
478 * Calculate the chroma plane(s) pitch using the horizontal subsampling
479 * factor. For semi-planar formats, the U and V planes are combined, the
480 * pitch must thus be doubled.
481 */
482 chroma_pitch = mode_cmd->pitches[0] / format->hsub;
483 if (format->planes == 2)
484 chroma_pitch *= 2;
485
486 for (i = 1; i < format->planes; ++i) {
487 if (mode_cmd->pitches[i] != chroma_pitch) {
488 dev_dbg(dev->dev,
489 "luma and chroma pitches are not compatible\n");
490 return ERR_PTR(-EINVAL);
491 }
492 }
493
494 return drm_gem_fb_create(dev, file_priv, info, mode_cmd);
495 }
496
497 /* -----------------------------------------------------------------------------
498 * Atomic Check and Update
499 */
500
rcar_du_atomic_check(struct drm_device * dev,struct drm_atomic_state * state)501 static int rcar_du_atomic_check(struct drm_device *dev,
502 struct drm_atomic_state *state)
503 {
504 struct rcar_du_device *rcdu = to_rcar_du_device(dev);
505 int ret;
506
507 ret = drm_atomic_helper_check(dev, state);
508 if (ret)
509 return ret;
510
511 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
512 return 0;
513
514 return rcar_du_atomic_check_planes(dev, state);
515 }
516
rcar_du_atomic_commit_tail(struct drm_atomic_state * old_state)517 static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
518 {
519 struct drm_device *dev = old_state->dev;
520 struct rcar_du_device *rcdu = to_rcar_du_device(dev);
521 struct drm_crtc_state *crtc_state;
522 struct drm_crtc *crtc;
523 unsigned int i;
524
525 /*
526 * Store RGB routing to DPAD0 and DPAD1, the hardware will be configured
527 * when starting the CRTCs.
528 */
529 rcdu->dpad1_source = -1;
530
531 for_each_new_crtc_in_state(old_state, crtc, crtc_state, i) {
532 struct rcar_du_crtc_state *rcrtc_state =
533 to_rcar_crtc_state(crtc_state);
534 struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
535
536 if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD0))
537 rcdu->dpad0_source = rcrtc->index;
538
539 if (rcrtc_state->outputs & BIT(RCAR_DU_OUTPUT_DPAD1))
540 rcdu->dpad1_source = rcrtc->index;
541 }
542
543 /* Apply the atomic update. */
544 drm_atomic_helper_commit_modeset_disables(dev, old_state);
545 drm_atomic_helper_commit_planes(dev, old_state,
546 DRM_PLANE_COMMIT_ACTIVE_ONLY);
547 drm_atomic_helper_commit_modeset_enables(dev, old_state);
548
549 drm_atomic_helper_commit_hw_done(old_state);
550 drm_atomic_helper_wait_for_flip_done(dev, old_state);
551
552 drm_atomic_helper_cleanup_planes(dev, old_state);
553 }
554
555 /* -----------------------------------------------------------------------------
556 * Initialization
557 */
558
559 static const struct drm_mode_config_helper_funcs rcar_du_mode_config_helper = {
560 .atomic_commit_tail = rcar_du_atomic_commit_tail,
561 };
562
563 static const struct drm_mode_config_funcs rcar_du_mode_config_funcs = {
564 .fb_create = rcar_du_fb_create,
565 .atomic_check = rcar_du_atomic_check,
566 .atomic_commit = drm_atomic_helper_commit,
567 };
568
rcar_du_encoders_init_one(struct rcar_du_device * rcdu,enum rcar_du_output output,struct of_endpoint * ep)569 static int rcar_du_encoders_init_one(struct rcar_du_device *rcdu,
570 enum rcar_du_output output,
571 struct of_endpoint *ep)
572 {
573 struct device_node *entity;
574 int ret;
575
576 /* Locate the connected entity and initialize the encoder. */
577 entity = of_graph_get_remote_port_parent(ep->local_node);
578 if (!entity) {
579 dev_dbg(rcdu->dev, "unconnected endpoint %pOF, skipping\n",
580 ep->local_node);
581 return -ENODEV;
582 }
583
584 if (!of_device_is_available(entity)) {
585 dev_dbg(rcdu->dev,
586 "connected entity %pOF is disabled, skipping\n",
587 entity);
588 of_node_put(entity);
589 return -ENODEV;
590 }
591
592 ret = rcar_du_encoder_init(rcdu, output, entity);
593 if (ret && ret != -EPROBE_DEFER && ret != -ENOLINK)
594 dev_warn(rcdu->dev,
595 "failed to initialize encoder %pOF on output %s (%d), skipping\n",
596 entity, rcar_du_output_name(output), ret);
597
598 of_node_put(entity);
599
600 return ret;
601 }
602
rcar_du_encoders_init(struct rcar_du_device * rcdu)603 static int rcar_du_encoders_init(struct rcar_du_device *rcdu)
604 {
605 struct device_node *np = rcdu->dev->of_node;
606 struct device_node *ep_node;
607 unsigned int num_encoders = 0;
608
609 /*
610 * Iterate over the endpoints and create one encoder for each output
611 * pipeline.
612 */
613 for_each_endpoint_of_node(np, ep_node) {
614 enum rcar_du_output output;
615 struct of_endpoint ep;
616 unsigned int i;
617 int ret;
618
619 ret = of_graph_parse_endpoint(ep_node, &ep);
620 if (ret < 0) {
621 of_node_put(ep_node);
622 return ret;
623 }
624
625 /* Find the output route corresponding to the port number. */
626 for (i = 0; i < RCAR_DU_OUTPUT_MAX; ++i) {
627 if (rcdu->info->routes[i].possible_crtcs &&
628 rcdu->info->routes[i].port == ep.port) {
629 output = i;
630 break;
631 }
632 }
633
634 if (i == RCAR_DU_OUTPUT_MAX) {
635 dev_warn(rcdu->dev,
636 "port %u references unexisting output, skipping\n",
637 ep.port);
638 continue;
639 }
640
641 /* Process the output pipeline. */
642 ret = rcar_du_encoders_init_one(rcdu, output, &ep);
643 if (ret < 0) {
644 if (ret == -EPROBE_DEFER) {
645 of_node_put(ep_node);
646 return ret;
647 }
648
649 continue;
650 }
651
652 num_encoders++;
653 }
654
655 return num_encoders;
656 }
657
rcar_du_properties_init(struct rcar_du_device * rcdu)658 static int rcar_du_properties_init(struct rcar_du_device *rcdu)
659 {
660 /*
661 * The color key is expressed as an RGB888 triplet stored in a 32-bit
662 * integer in XRGB8888 format. Bit 24 is used as a flag to disable (0)
663 * or enable source color keying (1).
664 */
665 rcdu->props.colorkey =
666 drm_property_create_range(&rcdu->ddev, 0, "colorkey",
667 0, 0x01ffffff);
668 if (rcdu->props.colorkey == NULL)
669 return -ENOMEM;
670
671 return 0;
672 }
673
rcar_du_vsps_init(struct rcar_du_device * rcdu)674 static int rcar_du_vsps_init(struct rcar_du_device *rcdu)
675 {
676 const struct device_node *np = rcdu->dev->of_node;
677 const char *vsps_prop_name = "renesas,vsps";
678 struct of_phandle_args args;
679 struct {
680 struct device_node *np;
681 unsigned int crtcs_mask;
682 } vsps[RCAR_DU_MAX_VSPS] = { { NULL, }, };
683 unsigned int vsps_count = 0;
684 unsigned int cells;
685 unsigned int i;
686 int ret;
687
688 /*
689 * First parse the DT vsps property to populate the list of VSPs. Each
690 * entry contains a pointer to the VSP DT node and a bitmask of the
691 * connected DU CRTCs.
692 */
693 ret = of_property_count_u32_elems(np, vsps_prop_name);
694 if (ret < 0) {
695 /* Backward compatibility with old DTBs. */
696 vsps_prop_name = "vsps";
697 ret = of_property_count_u32_elems(np, vsps_prop_name);
698 }
699 cells = ret / rcdu->num_crtcs - 1;
700 if (cells > 1)
701 return -EINVAL;
702
703 for (i = 0; i < rcdu->num_crtcs; ++i) {
704 unsigned int j;
705
706 ret = of_parse_phandle_with_fixed_args(np, vsps_prop_name,
707 cells, i, &args);
708 if (ret < 0)
709 goto done;
710
711 /*
712 * Add the VSP to the list or update the corresponding existing
713 * entry if the VSP has already been added.
714 */
715 for (j = 0; j < vsps_count; ++j) {
716 if (vsps[j].np == args.np)
717 break;
718 }
719
720 if (j < vsps_count)
721 of_node_put(args.np);
722 else
723 vsps[vsps_count++].np = args.np;
724
725 vsps[j].crtcs_mask |= BIT(i);
726
727 /*
728 * Store the VSP pointer and pipe index in the CRTC. If the
729 * second cell of the 'renesas,vsps' specifier isn't present,
730 * default to 0 to remain compatible with older DT bindings.
731 */
732 rcdu->crtcs[i].vsp = &rcdu->vsps[j];
733 rcdu->crtcs[i].vsp_pipe = cells >= 1 ? args.args[0] : 0;
734 }
735
736 /*
737 * Then initialize all the VSPs from the node pointers and CRTCs bitmask
738 * computed previously.
739 */
740 for (i = 0; i < vsps_count; ++i) {
741 struct rcar_du_vsp *vsp = &rcdu->vsps[i];
742
743 vsp->index = i;
744 vsp->dev = rcdu;
745
746 ret = rcar_du_vsp_init(vsp, vsps[i].np, vsps[i].crtcs_mask);
747 if (ret)
748 goto done;
749 }
750
751 done:
752 for (i = 0; i < ARRAY_SIZE(vsps); ++i)
753 of_node_put(vsps[i].np);
754
755 return ret;
756 }
757
rcar_du_cmm_init(struct rcar_du_device * rcdu)758 static int rcar_du_cmm_init(struct rcar_du_device *rcdu)
759 {
760 const struct device_node *np = rcdu->dev->of_node;
761 unsigned int i;
762 int cells;
763
764 cells = of_property_count_u32_elems(np, "renesas,cmms");
765 if (cells == -EINVAL)
766 return 0;
767
768 if (cells > rcdu->num_crtcs) {
769 dev_err(rcdu->dev,
770 "Invalid number of entries in 'renesas,cmms'\n");
771 return -EINVAL;
772 }
773
774 for (i = 0; i < cells; ++i) {
775 struct platform_device *pdev;
776 struct device_link *link;
777 struct device_node *cmm;
778 int ret;
779
780 cmm = of_parse_phandle(np, "renesas,cmms", i);
781 if (!cmm) {
782 dev_err(rcdu->dev,
783 "Failed to parse 'renesas,cmms' property\n");
784 return -EINVAL;
785 }
786
787 if (!of_device_is_available(cmm)) {
788 /* It's fine to have a phandle to a non-enabled CMM. */
789 of_node_put(cmm);
790 continue;
791 }
792
793 pdev = of_find_device_by_node(cmm);
794 if (!pdev) {
795 dev_err(rcdu->dev, "No device found for CMM%u\n", i);
796 of_node_put(cmm);
797 return -EINVAL;
798 }
799
800 of_node_put(cmm);
801
802 /*
803 * -ENODEV is used to report that the CMM config option is
804 * disabled: return 0 and let the DU continue probing.
805 */
806 ret = rcar_cmm_init(pdev);
807 if (ret) {
808 platform_device_put(pdev);
809 return ret == -ENODEV ? 0 : ret;
810 }
811
812 rcdu->cmms[i] = pdev;
813
814 /*
815 * Enforce suspend/resume ordering by making the CMM a provider
816 * of the DU: CMM is suspended after and resumed before the DU.
817 */
818 link = device_link_add(rcdu->dev, &pdev->dev, DL_FLAG_STATELESS);
819 if (!link) {
820 dev_err(rcdu->dev,
821 "Failed to create device link to CMM%u\n", i);
822 return -EINVAL;
823 }
824 }
825
826 return 0;
827 }
828
rcar_du_modeset_cleanup(struct drm_device * dev,void * res)829 static void rcar_du_modeset_cleanup(struct drm_device *dev, void *res)
830 {
831 struct rcar_du_device *rcdu = to_rcar_du_device(dev);
832 unsigned int i;
833
834 for (i = 0; i < ARRAY_SIZE(rcdu->cmms); ++i)
835 platform_device_put(rcdu->cmms[i]);
836 }
837
rcar_du_modeset_init(struct rcar_du_device * rcdu)838 int rcar_du_modeset_init(struct rcar_du_device *rcdu)
839 {
840 static const unsigned int mmio_offsets[] = {
841 DU0_REG_OFFSET, DU2_REG_OFFSET
842 };
843
844 struct drm_device *dev = &rcdu->ddev;
845 struct drm_encoder *encoder;
846 unsigned int dpad0_sources;
847 unsigned int num_encoders;
848 unsigned int num_groups;
849 unsigned int swindex;
850 unsigned int hwindex;
851 unsigned int i;
852 int ret;
853
854 ret = drmm_mode_config_init(dev);
855 if (ret)
856 return ret;
857
858 ret = drmm_add_action(&rcdu->ddev, rcar_du_modeset_cleanup, NULL);
859 if (ret)
860 return ret;
861
862 dev->mode_config.min_width = 0;
863 dev->mode_config.min_height = 0;
864 dev->mode_config.normalize_zpos = true;
865 dev->mode_config.funcs = &rcar_du_mode_config_funcs;
866 dev->mode_config.helper_private = &rcar_du_mode_config_helper;
867
868 if (rcdu->info->gen < 3) {
869 dev->mode_config.max_width = 4095;
870 dev->mode_config.max_height = 2047;
871 } else {
872 /*
873 * The Gen3 DU uses the VSP1 for memory access, and is limited
874 * to frame sizes of 8190x8190.
875 */
876 dev->mode_config.max_width = 8190;
877 dev->mode_config.max_height = 8190;
878 }
879
880 rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
881
882 ret = rcar_du_properties_init(rcdu);
883 if (ret < 0)
884 return ret;
885
886 /*
887 * Initialize vertical blanking interrupts handling. Start with vblank
888 * disabled for all CRTCs.
889 */
890 ret = drm_vblank_init(dev, rcdu->num_crtcs);
891 if (ret < 0)
892 return ret;
893
894 /* Initialize the groups. */
895 num_groups = DIV_ROUND_UP(rcdu->num_crtcs, 2);
896
897 for (i = 0; i < num_groups; ++i) {
898 struct rcar_du_group *rgrp = &rcdu->groups[i];
899
900 mutex_init(&rgrp->lock);
901
902 rgrp->dev = rcdu;
903 rgrp->mmio_offset = mmio_offsets[i];
904 rgrp->index = i;
905 /* Extract the channel mask for this group only. */
906 rgrp->channels_mask = (rcdu->info->channels_mask >> (2 * i))
907 & GENMASK(1, 0);
908 rgrp->num_crtcs = hweight8(rgrp->channels_mask);
909
910 /*
911 * If we have more than one CRTCs in this group pre-associate
912 * the low-order planes with CRTC 0 and the high-order planes
913 * with CRTC 1 to minimize flicker occurring when the
914 * association is changed.
915 */
916 rgrp->dptsr_planes = rgrp->num_crtcs > 1
917 ? (rcdu->info->gen >= 3 ? 0x04 : 0xf0)
918 : 0;
919
920 if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
921 ret = rcar_du_planes_init(rgrp);
922 if (ret < 0)
923 return ret;
924 }
925 }
926
927 /* Initialize the compositors. */
928 if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
929 ret = rcar_du_vsps_init(rcdu);
930 if (ret < 0)
931 return ret;
932 }
933
934 /* Initialize the Color Management Modules. */
935 ret = rcar_du_cmm_init(rcdu);
936 if (ret)
937 return dev_err_probe(rcdu->dev, ret,
938 "failed to initialize CMM\n");
939
940 /* Create the CRTCs. */
941 for (swindex = 0, hwindex = 0; swindex < rcdu->num_crtcs; ++hwindex) {
942 struct rcar_du_group *rgrp;
943
944 /* Skip unpopulated DU channels. */
945 if (!(rcdu->info->channels_mask & BIT(hwindex)))
946 continue;
947
948 rgrp = &rcdu->groups[hwindex / 2];
949
950 ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
951 if (ret < 0)
952 return ret;
953 }
954
955 /* Initialize the encoders. */
956 ret = rcar_du_encoders_init(rcdu);
957 if (ret < 0)
958 return dev_err_probe(rcdu->dev, ret,
959 "failed to initialize encoders\n");
960
961 if (ret == 0) {
962 dev_err(rcdu->dev, "error: no encoder could be initialized\n");
963 return -EINVAL;
964 }
965
966 num_encoders = ret;
967
968 /*
969 * Set the possible CRTCs and possible clones. There's always at least
970 * one way for all encoders to clone each other, set all bits in the
971 * possible clones field.
972 */
973 list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
974 struct rcar_du_encoder *renc = to_rcar_encoder(encoder);
975 const struct rcar_du_output_routing *route =
976 &rcdu->info->routes[renc->output];
977
978 encoder->possible_crtcs = route->possible_crtcs;
979 encoder->possible_clones = (1 << num_encoders) - 1;
980 }
981
982 /* Create the writeback connectors. */
983 if (rcdu->info->gen >= 3) {
984 for (i = 0; i < rcdu->num_crtcs; ++i) {
985 struct rcar_du_crtc *rcrtc = &rcdu->crtcs[i];
986
987 ret = rcar_du_writeback_init(rcdu, rcrtc);
988 if (ret < 0)
989 return ret;
990 }
991 }
992
993 /*
994 * Initialize the default DPAD0 source to the index of the first DU
995 * channel that can be connected to DPAD0. The exact value doesn't
996 * matter as it should be overwritten by mode setting for the RGB
997 * output, but it is nonetheless required to ensure a valid initial
998 * hardware configuration on Gen3 where DU0 can't always be connected to
999 * DPAD0.
1000 */
1001 dpad0_sources = rcdu->info->routes[RCAR_DU_OUTPUT_DPAD0].possible_crtcs;
1002 rcdu->dpad0_source = ffs(dpad0_sources) - 1;
1003
1004 drm_mode_config_reset(dev);
1005
1006 drm_kms_helper_poll_init(dev);
1007
1008 return 0;
1009 }
1010