1 /* 2 * Copyright 2025 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 */ 23 #include <linux/delay.h> 24 #include <linux/kernel.h> 25 #include <linux/firmware.h> 26 #include <linux/module.h> 27 #include <linux/pci.h> 28 #include "amdgpu.h" 29 #include "amdgpu_gfx.h" 30 #include "amdgpu_psp.h" 31 #include "amdgpu_smu.h" 32 #include "amdgpu_atomfirmware.h" 33 #include "amdgpu_userq_fence.h" 34 #include "imu_v12_1.h" 35 #include "soc_v1_0.h" 36 #include "gfx_v12_1_pkt.h" 37 38 #include "gc/gc_12_1_0_offset.h" 39 #include "gc/gc_12_1_0_sh_mask.h" 40 #include "soc24_enum.h" 41 #include "ivsrcid/gfx/irqsrcs_gfx_12_1_0.h" 42 43 #include "soc15.h" 44 #include "clearstate_gfx12.h" 45 #include "v12_structs.h" 46 #include "gfx_v12_1.h" 47 #include "mes_v12_1.h" 48 #include "amdgpu_ras_mgr.h" 49 50 #define GFX12_MEC_HPD_SIZE 2048 51 #define NUM_SIMD_PER_CU_GFX12_1 4 52 53 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L 54 55 #define regCP_HQD_EOP_CONTROL_DEFAULT 0x00000000 56 #define regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT 0x00000000 57 #define regCP_MQD_CONTROL_DEFAULT 0x00000100 58 #define regCP_HQD_PQ_CONTROL_DEFAULT 0x00308509 59 #define regCP_HQD_PQ_RPTR_DEFAULT 0x00000000 60 #define regCP_HQD_PERSISTENT_STATE_DEFAULT 0x0ae06301 61 #define regCP_HQD_IB_CONTROL_DEFAULT 0x00100000 62 63 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mec.bin"); 64 MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc.bin"); 65 MODULE_FIRMWARE("amdgpu/gc_12_1_0_mec_1.bin"); 66 MODULE_FIRMWARE("amdgpu/gc_12_1_0_rlc_1.bin"); 67 68 #define SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 0x00000001 69 #define DEFAULT_SH_MEM_CONFIG \ 70 ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \ 71 (SH_MEM_ALIGNMENT_MODE_UNALIGNED_GFX12_1_0 << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \ 72 (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT)) 73 74 75 static const struct amdgpu_hwip_reg_entry gc_reg_list_12_1[] = { 76 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS), 77 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS2), 78 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS3), 79 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT1), 80 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT2), 81 SOC15_REG_ENTRY_STR(GC, 0, regCP_STALLED_STAT3), 82 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STALLED_STAT1), 83 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STALLED_STAT1), 84 SOC15_REG_ENTRY_STR(GC, 0, regCP_BUSY_STAT), 85 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT), 86 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT), 87 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_BUSY_STAT2), 88 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_BUSY_STAT2), 89 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPF_STATUS), 90 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_ERROR), 91 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_HPD_STATUS0), 92 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_BASE), 93 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_RPTR), 94 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB_WPTR), 95 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_BASE), 96 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_RPTR), 97 SOC15_REG_ENTRY_STR(GC, 0, regCP_RB0_WPTR), 98 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_CMD_BUFSZ), 99 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_CMD_BUFSZ), 100 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_LO), 101 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BASE_HI), 102 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB1_BUFSZ), 103 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_LO), 104 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BASE_HI), 105 SOC15_REG_ENTRY_STR(GC, 0, regCP_IB2_BUFSZ), 106 SOC15_REG_ENTRY_STR(GC, 0, regCPF_UTCL1_STATUS), 107 SOC15_REG_ENTRY_STR(GC, 0, regCPC_UTCL1_STATUS), 108 SOC15_REG_ENTRY_STR(GC, 0, regCPG_UTCL1_STATUS), 109 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS), 110 SOC15_REG_ENTRY_STR(GC, 0, regIA_UTCL1_STATUS_2), 111 SOC15_REG_ENTRY_STR(GC, 0, regPA_CL_CNTL_STATUS), 112 SOC15_REG_ENTRY_STR(GC, 0, regRMI_UTCL1_STATUS), 113 SOC15_REG_ENTRY_STR(GC, 0, regSQC_CACHES), 114 SOC15_REG_ENTRY_STR(GC, 0, regSQG_STATUS), 115 SOC15_REG_ENTRY_STR(GC, 0, regWD_UTCL1_STATUS), 116 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_CNTL2), 117 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_LO32), 118 SOC15_REG_ENTRY_STR(GC, 0, regGCVM_L2_PROTECTION_FAULT_STATUS_HI32), 119 SOC15_REG_ENTRY_STR(GC, 0, regCP_DEBUG), 120 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_CNTL), 121 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_CNTL), 122 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_INSTR_PNTR), 123 SOC15_REG_ENTRY_STR(GC, 0, regCP_ME_INSTR_PNTR), 124 SOC15_REG_ENTRY_STR(GC, 0, regCP_PFP_INSTR_PNTR), 125 SOC15_REG_ENTRY_STR(GC, 0, regCP_CPC_STATUS), 126 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR0), 127 SOC15_REG_ENTRY_STR(GC, 0, regCP_GFX_RS64_INSTR_PNTR1), 128 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_RS64_INSTR_PNTR), 129 /* cp header registers */ 130 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 131 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 132 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 133 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 134 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 135 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 136 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 137 SOC15_REG_ENTRY_STR(GC, 0, regCP_MES_HEADER_DUMP), 138 /* SE status registers */ 139 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE0), 140 SOC15_REG_ENTRY_STR(GC, 0, regGRBM_STATUS_SE1), 141 }; 142 143 static const struct amdgpu_hwip_reg_entry gc_cp_reg_list_12_1[] = { 144 /* compute registers */ 145 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_VMID), 146 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PERSISTENT_STATE), 147 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PIPE_PRIORITY), 148 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUEUE_PRIORITY), 149 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_QUANTUM), 150 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE), 151 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_BASE_HI), 152 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_RPTR), 153 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR), 154 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI), 155 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL), 156 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_CONTROL), 157 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR), 158 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_BASE_ADDR_HI), 159 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_RPTR), 160 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_IB_CONTROL), 161 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_REQUEST), 162 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR), 163 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI), 164 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_CONTROL), 165 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_RPTR), 166 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR), 167 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_EVENTS), 168 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_LO), 169 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_BASE_ADDR_HI), 170 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_CONTROL), 171 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_OFFSET), 172 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CNTL_STACK_SIZE), 173 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_WG_STATE_OFFSET), 174 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_CTX_SAVE_SIZE), 175 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_GDS_RESOURCE_STATE), 176 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_ERROR), 177 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_EOP_WPTR_MEM), 178 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_LO), 179 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_PQ_WPTR_HI), 180 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_OFFSET), 181 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_CNTL_STACK_DW_CNT), 182 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_SUSPEND_WG_STATE_OFFSET), 183 SOC15_REG_ENTRY_STR(GC, 0, regCP_HQD_DEQUEUE_STATUS), 184 /* cp header registers */ 185 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 186 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 187 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 188 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 189 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 190 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 191 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 192 SOC15_REG_ENTRY_STR(GC, 0, regCP_MEC_ME1_HEADER_DUMP), 193 }; 194 195 static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, int xcc_id); 196 static void gfx_v12_1_set_ring_funcs(struct amdgpu_device *adev); 197 static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev); 198 static void gfx_v12_1_set_rlc_funcs(struct amdgpu_device *adev); 199 static void gfx_v12_1_set_mqd_funcs(struct amdgpu_device *adev); 200 static void gfx_v12_1_set_imu_funcs(struct amdgpu_device *adev); 201 static int gfx_v12_1_get_cu_info(struct amdgpu_device *adev, 202 struct amdgpu_cu_info *cu_info); 203 static uint64_t gfx_v12_1_get_gpu_clock_counter(struct amdgpu_device *adev); 204 static void gfx_v12_1_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 205 u32 sh_num, u32 instance, int xcc_id); 206 static int gfx_v12_1_wait_for_rlc_autoload_complete(struct amdgpu_device *adev); 207 static void gfx_v12_1_xcc_set_safe_mode(struct amdgpu_device *adev, int xcc_id); 208 static void gfx_v12_1_xcc_unset_safe_mode(struct amdgpu_device *adev, int xcc_id); 209 static void gfx_v12_1_update_perf_clk(struct amdgpu_device *adev, 210 bool enable); 211 static void gfx_v12_1_xcc_update_perf_clk(struct amdgpu_device *adev, 212 bool enable, int xcc_id); 213 static int gfx_v12_1_init_cp_compute_microcode_bo(struct amdgpu_device *adev); 214 static void gfx_v12_1_xcc_update_medium_grain_clock_gating( 215 struct amdgpu_device *adev, bool enable, int xcc_id, bool force); 216 static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev, int xcc_id, 217 struct amdgpu_ring *ring, unsigned vmid); 218 219 static void gfx_v12_1_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel, 220 int mem_space, int opt, uint32_t addr0, 221 uint32_t addr1, uint32_t ref, 222 uint32_t mask, uint32_t inv) 223 { 224 if (mem_space == 0) { 225 addr0 = soc_v1_0_normalize_xcc_reg_offset(addr0); 226 addr1 = soc_v1_0_normalize_xcc_reg_offset(addr1); 227 } 228 229 amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5)); 230 amdgpu_ring_write(ring, 231 /* memory (1) or register (0) */ 232 (PACKET3_WAIT_REG_MEM__MEM_SPACE(mem_space) | 233 PACKET3_WAIT_REG_MEM__OPERATION(opt) | /* wait */ 234 PACKET3_WAIT_REG_MEM__FUNCTION(3))); /* equal */ 235 236 if (mem_space) 237 WARN_ON(addr0 & 0x3); /* Dword align */ 238 amdgpu_ring_write(ring, addr0); 239 amdgpu_ring_write(ring, addr1); 240 amdgpu_ring_write(ring, ref); 241 amdgpu_ring_write(ring, mask); 242 amdgpu_ring_write(ring, inv); /* poll interval */ 243 } 244 245 static int gfx_v12_1_ring_test_ring(struct amdgpu_ring *ring) 246 { 247 struct amdgpu_device *adev = ring->adev; 248 uint32_t scratch_reg0_offset, xcc_offset; 249 uint32_t tmp = 0; 250 unsigned i; 251 int r; 252 253 /* Use register offset which is local to XCC in the packet */ 254 xcc_offset = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0); 255 scratch_reg0_offset = SOC15_REG_OFFSET(GC, GET_INST(GC, ring->xcc_id), regSCRATCH_REG0); 256 WREG32(scratch_reg0_offset, 0xCAFEDEAD); 257 tmp = RREG32(scratch_reg0_offset); 258 259 r = amdgpu_ring_alloc(ring, 5); 260 if (r) { 261 dev_err(adev->dev, 262 "amdgpu: cp failed to lock ring %d (%d).\n", 263 ring->idx, r); 264 return r; 265 } 266 267 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1)); 268 amdgpu_ring_write(ring, xcc_offset - PACKET3_SET_UCONFIG_REG_START); 269 amdgpu_ring_write(ring, 0xDEADBEEF); 270 amdgpu_ring_commit(ring); 271 272 for (i = 0; i < adev->usec_timeout; i++) { 273 tmp = RREG32(scratch_reg0_offset); 274 if (tmp == 0xDEADBEEF) 275 break; 276 if (amdgpu_emu_mode == 1) 277 msleep(1); 278 else 279 udelay(1); 280 } 281 282 if (i >= adev->usec_timeout) 283 r = -ETIMEDOUT; 284 return r; 285 } 286 287 static int gfx_v12_1_ring_test_ib(struct amdgpu_ring *ring, long timeout) 288 { 289 struct amdgpu_device *adev = ring->adev; 290 struct amdgpu_job *job; 291 struct amdgpu_ib *ib; 292 struct dma_fence *f = NULL; 293 unsigned index; 294 uint64_t gpu_addr; 295 volatile uint32_t *cpu_ptr; 296 long r; 297 298 r = amdgpu_wb_get(adev, &index); 299 if (r) 300 return r; 301 302 gpu_addr = adev->wb.gpu_addr + (index * 4); 303 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD); 304 cpu_ptr = &adev->wb.wb[index]; 305 306 r = amdgpu_job_alloc_with_ib(ring->adev, NULL, NULL, 16, 307 AMDGPU_IB_POOL_DIRECT, 308 AMDGPU_KERNEL_JOB_ID_GFX_RING_TEST, 309 &job); 310 if (r) { 311 dev_err(adev->dev, "amdgpu: failed to get ib (%ld).\n", r); 312 goto err1; 313 } 314 ib = &job->ibs[0]; 315 316 ib->ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3); 317 ib->ptr[1] = PACKET3_WRITE_DATA__DST_SEL(5) | PACKET3_WRITE_DATA__WR_CONFIRM(1); 318 ib->ptr[2] = lower_32_bits(gpu_addr); 319 ib->ptr[3] = upper_32_bits(gpu_addr); 320 ib->ptr[4] = 0xDEADBEEF; 321 ib->length_dw = 5; 322 323 r = amdgpu_job_submit_direct(job, ring, &f); 324 if (r) { 325 amdgpu_job_free(job); 326 goto err2; 327 } 328 329 r = dma_fence_wait_timeout(f, false, timeout); 330 if (r == 0) { 331 r = -ETIMEDOUT; 332 goto err2; 333 } else if (r < 0) { 334 goto err2; 335 } 336 337 if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF) 338 r = 0; 339 else 340 r = -EINVAL; 341 err2: 342 dma_fence_put(f); 343 err1: 344 amdgpu_wb_free(adev, index); 345 return r; 346 } 347 348 static void gfx_v12_1_free_microcode(struct amdgpu_device *adev) 349 { 350 amdgpu_ucode_release(&adev->gfx.rlc_fw); 351 amdgpu_ucode_release(&adev->gfx.mec_fw); 352 353 kfree(adev->gfx.rlc.register_list_format); 354 } 355 356 static int gfx_v12_1_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix) 357 { 358 const struct psp_firmware_header_v1_0 *toc_hdr; 359 int err = 0; 360 361 err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, 362 AMDGPU_UCODE_REQUIRED, 363 "amdgpu/%s_toc.bin", ucode_prefix); 364 if (err) 365 goto out; 366 367 toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data; 368 adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version); 369 adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version); 370 adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes); 371 adev->psp.toc.start_addr = (uint8_t *)toc_hdr + 372 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes); 373 return 0; 374 out: 375 amdgpu_ucode_release(&adev->psp.toc_fw); 376 return err; 377 } 378 379 static int gfx_v12_1_init_microcode(struct amdgpu_device *adev) 380 { 381 char ucode_prefix[15]; 382 int err; 383 const struct rlc_firmware_header_v2_0 *rlc_hdr; 384 uint16_t version_major; 385 uint16_t version_minor; 386 387 DRM_DEBUG("\n"); 388 389 amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix)); 390 391 if (!amdgpu_sriov_vf(adev)) { 392 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0) && 393 adev->rev_id == 0) 394 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 395 AMDGPU_UCODE_REQUIRED, 396 "amdgpu/%s_rlc_1.bin", ucode_prefix); 397 else 398 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, 399 AMDGPU_UCODE_REQUIRED, 400 "amdgpu/%s_rlc.bin", ucode_prefix); 401 if (err) 402 goto out; 403 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 404 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 405 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 406 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor); 407 if (err) 408 goto out; 409 } 410 411 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(12, 1, 0) && 412 adev->rev_id == 0) 413 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 414 AMDGPU_UCODE_REQUIRED, 415 "amdgpu/%s_mec_1.bin", ucode_prefix); 416 else 417 err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, 418 AMDGPU_UCODE_REQUIRED, 419 "amdgpu/%s_mec.bin", ucode_prefix); 420 if (err) 421 goto out; 422 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC); 423 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK); 424 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK); 425 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK); 426 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK); 427 428 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 429 err = gfx_v12_1_init_toc_microcode(adev, ucode_prefix); 430 431 /* only one MEC for gfx 12 */ 432 adev->gfx.mec2_fw = NULL; 433 434 if (adev->gfx.imu.funcs) { 435 if (adev->gfx.imu.funcs->init_microcode && 436 adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) { 437 err = adev->gfx.imu.funcs->init_microcode(adev); 438 if (err) 439 dev_err(adev->dev, "Failed to load imu firmware!\n"); 440 } 441 } 442 443 out: 444 if (err) { 445 amdgpu_ucode_release(&adev->gfx.rlc_fw); 446 amdgpu_ucode_release(&adev->gfx.mec_fw); 447 } 448 449 return err; 450 } 451 452 static u32 gfx_v12_1_get_csb_size(struct amdgpu_device *adev) 453 { 454 u32 count = 0; 455 const struct cs_section_def *sect = NULL; 456 const struct cs_extent_def *ext = NULL; 457 458 count += 1; 459 460 for (sect = gfx12_cs_data; sect->section != NULL; ++sect) { 461 if (sect->id == SECT_CONTEXT) { 462 for (ext = sect->section; ext->extent != NULL; ++ext) 463 count += 2 + ext->reg_count; 464 } else 465 return 0; 466 } 467 468 return count; 469 } 470 471 static void gfx_v12_1_get_csb_buffer(struct amdgpu_device *adev, u32 *buffer) 472 { 473 u32 count = 0, clustercount = 0, i; 474 const struct cs_section_def *sect = NULL; 475 const struct cs_extent_def *ext = NULL; 476 477 if (adev->gfx.rlc.cs_data == NULL) 478 return; 479 if (buffer == NULL) 480 return; 481 482 count += 1; 483 484 for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) { 485 if (sect->id == SECT_CONTEXT) { 486 for (ext = sect->section; ext->extent != NULL; ++ext) { 487 clustercount++; 488 buffer[count++] = ext->reg_count; 489 buffer[count++] = ext->reg_index; 490 491 for (i = 0; i < ext->reg_count; i++) 492 buffer[count++] = cpu_to_le32(ext->extent[i]); 493 } 494 } else 495 return; 496 } 497 498 buffer[0] = clustercount; 499 } 500 501 static void gfx_v12_1_rlc_fini(struct amdgpu_device *adev) 502 { 503 /* clear state block */ 504 amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj, 505 &adev->gfx.rlc.clear_state_gpu_addr, 506 (void **)&adev->gfx.rlc.cs_ptr); 507 508 /* jump table block */ 509 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj, 510 &adev->gfx.rlc.cp_table_gpu_addr, 511 (void **)&adev->gfx.rlc.cp_table_ptr); 512 } 513 514 static void gfx_v12_1_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev) 515 { 516 int xcc_id, num_xcc; 517 struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl; 518 519 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 520 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 521 reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[GET_INST(GC, xcc_id)]; 522 523 reg_access_ctrl->grbm_cntl = 524 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_CNTL); 525 reg_access_ctrl->grbm_idx = 526 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX); 527 528 reg_access_ctrl->vfi_cmd = 529 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_CMD); 530 reg_access_ctrl->vfi_stat = 531 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_STAT); 532 reg_access_ctrl->vfi_addr = 533 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_ADDR); 534 reg_access_ctrl->vfi_data = 535 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_DATA); 536 reg_access_ctrl->vfi_grbm_cntl = 537 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_CNTL); 538 reg_access_ctrl->vfi_grbm_idx = 539 SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_VFI_GRBM_GFX_INDEX); 540 reg_access_ctrl->vfi_grbm_cntl_data = 0; 541 reg_access_ctrl->vfi_grbm_idx_data = 0; 542 } 543 adev->gfx.rlc.rlcg_reg_access_supported = true; 544 } 545 546 static int gfx_v12_1_rlc_init(struct amdgpu_device *adev) 547 { 548 const struct cs_section_def *cs_data; 549 int r; 550 551 adev->gfx.rlc.cs_data = gfx12_cs_data; 552 553 cs_data = adev->gfx.rlc.cs_data; 554 555 if (cs_data) { 556 /* init clear state block */ 557 r = amdgpu_gfx_rlc_init_csb(adev); 558 if (r) 559 return r; 560 } 561 562 return 0; 563 } 564 565 static void gfx_v12_1_mec_fini(struct amdgpu_device *adev) 566 { 567 amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL); 568 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL); 569 amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL); 570 } 571 572 static int gfx_v12_1_mec_init(struct amdgpu_device *adev) 573 { 574 int r, i, num_xcc; 575 u32 *hpd; 576 size_t mec_hpd_size; 577 578 bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES); 579 580 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 581 for (i = 0; i < num_xcc; i++) 582 bitmap_zero(adev->gfx.mec_bitmap[i].queue_bitmap, 583 AMDGPU_MAX_COMPUTE_QUEUES); 584 585 /* take ownership of the relevant compute queues */ 586 amdgpu_gfx_compute_queue_acquire(adev); 587 mec_hpd_size = adev->gfx.num_compute_rings * 588 GFX12_MEC_HPD_SIZE * num_xcc; 589 590 if (mec_hpd_size) { 591 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE, 592 AMDGPU_GEM_DOMAIN_GTT, 593 &adev->gfx.mec.hpd_eop_obj, 594 &adev->gfx.mec.hpd_eop_gpu_addr, 595 (void **)&hpd); 596 if (r) { 597 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r); 598 gfx_v12_1_mec_fini(adev); 599 return r; 600 } 601 602 memset(hpd, 0, mec_hpd_size); 603 604 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj); 605 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj); 606 } 607 608 return 0; 609 } 610 611 static uint32_t wave_read_ind(struct amdgpu_device *adev, 612 uint32_t xcc_id, uint32_t wave, 613 uint32_t address) 614 { 615 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 616 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 617 (address << SQ_IND_INDEX__INDEX__SHIFT)); 618 return RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 619 } 620 621 static void wave_read_regs(struct amdgpu_device *adev, 622 uint32_t xcc_id, uint32_t wave, 623 uint32_t thread, uint32_t regno, 624 uint32_t num, uint32_t *out) 625 { 626 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_INDEX, 627 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) | 628 (regno << SQ_IND_INDEX__INDEX__SHIFT) | 629 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) | 630 (SQ_IND_INDEX__AUTO_INCR_MASK)); 631 while (num--) 632 *(out++) = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_IND_DATA); 633 } 634 635 static void gfx_v12_1_read_wave_data(struct amdgpu_device *adev, 636 uint32_t xcc_id, 637 uint32_t simd, uint32_t wave, 638 uint32_t *dst, int *no_fields) 639 { 640 /* in gfx12 the SIMD_ID is specified as part of the INSTANCE 641 * field when performing a select_se_sh so it should be 642 * zero here */ 643 WARN_ON(simd != 0); 644 645 /* type 4 wave data */ 646 dst[(*no_fields)++] = 4; 647 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATUS); 648 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_LO); 649 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_PC_HI); 650 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_LO); 651 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXEC_HI); 652 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_HW_ID1); 653 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_HW_ID2); 654 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_GPR_ALLOC); 655 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_LDS_ALLOC); 656 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_STS); 657 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_STS2); 658 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_IB_DBG1); 659 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_M0); 660 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_MODE); 661 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_STATE_PRIV); 662 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXCP_FLAG_PRIV); 663 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_EXCP_FLAG_USER); 664 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_TRAP_CTRL); 665 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_ACTIVE); 666 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_VALID_AND_IDLE); 667 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_DVGPR_ALLOC_LO); 668 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_DVGPR_ALLOC_HI); 669 dst[(*no_fields)++] = wave_read_ind(adev, xcc_id, wave, ixSQ_WAVE_SCHED_MODE); 670 } 671 672 static void gfx_v12_1_read_wave_sgprs(struct amdgpu_device *adev, 673 uint32_t xcc_id, uint32_t simd, 674 uint32_t wave, uint32_t start, 675 uint32_t size, uint32_t *dst) 676 { 677 WARN_ON(simd != 0); 678 679 wave_read_regs(adev, xcc_id, wave, 0, 680 start + SQIND_WAVE_SGPRS_OFFSET, 681 size, dst); 682 } 683 684 static void gfx_v12_1_read_wave_vgprs(struct amdgpu_device *adev, 685 uint32_t xcc_id, uint32_t simd, 686 uint32_t wave, uint32_t thread, 687 uint32_t start, uint32_t size, 688 uint32_t *dst) 689 { 690 wave_read_regs(adev, xcc_id, wave, thread, 691 start + SQIND_WAVE_VGPRS_OFFSET, 692 size, dst); 693 } 694 695 static void gfx_v12_1_select_me_pipe_q(struct amdgpu_device *adev, 696 u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id) 697 { 698 soc_v1_0_grbm_select(adev, me, pipe, q, vm, GET_INST(GC, xcc_id)); 699 } 700 701 static int gfx_v12_1_get_xccs_per_xcp(struct amdgpu_device *adev) 702 { 703 u32 reg_data; 704 705 /* the register data is expected to be the same on all instances */ 706 if (amdgpu_sriov_vf(adev)) { 707 /* 708 * RLCG cannot access the GFX_IMU registers, so take the field 709 * from RLC_IMU_AID_CONFIG and read it without going through 710 * the RLCG path. 711 */ 712 reg_data = RREG32_NO_KIQ(SOC15_REG_OFFSET(GC, GET_INST(GC, 0), 713 regRLC_IMU_AID_CONFIG)); 714 715 return REG_GET_FIELD(reg_data, RLC_IMU_AID_CONFIG, 716 TOTAL_XCCS_IN_XCP); 717 } 718 719 reg_data = RREG32_SOC15(GC, GET_INST(GC, 0), 720 regGFX_IMU_PARTITION_SWITCH_SHADOW); 721 722 return REG_GET_FIELD(reg_data, GFX_IMU_PARTITION_SWITCH_SHADOW, 723 TOTAL_XCCS_IN_XCP); 724 } 725 726 static int gfx_v12_1_ih_to_xcc_inst(struct amdgpu_device *adev, int ih_node) 727 { 728 int logic_xcc; 729 int xcc = (ih_node & 0x7) - 2 + (ih_node >> 3) * 4; 730 731 for (logic_xcc = 0; logic_xcc < NUM_XCC(adev->gfx.xcc_mask); logic_xcc++) { 732 if (xcc == GET_INST(GC, logic_xcc)) 733 return logic_xcc; 734 } 735 736 dev_err(adev->dev, "Couldn't find xcc mapping from IH node"); 737 return -EINVAL; 738 } 739 740 static const struct amdgpu_gfx_funcs gfx_v12_1_gfx_funcs = { 741 .get_gpu_clock_counter = &gfx_v12_1_get_gpu_clock_counter, 742 .select_se_sh = &gfx_v12_1_xcc_select_se_sh, 743 .read_wave_data = &gfx_v12_1_read_wave_data, 744 .read_wave_sgprs = &gfx_v12_1_read_wave_sgprs, 745 .read_wave_vgprs = &gfx_v12_1_read_wave_vgprs, 746 .select_me_pipe_q = &gfx_v12_1_select_me_pipe_q, 747 .update_perfmon_mgcg = &gfx_v12_1_update_perf_clk, 748 .get_xccs_per_xcp = &gfx_v12_1_get_xccs_per_xcp, 749 .ih_node_to_logical_xcc = &gfx_v12_1_ih_to_xcc_inst, 750 }; 751 752 static int gfx_v12_1_gpu_early_init(struct amdgpu_device *adev) 753 { 754 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 755 case IP_VERSION(12, 1, 0): 756 adev->gfx.config.max_hw_contexts = 8; 757 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20; 758 adev->gfx.config.sc_prim_fifo_size_backend = 0x100; 759 adev->gfx.config.sc_hiz_tile_fifo_size = 0; 760 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0; 761 break; 762 default: 763 dev_warn(adev->dev, "Unsupported GC version 0x%08x\n", 764 amdgpu_ip_version(adev, GC_HWIP, 0)); 765 return -EINVAL; 766 } 767 768 return 0; 769 } 770 771 static int gfx_v12_1_compute_ring_init(struct amdgpu_device *adev, int ring_id, 772 int xcc_id, int mec, int pipe, int queue) 773 { 774 int r; 775 unsigned irq_type; 776 struct amdgpu_ring *ring; 777 unsigned int hw_prio; 778 uint32_t xcc_doorbell_start; 779 780 ring = &adev->gfx.compute_ring[xcc_id * adev->gfx.num_compute_rings + 781 ring_id]; 782 783 /* mec0 is me1 */ 784 ring->xcc_id = xcc_id; 785 ring->me = mec + 1; 786 ring->pipe = pipe; 787 ring->queue = queue; 788 789 ring->ring_obj = NULL; 790 ring->use_doorbell = true; 791 xcc_doorbell_start = adev->doorbell_index.mec_ring0 + 792 xcc_id * adev->doorbell_index.xcc_doorbell_range; 793 ring->doorbell_index = (xcc_doorbell_start + ring_id) << 1; 794 ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr + 795 (ring_id + xcc_id * adev->gfx.num_compute_rings) * 796 GFX12_MEC_HPD_SIZE; 797 ring->vm_hub = AMDGPU_GFXHUB(xcc_id); 798 sprintf(ring->name, "comp_%d.%d.%d.%d", 799 ring->xcc_id, ring->me, ring->pipe, ring->queue); 800 801 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 802 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec) 803 + ring->pipe; 804 hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ? 805 AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL; 806 /* type-2 packets are deprecated on MEC, use type-3 instead */ 807 r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type, 808 hw_prio, NULL); 809 if (r) 810 return r; 811 812 return 0; 813 } 814 815 static struct { 816 SOC24_FIRMWARE_ID id; 817 unsigned int offset; 818 unsigned int size; 819 unsigned int size_x16; 820 unsigned int num_inst; 821 } rlc_autoload_info[SOC24_FIRMWARE_ID_MAX]; 822 823 #define RLC_TOC_OFFSET_DWUNIT 8 824 #define RLC_SIZE_MULTIPLE 1024 825 #define RLC_TOC_UMF_SIZE_inM 23ULL 826 #define RLC_TOC_FORMAT_API 165ULL 827 828 #define RLC_NUM_INS_CODE0 1 829 #define RLC_NUM_INS_CODE1 8 830 #define RLC_NUM_INS_CODE2 2 831 #define RLC_NUM_INS_CODE3 16 832 833 static void gfx_v12_1_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc) 834 { 835 RLC_TABLE_OF_CONTENT_V2 *ucode = rlc_toc; 836 837 while (ucode && (ucode->id > SOC24_FIRMWARE_ID_INVALID)) { 838 rlc_autoload_info[ucode->id].id = ucode->id; 839 rlc_autoload_info[ucode->id].offset = 840 ucode->offset * RLC_TOC_OFFSET_DWUNIT * 4; 841 rlc_autoload_info[ucode->id].size = 842 ucode->size_x16 ? ucode->size * RLC_SIZE_MULTIPLE * 4 : 843 ucode->size * 4; 844 switch (ucode->vfflr_image_code) { 845 case 0: 846 rlc_autoload_info[ucode->id].num_inst = 847 RLC_NUM_INS_CODE0; 848 break; 849 case 1: 850 rlc_autoload_info[ucode->id].num_inst = 851 RLC_NUM_INS_CODE1; 852 break; 853 case 2: 854 rlc_autoload_info[ucode->id].num_inst = 855 RLC_NUM_INS_CODE2; 856 break; 857 case 3: 858 rlc_autoload_info[ucode->id].num_inst = 859 RLC_NUM_INS_CODE3; 860 break; 861 default: 862 dev_err(adev->dev, 863 "Invalid Instance number detected\n"); 864 break; 865 } 866 ucode++; 867 } 868 } 869 870 static uint32_t gfx_v12_1_calc_toc_total_size(struct amdgpu_device *adev) 871 { 872 uint32_t total_size = 0; 873 SOC24_FIRMWARE_ID id; 874 875 gfx_v12_1_parse_rlc_toc(adev, adev->psp.toc.start_addr); 876 877 for (id = SOC24_FIRMWARE_ID_RLC_G_UCODE; id < SOC24_FIRMWARE_ID_MAX; id++) 878 total_size += rlc_autoload_info[id].size; 879 880 /* In case the offset in rlc toc ucode is aligned */ 881 if (total_size < rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset) 882 total_size = rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].offset + 883 rlc_autoload_info[SOC24_FIRMWARE_ID_MAX-1].size; 884 if (total_size < (RLC_TOC_UMF_SIZE_inM << 20)) 885 total_size = RLC_TOC_UMF_SIZE_inM << 20; 886 887 return total_size; 888 } 889 890 static int gfx_v12_1_rlc_autoload_buffer_init(struct amdgpu_device *adev) 891 { 892 int r; 893 uint32_t total_size; 894 895 total_size = gfx_v12_1_calc_toc_total_size(adev); 896 897 r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024, 898 AMDGPU_GEM_DOMAIN_VRAM, 899 &adev->gfx.rlc.rlc_autoload_bo, 900 &adev->gfx.rlc.rlc_autoload_gpu_addr, 901 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 902 903 if (r) { 904 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r); 905 return r; 906 } 907 908 return 0; 909 } 910 911 static void gfx_v12_1_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev, 912 SOC24_FIRMWARE_ID id, 913 const void *fw_data, 914 uint32_t fw_size) 915 { 916 uint32_t toc_offset; 917 uint32_t toc_fw_size, toc_fw_inst_size; 918 char *ptr = adev->gfx.rlc.rlc_autoload_ptr; 919 int i, num_inst; 920 921 if (id <= SOC24_FIRMWARE_ID_INVALID || id >= SOC24_FIRMWARE_ID_MAX) 922 return; 923 924 toc_offset = rlc_autoload_info[id].offset; 925 toc_fw_size = rlc_autoload_info[id].size; 926 num_inst = rlc_autoload_info[id].num_inst; 927 toc_fw_inst_size = toc_fw_size / num_inst; 928 929 if (fw_size == 0) 930 fw_size = toc_fw_inst_size; 931 932 if (fw_size > toc_fw_inst_size) 933 fw_size = toc_fw_inst_size; 934 935 for (i = 0; i < num_inst; i++) { 936 if ((num_inst == RLC_NUM_INS_CODE0) || 937 ((1 << (i / 2)) & adev->gfx.xcc_mask)) { 938 memcpy(ptr + toc_offset + i * toc_fw_inst_size, fw_data, fw_size); 939 940 if (fw_size < toc_fw_inst_size) 941 memset(ptr + toc_offset + fw_size + i * toc_fw_inst_size, 942 0, toc_fw_inst_size - fw_size); 943 } 944 } 945 } 946 947 static void 948 gfx_v12_1_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev) 949 { 950 void *data; 951 uint32_t size; 952 uint32_t *toc_ptr; 953 954 data = adev->psp.toc.start_addr; 955 size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_TOC].size; 956 957 toc_ptr = (uint32_t *)data + size / 4 - 2; 958 *toc_ptr = (RLC_TOC_FORMAT_API << 24) | 0x1; 959 960 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_TOC, 961 data, size); 962 } 963 964 static void 965 gfx_v12_1_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev) 966 { 967 const __le32 *fw_data; 968 uint32_t fw_size; 969 const struct gfx_firmware_header_v2_0 *cpv2_hdr; 970 const struct rlc_firmware_header_v2_0 *rlc_hdr; 971 const struct rlc_firmware_header_v2_1 *rlcv21_hdr; 972 const struct rlc_firmware_header_v2_2 *rlcv22_hdr; 973 uint16_t version_major, version_minor; 974 975 /* mec ucode */ 976 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *) 977 adev->gfx.mec_fw->data; 978 /* instruction */ 979 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 980 le32_to_cpu(cpv2_hdr->ucode_offset_bytes)); 981 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes); 982 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC, 983 fw_data, fw_size); 984 /* data */ 985 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 986 le32_to_cpu(cpv2_hdr->data_offset_bytes)); 987 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes); 988 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P0_STACK, 989 fw_data, fw_size); 990 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P1_STACK, 991 fw_data, fw_size); 992 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P2_STACK, 993 fw_data, fw_size); 994 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RS64_MEC_P3_STACK, 995 fw_data, fw_size); 996 997 /* rlc ucode */ 998 rlc_hdr = (const struct rlc_firmware_header_v2_0 *) 999 adev->gfx.rlc_fw->data; 1000 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1001 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes)); 1002 fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes); 1003 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_G_UCODE, 1004 fw_data, fw_size); 1005 1006 version_major = le16_to_cpu(rlc_hdr->header.header_version_major); 1007 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor); 1008 if (version_major == 2) { 1009 if (version_minor >= 1) { 1010 rlcv21_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data; 1011 1012 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1013 le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_offset_bytes)); 1014 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_gpm_size_bytes); 1015 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLCG_SCRATCH, 1016 fw_data, fw_size); 1017 1018 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1019 le32_to_cpu(rlcv21_hdr->save_restore_list_srm_offset_bytes)); 1020 fw_size = le32_to_cpu(rlcv21_hdr->save_restore_list_srm_size_bytes); 1021 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLC_SRM_ARAM, 1022 fw_data, fw_size); 1023 } 1024 if (version_minor >= 2) { 1025 rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1026 1027 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1028 le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes)); 1029 fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes); 1030 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_UCODE, 1031 fw_data, fw_size); 1032 1033 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1034 le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes)); 1035 fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes); 1036 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_RLX6_DRAM_BOOT, 1037 fw_data, fw_size); 1038 } 1039 } 1040 } 1041 1042 static void 1043 gfx_v12_1_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev) 1044 { 1045 const __le32 *fw_data; 1046 uint32_t fw_size; 1047 const struct sdma_firmware_header_v3_0 *sdma_hdr; 1048 1049 if (adev->sdma.instance[0].fw) { 1050 sdma_hdr = (const struct sdma_firmware_header_v3_0 *) 1051 adev->sdma.instance[0].fw->data; 1052 fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data + 1053 le32_to_cpu(sdma_hdr->ucode_offset_bytes)); 1054 fw_size = le32_to_cpu(sdma_hdr->ucode_size_bytes); 1055 1056 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, SOC24_FIRMWARE_ID_SDMA_UCODE_TH0, 1057 fw_data, fw_size); 1058 } 1059 } 1060 1061 static void 1062 gfx_v12_1_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev) 1063 { 1064 const __le32 *fw_data; 1065 unsigned fw_size; 1066 const struct mes_firmware_header_v1_0 *mes_hdr; 1067 int pipe, ucode_id, data_id; 1068 1069 for (pipe = 0; pipe < 2; pipe++) { 1070 if (pipe == 0) { 1071 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P0; 1072 data_id = SOC24_FIRMWARE_ID_RS64_MES_P0_STACK; 1073 } else { 1074 ucode_id = SOC24_FIRMWARE_ID_RS64_MES_P1; 1075 data_id = SOC24_FIRMWARE_ID_RS64_MES_P1_STACK; 1076 } 1077 1078 mes_hdr = (const struct mes_firmware_header_v1_0 *) 1079 adev->mes.fw[pipe]->data; 1080 1081 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1082 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes)); 1083 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes); 1084 1085 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, ucode_id, fw_data, fw_size); 1086 1087 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data + 1088 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes)); 1089 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes); 1090 1091 gfx_v12_1_rlc_backdoor_autoload_copy_ucode(adev, data_id, fw_data, fw_size); 1092 } 1093 } 1094 1095 static int gfx_v12_1_rlc_backdoor_autoload_enable(struct amdgpu_device *adev) 1096 { 1097 uint32_t rlc_g_offset, rlc_g_size; 1098 uint64_t gpu_addr; 1099 uint32_t data; 1100 int i, num_xcc; 1101 1102 /* RLC autoload sequence 2: copy ucode */ 1103 gfx_v12_1_rlc_backdoor_autoload_copy_sdma_ucode(adev); 1104 gfx_v12_1_rlc_backdoor_autoload_copy_gfx_ucode(adev); 1105 gfx_v12_1_rlc_backdoor_autoload_copy_mes_ucode(adev); 1106 gfx_v12_1_rlc_backdoor_autoload_copy_toc_ucode(adev); 1107 1108 rlc_g_offset = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].offset; 1109 rlc_g_size = rlc_autoload_info[SOC24_FIRMWARE_ID_RLC_G_UCODE].size; 1110 gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset - adev->gmc.vram_start; 1111 1112 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1113 for (i = 0; i < num_xcc; i++) { 1114 WREG32_SOC15(GC, GET_INST(GC, i), 1115 regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, 1116 upper_32_bits(gpu_addr)); 1117 WREG32_SOC15(GC, GET_INST(GC, i), 1118 regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, 1119 lower_32_bits(gpu_addr)); 1120 WREG32_SOC15(GC, GET_INST(GC, i), 1121 regGFX_IMU_RLC_BOOTLOADER_SIZE, 1122 rlc_g_size); 1123 } 1124 1125 if (adev->gfx.imu.funcs) { 1126 /* RLC autoload sequence 3: load IMU fw */ 1127 if (adev->gfx.imu.funcs->load_microcode) 1128 adev->gfx.imu.funcs->load_microcode(adev); 1129 } 1130 1131 /* unhalt rlc to start autoload */ 1132 for (i = 0; i < num_xcc; i++) { 1133 data = RREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE); 1134 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD0_ENABLE, 1); 1135 data = REG_SET_FIELD(data, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1); 1136 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_GPM_THREAD_ENABLE, data); 1137 WREG32_SOC15(GC, GET_INST(GC, i), regRLC_CNTL, RLC_CNTL__RLC_ENABLE_F32_MASK); 1138 } 1139 1140 return 0; 1141 } 1142 1143 static void gfx_v12_1_alloc_ip_dump(struct amdgpu_device *adev) 1144 { 1145 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_1); 1146 uint32_t *ptr, inst, num_xcc; 1147 1148 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1149 1150 ptr = kzalloc_objs(*ptr, reg_count * num_xcc); 1151 if (!ptr) { 1152 DRM_ERROR("Failed to allocate memory for GFX IP Dump\n"); 1153 adev->gfx.ip_dump_core = NULL; 1154 } else { 1155 adev->gfx.ip_dump_core = ptr; 1156 } 1157 1158 /* Allocate memory for compute queue registers for all the instances */ 1159 reg_count = ARRAY_SIZE(gc_cp_reg_list_12_1); 1160 inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1161 adev->gfx.mec.num_queue_per_pipe; 1162 1163 ptr = kzalloc_objs(*ptr, reg_count * inst * num_xcc); 1164 if (!ptr) { 1165 DRM_ERROR("Failed to allocate memory for Compute Queues IP Dump\n"); 1166 adev->gfx.ip_dump_compute_queues = NULL; 1167 } else { 1168 adev->gfx.ip_dump_compute_queues = ptr; 1169 } 1170 } 1171 1172 static void gfx_v12_1_ip_print(struct amdgpu_ip_block *ip_block, 1173 struct drm_printer *p) 1174 { 1175 struct amdgpu_device *adev = ip_block->adev; 1176 uint32_t i, j, k; 1177 uint32_t xcc_id, xcc_offset, inst_offset; 1178 uint32_t num_xcc, reg, num_inst; 1179 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_1); 1180 1181 if (!adev->gfx.ip_dump_core) 1182 return; 1183 1184 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1185 drm_printf(p, "Number of Instances:%d\n", num_xcc); 1186 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1187 xcc_offset = xcc_id * reg_count; 1188 drm_printf(p, "\nInstance id:%d\n", xcc_id); 1189 for (i = 0; i < reg_count; i++) 1190 drm_printf(p, "%-50s \t 0x%08x\n", 1191 gc_reg_list_12_1[i].reg_name, 1192 adev->gfx.ip_dump_core[xcc_offset + i]); 1193 } 1194 1195 /* print compute queue registers for all instances */ 1196 if (!adev->gfx.ip_dump_compute_queues) 1197 return; 1198 1199 reg_count = ARRAY_SIZE(gc_cp_reg_list_12_1); 1200 drm_printf(p, "\nnum_xcc: %d num_mec: %d num_pipe: %d num_queue: %d\n", 1201 num_xcc, 1202 adev->gfx.mec.num_mec, 1203 adev->gfx.mec.num_pipe_per_mec, 1204 adev->gfx.mec.num_queue_per_pipe); 1205 1206 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1207 adev->gfx.mec.num_queue_per_pipe; 1208 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1209 xcc_offset = xcc_id * reg_count * num_inst; 1210 inst_offset = 0; 1211 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 1212 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 1213 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 1214 drm_printf(p, 1215 "\nxcc:%d mec:%d, pipe:%d, queue:%d\n", 1216 xcc_id, i, j, k); 1217 for (reg = 0; reg < reg_count; reg++) { 1218 drm_printf(p, 1219 "%-50s \t 0x%08x\n", 1220 gc_cp_reg_list_12_1[reg].reg_name, 1221 adev->gfx.ip_dump_compute_queues 1222 [xcc_offset + inst_offset + 1223 reg]); 1224 } 1225 inst_offset += reg_count; 1226 } 1227 } 1228 } 1229 } 1230 } 1231 1232 static void gfx_v12_1_ip_dump(struct amdgpu_ip_block *ip_block) 1233 { 1234 struct amdgpu_device *adev = ip_block->adev; 1235 uint32_t i, j, k; 1236 uint32_t num_xcc, reg, num_inst; 1237 uint32_t xcc_id, xcc_offset, inst_offset; 1238 uint32_t reg_count = ARRAY_SIZE(gc_reg_list_12_1); 1239 1240 if (!adev->gfx.ip_dump_core) 1241 return; 1242 1243 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1244 1245 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1246 xcc_offset = xcc_id * reg_count; 1247 for (i = 0; i < reg_count; i++) 1248 adev->gfx.ip_dump_core[xcc_offset + i] = 1249 RREG32(SOC15_REG_ENTRY_OFFSET_INST(gc_reg_list_12_1[i], 1250 GET_INST(GC, xcc_id))); 1251 } 1252 1253 /* dump compute queue registers for all instances */ 1254 if (!adev->gfx.ip_dump_compute_queues) 1255 return; 1256 1257 num_inst = adev->gfx.mec.num_mec * adev->gfx.mec.num_pipe_per_mec * 1258 adev->gfx.mec.num_queue_per_pipe; 1259 reg_count = ARRAY_SIZE(gc_cp_reg_list_12_1); 1260 1261 mutex_lock(&adev->srbm_mutex); 1262 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1263 xcc_offset = xcc_id * reg_count * num_inst; 1264 inst_offset = 0; 1265 for (i = 0; i < adev->gfx.mec.num_mec; i++) { 1266 for (j = 0; j < adev->gfx.mec.num_pipe_per_mec; j++) { 1267 for (k = 0; k < adev->gfx.mec.num_queue_per_pipe; k++) { 1268 /* ME0 is for GFX so start from 1 for CP */ 1269 soc_v1_0_grbm_select(adev, 1 + i, j, k, 0, 1270 GET_INST(GC, xcc_id)); 1271 1272 for (reg = 0; reg < reg_count; reg++) { 1273 adev->gfx.ip_dump_compute_queues 1274 [xcc_offset + 1275 inst_offset + reg] = 1276 RREG32(SOC15_REG_ENTRY_OFFSET_INST( 1277 gc_cp_reg_list_12_1[reg], 1278 GET_INST(GC, xcc_id))); 1279 } 1280 inst_offset += reg_count; 1281 } 1282 } 1283 } 1284 } 1285 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, 0); 1286 mutex_unlock(&adev->srbm_mutex); 1287 } 1288 1289 static int gfx_v12_1_sw_init(struct amdgpu_ip_block *ip_block) 1290 { 1291 uint16_t major_ver, minor_ver; 1292 int i, j, k, r, ring_id = 0; 1293 unsigned num_compute_rings; 1294 int xcc_id, num_xcc; 1295 struct amdgpu_device *adev = ip_block->adev; 1296 1297 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) { 1298 case IP_VERSION(12, 1, 0): 1299 adev->gfx.mec.num_mec = 1; 1300 adev->gfx.mec.num_pipe_per_mec = 4; 1301 adev->gfx.mec.num_queue_per_pipe = 8; 1302 1303 if (!amdgpu_discovery_get_gc_major_minor_version( 1304 adev, &major_ver, &minor_ver)) { 1305 if (major_ver == 1 && minor_ver == 3) { 1306 adev->gfx.config.max_cu_per_sh /= 2; 1307 dev_dbg(adev->dev, "Halving max_cu_per_sh for GC Discovery table v1:3 %d\n", 1308 adev->gfx.config.max_cu_per_sh); 1309 } 1310 } 1311 break; 1312 default: 1313 adev->gfx.mec.num_mec = 2; 1314 adev->gfx.mec.num_pipe_per_mec = 2; 1315 adev->gfx.mec.num_queue_per_pipe = 4; 1316 break; 1317 } 1318 1319 if (adev->gfx.num_compute_rings) { 1320 /* recalculate compute rings to use based on hardware configuration */ 1321 num_compute_rings = (adev->gfx.mec.num_pipe_per_mec * 1322 adev->gfx.mec.num_queue_per_pipe) / 2; 1323 adev->gfx.num_compute_rings = min(adev->gfx.num_compute_rings, 1324 num_compute_rings); 1325 } 1326 1327 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1328 1329 /* EOP Event */ 1330 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, 1331 GFX_12_1_0__SRCID__CP_EOP_INTERRUPT, 1332 &adev->gfx.eop_irq); 1333 if (r) 1334 return r; 1335 1336 /* Privileged reg */ 1337 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, 1338 GFX_12_1_0__SRCID__CP_PRIV_REG_FAULT, 1339 &adev->gfx.priv_reg_irq); 1340 if (r) 1341 return r; 1342 1343 /* Privileged inst */ 1344 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GRBM_CP, 1345 GFX_12_1_0__SRCID__CP_PRIV_INSTR_FAULT, 1346 &adev->gfx.priv_inst_irq); 1347 if (r) 1348 return r; 1349 1350 /* RLC POISON Error */ 1351 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_RLC, 1352 GFX_12_1_0__SRCID__RLC_POISON_INTERRUPT, 1353 &adev->gfx.rlc_poison_irq); 1354 if (r) 1355 return r; 1356 1357 /* pmr ea error */ 1358 r = amdgpu_irq_add_id(adev, SOC_V1_0_IH_CLIENTID_GFX, 1359 GFX_12_1_0__SRCID__PMR_EA_ERROR_INTERRUPT, 1360 &adev->gfx.pmr_ea_irq); 1361 if (r) 1362 return r; 1363 1364 adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE; 1365 1366 r = gfx_v12_1_rlc_init(adev); 1367 if (r) { 1368 dev_err(adev->dev, "Failed to init rlc BOs!\n"); 1369 return r; 1370 } 1371 1372 r = gfx_v12_1_mec_init(adev); 1373 if (r) { 1374 dev_err(adev->dev, "Failed to init MEC BOs!\n"); 1375 return r; 1376 } 1377 1378 /* set up the compute queues - allocate horizontally across pipes */ 1379 for (xcc_id = 0; xcc_id < num_xcc; xcc_id++) { 1380 ring_id = 0; 1381 for (i = 0; i < adev->gfx.mec.num_mec; ++i) { 1382 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) { 1383 for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) { 1384 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 1385 xcc_id, i, k, j)) 1386 continue; 1387 1388 r = gfx_v12_1_compute_ring_init(adev, ring_id, 1389 xcc_id, i, k, j); 1390 if (r) 1391 return r; 1392 1393 ring_id++; 1394 } 1395 } 1396 } 1397 1398 r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v12_1_compute_mqd), xcc_id); 1399 if (r) 1400 return r; 1401 } 1402 1403 /* allocate visible FB for rlc auto-loading fw */ 1404 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 1405 r = gfx_v12_1_rlc_autoload_buffer_init(adev); 1406 if (r) 1407 return r; 1408 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1409 r = gfx_v12_1_init_cp_compute_microcode_bo(adev); 1410 if (r) 1411 return r; 1412 } 1413 1414 r = gfx_v12_1_gpu_early_init(adev); 1415 if (r) 1416 return r; 1417 1418 r = amdgpu_gfx_sysfs_init(adev); 1419 if (r) 1420 return r; 1421 1422 gfx_v12_1_alloc_ip_dump(adev); 1423 1424 adev->gfx.me.use_mmio_for_reset = false; 1425 adev->gfx.mec.use_mmio_for_reset = false; 1426 1427 mutex_init(&adev->gfx.mec.reset_mutex); 1428 1429 return 0; 1430 } 1431 1432 static void gfx_v12_1_rlc_autoload_buffer_fini(struct amdgpu_device *adev) 1433 { 1434 amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo, 1435 &adev->gfx.rlc.rlc_autoload_gpu_addr, 1436 (void **)&adev->gfx.rlc.rlc_autoload_ptr); 1437 } 1438 1439 static int gfx_v12_1_sw_fini(struct amdgpu_ip_block *ip_block) 1440 { 1441 int i, num_xcc; 1442 struct amdgpu_device *adev = ip_block->adev; 1443 1444 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1445 for (i = 0; i < adev->gfx.num_compute_rings * num_xcc; i++) 1446 amdgpu_ring_fini(&adev->gfx.compute_ring[i]); 1447 1448 for (i = 0; i < num_xcc; i++) 1449 amdgpu_gfx_mqd_sw_fini(adev, i); 1450 1451 gfx_v12_1_rlc_fini(adev); 1452 gfx_v12_1_mec_fini(adev); 1453 1454 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) 1455 gfx_v12_1_rlc_autoload_buffer_fini(adev); 1456 1457 gfx_v12_1_free_microcode(adev); 1458 amdgpu_gfx_sysfs_fini(adev); 1459 1460 kfree(adev->gfx.ip_dump_core); 1461 kfree(adev->gfx.ip_dump_compute_queues); 1462 1463 return 0; 1464 } 1465 1466 static void gfx_v12_1_xcc_select_se_sh(struct amdgpu_device *adev, u32 se_num, 1467 u32 sh_num, u32 instance, int xcc_id) 1468 { 1469 u32 data; 1470 1471 if (instance == 0xffffffff) 1472 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, 1473 INSTANCE_BROADCAST_WRITES, 1); 1474 else 1475 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, 1476 instance); 1477 1478 if (se_num == 0xffffffff) 1479 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1480 1); 1481 else 1482 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num); 1483 1484 if (sh_num == 0xffffffff) 1485 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES, 1486 1); 1487 else 1488 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num); 1489 1490 WREG32_SOC15_RLC_SHADOW_EX(reg, GC, GET_INST(GC, xcc_id), regGRBM_GFX_INDEX, data); 1491 } 1492 1493 static u32 gfx_v12_1_get_sa_active_bitmap(struct amdgpu_device *adev, 1494 int xcc_id) 1495 { 1496 u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask; 1497 1498 gc_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SA_UNIT_DISABLE); 1499 gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask, 1500 CC_GC_SA_UNIT_DISABLE, 1501 SA_DISABLE); 1502 gc_user_disabled_sa_mask = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SA_UNIT_DISABLE); 1503 gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask, 1504 GC_USER_SA_UNIT_DISABLE, 1505 SA_DISABLE); 1506 sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se * 1507 adev->gfx.config.max_shader_engines); 1508 1509 return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask)); 1510 } 1511 1512 static u32 gfx_v12_1_get_sh_mem_config(struct amdgpu_device *adev) 1513 { 1514 u32 sh_mem_config = DEFAULT_SH_MEM_CONFIG; 1515 1516 /* GC 12.1.0 A0 requires RETRY_DISABLE in SH_MEM_CONFIG. */ 1517 if (SOC_V1_0_DIE_REV_XCD(adev->rev_id) == 0) 1518 sh_mem_config |= 1 << SH_MEM_CONFIG__RETRY_DISABLE__SHIFT; 1519 1520 return sh_mem_config; 1521 } 1522 1523 static void gfx_v12_1_xcc_init_compute_vmid(struct amdgpu_device *adev, 1524 int xcc_id) 1525 { 1526 int i; 1527 uint32_t sh_mem_bases; 1528 uint32_t sh_mem_config; 1529 uint32_t data; 1530 1531 /* 1532 * Configure apertures: 1533 * LDS: 0x20000000'00000000 - 0x20000001'00000000 (4GB) 1534 * Scratch: 0x10000000'00000000 - 0x11ffffff'ffffffff (128PB 57-bit) 1535 */ 1536 sh_mem_bases = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1537 (adev->gmc.private_aperture_start >> 58)); 1538 sh_mem_bases = REG_SET_FIELD(sh_mem_bases, SH_MEM_BASES, SHARED_BASE, 1539 (adev->gmc.shared_aperture_start >> 48)); 1540 sh_mem_config = gfx_v12_1_get_sh_mem_config(adev); 1541 1542 mutex_lock(&adev->srbm_mutex); 1543 for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) { 1544 soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1545 /* CP and shaders */ 1546 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_CONFIG, sh_mem_config); 1547 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, sh_mem_bases); 1548 1549 /* Enable trap for each kfd vmid. */ 1550 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL); 1551 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1); 1552 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSPI_GDBG_PER_VMID_CNTL, data); 1553 1554 /* Disable VGPR deallocation instruction for each KFD vmid. */ 1555 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG); 1556 data = REG_SET_FIELD(data, SQ_DEBUG, DISABLE_VGPR_DEALLOC, 1); 1557 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSQ_DEBUG, data); 1558 } 1559 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1560 mutex_unlock(&adev->srbm_mutex); 1561 } 1562 1563 static void gfx_v12_1_xcc_xnack_set_chicken_bits(struct amdgpu_device *adev, int xcc_id) 1564 { 1565 /* NOTE: COMPRESSION_ENABLE is used a chicken bit to enable/disable xcc xnack */ 1566 mutex_lock(&adev->srbm_mutex); 1567 if (!adev->gmc.noretry) { 1568 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1569 TCP_PERFCOUNTER_FILTER, COMPRESSION_ENABLE, 0x1); 1570 } else 1571 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1572 TCP_PERFCOUNTER_FILTER, COMPRESSION_ENABLE, 0x0); 1573 mutex_unlock(&adev->srbm_mutex); 1574 } 1575 1576 static void gfx_v12_1_xcc_constants_init(struct amdgpu_device *adev, 1577 int xcc_id) 1578 { 1579 u32 tmp; 1580 u32 sh_mem_config; 1581 int i; 1582 1583 sh_mem_config = gfx_v12_1_get_sh_mem_config(adev); 1584 1585 /* XXX SH_MEM regs */ 1586 /* where to put LDS, scratch, GPUVM in FSA64 space */ 1587 mutex_lock(&adev->srbm_mutex); 1588 for_each_vmid_and_zero(i, adev, AMDGPU_GFXHUB(0)) { 1589 soc_v1_0_grbm_select(adev, 0, 0, 0, i, GET_INST(GC, xcc_id)); 1590 /* CP and shaders */ 1591 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1592 regSH_MEM_CONFIG, sh_mem_config); 1593 if (i != 0) { 1594 tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE, 1595 (adev->gmc.private_aperture_start >> 58)); 1596 tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE, 1597 (adev->gmc.shared_aperture_start >> 48)); 1598 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regSH_MEM_BASES, tmp); 1599 } 1600 } 1601 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1602 1603 mutex_unlock(&adev->srbm_mutex); 1604 1605 gfx_v12_1_xcc_init_compute_vmid(adev, xcc_id); 1606 gfx_v12_1_xcc_xnack_set_chicken_bits(adev, xcc_id); 1607 1608 } 1609 1610 static void gfx_v12_1_constants_init(struct amdgpu_device *adev) 1611 { 1612 int i, num_xcc; 1613 1614 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1615 1616 gfx_v12_1_get_cu_info(adev, &adev->gfx.cu_info); 1617 adev->gfx.config.pa_sc_tile_steering_override = 0; 1618 1619 for (i = 0; i < num_xcc; i++) 1620 gfx_v12_1_xcc_constants_init(adev, i); 1621 } 1622 1623 static void gfx_v12_1_xcc_enable_gui_idle_interrupt(struct amdgpu_device *adev, 1624 bool enable, int xcc_id) 1625 { 1626 u32 tmp; 1627 1628 if (amdgpu_sriov_vf(adev)) 1629 return; 1630 1631 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0); 1632 1633 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, 1634 enable ? 1 : 0); 1635 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, 1636 enable ? 1 : 0); 1637 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, 1638 enable ? 1 : 0); 1639 tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, 1640 enable ? 1 : 0); 1641 1642 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL_RING0, tmp); 1643 } 1644 1645 static int gfx_v12_1_xcc_init_csb(struct amdgpu_device *adev, 1646 int xcc_id) 1647 { 1648 adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr); 1649 1650 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CSIB_ADDR_HI, 1651 adev->gfx.rlc.clear_state_gpu_addr >> 32); 1652 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CSIB_ADDR_LO, 1653 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc); 1654 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1655 regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size); 1656 1657 return 0; 1658 } 1659 1660 static void gfx_v12_1_xcc_rlc_stop(struct amdgpu_device *adev, 1661 int xcc_id) 1662 { 1663 u32 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL); 1664 1665 tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0); 1666 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CNTL, tmp); 1667 } 1668 1669 static void gfx_v12_1_rlc_stop(struct amdgpu_device *adev) 1670 { 1671 int i, num_xcc; 1672 1673 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1674 for (i = 0; i < num_xcc; i++) 1675 gfx_v12_1_xcc_rlc_stop(adev, i); 1676 } 1677 1678 static void gfx_v12_1_xcc_rlc_reset(struct amdgpu_device *adev, 1679 int xcc_id) 1680 { 1681 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1682 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1); 1683 udelay(50); 1684 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), 1685 GRBM_SOFT_RESET, SOFT_RESET_RLC, 0); 1686 udelay(50); 1687 } 1688 1689 static void gfx_v12_1_rlc_reset(struct amdgpu_device *adev) 1690 { 1691 int i, num_xcc; 1692 1693 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1694 for (i = 0; i < num_xcc; i++) 1695 gfx_v12_1_xcc_rlc_reset(adev, i); 1696 } 1697 1698 static void gfx_v12_1_xcc_rlc_smu_handshake_cntl(struct amdgpu_device *adev, 1699 bool enable, int xcc_id) 1700 { 1701 uint32_t rlc_pg_cntl; 1702 1703 rlc_pg_cntl = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL); 1704 1705 if (!enable) { 1706 /* RLC_PG_CNTL[23] = 0 (default) 1707 * RLC will wait for handshake acks with SMU 1708 * GFXOFF will be enabled 1709 * RLC_PG_CNTL[23] = 1 1710 * RLC will not issue any message to SMU 1711 * hence no handshake between SMU & RLC 1712 * GFXOFF will be disabled 1713 */ 1714 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1715 } else 1716 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK; 1717 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL, rlc_pg_cntl); 1718 } 1719 1720 static void gfx_v12_1_xcc_rlc_start(struct amdgpu_device *adev, 1721 int xcc_id) 1722 { 1723 /* TODO: enable rlc & smu handshake until smu 1724 * and gfxoff feature works as expected */ 1725 if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK)) 1726 gfx_v12_1_xcc_rlc_smu_handshake_cntl(adev, false, xcc_id); 1727 1728 WREG32_FIELD15_PREREG(GC, GET_INST(GC, xcc_id), RLC_CNTL, RLC_ENABLE_F32, 1); 1729 udelay(50); 1730 } 1731 1732 static void gfx_v12_1_rlc_start(struct amdgpu_device *adev) 1733 { 1734 int i, num_xcc; 1735 1736 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1737 for (i = 0; i < num_xcc; i++) { 1738 gfx_v12_1_xcc_rlc_start(adev, i); 1739 } 1740 } 1741 1742 static void gfx_v12_1_xcc_rlc_enable_srm(struct amdgpu_device *adev, 1743 int xcc_id) 1744 { 1745 uint32_t tmp; 1746 1747 /* enable Save Restore Machine */ 1748 tmp = RREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL)); 1749 tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK; 1750 tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK; 1751 WREG32(SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SRM_CNTL), tmp); 1752 } 1753 1754 static void gfx_v12_1_xcc_load_rlcg_microcode(struct amdgpu_device *adev, 1755 int xcc_id) 1756 { 1757 const struct rlc_firmware_header_v2_0 *hdr; 1758 const __le32 *fw_data; 1759 unsigned i, fw_size; 1760 1761 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1762 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1763 le32_to_cpu(hdr->header.ucode_array_offset_bytes)); 1764 fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4; 1765 1766 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_GPM_UCODE_ADDR, 1767 RLCG_UCODE_LOADING_START_ADDRESS); 1768 1769 for (i = 0; i < fw_size; i++) 1770 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1771 regRLC_GPM_UCODE_DATA, 1772 le32_to_cpup(fw_data++)); 1773 1774 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1775 regRLC_GPM_UCODE_ADDR, 1776 adev->gfx.rlc_fw_version); 1777 } 1778 1779 static void gfx_v12_1_xcc_load_rlc_iram_dram_microcode(struct amdgpu_device *adev, 1780 int xcc_id) 1781 { 1782 const struct rlc_firmware_header_v2_2 *hdr; 1783 const __le32 *fw_data; 1784 unsigned i, fw_size; 1785 u32 tmp; 1786 1787 hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data; 1788 1789 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1790 le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes)); 1791 fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4; 1792 1793 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_IRAM_ADDR, 0); 1794 1795 for (i = 0; i < fw_size; i++) { 1796 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1797 msleep(1); 1798 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1799 regRLC_LX6_IRAM_DATA, 1800 le32_to_cpup(fw_data++)); 1801 } 1802 1803 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1804 regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1805 1806 fw_data = (const __le32 *)(adev->gfx.rlc_fw->data + 1807 le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes)); 1808 fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4; 1809 1810 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1811 regRLC_LX6_DRAM_ADDR, 0); 1812 for (i = 0; i < fw_size; i++) { 1813 if ((amdgpu_emu_mode == 1) && (i % 100 == 99)) 1814 msleep(1); 1815 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1816 regRLC_LX6_DRAM_DATA, 1817 le32_to_cpup(fw_data++)); 1818 } 1819 1820 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 1821 regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version); 1822 1823 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL); 1824 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1); 1825 tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0); 1826 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_LX6_CNTL, tmp); 1827 } 1828 1829 static int gfx_v12_1_xcc_rlc_load_microcode(struct amdgpu_device *adev, 1830 int xcc_id) 1831 { 1832 const struct rlc_firmware_header_v2_0 *hdr; 1833 uint16_t version_major; 1834 uint16_t version_minor; 1835 1836 if (!adev->gfx.rlc_fw) 1837 return -EINVAL; 1838 1839 hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data; 1840 amdgpu_ucode_print_rlc_hdr(&hdr->header); 1841 1842 version_major = le16_to_cpu(hdr->header.header_version_major); 1843 version_minor = le16_to_cpu(hdr->header.header_version_minor); 1844 1845 if (version_major == 2) { 1846 gfx_v12_1_xcc_load_rlcg_microcode(adev, xcc_id); 1847 if (amdgpu_dpm == 1) { 1848 if (version_minor >= 2) 1849 gfx_v12_1_xcc_load_rlc_iram_dram_microcode(adev, xcc_id); 1850 } 1851 1852 return 0; 1853 } 1854 1855 return -EINVAL; 1856 } 1857 1858 static int gfx_v12_1_xcc_rlc_resume(struct amdgpu_device *adev, 1859 int xcc_id) 1860 { 1861 int r; 1862 1863 /* init spm vmid with 0xf */ 1864 gfx_v12_1_update_spm_vmid(adev, xcc_id, NULL, 0xf); 1865 1866 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { 1867 gfx_v12_1_xcc_init_csb(adev, xcc_id); 1868 1869 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */ 1870 gfx_v12_1_xcc_rlc_enable_srm(adev, xcc_id); 1871 } else { 1872 if (amdgpu_sriov_vf(adev)) { 1873 gfx_v12_1_xcc_init_csb(adev, xcc_id); 1874 return 0; 1875 } 1876 1877 gfx_v12_1_xcc_rlc_stop(adev, xcc_id); 1878 1879 /* disable CG */ 1880 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, 0); 1881 1882 /* disable PG */ 1883 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_PG_CNTL, 0); 1884 1885 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 1886 /* legacy rlc firmware loading */ 1887 r = gfx_v12_1_xcc_rlc_load_microcode(adev, xcc_id); 1888 if (r) 1889 return r; 1890 } 1891 1892 gfx_v12_1_xcc_init_csb(adev, xcc_id); 1893 1894 gfx_v12_1_xcc_rlc_start(adev, xcc_id); 1895 } 1896 1897 return 0; 1898 } 1899 1900 static int gfx_v12_1_rlc_resume(struct amdgpu_device *adev) 1901 { 1902 int r, i, num_xcc; 1903 1904 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1905 for (i = 0; i < num_xcc; i++) { 1906 r = gfx_v12_1_xcc_rlc_resume(adev, i); 1907 if (r) 1908 return r; 1909 } 1910 1911 return 0; 1912 } 1913 1914 static void gfx_v12_1_xcc_config_gfx_rs64(struct amdgpu_device *adev, 1915 int xcc_id) 1916 { 1917 const struct gfx_firmware_header_v2_0 *mec_hdr; 1918 uint32_t pipe_id, tmp; 1919 1920 mec_hdr = (const struct gfx_firmware_header_v2_0 *) 1921 adev->gfx.mec_fw->data; 1922 1923 /* config mec program start addr */ 1924 for (pipe_id = 0; pipe_id < 4; pipe_id++) { 1925 soc_v1_0_grbm_select(adev, 1, pipe_id, 0, 0, GET_INST(GC, xcc_id)); 1926 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START, 1927 mec_hdr->ucode_start_addr_lo >> 2 | 1928 mec_hdr->ucode_start_addr_hi << 30); 1929 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI, 1930 mec_hdr->ucode_start_addr_hi >> 2); 1931 } 1932 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1933 1934 /* reset mec pipe */ 1935 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); 1936 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1); 1937 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1); 1938 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1); 1939 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1); 1940 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp); 1941 1942 /* clear mec pipe reset */ 1943 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0); 1944 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0); 1945 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0); 1946 tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0); 1947 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, tmp); 1948 } 1949 1950 static void gfx_v12_1_config_gfx_rs64(struct amdgpu_device *adev) 1951 { 1952 int i, num_xcc; 1953 1954 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 1955 1956 for (i = 0; i < num_xcc; i++) 1957 gfx_v12_1_xcc_config_gfx_rs64(adev, i); 1958 } 1959 1960 static void gfx_v12_1_xcc_set_mec_ucode_start_addr(struct amdgpu_device *adev, 1961 int xcc_id) 1962 { 1963 const struct gfx_firmware_header_v2_0 *cp_hdr; 1964 unsigned pipe_id; 1965 1966 cp_hdr = (const struct gfx_firmware_header_v2_0 *) 1967 adev->gfx.mec_fw->data; 1968 mutex_lock(&adev->srbm_mutex); 1969 for (pipe_id = 0; pipe_id < adev->gfx.mec.num_pipe_per_mec; pipe_id++) { 1970 soc_v1_0_grbm_select(adev, 1, pipe_id, 0, 0, GET_INST(GC, xcc_id)); 1971 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START, 1972 cp_hdr->ucode_start_addr_lo >> 2 | 1973 cp_hdr->ucode_start_addr_hi << 30); 1974 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_PRGRM_CNTR_START_HI, 1975 cp_hdr->ucode_start_addr_hi >> 2); 1976 } 1977 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 1978 mutex_unlock(&adev->srbm_mutex); 1979 } 1980 1981 static int gfx_v12_1_xcc_wait_for_rlc_autoload_complete(struct amdgpu_device *adev, 1982 int xcc_id) 1983 { 1984 uint32_t cp_status; 1985 uint32_t bootload_status; 1986 int i; 1987 1988 for (i = 0; i < adev->usec_timeout; i++) { 1989 cp_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_STAT); 1990 bootload_status = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 1991 regRLC_RLCS_BOOTLOAD_STATUS); 1992 1993 if ((cp_status == 0) && 1994 (REG_GET_FIELD(bootload_status, 1995 RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) { 1996 break; 1997 } 1998 udelay(1); 1999 if (amdgpu_emu_mode) 2000 msleep(10); 2001 } 2002 2003 if (i >= adev->usec_timeout) { 2004 dev_err(adev->dev, 2005 "rlc autoload: xcc%d gc ucode autoload timeout\n", xcc_id); 2006 return -ETIMEDOUT; 2007 } 2008 2009 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2010 gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id); 2011 } 2012 2013 return 0; 2014 } 2015 2016 static int gfx_v12_1_wait_for_rlc_autoload_complete(struct amdgpu_device *adev) 2017 { 2018 int xcc_id; 2019 2020 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) 2021 gfx_v12_1_xcc_wait_for_rlc_autoload_complete(adev, xcc_id); 2022 2023 return 0; 2024 } 2025 2026 static void gfx_v12_1_xcc_cp_compute_enable(struct amdgpu_device *adev, 2027 bool enable, int xcc_id) 2028 { 2029 u32 data; 2030 2031 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL); 2032 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE, 2033 enable ? 0 : 1); 2034 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 2035 enable ? 0 : 1); 2036 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 2037 enable ? 0 : 1); 2038 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 2039 enable ? 0 : 1); 2040 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 2041 enable ? 0 : 1); 2042 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE, 2043 enable ? 1 : 0); 2044 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE, 2045 enable ? 1 : 0); 2046 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE, 2047 enable ? 1 : 0); 2048 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE, 2049 enable ? 1 : 0); 2050 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT, 2051 enable ? 0 : 1); 2052 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_RS64_CNTL, data); 2053 2054 udelay(50); 2055 } 2056 2057 static int gfx_v12_1_init_cp_compute_microcode_bo(struct amdgpu_device *adev) 2058 { 2059 const struct gfx_firmware_header_v2_0 *mec_hdr; 2060 const __le32 *fw_ucode, *fw_data; 2061 u32 fw_ucode_size, fw_data_size; 2062 u32 *fw_ucode_ptr, *fw_data_ptr; 2063 int i, r, xcc_id; 2064 2065 if (!adev->gfx.mec_fw) 2066 return -EINVAL; 2067 2068 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2069 amdgpu_ucode_print_gfx_hdr(&mec_hdr->header); 2070 2071 fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data + 2072 le32_to_cpu(mec_hdr->ucode_offset_bytes)); 2073 fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes); 2074 2075 fw_data = (const __le32 *) (adev->gfx.mec_fw->data + 2076 le32_to_cpu(mec_hdr->data_offset_bytes)); 2077 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2078 2079 if (adev->gfx.mec.mec_fw_obj == NULL) { 2080 r = amdgpu_bo_create_reserved(adev, fw_ucode_size, 2081 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2082 &adev->gfx.mec.mec_fw_obj, 2083 &adev->gfx.mec.mec_fw_gpu_addr, 2084 (void **)&fw_ucode_ptr); 2085 if (r) { 2086 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r); 2087 gfx_v12_1_mec_fini(adev); 2088 return r; 2089 } 2090 2091 memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size); 2092 2093 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj); 2094 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj); 2095 } 2096 2097 if (adev->gfx.mec.mec_fw_data_obj == NULL) { 2098 r = amdgpu_bo_create_reserved(adev, 2099 ALIGN(fw_data_size, 64 * 1024) * 2100 adev->gfx.mec.num_pipe_per_mec * NUM_XCC(adev->gfx.xcc_mask), 2101 64 * 1024, AMDGPU_GEM_DOMAIN_VRAM, 2102 &adev->gfx.mec.mec_fw_data_obj, 2103 &adev->gfx.mec.mec_fw_data_gpu_addr, 2104 (void **)&fw_data_ptr); 2105 if (r) { 2106 dev_err(adev->dev, "(%d) failed to create mec fw data bo\n", r); 2107 gfx_v12_1_mec_fini(adev); 2108 return r; 2109 } 2110 2111 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 2112 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2113 u32 offset = (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * 2114 ALIGN(fw_data_size, 64 * 1024) / 4; 2115 memcpy(fw_data_ptr + offset, fw_data, fw_data_size); 2116 } 2117 } 2118 2119 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj); 2120 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj); 2121 } 2122 2123 return 0; 2124 } 2125 2126 static int gfx_v12_1_xcc_cp_compute_load_microcode_rs64(struct amdgpu_device *adev, 2127 int xcc_id) 2128 { 2129 const struct gfx_firmware_header_v2_0 *mec_hdr; 2130 u32 fw_data_size; 2131 u32 tmp, i, usec_timeout = 50000; /* Wait for 50 ms */ 2132 2133 if (!adev->gfx.mec_fw) 2134 return -EINVAL; 2135 2136 mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data; 2137 fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes); 2138 2139 gfx_v12_1_xcc_cp_compute_enable(adev, false, xcc_id); 2140 2141 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL); 2142 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0); 2143 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0); 2144 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0); 2145 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_CNTL, tmp); 2146 2147 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL); 2148 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0); 2149 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0); 2150 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_BASE_CNTL, tmp); 2151 2152 mutex_lock(&adev->srbm_mutex); 2153 for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) { 2154 soc_v1_0_grbm_select(adev, 1, i, 0, 0, GET_INST(GC, xcc_id)); 2155 2156 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_LO, 2157 lower_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2158 (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * 2159 ALIGN(fw_data_size, 64 * 1024))); 2160 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_MDBASE_HI, 2161 upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr + 2162 (xcc_id * adev->gfx.mec.num_pipe_per_mec + i) * 2163 ALIGN(fw_data_size, 64 * 1024))); 2164 2165 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_LO, 2166 lower_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2167 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_BASE_HI, 2168 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr)); 2169 } 2170 mutex_unlock(&adev->srbm_mutex); 2171 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2172 2173 /* Trigger an invalidation of the L1 instruction caches */ 2174 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL); 2175 tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1); 2176 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL, tmp); 2177 2178 /* Wait for invalidation complete */ 2179 for (i = 0; i < usec_timeout; i++) { 2180 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DC_OP_CNTL); 2181 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL, 2182 INVALIDATE_DCACHE_COMPLETE)) 2183 break; 2184 udelay(1); 2185 } 2186 2187 if (i >= usec_timeout) { 2188 dev_err(adev->dev, "failed to invalidate data cache\n"); 2189 return -EINVAL; 2190 } 2191 2192 /* Trigger an invalidation of the L1 instruction caches */ 2193 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL); 2194 tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1); 2195 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL, tmp); 2196 2197 /* Wait for invalidation complete */ 2198 for (i = 0; i < usec_timeout; i++) { 2199 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_CPC_IC_OP_CNTL); 2200 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL, 2201 INVALIDATE_CACHE_COMPLETE)) 2202 break; 2203 udelay(1); 2204 } 2205 2206 if (i >= usec_timeout) { 2207 dev_err(adev->dev, "failed to invalidate instruction cache\n"); 2208 return -EINVAL; 2209 } 2210 2211 gfx_v12_1_xcc_set_mec_ucode_start_addr(adev, xcc_id); 2212 2213 return 0; 2214 } 2215 2216 static void gfx_v12_1_xcc_cp_set_doorbell_range(struct amdgpu_device *adev, 2217 int xcc_id) 2218 { 2219 /* disable gfx engine doorbell range */ 2220 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_LOWER, 0); 2221 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_DOORBELL_RANGE_UPPER, 0); 2222 2223 /* set compute engine doorbell range */ 2224 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_LOWER, 2225 ((adev->doorbell_index.kiq + 2226 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2227 2) << 2); 2228 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_MEC_DOORBELL_RANGE_UPPER, 2229 ((adev->doorbell_index.userqueue_end + 2230 xcc_id * adev->doorbell_index.xcc_doorbell_range) * 2231 2) << 2); 2232 } 2233 2234 static int gfx_v12_1_compute_mqd_init(struct amdgpu_device *adev, void *m, 2235 struct amdgpu_mqd_prop *prop) 2236 { 2237 struct v12_1_compute_mqd *mqd = m; 2238 uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr; 2239 uint32_t tmp; 2240 2241 mqd->header = 0xC0310800; 2242 mqd->compute_pipelinestat_enable = 0x00000001; 2243 mqd->compute_static_thread_mgmt_se0 = 0xffffffff; 2244 mqd->compute_static_thread_mgmt_se1 = 0xffffffff; 2245 mqd->compute_static_thread_mgmt_se2 = 0xffffffff; 2246 mqd->compute_static_thread_mgmt_se3 = 0xffffffff; 2247 mqd->compute_misc_reserved = 0x00000007; 2248 2249 eop_base_addr = prop->eop_gpu_addr >> 8; 2250 mqd->cp_hqd_eop_base_addr_lo = eop_base_addr; 2251 mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr); 2252 2253 /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */ 2254 tmp = regCP_HQD_EOP_CONTROL_DEFAULT; 2255 tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE, 2256 (order_base_2(GFX12_MEC_HPD_SIZE / 4) - 1)); 2257 2258 mqd->cp_hqd_eop_control = tmp; 2259 2260 /* enable doorbell? */ 2261 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 2262 2263 if (prop->use_doorbell) { 2264 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2265 DOORBELL_OFFSET, prop->doorbell_index); 2266 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2267 DOORBELL_EN, 1); 2268 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2269 DOORBELL_SOURCE, 0); 2270 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2271 DOORBELL_HIT, 0); 2272 } else { 2273 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2274 DOORBELL_EN, 0); 2275 } 2276 2277 mqd->cp_hqd_pq_doorbell_control = tmp; 2278 2279 /* disable the queue if it's active */ 2280 mqd->cp_hqd_dequeue_request = 0; 2281 mqd->cp_hqd_pq_rptr = 0; 2282 mqd->cp_hqd_pq_wptr_lo = 0; 2283 mqd->cp_hqd_pq_wptr_hi = 0; 2284 2285 /* set the pointer to the MQD */ 2286 mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc; 2287 mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr); 2288 2289 /* set MQD vmid to 0 */ 2290 tmp = regCP_MQD_CONTROL_DEFAULT; 2291 tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0); 2292 mqd->cp_mqd_control = tmp; 2293 2294 /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */ 2295 hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8; 2296 mqd->cp_hqd_pq_base_lo = hqd_gpu_addr; 2297 mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr); 2298 2299 /* set up the HQD, this is similar to CP_RB0_CNTL */ 2300 tmp = regCP_HQD_PQ_CONTROL_DEFAULT; 2301 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE, 2302 (order_base_2(prop->queue_size / 4) - 1)); 2303 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE, 2304 (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1)); 2305 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0); 2306 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, SCOPE, 3); 2307 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0); 2308 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1); 2309 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1); 2310 mqd->cp_hqd_pq_control = tmp; 2311 2312 /* set the wb address whether it's enabled or not */ 2313 wb_gpu_addr = prop->rptr_gpu_addr; 2314 mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc; 2315 mqd->cp_hqd_pq_rptr_report_addr_hi = 2316 upper_32_bits(wb_gpu_addr) & 0xffff; 2317 2318 /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */ 2319 wb_gpu_addr = prop->wptr_gpu_addr; 2320 mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc; 2321 mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff; 2322 2323 tmp = 0; 2324 /* enable the doorbell if requested */ 2325 if (prop->use_doorbell) { 2326 tmp = regCP_HQD_PQ_DOORBELL_CONTROL_DEFAULT; 2327 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2328 DOORBELL_OFFSET, prop->doorbell_index); 2329 2330 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2331 DOORBELL_EN, 1); 2332 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2333 DOORBELL_SOURCE, 0); 2334 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL, 2335 DOORBELL_HIT, 0); 2336 } 2337 2338 mqd->cp_hqd_pq_doorbell_control = tmp; 2339 2340 /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */ 2341 mqd->cp_hqd_pq_rptr = regCP_HQD_PQ_RPTR_DEFAULT; 2342 2343 /* set the vmid for the queue */ 2344 mqd->cp_hqd_vmid = 0; 2345 2346 tmp = regCP_HQD_PERSISTENT_STATE_DEFAULT; 2347 tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x63); 2348 mqd->cp_hqd_persistent_state = tmp; 2349 2350 /* set MIN_IB_AVAIL_SIZE */ 2351 tmp = regCP_HQD_IB_CONTROL_DEFAULT; 2352 tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 1); 2353 mqd->cp_hqd_ib_control = tmp; 2354 2355 /* set static priority for a compute queue/ring */ 2356 mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority; 2357 mqd->cp_hqd_queue_priority = prop->hqd_queue_priority; 2358 2359 mqd->cp_mqd_stride_size = prop->mqd_stride_size ? prop->mqd_stride_size : 2360 AMDGPU_MQD_SIZE_ALIGN(adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size); 2361 2362 tmp = REG_SET_FIELD(0, CP_HQD_QUANTUM, QUANTUM_EN, 1); 2363 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_SCALE, 1); 2364 tmp = REG_SET_FIELD(tmp, CP_HQD_QUANTUM, QUANTUM_DURATION, 1); 2365 mqd->cp_hqd_quantum = tmp; 2366 2367 mqd->cp_hqd_active = prop->hqd_active; 2368 2369 return 0; 2370 } 2371 2372 static int gfx_v12_1_xcc_kcq_init_queue(struct amdgpu_ring *ring, 2373 int xcc_id) 2374 { 2375 struct amdgpu_device *adev = ring->adev; 2376 struct v12_1_compute_mqd *mqd = ring->mqd_ptr; 2377 int mqd_idx = ring - &adev->gfx.compute_ring[0]; 2378 2379 if (!amdgpu_in_reset(adev) && !adev->in_suspend) { 2380 memset((void *)mqd, 0, sizeof(*mqd)); 2381 mutex_lock(&adev->srbm_mutex); 2382 soc_v1_0_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0, GET_INST(GC, xcc_id)); 2383 amdgpu_ring_init_mqd(ring); 2384 soc_v1_0_grbm_select(adev, 0, 0, 0, 0, GET_INST(GC, xcc_id)); 2385 mutex_unlock(&adev->srbm_mutex); 2386 2387 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2388 memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd)); 2389 } else { 2390 /* restore MQD to a clean status */ 2391 if (adev->gfx.mec.mqd_backup[mqd_idx]) 2392 memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd)); 2393 /* reset ring buffer */ 2394 ring->wptr = 0; 2395 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0); 2396 amdgpu_ring_clear_ring(ring); 2397 } 2398 2399 return 0; 2400 } 2401 2402 static int gfx_v12_1_xcc_kcq_resume(struct amdgpu_device *adev, 2403 int xcc_id) 2404 { 2405 struct amdgpu_ring *ring = NULL; 2406 int r = 0, i; 2407 2408 if (!amdgpu_async_gfx_ring) 2409 gfx_v12_1_xcc_cp_compute_enable(adev, true, xcc_id); 2410 2411 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2412 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2413 2414 r = amdgpu_bo_reserve(ring->mqd_obj, false); 2415 if (unlikely(r != 0)) 2416 goto done; 2417 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr); 2418 if (!r) { 2419 r = gfx_v12_1_xcc_kcq_init_queue(ring, xcc_id); 2420 amdgpu_bo_kunmap(ring->mqd_obj); 2421 ring->mqd_ptr = NULL; 2422 } 2423 amdgpu_bo_unreserve(ring->mqd_obj); 2424 if (r) 2425 goto done; 2426 } 2427 2428 r = amdgpu_gfx_enable_kcq(adev, xcc_id); 2429 done: 2430 return r; 2431 } 2432 2433 static int gfx_v12_1_xcc_cp_resume(struct amdgpu_device *adev, uint16_t xcc_mask) 2434 { 2435 int r, i, xcc_id; 2436 struct amdgpu_ring *ring; 2437 2438 if (!adev->mes.kiq_hw_init) 2439 return -EINVAL; 2440 2441 for_each_inst(xcc_id, xcc_mask) { 2442 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2443 /* legacy firmware loading */ 2444 r = gfx_v12_1_xcc_cp_compute_load_microcode_rs64(adev, xcc_id); 2445 if (r) 2446 return r; 2447 } 2448 2449 /* MGCG is device wide and owned by the PF */ 2450 if (!amdgpu_sriov_vf(adev)) 2451 gfx_v12_1_xcc_update_medium_grain_clock_gating(adev, false, 2452 xcc_id, true); 2453 /* GFX CGCG and LS is disabled by rlc fw */ 2454 gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2455 2456 gfx_v12_1_xcc_cp_set_doorbell_range(adev, xcc_id); 2457 2458 gfx_v12_1_xcc_cp_compute_enable(adev, true, xcc_id); 2459 2460 r = amdgpu_mes_kiq_hw_init(adev, xcc_id); 2461 if (r) 2462 return r; 2463 2464 r = gfx_v12_1_xcc_kcq_resume(adev, xcc_id); 2465 if (r) 2466 return r; 2467 2468 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 2469 ring = &adev->gfx.compute_ring[i + xcc_id * adev->gfx.num_compute_rings]; 2470 r = amdgpu_ring_test_helper(ring); 2471 if (r) 2472 return r; 2473 } 2474 if (!amdgpu_sriov_vf(adev)) 2475 gfx_v12_1_xcc_update_medium_grain_clock_gating(adev, true, 2476 xcc_id, true); 2477 } 2478 2479 return 0; 2480 } 2481 2482 static int gfx_v12_1_cp_resume(struct amdgpu_device *adev) 2483 { 2484 int num_xcc, num_xcp, num_xcc_per_xcp; 2485 uint16_t xcc_mask; 2486 int r = 0; 2487 2488 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2489 if (amdgpu_sriov_vf(adev)) { 2490 enum amdgpu_gfx_partition mode; 2491 2492 mode = amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2493 AMDGPU_XCP_FL_NONE); 2494 if (mode == AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2495 return -EINVAL; 2496 if (adev->gfx.funcs && 2497 adev->gfx.funcs->get_xccs_per_xcp) { 2498 num_xcc_per_xcp = adev->gfx.funcs->get_xccs_per_xcp(adev); 2499 adev->gfx.num_xcc_per_xcp = num_xcc_per_xcp; 2500 num_xcp = num_xcc / num_xcc_per_xcp; 2501 } else { 2502 return -EINVAL; 2503 } 2504 r = amdgpu_xcp_init(adev->xcp_mgr, num_xcp, mode); 2505 2506 } else { 2507 if (amdgpu_xcp_query_partition_mode(adev->xcp_mgr, 2508 AMDGPU_XCP_FL_NONE) == 2509 AMDGPU_UNKNOWN_COMPUTE_PARTITION_MODE) 2510 r = amdgpu_xcp_switch_partition_mode(adev->xcp_mgr, 2511 amdgpu_user_partt_mode); 2512 } 2513 2514 if (r) 2515 return r; 2516 2517 xcc_mask = GENMASK(NUM_XCC(adev->gfx.xcc_mask) - 1, 0); 2518 2519 return gfx_v12_1_xcc_cp_resume(adev, xcc_mask); 2520 } 2521 2522 static int gfx_v12_1_gfxhub_enable(struct amdgpu_device *adev) 2523 { 2524 int r, i; 2525 bool value; 2526 2527 r = adev->gfxhub.funcs->gart_enable(adev); 2528 if (r) 2529 return r; 2530 2531 value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ? 2532 false : true; 2533 2534 adev->gfxhub.funcs->set_fault_enable_default(adev, value); 2535 /* TODO investigate why TLB flush is needed, 2536 * are we missing a flush somewhere else? */ 2537 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) { 2538 if (AMDGPU_IS_GFXHUB(i)) 2539 adev->gmc.gmc_funcs->flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(i), 0); 2540 } 2541 2542 return 0; 2543 } 2544 2545 static void gfx_v12_1_xcc_disable_gpa_mode(struct amdgpu_device *adev, 2546 int xcc_id) 2547 { 2548 uint32_t data; 2549 2550 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG); 2551 data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK; 2552 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPC_PSP_DEBUG, data); 2553 2554 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG); 2555 data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK; 2556 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCPG_PSP_DEBUG, data); 2557 } 2558 2559 static void gfx_v12_1_xcc_enable_atomics(struct amdgpu_device *adev, 2560 int xcc_id) 2561 { 2562 uint32_t data; 2563 2564 /* Set the TCP UTCL0 register to enable atomics */ 2565 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1); 2566 data = REG_SET_FIELD(data, TCP_UTCL0_CNTL1, ATOMIC_REQUESTER_EN, 0x1); 2567 2568 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_UTCL0_CNTL1, data); 2569 } 2570 2571 static void gfx_v12_1_xcc_disable_burst(struct amdgpu_device *adev, 2572 int xcc_id) 2573 { 2574 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGL1_DRAM_BURST_CTRL, 0xf); 2575 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGLARB_DRAM_BURST_CTRL, 0xf); 2576 } 2577 2578 static void gfx_v12_1_xcc_disable_early_write_ack(struct amdgpu_device *adev, 2579 int xcc_id) 2580 { 2581 uint32_t data; 2582 2583 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3); 2584 data = REG_SET_FIELD(data, TCP_CNTL3, DISABLE_EARLY_WRITE_ACK, 0x1); 2585 2586 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL3, data); 2587 } 2588 2589 static void gfx_v12_1_xcc_disable_tcp_spill_cache(struct amdgpu_device *adev, 2590 int xcc_id) 2591 { 2592 uint32_t data; 2593 2594 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL); 2595 data = REG_SET_FIELD(data, TCP_CNTL, TCP_SPILL_CACHE_DISABLE, 0x1); 2596 2597 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regTCP_CNTL, data); 2598 } 2599 2600 static void gfx_v12_1_init_golden_registers(struct amdgpu_device *adev) 2601 { 2602 int i; 2603 2604 for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); i++) { 2605 gfx_v12_1_xcc_disable_burst(adev, i); 2606 gfx_v12_1_xcc_enable_atomics(adev, i); 2607 gfx_v12_1_xcc_disable_early_write_ack(adev, i); 2608 gfx_v12_1_xcc_disable_tcp_spill_cache(adev, i); 2609 } 2610 } 2611 2612 static int gfx_v12_1_set_userq_eop_interrupts(struct amdgpu_device *adev, 2613 bool enable) 2614 { 2615 unsigned int irq_type; 2616 int m, p, r; 2617 2618 if (!adev->gfx.disable_kq) 2619 return 0; 2620 2621 for (m = 0; m < adev->gfx.mec.num_mec; ++m) { 2622 for (p = 0; p < adev->gfx.mec.num_pipe_per_mec; p++) { 2623 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2624 + (m * adev->gfx.mec.num_pipe_per_mec) 2625 + p; 2626 if (enable) 2627 r = amdgpu_irq_get(adev, &adev->gfx.eop_irq, irq_type); 2628 else 2629 r = amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2630 if (r) { 2631 if (!enable) 2632 return r; 2633 goto err_unwind; 2634 } 2635 } 2636 } 2637 2638 return 0; 2639 2640 err_unwind: 2641 for (p--; p >= 0; p--) { 2642 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2643 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 2644 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2645 } 2646 for (m--; m >= 0; m--) { 2647 for (p = adev->gfx.mec.num_pipe_per_mec - 1; p >= 0; p--) { 2648 irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP 2649 + (m * adev->gfx.mec.num_pipe_per_mec) + p; 2650 amdgpu_irq_put(adev, &adev->gfx.eop_irq, irq_type); 2651 } 2652 } 2653 return r; 2654 } 2655 2656 static int gfx_v12_1_hw_init(struct amdgpu_ip_block *ip_block) 2657 { 2658 int r, i, num_xcc; 2659 struct amdgpu_device *adev = ip_block->adev; 2660 2661 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) { 2662 /* rlc autoload firmware */ 2663 r = gfx_v12_1_rlc_backdoor_autoload_enable(adev); 2664 if (r) 2665 return r; 2666 } else { 2667 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) { 2668 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2669 2670 if (adev->gfx.imu.funcs) { 2671 if (adev->gfx.imu.funcs->load_microcode) 2672 adev->gfx.imu.funcs->load_microcode(adev); 2673 } 2674 2675 for (i = 0; i < num_xcc; i++) { 2676 /* disable gpa mode in backdoor loading */ 2677 gfx_v12_1_xcc_disable_gpa_mode(adev, i); 2678 } 2679 } 2680 } 2681 2682 if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) || 2683 (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) { 2684 r = gfx_v12_1_wait_for_rlc_autoload_complete(adev); 2685 if (r) { 2686 dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r); 2687 return r; 2688 } 2689 } 2690 2691 adev->gfx.is_poweron = true; 2692 2693 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) 2694 gfx_v12_1_config_gfx_rs64(adev); 2695 2696 r = gfx_v12_1_gfxhub_enable(adev); 2697 if (r) 2698 return r; 2699 2700 if (!amdgpu_sriov_vf(adev)) 2701 gfx_v12_1_init_golden_registers(adev); 2702 2703 gfx_v12_1_constants_init(adev); 2704 2705 if (adev->nbio.funcs->gc_doorbell_init) 2706 adev->nbio.funcs->gc_doorbell_init(adev); 2707 2708 r = gfx_v12_1_rlc_resume(adev); 2709 if (r) 2710 return r; 2711 2712 r = gfx_v12_1_cp_resume(adev); 2713 if (r) 2714 return r; 2715 2716 r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0); 2717 if (r) 2718 return r; 2719 2720 r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0); 2721 if (r) 2722 goto err_priv_inst; 2723 2724 r = gfx_v12_1_set_userq_eop_interrupts(adev, true); 2725 if (r) 2726 goto err_userq_eop; 2727 2728 return 0; 2729 2730 err_userq_eop: 2731 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2732 err_priv_inst: 2733 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2734 return r; 2735 } 2736 2737 static void gfx_v12_1_xcc_fini(struct amdgpu_device *adev, 2738 int xcc_id) 2739 { 2740 uint32_t tmp; 2741 2742 if (!adev->no_hw_access) { 2743 if (amdgpu_gfx_disable_kcq(adev, xcc_id)) 2744 DRM_ERROR("KCQ disable failed\n"); 2745 2746 amdgpu_mes_kiq_hw_fini(adev, xcc_id); 2747 } 2748 2749 if (amdgpu_sriov_vf(adev)) { 2750 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */ 2751 tmp = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS); 2752 tmp &= 0xffffff00; 2753 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CP_SCHEDULERS, tmp); 2754 } 2755 gfx_v12_1_xcc_cp_compute_enable(adev, false, xcc_id); 2756 gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, false, xcc_id); 2757 } 2758 2759 static int gfx_v12_1_hw_fini(struct amdgpu_ip_block *ip_block) 2760 { 2761 struct amdgpu_device *adev = ip_block->adev; 2762 int i, num_xcc; 2763 2764 gfx_v12_1_set_userq_eop_interrupts(adev, false); 2765 amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0); 2766 amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0); 2767 2768 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2769 for (i = 0; i < num_xcc; i++) { 2770 gfx_v12_1_xcc_fini(adev, i); 2771 } 2772 2773 adev->gfxhub.funcs->gart_disable(adev); 2774 2775 adev->gfx.is_poweron = false; 2776 2777 return 0; 2778 } 2779 2780 static int gfx_v12_1_suspend(struct amdgpu_ip_block *ip_block) 2781 { 2782 return gfx_v12_1_hw_fini(ip_block); 2783 } 2784 2785 static int gfx_v12_1_resume(struct amdgpu_ip_block *ip_block) 2786 { 2787 return gfx_v12_1_hw_init(ip_block); 2788 } 2789 2790 static bool gfx_v12_1_is_idle(struct amdgpu_ip_block *ip_block) 2791 { 2792 struct amdgpu_device *adev = ip_block->adev; 2793 int i, num_xcc; 2794 2795 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2796 for (i = 0; i < num_xcc; i++) { 2797 if (REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, i), 2798 regGRBM_STATUS), GRBM_STATUS, GUI_ACTIVE)) 2799 return false; 2800 } 2801 return true; 2802 } 2803 2804 static int gfx_v12_1_wait_for_idle(struct amdgpu_ip_block *ip_block) 2805 { 2806 unsigned i; 2807 struct amdgpu_device *adev = ip_block->adev; 2808 2809 for (i = 0; i < adev->usec_timeout; i++) { 2810 if (gfx_v12_1_is_idle(ip_block)) 2811 return 0; 2812 udelay(1); 2813 } 2814 return -ETIMEDOUT; 2815 } 2816 2817 static uint64_t gfx_v12_1_get_gpu_clock_counter(struct amdgpu_device *adev) 2818 { 2819 uint64_t clock = 0; 2820 2821 if (adev->smuio.funcs && 2822 adev->smuio.funcs->get_gpu_clock_counter) 2823 clock = adev->smuio.funcs->get_gpu_clock_counter(adev); 2824 else 2825 dev_warn(adev->dev, "query gpu clock counter is not supported\n"); 2826 2827 return clock; 2828 } 2829 2830 static int gfx_v12_1_early_init(struct amdgpu_ip_block *ip_block) 2831 { 2832 struct amdgpu_device *adev = ip_block->adev; 2833 2834 2835 switch (amdgpu_user_queue) { 2836 case -1: 2837 default: 2838 adev->gfx.disable_kq = true; 2839 adev->gfx.disable_uq = true; 2840 break; 2841 case 0: 2842 adev->gfx.disable_kq = false; 2843 adev->gfx.disable_uq = true; 2844 break; 2845 } 2846 2847 adev->gfx.funcs = &gfx_v12_1_gfx_funcs; 2848 2849 if (adev->gfx.disable_kq) 2850 adev->gfx.num_compute_rings = 0; 2851 else 2852 adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev), 2853 AMDGPU_MAX_COMPUTE_RINGS); 2854 2855 gfx_v12_1_set_ring_funcs(adev); 2856 gfx_v12_1_set_irq_funcs(adev); 2857 gfx_v12_1_set_rlc_funcs(adev); 2858 gfx_v12_1_set_mqd_funcs(adev); 2859 gfx_v12_1_set_imu_funcs(adev); 2860 2861 gfx_v12_1_init_rlcg_reg_access_ctrl(adev); 2862 2863 amdgpu_init_rlc_reg_funcs(adev); 2864 2865 /* Set NPA address size here as its needed in amdgpu_ttm_init(). 2866 * NPA address space is 52 bits or 2^40 pages long. 2867 */ 2868 adev->ualink.npa_size = 1ULL << 40; 2869 2870 return gfx_v12_1_init_microcode(adev); 2871 } 2872 2873 static bool gfx_v12_1_is_rlc_enabled(struct amdgpu_device *adev) 2874 { 2875 uint32_t rlc_cntl; 2876 2877 /* if RLC is not enabled, do nothing */ 2878 rlc_cntl = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CNTL); 2879 return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false; 2880 } 2881 2882 static void gfx_v12_1_xcc_set_safe_mode(struct amdgpu_device *adev, 2883 int xcc_id) 2884 { 2885 uint32_t data; 2886 unsigned i; 2887 2888 data = RLC_SAFE_MODE__CMD_MASK; 2889 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT); 2890 2891 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SAFE_MODE, data); 2892 2893 /* wait for RLC_SAFE_MODE */ 2894 for (i = 0; i < adev->usec_timeout; i++) { 2895 if (!REG_GET_FIELD(RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2896 regRLC_SAFE_MODE), RLC_SAFE_MODE, CMD)) 2897 break; 2898 udelay(1); 2899 } 2900 } 2901 2902 static void gfx_v12_1_xcc_unset_safe_mode(struct amdgpu_device *adev, 2903 int xcc_id) 2904 { 2905 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 2906 regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK); 2907 } 2908 2909 static void gfx_v12_1_update_perf_clk(struct amdgpu_device *adev, 2910 bool enable) 2911 { 2912 int i, num_xcc; 2913 2914 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 2915 for (i = 0; i < num_xcc; i++) 2916 gfx_v12_1_xcc_update_perf_clk(adev, enable, i); 2917 } 2918 2919 static void gfx_v12_1_update_spm_vmid(struct amdgpu_device *adev, 2920 int xcc_id, 2921 struct amdgpu_ring *ring, 2922 unsigned vmid) 2923 { 2924 u32 reg, data; 2925 2926 reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); 2927 if (amdgpu_sriov_is_pp_one_vf(adev)) 2928 data = RREG32_NO_KIQ(reg); 2929 else 2930 data = RREG32(reg); 2931 2932 data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK; 2933 data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT; 2934 2935 if (amdgpu_sriov_is_pp_one_vf(adev)) 2936 WREG32_SOC15_NO_KIQ(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); 2937 else 2938 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL, data); 2939 2940 if (ring 2941 && amdgpu_sriov_is_pp_one_vf(adev) 2942 && ((ring->funcs->type == AMDGPU_RING_TYPE_GFX) 2943 || (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE))) { 2944 uint32_t reg = SOC15_REG_OFFSET(GC, GET_INST(GC, xcc_id), regRLC_SPM_MC_CNTL); 2945 amdgpu_ring_emit_wreg(ring, reg, data); 2946 } 2947 } 2948 2949 static const struct amdgpu_rlc_funcs gfx_v12_1_rlc_funcs = { 2950 .is_rlc_enabled = gfx_v12_1_is_rlc_enabled, 2951 .set_safe_mode = gfx_v12_1_xcc_set_safe_mode, 2952 .unset_safe_mode = gfx_v12_1_xcc_unset_safe_mode, 2953 .init = gfx_v12_1_rlc_init, 2954 .get_csb_size = gfx_v12_1_get_csb_size, 2955 .get_csb_buffer = gfx_v12_1_get_csb_buffer, 2956 .resume = gfx_v12_1_rlc_resume, 2957 .stop = gfx_v12_1_rlc_stop, 2958 .reset = gfx_v12_1_rlc_reset, 2959 .start = gfx_v12_1_rlc_start, 2960 .update_spm_vmid = gfx_v12_1_update_spm_vmid, 2961 }; 2962 2963 #if 0 2964 static void gfx_v12_cntl_power_gating(struct amdgpu_device *adev, bool enable) 2965 { 2966 /* TODO */ 2967 } 2968 2969 static void gfx_v12_cntl_pg(struct amdgpu_device *adev, bool enable) 2970 { 2971 /* TODO */ 2972 } 2973 #endif 2974 2975 static int gfx_v12_1_set_powergating_state(struct amdgpu_ip_block *ip_block, 2976 enum amd_powergating_state state) 2977 { 2978 /* No powergating state for GC v12.1 */ 2979 return 0; 2980 } 2981 2982 static void gfx_v12_1_xcc_update_coarse_grain_clock_gating(struct amdgpu_device *adev, 2983 bool enable, int xcc_id) 2984 { 2985 uint32_t def, data; 2986 2987 if (!(adev->cg_flags & 2988 (AMD_CG_SUPPORT_GFX_CGCG | 2989 AMD_CG_SUPPORT_GFX_CGLS | 2990 AMD_CG_SUPPORT_GFX_3D_CGCG | 2991 AMD_CG_SUPPORT_GFX_3D_CGLS))) 2992 return; 2993 2994 if (enable) { 2995 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 2996 regRLC_CGTT_MGCG_OVERRIDE); 2997 2998 /* unset CGCG override */ 2999 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3000 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK; 3001 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3002 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK; 3003 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG || 3004 adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) 3005 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK; 3006 3007 /* update CGCG override bits */ 3008 if (def != data) 3009 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3010 regRLC_CGTT_MGCG_OVERRIDE, data); 3011 3012 /* enable cgcg FSM(0x0000363F) */ 3013 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 3014 3015 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) { 3016 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK; 3017 data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) | 3018 RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3019 } 3020 3021 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) { 3022 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK; 3023 data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) | 3024 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3025 } 3026 3027 if (def != data) 3028 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3029 regRLC_CGCG_CGLS_CTRL, data); 3030 3031 /* set IDLE_POLL_COUNT(0x00900100) */ 3032 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL); 3033 3034 data &= ~CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK; 3035 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK; 3036 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) | 3037 (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT); 3038 3039 if (def != data) 3040 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_RB_WPTR_POLL_CNTL, data); 3041 3042 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL); 3043 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1); 3044 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1); 3045 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1); 3046 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1); 3047 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regCP_INT_CNTL, data); 3048 } else { 3049 /* Program RLC_CGCG_CGLS_CTRL */ 3050 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL); 3051 3052 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) 3053 data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK; 3054 3055 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) 3056 data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK; 3057 3058 if (def != data) 3059 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGCG_CGLS_CTRL, data); 3060 } 3061 } 3062 3063 static void gfx_v12_1_xcc_update_medium_grain_clock_gating( 3064 struct amdgpu_device *adev, bool enable, int xcc_id, bool force) 3065 { 3066 uint32_t data, def; 3067 bool support_mgcg; 3068 3069 support_mgcg = force || (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG); 3070 3071 if (!support_mgcg) 3072 return; 3073 3074 /* It is disabled by HW by default */ 3075 if (enable) { 3076 /* 1 - RLC_CGTT_MGCG_OVERRIDE */ 3077 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3078 regRLC_CGTT_MGCG_OVERRIDE); 3079 3080 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3081 RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3082 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 3083 3084 if (def != data) 3085 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3086 regRLC_CGTT_MGCG_OVERRIDE, data); 3087 } else { 3088 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), 3089 regRLC_CGTT_MGCG_OVERRIDE); 3090 3091 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK | 3092 RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK | 3093 RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK); 3094 3095 if (def != data) 3096 WREG32_SOC15(GC, GET_INST(GC, xcc_id), 3097 regRLC_CGTT_MGCG_OVERRIDE, data); 3098 } 3099 } 3100 3101 static void gfx_v12_1_xcc_update_repeater_fgcg(struct amdgpu_device *adev, 3102 bool enable, int xcc_id) 3103 { 3104 uint32_t def, data; 3105 3106 if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG)) 3107 return; 3108 3109 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3110 3111 if (enable) 3112 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 3113 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK); 3114 else 3115 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK | 3116 RLC_CGTT_MGCG_OVERRIDE__RLC_REPEATER_FGCG_OVERRIDE_MASK; 3117 3118 if (def != data) 3119 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3120 } 3121 3122 static void gfx_v12_1_xcc_update_sram_fgcg(struct amdgpu_device *adev, 3123 bool enable, int xcc_id) 3124 { 3125 uint32_t def, data; 3126 3127 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG)) 3128 return; 3129 3130 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3131 3132 if (enable) 3133 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 3134 else 3135 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK; 3136 3137 if (def != data) 3138 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3139 } 3140 3141 static void gfx_v12_1_xcc_update_perf_clk(struct amdgpu_device *adev, 3142 bool enable, int xcc_id) 3143 { 3144 uint32_t def, data; 3145 3146 if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK)) 3147 return; 3148 3149 def = data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE); 3150 3151 if (enable) 3152 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3153 else 3154 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK; 3155 3156 if (def != data) 3157 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regRLC_CGTT_MGCG_OVERRIDE, data); 3158 } 3159 3160 static int gfx_v12_1_xcc_update_gfx_clock_gating(struct amdgpu_device *adev, 3161 bool enable, int xcc_id) 3162 { 3163 amdgpu_gfx_rlc_enter_safe_mode(adev, xcc_id); 3164 3165 gfx_v12_1_xcc_update_coarse_grain_clock_gating(adev, enable, xcc_id); 3166 3167 gfx_v12_1_xcc_update_medium_grain_clock_gating(adev, enable, xcc_id, 3168 false); 3169 3170 gfx_v12_1_xcc_update_repeater_fgcg(adev, enable, xcc_id); 3171 3172 gfx_v12_1_xcc_update_sram_fgcg(adev, enable, xcc_id); 3173 3174 gfx_v12_1_xcc_update_perf_clk(adev, enable, xcc_id); 3175 3176 if (adev->cg_flags & 3177 (AMD_CG_SUPPORT_GFX_MGCG | 3178 AMD_CG_SUPPORT_GFX_CGLS | 3179 AMD_CG_SUPPORT_GFX_CGCG | 3180 AMD_CG_SUPPORT_GFX_3D_CGCG | 3181 AMD_CG_SUPPORT_GFX_3D_CGLS)) 3182 gfx_v12_1_xcc_enable_gui_idle_interrupt(adev, enable, xcc_id); 3183 3184 amdgpu_gfx_rlc_exit_safe_mode(adev, xcc_id); 3185 3186 return 0; 3187 } 3188 3189 static int gfx_v12_1_set_clockgating_state(struct amdgpu_ip_block *ip_block, 3190 enum amd_clockgating_state state) 3191 { 3192 struct amdgpu_device *adev = ip_block->adev; 3193 int i, num_xcc; 3194 3195 if (amdgpu_sriov_vf(adev)) 3196 return 0; 3197 3198 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3199 switch (adev->ip_versions[GC_HWIP][0]) { 3200 case IP_VERSION(12, 1, 0): 3201 for (i = 0; i < num_xcc; i++) 3202 gfx_v12_1_xcc_update_gfx_clock_gating(adev, 3203 state == AMD_CG_STATE_GATE, i); 3204 break; 3205 default: 3206 break; 3207 } 3208 3209 return 0; 3210 } 3211 3212 static void gfx_v12_1_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags) 3213 { 3214 struct amdgpu_device *adev = ip_block->adev; 3215 int data; 3216 3217 /* AMD_CG_SUPPORT_GFX_MGCG */ 3218 data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGTT_MGCG_OVERRIDE); 3219 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK)) 3220 *flags |= AMD_CG_SUPPORT_GFX_MGCG; 3221 3222 /* AMD_CG_SUPPORT_REPEATER_FGCG */ 3223 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK)) 3224 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG; 3225 3226 /* AMD_CG_SUPPORT_GFX_FGCG */ 3227 if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK)) 3228 *flags |= AMD_CG_SUPPORT_GFX_FGCG; 3229 3230 /* AMD_CG_SUPPORT_GFX_PERF_CLK */ 3231 if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK)) 3232 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK; 3233 3234 /* AMD_CG_SUPPORT_GFX_CGCG */ 3235 data = RREG32_SOC15(GC, GET_INST(GC, 0), regRLC_CGCG_CGLS_CTRL); 3236 if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK) 3237 *flags |= AMD_CG_SUPPORT_GFX_CGCG; 3238 3239 /* AMD_CG_SUPPORT_GFX_CGLS */ 3240 if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK) 3241 *flags |= AMD_CG_SUPPORT_GFX_CGLS; 3242 } 3243 3244 static u64 gfx_v12_1_ring_get_rptr_compute(struct amdgpu_ring *ring) 3245 { 3246 /* gfx12 hardware is 32bit rptr */ 3247 return *(uint32_t *)ring->rptr_cpu_addr; 3248 } 3249 3250 static u64 gfx_v12_1_ring_get_wptr_compute(struct amdgpu_ring *ring) 3251 { 3252 struct amdgpu_device *adev = ring->adev; 3253 u64 wptr; 3254 3255 /* XXX check if swapping is necessary on BE */ 3256 if (ring->use_doorbell) { 3257 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr); 3258 } else { 3259 dev_warn_once(adev->dev, "%s requires doorbell!\n", __func__); 3260 wptr = 0; 3261 } 3262 return wptr; 3263 } 3264 3265 static void gfx_v12_1_ring_set_wptr_compute(struct amdgpu_ring *ring) 3266 { 3267 struct amdgpu_device *adev = ring->adev; 3268 3269 /* XXX check if swapping is necessary on BE */ 3270 if (ring->use_doorbell) { 3271 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 3272 ring->wptr); 3273 WDOORBELL64(ring->doorbell_index, ring->wptr); 3274 } else { 3275 dev_warn_once(adev->dev, "%s requires doorbell!\n", __func__); 3276 } 3277 } 3278 3279 static void gfx_v12_1_ring_emit_ib_compute(struct amdgpu_ring *ring, 3280 struct amdgpu_job *job, 3281 struct amdgpu_ib *ib, 3282 uint32_t flags) 3283 { 3284 unsigned vmid = AMDGPU_JOB_GET_VMID(job); 3285 u32 control = PACKET3_INDIRECT_BUFFER__VALID(1) | ib->length_dw | (vmid << 24); 3286 3287 /* Currently, there is a high possibility to get wave ID mismatch 3288 * between ME and GDS, leading to a hw deadlock, because ME generates 3289 * different wave IDs than the GDS expects. This situation happens 3290 * randomly when at least 5 compute pipes use GDS ordered append. 3291 * The wave IDs generated by ME are also wrong after suspend/resume. 3292 * Those are probably bugs somewhere else in the kernel driver. 3293 * 3294 * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and 3295 * GDS to 0 for this ring (me/pipe). 3296 */ 3297 if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) { 3298 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1)); 3299 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID); 3300 } 3301 3302 amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); 3303 WARN_ON(ib->gpu_addr & 0x3); /* Dword align */ 3304 amdgpu_ring_write(ring, 3305 #ifdef __BIG_ENDIAN 3306 (2 << 0) | 3307 #endif 3308 lower_32_bits(ib->gpu_addr)); 3309 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); 3310 amdgpu_ring_write(ring, control); 3311 } 3312 3313 static void gfx_v12_1_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, 3314 u64 seq, unsigned flags) 3315 { 3316 bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT; 3317 bool int_sel = flags & AMDGPU_FENCE_FLAG_INT; 3318 3319 /* RELEASE_MEM - flush caches, send int */ 3320 amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6)); 3321 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM__GCR_SEQ(1) | 3322 PACKET3_RELEASE_MEM__GCR_GLV_WB | 3323 PACKET3_RELEASE_MEM__GCR_GL2_WB | 3324 PACKET3_RELEASE_MEM__GCR_GL2_SCOPE(2) | 3325 PACKET3_RELEASE_MEM__TEMPORAL(3) | 3326 PACKET3_RELEASE_MEM__EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) | 3327 PACKET3_RELEASE_MEM__EVENT_INDEX(5))); 3328 amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM__DATA_SEL(write64bit ? 2 : 1) | 3329 PACKET3_RELEASE_MEM__INT_SEL(int_sel ? 2 : 0))); 3330 3331 /* 3332 * the address should be Qword aligned if 64bit write, Dword 3333 * aligned if only send 32bit data low (discard data high) 3334 */ 3335 if (write64bit) 3336 WARN_ON(addr & 0x7); 3337 else 3338 WARN_ON(addr & 0x3); 3339 amdgpu_ring_write(ring, lower_32_bits(addr)); 3340 amdgpu_ring_write(ring, upper_32_bits(addr)); 3341 amdgpu_ring_write(ring, lower_32_bits(seq)); 3342 amdgpu_ring_write(ring, upper_32_bits(seq)); 3343 amdgpu_ring_write(ring, 0); 3344 } 3345 3346 static void gfx_v12_1_ring_emit_pipeline_sync(struct amdgpu_ring *ring) 3347 { 3348 uint32_t seq = ring->fence_drv.sync_seq; 3349 uint64_t addr = ring->fence_drv.gpu_addr; 3350 3351 gfx_v12_1_wait_reg_mem(ring, 0, 1, 0, lower_32_bits(addr), 3352 upper_32_bits(addr), seq, 0xffffffff, 4); 3353 } 3354 3355 static void gfx_v12_1_ring_emit_vm_flush(struct amdgpu_ring *ring, 3356 unsigned vmid, uint64_t pd_addr) 3357 { 3358 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr); 3359 3360 /* compute doesn't have PFP */ 3361 } 3362 3363 static void gfx_v12_1_ring_emit_wreg(struct amdgpu_ring *ring, 3364 uint32_t reg, 3365 uint32_t val) 3366 { 3367 reg = soc_v1_0_normalize_xcc_reg_offset(reg); 3368 3369 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3)); 3370 amdgpu_ring_write(ring, PACKET3_WRITE_DATA__WR_CONFIRM(1)); 3371 amdgpu_ring_write(ring, reg); 3372 amdgpu_ring_write(ring, 0); 3373 amdgpu_ring_write(ring, val); 3374 } 3375 3376 static void gfx_v12_1_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg, 3377 uint32_t val, uint32_t mask) 3378 { 3379 gfx_v12_1_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20); 3380 } 3381 3382 static void gfx_v12_1_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring, 3383 uint32_t reg0, uint32_t reg1, 3384 uint32_t ref, uint32_t mask) 3385 { 3386 gfx_v12_1_wait_reg_mem(ring, 0, 0, 1, reg0, reg1, 3387 ref, mask, 0x20); 3388 } 3389 3390 static void gfx_v12_1_xcc_set_compute_eop_interrupt_state(struct amdgpu_device *adev, 3391 int me, int pipe, 3392 enum amdgpu_interrupt_state state, 3393 int xcc_id) 3394 { 3395 u32 mec_int_cntl, mec_int_cntl_reg; 3396 3397 /* 3398 * amdgpu controls only the first MEC. That's why this function only 3399 * handles the setting of interrupts for this specific MEC. All other 3400 * pipes' interrupts are set by amdkfd. 3401 */ 3402 3403 if (me == 1) { 3404 switch (pipe) { 3405 case 0: 3406 mec_int_cntl_reg = SOC15_REG_OFFSET( 3407 GC, GET_INST(GC, xcc_id), 3408 regCP_ME1_PIPE0_INT_CNTL); 3409 break; 3410 case 1: 3411 mec_int_cntl_reg = SOC15_REG_OFFSET( 3412 GC, GET_INST(GC, xcc_id), 3413 regCP_ME1_PIPE1_INT_CNTL); 3414 break; 3415 case 2: 3416 mec_int_cntl_reg = SOC15_REG_OFFSET( 3417 GC, GET_INST(GC, xcc_id), 3418 regCP_ME1_PIPE2_INT_CNTL); 3419 break; 3420 case 3: 3421 mec_int_cntl_reg = SOC15_REG_OFFSET( 3422 GC, GET_INST(GC, xcc_id), 3423 regCP_ME1_PIPE3_INT_CNTL); 3424 break; 3425 default: 3426 DRM_DEBUG("invalid pipe %d\n", pipe); 3427 return; 3428 } 3429 } else { 3430 DRM_DEBUG("invalid me %d\n", me); 3431 return; 3432 } 3433 3434 switch (state) { 3435 case AMDGPU_IRQ_STATE_DISABLE: 3436 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3437 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3438 TIME_STAMP_INT_ENABLE, 0); 3439 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3440 GENERIC0_INT_ENABLE, 0); 3441 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3442 break; 3443 case AMDGPU_IRQ_STATE_ENABLE: 3444 mec_int_cntl = RREG32_XCC(mec_int_cntl_reg, xcc_id); 3445 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3446 TIME_STAMP_INT_ENABLE, 1); 3447 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL, 3448 GENERIC0_INT_ENABLE, 1); 3449 WREG32_XCC(mec_int_cntl_reg, mec_int_cntl, xcc_id); 3450 break; 3451 default: 3452 break; 3453 } 3454 } 3455 3456 static int gfx_v12_1_set_eop_interrupt_state(struct amdgpu_device *adev, 3457 struct amdgpu_irq_src *src, 3458 unsigned type, 3459 enum amdgpu_interrupt_state state) 3460 { 3461 int i, num_xcc; 3462 3463 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3464 for (i = 0; i < num_xcc; i++) { 3465 switch (type) { 3466 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP: 3467 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3468 adev, 1, 0, state, i); 3469 break; 3470 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP: 3471 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3472 adev, 1, 1, state, i); 3473 break; 3474 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP: 3475 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3476 adev, 1, 2, state, i); 3477 break; 3478 case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP: 3479 gfx_v12_1_xcc_set_compute_eop_interrupt_state( 3480 adev, 1, 3, state, i); 3481 break; 3482 default: 3483 break; 3484 } 3485 } 3486 3487 return 0; 3488 } 3489 3490 static int gfx_v12_1_eop_irq(struct amdgpu_device *adev, 3491 struct amdgpu_irq_src *source, 3492 struct amdgpu_iv_entry *entry) 3493 { 3494 u32 doorbell_offset = entry->src_data[0]; 3495 u8 me_id, pipe_id, queue_id; 3496 struct amdgpu_ring *ring; 3497 int i, xcc_id; 3498 3499 DRM_DEBUG("IH: CP EOP\n"); 3500 3501 if (adev->enable_mes && doorbell_offset) { 3502 amdgpu_userq_process_fence_irq(adev, doorbell_offset); 3503 } else { 3504 me_id = (entry->ring_id & 0x0c) >> 2; 3505 pipe_id = (entry->ring_id & 0x03) >> 0; 3506 queue_id = (entry->ring_id & 0x70) >> 4; 3507 xcc_id = gfx_v12_1_ih_to_xcc_inst(adev, entry->node_id); 3508 3509 if (xcc_id == -EINVAL) 3510 return -EINVAL; 3511 3512 switch (me_id) { 3513 case 1: 3514 case 2: 3515 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3516 ring = &adev->gfx.compute_ring 3517 [i + 3518 xcc_id * adev->gfx.num_compute_rings]; 3519 /* Per-queue interrupt is supported for MEC starting from VI. 3520 * The interrupt can only be enabled/disabled per pipe instead 3521 * of per queue. 3522 */ 3523 if ((ring->me == me_id) && 3524 (ring->pipe == pipe_id) && 3525 (ring->queue == queue_id)) 3526 amdgpu_fence_process(ring); 3527 } 3528 break; 3529 default: 3530 dev_dbg(adev->dev, "Unexpected me %d in eop_irq\n", me_id); 3531 break; 3532 } 3533 } 3534 3535 return 0; 3536 } 3537 3538 static int gfx_v12_1_set_priv_reg_fault_state(struct amdgpu_device *adev, 3539 struct amdgpu_irq_src *source, 3540 unsigned type, 3541 enum amdgpu_interrupt_state state) 3542 { 3543 int i, num_xcc; 3544 3545 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3546 switch (state) { 3547 case AMDGPU_IRQ_STATE_DISABLE: 3548 case AMDGPU_IRQ_STATE_ENABLE: 3549 for (i = 0; i < num_xcc; i++) 3550 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3551 PRIV_REG_INT_ENABLE, 3552 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3553 break; 3554 default: 3555 break; 3556 } 3557 3558 return 0; 3559 } 3560 3561 static int gfx_v12_1_set_priv_inst_fault_state(struct amdgpu_device *adev, 3562 struct amdgpu_irq_src *source, 3563 unsigned type, 3564 enum amdgpu_interrupt_state state) 3565 { 3566 int i, num_xcc; 3567 3568 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3569 switch (state) { 3570 case AMDGPU_IRQ_STATE_DISABLE: 3571 case AMDGPU_IRQ_STATE_ENABLE: 3572 for (i = 0; i < num_xcc; i++) 3573 WREG32_FIELD15_PREREG(GC, GET_INST(GC, i), CP_INT_CNTL_RING0, 3574 PRIV_INSTR_INT_ENABLE, 3575 state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0); 3576 break; 3577 default: 3578 break; 3579 } 3580 3581 return 0; 3582 } 3583 3584 static void gfx_v12_1_handle_priv_fault(struct amdgpu_device *adev, 3585 struct amdgpu_iv_entry *entry) 3586 { 3587 u8 me_id, pipe_id, queue_id; 3588 struct amdgpu_ring *ring; 3589 int i, xcc_id; 3590 3591 me_id = (entry->ring_id & 0x0c) >> 2; 3592 pipe_id = (entry->ring_id & 0x03) >> 0; 3593 queue_id = (entry->ring_id & 0x70) >> 4; 3594 xcc_id = gfx_v12_1_ih_to_xcc_inst(adev, entry->node_id); 3595 3596 if (xcc_id == -EINVAL) 3597 return; 3598 3599 if (!adev->gfx.disable_kq) { 3600 switch (me_id) { 3601 case 1: 3602 case 2: 3603 for (i = 0; i < adev->gfx.num_compute_rings; i++) { 3604 ring = &adev->gfx.compute_ring 3605 [i + 3606 xcc_id * adev->gfx.num_compute_rings]; 3607 if (ring->me == me_id && ring->pipe == pipe_id && 3608 ring->queue == queue_id) 3609 drm_sched_fault(&ring->sched); 3610 } 3611 break; 3612 default: 3613 dev_dbg(adev->dev, "Unexpected me %d in priv_fault\n", me_id); 3614 break; 3615 } 3616 } 3617 } 3618 3619 static int gfx_v12_1_priv_reg_irq(struct amdgpu_device *adev, 3620 struct amdgpu_irq_src *source, 3621 struct amdgpu_iv_entry *entry) 3622 { 3623 DRM_ERROR("Illegal register access in command stream\n"); 3624 gfx_v12_1_handle_priv_fault(adev, entry); 3625 return 0; 3626 } 3627 3628 static int gfx_v12_1_priv_inst_irq(struct amdgpu_device *adev, 3629 struct amdgpu_irq_src *source, 3630 struct amdgpu_iv_entry *entry) 3631 { 3632 DRM_ERROR("Illegal instruction in command stream\n"); 3633 gfx_v12_1_handle_priv_fault(adev, entry); 3634 return 0; 3635 } 3636 3637 static int gfx_v12_1_rlc_poison_irq(struct amdgpu_device *adev, 3638 struct amdgpu_irq_src *source, 3639 struct amdgpu_iv_entry *entry) 3640 { 3641 uint32_t rlc_fed_status = 0; 3642 uint32_t ras_blk = RAS_BLOCK_ID__GFX; 3643 struct ras_ih_info ih_info = {0}; 3644 int i, num_xcc; 3645 3646 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3647 for (i = 0; i < num_xcc; i++) 3648 rlc_fed_status |= RREG32(SOC15_REG_OFFSET(GC, 3649 GET_INST(GC, i), regRLC_RLCS_FED_STATUS)); 3650 3651 if (!rlc_fed_status) 3652 return 0; 3653 3654 if (REG_GET_FIELD(rlc_fed_status, RLC_RLCS_FED_STATUS, SDMA0_FED_ERR) || 3655 REG_GET_FIELD(rlc_fed_status, RLC_RLCS_FED_STATUS, SDMA1_FED_ERR)) 3656 ras_blk = RAS_BLOCK_ID__SDMA; 3657 3658 dev_warn(adev->dev, "RLC %d FED IRQ\n", ras_blk); 3659 3660 ih_info.block = ras_blk; 3661 ih_info.reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; 3662 amdgpu_ras_mgr_dispatch_interrupt(adev, &ih_info); 3663 return 0; 3664 } 3665 3666 static int gfx_v12_1_pmr_ea_irq(struct amdgpu_device *adev, 3667 struct amdgpu_irq_src *source, 3668 struct amdgpu_iv_entry *entry) 3669 { 3670 uint32_t ras_blk = RAS_BLOCK_ID__GFX; 3671 struct ras_ih_info ih_info = {0}; 3672 uint32_t ctx_id = entry->src_data[0]; 3673 int i, num_xcc; 3674 3675 if (ctx_id & 0x1) { 3676 /* request RLC MCA logging here 3677 * nHT CTO status clearing is handled by RLC firmware 3678 */ 3679 3680 ih_info.block = ras_blk; 3681 ih_info.reset = AMDGPU_RAS_GPU_RESET_MODE2_RESET; 3682 amdgpu_ras_mgr_dispatch_interrupt(adev, &ih_info); 3683 } 3684 3685 if (ctx_id & 0x2) { 3686 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3687 /* ea_ill_op_status will be cleared in a future update */ 3688 for (i = 0; i < num_xcc; i++) 3689 dev_warn(adev->dev, 3690 "an EA illegal-op is detected and need to clear ea_ill_op_status\n"); 3691 } 3692 3693 return 0; 3694 } 3695 3696 static void gfx_v12_1_emit_mem_sync(struct amdgpu_ring *ring) 3697 { 3698 const unsigned int gcr_cntl = 3699 PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_INV(1) | 3700 PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_WB(1) | 3701 PACKET3_ACQUIRE_MEM__GCR_CNTL__GLV_INV(1) | 3702 PACKET3_ACQUIRE_MEM__GCR_CNTL__GLK_INV(1) | 3703 PACKET3_ACQUIRE_MEM__GCR_CNTL__GLI_INV(1) | 3704 PACKET3_ACQUIRE_MEM__GCR_CNTL__GL2_SCOPE(2); 3705 3706 /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */ 3707 amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6)); 3708 amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */ 3709 amdgpu_ring_write(ring, 0xffffffff); /* CP_COHER_SIZE */ 3710 amdgpu_ring_write(ring, 0xffffff); /* CP_COHER_SIZE_HI */ 3711 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */ 3712 amdgpu_ring_write(ring, 0); /* CP_COHER_BASE_HI */ 3713 amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */ 3714 amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */ 3715 } 3716 3717 static const struct amd_ip_funcs gfx_v12_1_ip_funcs = { 3718 .name = "gfx_v12_1", 3719 .early_init = gfx_v12_1_early_init, 3720 .sw_init = gfx_v12_1_sw_init, 3721 .sw_fini = gfx_v12_1_sw_fini, 3722 .hw_init = gfx_v12_1_hw_init, 3723 .hw_fini = gfx_v12_1_hw_fini, 3724 .suspend = gfx_v12_1_suspend, 3725 .resume = gfx_v12_1_resume, 3726 .wait_for_idle = gfx_v12_1_wait_for_idle, 3727 .set_clockgating_state = gfx_v12_1_set_clockgating_state, 3728 .set_powergating_state = gfx_v12_1_set_powergating_state, 3729 .get_clockgating_state = gfx_v12_1_get_clockgating_state, 3730 .dump_ip_state = gfx_v12_1_ip_dump, 3731 .print_ip_state = gfx_v12_1_ip_print, 3732 }; 3733 3734 static const struct amdgpu_ring_funcs gfx_v12_1_ring_funcs_compute = { 3735 .type = AMDGPU_RING_TYPE_COMPUTE, 3736 .align_mask = 0xff, 3737 .nop = PACKET3(PACKET3_NOP, 0x3FFF), 3738 .support_64bit_ptrs = true, 3739 .get_rptr = gfx_v12_1_ring_get_rptr_compute, 3740 .get_wptr = gfx_v12_1_ring_get_wptr_compute, 3741 .set_wptr = gfx_v12_1_ring_set_wptr_compute, 3742 .emit_frame_size = 3743 7 + /* gfx_v12_1_ring_emit_pipeline_sync */ 3744 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 + 3745 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 + 3746 2 + /* gfx_v12_1_ring_emit_vm_flush */ 3747 8 + 8 + 8 + /* gfx_v12_1_ring_emit_fence x3 for user fence, vm fence */ 3748 8, /* gfx_v12_1_emit_mem_sync */ 3749 .emit_ib_size = 7, /* gfx_v12_1_ring_emit_ib_compute */ 3750 .emit_ib = gfx_v12_1_ring_emit_ib_compute, 3751 .emit_fence = gfx_v12_1_ring_emit_fence, 3752 .emit_pipeline_sync = gfx_v12_1_ring_emit_pipeline_sync, 3753 .emit_vm_flush = gfx_v12_1_ring_emit_vm_flush, 3754 .test_ring = gfx_v12_1_ring_test_ring, 3755 .test_ib = gfx_v12_1_ring_test_ib, 3756 .insert_nop = amdgpu_ring_insert_nop, 3757 .pad_ib = amdgpu_ring_generic_pad_ib, 3758 .emit_wreg = gfx_v12_1_ring_emit_wreg, 3759 .emit_reg_wait = gfx_v12_1_ring_emit_reg_wait, 3760 .emit_reg_write_reg_wait = gfx_v12_1_ring_emit_reg_write_reg_wait, 3761 .emit_mem_sync = gfx_v12_1_emit_mem_sync, 3762 }; 3763 3764 static void gfx_v12_1_set_ring_funcs(struct amdgpu_device *adev) 3765 { 3766 int i, j, num_xcc; 3767 3768 num_xcc = NUM_XCC(adev->gfx.xcc_mask); 3769 for (i = 0; i < num_xcc; i++) { 3770 for (j = 0; j < adev->gfx.num_compute_rings; j++) 3771 adev->gfx.compute_ring[j + i * adev->gfx.num_compute_rings].funcs = 3772 &gfx_v12_1_ring_funcs_compute; 3773 } 3774 } 3775 3776 static const struct amdgpu_irq_src_funcs gfx_v12_1_eop_irq_funcs = { 3777 .set = gfx_v12_1_set_eop_interrupt_state, 3778 .process = gfx_v12_1_eop_irq, 3779 }; 3780 3781 static const struct amdgpu_irq_src_funcs gfx_v12_1_priv_reg_irq_funcs = { 3782 .set = gfx_v12_1_set_priv_reg_fault_state, 3783 .process = gfx_v12_1_priv_reg_irq, 3784 }; 3785 3786 static const struct amdgpu_irq_src_funcs gfx_v12_1_priv_inst_irq_funcs = { 3787 .set = gfx_v12_1_set_priv_inst_fault_state, 3788 .process = gfx_v12_1_priv_inst_irq, 3789 }; 3790 3791 static const struct amdgpu_irq_src_funcs gfx_v12_1_rlc_poison_irq_funcs = { 3792 .process = gfx_v12_1_rlc_poison_irq, 3793 }; 3794 3795 static const struct amdgpu_irq_src_funcs gfx_v12_1_pmr_ea_irq_funcs = { 3796 .process = gfx_v12_1_pmr_ea_irq, 3797 }; 3798 3799 static void gfx_v12_1_set_irq_funcs(struct amdgpu_device *adev) 3800 { 3801 adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST; 3802 adev->gfx.eop_irq.funcs = &gfx_v12_1_eop_irq_funcs; 3803 3804 adev->gfx.priv_reg_irq.num_types = 1; 3805 adev->gfx.priv_reg_irq.funcs = &gfx_v12_1_priv_reg_irq_funcs; 3806 3807 adev->gfx.priv_inst_irq.num_types = 1; 3808 adev->gfx.priv_inst_irq.funcs = &gfx_v12_1_priv_inst_irq_funcs; 3809 3810 adev->gfx.rlc_poison_irq.num_types = 1; 3811 adev->gfx.rlc_poison_irq.funcs = &gfx_v12_1_rlc_poison_irq_funcs; 3812 3813 adev->gfx.pmr_ea_irq.num_types = 1; 3814 adev->gfx.pmr_ea_irq.funcs = &gfx_v12_1_pmr_ea_irq_funcs; 3815 } 3816 3817 static void gfx_v12_1_set_imu_funcs(struct amdgpu_device *adev) 3818 { 3819 if (adev->flags & AMD_IS_APU) 3820 adev->gfx.imu.mode = MISSION_MODE; 3821 else 3822 adev->gfx.imu.mode = DEBUG_MODE; 3823 if (!amdgpu_sriov_vf(adev)) 3824 adev->gfx.imu.funcs = &gfx_v12_1_imu_funcs; 3825 } 3826 3827 static void gfx_v12_1_set_rlc_funcs(struct amdgpu_device *adev) 3828 { 3829 adev->gfx.rlc.funcs = &gfx_v12_1_rlc_funcs; 3830 } 3831 3832 static void gfx_v12_1_set_mqd_funcs(struct amdgpu_device *adev) 3833 { 3834 /* set compute eng mqd */ 3835 adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size = 3836 sizeof(struct v12_1_compute_mqd); 3837 adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd = 3838 gfx_v12_1_compute_mqd_init; 3839 } 3840 3841 static void gfx_v12_1_set_user_cu_inactive_bitmap_per_sh(struct amdgpu_device *adev, 3842 u32 bitmap, int xcc_id) 3843 { 3844 u32 data; 3845 3846 if (!bitmap) 3847 return; 3848 3849 data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 3850 data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 3851 3852 WREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG, data); 3853 } 3854 3855 static u32 gfx_v12_1_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev, 3856 int xcc_id) 3857 { 3858 u32 data, mask; 3859 3860 data = RREG32_SOC15(GC, GET_INST(GC, xcc_id), regCC_GC_SHADER_ARRAY_CONFIG); 3861 data |= RREG32_SOC15(GC, GET_INST(GC, xcc_id), regGC_USER_SHADER_ARRAY_CONFIG); 3862 3863 data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK; 3864 data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT; 3865 3866 mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh); 3867 3868 return (~data) & mask; 3869 } 3870 3871 static int gfx_v12_1_get_cu_info(struct amdgpu_device *adev, 3872 struct amdgpu_cu_info *cu_info) 3873 { 3874 int i, j, k, counter, xcc_id, active_cu_number = 0; 3875 u32 mask, bitmap; 3876 unsigned int disable_masks[2 * 2]; 3877 3878 if (!adev || !cu_info) 3879 return -EINVAL; 3880 3881 if (adev->gfx.config.max_shader_engines > 2 || 3882 adev->gfx.config.max_sh_per_se > 2) { 3883 dev_err(adev->dev, 3884 "Max SE (%d) and Max SA per SE (%d) is greater than expected\n", 3885 adev->gfx.config.max_shader_engines, 3886 adev->gfx.config.max_sh_per_se); 3887 return -EINVAL; 3888 } 3889 3890 amdgpu_gfx_parse_disable_cu(adev, disable_masks, 3891 adev->gfx.config.max_shader_engines, 3892 adev->gfx.config.max_sh_per_se); 3893 3894 mutex_lock(&adev->grbm_idx_mutex); 3895 for (xcc_id = 0; xcc_id < NUM_XCC(adev->gfx.xcc_mask); xcc_id++) { 3896 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) { 3897 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) { 3898 bitmap = i * adev->gfx.config.max_sh_per_se + j; 3899 if (!((gfx_v12_1_get_sa_active_bitmap(adev, xcc_id) >> bitmap) & 1)) 3900 continue; 3901 mask = 1; 3902 counter = 0; 3903 gfx_v12_1_xcc_select_se_sh(adev, i, j, 0xffffffff, xcc_id); 3904 gfx_v12_1_set_user_cu_inactive_bitmap_per_sh( 3905 adev, 3906 disable_masks[i * adev->gfx.config.max_sh_per_se + j], 3907 xcc_id); 3908 bitmap = gfx_v12_1_get_cu_active_bitmap_per_sh(adev, xcc_id); 3909 3910 cu_info->bitmap[xcc_id][i][j] = bitmap; 3911 3912 for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) { 3913 if (bitmap & mask) 3914 counter++; 3915 3916 mask <<= 1; 3917 } 3918 active_cu_number += counter; 3919 } 3920 } 3921 gfx_v12_1_xcc_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, xcc_id); 3922 } 3923 mutex_unlock(&adev->grbm_idx_mutex); 3924 3925 cu_info->number = active_cu_number; 3926 cu_info->simd_per_cu = NUM_SIMD_PER_CU_GFX12_1; 3927 cu_info->lds_size = 320; 3928 3929 return 0; 3930 } 3931 3932 const struct amdgpu_ip_block_version gfx_v12_1_ip_block = { 3933 .type = AMD_IP_BLOCK_TYPE_GFX, 3934 .major = 12, 3935 .minor = 1, 3936 .rev = 0, 3937 .funcs = &gfx_v12_1_ip_funcs, 3938 }; 3939 3940 static int gfx_v12_1_xcp_resume(void *handle, uint32_t inst_mask) 3941 { 3942 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3943 uint32_t tmp_mask; 3944 int i, r; 3945 3946 /* TODO : Initialize golden regs */ 3947 /* gfx_v12_1_init_golden_registers(adev); */ 3948 3949 tmp_mask = inst_mask; 3950 for_each_inst(i, tmp_mask) 3951 gfx_v12_1_xcc_constants_init(adev, i); 3952 3953 if (!amdgpu_sriov_vf(adev)) { 3954 tmp_mask = inst_mask; 3955 for_each_inst(i, tmp_mask) { 3956 r = gfx_v12_1_xcc_rlc_resume(adev, i); 3957 if (r) 3958 return r; 3959 } 3960 } 3961 3962 r = gfx_v12_1_xcc_cp_resume(adev, inst_mask); 3963 3964 return r; 3965 } 3966 3967 static int gfx_v12_1_xcp_suspend(void *handle, uint32_t inst_mask) 3968 { 3969 struct amdgpu_device *adev = (struct amdgpu_device *)handle; 3970 int i; 3971 3972 for_each_inst(i, inst_mask) 3973 gfx_v12_1_xcc_fini(adev, i); 3974 3975 return 0; 3976 } 3977 3978 struct amdgpu_xcp_ip_funcs gfx_v12_1_xcp_funcs = { 3979 .suspend = &gfx_v12_1_xcp_suspend, 3980 .resume = &gfx_v12_1_xcp_resume 3981 }; 3982