1 /* 2 * Copyright 2008 Advanced Micro Devices, Inc. 3 * Copyright 2008 Red Hat Inc. 4 * Copyright 2009 Jerome Glisse. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Dave Airlie 25 * Alex Deucher 26 * Jerome Glisse 27 */ 28 29 #include <linux/debugfs.h> 30 #include <linux/iosys-map.h> 31 #include <linux/pci.h> 32 33 #include <drm/drm_device.h> 34 #include <drm/drm_file.h> 35 #include <drm/drm_gem_ttm_helper.h> 36 #include <drm/radeon_drm.h> 37 38 #include "radeon.h" 39 #include "radeon_prime.h" 40 41 struct dma_buf *radeon_gem_prime_export(struct drm_gem_object *gobj, 42 int flags); 43 struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj); 44 int radeon_gem_prime_pin(struct drm_gem_object *obj); 45 void radeon_gem_prime_unpin(struct drm_gem_object *obj); 46 47 const struct drm_gem_object_funcs radeon_gem_object_funcs; 48 49 static vm_fault_t radeon_gem_fault(struct vm_fault *vmf) 50 { 51 struct ttm_buffer_object *bo = vmf->vma->vm_private_data; 52 struct radeon_device *rdev = radeon_get_rdev(bo->bdev); 53 vm_fault_t ret; 54 55 down_read(&rdev->pm.mclk_lock); 56 57 ret = ttm_bo_vm_reserve(bo, vmf); 58 if (ret) 59 goto unlock_mclk; 60 61 ret = radeon_bo_fault_reserve_notify(bo); 62 if (ret) 63 goto unlock_resv; 64 65 ret = ttm_bo_vm_fault_reserved(vmf, vmf->vma->vm_page_prot, 66 TTM_BO_VM_NUM_PREFAULT); 67 if (ret == VM_FAULT_RETRY && !(vmf->flags & FAULT_FLAG_RETRY_NOWAIT)) 68 goto unlock_mclk; 69 70 unlock_resv: 71 dma_resv_unlock(bo->base.resv); 72 73 unlock_mclk: 74 up_read(&rdev->pm.mclk_lock); 75 return ret; 76 } 77 78 static const struct vm_operations_struct radeon_gem_vm_ops = { 79 .fault = radeon_gem_fault, 80 .open = ttm_bo_vm_open, 81 .close = ttm_bo_vm_close, 82 .access = ttm_bo_vm_access 83 }; 84 85 static void radeon_gem_object_free(struct drm_gem_object *gobj) 86 { 87 struct radeon_bo *robj = gem_to_radeon_bo(gobj); 88 89 if (robj) { 90 radeon_mn_unregister(robj); 91 ttm_bo_put(&robj->tbo); 92 } 93 } 94 95 int radeon_gem_object_create(struct radeon_device *rdev, unsigned long size, 96 int alignment, int initial_domain, 97 u32 flags, bool kernel, 98 struct drm_gem_object **obj) 99 { 100 struct radeon_bo *robj; 101 unsigned long max_size; 102 int r; 103 104 *obj = NULL; 105 /* At least align on page size */ 106 if (alignment < PAGE_SIZE) { 107 alignment = PAGE_SIZE; 108 } 109 110 /* Maximum bo size is the unpinned gtt size since we use the gtt to 111 * handle vram to system pool migrations. 112 */ 113 max_size = rdev->mc.gtt_size - rdev->gart_pin_size; 114 if (size > max_size) { 115 DRM_DEBUG("Allocation size %ldMb bigger than %ldMb limit\n", 116 size >> 20, max_size >> 20); 117 return -ENOMEM; 118 } 119 120 retry: 121 r = radeon_bo_create(rdev, size, alignment, kernel, initial_domain, 122 flags, NULL, NULL, &robj); 123 if (r) { 124 if (r != -ERESTARTSYS) { 125 if (initial_domain == RADEON_GEM_DOMAIN_VRAM) { 126 initial_domain |= RADEON_GEM_DOMAIN_GTT; 127 goto retry; 128 } 129 DRM_ERROR("Failed to allocate GEM object (%ld, %d, %u, %d)\n", 130 size, initial_domain, alignment, r); 131 } 132 return r; 133 } 134 *obj = &robj->tbo.base; 135 (*obj)->funcs = &radeon_gem_object_funcs; 136 robj->pid = task_pid_nr(current); 137 138 mutex_lock(&rdev->gem.mutex); 139 list_add_tail(&robj->list, &rdev->gem.objects); 140 mutex_unlock(&rdev->gem.mutex); 141 142 return 0; 143 } 144 145 static int radeon_gem_set_domain(struct drm_gem_object *gobj, 146 uint32_t rdomain, uint32_t wdomain) 147 { 148 struct radeon_bo *robj; 149 uint32_t domain; 150 long r; 151 152 /* FIXME: reeimplement */ 153 robj = gem_to_radeon_bo(gobj); 154 /* work out where to validate the buffer to */ 155 domain = wdomain; 156 if (!domain) { 157 domain = rdomain; 158 } 159 if (!domain) { 160 /* Do nothings */ 161 pr_warn("Set domain without domain !\n"); 162 return 0; 163 } 164 if (domain == RADEON_GEM_DOMAIN_CPU) { 165 /* Asking for cpu access wait for object idle */ 166 r = dma_resv_wait_timeout(robj->tbo.base.resv, 167 DMA_RESV_USAGE_BOOKKEEP, 168 true, 30 * HZ); 169 if (!r) 170 r = -EBUSY; 171 172 if (r < 0 && r != -EINTR) { 173 pr_err("Failed to wait for object: %li\n", r); 174 return r; 175 } 176 } 177 if (domain == RADEON_GEM_DOMAIN_VRAM && robj->prime_shared_count) { 178 /* A BO that is associated with a dma-buf cannot be sensibly migrated to VRAM */ 179 return -EINVAL; 180 } 181 return 0; 182 } 183 184 int radeon_gem_init(struct radeon_device *rdev) 185 { 186 INIT_LIST_HEAD(&rdev->gem.objects); 187 return 0; 188 } 189 190 void radeon_gem_fini(struct radeon_device *rdev) 191 { 192 radeon_bo_force_delete(rdev); 193 } 194 195 /* 196 * Call from drm_gem_handle_create which appear in both new and open ioctl 197 * case. 198 */ 199 static int radeon_gem_object_open(struct drm_gem_object *obj, struct drm_file *file_priv) 200 { 201 struct radeon_bo *rbo = gem_to_radeon_bo(obj); 202 struct radeon_device *rdev = rbo->rdev; 203 struct radeon_fpriv *fpriv = file_priv->driver_priv; 204 struct radeon_vm *vm = &fpriv->vm; 205 struct radeon_bo_va *bo_va; 206 int r; 207 208 if ((rdev->family < CHIP_CAYMAN) || 209 (!rdev->accel_working)) { 210 return 0; 211 } 212 213 r = radeon_bo_reserve(rbo, false); 214 if (r) { 215 return r; 216 } 217 218 bo_va = radeon_vm_bo_find(vm, rbo); 219 if (!bo_va) { 220 bo_va = radeon_vm_bo_add(rdev, vm, rbo); 221 } else { 222 ++bo_va->ref_count; 223 } 224 radeon_bo_unreserve(rbo); 225 226 return 0; 227 } 228 229 static void radeon_gem_object_close(struct drm_gem_object *obj, 230 struct drm_file *file_priv) 231 { 232 struct radeon_bo *rbo = gem_to_radeon_bo(obj); 233 struct radeon_device *rdev = rbo->rdev; 234 struct radeon_fpriv *fpriv = file_priv->driver_priv; 235 struct radeon_vm *vm = &fpriv->vm; 236 struct radeon_bo_va *bo_va; 237 int r; 238 239 if ((rdev->family < CHIP_CAYMAN) || 240 (!rdev->accel_working)) { 241 return; 242 } 243 244 r = radeon_bo_reserve(rbo, true); 245 if (r) { 246 dev_err(rdev->dev, "leaking bo va because " 247 "we fail to reserve bo (%d)\n", r); 248 return; 249 } 250 bo_va = radeon_vm_bo_find(vm, rbo); 251 if (bo_va) { 252 if (--bo_va->ref_count == 0) { 253 radeon_vm_bo_rmv(rdev, bo_va); 254 } 255 } 256 radeon_bo_unreserve(rbo); 257 } 258 259 static int radeon_gem_handle_lockup(struct radeon_device *rdev, int r) 260 { 261 if (r == -EDEADLK) { 262 r = radeon_gpu_reset(rdev); 263 if (!r) 264 r = -EAGAIN; 265 } 266 return r; 267 } 268 269 static int radeon_gem_object_mmap(struct drm_gem_object *obj, struct vm_area_struct *vma) 270 { 271 struct radeon_bo *bo = gem_to_radeon_bo(obj); 272 struct radeon_device *rdev = radeon_get_rdev(bo->tbo.bdev); 273 274 if (radeon_ttm_tt_has_userptr(rdev, bo->tbo.ttm)) 275 return -EPERM; 276 277 return drm_gem_ttm_mmap(obj, vma); 278 } 279 280 const struct drm_gem_object_funcs radeon_gem_object_funcs = { 281 .free = radeon_gem_object_free, 282 .open = radeon_gem_object_open, 283 .close = radeon_gem_object_close, 284 .export = radeon_gem_prime_export, 285 .pin = radeon_gem_prime_pin, 286 .unpin = radeon_gem_prime_unpin, 287 .get_sg_table = radeon_gem_prime_get_sg_table, 288 .vmap = drm_gem_ttm_vmap, 289 .vunmap = drm_gem_ttm_vunmap, 290 .mmap = radeon_gem_object_mmap, 291 .vm_ops = &radeon_gem_vm_ops, 292 }; 293 294 /* 295 * GEM ioctls. 296 */ 297 int radeon_gem_info_ioctl(struct drm_device *dev, void *data, 298 struct drm_file *filp) 299 { 300 struct radeon_device *rdev = dev->dev_private; 301 struct drm_radeon_gem_info *args = data; 302 struct ttm_resource_manager *man; 303 304 man = ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM); 305 306 args->vram_size = (u64)man->size << PAGE_SHIFT; 307 args->vram_visible = rdev->mc.visible_vram_size; 308 args->vram_visible -= rdev->vram_pin_size; 309 args->gart_size = rdev->mc.gtt_size; 310 args->gart_size -= rdev->gart_pin_size; 311 312 return 0; 313 } 314 315 int radeon_gem_create_ioctl(struct drm_device *dev, void *data, 316 struct drm_file *filp) 317 { 318 struct radeon_device *rdev = dev->dev_private; 319 struct drm_radeon_gem_create *args = data; 320 struct drm_gem_object *gobj; 321 uint32_t handle; 322 int r; 323 324 down_read(&rdev->exclusive_lock); 325 /* create a gem object to contain this object in */ 326 args->size = roundup(args->size, PAGE_SIZE); 327 r = radeon_gem_object_create(rdev, args->size, args->alignment, 328 args->initial_domain, args->flags, 329 false, &gobj); 330 if (r) { 331 up_read(&rdev->exclusive_lock); 332 r = radeon_gem_handle_lockup(rdev, r); 333 return r; 334 } 335 r = drm_gem_handle_create(filp, gobj, &handle); 336 /* drop reference from allocate - handle holds it now */ 337 drm_gem_object_put(gobj); 338 if (r) { 339 up_read(&rdev->exclusive_lock); 340 r = radeon_gem_handle_lockup(rdev, r); 341 return r; 342 } 343 args->handle = handle; 344 up_read(&rdev->exclusive_lock); 345 return 0; 346 } 347 348 int radeon_gem_userptr_ioctl(struct drm_device *dev, void *data, 349 struct drm_file *filp) 350 { 351 struct ttm_operation_ctx ctx = { true, false }; 352 struct radeon_device *rdev = dev->dev_private; 353 struct drm_radeon_gem_userptr *args = data; 354 struct drm_gem_object *gobj; 355 struct radeon_bo *bo; 356 uint32_t handle; 357 int r; 358 359 args->addr = untagged_addr(args->addr); 360 361 if (offset_in_page(args->addr | args->size)) 362 return -EINVAL; 363 364 /* reject unknown flag values */ 365 if (args->flags & ~(RADEON_GEM_USERPTR_READONLY | 366 RADEON_GEM_USERPTR_ANONONLY | RADEON_GEM_USERPTR_VALIDATE | 367 RADEON_GEM_USERPTR_REGISTER)) 368 return -EINVAL; 369 370 if (args->flags & RADEON_GEM_USERPTR_READONLY) { 371 /* readonly pages not tested on older hardware */ 372 if (rdev->family < CHIP_R600) 373 return -EINVAL; 374 375 } else if (!(args->flags & RADEON_GEM_USERPTR_ANONONLY) || 376 !(args->flags & RADEON_GEM_USERPTR_REGISTER)) { 377 378 /* if we want to write to it we must require anonymous 379 memory and install a MMU notifier */ 380 return -EACCES; 381 } 382 383 down_read(&rdev->exclusive_lock); 384 385 /* create a gem object to contain this object in */ 386 r = radeon_gem_object_create(rdev, args->size, 0, 387 RADEON_GEM_DOMAIN_CPU, 0, 388 false, &gobj); 389 if (r) 390 goto handle_lockup; 391 392 bo = gem_to_radeon_bo(gobj); 393 r = radeon_ttm_tt_set_userptr(rdev, bo->tbo.ttm, args->addr, args->flags); 394 if (r) 395 goto release_object; 396 397 if (args->flags & RADEON_GEM_USERPTR_REGISTER) { 398 r = radeon_mn_register(bo, args->addr); 399 if (r) 400 goto release_object; 401 } 402 403 if (args->flags & RADEON_GEM_USERPTR_VALIDATE) { 404 mmap_read_lock(current->mm); 405 r = radeon_bo_reserve(bo, true); 406 if (r) { 407 mmap_read_unlock(current->mm); 408 goto release_object; 409 } 410 411 radeon_ttm_placement_from_domain(bo, RADEON_GEM_DOMAIN_GTT); 412 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 413 radeon_bo_unreserve(bo); 414 mmap_read_unlock(current->mm); 415 if (r) 416 goto release_object; 417 } 418 419 r = drm_gem_handle_create(filp, gobj, &handle); 420 /* drop reference from allocate - handle holds it now */ 421 drm_gem_object_put(gobj); 422 if (r) 423 goto handle_lockup; 424 425 args->handle = handle; 426 up_read(&rdev->exclusive_lock); 427 return 0; 428 429 release_object: 430 drm_gem_object_put(gobj); 431 432 handle_lockup: 433 up_read(&rdev->exclusive_lock); 434 r = radeon_gem_handle_lockup(rdev, r); 435 436 return r; 437 } 438 439 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data, 440 struct drm_file *filp) 441 { 442 /* transition the BO to a domain - 443 * just validate the BO into a certain domain */ 444 struct radeon_device *rdev = dev->dev_private; 445 struct drm_radeon_gem_set_domain *args = data; 446 struct drm_gem_object *gobj; 447 int r; 448 449 /* for now if someone requests domain CPU - 450 * just make sure the buffer is finished with */ 451 down_read(&rdev->exclusive_lock); 452 453 /* just do a BO wait for now */ 454 gobj = drm_gem_object_lookup(filp, args->handle); 455 if (gobj == NULL) { 456 up_read(&rdev->exclusive_lock); 457 return -ENOENT; 458 } 459 460 r = radeon_gem_set_domain(gobj, args->read_domains, args->write_domain); 461 462 drm_gem_object_put(gobj); 463 up_read(&rdev->exclusive_lock); 464 r = radeon_gem_handle_lockup(rdev, r); 465 return r; 466 } 467 468 int radeon_mode_dumb_mmap(struct drm_file *filp, 469 struct drm_device *dev, 470 uint32_t handle, uint64_t *offset_p) 471 { 472 struct drm_gem_object *gobj; 473 struct radeon_bo *robj; 474 475 gobj = drm_gem_object_lookup(filp, handle); 476 if (gobj == NULL) { 477 return -ENOENT; 478 } 479 robj = gem_to_radeon_bo(gobj); 480 if (radeon_ttm_tt_has_userptr(robj->rdev, robj->tbo.ttm)) { 481 drm_gem_object_put(gobj); 482 return -EPERM; 483 } 484 *offset_p = radeon_bo_mmap_offset(robj); 485 drm_gem_object_put(gobj); 486 return 0; 487 } 488 489 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data, 490 struct drm_file *filp) 491 { 492 struct drm_radeon_gem_mmap *args = data; 493 494 return radeon_mode_dumb_mmap(filp, dev, args->handle, &args->addr_ptr); 495 } 496 497 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data, 498 struct drm_file *filp) 499 { 500 struct drm_radeon_gem_busy *args = data; 501 struct drm_gem_object *gobj; 502 struct radeon_bo *robj; 503 int r; 504 uint32_t cur_placement = 0; 505 506 gobj = drm_gem_object_lookup(filp, args->handle); 507 if (gobj == NULL) { 508 return -ENOENT; 509 } 510 robj = gem_to_radeon_bo(gobj); 511 512 r = dma_resv_test_signaled(robj->tbo.base.resv, DMA_RESV_USAGE_READ); 513 if (r == 0) 514 r = -EBUSY; 515 else 516 r = 0; 517 518 cur_placement = READ_ONCE(robj->tbo.resource->mem_type); 519 args->domain = radeon_mem_type_to_domain(cur_placement); 520 drm_gem_object_put(gobj); 521 return r; 522 } 523 524 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data, 525 struct drm_file *filp) 526 { 527 struct radeon_device *rdev = dev->dev_private; 528 struct drm_radeon_gem_wait_idle *args = data; 529 struct drm_gem_object *gobj; 530 struct radeon_bo *robj; 531 int r = 0; 532 uint32_t cur_placement = 0; 533 long ret; 534 535 gobj = drm_gem_object_lookup(filp, args->handle); 536 if (gobj == NULL) { 537 return -ENOENT; 538 } 539 robj = gem_to_radeon_bo(gobj); 540 541 ret = dma_resv_wait_timeout(robj->tbo.base.resv, DMA_RESV_USAGE_READ, 542 true, 30 * HZ); 543 if (ret == 0) 544 r = -EBUSY; 545 else if (ret < 0) 546 r = ret; 547 548 /* Flush HDP cache via MMIO if necessary */ 549 cur_placement = READ_ONCE(robj->tbo.resource->mem_type); 550 if (rdev->asic->mmio_hdp_flush && 551 radeon_mem_type_to_domain(cur_placement) == RADEON_GEM_DOMAIN_VRAM) 552 robj->rdev->asic->mmio_hdp_flush(rdev); 553 drm_gem_object_put(gobj); 554 r = radeon_gem_handle_lockup(rdev, r); 555 return r; 556 } 557 558 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data, 559 struct drm_file *filp) 560 { 561 struct drm_radeon_gem_set_tiling *args = data; 562 struct drm_gem_object *gobj; 563 struct radeon_bo *robj; 564 int r = 0; 565 566 DRM_DEBUG("%d \n", args->handle); 567 gobj = drm_gem_object_lookup(filp, args->handle); 568 if (gobj == NULL) 569 return -ENOENT; 570 robj = gem_to_radeon_bo(gobj); 571 r = radeon_bo_set_tiling_flags(robj, args->tiling_flags, args->pitch); 572 drm_gem_object_put(gobj); 573 return r; 574 } 575 576 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data, 577 struct drm_file *filp) 578 { 579 struct drm_radeon_gem_get_tiling *args = data; 580 struct drm_gem_object *gobj; 581 struct radeon_bo *rbo; 582 int r = 0; 583 584 DRM_DEBUG("\n"); 585 gobj = drm_gem_object_lookup(filp, args->handle); 586 if (gobj == NULL) 587 return -ENOENT; 588 rbo = gem_to_radeon_bo(gobj); 589 r = radeon_bo_reserve(rbo, false); 590 if (unlikely(r != 0)) 591 goto out; 592 radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); 593 radeon_bo_unreserve(rbo); 594 out: 595 drm_gem_object_put(gobj); 596 return r; 597 } 598 599 /** 600 * radeon_gem_va_update_vm -update the bo_va in its VM 601 * 602 * @rdev: radeon_device pointer 603 * @bo_va: bo_va to update 604 * 605 * Update the bo_va directly after setting it's address. Errors are not 606 * vital here, so they are not reported back to userspace. 607 */ 608 static void radeon_gem_va_update_vm(struct radeon_device *rdev, 609 struct radeon_bo_va *bo_va) 610 { 611 struct ttm_validate_buffer tv, *entry; 612 struct radeon_bo_list *vm_bos; 613 struct ww_acquire_ctx ticket; 614 struct list_head list; 615 unsigned domain; 616 int r; 617 618 INIT_LIST_HEAD(&list); 619 620 tv.bo = &bo_va->bo->tbo; 621 tv.num_shared = 1; 622 list_add(&tv.head, &list); 623 624 vm_bos = radeon_vm_get_bos(rdev, bo_va->vm, &list); 625 if (!vm_bos) 626 return; 627 628 r = ttm_eu_reserve_buffers(&ticket, &list, true, NULL); 629 if (r) 630 goto error_free; 631 632 list_for_each_entry(entry, &list, head) { 633 domain = radeon_mem_type_to_domain(entry->bo->resource->mem_type); 634 /* if anything is swapped out don't swap it in here, 635 just abort and wait for the next CS */ 636 if (domain == RADEON_GEM_DOMAIN_CPU) 637 goto error_unreserve; 638 } 639 640 mutex_lock(&bo_va->vm->mutex); 641 r = radeon_vm_clear_freed(rdev, bo_va->vm); 642 if (r) 643 goto error_unlock; 644 645 if (bo_va->it.start && bo_va->bo) 646 r = radeon_vm_bo_update(rdev, bo_va, bo_va->bo->tbo.resource); 647 648 error_unlock: 649 mutex_unlock(&bo_va->vm->mutex); 650 651 error_unreserve: 652 ttm_eu_backoff_reservation(&ticket, &list); 653 654 error_free: 655 kvfree(vm_bos); 656 657 if (r && r != -ERESTARTSYS) 658 DRM_ERROR("Couldn't update BO_VA (%d)\n", r); 659 } 660 661 int radeon_gem_va_ioctl(struct drm_device *dev, void *data, 662 struct drm_file *filp) 663 { 664 struct drm_radeon_gem_va *args = data; 665 struct drm_gem_object *gobj; 666 struct radeon_device *rdev = dev->dev_private; 667 struct radeon_fpriv *fpriv = filp->driver_priv; 668 struct radeon_bo *rbo; 669 struct radeon_bo_va *bo_va; 670 u32 invalid_flags; 671 int r = 0; 672 673 if (!rdev->vm_manager.enabled) { 674 args->operation = RADEON_VA_RESULT_ERROR; 675 return -ENOTTY; 676 } 677 678 /* !! DONT REMOVE !! 679 * We don't support vm_id yet, to be sure we don't have broken 680 * userspace, reject anyone trying to use non 0 value thus moving 681 * forward we can use those fields without breaking existant userspace 682 */ 683 if (args->vm_id) { 684 args->operation = RADEON_VA_RESULT_ERROR; 685 return -EINVAL; 686 } 687 688 if (args->offset < RADEON_VA_RESERVED_SIZE) { 689 dev_err(dev->dev, 690 "offset 0x%lX is in reserved area 0x%X\n", 691 (unsigned long)args->offset, 692 RADEON_VA_RESERVED_SIZE); 693 args->operation = RADEON_VA_RESULT_ERROR; 694 return -EINVAL; 695 } 696 697 /* don't remove, we need to enforce userspace to set the snooped flag 698 * otherwise we will endup with broken userspace and we won't be able 699 * to enable this feature without adding new interface 700 */ 701 invalid_flags = RADEON_VM_PAGE_VALID | RADEON_VM_PAGE_SYSTEM; 702 if ((args->flags & invalid_flags)) { 703 dev_err(dev->dev, "invalid flags 0x%08X vs 0x%08X\n", 704 args->flags, invalid_flags); 705 args->operation = RADEON_VA_RESULT_ERROR; 706 return -EINVAL; 707 } 708 709 switch (args->operation) { 710 case RADEON_VA_MAP: 711 case RADEON_VA_UNMAP: 712 break; 713 default: 714 dev_err(dev->dev, "unsupported operation %d\n", 715 args->operation); 716 args->operation = RADEON_VA_RESULT_ERROR; 717 return -EINVAL; 718 } 719 720 gobj = drm_gem_object_lookup(filp, args->handle); 721 if (gobj == NULL) { 722 args->operation = RADEON_VA_RESULT_ERROR; 723 return -ENOENT; 724 } 725 rbo = gem_to_radeon_bo(gobj); 726 r = radeon_bo_reserve(rbo, false); 727 if (r) { 728 args->operation = RADEON_VA_RESULT_ERROR; 729 drm_gem_object_put(gobj); 730 return r; 731 } 732 bo_va = radeon_vm_bo_find(&fpriv->vm, rbo); 733 if (!bo_va) { 734 args->operation = RADEON_VA_RESULT_ERROR; 735 radeon_bo_unreserve(rbo); 736 drm_gem_object_put(gobj); 737 return -ENOENT; 738 } 739 740 switch (args->operation) { 741 case RADEON_VA_MAP: 742 if (bo_va->it.start) { 743 args->operation = RADEON_VA_RESULT_VA_EXIST; 744 args->offset = bo_va->it.start * RADEON_GPU_PAGE_SIZE; 745 radeon_bo_unreserve(rbo); 746 goto out; 747 } 748 r = radeon_vm_bo_set_addr(rdev, bo_va, args->offset, args->flags); 749 break; 750 case RADEON_VA_UNMAP: 751 r = radeon_vm_bo_set_addr(rdev, bo_va, 0, 0); 752 break; 753 default: 754 break; 755 } 756 if (!r) 757 radeon_gem_va_update_vm(rdev, bo_va); 758 args->operation = RADEON_VA_RESULT_OK; 759 if (r) { 760 args->operation = RADEON_VA_RESULT_ERROR; 761 } 762 out: 763 drm_gem_object_put(gobj); 764 return r; 765 } 766 767 int radeon_gem_op_ioctl(struct drm_device *dev, void *data, 768 struct drm_file *filp) 769 { 770 struct drm_radeon_gem_op *args = data; 771 struct drm_gem_object *gobj; 772 struct radeon_bo *robj; 773 int r; 774 775 gobj = drm_gem_object_lookup(filp, args->handle); 776 if (gobj == NULL) { 777 return -ENOENT; 778 } 779 robj = gem_to_radeon_bo(gobj); 780 781 r = -EPERM; 782 if (radeon_ttm_tt_has_userptr(robj->rdev, robj->tbo.ttm)) 783 goto out; 784 785 r = radeon_bo_reserve(robj, false); 786 if (unlikely(r)) 787 goto out; 788 789 switch (args->op) { 790 case RADEON_GEM_OP_GET_INITIAL_DOMAIN: 791 args->value = robj->initial_domain; 792 break; 793 case RADEON_GEM_OP_SET_INITIAL_DOMAIN: 794 robj->initial_domain = args->value & (RADEON_GEM_DOMAIN_VRAM | 795 RADEON_GEM_DOMAIN_GTT | 796 RADEON_GEM_DOMAIN_CPU); 797 break; 798 default: 799 r = -EINVAL; 800 } 801 802 radeon_bo_unreserve(robj); 803 out: 804 drm_gem_object_put(gobj); 805 return r; 806 } 807 808 int radeon_align_pitch(struct radeon_device *rdev, int width, int cpp, bool tiled) 809 { 810 int aligned = width; 811 int align_large = (ASIC_IS_AVIVO(rdev)) || tiled; 812 int pitch_mask = 0; 813 814 switch (cpp) { 815 case 1: 816 pitch_mask = align_large ? 255 : 127; 817 break; 818 case 2: 819 pitch_mask = align_large ? 127 : 31; 820 break; 821 case 3: 822 case 4: 823 pitch_mask = align_large ? 63 : 15; 824 break; 825 } 826 827 aligned += pitch_mask; 828 aligned &= ~pitch_mask; 829 return aligned * cpp; 830 } 831 832 int radeon_mode_dumb_create(struct drm_file *file_priv, 833 struct drm_device *dev, 834 struct drm_mode_create_dumb *args) 835 { 836 struct radeon_device *rdev = dev->dev_private; 837 struct drm_gem_object *gobj; 838 uint32_t handle; 839 int r; 840 841 args->pitch = radeon_align_pitch(rdev, args->width, 842 DIV_ROUND_UP(args->bpp, 8), 0); 843 args->size = (u64)args->pitch * args->height; 844 args->size = ALIGN(args->size, PAGE_SIZE); 845 846 r = radeon_gem_object_create(rdev, args->size, 0, 847 RADEON_GEM_DOMAIN_VRAM, 0, 848 false, &gobj); 849 if (r) 850 return -ENOMEM; 851 852 r = drm_gem_handle_create(file_priv, gobj, &handle); 853 /* drop reference from allocate - handle holds it now */ 854 drm_gem_object_put(gobj); 855 if (r) { 856 return r; 857 } 858 args->handle = handle; 859 return 0; 860 } 861 862 #if defined(CONFIG_DEBUG_FS) 863 static int radeon_debugfs_gem_info_show(struct seq_file *m, void *unused) 864 { 865 struct radeon_device *rdev = m->private; 866 struct radeon_bo *rbo; 867 unsigned i = 0; 868 869 mutex_lock(&rdev->gem.mutex); 870 list_for_each_entry(rbo, &rdev->gem.objects, list) { 871 unsigned domain; 872 const char *placement; 873 874 domain = radeon_mem_type_to_domain(rbo->tbo.resource->mem_type); 875 switch (domain) { 876 case RADEON_GEM_DOMAIN_VRAM: 877 placement = "VRAM"; 878 break; 879 case RADEON_GEM_DOMAIN_GTT: 880 placement = " GTT"; 881 break; 882 case RADEON_GEM_DOMAIN_CPU: 883 default: 884 placement = " CPU"; 885 break; 886 } 887 seq_printf(m, "bo[0x%08x] %8ldkB %8ldMB %s pid %8ld\n", 888 i, radeon_bo_size(rbo) >> 10, radeon_bo_size(rbo) >> 20, 889 placement, (unsigned long)rbo->pid); 890 i++; 891 } 892 mutex_unlock(&rdev->gem.mutex); 893 return 0; 894 } 895 896 DEFINE_SHOW_ATTRIBUTE(radeon_debugfs_gem_info); 897 #endif 898 899 void radeon_gem_debugfs_init(struct radeon_device *rdev) 900 { 901 #if defined(CONFIG_DEBUG_FS) 902 struct dentry *root = rdev_to_drm(rdev)->primary->debugfs_root; 903 904 debugfs_create_file("radeon_gem_info", 0444, root, rdev, 905 &radeon_debugfs_gem_info_fops); 906 907 #endif 908 } 909