1 /* 2 * Copyright 2009 Jerome Glisse. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 /* 27 * Authors: 28 * Jerome Glisse <glisse@freedesktop.org> 29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com> 30 * Dave Airlie 31 */ 32 33 #include <linux/io.h> 34 #include <linux/list.h> 35 #include <linux/slab.h> 36 37 #include <drm/drm_cache.h> 38 #include <drm/drm_prime.h> 39 #include <drm/radeon_drm.h> 40 41 #include "radeon.h" 42 #include "radeon_trace.h" 43 #include "radeon_ttm.h" 44 45 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo); 46 47 /* 48 * To exclude mutual BO access we rely on bo_reserve exclusion, as all 49 * function are calling it. 50 */ 51 52 static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo) 53 { 54 struct radeon_bo *bo; 55 56 bo = container_of(tbo, struct radeon_bo, tbo); 57 58 mutex_lock(&bo->rdev->gem.mutex); 59 list_del_init(&bo->list); 60 mutex_unlock(&bo->rdev->gem.mutex); 61 radeon_bo_clear_surface_reg(bo); 62 WARN_ON_ONCE(!list_empty(&bo->va)); 63 if (bo->tbo.base.import_attach) 64 drm_prime_gem_destroy(&bo->tbo.base, bo->tbo.sg); 65 drm_gem_object_release(&bo->tbo.base); 66 kfree(bo); 67 } 68 69 bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo) 70 { 71 if (bo->destroy == &radeon_ttm_bo_destroy) 72 return true; 73 return false; 74 } 75 76 void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) 77 { 78 u32 c = 0, i; 79 80 rbo->placement.placement = rbo->placements; 81 if (domain & RADEON_GEM_DOMAIN_VRAM) { 82 /* Try placing BOs which don't need CPU access outside of the 83 * CPU accessible part of VRAM 84 */ 85 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) && 86 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { 87 rbo->placements[c].fpfn = 88 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 89 rbo->placements[c].mem_type = TTM_PL_VRAM; 90 rbo->placements[c++].flags = 0; 91 } 92 93 rbo->placements[c].fpfn = 0; 94 rbo->placements[c].mem_type = TTM_PL_VRAM; 95 rbo->placements[c++].flags = 0; 96 } 97 98 if (domain & RADEON_GEM_DOMAIN_GTT) { 99 rbo->placements[c].fpfn = 0; 100 rbo->placements[c].mem_type = TTM_PL_TT; 101 rbo->placements[c++].flags = 0; 102 } 103 104 if (domain & RADEON_GEM_DOMAIN_CPU) { 105 rbo->placements[c].fpfn = 0; 106 rbo->placements[c].mem_type = TTM_PL_SYSTEM; 107 rbo->placements[c++].flags = 0; 108 } 109 if (!c) { 110 rbo->placements[c].fpfn = 0; 111 rbo->placements[c].mem_type = TTM_PL_SYSTEM; 112 rbo->placements[c++].flags = 0; 113 } 114 115 rbo->placement.num_placement = c; 116 117 for (i = 0; i < c; ++i) { 118 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && 119 (rbo->placements[i].mem_type == TTM_PL_VRAM) && 120 !rbo->placements[i].fpfn) 121 rbo->placements[i].lpfn = 122 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 123 else 124 rbo->placements[i].lpfn = 0; 125 } 126 } 127 128 int radeon_bo_create(struct radeon_device *rdev, 129 unsigned long size, int byte_align, bool kernel, 130 u32 domain, u32 flags, struct sg_table *sg, 131 struct dma_resv *resv, 132 struct radeon_bo **bo_ptr) 133 { 134 struct radeon_bo *bo; 135 enum ttm_bo_type type; 136 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT; 137 int r; 138 139 size = ALIGN(size, PAGE_SIZE); 140 141 if (kernel) { 142 type = ttm_bo_type_kernel; 143 } else if (sg) { 144 type = ttm_bo_type_sg; 145 } else { 146 type = ttm_bo_type_device; 147 } 148 *bo_ptr = NULL; 149 150 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL); 151 if (bo == NULL) 152 return -ENOMEM; 153 drm_gem_private_object_init(rdev_to_drm(rdev), &bo->tbo.base, size); 154 bo->rdev = rdev; 155 bo->surface_reg = -1; 156 INIT_LIST_HEAD(&bo->list); 157 INIT_LIST_HEAD(&bo->va); 158 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM | 159 RADEON_GEM_DOMAIN_GTT | 160 RADEON_GEM_DOMAIN_CPU); 161 162 bo->flags = flags; 163 /* PCI GART is always snooped */ 164 if (!(rdev->flags & RADEON_IS_PCIE)) 165 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 166 167 /* Write-combined CPU mappings of GTT cause GPU hangs with RV6xx 168 * See https://bugs.freedesktop.org/show_bug.cgi?id=91268 169 */ 170 if (rdev->family >= CHIP_RV610 && rdev->family <= CHIP_RV635) 171 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 172 173 #ifdef CONFIG_X86_32 174 /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit 175 * See https://bugs.freedesktop.org/show_bug.cgi?id=84627 176 */ 177 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 178 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT) 179 /* Don't try to enable write-combining when it can't work, or things 180 * may be slow 181 * See https://bugs.freedesktop.org/show_bug.cgi?id=88758 182 */ 183 #ifndef CONFIG_COMPILE_TEST 184 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \ 185 thanks to write-combining 186 #endif 187 188 if (bo->flags & RADEON_GEM_GTT_WC) 189 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for " 190 "better performance thanks to write-combining\n"); 191 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC); 192 #else 193 /* For architectures that don't support WC memory, 194 * mask out the WC flag from the BO 195 */ 196 if (!drm_arch_can_wc_memory()) 197 bo->flags &= ~RADEON_GEM_GTT_WC; 198 #endif 199 200 radeon_ttm_placement_from_domain(bo, domain); 201 /* Kernel allocation are uninterruptible */ 202 down_read(&rdev->pm.mclk_lock); 203 r = ttm_bo_init_validate(&rdev->mman.bdev, &bo->tbo, type, 204 &bo->placement, page_align, !kernel, sg, resv, 205 &radeon_ttm_bo_destroy); 206 up_read(&rdev->pm.mclk_lock); 207 if (unlikely(r != 0)) { 208 return r; 209 } 210 *bo_ptr = bo; 211 212 trace_radeon_bo_create(bo); 213 214 return 0; 215 } 216 217 int radeon_bo_kmap(struct radeon_bo *bo, void **ptr) 218 { 219 bool is_iomem; 220 long r; 221 222 r = dma_resv_wait_timeout(bo->tbo.base.resv, DMA_RESV_USAGE_KERNEL, 223 false, MAX_SCHEDULE_TIMEOUT); 224 if (r < 0) 225 return r; 226 227 if (bo->kptr) { 228 if (ptr) { 229 *ptr = bo->kptr; 230 } 231 return 0; 232 } 233 r = ttm_bo_kmap(&bo->tbo, 0, PFN_UP(bo->tbo.base.size), &bo->kmap); 234 if (r) { 235 return r; 236 } 237 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem); 238 if (ptr) { 239 *ptr = bo->kptr; 240 } 241 radeon_bo_check_tiling(bo, 0, 0); 242 return 0; 243 } 244 245 void radeon_bo_kunmap(struct radeon_bo *bo) 246 { 247 if (bo->kptr == NULL) 248 return; 249 bo->kptr = NULL; 250 radeon_bo_check_tiling(bo, 0, 0); 251 ttm_bo_kunmap(&bo->kmap); 252 } 253 254 struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo) 255 { 256 if (bo == NULL) 257 return NULL; 258 259 drm_gem_object_get(&bo->tbo.base); 260 return bo; 261 } 262 263 void radeon_bo_unref(struct radeon_bo **bo) 264 { 265 if ((*bo) == NULL) 266 return; 267 drm_gem_object_put(&(*bo)->tbo.base); 268 *bo = NULL; 269 } 270 271 int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset, 272 u64 *gpu_addr) 273 { 274 struct ttm_operation_ctx ctx = { false, false }; 275 int r, i; 276 277 if (radeon_ttm_tt_has_userptr(bo->rdev, bo->tbo.ttm)) 278 return -EPERM; 279 280 if (bo->tbo.pin_count) { 281 ttm_bo_pin(&bo->tbo); 282 if (gpu_addr) 283 *gpu_addr = radeon_bo_gpu_offset(bo); 284 285 if (max_offset != 0) { 286 u64 domain_start; 287 288 if (domain == RADEON_GEM_DOMAIN_VRAM) 289 domain_start = bo->rdev->mc.vram_start; 290 else 291 domain_start = bo->rdev->mc.gtt_start; 292 WARN_ON_ONCE(max_offset < 293 (radeon_bo_gpu_offset(bo) - domain_start)); 294 } 295 296 return 0; 297 } 298 if (bo->prime_shared_count && domain == RADEON_GEM_DOMAIN_VRAM) { 299 /* A BO shared as a dma-buf cannot be sensibly migrated to VRAM */ 300 return -EINVAL; 301 } 302 303 radeon_ttm_placement_from_domain(bo, domain); 304 for (i = 0; i < bo->placement.num_placement; i++) { 305 /* force to pin into visible video ram */ 306 if ((bo->placements[i].mem_type == TTM_PL_VRAM) && 307 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) && 308 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size)) 309 bo->placements[i].lpfn = 310 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT; 311 else 312 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT; 313 } 314 315 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 316 if (likely(r == 0)) { 317 ttm_bo_pin(&bo->tbo); 318 if (gpu_addr != NULL) 319 *gpu_addr = radeon_bo_gpu_offset(bo); 320 if (domain == RADEON_GEM_DOMAIN_VRAM) 321 bo->rdev->vram_pin_size += radeon_bo_size(bo); 322 else 323 bo->rdev->gart_pin_size += radeon_bo_size(bo); 324 } else { 325 dev_err(bo->rdev->dev, "%p pin failed\n", bo); 326 } 327 return r; 328 } 329 330 int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr) 331 { 332 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr); 333 } 334 335 void radeon_bo_unpin(struct radeon_bo *bo) 336 { 337 ttm_bo_unpin(&bo->tbo); 338 if (!bo->tbo.pin_count) { 339 if (bo->tbo.resource->mem_type == TTM_PL_VRAM) 340 bo->rdev->vram_pin_size -= radeon_bo_size(bo); 341 else 342 bo->rdev->gart_pin_size -= radeon_bo_size(bo); 343 } 344 } 345 346 int radeon_bo_evict_vram(struct radeon_device *rdev) 347 { 348 struct ttm_device *bdev = &rdev->mman.bdev; 349 struct ttm_resource_manager *man; 350 351 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */ 352 #ifndef CONFIG_HIBERNATION 353 if (rdev->flags & RADEON_IS_IGP) { 354 if (rdev->mc.igp_sideport_enabled == false) 355 /* Useless to evict on IGP chips */ 356 return 0; 357 } 358 #endif 359 man = ttm_manager_type(bdev, TTM_PL_VRAM); 360 if (!man) 361 return 0; 362 return ttm_resource_manager_evict_all(bdev, man); 363 } 364 365 void radeon_bo_force_delete(struct radeon_device *rdev) 366 { 367 struct radeon_bo *bo, *n; 368 369 if (list_empty(&rdev->gem.objects)) { 370 return; 371 } 372 dev_err(rdev->dev, "Userspace still has active objects !\n"); 373 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) { 374 dev_err(rdev->dev, "%p %p %lu %lu force free\n", 375 &bo->tbo.base, bo, (unsigned long)bo->tbo.base.size, 376 *((unsigned long *)&bo->tbo.base.refcount)); 377 mutex_lock(&bo->rdev->gem.mutex); 378 list_del_init(&bo->list); 379 mutex_unlock(&bo->rdev->gem.mutex); 380 /* this should unref the ttm bo */ 381 drm_gem_object_put(&bo->tbo.base); 382 } 383 } 384 385 int radeon_bo_init(struct radeon_device *rdev) 386 { 387 /* reserve PAT memory space to WC for VRAM */ 388 arch_io_reserve_memtype_wc(rdev->mc.aper_base, 389 rdev->mc.aper_size); 390 391 /* Add an MTRR for the VRAM */ 392 if (!rdev->fastfb_working) { 393 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base, 394 rdev->mc.aper_size); 395 } 396 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n", 397 rdev->mc.mc_vram_size >> 20, 398 (unsigned long long)rdev->mc.aper_size >> 20); 399 DRM_INFO("RAM width %dbits %cDR\n", 400 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); 401 return radeon_ttm_init(rdev); 402 } 403 404 void radeon_bo_fini(struct radeon_device *rdev) 405 { 406 radeon_ttm_fini(rdev); 407 arch_phys_wc_del(rdev->mc.vram_mtrr); 408 arch_io_free_memtype_wc(rdev->mc.aper_base, rdev->mc.aper_size); 409 } 410 411 /* Returns how many bytes TTM can move per IB. 412 */ 413 static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev) 414 { 415 u64 real_vram_size = rdev->mc.real_vram_size; 416 struct ttm_resource_manager *man = 417 ttm_manager_type(&rdev->mman.bdev, TTM_PL_VRAM); 418 u64 vram_usage = ttm_resource_manager_usage(man); 419 420 /* This function is based on the current VRAM usage. 421 * 422 * - If all of VRAM is free, allow relocating the number of bytes that 423 * is equal to 1/4 of the size of VRAM for this IB. 424 425 * - If more than one half of VRAM is occupied, only allow relocating 426 * 1 MB of data for this IB. 427 * 428 * - From 0 to one half of used VRAM, the threshold decreases 429 * linearly. 430 * __________________ 431 * 1/4 of -|\ | 432 * VRAM | \ | 433 * | \ | 434 * | \ | 435 * | \ | 436 * | \ | 437 * | \ | 438 * | \________|1 MB 439 * |----------------| 440 * VRAM 0 % 100 % 441 * used used 442 * 443 * Note: It's a threshold, not a limit. The threshold must be crossed 444 * for buffer relocations to stop, so any buffer of an arbitrary size 445 * can be moved as long as the threshold isn't crossed before 446 * the relocation takes place. We don't want to disable buffer 447 * relocations completely. 448 * 449 * The idea is that buffers should be placed in VRAM at creation time 450 * and TTM should only do a minimum number of relocations during 451 * command submission. In practice, you need to submit at least 452 * a dozen IBs to move all buffers to VRAM if they are in GTT. 453 * 454 * Also, things can get pretty crazy under memory pressure and actual 455 * VRAM usage can change a lot, so playing safe even at 50% does 456 * consistently increase performance. 457 */ 458 459 u64 half_vram = real_vram_size >> 1; 460 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage; 461 u64 bytes_moved_threshold = half_free_vram >> 1; 462 return max(bytes_moved_threshold, 1024*1024ull); 463 } 464 465 int radeon_bo_list_validate(struct radeon_device *rdev, 466 struct ww_acquire_ctx *ticket, 467 struct list_head *head, int ring) 468 { 469 struct ttm_operation_ctx ctx = { true, false }; 470 struct radeon_bo_list *lobj; 471 struct list_head duplicates; 472 int r; 473 u64 bytes_moved = 0, initial_bytes_moved; 474 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev); 475 476 INIT_LIST_HEAD(&duplicates); 477 r = ttm_eu_reserve_buffers(ticket, head, true, &duplicates); 478 if (unlikely(r != 0)) { 479 return r; 480 } 481 482 list_for_each_entry(lobj, head, tv.head) { 483 struct radeon_bo *bo = lobj->robj; 484 if (!bo->tbo.pin_count) { 485 u32 domain = lobj->preferred_domains; 486 u32 allowed = lobj->allowed_domains; 487 u32 current_domain = 488 radeon_mem_type_to_domain(bo->tbo.resource->mem_type); 489 490 /* Check if this buffer will be moved and don't move it 491 * if we have moved too many buffers for this IB already. 492 * 493 * Note that this allows moving at least one buffer of 494 * any size, because it doesn't take the current "bo" 495 * into account. We don't want to disallow buffer moves 496 * completely. 497 */ 498 if ((allowed & current_domain) != 0 && 499 (domain & current_domain) == 0 && /* will be moved */ 500 bytes_moved > bytes_moved_threshold) { 501 /* don't move it */ 502 domain = current_domain; 503 } 504 505 retry: 506 radeon_ttm_placement_from_domain(bo, domain); 507 if (ring == R600_RING_TYPE_UVD_INDEX) 508 radeon_uvd_force_into_uvd_segment(bo, allowed); 509 510 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved); 511 r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx); 512 bytes_moved += atomic64_read(&rdev->num_bytes_moved) - 513 initial_bytes_moved; 514 515 if (unlikely(r)) { 516 if (r != -ERESTARTSYS && 517 domain != lobj->allowed_domains) { 518 domain = lobj->allowed_domains; 519 goto retry; 520 } 521 ttm_eu_backoff_reservation(ticket, head); 522 return r; 523 } 524 } 525 lobj->gpu_offset = radeon_bo_gpu_offset(bo); 526 lobj->tiling_flags = bo->tiling_flags; 527 } 528 529 list_for_each_entry(lobj, &duplicates, tv.head) { 530 lobj->gpu_offset = radeon_bo_gpu_offset(lobj->robj); 531 lobj->tiling_flags = lobj->robj->tiling_flags; 532 } 533 534 return 0; 535 } 536 537 int radeon_bo_get_surface_reg(struct radeon_bo *bo) 538 { 539 struct radeon_device *rdev = bo->rdev; 540 struct radeon_surface_reg *reg; 541 struct radeon_bo *old_object; 542 int steal; 543 int i; 544 545 dma_resv_assert_held(bo->tbo.base.resv); 546 547 if (!bo->tiling_flags) 548 return 0; 549 550 if (bo->surface_reg >= 0) { 551 i = bo->surface_reg; 552 goto out; 553 } 554 555 steal = -1; 556 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { 557 558 reg = &rdev->surface_regs[i]; 559 if (!reg->bo) 560 break; 561 562 old_object = reg->bo; 563 if (old_object->tbo.pin_count == 0) 564 steal = i; 565 } 566 567 /* if we are all out */ 568 if (i == RADEON_GEM_MAX_SURFACES) { 569 if (steal == -1) 570 return -ENOMEM; 571 /* find someone with a surface reg and nuke their BO */ 572 reg = &rdev->surface_regs[steal]; 573 old_object = reg->bo; 574 /* blow away the mapping */ 575 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object); 576 ttm_bo_unmap_virtual(&old_object->tbo); 577 old_object->surface_reg = -1; 578 i = steal; 579 } 580 581 bo->surface_reg = i; 582 reg->bo = bo; 583 584 out: 585 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch, 586 bo->tbo.resource->start << PAGE_SHIFT, 587 bo->tbo.base.size); 588 return 0; 589 } 590 591 static void radeon_bo_clear_surface_reg(struct radeon_bo *bo) 592 { 593 struct radeon_device *rdev = bo->rdev; 594 struct radeon_surface_reg *reg; 595 596 if (bo->surface_reg == -1) 597 return; 598 599 reg = &rdev->surface_regs[bo->surface_reg]; 600 radeon_clear_surface_reg(rdev, bo->surface_reg); 601 602 reg->bo = NULL; 603 bo->surface_reg = -1; 604 } 605 606 int radeon_bo_set_tiling_flags(struct radeon_bo *bo, 607 uint32_t tiling_flags, uint32_t pitch) 608 { 609 struct radeon_device *rdev = bo->rdev; 610 int r; 611 612 if (rdev->family >= CHIP_CEDAR) { 613 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit; 614 615 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK; 616 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK; 617 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK; 618 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK; 619 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK; 620 switch (bankw) { 621 case 0: 622 case 1: 623 case 2: 624 case 4: 625 case 8: 626 break; 627 default: 628 return -EINVAL; 629 } 630 switch (bankh) { 631 case 0: 632 case 1: 633 case 2: 634 case 4: 635 case 8: 636 break; 637 default: 638 return -EINVAL; 639 } 640 switch (mtaspect) { 641 case 0: 642 case 1: 643 case 2: 644 case 4: 645 case 8: 646 break; 647 default: 648 return -EINVAL; 649 } 650 if (tilesplit > 6) { 651 return -EINVAL; 652 } 653 if (stilesplit > 6) { 654 return -EINVAL; 655 } 656 } 657 r = radeon_bo_reserve(bo, false); 658 if (unlikely(r != 0)) 659 return r; 660 bo->tiling_flags = tiling_flags; 661 bo->pitch = pitch; 662 radeon_bo_unreserve(bo); 663 return 0; 664 } 665 666 void radeon_bo_get_tiling_flags(struct radeon_bo *bo, 667 uint32_t *tiling_flags, 668 uint32_t *pitch) 669 { 670 dma_resv_assert_held(bo->tbo.base.resv); 671 672 if (tiling_flags) 673 *tiling_flags = bo->tiling_flags; 674 if (pitch) 675 *pitch = bo->pitch; 676 } 677 678 int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved, 679 bool force_drop) 680 { 681 if (!force_drop) 682 dma_resv_assert_held(bo->tbo.base.resv); 683 684 if (!(bo->tiling_flags & RADEON_TILING_SURFACE)) 685 return 0; 686 687 if (force_drop) { 688 radeon_bo_clear_surface_reg(bo); 689 return 0; 690 } 691 692 if (bo->tbo.resource->mem_type != TTM_PL_VRAM) { 693 if (!has_moved) 694 return 0; 695 696 if (bo->surface_reg >= 0) 697 radeon_bo_clear_surface_reg(bo); 698 return 0; 699 } 700 701 if ((bo->surface_reg >= 0) && !has_moved) 702 return 0; 703 704 return radeon_bo_get_surface_reg(bo); 705 } 706 707 void radeon_bo_move_notify(struct ttm_buffer_object *bo) 708 { 709 struct radeon_bo *rbo; 710 711 if (!radeon_ttm_bo_is_radeon_bo(bo)) 712 return; 713 714 rbo = container_of(bo, struct radeon_bo, tbo); 715 radeon_bo_check_tiling(rbo, 0, 1); 716 radeon_vm_bo_invalidate(rbo->rdev, rbo); 717 } 718 719 vm_fault_t radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo) 720 { 721 struct ttm_operation_ctx ctx = { false, false }; 722 struct radeon_device *rdev; 723 struct radeon_bo *rbo; 724 unsigned long offset, size, lpfn; 725 int i, r; 726 727 if (!radeon_ttm_bo_is_radeon_bo(bo)) 728 return 0; 729 rbo = container_of(bo, struct radeon_bo, tbo); 730 radeon_bo_check_tiling(rbo, 0, 0); 731 rdev = rbo->rdev; 732 if (bo->resource->mem_type != TTM_PL_VRAM) 733 return 0; 734 735 size = bo->resource->size; 736 offset = bo->resource->start << PAGE_SHIFT; 737 if ((offset + size) <= rdev->mc.visible_vram_size) 738 return 0; 739 740 /* Can't move a pinned BO to visible VRAM */ 741 if (rbo->tbo.pin_count > 0) 742 return VM_FAULT_SIGBUS; 743 744 /* hurrah the memory is not visible ! */ 745 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); 746 lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT; 747 for (i = 0; i < rbo->placement.num_placement; i++) { 748 /* Force into visible VRAM */ 749 if ((rbo->placements[i].mem_type == TTM_PL_VRAM) && 750 (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn)) 751 rbo->placements[i].lpfn = lpfn; 752 } 753 r = ttm_bo_validate(bo, &rbo->placement, &ctx); 754 if (unlikely(r == -ENOMEM)) { 755 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); 756 r = ttm_bo_validate(bo, &rbo->placement, &ctx); 757 } else if (likely(!r)) { 758 offset = bo->resource->start << PAGE_SHIFT; 759 /* this should never happen */ 760 if ((offset + size) > rdev->mc.visible_vram_size) 761 return VM_FAULT_SIGBUS; 762 } 763 764 if (unlikely(r == -EBUSY || r == -ERESTARTSYS)) 765 return VM_FAULT_NOPAGE; 766 else if (unlikely(r)) 767 return VM_FAULT_SIGBUS; 768 769 ttm_bo_move_to_lru_tail_unlocked(bo); 770 return 0; 771 } 772 773 /** 774 * radeon_bo_fence - add fence to buffer object 775 * 776 * @bo: buffer object in question 777 * @fence: fence to add 778 * @shared: true if fence should be added shared 779 * 780 */ 781 void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence, 782 bool shared) 783 { 784 struct dma_resv *resv = bo->tbo.base.resv; 785 int r; 786 787 r = dma_resv_reserve_fences(resv, 1); 788 if (r) { 789 /* As last resort on OOM we block for the fence */ 790 dma_fence_wait(&fence->base, false); 791 return; 792 } 793 794 dma_resv_add_fence(resv, &fence->base, shared ? 795 DMA_RESV_USAGE_READ : DMA_RESV_USAGE_WRITE); 796 } 797