1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (ST) 2012 Rajeev Kumar (rajeevkumar.linux@gmail.com) 4 */ 5 6 #ifndef __DESIGNWARE_LOCAL_H 7 #define __DESIGNWARE_LOCAL_H 8 9 #include <linux/clk.h> 10 #include <linux/device.h> 11 #include <linux/types.h> 12 #include <sound/dmaengine_pcm.h> 13 #include <sound/pcm.h> 14 #include <sound/designware_i2s.h> 15 16 /* common register for all channel */ 17 #define IER 0x000 18 #define IRER 0x004 19 #define ITER 0x008 20 #define CER 0x00C 21 #define CCR 0x010 22 #define RXFFR 0x014 23 #define TXFFR 0x018 24 25 /* Enable register fields */ 26 #define IER_TDM_SLOTS_SHIFT 8 27 #define IER_FRAME_OFF_SHIFT 5 28 #define IER_FRAME_OFF BIT(5) 29 #define IER_INTF_TYPE BIT(1) 30 #define IER_IEN BIT(0) 31 32 /* Interrupt status register fields */ 33 #define ISR_TXFO BIT(5) 34 #define ISR_TXFE BIT(4) 35 #define ISR_RXFO BIT(1) 36 #define ISR_RXDA BIT(0) 37 38 /* I2STxRxRegisters for all channels */ 39 #define LRBR_LTHR(x) (0x40 * x + 0x020) 40 #define RRBR_RTHR(x) (0x40 * x + 0x024) 41 #define RER(x) (0x40 * x + 0x028) 42 #define TER(x) (0x40 * x + 0x02C) 43 #define RCR(x) (0x40 * x + 0x030) 44 #define TCR(x) (0x40 * x + 0x034) 45 #define ISR(x) (0x40 * x + 0x038) 46 #define IMR(x) (0x40 * x + 0x03C) 47 #define ROR(x) (0x40 * x + 0x040) 48 #define TOR(x) (0x40 * x + 0x044) 49 #define RFCR(x) (0x40 * x + 0x048) 50 #define TFCR(x) (0x40 * x + 0x04C) 51 #define RFF(x) (0x40 * x + 0x050) 52 #define TFF(x) (0x40 * x + 0x054) 53 #define RSLOT_TSLOT(x) (0x4 * (x) + 0x224) 54 55 /* Receive enable register fields */ 56 #define RER_RXSLOT_SHIFT 8 57 #define RER_RXCHEN BIT(0) 58 59 /* Transmit enable register fields */ 60 #define TER_TXSLOT_SHIFT 8 61 #define TER_TXCHEN BIT(0) 62 63 /* I2SCOMPRegisters */ 64 #define I2S_COMP_PARAM_2 0x01F0 65 #define I2S_COMP_PARAM_1 0x01F4 66 #define I2S_COMP_VERSION 0x01F8 67 #define I2S_COMP_TYPE 0x01FC 68 69 #define I2S_RRXDMA 0x01C4 70 #define I2S_RTXDMA 0x01CC 71 #define I2S_DMACR 0x0200 72 #define I2S_DMAEN_RXBLOCK (1 << 16) 73 #define I2S_DMAEN_TXBLOCK (1 << 17) 74 75 /* 76 * Component parameter register fields - define the I2S block's 77 * configuration. 78 */ 79 #define COMP1_TX_WORDSIZE_3(r) (((r) & GENMASK(27, 25)) >> 25) 80 #define COMP1_TX_WORDSIZE_2(r) (((r) & GENMASK(24, 22)) >> 22) 81 #define COMP1_TX_WORDSIZE_1(r) (((r) & GENMASK(21, 19)) >> 19) 82 #define COMP1_TX_WORDSIZE_0(r) (((r) & GENMASK(18, 16)) >> 16) 83 #define COMP1_TX_CHANNELS(r) (((r) & GENMASK(10, 9)) >> 9) 84 #define COMP1_RX_CHANNELS(r) (((r) & GENMASK(8, 7)) >> 7) 85 #define COMP1_RX_ENABLED(r) (((r) & BIT(6)) >> 6) 86 #define COMP1_TX_ENABLED(r) (((r) & BIT(5)) >> 5) 87 #define COMP1_MODE_EN(r) (((r) & BIT(4)) >> 4) 88 #define COMP1_FIFO_DEPTH_GLOBAL(r) (((r) & GENMASK(3, 2)) >> 2) 89 #define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0) 90 91 #define COMP2_RX_WORDSIZE_3(r) (((r) & GENMASK(12, 10)) >> 10) 92 #define COMP2_RX_WORDSIZE_2(r) (((r) & GENMASK(9, 7)) >> 7) 93 #define COMP2_RX_WORDSIZE_1(r) (((r) & GENMASK(5, 3)) >> 3) 94 #define COMP2_RX_WORDSIZE_0(r) (((r) & GENMASK(2, 0)) >> 0) 95 96 /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */ 97 #define COMP_MAX_WORDSIZE (1 << 3) 98 #define COMP_MAX_DATA_WIDTH (1 << 2) 99 100 #define MAX_CHANNEL_NUM 8 101 #define MIN_CHANNEL_NUM 2 102 103 union dw_i2s_snd_dma_data { 104 struct i2s_dma_data pd; 105 struct snd_dmaengine_dai_dma_data dt; 106 }; 107 108 struct dw_i2s_dev { 109 void __iomem *i2s_base; 110 struct clk *clk; 111 struct reset_control *reset; 112 int active; 113 unsigned int capability; 114 unsigned int quirks; 115 unsigned int i2s_reg_comp1; 116 unsigned int i2s_reg_comp2; 117 struct device *dev; 118 u32 ccr; 119 u32 xfer_resolution; 120 u32 fifo_th; 121 u32 l_reg; 122 u32 r_reg; 123 bool is_jh7110; /* Flag for StarFive JH7110 SoC */ 124 125 /* data related to DMA transfers b/w i2s and DMAC */ 126 union dw_i2s_snd_dma_data play_dma_data; 127 union dw_i2s_snd_dma_data capture_dma_data; 128 struct i2s_clk_config_data config; 129 int (*i2s_clk_cfg)(struct i2s_clk_config_data *config); 130 131 /* data related to PIO transfers */ 132 bool use_pio; 133 134 /* data related to TDM mode */ 135 u32 tdm_slots; 136 u32 tdm_mask; 137 u32 frame_offset; 138 139 struct snd_pcm_substream __rcu *tx_substream; 140 struct snd_pcm_substream __rcu *rx_substream; 141 unsigned int (*tx_fn)(struct dw_i2s_dev *dev, 142 struct snd_pcm_runtime *runtime, unsigned int tx_ptr, 143 bool *period_elapsed); 144 unsigned int (*rx_fn)(struct dw_i2s_dev *dev, 145 struct snd_pcm_runtime *runtime, unsigned int rx_ptr, 146 bool *period_elapsed); 147 unsigned int tx_ptr; 148 unsigned int rx_ptr; 149 }; 150 151 #if IS_ENABLED(CONFIG_SND_DESIGNWARE_PCM) 152 void dw_pcm_push_tx(struct dw_i2s_dev *dev); 153 void dw_pcm_pop_rx(struct dw_i2s_dev *dev); 154 int dw_pcm_register(struct platform_device *pdev); 155 #else 156 static inline void dw_pcm_push_tx(struct dw_i2s_dev *dev) { } 157 static inline void dw_pcm_pop_rx(struct dw_i2s_dev *dev) { } 158 static inline int dw_pcm_register(struct platform_device *pdev) 159 { 160 return -EINVAL; 161 } 162 #endif 163 164 #endif 165