1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/V2H(P) CPG driver 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 14 15 #include "rzv2h-cpg.h" 16 17 enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A09G057_SPI_CLK_SPI, 20 21 /* External Input Clocks */ 22 CLK_AUDIO_EXTAL, 23 CLK_RTXIN, 24 CLK_QEXTAL, 25 26 /* PLL Clocks */ 27 CLK_PLLCM33, 28 CLK_PLLCLN, 29 CLK_PLLDTY, 30 CLK_PLLCA55, 31 CLK_PLLVDO, 32 CLK_PLLETH, 33 CLK_PLLGPU, 34 35 /* Internal Core Clocks */ 36 CLK_PLLCM33_DIV3, 37 CLK_PLLCM33_DIV4, 38 CLK_PLLCM33_DIV5, 39 CLK_PLLCM33_DIV16, 40 CLK_PLLCM33_GEAR, 41 CLK_SMUX2_XSPI_CLK0, 42 CLK_SMUX2_XSPI_CLK1, 43 CLK_PLLCM33_XSPI, 44 CLK_PLLCLN_DIV2, 45 CLK_PLLCLN_DIV8, 46 CLK_PLLCLN_DIV16, 47 CLK_PLLDTY_ACPU, 48 CLK_PLLDTY_ACPU_DIV2, 49 CLK_PLLDTY_ACPU_DIV4, 50 CLK_PLLDTY_DIV8, 51 CLK_PLLDTY_DIV16, 52 CLK_PLLDTY_RCPU, 53 CLK_PLLDTY_RCPU_DIV4, 54 CLK_PLLVDO_CRU0, 55 CLK_PLLVDO_CRU1, 56 CLK_PLLVDO_CRU2, 57 CLK_PLLVDO_CRU3, 58 CLK_PLLETH_DIV_250_FIX, 59 CLK_PLLETH_DIV_125_FIX, 60 CLK_CSDIV_PLLETH_GBE0, 61 CLK_CSDIV_PLLETH_GBE1, 62 CLK_SMUX2_GBE0_TXCLK, 63 CLK_SMUX2_GBE0_RXCLK, 64 CLK_SMUX2_GBE1_TXCLK, 65 CLK_SMUX2_GBE1_RXCLK, 66 CLK_PLLGPU_GEAR, 67 68 /* Module Clocks */ 69 MOD_CLK_BASE, 70 }; 71 72 static const struct clk_div_table dtable_1_8[] = { 73 {0, 1}, 74 {1, 2}, 75 {2, 4}, 76 {3, 8}, 77 {0, 0}, 78 }; 79 80 static const struct clk_div_table dtable_2_4[] = { 81 {0, 2}, 82 {1, 4}, 83 {0, 0}, 84 }; 85 86 static const struct clk_div_table dtable_2_16[] = { 87 {0, 2}, 88 {1, 4}, 89 {2, 8}, 90 {3, 16}, 91 {0, 0}, 92 }; 93 94 static const struct clk_div_table dtable_2_64[] = { 95 {0, 2}, 96 {1, 4}, 97 {2, 8}, 98 {3, 16}, 99 {4, 64}, 100 {0, 0}, 101 }; 102 103 static const struct clk_div_table dtable_2_100[] = { 104 {0, 2}, 105 {1, 10}, 106 {2, 100}, 107 {0, 0}, 108 }; 109 110 /* Mux clock tables */ 111 static const char * const smux2_gbe0_rxclk[] = { ".plleth_gbe0", "et0_rxclk" }; 112 static const char * const smux2_gbe0_txclk[] = { ".plleth_gbe0", "et0_txclk" }; 113 static const char * const smux2_gbe1_rxclk[] = { ".plleth_gbe1", "et1_rxclk" }; 114 static const char * const smux2_gbe1_txclk[] = { ".plleth_gbe1", "et1_txclk" }; 115 static const char * const smux2_xspi_clk0[] = { ".pllcm33_div3", ".pllcm33_div4" }; 116 static const char * const smux2_xspi_clk1[] = { ".smux2_xspi_clk0", ".pllcm33_div5" }; 117 118 static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 119 /* External Clock Inputs */ 120 DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), 121 DEF_INPUT("rtxin", CLK_RTXIN), 122 DEF_INPUT("qextal", CLK_QEXTAL), 123 124 /* PLL Clocks */ 125 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), 126 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), 127 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), 128 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), 129 DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), 130 DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3), 131 DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU), 132 133 /* Internal Core Clocks */ 134 DEF_FIXED(".pllcm33_div3", CLK_PLLCM33_DIV3, CLK_PLLCM33, 1, 3), 135 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4), 136 DEF_FIXED(".pllcm33_div5", CLK_PLLCM33_DIV5, CLK_PLLCM33, 1, 5), 137 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), 138 DEF_DDIV(".pllcm33_gear", CLK_PLLCM33_GEAR, CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64), 139 DEF_SMUX(".smux2_xspi_clk0", CLK_SMUX2_XSPI_CLK0, SSEL1_SELCTL2, smux2_xspi_clk0), 140 DEF_SMUX(".smux2_xspi_clk1", CLK_SMUX2_XSPI_CLK1, SSEL1_SELCTL3, smux2_xspi_clk1), 141 DEF_CSDIV(".pllcm33_xspi", CLK_PLLCM33_XSPI, CLK_SMUX2_XSPI_CLK1, CSDIV0_DIVCTL3, 142 dtable_2_16), 143 144 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), 145 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), 146 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), 147 148 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), 149 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), 150 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), 151 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8), 152 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), 153 DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64), 154 DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4), 155 156 DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), 157 DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4), 158 DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4), 159 DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4), 160 161 DEF_FIXED(".plleth_250_fix", CLK_PLLETH_DIV_250_FIX, CLK_PLLETH, 1, 4), 162 DEF_FIXED(".plleth_125_fix", CLK_PLLETH_DIV_125_FIX, CLK_PLLETH_DIV_250_FIX, 1, 2), 163 DEF_CSDIV(".plleth_gbe0", CLK_CSDIV_PLLETH_GBE0, 164 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL0, dtable_2_100), 165 DEF_CSDIV(".plleth_gbe1", CLK_CSDIV_PLLETH_GBE1, 166 CLK_PLLETH_DIV_250_FIX, CSDIV0_DIVCTL1, dtable_2_100), 167 DEF_SMUX(".smux2_gbe0_txclk", CLK_SMUX2_GBE0_TXCLK, SSEL0_SELCTL2, smux2_gbe0_txclk), 168 DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_gbe0_rxclk), 169 DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_gbe1_txclk), 170 DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_gbe1_rxclk), 171 172 DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64), 173 174 /* Core Clocks */ 175 DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1), 176 DEF_DDIV("ca55_0_coreclk0", R9A09G057_CA55_0_CORE_CLK0, CLK_PLLCA55, 177 CDDIV1_DIVCTL0, dtable_1_8), 178 DEF_DDIV("ca55_0_coreclk1", R9A09G057_CA55_0_CORE_CLK1, CLK_PLLCA55, 179 CDDIV1_DIVCTL1, dtable_1_8), 180 DEF_DDIV("ca55_0_coreclk2", R9A09G057_CA55_0_CORE_CLK2, CLK_PLLCA55, 181 CDDIV1_DIVCTL2, dtable_1_8), 182 DEF_DDIV("ca55_0_coreclk3", R9A09G057_CA55_0_CORE_CLK3, CLK_PLLCA55, 183 CDDIV1_DIVCTL3, dtable_1_8), 184 DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), 185 DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1), 186 DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1), 187 DEF_FIXED("gbeth_0_clk_ptp_ref_i", R9A09G057_GBETH_0_CLK_PTP_REF_I, 188 CLK_PLLETH_DIV_125_FIX, 1, 1), 189 DEF_FIXED("gbeth_1_clk_ptp_ref_i", R9A09G057_GBETH_1_CLK_PTP_REF_I, 190 CLK_PLLETH_DIV_125_FIX, 1, 1), 191 DEF_FIXED_MOD_STATUS("spi_clk_spi", R9A09G057_SPI_CLK_SPI, CLK_PLLCM33_XSPI, 1, 2, 192 FIXED_MOD_CONF_XSPI), 193 }; 194 195 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 196 DEF_MOD("dmac_0_aclk", CLK_PLLCM33_GEAR, 0, 0, 0, 0, 197 BUS_MSTOP(5, BIT(9))), 198 DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1, 199 BUS_MSTOP(3, BIT(2))), 200 DEF_MOD("dmac_2_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2, 201 BUS_MSTOP(3, BIT(3))), 202 DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3, 203 BUS_MSTOP(10, BIT(11))), 204 DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4, 205 BUS_MSTOP(10, BIT(12))), 206 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, 207 BUS_MSTOP_NONE), 208 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, 209 BUS_MSTOP(3, BIT(5))), 210 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, 211 BUS_MSTOP(5, BIT(10))), 212 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, 213 BUS_MSTOP(5, BIT(11))), 214 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5, 215 BUS_MSTOP(2, BIT(13))), 216 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6, 217 BUS_MSTOP(2, BIT(14))), 218 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7, 219 BUS_MSTOP(11, BIT(13))), 220 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8, 221 BUS_MSTOP(11, BIT(14))), 222 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9, 223 BUS_MSTOP(11, BIT(15))), 224 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, 225 BUS_MSTOP(12, BIT(0))), 226 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11, 227 BUS_MSTOP(3, BIT(10))), 228 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12, 229 BUS_MSTOP(3, BIT(10))), 230 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, 231 BUS_MSTOP(1, BIT(0))), 232 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, 233 BUS_MSTOP(1, BIT(0))), 234 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, 235 BUS_MSTOP(5, BIT(12))), 236 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, 237 BUS_MSTOP(5, BIT(12))), 238 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, 239 BUS_MSTOP(5, BIT(13))), 240 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, 241 BUS_MSTOP(5, BIT(13))), 242 DEF_MOD("rspi_0_pclk", CLK_PLLCLN_DIV8, 5, 4, 2, 20, 243 BUS_MSTOP(11, BIT(0))), 244 DEF_MOD("rspi_0_pclk_sfr", CLK_PLLCLN_DIV8, 5, 5, 2, 21, 245 BUS_MSTOP(11, BIT(0))), 246 DEF_MOD("rspi_0_tclk", CLK_PLLCLN_DIV8, 5, 6, 2, 22, 247 BUS_MSTOP(11, BIT(0))), 248 DEF_MOD("rspi_1_pclk", CLK_PLLCLN_DIV8, 5, 7, 2, 23, 249 BUS_MSTOP(11, BIT(1))), 250 DEF_MOD("rspi_1_pclk_sfr", CLK_PLLCLN_DIV8, 5, 8, 2, 24, 251 BUS_MSTOP(11, BIT(1))), 252 DEF_MOD("rspi_1_tclk", CLK_PLLCLN_DIV8, 5, 9, 2, 25, 253 BUS_MSTOP(11, BIT(1))), 254 DEF_MOD("rspi_2_pclk", CLK_PLLCLN_DIV8, 5, 10, 2, 26, 255 BUS_MSTOP(11, BIT(2))), 256 DEF_MOD("rspi_2_pclk_sfr", CLK_PLLCLN_DIV8, 5, 11, 2, 27, 257 BUS_MSTOP(11, BIT(2))), 258 DEF_MOD("rspi_2_tclk", CLK_PLLCLN_DIV8, 5, 12, 2, 28, 259 BUS_MSTOP(11, BIT(2))), 260 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 261 BUS_MSTOP(3, BIT(14))), 262 DEF_MOD("i3c_0_pclkrw", CLK_PLLCLN_DIV16, 9, 0, 4, 16, 263 BUS_MSTOP(10, BIT(15))), 264 DEF_MOD("i3c_0_pclk", CLK_PLLCLN_DIV16, 9, 1, 4, 17, 265 BUS_MSTOP(10, BIT(15))), 266 DEF_MOD("i3c_0_tclk", CLK_PLLCLN_DIV8, 9, 2, 4, 18, 267 BUS_MSTOP(10, BIT(15))), 268 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, 269 BUS_MSTOP(3, BIT(13))), 270 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, 271 BUS_MSTOP(1, BIT(1))), 272 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, 273 BUS_MSTOP(1, BIT(2))), 274 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, 275 BUS_MSTOP(1, BIT(3))), 276 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, 277 BUS_MSTOP(1, BIT(4))), 278 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, 279 BUS_MSTOP(1, BIT(5))), 280 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, 281 BUS_MSTOP(1, BIT(6))), 282 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, 283 BUS_MSTOP(1, BIT(7))), 284 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, 285 BUS_MSTOP(1, BIT(8))), 286 DEF_MOD("spi_hclk", CLK_PLLCM33_GEAR, 9, 15, 4, 31, 287 BUS_MSTOP(4, BIT(5))), 288 DEF_MOD("spi_aclk", CLK_PLLCM33_GEAR, 10, 0, 5, 0, 289 BUS_MSTOP(4, BIT(5))), 290 DEF_MOD("spi_clk_spix2", CLK_PLLCM33_XSPI, 10, 1, 5, 2, 291 BUS_MSTOP(4, BIT(5))), 292 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, 293 BUS_MSTOP(8, BIT(2))), 294 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, 295 BUS_MSTOP(8, BIT(2))), 296 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, 297 BUS_MSTOP(8, BIT(2))), 298 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, 299 BUS_MSTOP(8, BIT(2))), 300 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, 301 BUS_MSTOP(8, BIT(3))), 302 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, 303 BUS_MSTOP(8, BIT(3))), 304 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, 305 BUS_MSTOP(8, BIT(3))), 306 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, 307 BUS_MSTOP(8, BIT(3))), 308 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, 309 BUS_MSTOP(8, BIT(4))), 310 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, 311 BUS_MSTOP(8, BIT(4))), 312 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, 313 BUS_MSTOP(8, BIT(4))), 314 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, 315 BUS_MSTOP(8, BIT(4))), 316 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19, 317 BUS_MSTOP(7, BIT(7))), 318 DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20, 319 BUS_MSTOP(7, BIT(8))), 320 DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21, 321 BUS_MSTOP(7, BIT(9))), 322 DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22, 323 BUS_MSTOP(7, BIT(10))), 324 DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23, 325 BUS_MSTOP(7, BIT(11))), 326 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_i", CLK_SMUX2_GBE0_TXCLK, 11, 8, 5, 24, 327 BUS_MSTOP(8, BIT(5)), 1), 328 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_i", CLK_SMUX2_GBE0_RXCLK, 11, 9, 5, 25, 329 BUS_MSTOP(8, BIT(5)), 1), 330 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_tx_180_i", CLK_SMUX2_GBE0_TXCLK, 11, 10, 5, 26, 331 BUS_MSTOP(8, BIT(5)), 1), 332 DEF_MOD_MUX_EXTERNAL("gbeth_0_clk_rx_180_i", CLK_SMUX2_GBE0_RXCLK, 11, 11, 5, 27, 333 BUS_MSTOP(8, BIT(5)), 1), 334 DEF_MOD("gbeth_0_aclk_csr_i", CLK_PLLDTY_DIV8, 11, 12, 5, 28, 335 BUS_MSTOP(8, BIT(5))), 336 DEF_MOD("gbeth_0_aclk_i", CLK_PLLDTY_DIV8, 11, 13, 5, 29, 337 BUS_MSTOP(8, BIT(5))), 338 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_i", CLK_SMUX2_GBE1_TXCLK, 11, 14, 5, 30, 339 BUS_MSTOP(8, BIT(6)), 1), 340 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_i", CLK_SMUX2_GBE1_RXCLK, 11, 15, 5, 31, 341 BUS_MSTOP(8, BIT(6)), 1), 342 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_tx_180_i", CLK_SMUX2_GBE1_TXCLK, 12, 0, 6, 0, 343 BUS_MSTOP(8, BIT(6)), 1), 344 DEF_MOD_MUX_EXTERNAL("gbeth_1_clk_rx_180_i", CLK_SMUX2_GBE1_RXCLK, 12, 1, 6, 1, 345 BUS_MSTOP(8, BIT(6)), 1), 346 DEF_MOD("gbeth_1_aclk_csr_i", CLK_PLLDTY_DIV8, 12, 2, 6, 2, 347 BUS_MSTOP(8, BIT(6))), 348 DEF_MOD("gbeth_1_aclk_i", CLK_PLLDTY_DIV8, 12, 3, 6, 3, 349 BUS_MSTOP(8, BIT(6))), 350 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, 351 BUS_MSTOP(9, BIT(4))), 352 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, 353 BUS_MSTOP(9, BIT(4))), 354 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20, 355 BUS_MSTOP(9, BIT(4))), 356 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21, 357 BUS_MSTOP(9, BIT(5))), 358 DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22, 359 BUS_MSTOP(9, BIT(5))), 360 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23, 361 BUS_MSTOP(9, BIT(5))), 362 DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24, 363 BUS_MSTOP(9, BIT(6))), 364 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25, 365 BUS_MSTOP(9, BIT(6))), 366 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26, 367 BUS_MSTOP(9, BIT(6))), 368 DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27, 369 BUS_MSTOP(9, BIT(7))), 370 DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28, 371 BUS_MSTOP(9, BIT(7))), 372 DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29, 373 BUS_MSTOP(9, BIT(7))), 374 DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16, 375 BUS_MSTOP(3, BIT(4))), 376 DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17, 377 BUS_MSTOP(3, BIT(4))), 378 DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, 379 BUS_MSTOP(3, BIT(4))), 380 }; 381 382 static const struct rzv2h_reset r9a09g057_resets[] __initconst = { 383 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ 384 DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */ 385 DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */ 386 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */ 387 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */ 388 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */ 389 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ 390 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ 391 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ 392 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ 393 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */ 394 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */ 395 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */ 396 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */ 397 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */ 398 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */ 399 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */ 400 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */ 401 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ 402 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */ 403 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */ 404 DEF_RST(7, 11, 3, 12), /* RSPI_0_PRESETN */ 405 DEF_RST(7, 12, 3, 13), /* RSPI_0_TRESETN */ 406 DEF_RST(7, 13, 3, 14), /* RSPI_1_PRESETN */ 407 DEF_RST(7, 14, 3, 15), /* RSPI_1_TRESETN */ 408 DEF_RST(7, 15, 3, 16), /* RSPI_2_PRESETN */ 409 DEF_RST(8, 0, 3, 17), /* RSPI_2_TRESETN */ 410 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 411 DEF_RST(9, 6, 4, 7), /* I3C_0_PRESETN */ 412 DEF_RST(9, 7, 4, 8), /* I3C_0_TRESETN */ 413 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ 414 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ 415 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */ 416 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */ 417 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */ 418 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */ 419 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */ 420 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */ 421 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ 422 DEF_RST(10, 3, 4, 20), /* SPI_HRESETN */ 423 DEF_RST(10, 4, 4, 21), /* SPI_ARESETN */ 424 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ 425 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ 426 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ 427 DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */ 428 DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */ 429 DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */ 430 DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */ 431 DEF_RST(11, 0, 5, 1), /* GBETH_0_ARESETN_I */ 432 DEF_RST(11, 1, 5, 2), /* GBETH_1_ARESETN_I */ 433 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ 434 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ 435 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ 436 DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */ 437 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */ 438 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */ 439 DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */ 440 DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */ 441 DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */ 442 DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */ 443 DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */ 444 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */ 445 DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */ 446 DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */ 447 DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */ 448 }; 449 450 const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = { 451 /* Core Clocks */ 452 .core_clks = r9a09g057_core_clks, 453 .num_core_clks = ARRAY_SIZE(r9a09g057_core_clks), 454 .last_dt_core_clk = LAST_DT_CORE_CLK, 455 .num_total_core_clks = MOD_CLK_BASE, 456 457 /* Module Clocks */ 458 .mod_clks = r9a09g057_mod_clks, 459 .num_mod_clks = ARRAY_SIZE(r9a09g057_mod_clks), 460 .num_hw_mod_clks = 25 * 16, 461 462 /* Resets */ 463 .resets = r9a09g057_resets, 464 .num_resets = ARRAY_SIZE(r9a09g057_resets), 465 466 .num_mstop_bits = 192, 467 }; 468