1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Renesas RZ/V2H(P) CPG driver 4 * 5 * Copyright (C) 2024 Renesas Electronics Corp. 6 */ 7 8 #include <linux/clk-provider.h> 9 #include <linux/device.h> 10 #include <linux/init.h> 11 #include <linux/kernel.h> 12 13 #include <dt-bindings/clock/renesas,r9a09g057-cpg.h> 14 15 #include "rzv2h-cpg.h" 16 17 enum clk_ids { 18 /* Core Clock Outputs exported to DT */ 19 LAST_DT_CORE_CLK = R9A09G057_GBETH_1_CLK_PTP_REF_I, 20 21 /* External Input Clocks */ 22 CLK_AUDIO_EXTAL, 23 CLK_RTXIN, 24 CLK_QEXTAL, 25 26 /* PLL Clocks */ 27 CLK_PLLCM33, 28 CLK_PLLCLN, 29 CLK_PLLDTY, 30 CLK_PLLCA55, 31 CLK_PLLVDO, 32 CLK_PLLGPU, 33 34 /* Internal Core Clocks */ 35 CLK_PLLCM33_DIV4, 36 CLK_PLLCM33_DIV4_PLLCM33, 37 CLK_PLLCM33_DIV16, 38 CLK_PLLCLN_DIV2, 39 CLK_PLLCLN_DIV8, 40 CLK_PLLCLN_DIV16, 41 CLK_PLLDTY_ACPU, 42 CLK_PLLDTY_ACPU_DIV2, 43 CLK_PLLDTY_ACPU_DIV4, 44 CLK_PLLDTY_DIV8, 45 CLK_PLLDTY_DIV16, 46 CLK_PLLDTY_RCPU, 47 CLK_PLLDTY_RCPU_DIV4, 48 CLK_PLLVDO_CRU0, 49 CLK_PLLVDO_CRU1, 50 CLK_PLLVDO_CRU2, 51 CLK_PLLVDO_CRU3, 52 CLK_PLLGPU_GEAR, 53 54 /* Module Clocks */ 55 MOD_CLK_BASE, 56 }; 57 58 static const struct clk_div_table dtable_1_8[] = { 59 {0, 1}, 60 {1, 2}, 61 {2, 4}, 62 {3, 8}, 63 {0, 0}, 64 }; 65 66 static const struct clk_div_table dtable_2_4[] = { 67 {0, 2}, 68 {1, 4}, 69 {0, 0}, 70 }; 71 72 static const struct clk_div_table dtable_2_64[] = { 73 {0, 2}, 74 {1, 4}, 75 {2, 8}, 76 {3, 16}, 77 {4, 64}, 78 {0, 0}, 79 }; 80 81 static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { 82 /* External Clock Inputs */ 83 DEF_INPUT("audio_extal", CLK_AUDIO_EXTAL), 84 DEF_INPUT("rtxin", CLK_RTXIN), 85 DEF_INPUT("qextal", CLK_QEXTAL), 86 87 /* PLL Clocks */ 88 DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), 89 DEF_FIXED(".pllcln", CLK_PLLCLN, CLK_QEXTAL, 200, 3), 90 DEF_FIXED(".plldty", CLK_PLLDTY, CLK_QEXTAL, 200, 3), 91 DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), 92 DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), 93 DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU), 94 95 /* Internal Core Clocks */ 96 DEF_FIXED(".pllcm33_div4", CLK_PLLCM33_DIV4, CLK_PLLCM33, 1, 4), 97 DEF_DDIV(".pllcm33_div4_pllcm33", CLK_PLLCM33_DIV4_PLLCM33, 98 CLK_PLLCM33_DIV4, CDDIV0_DIVCTL1, dtable_2_64), 99 DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), 100 101 DEF_FIXED(".pllcln_div2", CLK_PLLCLN_DIV2, CLK_PLLCLN, 1, 2), 102 DEF_FIXED(".pllcln_div8", CLK_PLLCLN_DIV8, CLK_PLLCLN, 1, 8), 103 DEF_FIXED(".pllcln_div16", CLK_PLLCLN_DIV16, CLK_PLLCLN, 1, 16), 104 105 DEF_DDIV(".plldty_acpu", CLK_PLLDTY_ACPU, CLK_PLLDTY, CDDIV0_DIVCTL2, dtable_2_64), 106 DEF_FIXED(".plldty_acpu_div2", CLK_PLLDTY_ACPU_DIV2, CLK_PLLDTY_ACPU, 1, 2), 107 DEF_FIXED(".plldty_acpu_div4", CLK_PLLDTY_ACPU_DIV4, CLK_PLLDTY_ACPU, 1, 4), 108 DEF_FIXED(".plldty_div8", CLK_PLLDTY_DIV8, CLK_PLLDTY, 1, 8), 109 DEF_FIXED(".plldty_div16", CLK_PLLDTY_DIV16, CLK_PLLDTY, 1, 16), 110 DEF_DDIV(".plldty_rcpu", CLK_PLLDTY_RCPU, CLK_PLLDTY, CDDIV3_DIVCTL2, dtable_2_64), 111 DEF_FIXED(".plldty_rcpu_div4", CLK_PLLDTY_RCPU_DIV4, CLK_PLLDTY_RCPU, 1, 4), 112 113 DEF_DDIV(".pllvdo_cru0", CLK_PLLVDO_CRU0, CLK_PLLVDO, CDDIV3_DIVCTL3, dtable_2_4), 114 DEF_DDIV(".pllvdo_cru1", CLK_PLLVDO_CRU1, CLK_PLLVDO, CDDIV4_DIVCTL0, dtable_2_4), 115 DEF_DDIV(".pllvdo_cru2", CLK_PLLVDO_CRU2, CLK_PLLVDO, CDDIV4_DIVCTL1, dtable_2_4), 116 DEF_DDIV(".pllvdo_cru3", CLK_PLLVDO_CRU3, CLK_PLLVDO, CDDIV4_DIVCTL2, dtable_2_4), 117 118 DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dtable_2_64), 119 120 /* Core Clocks */ 121 DEF_FIXED("sys_0_pclk", R9A09G057_SYS_0_PCLK, CLK_QEXTAL, 1, 1), 122 DEF_DDIV("ca55_0_coreclk0", R9A09G057_CA55_0_CORE_CLK0, CLK_PLLCA55, 123 CDDIV1_DIVCTL0, dtable_1_8), 124 DEF_DDIV("ca55_0_coreclk1", R9A09G057_CA55_0_CORE_CLK1, CLK_PLLCA55, 125 CDDIV1_DIVCTL1, dtable_1_8), 126 DEF_DDIV("ca55_0_coreclk2", R9A09G057_CA55_0_CORE_CLK2, CLK_PLLCA55, 127 CDDIV1_DIVCTL2, dtable_1_8), 128 DEF_DDIV("ca55_0_coreclk3", R9A09G057_CA55_0_CORE_CLK3, CLK_PLLCA55, 129 CDDIV1_DIVCTL3, dtable_1_8), 130 DEF_FIXED("iotop_0_shclk", R9A09G057_IOTOP_0_SHCLK, CLK_PLLCM33_DIV16, 1, 1), 131 DEF_FIXED("usb2_0_clk_core0", R9A09G057_USB2_0_CLK_CORE0, CLK_QEXTAL, 1, 1), 132 DEF_FIXED("usb2_0_clk_core1", R9A09G057_USB2_0_CLK_CORE1, CLK_QEXTAL, 1, 1), 133 }; 134 135 static const struct rzv2h_mod_clk r9a09g057_mod_clks[] __initconst = { 136 DEF_MOD("dmac_0_aclk", CLK_PLLCM33_DIV4_PLLCM33, 0, 0, 0, 0, 137 BUS_MSTOP(5, BIT(9))), 138 DEF_MOD("dmac_1_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 1, 0, 1, 139 BUS_MSTOP(3, BIT(2))), 140 DEF_MOD("dmac_2_aclk", CLK_PLLDTY_ACPU_DIV2, 0, 2, 0, 2, 141 BUS_MSTOP(3, BIT(3))), 142 DEF_MOD("dmac_3_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 3, 0, 3, 143 BUS_MSTOP(10, BIT(11))), 144 DEF_MOD("dmac_4_aclk", CLK_PLLDTY_RCPU_DIV4, 0, 4, 0, 4, 145 BUS_MSTOP(10, BIT(12))), 146 DEF_MOD_CRITICAL("icu_0_pclk_i", CLK_PLLCM33_DIV16, 0, 5, 0, 5, 147 BUS_MSTOP_NONE), 148 DEF_MOD_CRITICAL("gic_0_gicclk", CLK_PLLDTY_ACPU_DIV4, 1, 3, 0, 19, 149 BUS_MSTOP(3, BIT(5))), 150 DEF_MOD("gtm_0_pclk", CLK_PLLCM33_DIV16, 4, 3, 2, 3, 151 BUS_MSTOP(5, BIT(10))), 152 DEF_MOD("gtm_1_pclk", CLK_PLLCM33_DIV16, 4, 4, 2, 4, 153 BUS_MSTOP(5, BIT(11))), 154 DEF_MOD("gtm_2_pclk", CLK_PLLCLN_DIV16, 4, 5, 2, 5, 155 BUS_MSTOP(2, BIT(13))), 156 DEF_MOD("gtm_3_pclk", CLK_PLLCLN_DIV16, 4, 6, 2, 6, 157 BUS_MSTOP(2, BIT(14))), 158 DEF_MOD("gtm_4_pclk", CLK_PLLCLN_DIV16, 4, 7, 2, 7, 159 BUS_MSTOP(11, BIT(13))), 160 DEF_MOD("gtm_5_pclk", CLK_PLLCLN_DIV16, 4, 8, 2, 8, 161 BUS_MSTOP(11, BIT(14))), 162 DEF_MOD("gtm_6_pclk", CLK_PLLCLN_DIV16, 4, 9, 2, 9, 163 BUS_MSTOP(11, BIT(15))), 164 DEF_MOD("gtm_7_pclk", CLK_PLLCLN_DIV16, 4, 10, 2, 10, 165 BUS_MSTOP(12, BIT(0))), 166 DEF_MOD("wdt_0_clkp", CLK_PLLCM33_DIV16, 4, 11, 2, 11, 167 BUS_MSTOP(3, BIT(10))), 168 DEF_MOD("wdt_0_clk_loco", CLK_QEXTAL, 4, 12, 2, 12, 169 BUS_MSTOP(3, BIT(10))), 170 DEF_MOD("wdt_1_clkp", CLK_PLLCLN_DIV16, 4, 13, 2, 13, 171 BUS_MSTOP(1, BIT(0))), 172 DEF_MOD("wdt_1_clk_loco", CLK_QEXTAL, 4, 14, 2, 14, 173 BUS_MSTOP(1, BIT(0))), 174 DEF_MOD("wdt_2_clkp", CLK_PLLCLN_DIV16, 4, 15, 2, 15, 175 BUS_MSTOP(5, BIT(12))), 176 DEF_MOD("wdt_2_clk_loco", CLK_QEXTAL, 5, 0, 2, 16, 177 BUS_MSTOP(5, BIT(12))), 178 DEF_MOD("wdt_3_clkp", CLK_PLLCLN_DIV16, 5, 1, 2, 17, 179 BUS_MSTOP(5, BIT(13))), 180 DEF_MOD("wdt_3_clk_loco", CLK_QEXTAL, 5, 2, 2, 18, 181 BUS_MSTOP(5, BIT(13))), 182 DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15, 183 BUS_MSTOP(3, BIT(14))), 184 DEF_MOD("riic_8_ckm", CLK_PLLCM33_DIV16, 9, 3, 4, 19, 185 BUS_MSTOP(3, BIT(13))), 186 DEF_MOD("riic_0_ckm", CLK_PLLCLN_DIV16, 9, 4, 4, 20, 187 BUS_MSTOP(1, BIT(1))), 188 DEF_MOD("riic_1_ckm", CLK_PLLCLN_DIV16, 9, 5, 4, 21, 189 BUS_MSTOP(1, BIT(2))), 190 DEF_MOD("riic_2_ckm", CLK_PLLCLN_DIV16, 9, 6, 4, 22, 191 BUS_MSTOP(1, BIT(3))), 192 DEF_MOD("riic_3_ckm", CLK_PLLCLN_DIV16, 9, 7, 4, 23, 193 BUS_MSTOP(1, BIT(4))), 194 DEF_MOD("riic_4_ckm", CLK_PLLCLN_DIV16, 9, 8, 4, 24, 195 BUS_MSTOP(1, BIT(5))), 196 DEF_MOD("riic_5_ckm", CLK_PLLCLN_DIV16, 9, 9, 4, 25, 197 BUS_MSTOP(1, BIT(6))), 198 DEF_MOD("riic_6_ckm", CLK_PLLCLN_DIV16, 9, 10, 4, 26, 199 BUS_MSTOP(1, BIT(7))), 200 DEF_MOD("riic_7_ckm", CLK_PLLCLN_DIV16, 9, 11, 4, 27, 201 BUS_MSTOP(1, BIT(8))), 202 DEF_MOD("sdhi_0_imclk", CLK_PLLCLN_DIV8, 10, 3, 5, 3, 203 BUS_MSTOP(8, BIT(2))), 204 DEF_MOD("sdhi_0_imclk2", CLK_PLLCLN_DIV8, 10, 4, 5, 4, 205 BUS_MSTOP(8, BIT(2))), 206 DEF_MOD("sdhi_0_clk_hs", CLK_PLLCLN_DIV2, 10, 5, 5, 5, 207 BUS_MSTOP(8, BIT(2))), 208 DEF_MOD("sdhi_0_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 6, 5, 6, 209 BUS_MSTOP(8, BIT(2))), 210 DEF_MOD("sdhi_1_imclk", CLK_PLLCLN_DIV8, 10, 7, 5, 7, 211 BUS_MSTOP(8, BIT(3))), 212 DEF_MOD("sdhi_1_imclk2", CLK_PLLCLN_DIV8, 10, 8, 5, 8, 213 BUS_MSTOP(8, BIT(3))), 214 DEF_MOD("sdhi_1_clk_hs", CLK_PLLCLN_DIV2, 10, 9, 5, 9, 215 BUS_MSTOP(8, BIT(3))), 216 DEF_MOD("sdhi_1_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 10, 5, 10, 217 BUS_MSTOP(8, BIT(3))), 218 DEF_MOD("sdhi_2_imclk", CLK_PLLCLN_DIV8, 10, 11, 5, 11, 219 BUS_MSTOP(8, BIT(4))), 220 DEF_MOD("sdhi_2_imclk2", CLK_PLLCLN_DIV8, 10, 12, 5, 12, 221 BUS_MSTOP(8, BIT(4))), 222 DEF_MOD("sdhi_2_clk_hs", CLK_PLLCLN_DIV2, 10, 13, 5, 13, 223 BUS_MSTOP(8, BIT(4))), 224 DEF_MOD("sdhi_2_aclk", CLK_PLLDTY_ACPU_DIV4, 10, 14, 5, 14, 225 BUS_MSTOP(8, BIT(4))), 226 DEF_MOD("usb2_0_u2h0_hclk", CLK_PLLDTY_DIV8, 11, 3, 5, 19, 227 BUS_MSTOP(7, BIT(7))), 228 DEF_MOD("usb2_0_u2h1_hclk", CLK_PLLDTY_DIV8, 11, 4, 5, 20, 229 BUS_MSTOP(7, BIT(8))), 230 DEF_MOD("usb2_0_u2p_exr_cpuclk", CLK_PLLDTY_ACPU_DIV4, 11, 5, 5, 21, 231 BUS_MSTOP(7, BIT(9))), 232 DEF_MOD("usb2_0_pclk_usbtst0", CLK_PLLDTY_ACPU_DIV4, 11, 6, 5, 22, 233 BUS_MSTOP(7, BIT(10))), 234 DEF_MOD("usb2_0_pclk_usbtst1", CLK_PLLDTY_ACPU_DIV4, 11, 7, 5, 23, 235 BUS_MSTOP(7, BIT(11))), 236 DEF_MOD("cru_0_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 2, 6, 18, 237 BUS_MSTOP(9, BIT(4))), 238 DEF_MOD_NO_PM("cru_0_vclk", CLK_PLLVDO_CRU0, 13, 3, 6, 19, 239 BUS_MSTOP(9, BIT(4))), 240 DEF_MOD("cru_0_pclk", CLK_PLLDTY_DIV16, 13, 4, 6, 20, 241 BUS_MSTOP(9, BIT(4))), 242 DEF_MOD("cru_1_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 5, 6, 21, 243 BUS_MSTOP(9, BIT(5))), 244 DEF_MOD_NO_PM("cru_1_vclk", CLK_PLLVDO_CRU1, 13, 6, 6, 22, 245 BUS_MSTOP(9, BIT(5))), 246 DEF_MOD("cru_1_pclk", CLK_PLLDTY_DIV16, 13, 7, 6, 23, 247 BUS_MSTOP(9, BIT(5))), 248 DEF_MOD("cru_2_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 8, 6, 24, 249 BUS_MSTOP(9, BIT(6))), 250 DEF_MOD_NO_PM("cru_2_vclk", CLK_PLLVDO_CRU2, 13, 9, 6, 25, 251 BUS_MSTOP(9, BIT(6))), 252 DEF_MOD("cru_2_pclk", CLK_PLLDTY_DIV16, 13, 10, 6, 26, 253 BUS_MSTOP(9, BIT(6))), 254 DEF_MOD("cru_3_aclk", CLK_PLLDTY_ACPU_DIV2, 13, 11, 6, 27, 255 BUS_MSTOP(9, BIT(7))), 256 DEF_MOD_NO_PM("cru_3_vclk", CLK_PLLVDO_CRU3, 13, 12, 6, 28, 257 BUS_MSTOP(9, BIT(7))), 258 DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29, 259 BUS_MSTOP(9, BIT(7))), 260 DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16, 261 BUS_MSTOP(3, BIT(4))), 262 DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17, 263 BUS_MSTOP(3, BIT(4))), 264 DEF_MOD("gpu_0_ace_clk", CLK_PLLDTY_ACPU_DIV2, 15, 2, 7, 18, 265 BUS_MSTOP(3, BIT(4))), 266 }; 267 268 static const struct rzv2h_reset r9a09g057_resets[] __initconst = { 269 DEF_RST(3, 0, 1, 1), /* SYS_0_PRESETN */ 270 DEF_RST(3, 1, 1, 2), /* DMAC_0_ARESETN */ 271 DEF_RST(3, 2, 1, 3), /* DMAC_1_ARESETN */ 272 DEF_RST(3, 3, 1, 4), /* DMAC_2_ARESETN */ 273 DEF_RST(3, 4, 1, 5), /* DMAC_3_ARESETN */ 274 DEF_RST(3, 5, 1, 6), /* DMAC_4_ARESETN */ 275 DEF_RST(3, 6, 1, 7), /* ICU_0_PRESETN_I */ 276 DEF_RST(3, 8, 1, 9), /* GIC_0_GICRESET_N */ 277 DEF_RST(3, 9, 1, 10), /* GIC_0_DBG_GICRESET_N */ 278 DEF_RST(6, 13, 2, 30), /* GTM_0_PRESETZ */ 279 DEF_RST(6, 14, 2, 31), /* GTM_1_PRESETZ */ 280 DEF_RST(6, 15, 3, 0), /* GTM_2_PRESETZ */ 281 DEF_RST(7, 0, 3, 1), /* GTM_3_PRESETZ */ 282 DEF_RST(7, 1, 3, 2), /* GTM_4_PRESETZ */ 283 DEF_RST(7, 2, 3, 3), /* GTM_5_PRESETZ */ 284 DEF_RST(7, 3, 3, 4), /* GTM_6_PRESETZ */ 285 DEF_RST(7, 4, 3, 5), /* GTM_7_PRESETZ */ 286 DEF_RST(7, 5, 3, 6), /* WDT_0_RESET */ 287 DEF_RST(7, 6, 3, 7), /* WDT_1_RESET */ 288 DEF_RST(7, 7, 3, 8), /* WDT_2_RESET */ 289 DEF_RST(7, 8, 3, 9), /* WDT_3_RESET */ 290 DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ 291 DEF_RST(9, 8, 4, 9), /* RIIC_0_MRST */ 292 DEF_RST(9, 9, 4, 10), /* RIIC_1_MRST */ 293 DEF_RST(9, 10, 4, 11), /* RIIC_2_MRST */ 294 DEF_RST(9, 11, 4, 12), /* RIIC_3_MRST */ 295 DEF_RST(9, 12, 4, 13), /* RIIC_4_MRST */ 296 DEF_RST(9, 13, 4, 14), /* RIIC_5_MRST */ 297 DEF_RST(9, 14, 4, 15), /* RIIC_6_MRST */ 298 DEF_RST(9, 15, 4, 16), /* RIIC_7_MRST */ 299 DEF_RST(10, 0, 4, 17), /* RIIC_8_MRST */ 300 DEF_RST(10, 7, 4, 24), /* SDHI_0_IXRST */ 301 DEF_RST(10, 8, 4, 25), /* SDHI_1_IXRST */ 302 DEF_RST(10, 9, 4, 26), /* SDHI_2_IXRST */ 303 DEF_RST(10, 12, 4, 29), /* USB2_0_U2H0_HRESETN */ 304 DEF_RST(10, 13, 4, 30), /* USB2_0_U2H1_HRESETN */ 305 DEF_RST(10, 14, 4, 31), /* USB2_0_U2P_EXL_SYSRST */ 306 DEF_RST(10, 15, 5, 0), /* USB2_0_PRESETN */ 307 DEF_RST(12, 5, 5, 22), /* CRU_0_PRESETN */ 308 DEF_RST(12, 6, 5, 23), /* CRU_0_ARESETN */ 309 DEF_RST(12, 7, 5, 24), /* CRU_0_S_RESETN */ 310 DEF_RST(12, 8, 5, 25), /* CRU_1_PRESETN */ 311 DEF_RST(12, 9, 5, 26), /* CRU_1_ARESETN */ 312 DEF_RST(12, 10, 5, 27), /* CRU_1_S_RESETN */ 313 DEF_RST(12, 11, 5, 28), /* CRU_2_PRESETN */ 314 DEF_RST(12, 12, 5, 29), /* CRU_2_ARESETN */ 315 DEF_RST(12, 13, 5, 30), /* CRU_2_S_RESETN */ 316 DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */ 317 DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */ 318 DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */ 319 DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */ 320 DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */ 321 DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */ 322 }; 323 324 const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst = { 325 /* Core Clocks */ 326 .core_clks = r9a09g057_core_clks, 327 .num_core_clks = ARRAY_SIZE(r9a09g057_core_clks), 328 .last_dt_core_clk = LAST_DT_CORE_CLK, 329 .num_total_core_clks = MOD_CLK_BASE, 330 331 /* Module Clocks */ 332 .mod_clks = r9a09g057_mod_clks, 333 .num_mod_clks = ARRAY_SIZE(r9a09g057_mod_clks), 334 .num_hw_mod_clks = 25 * 16, 335 336 /* Resets */ 337 .resets = r9a09g057_resets, 338 .num_resets = ARRAY_SIZE(r9a09g057_resets), 339 340 .num_mstop_bits = 192, 341 }; 342