1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * r8a73a4 Core CPG Clocks
4 *
5 * Copyright (C) 2014 Ulrich Hecht
6 */
7
8 #include <linux/clk-provider.h>
9 #include <linux/clk/renesas.h>
10 #include <linux/init.h>
11 #include <linux/io.h>
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/spinlock.h>
17
18 struct r8a73a4_cpg {
19 struct clk_onecell_data data;
20 spinlock_t lock;
21 };
22
23 #define CPG_CKSCR 0xc0
24 #define CPG_FRQCRA 0x00
25 #define CPG_FRQCRB 0x04
26 #define CPG_FRQCRC 0xe0
27 #define CPG_PLL0CR 0xd8
28 #define CPG_PLL1CR 0x28
29 #define CPG_PLL2CR 0x2c
30 #define CPG_PLL2HCR 0xe4
31 #define CPG_PLL2SCR 0xf4
32
33 struct div4_clk {
34 const char *name;
35 unsigned int reg;
36 unsigned int shift;
37 };
38
39 static struct div4_clk div4_clks[] = {
40 { "i", CPG_FRQCRA, 20 },
41 { "m3", CPG_FRQCRA, 12 },
42 { "b", CPG_FRQCRA, 8 },
43 { "m1", CPG_FRQCRA, 4 },
44 { "m2", CPG_FRQCRA, 0 },
45 { "zx", CPG_FRQCRB, 12 },
46 { "zs", CPG_FRQCRB, 8 },
47 { "hp", CPG_FRQCRB, 4 },
48 { NULL, 0, 0 },
49 };
50
51 static const struct clk_div_table div4_div_table[] = {
52 { 0, 2 }, { 1, 3 }, { 2, 4 }, { 3, 6 }, { 4, 8 }, { 5, 12 },
53 { 6, 16 }, { 7, 18 }, { 8, 24 }, { 10, 36 }, { 11, 48 },
54 { 12, 10 }, { 0, 0 }
55 };
56
57 static struct clk * __init
r8a73a4_cpg_register_clock(struct device_node * np,struct r8a73a4_cpg * cpg,void __iomem * base,const char * name)58 r8a73a4_cpg_register_clock(struct device_node *np, struct r8a73a4_cpg *cpg,
59 void __iomem *base, const char *name)
60 {
61 const struct clk_div_table *table = NULL;
62 const char *parent_name;
63 unsigned int shift, reg;
64 unsigned int mult = 1;
65 unsigned int div = 1;
66
67
68 if (!strcmp(name, "main")) {
69 u32 ckscr = readl(base + CPG_CKSCR);
70
71 switch ((ckscr >> 28) & 3) {
72 case 0: /* extal1 */
73 parent_name = of_clk_get_parent_name(np, 0);
74 break;
75 case 1: /* extal1 / 2 */
76 parent_name = of_clk_get_parent_name(np, 0);
77 div = 2;
78 break;
79 case 2: /* extal2 */
80 parent_name = of_clk_get_parent_name(np, 1);
81 break;
82 case 3: /* extal2 / 2 */
83 parent_name = of_clk_get_parent_name(np, 1);
84 div = 2;
85 break;
86 }
87 } else if (!strcmp(name, "pll0")) {
88 /* PLL0/1 are configurable multiplier clocks. Register them as
89 * fixed factor clocks for now as there's no generic multiplier
90 * clock implementation and we currently have no need to change
91 * the multiplier value.
92 */
93 u32 value = readl(base + CPG_PLL0CR);
94
95 parent_name = "main";
96 mult = ((value >> 24) & 0x7f) + 1;
97 if (value & BIT(20))
98 div = 2;
99 } else if (!strcmp(name, "pll1")) {
100 u32 value = readl(base + CPG_PLL1CR);
101
102 parent_name = "main";
103 /* XXX: enable bit? */
104 mult = ((value >> 24) & 0x7f) + 1;
105 if (value & BIT(7))
106 div = 2;
107 } else if (!strncmp(name, "pll2", 4)) {
108 u32 value, cr;
109
110 switch (name[4]) {
111 case 0:
112 cr = CPG_PLL2CR;
113 break;
114 case 's':
115 cr = CPG_PLL2SCR;
116 break;
117 case 'h':
118 cr = CPG_PLL2HCR;
119 break;
120 default:
121 return ERR_PTR(-EINVAL);
122 }
123 value = readl(base + cr);
124 switch ((value >> 5) & 7) {
125 case 0:
126 parent_name = "main";
127 div = 2;
128 break;
129 case 1:
130 parent_name = "extal2";
131 div = 2;
132 break;
133 case 3:
134 parent_name = "extal2";
135 div = 4;
136 break;
137 case 4:
138 parent_name = "main";
139 break;
140 case 5:
141 parent_name = "extal2";
142 break;
143 default:
144 pr_warn("%s: unexpected parent of %s\n", __func__,
145 name);
146 return ERR_PTR(-EINVAL);
147 }
148 /* XXX: enable bit? */
149 mult = ((value >> 24) & 0x7f) + 1;
150 } else if (!strcmp(name, "z") || !strcmp(name, "z2")) {
151 u32 shift = 8;
152
153 parent_name = "pll0";
154 if (name[1] == '2') {
155 div = 2;
156 shift = 0;
157 }
158 div *= 32;
159 mult = 0x20 - ((readl(base + CPG_FRQCRC) >> shift) & 0x1f);
160 } else {
161 struct div4_clk *c;
162
163 for (c = div4_clks; c->name; c++) {
164 if (!strcmp(name, c->name))
165 break;
166 }
167 if (!c->name)
168 return ERR_PTR(-EINVAL);
169
170 parent_name = "pll1";
171 table = div4_div_table;
172 reg = c->reg;
173 shift = c->shift;
174 }
175
176 if (!table) {
177 return clk_register_fixed_factor(NULL, name, parent_name, 0,
178 mult, div);
179 } else {
180 return clk_register_divider_table(NULL, name, parent_name, 0,
181 base + reg, shift, 4, 0,
182 table, &cpg->lock);
183 }
184 }
185
r8a73a4_cpg_clocks_init(struct device_node * np)186 static void __init r8a73a4_cpg_clocks_init(struct device_node *np)
187 {
188 struct r8a73a4_cpg *cpg;
189 void __iomem *base;
190 struct clk **clks;
191 unsigned int i;
192 int num_clks;
193
194 num_clks = of_property_count_strings(np, "clock-output-names");
195 if (num_clks < 0) {
196 pr_err("%s: failed to count clocks\n", __func__);
197 return;
198 }
199
200 cpg = kzalloc(sizeof(*cpg), GFP_KERNEL);
201 clks = kcalloc(num_clks, sizeof(*clks), GFP_KERNEL);
202 if (cpg == NULL || clks == NULL) {
203 /* We're leaking memory on purpose, there's no point in cleaning
204 * up as the system won't boot anyway.
205 */
206 return;
207 }
208
209 spin_lock_init(&cpg->lock);
210
211 cpg->data.clks = clks;
212 cpg->data.clk_num = num_clks;
213
214 base = of_iomap(np, 0);
215 if (WARN_ON(base == NULL))
216 return;
217
218 for (i = 0; i < num_clks; ++i) {
219 const char *name;
220 struct clk *clk;
221
222 of_property_read_string_index(np, "clock-output-names", i,
223 &name);
224
225 clk = r8a73a4_cpg_register_clock(np, cpg, base, name);
226 if (IS_ERR(clk))
227 pr_err("%s: failed to register %pOFn %s clock (%ld)\n",
228 __func__, np, name, PTR_ERR(clk));
229 else
230 cpg->data.clks[i] = clk;
231 }
232
233 of_clk_add_provider(np, of_clk_src_onecell_get, &cpg->data);
234 }
235 CLK_OF_DECLARE(r8a73a4_cpg_clks, "renesas,r8a73a4-cpg-clocks",
236 r8a73a4_cpg_clocks_init);
237