1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/aer.h> 16 #include <linux/align.h> 17 #include <linux/bitfield.h> 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/export.h> 21 #include <linux/pci.h> 22 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */ 23 #include <linux/init.h> 24 #include <linux/delay.h> 25 #include <linux/acpi.h> 26 #include <linux/dmi.h> 27 #include <linux/ioport.h> 28 #include <linux/sched.h> 29 #include <linux/ktime.h> 30 #include <linux/mm.h> 31 #include <linux/nvme.h> 32 #include <linux/platform_data/x86/apple.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/sizes.h> 35 #include <linux/suspend.h> 36 #include <linux/switchtec.h> 37 #include "pci.h" 38 39 static bool pcie_lbms_seen(struct pci_dev *dev, u16 lnksta) 40 { 41 unsigned long count; 42 int ret; 43 44 ret = pcie_lbms_count(dev, &count); 45 if (ret < 0) 46 return lnksta & PCI_EXP_LNKSTA_LBMS; 47 48 return count > 0; 49 } 50 51 /* 52 * Retrain the link of a downstream PCIe port by hand if necessary. 53 * 54 * This is needed at least where a downstream port of the ASMedia ASM2824 55 * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304 56 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 > 57 * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched 58 * board. 59 * 60 * In such a configuration the switches are supposed to negotiate the link 61 * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link 62 * continues switching between the two speeds indefinitely and the data 63 * link layer never reaches the active state, with link training reported 64 * repeatedly active ~84% of the time. Forcing the target link speed to 65 * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to 66 * each other correctly however. And more interestingly retraining with a 67 * higher target link speed afterwards lets the two successfully negotiate 68 * 5.0GT/s. 69 * 70 * With the ASM2824 we can rely on the otherwise optional Data Link Layer 71 * Link Active status bit and in the failed link training scenario it will 72 * be off along with the Link Bandwidth Management Status indicating that 73 * hardware has changed the link speed or width in an attempt to correct 74 * unreliable link operation. For a port that has been left unconnected 75 * both bits will be clear. So use this information to detect the problem 76 * rather than polling the Link Training bit and watching out for flips or 77 * at least the active status. 78 * 79 * Since the exact nature of the problem isn't known and in principle this 80 * could trigger where an ASM2824 device is downstream rather upstream, 81 * apply this erratum workaround to any downstream ports as long as they 82 * support Link Active reporting and have the Link Control 2 register. 83 * Restrict the speed to 2.5GT/s then with the Target Link Speed field, 84 * request a retrain and check the result. 85 * 86 * If this turns out successful and we know by the Vendor:Device ID it is 87 * safe to do so, then lift the restriction, letting the devices negotiate 88 * a higher speed. Also check for a similar 2.5GT/s speed restriction the 89 * firmware may have already arranged and lift it with ports that already 90 * report their data link being up. 91 * 92 * Otherwise revert the speed to the original setting and request a retrain 93 * again to remove any residual state, ignoring the result as it's supposed 94 * to fail anyway. 95 * 96 * Return 0 if the link has been successfully retrained. Return an error 97 * if retraining was not needed or we attempted a retrain and it failed. 98 */ 99 int pcie_failed_link_retrain(struct pci_dev *dev) 100 { 101 static const struct pci_device_id ids[] = { 102 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ 103 {} 104 }; 105 u16 lnksta, lnkctl2; 106 int ret = -ENOTTY; 107 108 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || 109 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) 110 return ret; 111 112 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); 113 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 114 if (!(lnksta & PCI_EXP_LNKSTA_DLLLA) && pcie_lbms_seen(dev, lnksta)) { 115 u16 oldlnkctl2 = lnkctl2; 116 117 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); 118 119 ret = pcie_set_target_speed(dev, PCIE_SPEED_2_5GT, false); 120 if (ret) { 121 pci_info(dev, "retraining failed\n"); 122 pcie_set_target_speed(dev, PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2), 123 true); 124 return ret; 125 } 126 127 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 128 } 129 130 if ((lnksta & PCI_EXP_LNKSTA_DLLLA) && 131 (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT && 132 pci_match_id(ids, dev)) { 133 u32 lnkcap; 134 135 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); 136 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 137 ret = pcie_set_target_speed(dev, PCIE_LNKCAP_SLS2SPEED(lnkcap), false); 138 if (ret) { 139 pci_info(dev, "retraining failed\n"); 140 return ret; 141 } 142 } 143 144 return ret; 145 } 146 147 static ktime_t fixup_debug_start(struct pci_dev *dev, 148 void (*fn)(struct pci_dev *dev)) 149 { 150 if (initcall_debug) 151 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); 152 153 return ktime_get(); 154 } 155 156 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 157 void (*fn)(struct pci_dev *dev)) 158 { 159 ktime_t delta, rettime; 160 unsigned long long duration; 161 162 rettime = ktime_get(); 163 delta = ktime_sub(rettime, calltime); 164 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 165 if (initcall_debug || duration > 10000) 166 pci_info(dev, "%pS took %lld usecs\n", fn, duration); 167 } 168 169 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 170 struct pci_fixup *end) 171 { 172 ktime_t calltime; 173 174 for (; f < end; f++) 175 if ((f->class == (u32) (dev->class >> f->class_shift) || 176 f->class == (u32) PCI_ANY_ID) && 177 (f->vendor == dev->vendor || 178 f->vendor == (u16) PCI_ANY_ID) && 179 (f->device == dev->device || 180 f->device == (u16) PCI_ANY_ID)) { 181 void (*hook)(struct pci_dev *dev); 182 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 183 hook = offset_to_ptr(&f->hook_offset); 184 #else 185 hook = f->hook; 186 #endif 187 calltime = fixup_debug_start(dev, hook); 188 hook(dev); 189 fixup_debug_report(dev, calltime, hook); 190 } 191 } 192 193 extern struct pci_fixup __start_pci_fixups_early[]; 194 extern struct pci_fixup __end_pci_fixups_early[]; 195 extern struct pci_fixup __start_pci_fixups_header[]; 196 extern struct pci_fixup __end_pci_fixups_header[]; 197 extern struct pci_fixup __start_pci_fixups_final[]; 198 extern struct pci_fixup __end_pci_fixups_final[]; 199 extern struct pci_fixup __start_pci_fixups_enable[]; 200 extern struct pci_fixup __end_pci_fixups_enable[]; 201 extern struct pci_fixup __start_pci_fixups_resume[]; 202 extern struct pci_fixup __end_pci_fixups_resume[]; 203 extern struct pci_fixup __start_pci_fixups_resume_early[]; 204 extern struct pci_fixup __end_pci_fixups_resume_early[]; 205 extern struct pci_fixup __start_pci_fixups_suspend[]; 206 extern struct pci_fixup __end_pci_fixups_suspend[]; 207 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 208 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 209 210 static bool pci_apply_fixup_final_quirks; 211 212 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 213 { 214 struct pci_fixup *start, *end; 215 216 switch (pass) { 217 case pci_fixup_early: 218 start = __start_pci_fixups_early; 219 end = __end_pci_fixups_early; 220 break; 221 222 case pci_fixup_header: 223 start = __start_pci_fixups_header; 224 end = __end_pci_fixups_header; 225 break; 226 227 case pci_fixup_final: 228 if (!pci_apply_fixup_final_quirks) 229 return; 230 start = __start_pci_fixups_final; 231 end = __end_pci_fixups_final; 232 break; 233 234 case pci_fixup_enable: 235 start = __start_pci_fixups_enable; 236 end = __end_pci_fixups_enable; 237 break; 238 239 case pci_fixup_resume: 240 start = __start_pci_fixups_resume; 241 end = __end_pci_fixups_resume; 242 break; 243 244 case pci_fixup_resume_early: 245 start = __start_pci_fixups_resume_early; 246 end = __end_pci_fixups_resume_early; 247 break; 248 249 case pci_fixup_suspend: 250 start = __start_pci_fixups_suspend; 251 end = __end_pci_fixups_suspend; 252 break; 253 254 case pci_fixup_suspend_late: 255 start = __start_pci_fixups_suspend_late; 256 end = __end_pci_fixups_suspend_late; 257 break; 258 259 default: 260 /* stupid compiler warning, you would think with an enum... */ 261 return; 262 } 263 pci_do_fixups(dev, start, end); 264 } 265 EXPORT_SYMBOL(pci_fixup_device); 266 267 static int __init pci_apply_final_quirks(void) 268 { 269 struct pci_dev *dev = NULL; 270 u8 cls = 0; 271 u8 tmp; 272 273 if (pci_cache_line_size) 274 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); 275 276 pci_apply_fixup_final_quirks = true; 277 for_each_pci_dev(dev) { 278 pci_fixup_device(pci_fixup_final, dev); 279 /* 280 * If arch hasn't set it explicitly yet, use the CLS 281 * value shared by all PCI devices. If there's a 282 * mismatch, fall back to the default value. 283 */ 284 if (!pci_cache_line_size) { 285 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 286 if (!cls) 287 cls = tmp; 288 if (!tmp || cls == tmp) 289 continue; 290 291 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", 292 cls << 2, tmp << 2, 293 pci_dfl_cache_line_size << 2); 294 pci_cache_line_size = pci_dfl_cache_line_size; 295 } 296 } 297 298 if (!pci_cache_line_size) { 299 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, 300 pci_dfl_cache_line_size << 2); 301 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 302 } 303 304 return 0; 305 } 306 fs_initcall_sync(pci_apply_final_quirks); 307 308 /* 309 * Decoding should be disabled for a PCI device during BAR sizing to avoid 310 * conflict. But doing so may cause problems on host bridge and perhaps other 311 * key system devices. For devices that need to have mmio decoding always-on, 312 * we need to set the dev->mmio_always_on bit. 313 */ 314 static void quirk_mmio_always_on(struct pci_dev *dev) 315 { 316 dev->mmio_always_on = 1; 317 } 318 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 319 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 320 321 /* 322 * The Mellanox Tavor device gives false positive parity errors. Disable 323 * parity error reporting. 324 */ 325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity); 326 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity); 327 328 /* 329 * Deal with broken BIOSes that neglect to enable passive release, 330 * which can cause problems in combination with the 82441FX/PPro MTRRs 331 */ 332 static void quirk_passive_release(struct pci_dev *dev) 333 { 334 struct pci_dev *d = NULL; 335 unsigned char dlc; 336 337 /* 338 * We have to make sure a particular bit is set in the PIIX3 339 * ISA bridge, so we have to go out and find it. 340 */ 341 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 342 pci_read_config_byte(d, 0x82, &dlc); 343 if (!(dlc & 1<<1)) { 344 pci_info(d, "PIIX3: Enabling Passive Release\n"); 345 dlc |= 1<<1; 346 pci_write_config_byte(d, 0x82, dlc); 347 } 348 } 349 } 350 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 351 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 352 353 #ifdef CONFIG_X86_32 354 /* 355 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 356 * workaround but VIA don't answer queries. If you happen to have good 357 * contacts at VIA ask them for me please -- Alan 358 * 359 * This appears to be BIOS not version dependent. So presumably there is a 360 * chipset level fix. 361 */ 362 static void quirk_isa_dma_hangs(struct pci_dev *dev) 363 { 364 if (!isa_dma_bridge_buggy) { 365 isa_dma_bridge_buggy = 1; 366 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 367 } 368 } 369 /* 370 * It's not totally clear which chipsets are the problematic ones. We know 371 * 82C586 and 82C596 variants are affected. 372 */ 373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 376 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 377 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 378 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 379 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 380 #endif 381 382 #ifdef CONFIG_HAS_IOPORT 383 /* 384 * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear 385 * for some HT machines to use C4 w/o hanging. 386 */ 387 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 388 { 389 u32 pmbase; 390 u16 pm1a; 391 392 pci_read_config_dword(dev, 0x40, &pmbase); 393 pmbase = pmbase & 0xff80; 394 pm1a = inw(pmbase); 395 396 if (pm1a & 0x10) { 397 pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); 398 outw(0x10, pmbase); 399 } 400 } 401 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 402 #endif 403 404 /* Chipsets where PCI->PCI transfers vanish or hang */ 405 static void quirk_nopcipci(struct pci_dev *dev) 406 { 407 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 408 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 409 pci_pci_problems |= PCIPCI_FAIL; 410 } 411 } 412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 413 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 414 415 static void quirk_nopciamd(struct pci_dev *dev) 416 { 417 u8 rev; 418 pci_read_config_byte(dev, 0x08, &rev); 419 if (rev == 0x13) { 420 /* Erratum 24 */ 421 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 422 pci_pci_problems |= PCIAGP_FAIL; 423 } 424 } 425 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 426 427 /* Triton requires workarounds to be used by the drivers */ 428 static void quirk_triton(struct pci_dev *dev) 429 { 430 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 431 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 432 pci_pci_problems |= PCIPCI_TRITON; 433 } 434 } 435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 436 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 437 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 438 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 439 440 /* 441 * VIA Apollo KT133 needs PCI latency patch 442 * Made according to a Windows driver-based patch by George E. Breese; 443 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 444 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 445 * which Mr Breese based his work. 446 * 447 * Updated based on further information from the site and also on 448 * information provided by VIA 449 */ 450 static void quirk_vialatency(struct pci_dev *dev) 451 { 452 struct pci_dev *p; 453 u8 busarb; 454 455 /* 456 * Ok, we have a potential problem chipset here. Now see if we have 457 * a buggy southbridge. 458 */ 459 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 460 if (p != NULL) { 461 462 /* 463 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 464 * thanks Dan Hollis. 465 * Check for buggy part revisions 466 */ 467 if (p->revision < 0x40 || p->revision > 0x42) 468 goto exit; 469 } else { 470 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 471 if (p == NULL) /* No problem parts */ 472 goto exit; 473 474 /* Check for buggy part revisions */ 475 if (p->revision < 0x10 || p->revision > 0x12) 476 goto exit; 477 } 478 479 /* 480 * Ok we have the problem. Now set the PCI master grant to occur 481 * every master grant. The apparent bug is that under high PCI load 482 * (quite common in Linux of course) you can get data loss when the 483 * CPU is held off the bus for 3 bus master requests. This happens 484 * to include the IDE controllers.... 485 * 486 * VIA only apply this fix when an SB Live! is present but under 487 * both Linux and Windows this isn't enough, and we have seen 488 * corruption without SB Live! but with things like 3 UDMA IDE 489 * controllers. So we ignore that bit of the VIA recommendation.. 490 */ 491 pci_read_config_byte(dev, 0x76, &busarb); 492 493 /* 494 * Set bit 4 and bit 5 of byte 76 to 0x01 495 * "Master priority rotation on every PCI master grant" 496 */ 497 busarb &= ~(1<<5); 498 busarb |= (1<<4); 499 pci_write_config_byte(dev, 0x76, busarb); 500 pci_info(dev, "Applying VIA southbridge workaround\n"); 501 exit: 502 pci_dev_put(p); 503 } 504 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 505 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 506 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 507 /* Must restore this on a resume from RAM */ 508 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 509 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 510 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 511 512 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 513 static void quirk_viaetbf(struct pci_dev *dev) 514 { 515 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 516 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 517 pci_pci_problems |= PCIPCI_VIAETBF; 518 } 519 } 520 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 521 522 static void quirk_vsfx(struct pci_dev *dev) 523 { 524 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 525 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 526 pci_pci_problems |= PCIPCI_VSFX; 527 } 528 } 529 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 530 531 /* 532 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 533 * space. Latency must be set to 0xA and Triton workaround applied too. 534 * [Info kindly provided by ALi] 535 */ 536 static void quirk_alimagik(struct pci_dev *dev) 537 { 538 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 539 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 540 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 541 } 542 } 543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 544 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 545 546 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 547 static void quirk_natoma(struct pci_dev *dev) 548 { 549 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 550 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 551 pci_pci_problems |= PCIPCI_NATOMA; 552 } 553 } 554 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 555 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 556 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 557 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 558 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 559 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 560 561 /* 562 * This chip can cause PCI parity errors if config register 0xA0 is read 563 * while DMAs are occurring. 564 */ 565 static void quirk_citrine(struct pci_dev *dev) 566 { 567 dev->cfg_size = 0xA0; 568 } 569 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 570 571 /* 572 * This chip can cause bus lockups if config addresses above 0x600 573 * are read or written. 574 */ 575 static void quirk_nfp6000(struct pci_dev *dev) 576 { 577 dev->cfg_size = 0x600; 578 } 579 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 580 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 581 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 582 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 583 584 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 585 static void quirk_extend_bar_to_page(struct pci_dev *dev) 586 { 587 int i; 588 589 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 590 struct resource *r = &dev->resource[i]; 591 const char *r_name = pci_resource_name(dev, i); 592 593 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 594 resource_set_range(r, 0, PAGE_SIZE); 595 r->flags |= IORESOURCE_UNSET; 596 pci_info(dev, "%s %pR: expanded to page size\n", 597 r_name, r); 598 } 599 } 600 } 601 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 602 603 /* 604 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 605 * If it's needed, re-allocate the region. 606 */ 607 static void quirk_s3_64M(struct pci_dev *dev) 608 { 609 struct resource *r = &dev->resource[0]; 610 611 if (!IS_ALIGNED(r->start, SZ_64M) || resource_size(r) != SZ_64M) { 612 r->flags |= IORESOURCE_UNSET; 613 resource_set_range(r, 0, SZ_64M); 614 } 615 } 616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 617 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 618 619 static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, 620 const char *name) 621 { 622 u32 region; 623 struct pci_bus_region bus_region; 624 struct resource *res = pci_resource_n(dev, pos); 625 const char *res_name = pci_resource_name(dev, pos); 626 627 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 628 629 if (!region) 630 return; 631 632 res->name = pci_name(dev); 633 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 634 res->flags |= 635 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 636 region &= ~(size - 1); 637 638 /* Convert from PCI bus to resource space */ 639 bus_region.start = region; 640 bus_region.end = region + size - 1; 641 pcibios_bus_to_resource(dev->bus, res, &bus_region); 642 643 pci_info(dev, FW_BUG "%s %pR: %s quirk\n", res_name, res, name); 644 } 645 646 /* 647 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 648 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 649 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 650 * (which conflicts w/ BAR1's memory range). 651 * 652 * CS553x's ISA PCI BARs may also be read-only (ref: 653 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 654 */ 655 static void quirk_cs5536_vsa(struct pci_dev *dev) 656 { 657 static char *name = "CS5536 ISA bridge"; 658 659 if (pci_resource_len(dev, 0) != 8) { 660 quirk_io(dev, 0, 8, name); /* SMB */ 661 quirk_io(dev, 1, 256, name); /* GPIO */ 662 quirk_io(dev, 2, 64, name); /* MFGPT */ 663 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 664 name); 665 } 666 } 667 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 668 669 static void quirk_io_region(struct pci_dev *dev, int port, 670 unsigned int size, int nr, const char *name) 671 { 672 u16 region; 673 struct pci_bus_region bus_region; 674 struct resource *res = pci_resource_n(dev, nr); 675 676 pci_read_config_word(dev, port, ®ion); 677 region &= ~(size - 1); 678 679 if (!region) 680 return; 681 682 res->name = pci_name(dev); 683 res->flags = IORESOURCE_IO; 684 685 /* Convert from PCI bus to resource space */ 686 bus_region.start = region; 687 bus_region.end = region + size - 1; 688 pcibios_bus_to_resource(dev->bus, res, &bus_region); 689 690 /* 691 * "res" is typically a bridge window resource that's not being 692 * used for a bridge window, so it's just a place to stash this 693 * non-standard resource. Printing "nr" or pci_resource_name() of 694 * it doesn't really make sense. 695 */ 696 if (!pci_claim_resource(dev, nr)) 697 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 698 } 699 700 /* 701 * ATI Northbridge setups MCE the processor if you even read somewhere 702 * between 0x3b0->0x3bb or read 0x3d3 703 */ 704 static void quirk_ati_exploding_mce(struct pci_dev *dev) 705 { 706 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 707 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 708 request_region(0x3b0, 0x0C, "RadeonIGP"); 709 request_region(0x3d3, 0x01, "RadeonIGP"); 710 } 711 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 712 713 /* 714 * In the AMD NL platform, this device ([1022:7912]) has a class code of 715 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 716 * claim it. The same applies on the VanGogh platform device ([1022:163a]). 717 * 718 * But the dwc3 driver is a more specific driver for this device, and we'd 719 * prefer to use it instead of xhci. To prevent xhci from claiming the 720 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 721 * defines as "USB device (not host controller)". The dwc3 driver can then 722 * claim it based on its Vendor and Device ID. 723 */ 724 static void quirk_amd_dwc_class(struct pci_dev *pdev) 725 { 726 u32 class = pdev->class; 727 728 if (class != PCI_CLASS_SERIAL_USB_DEVICE) { 729 /* Use "USB Device (not host controller)" class */ 730 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 731 pci_info(pdev, 732 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 733 class, pdev->class); 734 } 735 } 736 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 737 quirk_amd_dwc_class); 738 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB, 739 quirk_amd_dwc_class); 740 741 /* 742 * Synopsys USB 3.x host HAPS platform has a class code of 743 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 744 * devices should use dwc3-haps driver. Change these devices' class code to 745 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 746 * them. 747 */ 748 static void quirk_synopsys_haps(struct pci_dev *pdev) 749 { 750 u32 class = pdev->class; 751 752 switch (pdev->device) { 753 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 754 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 755 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 756 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 757 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 758 class, pdev->class); 759 break; 760 } 761 } 762 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 763 PCI_CLASS_SERIAL_USB_XHCI, 0, 764 quirk_synopsys_haps); 765 766 /* 767 * Let's make the southbridge information explicit instead of having to 768 * worry about people probing the ACPI areas, for example.. (Yes, it 769 * happens, and if you read the wrong ACPI register it will put the machine 770 * to sleep with no way of waking it up again. Bummer). 771 * 772 * ALI M7101: Two IO regions pointed to by words at 773 * 0xE0 (64 bytes of ACPI registers) 774 * 0xE2 (32 bytes of SMB registers) 775 */ 776 static void quirk_ali7101_acpi(struct pci_dev *dev) 777 { 778 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 779 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 780 } 781 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 782 783 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 784 { 785 u32 devres; 786 u32 mask, size, base; 787 788 pci_read_config_dword(dev, port, &devres); 789 if ((devres & enable) != enable) 790 return; 791 mask = (devres >> 16) & 15; 792 base = devres & 0xffff; 793 size = 16; 794 for (;;) { 795 unsigned int bit = size >> 1; 796 if ((bit & mask) == bit) 797 break; 798 size = bit; 799 } 800 /* 801 * For now we only print it out. Eventually we'll want to 802 * reserve it (at least if it's in the 0x1000+ range), but 803 * let's get enough confirmation reports first. 804 */ 805 base &= -size; 806 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 807 } 808 809 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 810 { 811 u32 devres; 812 u32 mask, size, base; 813 814 pci_read_config_dword(dev, port, &devres); 815 if ((devres & enable) != enable) 816 return; 817 base = devres & 0xffff0000; 818 mask = (devres & 0x3f) << 16; 819 size = 128 << 16; 820 for (;;) { 821 unsigned int bit = size >> 1; 822 if ((bit & mask) == bit) 823 break; 824 size = bit; 825 } 826 827 /* 828 * For now we only print it out. Eventually we'll want to 829 * reserve it, but let's get enough confirmation reports first. 830 */ 831 base &= -size; 832 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 833 } 834 835 /* 836 * PIIX4 ACPI: Two IO regions pointed to by longwords at 837 * 0x40 (64 bytes of ACPI registers) 838 * 0x90 (16 bytes of SMB registers) 839 * and a few strange programmable PIIX4 device resources. 840 */ 841 static void quirk_piix4_acpi(struct pci_dev *dev) 842 { 843 u32 res_a; 844 845 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 846 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 847 848 /* Device resource A has enables for some of the other ones */ 849 pci_read_config_dword(dev, 0x5c, &res_a); 850 851 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 852 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 853 854 /* Device resource D is just bitfields for static resources */ 855 856 /* Device 12 enabled? */ 857 if (res_a & (1 << 29)) { 858 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 859 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 860 } 861 /* Device 13 enabled? */ 862 if (res_a & (1 << 30)) { 863 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 864 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 865 } 866 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 867 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 868 } 869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 870 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 871 872 #define ICH_PMBASE 0x40 873 #define ICH_ACPI_CNTL 0x44 874 #define ICH4_ACPI_EN 0x10 875 #define ICH6_ACPI_EN 0x80 876 #define ICH4_GPIOBASE 0x58 877 #define ICH4_GPIO_CNTL 0x5c 878 #define ICH4_GPIO_EN 0x10 879 #define ICH6_GPIOBASE 0x48 880 #define ICH6_GPIO_CNTL 0x4c 881 #define ICH6_GPIO_EN 0x10 882 883 /* 884 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 885 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 886 * 0x58 (64 bytes of GPIO I/O space) 887 */ 888 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 889 { 890 u8 enable; 891 892 /* 893 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 894 * with low legacy (and fixed) ports. We don't know the decoding 895 * priority and can't tell whether the legacy device or the one created 896 * here is really at that address. This happens on boards with broken 897 * BIOSes. 898 */ 899 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 900 if (enable & ICH4_ACPI_EN) 901 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 902 "ICH4 ACPI/GPIO/TCO"); 903 904 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 905 if (enable & ICH4_GPIO_EN) 906 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 907 "ICH4 GPIO"); 908 } 909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 915 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 918 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 919 920 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 921 { 922 u8 enable; 923 924 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 925 if (enable & ICH6_ACPI_EN) 926 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 927 "ICH6 ACPI/GPIO/TCO"); 928 929 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 930 if (enable & ICH6_GPIO_EN) 931 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 932 "ICH6 GPIO"); 933 } 934 935 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 936 const char *name, int dynsize) 937 { 938 u32 val; 939 u32 size, base; 940 941 pci_read_config_dword(dev, reg, &val); 942 943 /* Enabled? */ 944 if (!(val & 1)) 945 return; 946 base = val & 0xfffc; 947 if (dynsize) { 948 /* 949 * This is not correct. It is 16, 32 or 64 bytes depending on 950 * register D31:F0:ADh bits 5:4. 951 * 952 * But this gets us at least _part_ of it. 953 */ 954 size = 16; 955 } else { 956 size = 128; 957 } 958 base &= ~(size-1); 959 960 /* 961 * Just print it out for now. We should reserve it after more 962 * debugging. 963 */ 964 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 965 } 966 967 static void quirk_ich6_lpc(struct pci_dev *dev) 968 { 969 /* Shared ACPI/GPIO decode with all ICH6+ */ 970 ich6_lpc_acpi_gpio(dev); 971 972 /* ICH6-specific generic IO decode */ 973 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 974 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 975 } 976 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 977 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 978 979 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 980 const char *name) 981 { 982 u32 val; 983 u32 mask, base; 984 985 pci_read_config_dword(dev, reg, &val); 986 987 /* Enabled? */ 988 if (!(val & 1)) 989 return; 990 991 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 992 base = val & 0xfffc; 993 mask = (val >> 16) & 0xfc; 994 mask |= 3; 995 996 /* 997 * Just print it out for now. We should reserve it after more 998 * debugging. 999 */ 1000 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 1001 } 1002 1003 /* ICH7-10 has the same common LPC generic IO decode registers */ 1004 static void quirk_ich7_lpc(struct pci_dev *dev) 1005 { 1006 /* We share the common ACPI/GPIO decode with ICH6 */ 1007 ich6_lpc_acpi_gpio(dev); 1008 1009 /* And have 4 ICH7+ generic decodes */ 1010 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 1011 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 1012 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 1013 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 1014 } 1015 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 1016 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 1017 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 1018 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 1019 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 1020 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 1021 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 1022 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 1023 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 1024 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 1025 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 1026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 1027 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 1028 1029 /* 1030 * VIA ACPI: One IO region pointed to by longword at 1031 * 0x48 or 0x20 (256 bytes of ACPI registers) 1032 */ 1033 static void quirk_vt82c586_acpi(struct pci_dev *dev) 1034 { 1035 if (dev->revision & 0x10) 1036 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 1037 "vt82c586 ACPI"); 1038 } 1039 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 1040 1041 /* 1042 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 1043 * 0x48 (256 bytes of ACPI registers) 1044 * 0x70 (128 bytes of hardware monitoring register) 1045 * 0x90 (16 bytes of SMB registers) 1046 */ 1047 static void quirk_vt82c686_acpi(struct pci_dev *dev) 1048 { 1049 quirk_vt82c586_acpi(dev); 1050 1051 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 1052 "vt82c686 HW-mon"); 1053 1054 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 1055 } 1056 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 1057 1058 /* 1059 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 1060 * 0x88 (128 bytes of power management registers) 1061 * 0xd0 (16 bytes of SMB registers) 1062 */ 1063 static void quirk_vt8235_acpi(struct pci_dev *dev) 1064 { 1065 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 1066 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 1067 } 1068 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 1069 1070 /* 1071 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 1072 * back-to-back: Disable fast back-to-back on the secondary bus segment 1073 */ 1074 static void quirk_xio2000a(struct pci_dev *dev) 1075 { 1076 struct pci_dev *pdev; 1077 u16 command; 1078 1079 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 1080 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 1081 pci_read_config_word(pdev, PCI_COMMAND, &command); 1082 if (command & PCI_COMMAND_FAST_BACK) 1083 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 1084 } 1085 } 1086 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 1087 quirk_xio2000a); 1088 1089 #ifdef CONFIG_X86_IO_APIC 1090 1091 #include <asm/io_apic.h> 1092 1093 /* 1094 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 1095 * devices to the external APIC. 1096 * 1097 * TODO: When we have device-specific interrupt routers, this code will go 1098 * away from quirks. 1099 */ 1100 static void quirk_via_ioapic(struct pci_dev *dev) 1101 { 1102 u8 tmp; 1103 1104 if (nr_ioapics < 1) 1105 tmp = 0; /* nothing routed to external APIC */ 1106 else 1107 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 1108 1109 pci_info(dev, "%s VIA external APIC routing\n", 1110 tmp ? "Enabling" : "Disabling"); 1111 1112 /* Offset 0x58: External APIC IRQ output control */ 1113 pci_write_config_byte(dev, 0x58, tmp); 1114 } 1115 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1116 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1117 1118 /* 1119 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 1120 * This leads to doubled level interrupt rates. 1121 * Set this bit to get rid of cycle wastage. 1122 * Otherwise uncritical. 1123 */ 1124 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 1125 { 1126 u8 misc_control2; 1127 #define BYPASS_APIC_DEASSERT 8 1128 1129 pci_read_config_byte(dev, 0x5B, &misc_control2); 1130 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1131 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1132 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1133 } 1134 } 1135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1136 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1137 1138 /* 1139 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1140 * We check all revs >= B0 (yet not in the pre production!) as the bug 1141 * is currently marked NoFix 1142 * 1143 * We have multiple reports of hangs with this chipset that went away with 1144 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1145 * of course. However the advice is demonstrably good even if so. 1146 */ 1147 static void quirk_amd_ioapic(struct pci_dev *dev) 1148 { 1149 if (dev->revision >= 0x02) { 1150 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1151 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1152 } 1153 } 1154 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1155 #endif /* CONFIG_X86_IO_APIC */ 1156 1157 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1158 1159 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1160 { 1161 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1162 if (dev->subsystem_device == 0xa118) 1163 dev->sriov->link = dev->devfn; 1164 } 1165 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1166 #endif 1167 1168 /* 1169 * Some settings of MMRBC can lead to data corruption so block changes. 1170 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1171 */ 1172 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1173 { 1174 if (dev->subordinate && dev->revision <= 0x12) { 1175 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1176 dev->revision); 1177 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1178 } 1179 } 1180 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1181 1182 /* 1183 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1184 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1185 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1186 * of the ACPI SCI interrupt is only done for convenience. 1187 * -jgarzik 1188 */ 1189 static void quirk_via_acpi(struct pci_dev *d) 1190 { 1191 u8 irq; 1192 1193 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1194 pci_read_config_byte(d, 0x42, &irq); 1195 irq &= 0xf; 1196 if (irq && (irq != 2)) 1197 d->irq = irq; 1198 } 1199 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1200 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1201 1202 /* VIA bridges which have VLink */ 1203 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1204 1205 static void quirk_via_bridge(struct pci_dev *dev) 1206 { 1207 /* See what bridge we have and find the device ranges */ 1208 switch (dev->device) { 1209 case PCI_DEVICE_ID_VIA_82C686: 1210 /* 1211 * The VT82C686 is special; it attaches to PCI and can have 1212 * any device number. All its subdevices are functions of 1213 * that single device. 1214 */ 1215 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1216 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1217 break; 1218 case PCI_DEVICE_ID_VIA_8237: 1219 case PCI_DEVICE_ID_VIA_8237A: 1220 via_vlink_dev_lo = 15; 1221 break; 1222 case PCI_DEVICE_ID_VIA_8235: 1223 via_vlink_dev_lo = 16; 1224 break; 1225 case PCI_DEVICE_ID_VIA_8231: 1226 case PCI_DEVICE_ID_VIA_8233_0: 1227 case PCI_DEVICE_ID_VIA_8233A: 1228 case PCI_DEVICE_ID_VIA_8233C_0: 1229 via_vlink_dev_lo = 17; 1230 break; 1231 } 1232 } 1233 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1234 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1240 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1241 1242 /* 1243 * quirk_via_vlink - VIA VLink IRQ number update 1244 * @dev: PCI device 1245 * 1246 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1247 * the IRQ line register which usually is not relevant for PCI cards, is 1248 * actually written so that interrupts get sent to the right place. 1249 * 1250 * We only do this on systems where a VIA south bridge was detected, and 1251 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1252 */ 1253 static void quirk_via_vlink(struct pci_dev *dev) 1254 { 1255 u8 irq, new_irq; 1256 1257 /* Check if we have VLink at all */ 1258 if (via_vlink_dev_lo == -1) 1259 return; 1260 1261 new_irq = dev->irq; 1262 1263 /* Don't quirk interrupts outside the legacy IRQ range */ 1264 if (!new_irq || new_irq > 15) 1265 return; 1266 1267 /* Internal device ? */ 1268 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1269 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1270 return; 1271 1272 /* 1273 * This is an internal VLink device on a PIC interrupt. The BIOS 1274 * ought to have set this but may not have, so we redo it. 1275 */ 1276 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1277 if (new_irq != irq) { 1278 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1279 irq, new_irq); 1280 udelay(15); /* unknown if delay really needed */ 1281 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1282 } 1283 } 1284 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1285 1286 /* 1287 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1288 * of VT82C597 for backward compatibility. We need to switch it off to be 1289 * able to recognize the real type of the chip. 1290 */ 1291 static void quirk_vt82c598_id(struct pci_dev *dev) 1292 { 1293 pci_write_config_byte(dev, 0xfc, 0); 1294 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1295 } 1296 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1297 1298 /* 1299 * CardBus controllers have a legacy base address that enables them to 1300 * respond as i82365 pcmcia controllers. We don't want them to do this 1301 * even if the Linux CardBus driver is not loaded, because the Linux i82365 1302 * driver does not (and should not) handle CardBus. 1303 */ 1304 static void quirk_cardbus_legacy(struct pci_dev *dev) 1305 { 1306 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1307 } 1308 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1309 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1310 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1311 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1312 1313 /* 1314 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1315 * what the designers were smoking but let's not inhale... 1316 * 1317 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1318 * turn it off! 1319 */ 1320 static void quirk_amd_ordering(struct pci_dev *dev) 1321 { 1322 u32 pcic; 1323 pci_read_config_dword(dev, 0x4C, &pcic); 1324 if ((pcic & 6) != 6) { 1325 pcic |= 6; 1326 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1327 pci_write_config_dword(dev, 0x4C, pcic); 1328 pci_read_config_dword(dev, 0x84, &pcic); 1329 pcic |= (1 << 23); /* Required in this mode */ 1330 pci_write_config_dword(dev, 0x84, pcic); 1331 } 1332 } 1333 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1334 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1335 1336 /* 1337 * DreamWorks-provided workaround for Dunord I-3000 problem 1338 * 1339 * This card decodes and responds to addresses not apparently assigned to 1340 * it. We force a larger allocation to ensure that nothing gets put too 1341 * close to it. 1342 */ 1343 static void quirk_dunord(struct pci_dev *dev) 1344 { 1345 struct resource *r = &dev->resource[1]; 1346 1347 r->flags |= IORESOURCE_UNSET; 1348 resource_set_range(r, 0, SZ_16M); 1349 } 1350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1351 1352 /* 1353 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1354 * decoding (transparent), and does indicate this in the ProgIf. 1355 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1356 */ 1357 static void quirk_transparent_bridge(struct pci_dev *dev) 1358 { 1359 dev->transparent = 1; 1360 } 1361 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1363 1364 /* 1365 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1366 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1367 * found at http://www.national.com/analog for info on what these bits do. 1368 * <christer@weinigel.se> 1369 */ 1370 static void quirk_mediagx_master(struct pci_dev *dev) 1371 { 1372 u8 reg; 1373 1374 pci_read_config_byte(dev, 0x41, ®); 1375 if (reg & 2) { 1376 reg &= ~2; 1377 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1378 reg); 1379 pci_write_config_byte(dev, 0x41, reg); 1380 } 1381 } 1382 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1383 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1384 1385 /* 1386 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1387 * in the odd case it is not the results are corruption hence the presence 1388 * of a Linux check. 1389 */ 1390 static void quirk_disable_pxb(struct pci_dev *pdev) 1391 { 1392 u16 config; 1393 1394 if (pdev->revision != 0x04) /* Only C0 requires this */ 1395 return; 1396 pci_read_config_word(pdev, 0x40, &config); 1397 if (config & (1<<6)) { 1398 config &= ~(1<<6); 1399 pci_write_config_word(pdev, 0x40, config); 1400 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1401 } 1402 } 1403 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1404 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1405 1406 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1407 { 1408 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1409 u8 tmp; 1410 1411 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1412 if (tmp == 0x01) { 1413 pci_read_config_byte(pdev, 0x40, &tmp); 1414 pci_write_config_byte(pdev, 0x40, tmp|1); 1415 pci_write_config_byte(pdev, 0x9, 1); 1416 pci_write_config_byte(pdev, 0xa, 6); 1417 pci_write_config_byte(pdev, 0x40, tmp); 1418 1419 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1420 pci_info(pdev, "set SATA to AHCI mode\n"); 1421 } 1422 } 1423 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1424 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1425 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1426 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1427 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1428 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1429 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1430 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1431 1432 /* Serverworks CSB5 IDE does not fully support native mode */ 1433 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1434 { 1435 u8 prog; 1436 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1437 if (prog & 5) { 1438 prog &= ~5; 1439 pdev->class &= ~5; 1440 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1441 /* PCI layer will sort out resources */ 1442 } 1443 } 1444 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1445 1446 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1447 static void quirk_ide_samemode(struct pci_dev *pdev) 1448 { 1449 u8 prog; 1450 1451 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1452 1453 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1454 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1455 prog &= ~5; 1456 pdev->class &= ~5; 1457 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1458 } 1459 } 1460 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1461 1462 /* Some ATA devices break if put into D3 */ 1463 static void quirk_no_ata_d3(struct pci_dev *pdev) 1464 { 1465 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1466 } 1467 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1468 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1469 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1470 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1471 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1472 /* ALi loses some register settings that we cannot then restore */ 1473 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1474 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1475 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1476 occur when mode detecting */ 1477 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1478 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1479 1480 /* 1481 * This was originally an Alpha-specific thing, but it really fits here. 1482 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1483 */ 1484 static void quirk_eisa_bridge(struct pci_dev *dev) 1485 { 1486 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1487 } 1488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1489 1490 /* 1491 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1492 * is not activated. The myth is that Asus said that they do not want the 1493 * users to be irritated by just another PCI Device in the Win98 device 1494 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1495 * package 2.7.0 for details) 1496 * 1497 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1498 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1499 * becomes necessary to do this tweak in two steps -- the chosen trigger 1500 * is either the Host bridge (preferred) or on-board VGA controller. 1501 * 1502 * Note that we used to unhide the SMBus that way on Toshiba laptops 1503 * (Satellite A40 and Tecra M2) but then found that the thermal management 1504 * was done by SMM code, which could cause unsynchronized concurrent 1505 * accesses to the SMBus registers, with potentially bad effects. Thus you 1506 * should be very careful when adding new entries: if SMM is accessing the 1507 * Intel SMBus, this is a very good reason to leave it hidden. 1508 * 1509 * Likewise, many recent laptops use ACPI for thermal management. If the 1510 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1511 * natively, and keeping the SMBus hidden is the right thing to do. If you 1512 * are about to add an entry in the table below, please first disassemble 1513 * the DSDT and double-check that there is no code accessing the SMBus. 1514 */ 1515 static int asus_hides_smbus; 1516 1517 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1518 { 1519 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1520 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1521 switch (dev->subsystem_device) { 1522 case 0x8025: /* P4B-LX */ 1523 case 0x8070: /* P4B */ 1524 case 0x8088: /* P4B533 */ 1525 case 0x1626: /* L3C notebook */ 1526 asus_hides_smbus = 1; 1527 } 1528 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1529 switch (dev->subsystem_device) { 1530 case 0x80b1: /* P4GE-V */ 1531 case 0x80b2: /* P4PE */ 1532 case 0x8093: /* P4B533-V */ 1533 asus_hides_smbus = 1; 1534 } 1535 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1536 switch (dev->subsystem_device) { 1537 case 0x8030: /* P4T533 */ 1538 asus_hides_smbus = 1; 1539 } 1540 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1541 switch (dev->subsystem_device) { 1542 case 0x8070: /* P4G8X Deluxe */ 1543 asus_hides_smbus = 1; 1544 } 1545 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1546 switch (dev->subsystem_device) { 1547 case 0x80c9: /* PU-DLS */ 1548 asus_hides_smbus = 1; 1549 } 1550 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1551 switch (dev->subsystem_device) { 1552 case 0x1751: /* M2N notebook */ 1553 case 0x1821: /* M5N notebook */ 1554 case 0x1897: /* A6L notebook */ 1555 asus_hides_smbus = 1; 1556 } 1557 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1558 switch (dev->subsystem_device) { 1559 case 0x184b: /* W1N notebook */ 1560 case 0x186a: /* M6Ne notebook */ 1561 asus_hides_smbus = 1; 1562 } 1563 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1564 switch (dev->subsystem_device) { 1565 case 0x80f2: /* P4P800-X */ 1566 asus_hides_smbus = 1; 1567 } 1568 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1569 switch (dev->subsystem_device) { 1570 case 0x1882: /* M6V notebook */ 1571 case 0x1977: /* A6VA notebook */ 1572 asus_hides_smbus = 1; 1573 } 1574 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1575 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1576 switch (dev->subsystem_device) { 1577 case 0x088C: /* HP Compaq nc8000 */ 1578 case 0x0890: /* HP Compaq nc6000 */ 1579 asus_hides_smbus = 1; 1580 } 1581 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1582 switch (dev->subsystem_device) { 1583 case 0x12bc: /* HP D330L */ 1584 case 0x12bd: /* HP D530 */ 1585 case 0x006a: /* HP Compaq nx9500 */ 1586 asus_hides_smbus = 1; 1587 } 1588 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1589 switch (dev->subsystem_device) { 1590 case 0x12bf: /* HP xw4100 */ 1591 asus_hides_smbus = 1; 1592 } 1593 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1594 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1595 switch (dev->subsystem_device) { 1596 case 0xC00C: /* Samsung P35 notebook */ 1597 asus_hides_smbus = 1; 1598 } 1599 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1600 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1601 switch (dev->subsystem_device) { 1602 case 0x0058: /* Compaq Evo N620c */ 1603 asus_hides_smbus = 1; 1604 } 1605 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1606 switch (dev->subsystem_device) { 1607 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1608 /* Motherboard doesn't have Host bridge 1609 * subvendor/subdevice IDs, therefore checking 1610 * its on-board VGA controller */ 1611 asus_hides_smbus = 1; 1612 } 1613 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1614 switch (dev->subsystem_device) { 1615 case 0x00b8: /* Compaq Evo D510 CMT */ 1616 case 0x00b9: /* Compaq Evo D510 SFF */ 1617 case 0x00ba: /* Compaq Evo D510 USDT */ 1618 /* Motherboard doesn't have Host bridge 1619 * subvendor/subdevice IDs and on-board VGA 1620 * controller is disabled if an AGP card is 1621 * inserted, therefore checking USB UHCI 1622 * Controller #1 */ 1623 asus_hides_smbus = 1; 1624 } 1625 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1626 switch (dev->subsystem_device) { 1627 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1628 /* Motherboard doesn't have host bridge 1629 * subvendor/subdevice IDs, therefore checking 1630 * its on-board VGA controller */ 1631 asus_hides_smbus = 1; 1632 } 1633 } 1634 } 1635 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1636 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1637 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1638 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1639 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1640 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1641 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1642 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1643 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1645 1646 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1647 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1648 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1649 1650 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1651 { 1652 u16 val; 1653 1654 if (likely(!asus_hides_smbus)) 1655 return; 1656 1657 pci_read_config_word(dev, 0xF2, &val); 1658 if (val & 0x8) { 1659 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1660 pci_read_config_word(dev, 0xF2, &val); 1661 if (val & 0x8) 1662 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1663 val); 1664 else 1665 pci_info(dev, "Enabled i801 SMBus device\n"); 1666 } 1667 } 1668 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1669 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1670 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1671 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1672 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1673 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1674 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1675 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1676 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1677 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1678 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1679 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1680 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1681 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1682 1683 /* It appears we just have one such device. If not, we have a warning */ 1684 static void __iomem *asus_rcba_base; 1685 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1686 { 1687 u32 rcba; 1688 1689 if (likely(!asus_hides_smbus)) 1690 return; 1691 WARN_ON(asus_rcba_base); 1692 1693 pci_read_config_dword(dev, 0xF0, &rcba); 1694 /* use bits 31:14, 16 kB aligned */ 1695 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); 1696 if (asus_rcba_base == NULL) 1697 return; 1698 } 1699 1700 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1701 { 1702 u32 val; 1703 1704 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1705 return; 1706 1707 /* read the Function Disable register, dword mode only */ 1708 val = readl(asus_rcba_base + 0x3418); 1709 1710 /* enable the SMBus device */ 1711 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1712 } 1713 1714 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1715 { 1716 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1717 return; 1718 1719 iounmap(asus_rcba_base); 1720 asus_rcba_base = NULL; 1721 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1722 } 1723 1724 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1725 { 1726 asus_hides_smbus_lpc_ich6_suspend(dev); 1727 asus_hides_smbus_lpc_ich6_resume_early(dev); 1728 asus_hides_smbus_lpc_ich6_resume(dev); 1729 } 1730 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1731 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1732 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1733 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1734 1735 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1736 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1737 { 1738 u8 val = 0; 1739 pci_read_config_byte(dev, 0x77, &val); 1740 if (val & 0x10) { 1741 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1742 pci_write_config_byte(dev, 0x77, val & ~0x10); 1743 } 1744 } 1745 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1746 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1747 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1748 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1749 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1750 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1751 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1752 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1753 1754 /* 1755 * ... This is further complicated by the fact that some SiS96x south 1756 * bridges pretend to be 85C503/5513 instead. In that case see if we 1757 * spotted a compatible north bridge to make sure. 1758 * (pci_find_device() doesn't work yet) 1759 * 1760 * We can also enable the sis96x bit in the discovery register.. 1761 */ 1762 #define SIS_DETECT_REGISTER 0x40 1763 1764 static void quirk_sis_503(struct pci_dev *dev) 1765 { 1766 u8 reg; 1767 u16 devid; 1768 1769 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1770 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1771 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1772 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1773 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1774 return; 1775 } 1776 1777 /* 1778 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1779 * it has already been processed. (Depends on link order, which is 1780 * apparently not guaranteed) 1781 */ 1782 dev->device = devid; 1783 quirk_sis_96x_smbus(dev); 1784 } 1785 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1786 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1787 1788 /* 1789 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1790 * and MC97 modem controller are disabled when a second PCI soundcard is 1791 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1792 * -- bjd 1793 */ 1794 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1795 { 1796 u8 val; 1797 int asus_hides_ac97 = 0; 1798 1799 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1800 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1801 asus_hides_ac97 = 1; 1802 } 1803 1804 if (!asus_hides_ac97) 1805 return; 1806 1807 pci_read_config_byte(dev, 0x50, &val); 1808 if (val & 0xc0) { 1809 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1810 pci_read_config_byte(dev, 0x50, &val); 1811 if (val & 0xc0) 1812 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1813 val); 1814 else 1815 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1816 } 1817 } 1818 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1819 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1820 1821 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1822 1823 /* 1824 * If we are using libata we can drive this chip properly but must do this 1825 * early on to make the additional device appear during the PCI scanning. 1826 */ 1827 static void quirk_jmicron_ata(struct pci_dev *pdev) 1828 { 1829 u32 conf1, conf5, class; 1830 u8 hdr; 1831 1832 /* Only poke fn 0 */ 1833 if (PCI_FUNC(pdev->devfn)) 1834 return; 1835 1836 pci_read_config_dword(pdev, 0x40, &conf1); 1837 pci_read_config_dword(pdev, 0x80, &conf5); 1838 1839 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1840 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1841 1842 switch (pdev->device) { 1843 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1844 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1845 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1846 /* The controller should be in single function ahci mode */ 1847 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1848 break; 1849 1850 case PCI_DEVICE_ID_JMICRON_JMB365: 1851 case PCI_DEVICE_ID_JMICRON_JMB366: 1852 /* Redirect IDE second PATA port to the right spot */ 1853 conf5 |= (1 << 24); 1854 fallthrough; 1855 case PCI_DEVICE_ID_JMICRON_JMB361: 1856 case PCI_DEVICE_ID_JMICRON_JMB363: 1857 case PCI_DEVICE_ID_JMICRON_JMB369: 1858 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1859 /* Set the class codes correctly and then direct IDE 0 */ 1860 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1861 break; 1862 1863 case PCI_DEVICE_ID_JMICRON_JMB368: 1864 /* The controller should be in single function IDE mode */ 1865 conf1 |= 0x00C00000; /* Set 22, 23 */ 1866 break; 1867 } 1868 1869 pci_write_config_dword(pdev, 0x40, conf1); 1870 pci_write_config_dword(pdev, 0x80, conf5); 1871 1872 /* Update pdev accordingly */ 1873 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1874 pdev->hdr_type = hdr & PCI_HEADER_TYPE_MASK; 1875 pdev->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr); 1876 1877 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1878 pdev->class = class >> 8; 1879 } 1880 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1881 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1882 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1883 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1884 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1885 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1886 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1887 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1888 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1889 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1890 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1891 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1892 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1893 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1894 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1895 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1896 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1897 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1898 1899 #endif 1900 1901 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1902 { 1903 if (dev->multifunction) { 1904 device_disable_async_suspend(&dev->dev); 1905 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1906 } 1907 } 1908 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1909 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1910 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1911 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1912 1913 #ifdef CONFIG_X86_IO_APIC 1914 static void quirk_alder_ioapic(struct pci_dev *pdev) 1915 { 1916 int i; 1917 1918 if ((pdev->class >> 8) != 0xff00) 1919 return; 1920 1921 /* 1922 * The first BAR is the location of the IO-APIC... we must 1923 * not touch this (and it's already covered by the fixmap), so 1924 * forcibly insert it into the resource tree. 1925 */ 1926 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1927 insert_resource(&iomem_resource, &pdev->resource[0]); 1928 1929 /* 1930 * The next five BARs all seem to be rubbish, so just clean 1931 * them out. 1932 */ 1933 for (i = 1; i < PCI_STD_NUM_BARS; i++) 1934 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1935 } 1936 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1937 #endif 1938 1939 static void quirk_no_msi(struct pci_dev *dev) 1940 { 1941 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); 1942 dev->no_msi = 1; 1943 } 1944 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi); 1945 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi); 1946 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi); 1947 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi); 1948 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi); 1949 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi); 1950 1951 static void quirk_pcie_mch(struct pci_dev *pdev) 1952 { 1953 pdev->no_msi = 1; 1954 } 1955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1956 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1957 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1958 1959 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1960 1961 /* 1962 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are 1963 * actually on the AMBA bus. These fake PCI devices can support SVA via 1964 * SMMU stall feature, by setting dma-can-stall for ACPI platforms. 1965 * 1966 * Normally stalling must not be enabled for PCI devices, since it would 1967 * break the PCI requirement for free-flowing writes and may lead to 1968 * deadlock. We expect PCI devices to support ATS and PRI if they want to 1969 * be fault-tolerant, so there's no ACPI binding to describe anything else, 1970 * even when a "PCI" device turns out to be a regular old SoC device 1971 * dressed up as a RCiEP and normal rules don't apply. 1972 */ 1973 static void quirk_huawei_pcie_sva(struct pci_dev *pdev) 1974 { 1975 struct property_entry properties[] = { 1976 PROPERTY_ENTRY_BOOL("dma-can-stall"), 1977 {}, 1978 }; 1979 1980 if (pdev->revision != 0x21 && pdev->revision != 0x30) 1981 return; 1982 1983 pdev->pasid_no_tlp = 1; 1984 1985 /* 1986 * Set the dma-can-stall property on ACPI platforms. Device tree 1987 * can set it directly. 1988 */ 1989 if (!pdev->dev.of_node && 1990 device_create_managed_software_node(&pdev->dev, properties, NULL)) 1991 pci_warn(pdev, "could not add stall property"); 1992 } 1993 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); 1994 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); 1995 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva); 1996 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva); 1997 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva); 1998 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva); 1999 2000 /* 2001 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 2002 * together on certain PXH-based systems. 2003 */ 2004 static void quirk_pcie_pxh(struct pci_dev *dev) 2005 { 2006 dev->no_msi = 1; 2007 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 2008 } 2009 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 2010 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 2011 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 2012 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 2013 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 2014 2015 /* 2016 * Some Intel PCI Express chipsets have trouble with downstream device 2017 * power management. 2018 */ 2019 static void quirk_intel_pcie_pm(struct pci_dev *dev) 2020 { 2021 pci_pm_d3hot_delay = 120; 2022 dev->no_d1d2 = 1; 2023 } 2024 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 2025 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 2026 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 2027 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 2028 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 2029 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 2030 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 2031 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 2032 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 2033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 2036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 2038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 2039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 2040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 2041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 2042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 2043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 2044 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 2045 2046 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) 2047 { 2048 if (dev->d3hot_delay >= delay) 2049 return; 2050 2051 dev->d3hot_delay = delay; 2052 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", 2053 dev->d3hot_delay); 2054 } 2055 2056 static void quirk_radeon_pm(struct pci_dev *dev) 2057 { 2058 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 2059 dev->subsystem_device == 0x00e2) 2060 quirk_d3hot_delay(dev, 20); 2061 } 2062 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 2063 2064 /* 2065 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus 2066 * reset is performed too soon after transition to D0, extend d3hot_delay 2067 * to previous effective default for all NVIDIA HDA controllers. 2068 */ 2069 static void quirk_nvidia_hda_pm(struct pci_dev *dev) 2070 { 2071 quirk_d3hot_delay(dev, 20); 2072 } 2073 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 2074 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, 2075 quirk_nvidia_hda_pm); 2076 2077 /* 2078 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. 2079 * https://bugzilla.kernel.org/show_bug.cgi?id=205587 2080 * 2081 * The kernel attempts to transition these devices to D3cold, but that seems 2082 * to be ineffective on the platforms in question; the PCI device appears to 2083 * remain on in D3hot state. The D3hot-to-D0 transition then requires an 2084 * extended delay in order to succeed. 2085 */ 2086 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) 2087 { 2088 quirk_d3hot_delay(dev, 20); 2089 } 2090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); 2091 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); 2092 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); 2093 2094 #ifdef CONFIG_X86_IO_APIC 2095 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 2096 { 2097 noioapicreroute = 1; 2098 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 2099 2100 return 0; 2101 } 2102 2103 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 2104 /* 2105 * Systems to exclude from boot interrupt reroute quirks 2106 */ 2107 { 2108 .callback = dmi_disable_ioapicreroute, 2109 .ident = "ASUSTek Computer INC. M2N-LR", 2110 .matches = { 2111 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 2112 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 2113 }, 2114 }, 2115 {} 2116 }; 2117 2118 /* 2119 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 2120 * remap the original interrupt in the Linux kernel to the boot interrupt, so 2121 * that a PCI device's interrupt handler is installed on the boot interrupt 2122 * line instead. 2123 */ 2124 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 2125 { 2126 dmi_check_system(boot_interrupt_dmi_table); 2127 if (noioapicquirk || noioapicreroute) 2128 return; 2129 2130 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 2131 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 2132 dev->vendor, dev->device); 2133 } 2134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2135 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2136 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2137 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2138 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2139 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2141 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2142 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2143 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2144 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2145 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2146 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2147 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2148 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2149 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2150 2151 /* 2152 * On some chipsets we can disable the generation of legacy INTx boot 2153 * interrupts. 2154 */ 2155 2156 /* 2157 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 2158 * 300641-004US, section 5.7.3. 2159 * 2160 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. 2161 * Core IO on Xeon E5 v2, see Intel order no 329188-003. 2162 * Core IO on Xeon E7 v2, see Intel order no 329595-002. 2163 * Core IO on Xeon E5 v3, see Intel order no 330784-003. 2164 * Core IO on Xeon E7 v3, see Intel order no 332315-001US. 2165 * Core IO on Xeon E5 v4, see Intel order no 333810-002US. 2166 * Core IO on Xeon E7 v4, see Intel order no 332315-001US. 2167 * Core IO on Xeon D-1500, see Intel order no 332051-001. 2168 * Core IO on Xeon Scalable, see Intel order no 610950. 2169 */ 2170 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ 2171 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 2172 2173 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ 2174 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) 2175 2176 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 2177 { 2178 u16 pci_config_word; 2179 u32 pci_config_dword; 2180 2181 if (noioapicquirk) 2182 return; 2183 2184 switch (dev->device) { 2185 case PCI_DEVICE_ID_INTEL_ESB_10: 2186 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2187 &pci_config_word); 2188 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 2189 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2190 pci_config_word); 2191 break; 2192 case 0x3c28: /* Xeon E5 1600/2600/4600 */ 2193 case 0x0e28: /* Xeon E5/E7 V2 */ 2194 case 0x2f28: /* Xeon E5/E7 V3,V4 */ 2195 case 0x6f28: /* Xeon D-1500 */ 2196 case 0x2034: /* Xeon Scalable Family */ 2197 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2198 &pci_config_dword); 2199 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; 2200 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2201 pci_config_dword); 2202 break; 2203 default: 2204 return; 2205 } 2206 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2207 dev->vendor, dev->device); 2208 } 2209 /* 2210 * Device 29 Func 5 Device IDs of IO-APIC 2211 * containing ABAR—APIC1 Alternate Base Address Register 2212 */ 2213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2214 quirk_disable_intel_boot_interrupt); 2215 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2216 quirk_disable_intel_boot_interrupt); 2217 2218 /* 2219 * Device 5 Func 0 Device IDs of Core IO modules/hubs 2220 * containing Coherent Interface Protocol Interrupt Control 2221 * 2222 * Device IDs obtained from volume 2 datasheets of commented 2223 * families above. 2224 */ 2225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, 2226 quirk_disable_intel_boot_interrupt); 2227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, 2228 quirk_disable_intel_boot_interrupt); 2229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, 2230 quirk_disable_intel_boot_interrupt); 2231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, 2232 quirk_disable_intel_boot_interrupt); 2233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, 2234 quirk_disable_intel_boot_interrupt); 2235 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, 2236 quirk_disable_intel_boot_interrupt); 2237 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, 2238 quirk_disable_intel_boot_interrupt); 2239 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, 2240 quirk_disable_intel_boot_interrupt); 2241 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, 2242 quirk_disable_intel_boot_interrupt); 2243 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, 2244 quirk_disable_intel_boot_interrupt); 2245 2246 /* Disable boot interrupts on HT-1000 */ 2247 #define BC_HT1000_FEATURE_REG 0x64 2248 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 2249 #define BC_HT1000_MAP_IDX 0xC00 2250 #define BC_HT1000_MAP_DATA 0xC01 2251 2252 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 2253 { 2254 u32 pci_config_dword; 2255 u8 irq; 2256 2257 if (noioapicquirk) 2258 return; 2259 2260 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 2261 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 2262 BC_HT1000_PIC_REGS_ENABLE); 2263 2264 for (irq = 0x10; irq < 0x10 + 32; irq++) { 2265 outb(irq, BC_HT1000_MAP_IDX); 2266 outb(0x00, BC_HT1000_MAP_DATA); 2267 } 2268 2269 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 2270 2271 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2272 dev->vendor, dev->device); 2273 } 2274 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2275 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2276 2277 /* Disable boot interrupts on AMD and ATI chipsets */ 2278 2279 /* 2280 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2281 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2282 * (due to an erratum). 2283 */ 2284 #define AMD_813X_MISC 0x40 2285 #define AMD_813X_NOIOAMODE (1<<0) 2286 #define AMD_813X_REV_B1 0x12 2287 #define AMD_813X_REV_B2 0x13 2288 2289 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2290 { 2291 u32 pci_config_dword; 2292 2293 if (noioapicquirk) 2294 return; 2295 if ((dev->revision == AMD_813X_REV_B1) || 2296 (dev->revision == AMD_813X_REV_B2)) 2297 return; 2298 2299 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2300 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2301 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2302 2303 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2304 dev->vendor, dev->device); 2305 } 2306 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2307 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2308 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2309 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2310 2311 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2312 2313 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2314 { 2315 u16 pci_config_word; 2316 2317 if (noioapicquirk) 2318 return; 2319 2320 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2321 if (!pci_config_word) { 2322 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2323 dev->vendor, dev->device); 2324 return; 2325 } 2326 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2327 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2328 dev->vendor, dev->device); 2329 } 2330 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2331 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2332 #endif /* CONFIG_X86_IO_APIC */ 2333 2334 /* 2335 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2336 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2337 * Re-allocate the region if needed... 2338 */ 2339 static void quirk_tc86c001_ide(struct pci_dev *dev) 2340 { 2341 struct resource *r = &dev->resource[0]; 2342 2343 if (r->start & 0x8) { 2344 r->flags |= IORESOURCE_UNSET; 2345 resource_set_range(r, 0, SZ_16); 2346 } 2347 } 2348 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2349 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2350 quirk_tc86c001_ide); 2351 2352 /* 2353 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2354 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2355 * being read correctly if bit 7 of the base address is set. 2356 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2357 * Re-allocate the regions to a 256-byte boundary if necessary. 2358 */ 2359 static void quirk_plx_pci9050(struct pci_dev *dev) 2360 { 2361 unsigned int bar; 2362 2363 /* Fixed in revision 2 (PCI 9052). */ 2364 if (dev->revision >= 2) 2365 return; 2366 for (bar = 0; bar <= 1; bar++) 2367 if (pci_resource_len(dev, bar) == 0x80 && 2368 (pci_resource_start(dev, bar) & 0x80)) { 2369 struct resource *r = &dev->resource[bar]; 2370 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2371 bar); 2372 r->flags |= IORESOURCE_UNSET; 2373 resource_set_range(r, 0, SZ_256); 2374 } 2375 } 2376 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2377 quirk_plx_pci9050); 2378 /* 2379 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2380 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2381 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2382 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2383 * 2384 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2385 * driver. 2386 */ 2387 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2388 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2389 2390 static void quirk_netmos(struct pci_dev *dev) 2391 { 2392 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2393 unsigned int num_serial = dev->subsystem_device & 0xf; 2394 2395 /* 2396 * These Netmos parts are multiport serial devices with optional 2397 * parallel ports. Even when parallel ports are present, they 2398 * are identified as class SERIAL, which means the serial driver 2399 * will claim them. To prevent this, mark them as class OTHER. 2400 * These combo devices should be claimed by parport_serial. 2401 * 2402 * The subdevice ID is of the form 0x00PS, where <P> is the number 2403 * of parallel ports and <S> is the number of serial ports. 2404 */ 2405 switch (dev->device) { 2406 case PCI_DEVICE_ID_NETMOS_9835: 2407 /* Well, this rule doesn't hold for the following 9835 device */ 2408 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2409 dev->subsystem_device == 0x0299) 2410 return; 2411 fallthrough; 2412 case PCI_DEVICE_ID_NETMOS_9735: 2413 case PCI_DEVICE_ID_NETMOS_9745: 2414 case PCI_DEVICE_ID_NETMOS_9845: 2415 case PCI_DEVICE_ID_NETMOS_9855: 2416 if (num_parallel) { 2417 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2418 dev->device, num_parallel, num_serial); 2419 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2420 (dev->class & 0xff); 2421 } 2422 } 2423 } 2424 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2425 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2426 2427 static void quirk_e100_interrupt(struct pci_dev *dev) 2428 { 2429 u16 command, pmcsr; 2430 u8 __iomem *csr; 2431 u8 cmd_hi; 2432 2433 switch (dev->device) { 2434 /* PCI IDs taken from drivers/net/e100.c */ 2435 case 0x1029: 2436 case 0x1030 ... 0x1034: 2437 case 0x1038 ... 0x103E: 2438 case 0x1050 ... 0x1057: 2439 case 0x1059: 2440 case 0x1064 ... 0x106B: 2441 case 0x1091 ... 0x1095: 2442 case 0x1209: 2443 case 0x1229: 2444 case 0x2449: 2445 case 0x2459: 2446 case 0x245D: 2447 case 0x27DC: 2448 break; 2449 default: 2450 return; 2451 } 2452 2453 /* 2454 * Some firmware hands off the e100 with interrupts enabled, 2455 * which can cause a flood of interrupts if packets are 2456 * received before the driver attaches to the device. So 2457 * disable all e100 interrupts here. The driver will 2458 * re-enable them when it's ready. 2459 */ 2460 pci_read_config_word(dev, PCI_COMMAND, &command); 2461 2462 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2463 return; 2464 2465 /* 2466 * Check that the device is in the D0 power state. If it's not, 2467 * there is no point to look any further. 2468 */ 2469 if (dev->pm_cap) { 2470 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2471 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2472 return; 2473 } 2474 2475 /* Convert from PCI bus to resource space. */ 2476 csr = ioremap(pci_resource_start(dev, 0), 8); 2477 if (!csr) { 2478 pci_warn(dev, "Can't map e100 registers\n"); 2479 return; 2480 } 2481 2482 cmd_hi = readb(csr + 3); 2483 if (cmd_hi == 0) { 2484 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2485 writeb(1, csr + 3); 2486 } 2487 2488 iounmap(csr); 2489 } 2490 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2491 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2492 2493 /* 2494 * The 82575 and 82598 may experience data corruption issues when transitioning 2495 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2496 */ 2497 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2498 { 2499 pci_info(dev, "Disabling L0s\n"); 2500 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S); 2501 } 2502 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2503 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2504 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2505 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2506 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2507 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2508 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2509 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2510 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2511 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2512 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2513 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2514 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2515 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2516 2517 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 2518 { 2519 pci_info(dev, "Disabling ASPM L0s/L1\n"); 2520 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1); 2521 } 2522 2523 /* 2524 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the 2525 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; 2526 * disable both L0s and L1 for now to be safe. 2527 */ 2528 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); 2529 2530 /* 2531 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain 2532 * Link bit cleared after starting the link retrain process to allow this 2533 * process to finish. 2534 * 2535 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the 2536 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. 2537 */ 2538 static void quirk_enable_clear_retrain_link(struct pci_dev *dev) 2539 { 2540 dev->clear_retrain_link = 1; 2541 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2542 } 2543 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); 2544 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); 2545 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); 2546 2547 static void fixup_rev1_53c810(struct pci_dev *dev) 2548 { 2549 u32 class = dev->class; 2550 2551 /* 2552 * rev 1 ncr53c810 chips don't set the class at all which means 2553 * they don't get their resources remapped. Fix that here. 2554 */ 2555 if (class) 2556 return; 2557 2558 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2559 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2560 class, dev->class); 2561 } 2562 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2563 2564 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2565 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2566 { 2567 u16 en1k; 2568 2569 pci_read_config_word(dev, 0x40, &en1k); 2570 2571 if (en1k & 0x200) { 2572 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2573 dev->io_window_1k = 1; 2574 } 2575 } 2576 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2577 2578 /* 2579 * Under some circumstances, AER is not linked with extended capabilities. 2580 * Force it to be linked by setting the corresponding control bit in the 2581 * config space. 2582 */ 2583 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2584 { 2585 uint8_t b; 2586 2587 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2588 if (!(b & 0x20)) { 2589 pci_write_config_byte(dev, 0xf41, b | 0x20); 2590 pci_info(dev, "Linking AER extended capability\n"); 2591 } 2592 } 2593 } 2594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2595 quirk_nvidia_ck804_pcie_aer_ext_cap); 2596 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2597 quirk_nvidia_ck804_pcie_aer_ext_cap); 2598 2599 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2600 { 2601 /* 2602 * Disable PCI Bus Parking and PCI Master read caching on CX700 2603 * which causes unspecified timing errors with a VT6212L on the PCI 2604 * bus leading to USB2.0 packet loss. 2605 * 2606 * This quirk is only enabled if a second (on the external PCI bus) 2607 * VT6212L is found -- the CX700 core itself also contains a USB 2608 * host controller with the same PCI ID as the VT6212L. 2609 */ 2610 2611 /* Count VT6212L instances */ 2612 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2613 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2614 uint8_t b; 2615 2616 /* 2617 * p should contain the first (internal) VT6212L -- see if we have 2618 * an external one by searching again. 2619 */ 2620 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2621 if (!p) 2622 return; 2623 pci_dev_put(p); 2624 2625 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2626 if (b & 0x40) { 2627 /* Turn off PCI Bus Parking */ 2628 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2629 2630 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2631 } 2632 } 2633 2634 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2635 if (b != 0) { 2636 /* Turn off PCI Master read caching */ 2637 pci_write_config_byte(dev, 0x72, 0x0); 2638 2639 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2640 pci_write_config_byte(dev, 0x75, 0x1); 2641 2642 /* Disable "Read FIFO Timer" */ 2643 pci_write_config_byte(dev, 0x77, 0x0); 2644 2645 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2646 } 2647 } 2648 } 2649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2650 2651 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2652 { 2653 u32 rev; 2654 2655 pci_read_config_dword(dev, 0xf4, &rev); 2656 2657 /* Only CAP the MRRS if the device is a 5719 A0 */ 2658 if (rev == 0x05719000) { 2659 int readrq = pcie_get_readrq(dev); 2660 if (readrq > 2048) 2661 pcie_set_readrq(dev, 2048); 2662 } 2663 } 2664 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2665 PCI_DEVICE_ID_TIGON3_5719, 2666 quirk_brcm_5719_limit_mrrs); 2667 2668 /* 2669 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2670 * hide device 6 which configures the overflow device access containing the 2671 * DRBs - this is where we expose device 6. 2672 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2673 */ 2674 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2675 { 2676 u8 reg; 2677 2678 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2679 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2680 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2681 } 2682 } 2683 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2684 quirk_unhide_mch_dev6); 2685 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2686 quirk_unhide_mch_dev6); 2687 2688 #ifdef CONFIG_PCI_MSI 2689 /* 2690 * Some chipsets do not support MSI. We cannot easily rely on setting 2691 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2692 * other buses controlled by the chipset even if Linux is not aware of it. 2693 * Instead of setting the flag on all buses in the machine, simply disable 2694 * MSI globally. 2695 */ 2696 static void quirk_disable_all_msi(struct pci_dev *dev) 2697 { 2698 pci_no_msi(); 2699 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2700 } 2701 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2702 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2703 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2704 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2705 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2706 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2707 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2709 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); 2710 2711 /* Disable MSI on chipsets that are known to not support it */ 2712 static void quirk_disable_msi(struct pci_dev *dev) 2713 { 2714 if (dev->subordinate) { 2715 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2716 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2717 } 2718 } 2719 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2721 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2722 2723 /* 2724 * The APC bridge device in AMD 780 family northbridges has some random 2725 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2726 * we use the possible vendor/device IDs of the host bridge for the 2727 * declared quirk, and search for the APC bridge by slot number. 2728 */ 2729 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2730 { 2731 struct pci_dev *apc_bridge; 2732 2733 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2734 if (apc_bridge) { 2735 if (apc_bridge->device == 0x9602) 2736 quirk_disable_msi(apc_bridge); 2737 pci_dev_put(apc_bridge); 2738 } 2739 } 2740 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2741 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2742 2743 /* 2744 * Go through the list of HyperTransport capabilities and return 1 if a HT 2745 * MSI capability is found and enabled. 2746 */ 2747 static int msi_ht_cap_enabled(struct pci_dev *dev) 2748 { 2749 int pos, ttl = PCI_FIND_CAP_TTL; 2750 2751 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2752 while (pos && ttl--) { 2753 u8 flags; 2754 2755 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2756 &flags) == 0) { 2757 pci_info(dev, "Found %s HT MSI Mapping\n", 2758 flags & HT_MSI_FLAGS_ENABLE ? 2759 "enabled" : "disabled"); 2760 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2761 } 2762 2763 pos = pci_find_next_ht_capability(dev, pos, 2764 HT_CAPTYPE_MSI_MAPPING); 2765 } 2766 return 0; 2767 } 2768 2769 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2770 static void quirk_msi_ht_cap(struct pci_dev *dev) 2771 { 2772 if (!msi_ht_cap_enabled(dev)) 2773 quirk_disable_msi(dev); 2774 } 2775 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2776 quirk_msi_ht_cap); 2777 2778 /* 2779 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2780 * if the MSI capability is set in any of these mappings. 2781 */ 2782 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2783 { 2784 struct pci_dev *pdev; 2785 2786 /* 2787 * Check HT MSI cap on this chipset and the root one. A single one 2788 * having MSI is enough to be sure that MSI is supported. 2789 */ 2790 pdev = pci_get_slot(dev->bus, 0); 2791 if (!pdev) 2792 return; 2793 if (!msi_ht_cap_enabled(pdev)) 2794 quirk_msi_ht_cap(dev); 2795 pci_dev_put(pdev); 2796 } 2797 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2798 quirk_nvidia_ck804_msi_ht_cap); 2799 2800 /* Force enable MSI mapping capability on HT bridges */ 2801 static void ht_enable_msi_mapping(struct pci_dev *dev) 2802 { 2803 int pos, ttl = PCI_FIND_CAP_TTL; 2804 2805 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2806 while (pos && ttl--) { 2807 u8 flags; 2808 2809 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2810 &flags) == 0) { 2811 pci_info(dev, "Enabling HT MSI Mapping\n"); 2812 2813 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2814 flags | HT_MSI_FLAGS_ENABLE); 2815 } 2816 pos = pci_find_next_ht_capability(dev, pos, 2817 HT_CAPTYPE_MSI_MAPPING); 2818 } 2819 } 2820 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2821 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2822 ht_enable_msi_mapping); 2823 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2824 ht_enable_msi_mapping); 2825 2826 /* 2827 * The P5N32-SLI motherboards from Asus have a problem with MSI 2828 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2829 * also affects other devices. As for now, turn off MSI for this device. 2830 */ 2831 static void nvenet_msi_disable(struct pci_dev *dev) 2832 { 2833 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2834 2835 if (board_name && 2836 (strstr(board_name, "P5N32-SLI PREMIUM") || 2837 strstr(board_name, "P5N32-E SLI"))) { 2838 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2839 dev->no_msi = 1; 2840 } 2841 } 2842 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2843 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2844 nvenet_msi_disable); 2845 2846 /* 2847 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device 2848 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI 2849 * interrupts for PME and AER events; instead only INTx interrupts are 2850 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts 2851 * for other events, since PCIe specification doesn't support using a mix of 2852 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port 2853 * service drivers registering their respective ISRs for MSIs. 2854 */ 2855 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) 2856 { 2857 dev->no_msi = 1; 2858 } 2859 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, 2860 PCI_CLASS_BRIDGE_PCI, 8, 2861 pci_quirk_nvidia_tegra_disable_rp_msi); 2862 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, 2863 PCI_CLASS_BRIDGE_PCI, 8, 2864 pci_quirk_nvidia_tegra_disable_rp_msi); 2865 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, 2866 PCI_CLASS_BRIDGE_PCI, 8, 2867 pci_quirk_nvidia_tegra_disable_rp_msi); 2868 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, 2869 PCI_CLASS_BRIDGE_PCI, 8, 2870 pci_quirk_nvidia_tegra_disable_rp_msi); 2871 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, 2872 PCI_CLASS_BRIDGE_PCI, 8, 2873 pci_quirk_nvidia_tegra_disable_rp_msi); 2874 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, 2875 PCI_CLASS_BRIDGE_PCI, 8, 2876 pci_quirk_nvidia_tegra_disable_rp_msi); 2877 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, 2878 PCI_CLASS_BRIDGE_PCI, 8, 2879 pci_quirk_nvidia_tegra_disable_rp_msi); 2880 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, 2881 PCI_CLASS_BRIDGE_PCI, 8, 2882 pci_quirk_nvidia_tegra_disable_rp_msi); 2883 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, 2884 PCI_CLASS_BRIDGE_PCI, 8, 2885 pci_quirk_nvidia_tegra_disable_rp_msi); 2886 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, 2887 PCI_CLASS_BRIDGE_PCI, 8, 2888 pci_quirk_nvidia_tegra_disable_rp_msi); 2889 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, 2890 PCI_CLASS_BRIDGE_PCI, 8, 2891 pci_quirk_nvidia_tegra_disable_rp_msi); 2892 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 2893 PCI_CLASS_BRIDGE_PCI, 8, 2894 pci_quirk_nvidia_tegra_disable_rp_msi); 2895 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, 2896 PCI_CLASS_BRIDGE_PCI, 8, 2897 pci_quirk_nvidia_tegra_disable_rp_msi); 2898 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, 2899 PCI_CLASS_BRIDGE_PCI, 8, 2900 pci_quirk_nvidia_tegra_disable_rp_msi); 2901 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, 2902 PCI_CLASS_BRIDGE_PCI, 8, 2903 pci_quirk_nvidia_tegra_disable_rp_msi); 2904 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, 2905 PCI_CLASS_BRIDGE_PCI, 8, 2906 pci_quirk_nvidia_tegra_disable_rp_msi); 2907 2908 /* 2909 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2910 * config register. This register controls the routing of legacy 2911 * interrupts from devices that route through the MCP55. If this register 2912 * is misprogrammed, interrupts are only sent to the BSP, unlike 2913 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2914 * having this register set properly prevents kdump from booting up 2915 * properly, so let's make sure that we have it set correctly. 2916 * Note that this is an undocumented register. 2917 */ 2918 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2919 { 2920 u32 cfg; 2921 2922 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2923 return; 2924 2925 pci_read_config_dword(dev, 0x74, &cfg); 2926 2927 if (cfg & ((1 << 2) | (1 << 15))) { 2928 pr_info("Rewriting IRQ routing register on MCP55\n"); 2929 cfg &= ~((1 << 2) | (1 << 15)); 2930 pci_write_config_dword(dev, 0x74, cfg); 2931 } 2932 } 2933 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2934 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2935 nvbridge_check_legacy_irq_routing); 2936 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2937 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2938 nvbridge_check_legacy_irq_routing); 2939 2940 static int ht_check_msi_mapping(struct pci_dev *dev) 2941 { 2942 int pos, ttl = PCI_FIND_CAP_TTL; 2943 int found = 0; 2944 2945 /* Check if there is HT MSI cap or enabled on this device */ 2946 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2947 while (pos && ttl--) { 2948 u8 flags; 2949 2950 if (found < 1) 2951 found = 1; 2952 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2953 &flags) == 0) { 2954 if (flags & HT_MSI_FLAGS_ENABLE) { 2955 if (found < 2) { 2956 found = 2; 2957 break; 2958 } 2959 } 2960 } 2961 pos = pci_find_next_ht_capability(dev, pos, 2962 HT_CAPTYPE_MSI_MAPPING); 2963 } 2964 2965 return found; 2966 } 2967 2968 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2969 { 2970 struct pci_dev *dev; 2971 int pos; 2972 int i, dev_no; 2973 int found = 0; 2974 2975 dev_no = host_bridge->devfn >> 3; 2976 for (i = dev_no + 1; i < 0x20; i++) { 2977 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2978 if (!dev) 2979 continue; 2980 2981 /* found next host bridge? */ 2982 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2983 if (pos != 0) { 2984 pci_dev_put(dev); 2985 break; 2986 } 2987 2988 if (ht_check_msi_mapping(dev)) { 2989 found = 1; 2990 pci_dev_put(dev); 2991 break; 2992 } 2993 pci_dev_put(dev); 2994 } 2995 2996 return found; 2997 } 2998 2999 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 3000 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 3001 3002 static int is_end_of_ht_chain(struct pci_dev *dev) 3003 { 3004 int pos, ctrl_off; 3005 int end = 0; 3006 u16 flags, ctrl; 3007 3008 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 3009 3010 if (!pos) 3011 goto out; 3012 3013 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 3014 3015 ctrl_off = ((flags >> 10) & 1) ? 3016 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 3017 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 3018 3019 if (ctrl & (1 << 6)) 3020 end = 1; 3021 3022 out: 3023 return end; 3024 } 3025 3026 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 3027 { 3028 struct pci_dev *host_bridge; 3029 int pos; 3030 int i, dev_no; 3031 int found = 0; 3032 3033 dev_no = dev->devfn >> 3; 3034 for (i = dev_no; i >= 0; i--) { 3035 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 3036 if (!host_bridge) 3037 continue; 3038 3039 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3040 if (pos != 0) { 3041 found = 1; 3042 break; 3043 } 3044 pci_dev_put(host_bridge); 3045 } 3046 3047 if (!found) 3048 return; 3049 3050 /* don't enable end_device/host_bridge with leaf directly here */ 3051 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 3052 host_bridge_with_leaf(host_bridge)) 3053 goto out; 3054 3055 /* root did that ! */ 3056 if (msi_ht_cap_enabled(host_bridge)) 3057 goto out; 3058 3059 ht_enable_msi_mapping(dev); 3060 3061 out: 3062 pci_dev_put(host_bridge); 3063 } 3064 3065 static void ht_disable_msi_mapping(struct pci_dev *dev) 3066 { 3067 int pos, ttl = PCI_FIND_CAP_TTL; 3068 3069 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 3070 while (pos && ttl--) { 3071 u8 flags; 3072 3073 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 3074 &flags) == 0) { 3075 pci_info(dev, "Disabling HT MSI Mapping\n"); 3076 3077 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 3078 flags & ~HT_MSI_FLAGS_ENABLE); 3079 } 3080 pos = pci_find_next_ht_capability(dev, pos, 3081 HT_CAPTYPE_MSI_MAPPING); 3082 } 3083 } 3084 3085 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 3086 { 3087 struct pci_dev *host_bridge; 3088 int pos; 3089 int found; 3090 3091 if (!pci_msi_enabled()) 3092 return; 3093 3094 /* check if there is HT MSI cap or enabled on this device */ 3095 found = ht_check_msi_mapping(dev); 3096 3097 /* no HT MSI CAP */ 3098 if (found == 0) 3099 return; 3100 3101 /* 3102 * HT MSI mapping should be disabled on devices that are below 3103 * a non-HyperTransport host bridge. Locate the host bridge. 3104 */ 3105 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 3106 PCI_DEVFN(0, 0)); 3107 if (host_bridge == NULL) { 3108 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 3109 return; 3110 } 3111 3112 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3113 if (pos != 0) { 3114 /* Host bridge is to HT */ 3115 if (found == 1) { 3116 /* it is not enabled, try to enable it */ 3117 if (all) 3118 ht_enable_msi_mapping(dev); 3119 else 3120 nv_ht_enable_msi_mapping(dev); 3121 } 3122 goto out; 3123 } 3124 3125 /* HT MSI is not enabled */ 3126 if (found == 1) 3127 goto out; 3128 3129 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 3130 ht_disable_msi_mapping(dev); 3131 3132 out: 3133 pci_dev_put(host_bridge); 3134 } 3135 3136 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 3137 { 3138 return __nv_msi_ht_cap_quirk(dev, 1); 3139 } 3140 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3141 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3142 3143 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 3144 { 3145 return __nv_msi_ht_cap_quirk(dev, 0); 3146 } 3147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3148 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3149 3150 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 3151 { 3152 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3153 } 3154 3155 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 3156 { 3157 struct pci_dev *p; 3158 3159 /* 3160 * SB700 MSI issue will be fixed at HW level from revision A21; 3161 * we need check PCI REVISION ID of SMBus controller to get SB700 3162 * revision. 3163 */ 3164 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3165 NULL); 3166 if (!p) 3167 return; 3168 3169 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 3170 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3171 pci_dev_put(p); 3172 } 3173 3174 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 3175 { 3176 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 3177 if (dev->revision < 0x18) { 3178 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 3179 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3180 } 3181 } 3182 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3183 PCI_DEVICE_ID_TIGON3_5780, 3184 quirk_msi_intx_disable_bug); 3185 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3186 PCI_DEVICE_ID_TIGON3_5780S, 3187 quirk_msi_intx_disable_bug); 3188 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3189 PCI_DEVICE_ID_TIGON3_5714, 3190 quirk_msi_intx_disable_bug); 3191 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3192 PCI_DEVICE_ID_TIGON3_5714S, 3193 quirk_msi_intx_disable_bug); 3194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3195 PCI_DEVICE_ID_TIGON3_5715, 3196 quirk_msi_intx_disable_bug); 3197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3198 PCI_DEVICE_ID_TIGON3_5715S, 3199 quirk_msi_intx_disable_bug); 3200 3201 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 3202 quirk_msi_intx_disable_ati_bug); 3203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 3204 quirk_msi_intx_disable_ati_bug); 3205 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 3206 quirk_msi_intx_disable_ati_bug); 3207 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 3208 quirk_msi_intx_disable_ati_bug); 3209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 3210 quirk_msi_intx_disable_ati_bug); 3211 3212 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 3213 quirk_msi_intx_disable_bug); 3214 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 3215 quirk_msi_intx_disable_bug); 3216 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 3217 quirk_msi_intx_disable_bug); 3218 3219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 3220 quirk_msi_intx_disable_bug); 3221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 3222 quirk_msi_intx_disable_bug); 3223 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 3224 quirk_msi_intx_disable_bug); 3225 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 3226 quirk_msi_intx_disable_bug); 3227 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 3228 quirk_msi_intx_disable_bug); 3229 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 3230 quirk_msi_intx_disable_bug); 3231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 3232 quirk_msi_intx_disable_qca_bug); 3233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 3234 quirk_msi_intx_disable_qca_bug); 3235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 3236 quirk_msi_intx_disable_qca_bug); 3237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 3238 quirk_msi_intx_disable_qca_bug); 3239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 3240 quirk_msi_intx_disable_qca_bug); 3241 3242 /* 3243 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it 3244 * should be disabled on platforms where the device (mistakenly) advertises it. 3245 * 3246 * Notice that this quirk also disables MSI (which may work, but hasn't been 3247 * tested), since currently there is no standard way to disable only MSI-X. 3248 * 3249 * The 0031 device id is reused for other non Root Port device types, 3250 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. 3251 */ 3252 static void quirk_al_msi_disable(struct pci_dev *dev) 3253 { 3254 dev->no_msi = 1; 3255 pci_warn(dev, "Disabling MSI/MSI-X\n"); 3256 } 3257 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, 3258 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); 3259 #endif /* CONFIG_PCI_MSI */ 3260 3261 /* 3262 * Allow manual resource allocation for PCI hotplug bridges via 3263 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 3264 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 3265 * allocate resources when hotplug device is inserted and PCI bus is 3266 * rescanned. 3267 */ 3268 static void quirk_hotplug_bridge(struct pci_dev *dev) 3269 { 3270 dev->is_hotplug_bridge = 1; 3271 } 3272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 3273 3274 /* 3275 * This is a quirk for the Ricoh MMC controller found as a part of some 3276 * multifunction chips. 3277 * 3278 * This is very similar and based on the ricoh_mmc driver written by 3279 * Philip Langdale. Thank you for these magic sequences. 3280 * 3281 * These chips implement the four main memory card controllers (SD, MMC, 3282 * MS, xD) and one or both of CardBus or FireWire. 3283 * 3284 * It happens that they implement SD and MMC support as separate 3285 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 3286 * cards but the chip detects MMC cards in hardware and directs them to the 3287 * MMC controller - so the SDHCI driver never sees them. 3288 * 3289 * To get around this, we must disable the useless MMC controller. At that 3290 * point, the SDHCI controller will start seeing them. It seems to be the 3291 * case that the relevant PCI registers to deactivate the MMC controller 3292 * live on PCI function 0, which might be the CardBus controller or the 3293 * FireWire controller, depending on the particular chip in question 3294 * 3295 * This has to be done early, because as soon as we disable the MMC controller 3296 * other PCI functions shift up one level, e.g. function #2 becomes function 3297 * #1, and this will confuse the PCI core. 3298 */ 3299 #ifdef CONFIG_MMC_RICOH_MMC 3300 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 3301 { 3302 u8 write_enable; 3303 u8 write_target; 3304 u8 disable; 3305 3306 /* 3307 * Disable via CardBus interface 3308 * 3309 * This must be done via function #0 3310 */ 3311 if (PCI_FUNC(dev->devfn)) 3312 return; 3313 3314 pci_read_config_byte(dev, 0xB7, &disable); 3315 if (disable & 0x02) 3316 return; 3317 3318 pci_read_config_byte(dev, 0x8E, &write_enable); 3319 pci_write_config_byte(dev, 0x8E, 0xAA); 3320 pci_read_config_byte(dev, 0x8D, &write_target); 3321 pci_write_config_byte(dev, 0x8D, 0xB7); 3322 pci_write_config_byte(dev, 0xB7, disable | 0x02); 3323 pci_write_config_byte(dev, 0x8E, write_enable); 3324 pci_write_config_byte(dev, 0x8D, write_target); 3325 3326 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 3327 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3328 } 3329 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3330 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3331 3332 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 3333 { 3334 u8 write_enable; 3335 u8 disable; 3336 3337 /* 3338 * Disable via FireWire interface 3339 * 3340 * This must be done via function #0 3341 */ 3342 if (PCI_FUNC(dev->devfn)) 3343 return; 3344 /* 3345 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 3346 * certain types of SD/MMC cards. Lowering the SD base clock 3347 * frequency from 200Mhz to 50Mhz fixes this issue. 3348 * 3349 * 0x150 - SD2.0 mode enable for changing base clock 3350 * frequency to 50Mhz 3351 * 0xe1 - Base clock frequency 3352 * 0x32 - 50Mhz new clock frequency 3353 * 0xf9 - Key register for 0x150 3354 * 0xfc - key register for 0xe1 3355 */ 3356 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3357 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3358 pci_write_config_byte(dev, 0xf9, 0xfc); 3359 pci_write_config_byte(dev, 0x150, 0x10); 3360 pci_write_config_byte(dev, 0xf9, 0x00); 3361 pci_write_config_byte(dev, 0xfc, 0x01); 3362 pci_write_config_byte(dev, 0xe1, 0x32); 3363 pci_write_config_byte(dev, 0xfc, 0x00); 3364 3365 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3366 } 3367 3368 pci_read_config_byte(dev, 0xCB, &disable); 3369 3370 if (disable & 0x02) 3371 return; 3372 3373 pci_read_config_byte(dev, 0xCA, &write_enable); 3374 pci_write_config_byte(dev, 0xCA, 0x57); 3375 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3376 pci_write_config_byte(dev, 0xCA, write_enable); 3377 3378 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3379 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3380 3381 } 3382 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3383 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3384 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3385 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3386 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3387 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3388 #endif /*CONFIG_MMC_RICOH_MMC*/ 3389 3390 #ifdef CONFIG_DMAR_TABLE 3391 #define VTUNCERRMSK_REG 0x1ac 3392 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3393 /* 3394 * This is a quirk for masking VT-d spec-defined errors to platform error 3395 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3396 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3397 * on the RAS config settings of the platform) when a VT-d fault happens. 3398 * The resulting SMI caused the system to hang. 3399 * 3400 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3401 * need to report the same error through other channels. 3402 */ 3403 static void vtd_mask_spec_errors(struct pci_dev *dev) 3404 { 3405 u32 word; 3406 3407 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3408 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3409 } 3410 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3411 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3412 #endif 3413 3414 static void fixup_ti816x_class(struct pci_dev *dev) 3415 { 3416 u32 class = dev->class; 3417 3418 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3419 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3420 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3421 class, dev->class); 3422 } 3423 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3424 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3425 3426 /* 3427 * Some PCIe devices do not work reliably with the claimed maximum 3428 * payload size supported. 3429 */ 3430 static void fixup_mpss_256(struct pci_dev *dev) 3431 { 3432 dev->pcie_mpss = 1; /* 256 bytes */ 3433 } 3434 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3435 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3436 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3437 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3438 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3439 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3440 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); 3441 3442 /* 3443 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3444 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3445 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3446 * until all of the devices are discovered and buses walked, read completion 3447 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3448 * it is possible to hotplug a device with MPS of 256B. 3449 */ 3450 static void quirk_intel_mc_errata(struct pci_dev *dev) 3451 { 3452 int err; 3453 u16 rcc; 3454 3455 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3456 pcie_bus_config == PCIE_BUS_DEFAULT) 3457 return; 3458 3459 /* 3460 * Intel erratum specifies bits to change but does not say what 3461 * they are. Keeping them magical until such time as the registers 3462 * and values can be explained. 3463 */ 3464 err = pci_read_config_word(dev, 0x48, &rcc); 3465 if (err) { 3466 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3467 return; 3468 } 3469 3470 if (!(rcc & (1 << 10))) 3471 return; 3472 3473 rcc &= ~(1 << 10); 3474 3475 err = pci_write_config_word(dev, 0x48, rcc); 3476 if (err) { 3477 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3478 return; 3479 } 3480 3481 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3482 } 3483 /* Intel 5000 series memory controllers and ports 2-7 */ 3484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3486 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3487 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3488 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3489 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3490 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3491 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3492 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3493 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3494 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3495 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3498 /* Intel 5100 series memory controllers and ports 2-7 */ 3499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3510 3511 /* 3512 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3513 * To work around this, query the size it should be configured to by the 3514 * device and modify the resource end to correspond to this new size. 3515 */ 3516 static void quirk_intel_ntb(struct pci_dev *dev) 3517 { 3518 int rc; 3519 u8 val; 3520 3521 rc = pci_read_config_byte(dev, 0x00D0, &val); 3522 if (rc) 3523 return; 3524 3525 resource_set_size(&dev->resource[2], (resource_size_t)1 << val); 3526 3527 rc = pci_read_config_byte(dev, 0x00D1, &val); 3528 if (rc) 3529 return; 3530 3531 resource_set_size(&dev->resource[4], (resource_size_t)1 << val); 3532 } 3533 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3534 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3535 3536 /* 3537 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3538 * though no one is handling them (e.g., if the i915 driver is never 3539 * loaded). Additionally the interrupt destination is not set up properly 3540 * and the interrupt ends up -somewhere-. 3541 * 3542 * These spurious interrupts are "sticky" and the kernel disables the 3543 * (shared) interrupt line after 100,000+ generated interrupts. 3544 * 3545 * Fix it by disabling the still enabled interrupts. This resolves crashes 3546 * often seen on monitor unplug. 3547 */ 3548 #define I915_DEIER_REG 0x4400c 3549 static void disable_igfx_irq(struct pci_dev *dev) 3550 { 3551 void __iomem *regs = pci_iomap(dev, 0, 0); 3552 if (regs == NULL) { 3553 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3554 return; 3555 } 3556 3557 /* Check if any interrupt line is still enabled */ 3558 if (readl(regs + I915_DEIER_REG) != 0) { 3559 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3560 3561 writel(0, regs + I915_DEIER_REG); 3562 } 3563 3564 pci_iounmap(dev, regs); 3565 } 3566 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3567 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3568 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3569 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3570 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3571 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3572 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3573 3574 /* 3575 * PCI devices which are on Intel chips can skip the 10ms delay 3576 * before entering D3 mode. 3577 */ 3578 static void quirk_remove_d3hot_delay(struct pci_dev *dev) 3579 { 3580 dev->d3hot_delay = 0; 3581 } 3582 /* C600 Series devices do not need 10ms d3hot_delay */ 3583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); 3584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); 3585 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); 3586 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ 3587 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); 3588 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); 3589 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); 3590 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); 3591 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); 3592 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); 3593 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); 3594 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); 3595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); 3596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); 3597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); 3598 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */ 3599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); 3600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); 3601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); 3602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); 3603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); 3604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); 3605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); 3606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); 3607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); 3608 3609 /* 3610 * Some devices may pass our check in pci_intx_mask_supported() if 3611 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3612 * support this feature. 3613 */ 3614 static void quirk_broken_intx_masking(struct pci_dev *dev) 3615 { 3616 dev->broken_intx_masking = 1; 3617 } 3618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3619 quirk_broken_intx_masking); 3620 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3621 quirk_broken_intx_masking); 3622 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3623 quirk_broken_intx_masking); 3624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K2, 3625 quirk_broken_intx_masking); 3626 3627 /* 3628 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3629 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3630 * 3631 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3632 */ 3633 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3634 quirk_broken_intx_masking); 3635 3636 /* 3637 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3638 * DisINTx can be set but the interrupt status bit is non-functional. 3639 */ 3640 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3642 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3643 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3644 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3646 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3647 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3648 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3649 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3650 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3651 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3656 3657 static u16 mellanox_broken_intx_devs[] = { 3658 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3659 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3660 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3661 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3662 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3663 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3664 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3665 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3666 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3667 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3668 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3669 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3670 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3671 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3672 }; 3673 3674 #define CONNECTX_4_CURR_MAX_MINOR 99 3675 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3676 3677 /* 3678 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3679 * If so, don't mark it as broken. 3680 * FW minor > 99 means older FW version format and no INTx masking support. 3681 * FW minor < 14 means new FW version format and no INTx masking support. 3682 */ 3683 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3684 { 3685 __be32 __iomem *fw_ver; 3686 u16 fw_major; 3687 u16 fw_minor; 3688 u16 fw_subminor; 3689 u32 fw_maj_min; 3690 u32 fw_sub_min; 3691 int i; 3692 3693 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3694 if (pdev->device == mellanox_broken_intx_devs[i]) { 3695 pdev->broken_intx_masking = 1; 3696 return; 3697 } 3698 } 3699 3700 /* 3701 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3702 * support so shouldn't be checked further 3703 */ 3704 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3705 return; 3706 3707 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3708 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3709 return; 3710 3711 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3712 if (pci_enable_device_mem(pdev)) { 3713 pci_warn(pdev, "Can't enable device memory\n"); 3714 return; 3715 } 3716 3717 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3718 if (!fw_ver) { 3719 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3720 goto out; 3721 } 3722 3723 /* Reading from resource space should be 32b aligned */ 3724 fw_maj_min = ioread32be(fw_ver); 3725 fw_sub_min = ioread32be(fw_ver + 1); 3726 fw_major = fw_maj_min & 0xffff; 3727 fw_minor = fw_maj_min >> 16; 3728 fw_subminor = fw_sub_min & 0xffff; 3729 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3730 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3731 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3732 fw_major, fw_minor, fw_subminor, pdev->device == 3733 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3734 pdev->broken_intx_masking = 1; 3735 } 3736 3737 iounmap(fw_ver); 3738 3739 out: 3740 pci_disable_device(pdev); 3741 } 3742 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3743 mellanox_check_broken_intx_masking); 3744 3745 static void quirk_no_bus_reset(struct pci_dev *dev) 3746 { 3747 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3748 } 3749 3750 /* 3751 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3752 * prevented for those affected devices. 3753 */ 3754 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) 3755 { 3756 if ((dev->device & 0xffc0) == 0x2340) 3757 quirk_no_bus_reset(dev); 3758 } 3759 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 3760 quirk_nvidia_no_bus_reset); 3761 3762 /* 3763 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3764 * The device will throw a Link Down error on AER-capable systems and 3765 * regardless of AER, config space of the device is never accessible again 3766 * and typically causes the system to hang or reset when access is attempted. 3767 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ 3768 */ 3769 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3770 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3771 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3772 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3773 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); 3774 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); 3775 3776 /* 3777 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3778 * reset when used with certain child devices. After the reset, config 3779 * accesses to the child may fail. 3780 */ 3781 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3782 3783 /* 3784 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS 3785 * automatically disables LTSSM when Secondary Bus Reset is received and 3786 * the device stops working. Prevent bus reset for these devices. With 3787 * this change, the device can be assigned to VMs with VFIO, but it will 3788 * leak state between VMs. Reference 3789 * https://e2e.ti.com/support/processors/f/791/t/954382 3790 */ 3791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3792 3793 static void quirk_no_pm_reset(struct pci_dev *dev) 3794 { 3795 /* 3796 * We can't do a bus reset on root bus devices, but an ineffective 3797 * PM reset may be better than nothing. 3798 */ 3799 if (!pci_is_root_bus(dev->bus)) 3800 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3801 } 3802 3803 /* 3804 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3805 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3806 * to have no effect on the device: it retains the framebuffer contents and 3807 * monitor sync. Advertising this support makes other layers, like VFIO, 3808 * assume pci_reset_function() is viable for this device. Mark it as 3809 * unavailable to skip it when testing reset methods. 3810 */ 3811 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3812 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3813 3814 /* 3815 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset 3816 * (i.e., they advertise NoSoftRst-). However, this transition does not have 3817 * any effect on the device: It continues to be operational and network ports 3818 * remain up. Advertising this support makes it seem as if a PM reset is viable 3819 * for these devices. Mark it as unavailable to skip it when testing reset 3820 * methods. 3821 */ 3822 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset); 3823 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset); 3824 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset); 3825 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset); 3826 3827 /* 3828 * Thunderbolt controllers with broken MSI hotplug signaling: 3829 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3830 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3831 */ 3832 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3833 { 3834 if (pdev->is_hotplug_bridge && 3835 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3836 pdev->revision <= 1)) 3837 pdev->no_msi = 1; 3838 } 3839 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3840 quirk_thunderbolt_hotplug_msi); 3841 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3842 quirk_thunderbolt_hotplug_msi); 3843 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3844 quirk_thunderbolt_hotplug_msi); 3845 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3846 quirk_thunderbolt_hotplug_msi); 3847 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3848 quirk_thunderbolt_hotplug_msi); 3849 3850 #ifdef CONFIG_ACPI 3851 /* 3852 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3853 * 3854 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3855 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3856 * be present after resume if a device was plugged in before suspend. 3857 * 3858 * The Thunderbolt controller consists of a PCIe switch with downstream 3859 * bridges leading to the NHI and to the tunnel PCI bridges. 3860 * 3861 * This quirk cuts power to the whole chip. Therefore we have to apply it 3862 * during suspend_noirq of the upstream bridge. 3863 * 3864 * Power is automagically restored before resume. No action is needed. 3865 */ 3866 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3867 { 3868 acpi_handle bridge, SXIO, SXFP, SXLV; 3869 3870 if (!x86_apple_machine) 3871 return; 3872 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3873 return; 3874 3875 /* 3876 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. 3877 * We don't know how to turn it back on again, but firmware does, 3878 * so we can only use SXIO/SXFP/SXLF if we're suspending via 3879 * firmware. 3880 */ 3881 if (!pm_suspend_via_firmware()) 3882 return; 3883 3884 bridge = ACPI_HANDLE(&dev->dev); 3885 if (!bridge) 3886 return; 3887 3888 /* 3889 * SXIO and SXLV are present only on machines requiring this quirk. 3890 * Thunderbolt bridges in external devices might have the same 3891 * device ID as those on the host, but they will not have the 3892 * associated ACPI methods. This implicitly checks that we are at 3893 * the right bridge. 3894 */ 3895 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3896 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3897 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3898 return; 3899 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3900 3901 /* magic sequence */ 3902 acpi_execute_simple_method(SXIO, NULL, 1); 3903 acpi_execute_simple_method(SXFP, NULL, 0); 3904 msleep(300); 3905 acpi_execute_simple_method(SXLV, NULL, 0); 3906 acpi_execute_simple_method(SXIO, NULL, 0); 3907 acpi_execute_simple_method(SXLV, NULL, 0); 3908 } 3909 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3910 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3911 quirk_apple_poweroff_thunderbolt); 3912 #endif 3913 3914 /* 3915 * Following are device-specific reset methods which can be used to 3916 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3917 * not available. 3918 */ 3919 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) 3920 { 3921 /* 3922 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3923 * 3924 * The 82599 supports FLR on VFs, but FLR support is reported only 3925 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3926 * Thus we must call pcie_flr() directly without first checking if it is 3927 * supported. 3928 */ 3929 if (!probe) 3930 pcie_flr(dev); 3931 return 0; 3932 } 3933 3934 #define SOUTH_CHICKEN2 0xc2004 3935 #define PCH_PP_STATUS 0xc7200 3936 #define PCH_PP_CONTROL 0xc7204 3937 #define MSG_CTL 0x45010 3938 #define NSDE_PWR_STATE 0xd0100 3939 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3940 3941 static int reset_ivb_igd(struct pci_dev *dev, bool probe) 3942 { 3943 void __iomem *mmio_base; 3944 unsigned long timeout; 3945 u32 val; 3946 3947 if (probe) 3948 return 0; 3949 3950 mmio_base = pci_iomap(dev, 0, 0); 3951 if (!mmio_base) 3952 return -ENOMEM; 3953 3954 iowrite32(0x00000002, mmio_base + MSG_CTL); 3955 3956 /* 3957 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3958 * driver loaded sets the right bits. However, this's a reset and 3959 * the bits have been set by i915 previously, so we clobber 3960 * SOUTH_CHICKEN2 register directly here. 3961 */ 3962 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3963 3964 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3965 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3966 3967 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3968 do { 3969 val = ioread32(mmio_base + PCH_PP_STATUS); 3970 if ((val & 0xb0000000) == 0) 3971 goto reset_complete; 3972 msleep(10); 3973 } while (time_before(jiffies, timeout)); 3974 pci_warn(dev, "timeout during reset\n"); 3975 3976 reset_complete: 3977 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 3978 3979 pci_iounmap(dev, mmio_base); 3980 return 0; 3981 } 3982 3983 /* Device-specific reset method for Chelsio T4-based adapters */ 3984 static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) 3985 { 3986 u16 old_command; 3987 u16 msix_flags; 3988 3989 /* 3990 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 3991 * that we have no device-specific reset method. 3992 */ 3993 if ((dev->device & 0xf000) != 0x4000) 3994 return -ENOTTY; 3995 3996 /* 3997 * If this is the "probe" phase, return 0 indicating that we can 3998 * reset this device. 3999 */ 4000 if (probe) 4001 return 0; 4002 4003 /* 4004 * T4 can wedge if there are DMAs in flight within the chip and Bus 4005 * Master has been disabled. We need to have it on till the Function 4006 * Level Reset completes. (BUS_MASTER is disabled in 4007 * pci_reset_function()). 4008 */ 4009 pci_read_config_word(dev, PCI_COMMAND, &old_command); 4010 pci_write_config_word(dev, PCI_COMMAND, 4011 old_command | PCI_COMMAND_MASTER); 4012 4013 /* 4014 * Perform the actual device function reset, saving and restoring 4015 * configuration information around the reset. 4016 */ 4017 pci_save_state(dev); 4018 4019 /* 4020 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 4021 * are disabled when an MSI-X interrupt message needs to be delivered. 4022 * So we briefly re-enable MSI-X interrupts for the duration of the 4023 * FLR. The pci_restore_state() below will restore the original 4024 * MSI-X state. 4025 */ 4026 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 4027 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 4028 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 4029 msix_flags | 4030 PCI_MSIX_FLAGS_ENABLE | 4031 PCI_MSIX_FLAGS_MASKALL); 4032 4033 pcie_flr(dev); 4034 4035 /* 4036 * Restore the configuration information (BAR values, etc.) including 4037 * the original PCI Configuration Space Command word, and return 4038 * success. 4039 */ 4040 pci_restore_state(dev); 4041 pci_write_config_word(dev, PCI_COMMAND, old_command); 4042 return 0; 4043 } 4044 4045 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 4046 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 4047 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 4048 4049 /* 4050 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 4051 * FLR where config space reads from the device return -1. We seem to be 4052 * able to avoid this condition if we disable the NVMe controller prior to 4053 * FLR. This quirk is generic for any NVMe class device requiring similar 4054 * assistance to quiesce the device prior to FLR. 4055 * 4056 * NVMe specification: https://nvmexpress.org/resources/specifications/ 4057 * Revision 1.0e: 4058 * Chapter 2: Required and optional PCI config registers 4059 * Chapter 3: NVMe control registers 4060 * Chapter 7.3: Reset behavior 4061 */ 4062 static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) 4063 { 4064 void __iomem *bar; 4065 u16 cmd; 4066 u32 cfg; 4067 4068 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 4069 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) 4070 return -ENOTTY; 4071 4072 if (probe) 4073 return 0; 4074 4075 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 4076 if (!bar) 4077 return -ENOTTY; 4078 4079 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4080 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 4081 4082 cfg = readl(bar + NVME_REG_CC); 4083 4084 /* Disable controller if enabled */ 4085 if (cfg & NVME_CC_ENABLE) { 4086 u32 cap = readl(bar + NVME_REG_CAP); 4087 unsigned long timeout; 4088 4089 /* 4090 * Per nvme_disable_ctrl() skip shutdown notification as it 4091 * could complete commands to the admin queue. We only intend 4092 * to quiesce the device before reset. 4093 */ 4094 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 4095 4096 writel(cfg, bar + NVME_REG_CC); 4097 4098 /* 4099 * Some controllers require an additional delay here, see 4100 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 4101 * supported by this quirk. 4102 */ 4103 4104 /* Cap register provides max timeout in 500ms increments */ 4105 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 4106 4107 for (;;) { 4108 u32 status = readl(bar + NVME_REG_CSTS); 4109 4110 /* Ready status becomes zero on disable complete */ 4111 if (!(status & NVME_CSTS_RDY)) 4112 break; 4113 4114 msleep(100); 4115 4116 if (time_after(jiffies, timeout)) { 4117 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 4118 break; 4119 } 4120 } 4121 } 4122 4123 pci_iounmap(dev, bar); 4124 4125 pcie_flr(dev); 4126 4127 return 0; 4128 } 4129 4130 /* 4131 * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will 4132 * timeout waiting for ready status to change after NVMe enable if the driver 4133 * starts interacting with the device too soon after FLR. A 250ms delay after 4134 * FLR has heuristically proven to produce reliably working results for device 4135 * assignment cases. 4136 */ 4137 static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) 4138 { 4139 if (probe) 4140 return pcie_reset_flr(dev, PCI_RESET_PROBE); 4141 4142 pcie_reset_flr(dev, PCI_RESET_DO_RESET); 4143 4144 msleep(250); 4145 4146 return 0; 4147 } 4148 4149 #define PCI_DEVICE_ID_HINIC_VF 0x375E 4150 #define HINIC_VF_FLR_TYPE 0x1000 4151 #define HINIC_VF_FLR_CAP_BIT (1UL << 30) 4152 #define HINIC_VF_OP 0xE80 4153 #define HINIC_VF_FLR_PROC_BIT (1UL << 18) 4154 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ 4155 4156 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ 4157 static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) 4158 { 4159 unsigned long timeout; 4160 void __iomem *bar; 4161 u32 val; 4162 4163 if (probe) 4164 return 0; 4165 4166 bar = pci_iomap(pdev, 0, 0); 4167 if (!bar) 4168 return -ENOTTY; 4169 4170 /* Get and check firmware capabilities */ 4171 val = ioread32be(bar + HINIC_VF_FLR_TYPE); 4172 if (!(val & HINIC_VF_FLR_CAP_BIT)) { 4173 pci_iounmap(pdev, bar); 4174 return -ENOTTY; 4175 } 4176 4177 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ 4178 val = ioread32be(bar + HINIC_VF_OP); 4179 val = val | HINIC_VF_FLR_PROC_BIT; 4180 iowrite32be(val, bar + HINIC_VF_OP); 4181 4182 pcie_flr(pdev); 4183 4184 /* 4185 * The device must recapture its Bus and Device Numbers after FLR 4186 * in order generate Completions. Issue a config write to let the 4187 * device capture this information. 4188 */ 4189 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); 4190 4191 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ 4192 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); 4193 do { 4194 val = ioread32be(bar + HINIC_VF_OP); 4195 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4196 goto reset_complete; 4197 msleep(20); 4198 } while (time_before(jiffies, timeout)); 4199 4200 val = ioread32be(bar + HINIC_VF_OP); 4201 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4202 goto reset_complete; 4203 4204 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); 4205 4206 reset_complete: 4207 pci_iounmap(pdev, bar); 4208 4209 return 0; 4210 } 4211 4212 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 4213 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 4214 reset_intel_82599_sfp_virtfn }, 4215 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 4216 reset_ivb_igd }, 4217 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 4218 reset_ivb_igd }, 4219 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 4220 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 4221 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, 4222 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr }, 4223 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4224 reset_chelsio_generic_dev }, 4225 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, 4226 reset_hinic_vf_dev }, 4227 { 0 } 4228 }; 4229 4230 /* 4231 * These device-specific reset methods are here rather than in a driver 4232 * because when a host assigns a device to a guest VM, the host may need 4233 * to reset the device but probably doesn't have a driver for it. 4234 */ 4235 int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 4236 { 4237 const struct pci_dev_reset_methods *i; 4238 4239 for (i = pci_dev_reset_methods; i->reset; i++) { 4240 if ((i->vendor == dev->vendor || 4241 i->vendor == (u16)PCI_ANY_ID) && 4242 (i->device == dev->device || 4243 i->device == (u16)PCI_ANY_ID)) 4244 return i->reset(dev, probe); 4245 } 4246 4247 return -ENOTTY; 4248 } 4249 4250 static void quirk_dma_func0_alias(struct pci_dev *dev) 4251 { 4252 if (PCI_FUNC(dev->devfn) != 0) 4253 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); 4254 } 4255 4256 /* 4257 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 4258 * 4259 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 4260 */ 4261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 4262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 4263 4264 /* Some Glenfly chips use function 0 as the PCIe Requester ID for DMA */ 4265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d40, quirk_dma_func0_alias); 4266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d41, quirk_dma_func0_alias); 4267 4268 static void quirk_dma_func1_alias(struct pci_dev *dev) 4269 { 4270 if (PCI_FUNC(dev->devfn) != 1) 4271 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); 4272 } 4273 4274 /* 4275 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 4276 * SKUs function 1 is present and is a legacy IDE controller, in other 4277 * SKUs this function is not present, making this a ghost requester. 4278 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 4279 */ 4280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 4281 quirk_dma_func1_alias); 4282 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 4283 quirk_dma_func1_alias); 4284 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */ 4285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, 4286 quirk_dma_func1_alias); 4287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 4288 quirk_dma_func1_alias); 4289 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 4290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 4291 quirk_dma_func1_alias); 4292 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, 4293 quirk_dma_func1_alias); 4294 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 4295 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 4296 quirk_dma_func1_alias); 4297 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 4298 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 4299 quirk_dma_func1_alias); 4300 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 4301 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 4302 quirk_dma_func1_alias); 4303 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 4304 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 4305 quirk_dma_func1_alias); 4306 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4308 quirk_dma_func1_alias); 4309 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4310 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4311 quirk_dma_func1_alias); 4312 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4313 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4314 quirk_dma_func1_alias); 4315 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 4316 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 4317 quirk_dma_func1_alias); 4318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, 4319 quirk_dma_func1_alias); 4320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 4321 quirk_dma_func1_alias); 4322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 4323 quirk_dma_func1_alias); 4324 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 4325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 4326 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 4327 quirk_dma_func1_alias); 4328 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 4329 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 4330 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 4331 quirk_dma_func1_alias); 4332 4333 /* 4334 * Some devices DMA with the wrong devfn, not just the wrong function. 4335 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 4336 * the alias is "fixed" and independent of the device devfn. 4337 * 4338 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 4339 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 4340 * single device on the secondary bus. In reality, the single exposed 4341 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 4342 * that provides a bridge to the internal bus of the I/O processor. The 4343 * controller supports private devices, which can be hidden from PCI config 4344 * space. In the case of the Adaptec 3405, a private device at 01.0 4345 * appears to be the DMA engine, which therefore needs to become a DMA 4346 * alias for the device. 4347 */ 4348 static const struct pci_device_id fixed_dma_alias_tbl[] = { 4349 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4350 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 4351 .driver_data = PCI_DEVFN(1, 0) }, 4352 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4353 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 4354 .driver_data = PCI_DEVFN(1, 0) }, 4355 { 0 } 4356 }; 4357 4358 static void quirk_fixed_dma_alias(struct pci_dev *dev) 4359 { 4360 const struct pci_device_id *id; 4361 4362 id = pci_match_id(fixed_dma_alias_tbl, dev); 4363 if (id) 4364 pci_add_dma_alias(dev, id->driver_data, 1); 4365 } 4366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 4367 4368 /* 4369 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 4370 * using the wrong DMA alias for the device. Some of these devices can be 4371 * used as either forward or reverse bridges, so we need to test whether the 4372 * device is operating in the correct mode. We could probably apply this 4373 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 4374 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 4375 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 4376 */ 4377 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 4378 { 4379 if (!pci_is_root_bus(pdev->bus) && 4380 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4381 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 4382 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 4383 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 4384 } 4385 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 4386 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 4387 quirk_use_pcie_bridge_dma_alias); 4388 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 4389 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 4390 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 4391 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 4392 /* ITE 8893 has the same problem as the 8892 */ 4393 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 4394 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 4395 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 4396 4397 /* 4398 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 4399 * be added as aliases to the DMA device in order to allow buffer access 4400 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 4401 * programmed in the EEPROM. 4402 */ 4403 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 4404 { 4405 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); 4406 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); 4407 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); 4408 } 4409 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 4410 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 4411 4412 /* 4413 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices 4414 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). 4415 * 4416 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access 4417 * when IOMMU is enabled. These aliases allow computational unit access to 4418 * host memory. These aliases mark the whole VCA device as one IOMMU 4419 * group. 4420 * 4421 * All possible slot numbers (0x20) are used, since we are unable to tell 4422 * what slot is used on other side. This quirk is intended for both host 4423 * and computational unit sides. The VCA devices have up to five functions 4424 * (four for DMA channels and one additional). 4425 */ 4426 static void quirk_pex_vca_alias(struct pci_dev *pdev) 4427 { 4428 const unsigned int num_pci_slots = 0x20; 4429 unsigned int slot; 4430 4431 for (slot = 0; slot < num_pci_slots; slot++) 4432 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); 4433 } 4434 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); 4435 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); 4436 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); 4437 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); 4438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); 4439 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); 4440 4441 /* 4442 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 4443 * associated not at the root bus, but at a bridge below. This quirk avoids 4444 * generating invalid DMA aliases. 4445 */ 4446 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4447 { 4448 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4449 } 4450 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4451 quirk_bridge_cavm_thrx2_pcie_root); 4452 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4453 quirk_bridge_cavm_thrx2_pcie_root); 4454 4455 /* 4456 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4457 * class code. Fix it. 4458 */ 4459 static void quirk_tw686x_class(struct pci_dev *pdev) 4460 { 4461 u32 class = pdev->class; 4462 4463 /* Use "Multimedia controller" class */ 4464 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4465 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4466 class, pdev->class); 4467 } 4468 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4469 quirk_tw686x_class); 4470 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4471 quirk_tw686x_class); 4472 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4473 quirk_tw686x_class); 4474 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4475 quirk_tw686x_class); 4476 4477 /* 4478 * Some devices have problems with Transaction Layer Packets with the Relaxed 4479 * Ordering Attribute set. Such devices should mark themselves and other 4480 * device drivers should check before sending TLPs with RO set. 4481 */ 4482 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4483 { 4484 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4485 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4486 } 4487 4488 /* 4489 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4490 * Complex have a Flow Control Credit issue which can cause performance 4491 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4492 */ 4493 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4494 quirk_relaxedordering_disable); 4495 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4496 quirk_relaxedordering_disable); 4497 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4498 quirk_relaxedordering_disable); 4499 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4500 quirk_relaxedordering_disable); 4501 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4502 quirk_relaxedordering_disable); 4503 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4504 quirk_relaxedordering_disable); 4505 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4506 quirk_relaxedordering_disable); 4507 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4508 quirk_relaxedordering_disable); 4509 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4510 quirk_relaxedordering_disable); 4511 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4512 quirk_relaxedordering_disable); 4513 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4514 quirk_relaxedordering_disable); 4515 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4516 quirk_relaxedordering_disable); 4517 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4518 quirk_relaxedordering_disable); 4519 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4520 quirk_relaxedordering_disable); 4521 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4522 quirk_relaxedordering_disable); 4523 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4524 quirk_relaxedordering_disable); 4525 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4526 quirk_relaxedordering_disable); 4527 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4528 quirk_relaxedordering_disable); 4529 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4530 quirk_relaxedordering_disable); 4531 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4532 quirk_relaxedordering_disable); 4533 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4534 quirk_relaxedordering_disable); 4535 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4536 quirk_relaxedordering_disable); 4537 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4538 quirk_relaxedordering_disable); 4539 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4540 quirk_relaxedordering_disable); 4541 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4542 quirk_relaxedordering_disable); 4543 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4544 quirk_relaxedordering_disable); 4545 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4546 quirk_relaxedordering_disable); 4547 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4548 quirk_relaxedordering_disable); 4549 4550 /* 4551 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4552 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4553 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4554 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4555 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4556 * November 10, 2010). As a result, on this platform we can't use Relaxed 4557 * Ordering for Upstream TLPs. 4558 */ 4559 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4560 quirk_relaxedordering_disable); 4561 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4562 quirk_relaxedordering_disable); 4563 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4564 quirk_relaxedordering_disable); 4565 4566 /* 4567 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4568 * values for the Attribute as were supplied in the header of the 4569 * corresponding Request, except as explicitly allowed when IDO is used." 4570 * 4571 * If a non-compliant device generates a completion with a different 4572 * attribute than the request, the receiver may accept it (which itself 4573 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4574 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4575 * device access timeout. 4576 * 4577 * If the non-compliant device generates completions with zero attributes 4578 * (instead of copying the attributes from the request), we can work around 4579 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4580 * upstream devices so they always generate requests with zero attributes. 4581 * 4582 * This affects other devices under the same Root Port, but since these 4583 * attributes are performance hints, there should be no functional problem. 4584 * 4585 * Note that Configuration Space accesses are never supposed to have TLP 4586 * Attributes, so we're safe waiting till after any Configuration Space 4587 * accesses to do the Root Port fixup. 4588 */ 4589 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4590 { 4591 struct pci_dev *root_port = pcie_find_root_port(pdev); 4592 4593 if (!root_port) { 4594 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4595 return; 4596 } 4597 4598 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4599 dev_name(&pdev->dev)); 4600 pcie_capability_clear_word(root_port, PCI_EXP_DEVCTL, 4601 PCI_EXP_DEVCTL_RELAX_EN | 4602 PCI_EXP_DEVCTL_NOSNOOP_EN); 4603 } 4604 4605 /* 4606 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4607 * Completion it generates. 4608 */ 4609 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4610 { 4611 /* 4612 * This mask/compare operation selects for Physical Function 4 on a 4613 * T5. We only need to fix up the Root Port once for any of the 4614 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4615 * 0x54xx so we use that one. 4616 */ 4617 if ((pdev->device & 0xff00) == 0x5400) 4618 quirk_disable_root_port_attributes(pdev); 4619 } 4620 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4621 quirk_chelsio_T5_disable_root_port_attributes); 4622 4623 /* 4624 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided 4625 * by a device 4626 * @acs_ctrl_req: Bitmask of desired ACS controls 4627 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by 4628 * the hardware design 4629 * 4630 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included 4631 * in @acs_ctrl_ena, i.e., the device provides all the access controls the 4632 * caller desires. Return 0 otherwise. 4633 */ 4634 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) 4635 { 4636 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) 4637 return 1; 4638 return 0; 4639 } 4640 4641 /* 4642 * AMD has indicated that the devices below do not support peer-to-peer 4643 * in any system where they are found in the southbridge with an AMD 4644 * IOMMU in the system. Multifunction devices that do not support 4645 * peer-to-peer between functions can claim to support a subset of ACS. 4646 * Such devices effectively enable request redirect (RR) and completion 4647 * redirect (CR) since all transactions are redirected to the upstream 4648 * root complex. 4649 * 4650 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ 4651 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ 4652 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ 4653 * 4654 * 1002:4385 SBx00 SMBus Controller 4655 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4656 * 1002:4383 SBx00 Azalia (Intel HDA) 4657 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4658 * 1002:4384 SBx00 PCI to PCI Bridge 4659 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4660 * 4661 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4662 * 4663 * 1022:780f [AMD] FCH PCI Bridge 4664 * 1022:7809 [AMD] FCH USB OHCI Controller 4665 */ 4666 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4667 { 4668 #ifdef CONFIG_ACPI 4669 struct acpi_table_header *header = NULL; 4670 acpi_status status; 4671 4672 /* Targeting multifunction devices on the SB (appears on root bus) */ 4673 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4674 return -ENODEV; 4675 4676 /* The IVRS table describes the AMD IOMMU */ 4677 status = acpi_get_table("IVRS", 0, &header); 4678 if (ACPI_FAILURE(status)) 4679 return -ENODEV; 4680 4681 acpi_put_table(header); 4682 4683 /* Filter out flags not applicable to multifunction */ 4684 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4685 4686 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); 4687 #else 4688 return -ENODEV; 4689 #endif 4690 } 4691 4692 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4693 { 4694 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4695 return false; 4696 4697 switch (dev->device) { 4698 /* 4699 * Effectively selects all downstream ports for whole ThunderX1 4700 * (which represents 8 SoCs). 4701 */ 4702 case 0xa000 ... 0xa7ff: /* ThunderX1 */ 4703 case 0xaf84: /* ThunderX2 */ 4704 case 0xb884: /* ThunderX3 */ 4705 return true; 4706 default: 4707 return false; 4708 } 4709 } 4710 4711 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4712 { 4713 if (!pci_quirk_cavium_acs_match(dev)) 4714 return -ENOTTY; 4715 4716 /* 4717 * Cavium Root Ports don't advertise an ACS capability. However, 4718 * the RTL internally implements similar protection as if ACS had 4719 * Source Validation, Request Redirection, Completion Redirection, 4720 * and Upstream Forwarding features enabled. Assert that the 4721 * hardware implements and enables equivalent ACS functionality for 4722 * these flags. 4723 */ 4724 return pci_acs_ctrl_enabled(acs_flags, 4725 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4726 } 4727 4728 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4729 { 4730 /* 4731 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4732 * transactions with others, allowing masking out these bits as if they 4733 * were unimplemented in the ACS capability. 4734 */ 4735 return pci_acs_ctrl_enabled(acs_flags, 4736 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4737 } 4738 4739 /* 4740 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. 4741 * But the implementation could block peer-to-peer transactions between them 4742 * and provide ACS-like functionality. 4743 */ 4744 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 4745 { 4746 if (!pci_is_pcie(dev) || 4747 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 4748 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 4749 return -ENOTTY; 4750 4751 /* 4752 * Future Zhaoxin Root Ports and Switch Downstream Ports will 4753 * implement ACS capability in accordance with the PCIe Spec. 4754 */ 4755 switch (dev->device) { 4756 case 0x0710 ... 0x071e: 4757 case 0x0721: 4758 case 0x0723 ... 0x0752: 4759 return pci_acs_ctrl_enabled(acs_flags, 4760 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4761 } 4762 4763 return false; 4764 } 4765 4766 /* 4767 * Many Intel PCH Root Ports do provide ACS-like features to disable peer 4768 * transactions and validate bus numbers in requests, but do not provide an 4769 * actual PCIe ACS capability. This is the list of device IDs known to fall 4770 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4771 */ 4772 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4773 /* Ibexpeak PCH */ 4774 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4775 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4776 /* Cougarpoint PCH */ 4777 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4778 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4779 /* Pantherpoint PCH */ 4780 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4781 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4782 /* Lynxpoint-H PCH */ 4783 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4784 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4785 /* Lynxpoint-LP PCH */ 4786 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4787 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4788 /* Wildcat PCH */ 4789 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4790 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4791 /* Patsburg (X79) PCH */ 4792 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4793 /* Wellsburg (X99) PCH */ 4794 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4795 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4796 /* Lynx Point (9 series) PCH */ 4797 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4798 }; 4799 4800 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4801 { 4802 int i; 4803 4804 /* Filter out a few obvious non-matches first */ 4805 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4806 return false; 4807 4808 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4809 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4810 return true; 4811 4812 return false; 4813 } 4814 4815 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4816 { 4817 if (!pci_quirk_intel_pch_acs_match(dev)) 4818 return -ENOTTY; 4819 4820 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) 4821 return pci_acs_ctrl_enabled(acs_flags, 4822 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4823 4824 return pci_acs_ctrl_enabled(acs_flags, 0); 4825 } 4826 4827 /* 4828 * These QCOM Root Ports do provide ACS-like features to disable peer 4829 * transactions and validate bus numbers in requests, but do not provide an 4830 * actual PCIe ACS capability. Hardware supports source validation but it 4831 * will report the issue as Completer Abort instead of ACS Violation. 4832 * Hardware doesn't support peer-to-peer and each Root Port is a Root 4833 * Complex with unique segment numbers. It is not possible for one Root 4834 * Port to pass traffic to another Root Port. All PCIe transactions are 4835 * terminated inside the Root Port. 4836 */ 4837 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4838 { 4839 return pci_acs_ctrl_enabled(acs_flags, 4840 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4841 } 4842 4843 /* 4844 * Each of these NXP Root Ports is in a Root Complex with a unique segment 4845 * number and does provide isolation features to disable peer transactions 4846 * and validate bus numbers in requests, but does not provide an ACS 4847 * capability. 4848 */ 4849 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) 4850 { 4851 return pci_acs_ctrl_enabled(acs_flags, 4852 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4853 } 4854 4855 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) 4856 { 4857 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4858 return -ENOTTY; 4859 4860 /* 4861 * Amazon's Annapurna Labs root ports don't include an ACS capability, 4862 * but do include ACS-like functionality. The hardware doesn't support 4863 * peer-to-peer transactions via the root port and each has a unique 4864 * segment number. 4865 * 4866 * Additionally, the root ports cannot send traffic to each other. 4867 */ 4868 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4869 4870 return acs_flags ? 0 : 1; 4871 } 4872 4873 /* 4874 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4875 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4876 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4877 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4878 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4879 * control register is at offset 8 instead of 6 and we should probably use 4880 * dword accesses to them. This applies to the following PCI Device IDs, as 4881 * found in volume 1 of the datasheet[2]: 4882 * 4883 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4884 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4885 * 4886 * N.B. This doesn't fix what lspci shows. 4887 * 4888 * The 100 series chipset specification update includes this as errata #23[3]. 4889 * 4890 * The 200 series chipset (Union Point) has the same bug according to the 4891 * specification update (Intel 200 Series Chipset Family Platform Controller 4892 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4893 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4894 * chipset include: 4895 * 4896 * 0xa290-0xa29f PCI Express Root port #{0-16} 4897 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4898 * 4899 * Mobile chipsets are also affected, 7th & 8th Generation 4900 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4901 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4902 * Processor Family I/O for U Quad Core Platforms Specification Update, 4903 * August 2017, Revision 002, Document#: 334660-002)[6] 4904 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4905 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4906 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4907 * 4908 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4909 * 4910 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4911 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4912 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4913 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4914 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4915 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4916 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4917 */ 4918 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4919 { 4920 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4921 return false; 4922 4923 switch (dev->device) { 4924 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4925 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4926 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4927 return true; 4928 } 4929 4930 return false; 4931 } 4932 4933 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4934 4935 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4936 { 4937 int pos; 4938 u32 cap, ctrl; 4939 4940 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4941 return -ENOTTY; 4942 4943 pos = dev->acs_cap; 4944 if (!pos) 4945 return -ENOTTY; 4946 4947 /* see pci_acs_flags_enabled() */ 4948 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 4949 acs_flags &= (cap | PCI_ACS_EC); 4950 4951 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 4952 4953 return pci_acs_ctrl_enabled(acs_flags, ctrl); 4954 } 4955 4956 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 4957 { 4958 /* 4959 * SV, TB, and UF are not relevant to multifunction endpoints. 4960 * 4961 * Multifunction devices are only required to implement RR, CR, and DT 4962 * in their ACS capability if they support peer-to-peer transactions. 4963 * Devices matching this quirk have been verified by the vendor to not 4964 * perform peer-to-peer with other functions, allowing us to mask out 4965 * these bits as if they were unimplemented in the ACS capability. 4966 */ 4967 return pci_acs_ctrl_enabled(acs_flags, 4968 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 4969 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 4970 } 4971 4972 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) 4973 { 4974 /* 4975 * Intel RCiEP's are required to allow p2p only on translated 4976 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, 4977 * "Root-Complex Peer to Peer Considerations". 4978 */ 4979 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) 4980 return -ENOTTY; 4981 4982 return pci_acs_ctrl_enabled(acs_flags, 4983 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4984 } 4985 4986 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) 4987 { 4988 /* 4989 * iProc PAXB Root Ports don't advertise an ACS capability, but 4990 * they do not allow peer-to-peer transactions between Root Ports. 4991 * Allow each Root Port to be in a separate IOMMU group by masking 4992 * SV/RR/CR/UF bits. 4993 */ 4994 return pci_acs_ctrl_enabled(acs_flags, 4995 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4996 } 4997 4998 /* 4999 * Wangxun 40G/25G/10G/1G NICs have no ACS capability, but on 5000 * multi-function devices, the hardware isolates the functions by 5001 * directing all peer-to-peer traffic upstream as though PCI_ACS_RR and 5002 * PCI_ACS_CR were set. 5003 * SFxxx 1G NICs(em). 5004 * RP1000/RP2000 10G NICs(sp). 5005 * FF5xxx 40G/25G/10G NICs(aml). 5006 */ 5007 static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) 5008 { 5009 switch (dev->device) { 5010 case 0x0100 ... 0x010F: /* EM */ 5011 case 0x1001: case 0x2001: /* SP */ 5012 case 0x5010: case 0x5025: case 0x5040: /* AML */ 5013 case 0x5110: case 0x5125: case 0x5140: /* AML */ 5014 return pci_acs_ctrl_enabled(acs_flags, 5015 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5016 } 5017 5018 return false; 5019 } 5020 5021 static const struct pci_dev_acs_enabled { 5022 u16 vendor; 5023 u16 device; 5024 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 5025 } pci_dev_acs_enabled[] = { 5026 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 5027 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 5028 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 5029 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 5030 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 5031 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 5032 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 5033 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 5034 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 5035 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 5036 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 5037 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 5038 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 5039 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 5040 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 5041 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 5042 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 5043 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 5044 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 5045 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 5046 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 5047 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 5048 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 5049 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 5050 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 5051 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 5052 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 5053 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 5054 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 5055 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 5056 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 5057 /* 82580 */ 5058 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 5059 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 5060 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 5061 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 5062 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 5063 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 5064 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 5065 /* 82576 */ 5066 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 5067 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 5068 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 5069 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 5070 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 5071 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 5072 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 5073 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 5074 /* 82575 */ 5075 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 5076 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 5077 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 5078 /* I350 */ 5079 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 5080 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 5081 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 5082 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 5083 /* 82571 (Quads omitted due to non-ACS switch) */ 5084 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 5085 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 5086 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 5087 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 5088 /* I219 */ 5089 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 5090 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 5091 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, 5092 /* QCOM QDF2xxx root ports */ 5093 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 5094 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 5095 /* QCOM SA8775P root port */ 5096 { PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs }, 5097 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 5098 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 5099 /* Intel PCH root ports */ 5100 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 5101 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 5102 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 5103 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 5104 /* Cavium ThunderX */ 5105 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 5106 /* Cavium multi-function devices */ 5107 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, 5108 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, 5109 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, 5110 /* APM X-Gene */ 5111 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 5112 /* Ampere Computing */ 5113 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 5114 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 5115 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 5116 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 5117 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 5118 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 5119 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 5120 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 5121 /* Broadcom multi-function device */ 5122 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, 5123 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs }, 5124 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs }, 5125 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs }, 5126 { PCI_VENDOR_ID_BROADCOM, 0x1760, pci_quirk_mf_endpoint_acs }, 5127 { PCI_VENDOR_ID_BROADCOM, 0x1761, pci_quirk_mf_endpoint_acs }, 5128 { PCI_VENDOR_ID_BROADCOM, 0x1762, pci_quirk_mf_endpoint_acs }, 5129 { PCI_VENDOR_ID_BROADCOM, 0x1763, pci_quirk_mf_endpoint_acs }, 5130 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 5131 /* Amazon Annapurna Labs */ 5132 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, 5133 /* Zhaoxin multi-function devices */ 5134 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, 5135 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, 5136 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, 5137 /* NXP root ports, xx=16, 12, or 08 cores */ 5138 /* LX2xx0A : without security features + CAN-FD */ 5139 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, 5140 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, 5141 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, 5142 /* LX2xx0C : security features + CAN-FD */ 5143 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, 5144 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, 5145 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, 5146 /* LX2xx0E : security features + CAN */ 5147 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, 5148 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, 5149 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, 5150 /* LX2xx0N : without security features + CAN */ 5151 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, 5152 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, 5153 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, 5154 /* LX2xx2A : without security features + CAN-FD */ 5155 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, 5156 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, 5157 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, 5158 /* LX2xx2C : security features + CAN-FD */ 5159 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, 5160 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, 5161 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, 5162 /* LX2xx2E : security features + CAN */ 5163 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, 5164 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, 5165 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, 5166 /* LX2xx2N : without security features + CAN */ 5167 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, 5168 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, 5169 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, 5170 /* Zhaoxin Root/Downstream Ports */ 5171 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, 5172 /* Wangxun nics */ 5173 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs }, 5174 { 0 } 5175 }; 5176 5177 /* 5178 * pci_dev_specific_acs_enabled - check whether device provides ACS controls 5179 * @dev: PCI device 5180 * @acs_flags: Bitmask of desired ACS controls 5181 * 5182 * Returns: 5183 * -ENOTTY: No quirk applies to this device; we can't tell whether the 5184 * device provides the desired controls 5185 * 0: Device does not provide all the desired controls 5186 * >0: Device provides all the controls in @acs_flags 5187 */ 5188 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 5189 { 5190 const struct pci_dev_acs_enabled *i; 5191 int ret; 5192 5193 /* 5194 * Allow devices that do not expose standard PCIe ACS capabilities 5195 * or control to indicate their support here. Multi-function express 5196 * devices which do not allow internal peer-to-peer between functions, 5197 * but do not implement PCIe ACS may wish to return true here. 5198 */ 5199 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 5200 if ((i->vendor == dev->vendor || 5201 i->vendor == (u16)PCI_ANY_ID) && 5202 (i->device == dev->device || 5203 i->device == (u16)PCI_ANY_ID)) { 5204 ret = i->acs_enabled(dev, acs_flags); 5205 if (ret >= 0) 5206 return ret; 5207 } 5208 } 5209 5210 return -ENOTTY; 5211 } 5212 5213 /* Config space offset of Root Complex Base Address register */ 5214 #define INTEL_LPC_RCBA_REG 0xf0 5215 /* 31:14 RCBA address */ 5216 #define INTEL_LPC_RCBA_MASK 0xffffc000 5217 /* RCBA Enable */ 5218 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 5219 5220 /* Backbone Scratch Pad Register */ 5221 #define INTEL_BSPR_REG 0x1104 5222 /* Backbone Peer Non-Posted Disable */ 5223 #define INTEL_BSPR_REG_BPNPD (1 << 8) 5224 /* Backbone Peer Posted Disable */ 5225 #define INTEL_BSPR_REG_BPPD (1 << 9) 5226 5227 /* Upstream Peer Decode Configuration Register */ 5228 #define INTEL_UPDCR_REG 0x1014 5229 /* 5:0 Peer Decode Enable bits */ 5230 #define INTEL_UPDCR_REG_MASK 0x3f 5231 5232 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 5233 { 5234 u32 rcba, bspr, updcr; 5235 void __iomem *rcba_mem; 5236 5237 /* 5238 * Read the RCBA register from the LPC (D31:F0). PCH root ports 5239 * are D28:F* and therefore get probed before LPC, thus we can't 5240 * use pci_get_slot()/pci_read_config_dword() here. 5241 */ 5242 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 5243 INTEL_LPC_RCBA_REG, &rcba); 5244 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 5245 return -EINVAL; 5246 5247 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, 5248 PAGE_ALIGN(INTEL_UPDCR_REG)); 5249 if (!rcba_mem) 5250 return -ENOMEM; 5251 5252 /* 5253 * The BSPR can disallow peer cycles, but it's set by soft strap and 5254 * therefore read-only. If both posted and non-posted peer cycles are 5255 * disallowed, we're ok. If either are allowed, then we need to use 5256 * the UPDCR to disable peer decodes for each port. This provides the 5257 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5258 */ 5259 bspr = readl(rcba_mem + INTEL_BSPR_REG); 5260 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 5261 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 5262 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 5263 if (updcr & INTEL_UPDCR_REG_MASK) { 5264 pci_info(dev, "Disabling UPDCR peer decodes\n"); 5265 updcr &= ~INTEL_UPDCR_REG_MASK; 5266 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 5267 } 5268 } 5269 5270 iounmap(rcba_mem); 5271 return 0; 5272 } 5273 5274 /* Miscellaneous Port Configuration register */ 5275 #define INTEL_MPC_REG 0xd8 5276 /* MPC: Invalid Receive Bus Number Check Enable */ 5277 #define INTEL_MPC_REG_IRBNCE (1 << 26) 5278 5279 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 5280 { 5281 u32 mpc; 5282 5283 /* 5284 * When enabled, the IRBNCE bit of the MPC register enables the 5285 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 5286 * ensures that requester IDs fall within the bus number range 5287 * of the bridge. Enable if not already. 5288 */ 5289 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 5290 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 5291 pci_info(dev, "Enabling MPC IRBNCE\n"); 5292 mpc |= INTEL_MPC_REG_IRBNCE; 5293 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 5294 } 5295 } 5296 5297 /* 5298 * Currently this quirk does the equivalent of 5299 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5300 * 5301 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, 5302 * if dev->external_facing || dev->untrusted 5303 */ 5304 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 5305 { 5306 if (!pci_quirk_intel_pch_acs_match(dev)) 5307 return -ENOTTY; 5308 5309 if (pci_quirk_enable_intel_lpc_acs(dev)) { 5310 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 5311 return 0; 5312 } 5313 5314 pci_quirk_enable_intel_rp_mpc_acs(dev); 5315 5316 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 5317 5318 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 5319 5320 return 0; 5321 } 5322 5323 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 5324 { 5325 int pos; 5326 u32 cap, ctrl; 5327 5328 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5329 return -ENOTTY; 5330 5331 pos = dev->acs_cap; 5332 if (!pos) 5333 return -ENOTTY; 5334 5335 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5336 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5337 5338 ctrl |= (cap & PCI_ACS_SV); 5339 ctrl |= (cap & PCI_ACS_RR); 5340 ctrl |= (cap & PCI_ACS_CR); 5341 ctrl |= (cap & PCI_ACS_UF); 5342 5343 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) 5344 ctrl |= (cap & PCI_ACS_TB); 5345 5346 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5347 5348 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 5349 5350 return 0; 5351 } 5352 5353 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 5354 { 5355 int pos; 5356 u32 cap, ctrl; 5357 5358 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5359 return -ENOTTY; 5360 5361 pos = dev->acs_cap; 5362 if (!pos) 5363 return -ENOTTY; 5364 5365 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5366 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5367 5368 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 5369 5370 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5371 5372 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 5373 5374 return 0; 5375 } 5376 5377 static const struct pci_dev_acs_ops { 5378 u16 vendor; 5379 u16 device; 5380 int (*enable_acs)(struct pci_dev *dev); 5381 int (*disable_acs_redir)(struct pci_dev *dev); 5382 } pci_dev_acs_ops[] = { 5383 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5384 .enable_acs = pci_quirk_enable_intel_pch_acs, 5385 }, 5386 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5387 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 5388 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 5389 }, 5390 }; 5391 5392 int pci_dev_specific_enable_acs(struct pci_dev *dev) 5393 { 5394 const struct pci_dev_acs_ops *p; 5395 int i, ret; 5396 5397 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5398 p = &pci_dev_acs_ops[i]; 5399 if ((p->vendor == dev->vendor || 5400 p->vendor == (u16)PCI_ANY_ID) && 5401 (p->device == dev->device || 5402 p->device == (u16)PCI_ANY_ID) && 5403 p->enable_acs) { 5404 ret = p->enable_acs(dev); 5405 if (ret >= 0) 5406 return ret; 5407 } 5408 } 5409 5410 return -ENOTTY; 5411 } 5412 5413 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 5414 { 5415 const struct pci_dev_acs_ops *p; 5416 int i, ret; 5417 5418 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5419 p = &pci_dev_acs_ops[i]; 5420 if ((p->vendor == dev->vendor || 5421 p->vendor == (u16)PCI_ANY_ID) && 5422 (p->device == dev->device || 5423 p->device == (u16)PCI_ANY_ID) && 5424 p->disable_acs_redir) { 5425 ret = p->disable_acs_redir(dev); 5426 if (ret >= 0) 5427 return ret; 5428 } 5429 } 5430 5431 return -ENOTTY; 5432 } 5433 5434 /* 5435 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 5436 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 5437 * Next Capability pointer in the MSI Capability Structure should point to 5438 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 5439 * the list. 5440 */ 5441 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 5442 { 5443 int pos, i = 0, ret; 5444 u8 next_cap; 5445 u16 reg16, *cap; 5446 struct pci_cap_saved_state *state; 5447 5448 /* Bail if the hardware bug is fixed */ 5449 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 5450 return; 5451 5452 /* Bail if MSI Capability Structure is not found for some reason */ 5453 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 5454 if (!pos) 5455 return; 5456 5457 /* 5458 * Bail if Next Capability pointer in the MSI Capability Structure 5459 * is not the expected incorrect 0x00. 5460 */ 5461 pci_read_config_byte(pdev, pos + 1, &next_cap); 5462 if (next_cap) 5463 return; 5464 5465 /* 5466 * PCIe Capability Structure is expected to be at 0x50 and should 5467 * terminate the list (Next Capability pointer is 0x00). Verify 5468 * Capability Id and Next Capability pointer is as expected. 5469 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 5470 * to correctly set kernel data structures which have already been 5471 * set incorrectly due to the hardware bug. 5472 */ 5473 pos = 0x50; 5474 pci_read_config_word(pdev, pos, ®16); 5475 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 5476 u32 status; 5477 #ifndef PCI_EXP_SAVE_REGS 5478 #define PCI_EXP_SAVE_REGS 7 5479 #endif 5480 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 5481 5482 pdev->pcie_cap = pos; 5483 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 5484 pdev->pcie_flags_reg = reg16; 5485 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 5486 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 5487 5488 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 5489 ret = pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status); 5490 if ((ret != PCIBIOS_SUCCESSFUL) || (PCI_POSSIBLE_ERROR(status))) 5491 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 5492 5493 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 5494 return; 5495 5496 /* Save PCIe cap */ 5497 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 5498 if (!state) 5499 return; 5500 5501 state->cap.cap_nr = PCI_CAP_ID_EXP; 5502 state->cap.cap_extended = 0; 5503 state->cap.size = size; 5504 cap = (u16 *)&state->cap.data[0]; 5505 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 5506 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 5507 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 5508 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 5509 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 5510 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 5511 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 5512 hlist_add_head(&state->next, &pdev->saved_cap_space); 5513 } 5514 } 5515 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 5516 5517 /* 5518 * FLR may cause the following to devices to hang: 5519 * 5520 * AMD Starship/Matisse HD Audio Controller 0x1487 5521 * AMD Starship USB 3.0 Host Controller 0x148c 5522 * AMD Matisse USB 3.0 Host Controller 0x149c 5523 * Intel 82579LM Gigabit Ethernet Controller 0x1502 5524 * Intel 82579V Gigabit Ethernet Controller 0x1503 5525 * Mediatek MT7922 802.11ax PCI Express Wireless Network Adapter 5526 */ 5527 static void quirk_no_flr(struct pci_dev *dev) 5528 { 5529 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 5530 } 5531 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); 5532 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); 5533 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); 5534 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); 5535 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); 5536 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); 5537 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x0616, quirk_no_flr); 5538 5539 /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */ 5540 static void quirk_no_flr_snet(struct pci_dev *dev) 5541 { 5542 if (dev->revision == 0x1) 5543 quirk_no_flr(dev); 5544 } 5545 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet); 5546 5547 static void quirk_no_ext_tags(struct pci_dev *pdev) 5548 { 5549 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 5550 5551 if (!bridge) 5552 return; 5553 5554 bridge->no_ext_tags = 1; 5555 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 5556 5557 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 5558 } 5559 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags); 5560 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 5561 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 5562 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 5563 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 5564 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 5565 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 5566 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 5567 5568 #ifdef CONFIG_PCI_ATS 5569 static void quirk_no_ats(struct pci_dev *pdev) 5570 { 5571 pci_info(pdev, "disabling ATS\n"); 5572 pdev->ats_cap = 0; 5573 } 5574 5575 /* 5576 * Some devices require additional driver setup to enable ATS. Don't use 5577 * ATS for those devices as ATS will be enabled before the driver has had a 5578 * chance to load and configure the device. 5579 */ 5580 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5581 { 5582 if (pdev->device == 0x15d8) { 5583 if (pdev->revision == 0xcf && 5584 pdev->subsystem_vendor == 0xea50 && 5585 (pdev->subsystem_device == 0xce19 || 5586 pdev->subsystem_device == 0xcc10 || 5587 pdev->subsystem_device == 0xcc08)) 5588 quirk_no_ats(pdev); 5589 } else { 5590 quirk_no_ats(pdev); 5591 } 5592 } 5593 5594 /* AMD Stoney platform GPU */ 5595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); 5596 /* AMD Iceland dGPU */ 5597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); 5598 /* AMD Navi10 dGPU */ 5599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats); 5600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats); 5602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats); 5603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats); 5604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats); 5605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats); 5606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats); 5607 /* AMD Navi14 dGPU */ 5608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); 5610 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats); 5611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats); 5612 /* AMD Raven platform iGPU */ 5613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5614 5615 /* 5616 * Intel IPU E2000 revisions before C0 implement incorrect endianness 5617 * in ATS Invalidate Request message body. Disable ATS for those devices. 5618 */ 5619 static void quirk_intel_e2000_no_ats(struct pci_dev *pdev) 5620 { 5621 if (pdev->revision < 0x20) 5622 quirk_no_ats(pdev); 5623 } 5624 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats); 5625 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats); 5626 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats); 5627 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats); 5628 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats); 5629 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats); 5630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats); 5631 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats); 5632 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats); 5633 #endif /* CONFIG_PCI_ATS */ 5634 5635 /* Freescale PCIe doesn't support MSI in RC mode */ 5636 static void quirk_fsl_no_msi(struct pci_dev *pdev) 5637 { 5638 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 5639 pdev->no_msi = 1; 5640 } 5641 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 5642 5643 /* 5644 * Although not allowed by the spec, some multi-function devices have 5645 * dependencies of one function (consumer) on another (supplier). For the 5646 * consumer to work in D0, the supplier must also be in D0. Create a 5647 * device link from the consumer to the supplier to enforce this 5648 * dependency. Runtime PM is allowed by default on the consumer to prevent 5649 * it from permanently keeping the supplier awake. 5650 */ 5651 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, 5652 unsigned int supplier, unsigned int class, 5653 unsigned int class_shift) 5654 { 5655 struct pci_dev *supplier_pdev; 5656 5657 if (PCI_FUNC(pdev->devfn) != consumer) 5658 return; 5659 5660 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 5661 pdev->bus->number, 5662 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); 5663 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { 5664 pci_dev_put(supplier_pdev); 5665 return; 5666 } 5667 5668 if (device_link_add(&pdev->dev, &supplier_pdev->dev, 5669 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 5670 pci_info(pdev, "D0 power state depends on %s\n", 5671 pci_name(supplier_pdev)); 5672 else 5673 pci_err(pdev, "Cannot enforce power dependency on %s\n", 5674 pci_name(supplier_pdev)); 5675 5676 pm_runtime_allow(&pdev->dev); 5677 pci_dev_put(supplier_pdev); 5678 } 5679 5680 /* 5681 * Create device link for GPUs with integrated HDA controller for streaming 5682 * audio to attached displays. 5683 */ 5684 static void quirk_gpu_hda(struct pci_dev *hda) 5685 { 5686 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); 5687 } 5688 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5689 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5690 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 5691 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5692 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5693 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5694 5695 /* 5696 * Create device link for GPUs with integrated USB xHCI Host 5697 * controller to VGA. 5698 */ 5699 static void quirk_gpu_usb(struct pci_dev *usb) 5700 { 5701 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); 5702 } 5703 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5704 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5705 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5706 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5707 5708 /* 5709 * Create device link for GPUs with integrated Type-C UCSI controller 5710 * to VGA. Currently there is no class code defined for UCSI device over PCI 5711 * so using UNKNOWN class for now and it will be updated when UCSI 5712 * over PCI gets a class code. 5713 */ 5714 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 5715 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) 5716 { 5717 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); 5718 } 5719 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5720 PCI_CLASS_SERIAL_UNKNOWN, 8, 5721 quirk_gpu_usb_typec_ucsi); 5722 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5723 PCI_CLASS_SERIAL_UNKNOWN, 8, 5724 quirk_gpu_usb_typec_ucsi); 5725 5726 /* 5727 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it 5728 * disabled. https://devtalk.nvidia.com/default/topic/1024022 5729 */ 5730 static void quirk_nvidia_hda(struct pci_dev *gpu) 5731 { 5732 u8 hdr_type; 5733 u32 val; 5734 5735 /* There was no integrated HDA controller before MCP89 */ 5736 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) 5737 return; 5738 5739 /* Bit 25 at offset 0x488 enables the HDA controller */ 5740 pci_read_config_dword(gpu, 0x488, &val); 5741 if (val & BIT(25)) 5742 return; 5743 5744 pci_info(gpu, "Enabling HDA controller\n"); 5745 pci_write_config_dword(gpu, 0x488, val | BIT(25)); 5746 5747 /* The GPU becomes a multi-function device when the HDA is enabled */ 5748 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 5749 gpu->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr_type); 5750 } 5751 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5752 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5753 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5754 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5755 5756 /* 5757 * Some IDT switches incorrectly flag an ACS Source Validation error on 5758 * completions for config read requests even though PCIe r4.0, sec 5759 * 6.12.1.1, says that completions are never affected by ACS Source 5760 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 5761 * 5762 * Item #36 - Downstream port applies ACS Source Validation to Completions 5763 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 5764 * completions are never affected by ACS Source Validation. However, 5765 * completions received by a downstream port of the PCIe switch from a 5766 * device that has not yet captured a PCIe bus number are incorrectly 5767 * dropped by ACS Source Validation by the switch downstream port. 5768 * 5769 * The workaround suggested by IDT is to issue a config write to the 5770 * downstream device before issuing the first config read. This allows the 5771 * downstream device to capture its bus and device numbers (see PCIe r4.0, 5772 * sec 2.2.9), thus avoiding the ACS error on the completion. 5773 * 5774 * However, we don't know when the device is ready to accept the config 5775 * write, so we do config reads until we receive a non-Config Request Retry 5776 * Status, then do the config write. 5777 * 5778 * To avoid hitting the erratum when doing the config reads, we disable ACS 5779 * SV around this process. 5780 */ 5781 int pci_idt_bus_quirk(struct pci_bus *bus, int devfn, u32 *l, int timeout) 5782 { 5783 int pos; 5784 u16 ctrl = 0; 5785 bool found; 5786 struct pci_dev *bridge = bus->self; 5787 5788 pos = bridge->acs_cap; 5789 5790 /* Disable ACS SV before initial config reads */ 5791 if (pos) { 5792 pci_read_config_word(bridge, pos + PCI_ACS_CTRL, &ctrl); 5793 if (ctrl & PCI_ACS_SV) 5794 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, 5795 ctrl & ~PCI_ACS_SV); 5796 } 5797 5798 found = pci_bus_generic_read_dev_vendor_id(bus, devfn, l, timeout); 5799 5800 /* Write Vendor ID (read-only) so the endpoint latches its bus/dev */ 5801 if (found) 5802 pci_bus_write_config_word(bus, devfn, PCI_VENDOR_ID, 0); 5803 5804 /* Re-enable ACS_SV if it was previously enabled */ 5805 if (ctrl & PCI_ACS_SV) 5806 pci_write_config_word(bridge, pos + PCI_ACS_CTRL, ctrl); 5807 5808 return found; 5809 } 5810 5811 /* 5812 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 5813 * NT endpoints via the internal switch fabric. These IDs replace the 5814 * originating Requester ID TLPs which access host memory on peer NTB 5815 * ports. Therefore, all proxy IDs must be aliased to the NTB device 5816 * to permit access when the IOMMU is turned on. 5817 */ 5818 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 5819 { 5820 void __iomem *mmio; 5821 struct ntb_info_regs __iomem *mmio_ntb; 5822 struct ntb_ctrl_regs __iomem *mmio_ctrl; 5823 u64 partition_map; 5824 u8 partition; 5825 int pp; 5826 5827 if (pci_enable_device(pdev)) { 5828 pci_err(pdev, "Cannot enable Switchtec device\n"); 5829 return; 5830 } 5831 5832 mmio = pci_iomap(pdev, 0, 0); 5833 if (mmio == NULL) { 5834 pci_disable_device(pdev); 5835 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5836 return; 5837 } 5838 5839 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5840 5841 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5842 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5843 5844 partition = ioread8(&mmio_ntb->partition_id); 5845 5846 partition_map = ioread32(&mmio_ntb->ep_map); 5847 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5848 partition_map &= ~(1ULL << partition); 5849 5850 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5851 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5852 u32 table_sz = 0; 5853 int te; 5854 5855 if (!(partition_map & (1ULL << pp))) 5856 continue; 5857 5858 pci_dbg(pdev, "Processing partition %d\n", pp); 5859 5860 mmio_peer_ctrl = &mmio_ctrl[pp]; 5861 5862 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5863 if (!table_sz) { 5864 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5865 continue; 5866 } 5867 5868 if (table_sz > 512) { 5869 pci_warn(pdev, 5870 "Invalid Switchtec partition %d table_sz %d\n", 5871 pp, table_sz); 5872 continue; 5873 } 5874 5875 for (te = 0; te < table_sz; te++) { 5876 u32 rid_entry; 5877 u8 devfn; 5878 5879 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5880 devfn = (rid_entry >> 1) & 0xFF; 5881 pci_dbg(pdev, 5882 "Aliasing Partition %d Proxy ID %02x.%d\n", 5883 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5884 pci_add_dma_alias(pdev, devfn, 1); 5885 } 5886 } 5887 5888 pci_iounmap(pdev, mmio); 5889 pci_disable_device(pdev); 5890 } 5891 #define SWITCHTEC_QUIRK(vid) \ 5892 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 5893 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5894 5895 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 5896 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 5897 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 5898 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 5899 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 5900 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 5901 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 5902 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 5903 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 5904 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 5905 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 5906 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 5907 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 5908 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 5909 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 5910 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 5911 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 5912 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 5913 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 5914 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 5915 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 5916 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 5917 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 5918 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 5919 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 5920 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 5921 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 5922 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 5923 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 5924 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 5925 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ 5926 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ 5927 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ 5928 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ 5929 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ 5930 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ 5931 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ 5932 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ 5933 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ 5934 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ 5935 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ 5936 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ 5937 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ 5938 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ 5939 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ 5940 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ 5941 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ 5942 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ 5943 SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */ 5944 SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */ 5945 SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */ 5946 SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */ 5947 SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */ 5948 SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */ 5949 SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */ 5950 SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */ 5951 SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */ 5952 SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */ 5953 SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */ 5954 SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */ 5955 SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */ 5956 SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */ 5957 SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */ 5958 SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */ 5959 SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */ 5960 SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */ 5961 SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */ 5962 SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */ 5963 SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */ 5964 SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */ 5965 SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */ 5966 SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */ 5967 SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */ 5968 SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */ 5969 SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */ 5970 SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */ 5971 SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */ 5972 SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */ 5973 SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */ 5974 SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */ 5975 SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */ 5976 SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */ 5977 SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */ 5978 SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */ 5979 SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */ 5980 SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */ 5981 SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */ 5982 SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */ 5983 SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */ 5984 SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */ 5985 SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */ 5986 SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */ 5987 SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */ 5988 5989 #define SWITCHTEC_PCI100X_QUIRK(vid) \ 5990 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_EFAR, vid, \ 5991 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5992 SWITCHTEC_PCI100X_QUIRK(0x1001); /* PCI1001XG4 */ 5993 SWITCHTEC_PCI100X_QUIRK(0x1002); /* PCI1002XG4 */ 5994 SWITCHTEC_PCI100X_QUIRK(0x1003); /* PCI1003XG4 */ 5995 SWITCHTEC_PCI100X_QUIRK(0x1004); /* PCI1004XG4 */ 5996 SWITCHTEC_PCI100X_QUIRK(0x1005); /* PCI1005XG4 */ 5997 SWITCHTEC_PCI100X_QUIRK(0x1006); /* PCI1006XG4 */ 5998 5999 6000 /* 6001 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. 6002 * These IDs are used to forward responses to the originator on the other 6003 * side of the NTB. Alias all possible IDs to the NTB to permit access when 6004 * the IOMMU is turned on. 6005 */ 6006 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) 6007 { 6008 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); 6009 /* PLX NTB may use all 256 devfns */ 6010 pci_add_dma_alias(pdev, 0, 256); 6011 } 6012 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); 6013 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); 6014 6015 /* 6016 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does 6017 * not always reset the secondary Nvidia GPU between reboots if the system 6018 * is configured to use Hybrid Graphics mode. This results in the GPU 6019 * being left in whatever state it was in during the *previous* boot, which 6020 * causes spurious interrupts from the GPU, which in turn causes us to 6021 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, 6022 * this also completely breaks nouveau. 6023 * 6024 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a 6025 * clean state and fixes all these issues. 6026 * 6027 * When the machine is configured in Dedicated display mode, the issue 6028 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this 6029 * mode, so we can detect that and avoid resetting it. 6030 */ 6031 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) 6032 { 6033 void __iomem *map; 6034 int ret; 6035 6036 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || 6037 pdev->subsystem_device != 0x222e || 6038 !pci_reset_supported(pdev)) 6039 return; 6040 6041 if (pci_enable_device_mem(pdev)) 6042 return; 6043 6044 /* 6045 * Based on nvkm_device_ctor() in 6046 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 6047 */ 6048 map = pci_iomap(pdev, 0, 0x23000); 6049 if (!map) { 6050 pci_err(pdev, "Can't map MMIO space\n"); 6051 goto out_disable; 6052 } 6053 6054 /* 6055 * Make sure the GPU looks like it's been POSTed before resetting 6056 * it. 6057 */ 6058 if (ioread32(map + 0x2240c) & 0x2) { 6059 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); 6060 ret = pci_reset_bus(pdev); 6061 if (ret < 0) 6062 pci_err(pdev, "Failed to reset GPU: %d\n", ret); 6063 } 6064 6065 iounmap(map); 6066 out_disable: 6067 pci_disable_device(pdev); 6068 } 6069 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, 6070 PCI_CLASS_DISPLAY_VGA, 8, 6071 quirk_reset_lenovo_thinkpad_p50_nvgpu); 6072 6073 /* 6074 * Device [1b21:2142] 6075 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. 6076 */ 6077 static void pci_fixup_no_d0_pme(struct pci_dev *dev) 6078 { 6079 pci_info(dev, "PME# does not work under D0, disabling it\n"); 6080 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 6081 } 6082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 6083 6084 /* 6085 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 6086 * 6087 * These devices advertise PME# support in all power states but don't 6088 * reliably assert it. 6089 * 6090 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 6091 * says "The MSI Function is not implemented on this device" in chapters 6092 * 7.3.27, 7.3.29-7.3.31. 6093 */ 6094 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 6095 { 6096 #ifdef CONFIG_PCI_MSI 6097 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 6098 dev->no_msi = 1; 6099 #endif 6100 pci_info(dev, "PME# is unreliable, disabling it\n"); 6101 dev->pme_support = 0; 6102 } 6103 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 6104 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 6105 6106 static void apex_pci_fixup_class(struct pci_dev *pdev) 6107 { 6108 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; 6109 } 6110 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, 6111 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); 6112 6113 /* 6114 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 - 6115 * ACS P2P Request Redirect is not functional 6116 * 6117 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced 6118 * between upstream and downstream ports, packets are queued in an internal 6119 * buffer until CPLD packet. The workaround is to use the switch in store and 6120 * forward mode. 6121 */ 6122 #define PI7C9X2Gxxx_MODE_REG 0x74 6123 #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0) 6124 static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev) 6125 { 6126 struct pci_dev *upstream; 6127 u16 val; 6128 6129 /* Downstream ports only */ 6130 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) 6131 return; 6132 6133 /* Check for ACS P2P Request Redirect use */ 6134 if (!pdev->acs_cap) 6135 return; 6136 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); 6137 if (!(val & PCI_ACS_RR)) 6138 return; 6139 6140 upstream = pci_upstream_bridge(pdev); 6141 if (!upstream) 6142 return; 6143 6144 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val); 6145 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) { 6146 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); 6147 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val | 6148 PI7C9X2Gxxx_STORE_FORWARD_MODE); 6149 } 6150 } 6151 /* 6152 * Apply fixup on enable and on resume, in order to apply the fix up whenever 6153 * ACS configuration changes or switch mode is reset 6154 */ 6155 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404, 6156 pci_fixup_pericom_acs_store_forward); 6157 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404, 6158 pci_fixup_pericom_acs_store_forward); 6159 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304, 6160 pci_fixup_pericom_acs_store_forward); 6161 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304, 6162 pci_fixup_pericom_acs_store_forward); 6163 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, 6164 pci_fixup_pericom_acs_store_forward); 6165 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, 6166 pci_fixup_pericom_acs_store_forward); 6167 6168 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) 6169 { 6170 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; 6171 } 6172 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); 6173 6174 static void rom_bar_overlap_defect(struct pci_dev *dev) 6175 { 6176 pci_info(dev, "working around ROM BAR overlap defect\n"); 6177 dev->rom_bar_overlap = 1; 6178 } 6179 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect); 6180 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect); 6181 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect); 6182 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect); 6183 6184 #ifdef CONFIG_PCIEASPM 6185 /* 6186 * Several Intel DG2 graphics devices advertise that they can only tolerate 6187 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1 6188 * from being enabled. But in fact these devices can tolerate unlimited 6189 * latency. Override their Device Capabilities value to allow ASPM L1 to 6190 * be enabled. 6191 */ 6192 static void aspm_l1_acceptable_latency(struct pci_dev *dev) 6193 { 6194 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); 6195 6196 if (l1_lat < 7) { 6197 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); 6198 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", 6199 l1_lat); 6200 } 6201 } 6202 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency); 6203 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency); 6204 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency); 6205 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency); 6206 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency); 6207 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency); 6208 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency); 6209 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency); 6210 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency); 6211 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency); 6212 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency); 6213 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency); 6214 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency); 6215 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency); 6216 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency); 6217 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency); 6218 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency); 6219 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency); 6220 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency); 6221 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency); 6222 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency); 6223 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency); 6224 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency); 6225 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); 6226 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); 6227 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); 6228 #endif 6229 6230 #ifdef CONFIG_PCIE_DPC 6231 /* 6232 * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears 6233 * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root 6234 * Ports. 6235 */ 6236 static void dpc_log_size(struct pci_dev *dev) 6237 { 6238 u16 dpc, val; 6239 6240 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); 6241 if (!dpc) 6242 return; 6243 6244 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val); 6245 if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) 6246 return; 6247 6248 if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) { 6249 pci_info(dev, "Overriding RP PIO Log Size to %d\n", 6250 PCIE_STD_NUM_TLP_HEADERLOG); 6251 dev->dpc_rp_log_size = PCIE_STD_NUM_TLP_HEADERLOG; 6252 } 6253 } 6254 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size); 6255 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size); 6256 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size); 6257 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size); 6258 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size); 6259 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size); 6260 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size); 6261 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size); 6262 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size); 6263 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size); 6264 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size); 6265 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size); 6266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size); 6267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); 6268 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); 6269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); 6270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa72f, dpc_log_size); 6271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size); 6272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size); 6273 #endif 6274 6275 /* 6276 * For a PCI device with multiple downstream devices, its driver may use 6277 * a flattened device tree to describe the downstream devices. 6278 * To overlay the flattened device tree, the PCI device and all its ancestor 6279 * devices need to have device tree nodes on system base device tree. Thus, 6280 * before driver probing, it might need to add a device tree node as the final 6281 * fixup. 6282 */ 6283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); 6284 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); 6285 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node); 6286 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node); 6287 6288 /* 6289 * Devices known to require a longer delay before first config space access 6290 * after reset recovery or resume from D3cold: 6291 * 6292 * VideoPropulsion (aka Genroco) Torrent QN16e MPEG QAM Modulator 6293 */ 6294 static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev) 6295 { 6296 pdev->d3cold_delay = 1000; 6297 } 6298 DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec); 6299 6300 #ifdef CONFIG_PCIEAER 6301 static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) 6302 { 6303 struct pci_dev *parent = pci_upstream_bridge(pdev); 6304 u32 val; 6305 6306 if (!parent || !parent->aer_cap) 6307 return; 6308 6309 pci_info(parent, "mask Replay Timer Timeout Correctable Errors due to %s hardware defect", 6310 pci_name(pdev)); 6311 6312 pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val); 6313 val |= PCI_ERR_COR_REP_TIMER; 6314 pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val); 6315 } 6316 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); 6317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); 6318 #endif 6319