1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * This file contains work-arounds for many known PCI hardware bugs. 4 * Devices present only on certain architectures (host bridges et cetera) 5 * should be handled in arch-specific code. 6 * 7 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init. 8 * 9 * Copyright (c) 1999 Martin Mares <mj@ucw.cz> 10 * 11 * Init/reset quirks for USB host controllers should be in the USB quirks 12 * file, where their drivers can use them. 13 */ 14 15 #include <linux/aer.h> 16 #include <linux/align.h> 17 #include <linux/bitfield.h> 18 #include <linux/types.h> 19 #include <linux/kernel.h> 20 #include <linux/export.h> 21 #include <linux/pci.h> 22 #include <linux/isa-dma.h> /* isa_dma_bridge_buggy */ 23 #include <linux/init.h> 24 #include <linux/iommu.h> 25 #include <linux/delay.h> 26 #include <linux/acpi.h> 27 #include <linux/dmi.h> 28 #include <linux/ioport.h> 29 #include <linux/sched.h> 30 #include <linux/ktime.h> 31 #include <linux/mm.h> 32 #include <linux/nvme.h> 33 #include <linux/platform_data/x86/apple.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/sizes.h> 36 #include <linux/suspend.h> 37 #include <linux/switchtec.h> 38 #include "pci.h" 39 40 static bool pcie_lbms_seen(struct pci_dev *dev, u16 lnksta) 41 { 42 if (test_bit(PCI_LINK_LBMS_SEEN, &dev->priv_flags)) 43 return true; 44 45 return lnksta & PCI_EXP_LNKSTA_LBMS; 46 } 47 48 /* 49 * Retrain the link of a downstream PCIe port by hand if necessary. 50 * 51 * This is needed at least where a downstream port of the ASMedia ASM2824 52 * Gen 3 switch is wired to the upstream port of the Pericom PI7C9X2G304 53 * Gen 2 switch, and observed with the Delock Riser Card PCI Express x1 > 54 * 2 x PCIe x1 device, P/N 41433, plugged into the SiFive HiFive Unmatched 55 * board. 56 * 57 * In such a configuration the switches are supposed to negotiate the link 58 * speed of preferably 5.0GT/s, falling back to 2.5GT/s. However the link 59 * continues switching between the two speeds indefinitely and the data 60 * link layer never reaches the active state, with link training reported 61 * repeatedly active ~84% of the time. Forcing the target link speed to 62 * 2.5GT/s with the upstream ASM2824 device makes the two switches talk to 63 * each other correctly however. And more interestingly retraining with a 64 * higher target link speed afterwards lets the two successfully negotiate 65 * 5.0GT/s. 66 * 67 * With the ASM2824 we can rely on the otherwise optional Data Link Layer 68 * Link Active status bit and in the failed link training scenario it will 69 * be off along with the Link Bandwidth Management Status indicating that 70 * hardware has changed the link speed or width in an attempt to correct 71 * unreliable link operation. For a port that has been left unconnected 72 * both bits will be clear. So use this information to detect the problem 73 * rather than polling the Link Training bit and watching out for flips or 74 * at least the active status. 75 * 76 * Since the exact nature of the problem isn't known and in principle this 77 * could trigger where an ASM2824 device is downstream rather upstream, 78 * apply this erratum workaround to any downstream ports as long as they 79 * support Link Active reporting and have the Link Control 2 register. 80 * Restrict the speed to 2.5GT/s then with the Target Link Speed field, 81 * request a retrain and check the result. 82 * 83 * If this turns out successful and we know by the Vendor:Device ID it is 84 * safe to do so, then lift the restriction, letting the devices negotiate 85 * a higher speed. Also check for a similar 2.5GT/s speed restriction the 86 * firmware may have already arranged and lift it with ports that already 87 * report their data link being up. 88 * 89 * Otherwise revert the speed to the original setting and request a retrain 90 * again to remove any residual state, ignoring the result as it's supposed 91 * to fail anyway. 92 * 93 * Return 0 if the link has been successfully retrained. Return an error 94 * if retraining was not needed or we attempted a retrain and it failed. 95 */ 96 int pcie_failed_link_retrain(struct pci_dev *dev) 97 { 98 static const struct pci_device_id ids[] = { 99 { PCI_VDEVICE(ASMEDIA, 0x2824) }, /* ASMedia ASM2824 */ 100 {} 101 }; 102 u16 lnksta, lnkctl2; 103 int ret = -ENOTTY; 104 105 if (!pci_is_pcie(dev) || !pcie_downstream_port(dev) || 106 !pcie_cap_has_lnkctl2(dev) || !dev->link_active_reporting) 107 return ret; 108 109 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 110 if (!(lnksta & PCI_EXP_LNKSTA_DLLLA) && pcie_lbms_seen(dev, lnksta)) { 111 u16 oldlnkctl2; 112 113 pci_info(dev, "broken device, retraining non-functional downstream link at 2.5GT/s\n"); 114 115 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &oldlnkctl2); 116 ret = pcie_set_target_speed(dev, PCIE_SPEED_2_5GT, false); 117 if (ret) { 118 pci_info(dev, "retraining failed\n"); 119 pcie_set_target_speed(dev, PCIE_LNKCTL2_TLS2SPEED(oldlnkctl2), 120 true); 121 return ret; 122 } 123 124 pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta); 125 } 126 127 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &lnkctl2); 128 129 if ((lnksta & PCI_EXP_LNKSTA_DLLLA) && 130 (lnkctl2 & PCI_EXP_LNKCTL2_TLS) == PCI_EXP_LNKCTL2_TLS_2_5GT && 131 pci_match_id(ids, dev)) { 132 u32 lnkcap; 133 134 pci_info(dev, "removing 2.5GT/s downstream link speed restriction\n"); 135 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP, &lnkcap); 136 ret = pcie_set_target_speed(dev, PCIE_LNKCAP_SLS2SPEED(lnkcap), false); 137 if (ret) { 138 pci_info(dev, "retraining failed\n"); 139 return ret; 140 } 141 } 142 143 return ret; 144 } 145 146 static ktime_t fixup_debug_start(struct pci_dev *dev, 147 void (*fn)(struct pci_dev *dev)) 148 { 149 if (initcall_debug) 150 pci_info(dev, "calling %pS @ %i\n", fn, task_pid_nr(current)); 151 152 return ktime_get(); 153 } 154 155 static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime, 156 void (*fn)(struct pci_dev *dev)) 157 { 158 ktime_t delta, rettime; 159 unsigned long long duration; 160 161 rettime = ktime_get(); 162 delta = ktime_sub(rettime, calltime); 163 duration = (unsigned long long) ktime_to_ns(delta) >> 10; 164 if (initcall_debug || duration > 10000) 165 pci_info(dev, "%pS took %lld usecs\n", fn, duration); 166 } 167 168 static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f, 169 struct pci_fixup *end) 170 { 171 ktime_t calltime; 172 173 for (; f < end; f++) 174 if ((f->class == (u32) (dev->class >> f->class_shift) || 175 f->class == (u32) PCI_ANY_ID) && 176 (f->vendor == dev->vendor || 177 f->vendor == (u16) PCI_ANY_ID) && 178 (f->device == dev->device || 179 f->device == (u16) PCI_ANY_ID)) { 180 void (*hook)(struct pci_dev *dev); 181 #ifdef CONFIG_HAVE_ARCH_PREL32_RELOCATIONS 182 hook = offset_to_ptr(&f->hook_offset); 183 #else 184 hook = f->hook; 185 #endif 186 calltime = fixup_debug_start(dev, hook); 187 hook(dev); 188 fixup_debug_report(dev, calltime, hook); 189 } 190 } 191 192 extern struct pci_fixup __start_pci_fixups_early[]; 193 extern struct pci_fixup __end_pci_fixups_early[]; 194 extern struct pci_fixup __start_pci_fixups_header[]; 195 extern struct pci_fixup __end_pci_fixups_header[]; 196 extern struct pci_fixup __start_pci_fixups_final[]; 197 extern struct pci_fixup __end_pci_fixups_final[]; 198 extern struct pci_fixup __start_pci_fixups_enable[]; 199 extern struct pci_fixup __end_pci_fixups_enable[]; 200 extern struct pci_fixup __start_pci_fixups_resume[]; 201 extern struct pci_fixup __end_pci_fixups_resume[]; 202 extern struct pci_fixup __start_pci_fixups_resume_early[]; 203 extern struct pci_fixup __end_pci_fixups_resume_early[]; 204 extern struct pci_fixup __start_pci_fixups_suspend[]; 205 extern struct pci_fixup __end_pci_fixups_suspend[]; 206 extern struct pci_fixup __start_pci_fixups_suspend_late[]; 207 extern struct pci_fixup __end_pci_fixups_suspend_late[]; 208 209 static bool pci_apply_fixup_final_quirks; 210 211 void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev) 212 { 213 struct pci_fixup *start, *end; 214 215 switch (pass) { 216 case pci_fixup_early: 217 start = __start_pci_fixups_early; 218 end = __end_pci_fixups_early; 219 break; 220 221 case pci_fixup_header: 222 start = __start_pci_fixups_header; 223 end = __end_pci_fixups_header; 224 break; 225 226 case pci_fixup_final: 227 if (!pci_apply_fixup_final_quirks) 228 return; 229 start = __start_pci_fixups_final; 230 end = __end_pci_fixups_final; 231 break; 232 233 case pci_fixup_enable: 234 start = __start_pci_fixups_enable; 235 end = __end_pci_fixups_enable; 236 break; 237 238 case pci_fixup_resume: 239 start = __start_pci_fixups_resume; 240 end = __end_pci_fixups_resume; 241 break; 242 243 case pci_fixup_resume_early: 244 start = __start_pci_fixups_resume_early; 245 end = __end_pci_fixups_resume_early; 246 break; 247 248 case pci_fixup_suspend: 249 start = __start_pci_fixups_suspend; 250 end = __end_pci_fixups_suspend; 251 break; 252 253 case pci_fixup_suspend_late: 254 start = __start_pci_fixups_suspend_late; 255 end = __end_pci_fixups_suspend_late; 256 break; 257 258 default: 259 /* stupid compiler warning, you would think with an enum... */ 260 return; 261 } 262 pci_do_fixups(dev, start, end); 263 } 264 EXPORT_SYMBOL(pci_fixup_device); 265 266 static int __init pci_apply_final_quirks(void) 267 { 268 struct pci_dev *dev = NULL; 269 u8 cls = 0; 270 u8 tmp; 271 272 if (pci_cache_line_size) 273 pr_info("PCI: CLS %u bytes\n", pci_cache_line_size << 2); 274 275 pci_apply_fixup_final_quirks = true; 276 for_each_pci_dev(dev) { 277 pci_fixup_device(pci_fixup_final, dev); 278 /* 279 * If arch hasn't set it explicitly yet, use the CLS 280 * value shared by all PCI devices. If there's a 281 * mismatch, fall back to the default value. 282 */ 283 if (!pci_cache_line_size) { 284 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp); 285 if (!cls) 286 cls = tmp; 287 if (!tmp || cls == tmp) 288 continue; 289 290 pci_info(dev, "CLS mismatch (%u != %u), using %u bytes\n", 291 cls << 2, tmp << 2, 292 pci_dfl_cache_line_size << 2); 293 pci_cache_line_size = pci_dfl_cache_line_size; 294 } 295 } 296 297 if (!pci_cache_line_size) { 298 pr_info("PCI: CLS %u bytes, default %u\n", cls << 2, 299 pci_dfl_cache_line_size << 2); 300 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size; 301 } 302 303 return 0; 304 } 305 fs_initcall_sync(pci_apply_final_quirks); 306 307 /* 308 * Decoding should be disabled for a PCI device during BAR sizing to avoid 309 * conflict. But doing so may cause problems on host bridge and perhaps other 310 * key system devices. For devices that need to have mmio decoding always-on, 311 * we need to set the dev->mmio_always_on bit. 312 */ 313 static void quirk_mmio_always_on(struct pci_dev *dev) 314 { 315 dev->mmio_always_on = 1; 316 } 317 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID, 318 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on); 319 320 /* 321 * The Mellanox Tavor device gives false positive parity errors. Disable 322 * parity error reporting. 323 */ 324 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, pci_disable_parity); 325 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, pci_disable_parity); 326 327 /* 328 * Deal with broken BIOSes that neglect to enable passive release, 329 * which can cause problems in combination with the 82441FX/PPro MTRRs 330 */ 331 static void quirk_passive_release(struct pci_dev *dev) 332 { 333 struct pci_dev *d = NULL; 334 unsigned char dlc; 335 336 /* 337 * We have to make sure a particular bit is set in the PIIX3 338 * ISA bridge, so we have to go out and find it. 339 */ 340 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) { 341 pci_read_config_byte(d, 0x82, &dlc); 342 if (!(dlc & 1<<1)) { 343 pci_info(d, "PIIX3: Enabling Passive Release\n"); 344 dlc |= 1<<1; 345 pci_write_config_byte(d, 0x82, dlc); 346 } 347 } 348 } 349 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 350 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release); 351 352 #ifdef CONFIG_X86_32 353 /* 354 * The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a 355 * workaround but VIA don't answer queries. If you happen to have good 356 * contacts at VIA ask them for me please -- Alan 357 * 358 * This appears to be BIOS not version dependent. So presumably there is a 359 * chipset level fix. 360 */ 361 static void quirk_isa_dma_hangs(struct pci_dev *dev) 362 { 363 if (!isa_dma_bridge_buggy) { 364 isa_dma_bridge_buggy = 1; 365 pci_info(dev, "Activating ISA DMA hang workarounds\n"); 366 } 367 } 368 /* 369 * It's not totally clear which chipsets are the problematic ones. We know 370 * 82C586 and 82C596 variants are affected. 371 */ 372 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs); 373 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs); 374 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs); 375 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs); 376 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs); 377 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs); 378 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs); 379 #endif 380 381 #ifdef CONFIG_HAS_IOPORT 382 /* 383 * Intel NM10 "Tiger Point" LPC PM1a_STS.BM_STS must be clear 384 * for some HT machines to use C4 w/o hanging. 385 */ 386 static void quirk_tigerpoint_bm_sts(struct pci_dev *dev) 387 { 388 u32 pmbase; 389 u16 pm1a; 390 391 pci_read_config_dword(dev, 0x40, &pmbase); 392 pmbase = pmbase & 0xff80; 393 pm1a = inw(pmbase); 394 395 if (pm1a & 0x10) { 396 pci_info(dev, FW_BUG "Tiger Point LPC.BM_STS cleared\n"); 397 outw(0x10, pmbase); 398 } 399 } 400 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts); 401 #endif 402 403 /* Chipsets where PCI->PCI transfers vanish or hang */ 404 static void quirk_nopcipci(struct pci_dev *dev) 405 { 406 if ((pci_pci_problems & PCIPCI_FAIL) == 0) { 407 pci_info(dev, "Disabling direct PCI/PCI transfers\n"); 408 pci_pci_problems |= PCIPCI_FAIL; 409 } 410 } 411 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci); 412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci); 413 414 static void quirk_nopciamd(struct pci_dev *dev) 415 { 416 u8 rev; 417 pci_read_config_byte(dev, 0x08, &rev); 418 if (rev == 0x13) { 419 /* Erratum 24 */ 420 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n"); 421 pci_pci_problems |= PCIAGP_FAIL; 422 } 423 } 424 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd); 425 426 /* Triton requires workarounds to be used by the drivers */ 427 static void quirk_triton(struct pci_dev *dev) 428 { 429 if ((pci_pci_problems&PCIPCI_TRITON) == 0) { 430 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 431 pci_pci_problems |= PCIPCI_TRITON; 432 } 433 } 434 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton); 435 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton); 436 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton); 437 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton); 438 439 /* 440 * VIA Apollo KT133 needs PCI latency patch 441 * Made according to a Windows driver-based patch by George E. Breese; 442 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm 443 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for the info on 444 * which Mr Breese based his work. 445 * 446 * Updated based on further information from the site and also on 447 * information provided by VIA 448 */ 449 static void quirk_vialatency(struct pci_dev *dev) 450 { 451 struct pci_dev *p; 452 u8 busarb; 453 454 /* 455 * Ok, we have a potential problem chipset here. Now see if we have 456 * a buggy southbridge. 457 */ 458 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL); 459 if (p != NULL) { 460 461 /* 462 * 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; 463 * thanks Dan Hollis. 464 * Check for buggy part revisions 465 */ 466 if (p->revision < 0x40 || p->revision > 0x42) 467 goto exit; 468 } else { 469 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL); 470 if (p == NULL) /* No problem parts */ 471 goto exit; 472 473 /* Check for buggy part revisions */ 474 if (p->revision < 0x10 || p->revision > 0x12) 475 goto exit; 476 } 477 478 /* 479 * Ok we have the problem. Now set the PCI master grant to occur 480 * every master grant. The apparent bug is that under high PCI load 481 * (quite common in Linux of course) you can get data loss when the 482 * CPU is held off the bus for 3 bus master requests. This happens 483 * to include the IDE controllers.... 484 * 485 * VIA only apply this fix when an SB Live! is present but under 486 * both Linux and Windows this isn't enough, and we have seen 487 * corruption without SB Live! but with things like 3 UDMA IDE 488 * controllers. So we ignore that bit of the VIA recommendation.. 489 */ 490 pci_read_config_byte(dev, 0x76, &busarb); 491 492 /* 493 * Set bit 4 and bit 5 of byte 76 to 0x01 494 * "Master priority rotation on every PCI master grant" 495 */ 496 busarb &= ~(1<<5); 497 busarb |= (1<<4); 498 pci_write_config_byte(dev, 0x76, busarb); 499 pci_info(dev, "Applying VIA southbridge workaround\n"); 500 exit: 501 pci_dev_put(p); 502 } 503 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 504 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 505 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 506 /* Must restore this on a resume from RAM */ 507 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency); 508 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency); 509 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency); 510 511 /* VIA Apollo VP3 needs ETBF on BT848/878 */ 512 static void quirk_viaetbf(struct pci_dev *dev) 513 { 514 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) { 515 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 516 pci_pci_problems |= PCIPCI_VIAETBF; 517 } 518 } 519 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf); 520 521 static void quirk_vsfx(struct pci_dev *dev) 522 { 523 if ((pci_pci_problems&PCIPCI_VSFX) == 0) { 524 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 525 pci_pci_problems |= PCIPCI_VSFX; 526 } 527 } 528 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx); 529 530 /* 531 * ALi Magik requires workarounds to be used by the drivers that DMA to AGP 532 * space. Latency must be set to 0xA and Triton workaround applied too. 533 * [Info kindly provided by ALi] 534 */ 535 static void quirk_alimagik(struct pci_dev *dev) 536 { 537 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) { 538 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 539 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON; 540 } 541 } 542 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik); 543 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik); 544 545 /* Natoma has some interesting boundary conditions with Zoran stuff at least */ 546 static void quirk_natoma(struct pci_dev *dev) 547 { 548 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) { 549 pci_info(dev, "Limiting direct PCI/PCI transfers\n"); 550 pci_pci_problems |= PCIPCI_NATOMA; 551 } 552 } 553 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma); 554 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma); 555 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma); 556 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma); 557 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma); 558 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma); 559 560 /* 561 * This chip can cause PCI parity errors if config register 0xA0 is read 562 * while DMAs are occurring. 563 */ 564 static void quirk_citrine(struct pci_dev *dev) 565 { 566 dev->cfg_size = 0xA0; 567 } 568 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine); 569 570 /* 571 * This chip can cause bus lockups if config addresses above 0x600 572 * are read or written. 573 */ 574 static void quirk_nfp6000(struct pci_dev *dev) 575 { 576 dev->cfg_size = 0x600; 577 } 578 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000); 579 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000); 580 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP5000, quirk_nfp6000); 581 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000); 582 583 /* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */ 584 static void quirk_extend_bar_to_page(struct pci_dev *dev) 585 { 586 int i; 587 588 for (i = 0; i < PCI_STD_NUM_BARS; i++) { 589 struct resource *r = &dev->resource[i]; 590 const char *r_name = pci_resource_name(dev, i); 591 592 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) { 593 resource_set_range(r, 0, PAGE_SIZE); 594 r->flags |= IORESOURCE_UNSET; 595 pci_info(dev, "%s %pR: expanded to page size\n", 596 r_name, r); 597 } 598 } 599 } 600 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page); 601 602 /* 603 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M. 604 * If it's needed, re-allocate the region. 605 */ 606 static void quirk_s3_64M(struct pci_dev *dev) 607 { 608 struct resource *r = &dev->resource[0]; 609 610 if (!IS_ALIGNED(r->start, SZ_64M) || resource_size(r) != SZ_64M) { 611 r->flags |= IORESOURCE_UNSET; 612 resource_set_range(r, 0, SZ_64M); 613 } 614 } 615 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M); 616 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M); 617 618 static void quirk_io(struct pci_dev *dev, int pos, unsigned int size, 619 const char *name) 620 { 621 u32 region; 622 struct pci_bus_region bus_region; 623 struct resource *res = pci_resource_n(dev, pos); 624 const char *res_name = pci_resource_name(dev, pos); 625 626 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion); 627 628 if (!region) 629 return; 630 631 res->name = pci_name(dev); 632 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK; 633 res->flags |= 634 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN); 635 region &= ~(size - 1); 636 637 /* Convert from PCI bus to resource space */ 638 bus_region.start = region; 639 bus_region.end = region + size - 1; 640 pcibios_bus_to_resource(dev->bus, res, &bus_region); 641 642 pci_info(dev, FW_BUG "%s %pR: %s quirk\n", res_name, res, name); 643 } 644 645 /* 646 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS 647 * ver. 1.33 20070103) don't set the correct ISA PCI region header info. 648 * BAR0 should be 8 bytes; instead, it may be set to something like 8k 649 * (which conflicts w/ BAR1's memory range). 650 * 651 * CS553x's ISA PCI BARs may also be read-only (ref: 652 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward). 653 */ 654 static void quirk_cs5536_vsa(struct pci_dev *dev) 655 { 656 static char *name = "CS5536 ISA bridge"; 657 658 if (pci_resource_len(dev, 0) != 8) { 659 quirk_io(dev, 0, 8, name); /* SMB */ 660 quirk_io(dev, 1, 256, name); /* GPIO */ 661 quirk_io(dev, 2, 64, name); /* MFGPT */ 662 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n", 663 name); 664 } 665 } 666 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa); 667 668 static void quirk_io_region(struct pci_dev *dev, int port, 669 unsigned int size, int nr, const char *name) 670 { 671 u16 region; 672 struct pci_bus_region bus_region; 673 struct resource *res = pci_resource_n(dev, nr); 674 675 pci_read_config_word(dev, port, ®ion); 676 region &= ~(size - 1); 677 678 if (!region) 679 return; 680 681 res->name = pci_name(dev); 682 res->flags = IORESOURCE_IO; 683 684 /* Convert from PCI bus to resource space */ 685 bus_region.start = region; 686 bus_region.end = region + size - 1; 687 pcibios_bus_to_resource(dev->bus, res, &bus_region); 688 689 /* 690 * "res" is typically a bridge window resource that's not being 691 * used for a bridge window, so it's just a place to stash this 692 * non-standard resource. Printing "nr" or pci_resource_name() of 693 * it doesn't really make sense. 694 */ 695 if (!pci_claim_resource(dev, nr)) 696 pci_info(dev, "quirk: %pR claimed by %s\n", res, name); 697 } 698 699 /* 700 * ATI Northbridge setups MCE the processor if you even read somewhere 701 * between 0x3b0->0x3bb or read 0x3d3 702 */ 703 static void quirk_ati_exploding_mce(struct pci_dev *dev) 704 { 705 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n"); 706 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */ 707 request_region(0x3b0, 0x0C, "RadeonIGP"); 708 request_region(0x3d3, 0x01, "RadeonIGP"); 709 } 710 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce); 711 712 /* 713 * In the AMD NL platform, this device ([1022:7912]) has a class code of 714 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will 715 * claim it. The same applies on the VanGogh platform device ([1022:163a]). 716 * 717 * But the dwc3 driver is a more specific driver for this device, and we'd 718 * prefer to use it instead of xhci. To prevent xhci from claiming the 719 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec 720 * defines as "USB device (not host controller)". The dwc3 driver can then 721 * claim it based on its Vendor and Device ID. 722 */ 723 static void quirk_amd_dwc_class(struct pci_dev *pdev) 724 { 725 u32 class = pdev->class; 726 727 if (class != PCI_CLASS_SERIAL_USB_DEVICE) { 728 /* Use "USB Device (not host controller)" class */ 729 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 730 pci_info(pdev, 731 "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 732 class, pdev->class); 733 } 734 } 735 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB, 736 quirk_amd_dwc_class); 737 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VANGOGH_USB, 738 quirk_amd_dwc_class); 739 740 /* 741 * Synopsys USB 3.x host HAPS platform has a class code of 742 * PCI_CLASS_SERIAL_USB_XHCI, and xhci driver can claim it. However, these 743 * devices should use dwc3-haps driver. Change these devices' class code to 744 * PCI_CLASS_SERIAL_USB_DEVICE to prevent the xhci-pci driver from claiming 745 * them. 746 */ 747 static void quirk_synopsys_haps(struct pci_dev *pdev) 748 { 749 u32 class = pdev->class; 750 751 switch (pdev->device) { 752 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3: 753 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB3_AXI: 754 case PCI_DEVICE_ID_SYNOPSYS_HAPSUSB31: 755 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE; 756 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n", 757 class, pdev->class); 758 break; 759 } 760 } 761 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, PCI_ANY_ID, 762 PCI_CLASS_SERIAL_USB_XHCI, 0, 763 quirk_synopsys_haps); 764 765 /* 766 * Let's make the southbridge information explicit instead of having to 767 * worry about people probing the ACPI areas, for example.. (Yes, it 768 * happens, and if you read the wrong ACPI register it will put the machine 769 * to sleep with no way of waking it up again. Bummer). 770 * 771 * ALI M7101: Two IO regions pointed to by words at 772 * 0xE0 (64 bytes of ACPI registers) 773 * 0xE2 (32 bytes of SMB registers) 774 */ 775 static void quirk_ali7101_acpi(struct pci_dev *dev) 776 { 777 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI"); 778 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB"); 779 } 780 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi); 781 782 static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 783 { 784 u32 devres; 785 u32 mask, size, base; 786 787 pci_read_config_dword(dev, port, &devres); 788 if ((devres & enable) != enable) 789 return; 790 mask = (devres >> 16) & 15; 791 base = devres & 0xffff; 792 size = 16; 793 for (;;) { 794 unsigned int bit = size >> 1; 795 if ((bit & mask) == bit) 796 break; 797 size = bit; 798 } 799 /* 800 * For now we only print it out. Eventually we'll want to 801 * reserve it (at least if it's in the 0x1000+ range), but 802 * let's get enough confirmation reports first. 803 */ 804 base &= -size; 805 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1); 806 } 807 808 static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable) 809 { 810 u32 devres; 811 u32 mask, size, base; 812 813 pci_read_config_dword(dev, port, &devres); 814 if ((devres & enable) != enable) 815 return; 816 base = devres & 0xffff0000; 817 mask = (devres & 0x3f) << 16; 818 size = 128 << 16; 819 for (;;) { 820 unsigned int bit = size >> 1; 821 if ((bit & mask) == bit) 822 break; 823 size = bit; 824 } 825 826 /* 827 * For now we only print it out. Eventually we'll want to 828 * reserve it, but let's get enough confirmation reports first. 829 */ 830 base &= -size; 831 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1); 832 } 833 834 /* 835 * PIIX4 ACPI: Two IO regions pointed to by longwords at 836 * 0x40 (64 bytes of ACPI registers) 837 * 0x90 (16 bytes of SMB registers) 838 * and a few strange programmable PIIX4 device resources. 839 */ 840 static void quirk_piix4_acpi(struct pci_dev *dev) 841 { 842 u32 res_a; 843 844 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI"); 845 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB"); 846 847 /* Device resource A has enables for some of the other ones */ 848 pci_read_config_dword(dev, 0x5c, &res_a); 849 850 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21); 851 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21); 852 853 /* Device resource D is just bitfields for static resources */ 854 855 /* Device 12 enabled? */ 856 if (res_a & (1 << 29)) { 857 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20); 858 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7); 859 } 860 /* Device 13 enabled? */ 861 if (res_a & (1 << 30)) { 862 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20); 863 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7); 864 } 865 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20); 866 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20); 867 } 868 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi); 869 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi); 870 871 #define ICH_PMBASE 0x40 872 #define ICH_ACPI_CNTL 0x44 873 #define ICH4_ACPI_EN 0x10 874 #define ICH6_ACPI_EN 0x80 875 #define ICH4_GPIOBASE 0x58 876 #define ICH4_GPIO_CNTL 0x5c 877 #define ICH4_GPIO_EN 0x10 878 #define ICH6_GPIOBASE 0x48 879 #define ICH6_GPIO_CNTL 0x4c 880 #define ICH6_GPIO_EN 0x10 881 882 /* 883 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at 884 * 0x40 (128 bytes of ACPI, GPIO & TCO registers) 885 * 0x58 (64 bytes of GPIO I/O space) 886 */ 887 static void quirk_ich4_lpc_acpi(struct pci_dev *dev) 888 { 889 u8 enable; 890 891 /* 892 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict 893 * with low legacy (and fixed) ports. We don't know the decoding 894 * priority and can't tell whether the legacy device or the one created 895 * here is really at that address. This happens on boards with broken 896 * BIOSes. 897 */ 898 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 899 if (enable & ICH4_ACPI_EN) 900 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 901 "ICH4 ACPI/GPIO/TCO"); 902 903 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable); 904 if (enable & ICH4_GPIO_EN) 905 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 906 "ICH4 GPIO"); 907 } 908 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi); 909 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi); 910 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi); 911 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi); 912 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi); 913 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi); 914 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi); 915 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi); 916 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi); 917 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi); 918 919 static void ich6_lpc_acpi_gpio(struct pci_dev *dev) 920 { 921 u8 enable; 922 923 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable); 924 if (enable & ICH6_ACPI_EN) 925 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES, 926 "ICH6 ACPI/GPIO/TCO"); 927 928 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable); 929 if (enable & ICH6_GPIO_EN) 930 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1, 931 "ICH6 GPIO"); 932 } 933 934 static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 935 const char *name, int dynsize) 936 { 937 u32 val; 938 u32 size, base; 939 940 pci_read_config_dword(dev, reg, &val); 941 942 /* Enabled? */ 943 if (!(val & 1)) 944 return; 945 base = val & 0xfffc; 946 if (dynsize) { 947 /* 948 * This is not correct. It is 16, 32 or 64 bytes depending on 949 * register D31:F0:ADh bits 5:4. 950 * 951 * But this gets us at least _part_ of it. 952 */ 953 size = 16; 954 } else { 955 size = 128; 956 } 957 base &= ~(size-1); 958 959 /* 960 * Just print it out for now. We should reserve it after more 961 * debugging. 962 */ 963 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1); 964 } 965 966 static void quirk_ich6_lpc(struct pci_dev *dev) 967 { 968 /* Shared ACPI/GPIO decode with all ICH6+ */ 969 ich6_lpc_acpi_gpio(dev); 970 971 /* ICH6-specific generic IO decode */ 972 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0); 973 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1); 974 } 975 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc); 976 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc); 977 978 static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned int reg, 979 const char *name) 980 { 981 u32 val; 982 u32 mask, base; 983 984 pci_read_config_dword(dev, reg, &val); 985 986 /* Enabled? */ 987 if (!(val & 1)) 988 return; 989 990 /* IO base in bits 15:2, mask in bits 23:18, both are dword-based */ 991 base = val & 0xfffc; 992 mask = (val >> 16) & 0xfc; 993 mask |= 3; 994 995 /* 996 * Just print it out for now. We should reserve it after more 997 * debugging. 998 */ 999 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask); 1000 } 1001 1002 /* ICH7-10 has the same common LPC generic IO decode registers */ 1003 static void quirk_ich7_lpc(struct pci_dev *dev) 1004 { 1005 /* We share the common ACPI/GPIO decode with ICH6 */ 1006 ich6_lpc_acpi_gpio(dev); 1007 1008 /* And have 4 ICH7+ generic decodes */ 1009 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1"); 1010 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2"); 1011 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3"); 1012 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4"); 1013 } 1014 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc); 1015 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc); 1016 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc); 1017 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc); 1018 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc); 1019 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc); 1020 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc); 1021 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc); 1022 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc); 1023 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc); 1024 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc); 1025 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc); 1026 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc); 1027 1028 /* 1029 * VIA ACPI: One IO region pointed to by longword at 1030 * 0x48 or 0x20 (256 bytes of ACPI registers) 1031 */ 1032 static void quirk_vt82c586_acpi(struct pci_dev *dev) 1033 { 1034 if (dev->revision & 0x10) 1035 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES, 1036 "vt82c586 ACPI"); 1037 } 1038 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi); 1039 1040 /* 1041 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at 1042 * 0x48 (256 bytes of ACPI registers) 1043 * 0x70 (128 bytes of hardware monitoring register) 1044 * 0x90 (16 bytes of SMB registers) 1045 */ 1046 static void quirk_vt82c686_acpi(struct pci_dev *dev) 1047 { 1048 quirk_vt82c586_acpi(dev); 1049 1050 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1, 1051 "vt82c686 HW-mon"); 1052 1053 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB"); 1054 } 1055 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi); 1056 1057 /* 1058 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at 1059 * 0x88 (128 bytes of power management registers) 1060 * 0xd0 (16 bytes of SMB registers) 1061 */ 1062 static void quirk_vt8235_acpi(struct pci_dev *dev) 1063 { 1064 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM"); 1065 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB"); 1066 } 1067 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi); 1068 1069 /* 1070 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast 1071 * back-to-back: Disable fast back-to-back on the secondary bus segment 1072 */ 1073 static void quirk_xio2000a(struct pci_dev *dev) 1074 { 1075 struct pci_dev *pdev; 1076 u16 command; 1077 1078 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n"); 1079 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) { 1080 pci_read_config_word(pdev, PCI_COMMAND, &command); 1081 if (command & PCI_COMMAND_FAST_BACK) 1082 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK); 1083 } 1084 } 1085 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A, 1086 quirk_xio2000a); 1087 1088 #ifdef CONFIG_X86_IO_APIC 1089 1090 #include <asm/io_apic.h> 1091 1092 /* 1093 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip 1094 * devices to the external APIC. 1095 * 1096 * TODO: When we have device-specific interrupt routers, this code will go 1097 * away from quirks. 1098 */ 1099 static void quirk_via_ioapic(struct pci_dev *dev) 1100 { 1101 u8 tmp; 1102 1103 if (nr_ioapics < 1) 1104 tmp = 0; /* nothing routed to external APIC */ 1105 else 1106 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */ 1107 1108 pci_info(dev, "%s VIA external APIC routing\n", 1109 tmp ? "Enabling" : "Disabling"); 1110 1111 /* Offset 0x58: External APIC IRQ output control */ 1112 pci_write_config_byte(dev, 0x58, tmp); 1113 } 1114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1115 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic); 1116 1117 /* 1118 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit. 1119 * This leads to doubled level interrupt rates. 1120 * Set this bit to get rid of cycle wastage. 1121 * Otherwise uncritical. 1122 */ 1123 static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev) 1124 { 1125 u8 misc_control2; 1126 #define BYPASS_APIC_DEASSERT 8 1127 1128 pci_read_config_byte(dev, 0x5B, &misc_control2); 1129 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) { 1130 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n"); 1131 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT); 1132 } 1133 } 1134 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1135 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert); 1136 1137 /* 1138 * The AMD IO-APIC can hang the box when an APIC IRQ is masked. 1139 * We check all revs >= B0 (yet not in the pre production!) as the bug 1140 * is currently marked NoFix 1141 * 1142 * We have multiple reports of hangs with this chipset that went away with 1143 * noapic specified. For the moment we assume it's the erratum. We may be wrong 1144 * of course. However the advice is demonstrably good even if so. 1145 */ 1146 static void quirk_amd_ioapic(struct pci_dev *dev) 1147 { 1148 if (dev->revision >= 0x02) { 1149 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n"); 1150 pci_warn(dev, " : booting with the \"noapic\" option\n"); 1151 } 1152 } 1153 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic); 1154 #endif /* CONFIG_X86_IO_APIC */ 1155 1156 #if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS) 1157 1158 static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev) 1159 { 1160 /* Fix for improper SR-IOV configuration on Cavium cn88xx RNM device */ 1161 if (dev->subsystem_device == 0xa118) 1162 dev->sriov->link = dev->devfn; 1163 } 1164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link); 1165 #endif 1166 1167 /* 1168 * Some settings of MMRBC can lead to data corruption so block changes. 1169 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide 1170 */ 1171 static void quirk_amd_8131_mmrbc(struct pci_dev *dev) 1172 { 1173 if (dev->subordinate && dev->revision <= 0x12) { 1174 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n", 1175 dev->revision); 1176 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC; 1177 } 1178 } 1179 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc); 1180 1181 /* 1182 * FIXME: it is questionable that quirk_via_acpi() is needed. It shows up 1183 * as an ISA bridge, and does not support the PCI_INTERRUPT_LINE register 1184 * at all. Therefore it seems like setting the pci_dev's IRQ to the value 1185 * of the ACPI SCI interrupt is only done for convenience. 1186 * -jgarzik 1187 */ 1188 static void quirk_via_acpi(struct pci_dev *d) 1189 { 1190 u8 irq; 1191 1192 /* VIA ACPI device: SCI IRQ line in PCI config byte 0x42 */ 1193 pci_read_config_byte(d, 0x42, &irq); 1194 irq &= 0xf; 1195 if (irq && (irq != 2)) 1196 d->irq = irq; 1197 } 1198 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi); 1199 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi); 1200 1201 /* VIA bridges which have VLink */ 1202 static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18; 1203 1204 static void quirk_via_bridge(struct pci_dev *dev) 1205 { 1206 /* See what bridge we have and find the device ranges */ 1207 switch (dev->device) { 1208 case PCI_DEVICE_ID_VIA_82C686: 1209 /* 1210 * The VT82C686 is special; it attaches to PCI and can have 1211 * any device number. All its subdevices are functions of 1212 * that single device. 1213 */ 1214 via_vlink_dev_lo = PCI_SLOT(dev->devfn); 1215 via_vlink_dev_hi = PCI_SLOT(dev->devfn); 1216 break; 1217 case PCI_DEVICE_ID_VIA_8237: 1218 case PCI_DEVICE_ID_VIA_8237A: 1219 via_vlink_dev_lo = 15; 1220 break; 1221 case PCI_DEVICE_ID_VIA_8235: 1222 via_vlink_dev_lo = 16; 1223 break; 1224 case PCI_DEVICE_ID_VIA_8231: 1225 case PCI_DEVICE_ID_VIA_8233_0: 1226 case PCI_DEVICE_ID_VIA_8233A: 1227 case PCI_DEVICE_ID_VIA_8233C_0: 1228 via_vlink_dev_lo = 17; 1229 break; 1230 } 1231 } 1232 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge); 1233 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge); 1234 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge); 1235 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge); 1236 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge); 1237 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge); 1238 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge); 1239 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge); 1240 1241 /* 1242 * quirk_via_vlink - VIA VLink IRQ number update 1243 * @dev: PCI device 1244 * 1245 * If the device we are dealing with is on a PIC IRQ we need to ensure that 1246 * the IRQ line register which usually is not relevant for PCI cards, is 1247 * actually written so that interrupts get sent to the right place. 1248 * 1249 * We only do this on systems where a VIA south bridge was detected, and 1250 * only for VIA devices on the motherboard (see quirk_via_bridge above). 1251 */ 1252 static void quirk_via_vlink(struct pci_dev *dev) 1253 { 1254 u8 irq, new_irq; 1255 1256 /* Check if we have VLink at all */ 1257 if (via_vlink_dev_lo == -1) 1258 return; 1259 1260 new_irq = dev->irq; 1261 1262 /* Don't quirk interrupts outside the legacy IRQ range */ 1263 if (!new_irq || new_irq > 15) 1264 return; 1265 1266 /* Internal device ? */ 1267 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi || 1268 PCI_SLOT(dev->devfn) < via_vlink_dev_lo) 1269 return; 1270 1271 /* 1272 * This is an internal VLink device on a PIC interrupt. The BIOS 1273 * ought to have set this but may not have, so we redo it. 1274 */ 1275 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq); 1276 if (new_irq != irq) { 1277 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n", 1278 irq, new_irq); 1279 udelay(15); /* unknown if delay really needed */ 1280 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq); 1281 } 1282 } 1283 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink); 1284 1285 /* 1286 * VIA VT82C598 has its device ID settable and many BIOSes set it to the ID 1287 * of VT82C597 for backward compatibility. We need to switch it off to be 1288 * able to recognize the real type of the chip. 1289 */ 1290 static void quirk_vt82c598_id(struct pci_dev *dev) 1291 { 1292 pci_write_config_byte(dev, 0xfc, 0); 1293 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device); 1294 } 1295 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id); 1296 1297 /* 1298 * CardBus controllers have a legacy base address that enables them to 1299 * respond as i82365 pcmcia controllers. We don't want them to do this 1300 * even if the Linux CardBus driver is not loaded, because the Linux i82365 1301 * driver does not (and should not) handle CardBus. 1302 */ 1303 static void quirk_cardbus_legacy(struct pci_dev *dev) 1304 { 1305 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0); 1306 } 1307 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID, 1308 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1309 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID, 1310 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy); 1311 1312 /* 1313 * Following the PCI ordering rules is optional on the AMD762. I'm not sure 1314 * what the designers were smoking but let's not inhale... 1315 * 1316 * To be fair to AMD, it follows the spec by default, it's BIOS people who 1317 * turn it off! 1318 */ 1319 static void quirk_amd_ordering(struct pci_dev *dev) 1320 { 1321 u32 pcic; 1322 pci_read_config_dword(dev, 0x4C, &pcic); 1323 if ((pcic & 6) != 6) { 1324 pcic |= 6; 1325 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n"); 1326 pci_write_config_dword(dev, 0x4C, pcic); 1327 pci_read_config_dword(dev, 0x84, &pcic); 1328 pcic |= (1 << 23); /* Required in this mode */ 1329 pci_write_config_dword(dev, 0x84, pcic); 1330 } 1331 } 1332 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1333 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering); 1334 1335 /* 1336 * DreamWorks-provided workaround for Dunord I-3000 problem 1337 * 1338 * This card decodes and responds to addresses not apparently assigned to 1339 * it. We force a larger allocation to ensure that nothing gets put too 1340 * close to it. 1341 */ 1342 static void quirk_dunord(struct pci_dev *dev) 1343 { 1344 struct resource *r = &dev->resource[1]; 1345 1346 r->flags |= IORESOURCE_UNSET; 1347 resource_set_range(r, 0, SZ_16M); 1348 } 1349 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord); 1350 1351 /* 1352 * i82380FB mobile docking controller: its PCI-to-PCI bridge is subtractive 1353 * decoding (transparent), and does indicate this in the ProgIf. 1354 * Unfortunately, the ProgIf value is wrong - 0x80 instead of 0x01. 1355 */ 1356 static void quirk_transparent_bridge(struct pci_dev *dev) 1357 { 1358 dev->transparent = 1; 1359 } 1360 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge); 1361 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge); 1362 1363 /* 1364 * Enabling Link Bandwidth Management Interrupts (BW notifications) can cause 1365 * boot hangs on P45. 1366 */ 1367 static void quirk_p45_bw_notifications(struct pci_dev *dev) 1368 { 1369 dev->no_bw_notif = 1; 1370 } 1371 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2e21, quirk_p45_bw_notifications); 1372 1373 /* 1374 * Common misconfiguration of the MediaGX/Geode PCI master that will reduce 1375 * PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1 datasheets 1376 * found at http://www.national.com/analog for info on what these bits do. 1377 * <christer@weinigel.se> 1378 */ 1379 static void quirk_mediagx_master(struct pci_dev *dev) 1380 { 1381 u8 reg; 1382 1383 pci_read_config_byte(dev, 0x41, ®); 1384 if (reg & 2) { 1385 reg &= ~2; 1386 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n", 1387 reg); 1388 pci_write_config_byte(dev, 0x41, reg); 1389 } 1390 } 1391 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1392 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master); 1393 1394 /* 1395 * Ensure C0 rev restreaming is off. This is normally done by the BIOS but 1396 * in the odd case it is not the results are corruption hence the presence 1397 * of a Linux check. 1398 */ 1399 static void quirk_disable_pxb(struct pci_dev *pdev) 1400 { 1401 u16 config; 1402 1403 if (pdev->revision != 0x04) /* Only C0 requires this */ 1404 return; 1405 pci_read_config_word(pdev, 0x40, &config); 1406 if (config & (1<<6)) { 1407 config &= ~(1<<6); 1408 pci_write_config_word(pdev, 0x40, config); 1409 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n"); 1410 } 1411 } 1412 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1413 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb); 1414 1415 static void quirk_amd_ide_mode(struct pci_dev *pdev) 1416 { 1417 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */ 1418 u8 tmp; 1419 1420 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp); 1421 if (tmp == 0x01) { 1422 pci_read_config_byte(pdev, 0x40, &tmp); 1423 pci_write_config_byte(pdev, 0x40, tmp|1); 1424 pci_write_config_byte(pdev, 0x9, 1); 1425 pci_write_config_byte(pdev, 0xa, 6); 1426 pci_write_config_byte(pdev, 0x40, tmp); 1427 1428 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI; 1429 pci_info(pdev, "set SATA to AHCI mode\n"); 1430 } 1431 } 1432 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1433 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode); 1434 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1435 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode); 1436 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1437 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode); 1438 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1439 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode); 1440 1441 /* Serverworks CSB5 IDE does not fully support native mode */ 1442 static void quirk_svwks_csb5ide(struct pci_dev *pdev) 1443 { 1444 u8 prog; 1445 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1446 if (prog & 5) { 1447 prog &= ~5; 1448 pdev->class &= ~5; 1449 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1450 /* PCI layer will sort out resources */ 1451 } 1452 } 1453 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide); 1454 1455 /* Intel 82801CAM ICH3-M datasheet says IDE modes must be the same */ 1456 static void quirk_ide_samemode(struct pci_dev *pdev) 1457 { 1458 u8 prog; 1459 1460 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog); 1461 1462 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) { 1463 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n"); 1464 prog &= ~5; 1465 pdev->class &= ~5; 1466 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog); 1467 } 1468 } 1469 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode); 1470 1471 /* Some ATA devices break if put into D3 */ 1472 static void quirk_no_ata_d3(struct pci_dev *pdev) 1473 { 1474 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3; 1475 } 1476 /* Quirk the legacy ATA devices only. The AHCI ones are ok */ 1477 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID, 1478 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1479 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 1480 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1481 /* ALi loses some register settings that we cannot then restore */ 1482 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, 1483 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1484 /* VIA comes back fine but we need to keep it alive or ACPI GTM failures 1485 occur when mode detecting */ 1486 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID, 1487 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3); 1488 1489 /* 1490 * This was originally an Alpha-specific thing, but it really fits here. 1491 * The i82375 PCI/EISA bridge appears as non-classified. Fix that. 1492 */ 1493 static void quirk_eisa_bridge(struct pci_dev *dev) 1494 { 1495 dev->class = PCI_CLASS_BRIDGE_EISA << 8; 1496 } 1497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge); 1498 1499 /* 1500 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge 1501 * is not activated. The myth is that Asus said that they do not want the 1502 * users to be irritated by just another PCI Device in the Win98 device 1503 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors 1504 * package 2.7.0 for details) 1505 * 1506 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC 1507 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it 1508 * becomes necessary to do this tweak in two steps -- the chosen trigger 1509 * is either the Host bridge (preferred) or on-board VGA controller. 1510 * 1511 * Note that we used to unhide the SMBus that way on Toshiba laptops 1512 * (Satellite A40 and Tecra M2) but then found that the thermal management 1513 * was done by SMM code, which could cause unsynchronized concurrent 1514 * accesses to the SMBus registers, with potentially bad effects. Thus you 1515 * should be very careful when adding new entries: if SMM is accessing the 1516 * Intel SMBus, this is a very good reason to leave it hidden. 1517 * 1518 * Likewise, many recent laptops use ACPI for thermal management. If the 1519 * ACPI DSDT code accesses the SMBus, then Linux should not access it 1520 * natively, and keeping the SMBus hidden is the right thing to do. If you 1521 * are about to add an entry in the table below, please first disassemble 1522 * the DSDT and double-check that there is no code accessing the SMBus. 1523 */ 1524 static int asus_hides_smbus; 1525 1526 static void asus_hides_smbus_hostbridge(struct pci_dev *dev) 1527 { 1528 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1529 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB) 1530 switch (dev->subsystem_device) { 1531 case 0x8025: /* P4B-LX */ 1532 case 0x8070: /* P4B */ 1533 case 0x8088: /* P4B533 */ 1534 case 0x1626: /* L3C notebook */ 1535 asus_hides_smbus = 1; 1536 } 1537 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) 1538 switch (dev->subsystem_device) { 1539 case 0x80b1: /* P4GE-V */ 1540 case 0x80b2: /* P4PE */ 1541 case 0x8093: /* P4B533-V */ 1542 asus_hides_smbus = 1; 1543 } 1544 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB) 1545 switch (dev->subsystem_device) { 1546 case 0x8030: /* P4T533 */ 1547 asus_hides_smbus = 1; 1548 } 1549 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0) 1550 switch (dev->subsystem_device) { 1551 case 0x8070: /* P4G8X Deluxe */ 1552 asus_hides_smbus = 1; 1553 } 1554 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH) 1555 switch (dev->subsystem_device) { 1556 case 0x80c9: /* PU-DLS */ 1557 asus_hides_smbus = 1; 1558 } 1559 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB) 1560 switch (dev->subsystem_device) { 1561 case 0x1751: /* M2N notebook */ 1562 case 0x1821: /* M5N notebook */ 1563 case 0x1897: /* A6L notebook */ 1564 asus_hides_smbus = 1; 1565 } 1566 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1567 switch (dev->subsystem_device) { 1568 case 0x184b: /* W1N notebook */ 1569 case 0x186a: /* M6Ne notebook */ 1570 asus_hides_smbus = 1; 1571 } 1572 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1573 switch (dev->subsystem_device) { 1574 case 0x80f2: /* P4P800-X */ 1575 asus_hides_smbus = 1; 1576 } 1577 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB) 1578 switch (dev->subsystem_device) { 1579 case 0x1882: /* M6V notebook */ 1580 case 0x1977: /* A6VA notebook */ 1581 asus_hides_smbus = 1; 1582 } 1583 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) { 1584 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1585 switch (dev->subsystem_device) { 1586 case 0x088C: /* HP Compaq nc8000 */ 1587 case 0x0890: /* HP Compaq nc6000 */ 1588 asus_hides_smbus = 1; 1589 } 1590 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB) 1591 switch (dev->subsystem_device) { 1592 case 0x12bc: /* HP D330L */ 1593 case 0x12bd: /* HP D530 */ 1594 case 0x006a: /* HP Compaq nx9500 */ 1595 asus_hides_smbus = 1; 1596 } 1597 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB) 1598 switch (dev->subsystem_device) { 1599 case 0x12bf: /* HP xw4100 */ 1600 asus_hides_smbus = 1; 1601 } 1602 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) { 1603 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1604 switch (dev->subsystem_device) { 1605 case 0xC00C: /* Samsung P35 notebook */ 1606 asus_hides_smbus = 1; 1607 } 1608 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) { 1609 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB) 1610 switch (dev->subsystem_device) { 1611 case 0x0058: /* Compaq Evo N620c */ 1612 asus_hides_smbus = 1; 1613 } 1614 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3) 1615 switch (dev->subsystem_device) { 1616 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */ 1617 /* Motherboard doesn't have Host bridge 1618 * subvendor/subdevice IDs, therefore checking 1619 * its on-board VGA controller */ 1620 asus_hides_smbus = 1; 1621 } 1622 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2) 1623 switch (dev->subsystem_device) { 1624 case 0x00b8: /* Compaq Evo D510 CMT */ 1625 case 0x00b9: /* Compaq Evo D510 SFF */ 1626 case 0x00ba: /* Compaq Evo D510 USDT */ 1627 /* Motherboard doesn't have Host bridge 1628 * subvendor/subdevice IDs and on-board VGA 1629 * controller is disabled if an AGP card is 1630 * inserted, therefore checking USB UHCI 1631 * Controller #1 */ 1632 asus_hides_smbus = 1; 1633 } 1634 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC) 1635 switch (dev->subsystem_device) { 1636 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */ 1637 /* Motherboard doesn't have host bridge 1638 * subvendor/subdevice IDs, therefore checking 1639 * its on-board VGA controller */ 1640 asus_hides_smbus = 1; 1641 } 1642 } 1643 } 1644 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge); 1645 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge); 1646 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge); 1647 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge); 1648 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge); 1649 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge); 1650 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge); 1651 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge); 1652 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge); 1653 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge); 1654 1655 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge); 1656 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge); 1657 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge); 1658 1659 static void asus_hides_smbus_lpc(struct pci_dev *dev) 1660 { 1661 u16 val; 1662 1663 if (likely(!asus_hides_smbus)) 1664 return; 1665 1666 pci_read_config_word(dev, 0xF2, &val); 1667 if (val & 0x8) { 1668 pci_write_config_word(dev, 0xF2, val & (~0x8)); 1669 pci_read_config_word(dev, 0xF2, &val); 1670 if (val & 0x8) 1671 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n", 1672 val); 1673 else 1674 pci_info(dev, "Enabled i801 SMBus device\n"); 1675 } 1676 } 1677 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1678 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1679 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1680 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1681 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1682 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1683 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1684 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc); 1685 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc); 1686 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc); 1687 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc); 1688 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc); 1689 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc); 1690 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc); 1691 1692 /* It appears we just have one such device. If not, we have a warning */ 1693 static void __iomem *asus_rcba_base; 1694 static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev) 1695 { 1696 u32 rcba; 1697 1698 if (likely(!asus_hides_smbus)) 1699 return; 1700 WARN_ON(asus_rcba_base); 1701 1702 pci_read_config_dword(dev, 0xF0, &rcba); 1703 /* use bits 31:14, 16 kB aligned */ 1704 asus_rcba_base = ioremap(rcba & 0xFFFFC000, 0x4000); 1705 if (asus_rcba_base == NULL) 1706 return; 1707 } 1708 1709 static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev) 1710 { 1711 u32 val; 1712 1713 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1714 return; 1715 1716 /* read the Function Disable register, dword mode only */ 1717 val = readl(asus_rcba_base + 0x3418); 1718 1719 /* enable the SMBus device */ 1720 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); 1721 } 1722 1723 static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev) 1724 { 1725 if (likely(!asus_hides_smbus || !asus_rcba_base)) 1726 return; 1727 1728 iounmap(asus_rcba_base); 1729 asus_rcba_base = NULL; 1730 pci_info(dev, "Enabled ICH6/i801 SMBus device\n"); 1731 } 1732 1733 static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev) 1734 { 1735 asus_hides_smbus_lpc_ich6_suspend(dev); 1736 asus_hides_smbus_lpc_ich6_resume_early(dev); 1737 asus_hides_smbus_lpc_ich6_resume(dev); 1738 } 1739 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6); 1740 DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend); 1741 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume); 1742 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early); 1743 1744 /* SiS 96x south bridge: BIOS typically hides SMBus device... */ 1745 static void quirk_sis_96x_smbus(struct pci_dev *dev) 1746 { 1747 u8 val = 0; 1748 pci_read_config_byte(dev, 0x77, &val); 1749 if (val & 0x10) { 1750 pci_info(dev, "Enabling SiS 96x SMBus\n"); 1751 pci_write_config_byte(dev, 0x77, val & ~0x10); 1752 } 1753 } 1754 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1755 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1756 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1757 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1758 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus); 1759 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus); 1760 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus); 1761 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus); 1762 1763 /* 1764 * ... This is further complicated by the fact that some SiS96x south 1765 * bridges pretend to be 85C503/5513 instead. In that case see if we 1766 * spotted a compatible north bridge to make sure. 1767 * (pci_find_device() doesn't work yet) 1768 * 1769 * We can also enable the sis96x bit in the discovery register.. 1770 */ 1771 #define SIS_DETECT_REGISTER 0x40 1772 1773 static void quirk_sis_503(struct pci_dev *dev) 1774 { 1775 u8 reg; 1776 u16 devid; 1777 1778 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®); 1779 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6)); 1780 pci_read_config_word(dev, PCI_DEVICE_ID, &devid); 1781 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) { 1782 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg); 1783 return; 1784 } 1785 1786 /* 1787 * Ok, it now shows up as a 96x. Run the 96x quirk by hand in case 1788 * it has already been processed. (Depends on link order, which is 1789 * apparently not guaranteed) 1790 */ 1791 dev->device = devid; 1792 quirk_sis_96x_smbus(dev); 1793 } 1794 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1795 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503); 1796 1797 /* 1798 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller 1799 * and MC97 modem controller are disabled when a second PCI soundcard is 1800 * present. This patch, tweaking the VT8237 ISA bridge, enables them. 1801 * -- bjd 1802 */ 1803 static void asus_hides_ac97_lpc(struct pci_dev *dev) 1804 { 1805 u8 val; 1806 int asus_hides_ac97 = 0; 1807 1808 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) { 1809 if (dev->device == PCI_DEVICE_ID_VIA_8237) 1810 asus_hides_ac97 = 1; 1811 } 1812 1813 if (!asus_hides_ac97) 1814 return; 1815 1816 pci_read_config_byte(dev, 0x50, &val); 1817 if (val & 0xc0) { 1818 pci_write_config_byte(dev, 0x50, val & (~0xc0)); 1819 pci_read_config_byte(dev, 0x50, &val); 1820 if (val & 0xc0) 1821 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n", 1822 val); 1823 else 1824 pci_info(dev, "Enabled onboard AC97/MC97 devices\n"); 1825 } 1826 } 1827 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1828 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc); 1829 1830 #if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE) 1831 1832 /* 1833 * If we are using libata we can drive this chip properly but must do this 1834 * early on to make the additional device appear during the PCI scanning. 1835 */ 1836 static void quirk_jmicron_ata(struct pci_dev *pdev) 1837 { 1838 u32 conf1, conf5, class; 1839 u8 hdr; 1840 1841 /* Only poke fn 0 */ 1842 if (PCI_FUNC(pdev->devfn)) 1843 return; 1844 1845 pci_read_config_dword(pdev, 0x40, &conf1); 1846 pci_read_config_dword(pdev, 0x80, &conf5); 1847 1848 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */ 1849 conf5 &= ~(1 << 24); /* Clear bit 24 */ 1850 1851 switch (pdev->device) { 1852 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */ 1853 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */ 1854 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */ 1855 /* The controller should be in single function ahci mode */ 1856 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */ 1857 break; 1858 1859 case PCI_DEVICE_ID_JMICRON_JMB365: 1860 case PCI_DEVICE_ID_JMICRON_JMB366: 1861 /* Redirect IDE second PATA port to the right spot */ 1862 conf5 |= (1 << 24); 1863 fallthrough; 1864 case PCI_DEVICE_ID_JMICRON_JMB361: 1865 case PCI_DEVICE_ID_JMICRON_JMB363: 1866 case PCI_DEVICE_ID_JMICRON_JMB369: 1867 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */ 1868 /* Set the class codes correctly and then direct IDE 0 */ 1869 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */ 1870 break; 1871 1872 case PCI_DEVICE_ID_JMICRON_JMB368: 1873 /* The controller should be in single function IDE mode */ 1874 conf1 |= 0x00C00000; /* Set 22, 23 */ 1875 break; 1876 } 1877 1878 pci_write_config_dword(pdev, 0x40, conf1); 1879 pci_write_config_dword(pdev, 0x80, conf5); 1880 1881 /* Update pdev accordingly */ 1882 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr); 1883 pdev->hdr_type = hdr & PCI_HEADER_TYPE_MASK; 1884 pdev->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr); 1885 1886 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class); 1887 pdev->class = class >> 8; 1888 } 1889 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1890 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1891 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1892 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1893 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1894 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1895 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1896 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1897 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1898 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata); 1899 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata); 1900 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata); 1901 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata); 1902 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata); 1903 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata); 1904 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata); 1905 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata); 1906 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata); 1907 1908 #endif 1909 1910 static void quirk_jmicron_async_suspend(struct pci_dev *dev) 1911 { 1912 if (dev->multifunction) { 1913 device_disable_async_suspend(&dev->dev); 1914 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n"); 1915 } 1916 } 1917 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend); 1918 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend); 1919 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend); 1920 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend); 1921 1922 #ifdef CONFIG_X86_IO_APIC 1923 static void quirk_alder_ioapic(struct pci_dev *pdev) 1924 { 1925 int i; 1926 1927 if ((pdev->class >> 8) != 0xff00) 1928 return; 1929 1930 /* 1931 * The first BAR is the location of the IO-APIC... we must 1932 * not touch this (and it's already covered by the fixmap), so 1933 * forcibly insert it into the resource tree. 1934 */ 1935 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0)) 1936 insert_resource(&iomem_resource, &pdev->resource[0]); 1937 1938 /* 1939 * The next five BARs all seem to be rubbish, so just clean 1940 * them out. 1941 */ 1942 for (i = 1; i < PCI_STD_NUM_BARS; i++) 1943 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i])); 1944 } 1945 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic); 1946 #endif 1947 1948 static void quirk_no_msi(struct pci_dev *dev) 1949 { 1950 pci_info(dev, "avoiding MSI to work around a hardware defect\n"); 1951 dev->no_msi = 1; 1952 } 1953 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4386, quirk_no_msi); 1954 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4387, quirk_no_msi); 1955 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4388, quirk_no_msi); 1956 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4389, quirk_no_msi); 1957 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438a, quirk_no_msi); 1958 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x438b, quirk_no_msi); 1959 1960 static void quirk_pcie_mch(struct pci_dev *pdev) 1961 { 1962 pdev->no_msi = 1; 1963 } 1964 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch); 1965 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch); 1966 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch); 1967 1968 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch); 1969 1970 /* 1971 * HiSilicon KunPeng920 and KunPeng930 have devices appear as PCI but are 1972 * actually on the AMBA bus. These fake PCI devices can support SVA via 1973 * SMMU stall feature, by setting dma-can-stall for ACPI platforms. 1974 * 1975 * Normally stalling must not be enabled for PCI devices, since it would 1976 * break the PCI requirement for free-flowing writes and may lead to 1977 * deadlock. We expect PCI devices to support ATS and PRI if they want to 1978 * be fault-tolerant, so there's no ACPI binding to describe anything else, 1979 * even when a "PCI" device turns out to be a regular old SoC device 1980 * dressed up as a RCiEP and normal rules don't apply. 1981 */ 1982 static void quirk_huawei_pcie_sva(struct pci_dev *pdev) 1983 { 1984 struct property_entry properties[] = { 1985 PROPERTY_ENTRY_BOOL("dma-can-stall"), 1986 {}, 1987 }; 1988 1989 if (pdev->revision != 0x21 && pdev->revision != 0x30) 1990 return; 1991 1992 pdev->pasid_no_tlp = 1; 1993 1994 /* 1995 * Set the dma-can-stall property on ACPI platforms. Device tree 1996 * can set it directly. 1997 */ 1998 if (!pdev->dev.of_node && 1999 device_create_managed_software_node(&pdev->dev, properties, NULL)) 2000 pci_warn(pdev, "could not add stall property"); 2001 } 2002 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa250, quirk_huawei_pcie_sva); 2003 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa251, quirk_huawei_pcie_sva); 2004 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa255, quirk_huawei_pcie_sva); 2005 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa256, quirk_huawei_pcie_sva); 2006 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa258, quirk_huawei_pcie_sva); 2007 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0xa259, quirk_huawei_pcie_sva); 2008 2009 /* 2010 * It's possible for the MSI to get corrupted if SHPC and ACPI are used 2011 * together on certain PXH-based systems. 2012 */ 2013 static void quirk_pcie_pxh(struct pci_dev *dev) 2014 { 2015 dev->no_msi = 1; 2016 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n"); 2017 } 2018 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh); 2019 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh); 2020 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh); 2021 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh); 2022 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh); 2023 2024 /* 2025 * Some Intel PCI Express chipsets have trouble with downstream device 2026 * power management. 2027 */ 2028 static void quirk_intel_pcie_pm(struct pci_dev *dev) 2029 { 2030 pci_pm_d3hot_delay = 120; 2031 dev->no_d1d2 = 1; 2032 } 2033 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm); 2034 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm); 2035 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm); 2036 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm); 2037 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm); 2038 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm); 2039 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm); 2040 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm); 2041 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm); 2042 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm); 2043 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm); 2044 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm); 2045 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm); 2046 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm); 2047 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm); 2048 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm); 2049 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm); 2050 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm); 2051 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm); 2052 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm); 2053 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm); 2054 2055 static void quirk_d3hot_delay(struct pci_dev *dev, unsigned int delay) 2056 { 2057 if (dev->d3hot_delay >= delay) 2058 return; 2059 2060 dev->d3hot_delay = delay; 2061 pci_info(dev, "extending delay after power-on from D3hot to %d msec\n", 2062 dev->d3hot_delay); 2063 } 2064 2065 static void quirk_radeon_pm(struct pci_dev *dev) 2066 { 2067 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE && 2068 dev->subsystem_device == 0x00e2) 2069 quirk_d3hot_delay(dev, 20); 2070 } 2071 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm); 2072 2073 /* 2074 * NVIDIA Ampere-based HDA controllers can wedge the whole device if a bus 2075 * reset is performed too soon after transition to D0, extend d3hot_delay 2076 * to previous effective default for all NVIDIA HDA controllers. 2077 */ 2078 static void quirk_nvidia_hda_pm(struct pci_dev *dev) 2079 { 2080 quirk_d3hot_delay(dev, 20); 2081 } 2082 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 2083 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, 2084 quirk_nvidia_hda_pm); 2085 2086 /* 2087 * Ryzen5/7 XHCI controllers fail upon resume from runtime suspend or s2idle. 2088 * https://bugzilla.kernel.org/show_bug.cgi?id=205587 2089 * 2090 * The kernel attempts to transition these devices to D3cold, but that seems 2091 * to be ineffective on the platforms in question; the PCI device appears to 2092 * remain on in D3hot state. The D3hot-to-D0 transition then requires an 2093 * extended delay in order to succeed. 2094 */ 2095 static void quirk_ryzen_xhci_d3hot(struct pci_dev *dev) 2096 { 2097 quirk_d3hot_delay(dev, 20); 2098 } 2099 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e0, quirk_ryzen_xhci_d3hot); 2100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x15e1, quirk_ryzen_xhci_d3hot); 2101 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x1639, quirk_ryzen_xhci_d3hot); 2102 2103 #ifdef CONFIG_X86_IO_APIC 2104 static int dmi_disable_ioapicreroute(const struct dmi_system_id *d) 2105 { 2106 noioapicreroute = 1; 2107 pr_info("%s detected: disable boot interrupt reroute\n", d->ident); 2108 2109 return 0; 2110 } 2111 2112 static const struct dmi_system_id boot_interrupt_dmi_table[] = { 2113 /* 2114 * Systems to exclude from boot interrupt reroute quirks 2115 */ 2116 { 2117 .callback = dmi_disable_ioapicreroute, 2118 .ident = "ASUSTek Computer INC. M2N-LR", 2119 .matches = { 2120 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."), 2121 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"), 2122 }, 2123 }, 2124 {} 2125 }; 2126 2127 /* 2128 * Boot interrupts on some chipsets cannot be turned off. For these chipsets, 2129 * remap the original interrupt in the Linux kernel to the boot interrupt, so 2130 * that a PCI device's interrupt handler is installed on the boot interrupt 2131 * line instead. 2132 */ 2133 static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev) 2134 { 2135 dmi_check_system(boot_interrupt_dmi_table); 2136 if (noioapicquirk || noioapicreroute) 2137 return; 2138 2139 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT; 2140 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n", 2141 dev->vendor, dev->device); 2142 } 2143 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2144 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2145 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2146 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2147 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2148 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2149 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2150 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2151 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel); 2152 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel); 2153 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel); 2154 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel); 2155 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel); 2156 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel); 2157 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel); 2158 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel); 2159 2160 /* 2161 * On some chipsets we can disable the generation of legacy INTx boot 2162 * interrupts. 2163 */ 2164 2165 /* 2166 * IO-APIC1 on 6300ESB generates boot interrupts, see Intel order no 2167 * 300641-004US, section 5.7.3. 2168 * 2169 * Core IO on Xeon E5 1600/2600/4600, see Intel order no 326509-003. 2170 * Core IO on Xeon E5 v2, see Intel order no 329188-003. 2171 * Core IO on Xeon E7 v2, see Intel order no 329595-002. 2172 * Core IO on Xeon E5 v3, see Intel order no 330784-003. 2173 * Core IO on Xeon E7 v3, see Intel order no 332315-001US. 2174 * Core IO on Xeon E5 v4, see Intel order no 333810-002US. 2175 * Core IO on Xeon E7 v4, see Intel order no 332315-001US. 2176 * Core IO on Xeon D-1500, see Intel order no 332051-001. 2177 * Core IO on Xeon Scalable, see Intel order no 610950. 2178 */ 2179 #define INTEL_6300_IOAPIC_ABAR 0x40 /* Bus 0, Dev 29, Func 5 */ 2180 #define INTEL_6300_DISABLE_BOOT_IRQ (1<<14) 2181 2182 #define INTEL_CIPINTRC_CFG_OFFSET 0x14C /* Bus 0, Dev 5, Func 0 */ 2183 #define INTEL_CIPINTRC_DIS_INTX_ICH (1<<25) 2184 2185 static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev) 2186 { 2187 u16 pci_config_word; 2188 u32 pci_config_dword; 2189 2190 if (noioapicquirk) 2191 return; 2192 2193 switch (dev->device) { 2194 case PCI_DEVICE_ID_INTEL_ESB_10: 2195 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2196 &pci_config_word); 2197 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ; 2198 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, 2199 pci_config_word); 2200 break; 2201 case 0x3c28: /* Xeon E5 1600/2600/4600 */ 2202 case 0x0e28: /* Xeon E5/E7 V2 */ 2203 case 0x2f28: /* Xeon E5/E7 V3,V4 */ 2204 case 0x6f28: /* Xeon D-1500 */ 2205 case 0x2034: /* Xeon Scalable Family */ 2206 pci_read_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2207 &pci_config_dword); 2208 pci_config_dword |= INTEL_CIPINTRC_DIS_INTX_ICH; 2209 pci_write_config_dword(dev, INTEL_CIPINTRC_CFG_OFFSET, 2210 pci_config_dword); 2211 break; 2212 default: 2213 return; 2214 } 2215 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2216 dev->vendor, dev->device); 2217 } 2218 /* 2219 * Device 29 Func 5 Device IDs of IO-APIC 2220 * containing ABAR—APIC1 Alternate Base Address Register 2221 */ 2222 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2223 quirk_disable_intel_boot_interrupt); 2224 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, 2225 quirk_disable_intel_boot_interrupt); 2226 2227 /* 2228 * Device 5 Func 0 Device IDs of Core IO modules/hubs 2229 * containing Coherent Interface Protocol Interrupt Control 2230 * 2231 * Device IDs obtained from volume 2 datasheets of commented 2232 * families above. 2233 */ 2234 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x3c28, 2235 quirk_disable_intel_boot_interrupt); 2236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0e28, 2237 quirk_disable_intel_boot_interrupt); 2238 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2f28, 2239 quirk_disable_intel_boot_interrupt); 2240 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x6f28, 2241 quirk_disable_intel_boot_interrupt); 2242 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2034, 2243 quirk_disable_intel_boot_interrupt); 2244 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x3c28, 2245 quirk_disable_intel_boot_interrupt); 2246 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x0e28, 2247 quirk_disable_intel_boot_interrupt); 2248 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2f28, 2249 quirk_disable_intel_boot_interrupt); 2250 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x6f28, 2251 quirk_disable_intel_boot_interrupt); 2252 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, 0x2034, 2253 quirk_disable_intel_boot_interrupt); 2254 2255 /* Disable boot interrupts on HT-1000 */ 2256 #define BC_HT1000_FEATURE_REG 0x64 2257 #define BC_HT1000_PIC_REGS_ENABLE (1<<0) 2258 #define BC_HT1000_MAP_IDX 0xC00 2259 #define BC_HT1000_MAP_DATA 0xC01 2260 2261 static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev) 2262 { 2263 u32 pci_config_dword; 2264 u8 irq; 2265 2266 if (noioapicquirk) 2267 return; 2268 2269 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword); 2270 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword | 2271 BC_HT1000_PIC_REGS_ENABLE); 2272 2273 for (irq = 0x10; irq < 0x10 + 32; irq++) { 2274 outb(irq, BC_HT1000_MAP_IDX); 2275 outb(0x00, BC_HT1000_MAP_DATA); 2276 } 2277 2278 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword); 2279 2280 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2281 dev->vendor, dev->device); 2282 } 2283 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2284 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt); 2285 2286 /* Disable boot interrupts on AMD and ATI chipsets */ 2287 2288 /* 2289 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131 2290 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode 2291 * (due to an erratum). 2292 */ 2293 #define AMD_813X_MISC 0x40 2294 #define AMD_813X_NOIOAMODE (1<<0) 2295 #define AMD_813X_REV_B1 0x12 2296 #define AMD_813X_REV_B2 0x13 2297 2298 static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev) 2299 { 2300 u32 pci_config_dword; 2301 2302 if (noioapicquirk) 2303 return; 2304 if ((dev->revision == AMD_813X_REV_B1) || 2305 (dev->revision == AMD_813X_REV_B2)) 2306 return; 2307 2308 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword); 2309 pci_config_dword &= ~AMD_813X_NOIOAMODE; 2310 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword); 2311 2312 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2313 dev->vendor, dev->device); 2314 } 2315 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2316 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2317 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2318 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt); 2319 2320 #define AMD_8111_PCI_IRQ_ROUTING 0x56 2321 2322 static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev) 2323 { 2324 u16 pci_config_word; 2325 2326 if (noioapicquirk) 2327 return; 2328 2329 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word); 2330 if (!pci_config_word) { 2331 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n", 2332 dev->vendor, dev->device); 2333 return; 2334 } 2335 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0); 2336 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n", 2337 dev->vendor, dev->device); 2338 } 2339 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2340 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt); 2341 #endif /* CONFIG_X86_IO_APIC */ 2342 2343 /* 2344 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size 2345 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes. 2346 * Re-allocate the region if needed... 2347 */ 2348 static void quirk_tc86c001_ide(struct pci_dev *dev) 2349 { 2350 struct resource *r = &dev->resource[0]; 2351 2352 if (r->start & 0x8) { 2353 r->flags |= IORESOURCE_UNSET; 2354 resource_set_range(r, 0, SZ_16); 2355 } 2356 } 2357 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2, 2358 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE, 2359 quirk_tc86c001_ide); 2360 2361 /* 2362 * PLX PCI 9050 PCI Target bridge controller has an erratum that prevents the 2363 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o) 2364 * being read correctly if bit 7 of the base address is set. 2365 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128). 2366 * Re-allocate the regions to a 256-byte boundary if necessary. 2367 */ 2368 static void quirk_plx_pci9050(struct pci_dev *dev) 2369 { 2370 unsigned int bar; 2371 2372 /* Fixed in revision 2 (PCI 9052). */ 2373 if (dev->revision >= 2) 2374 return; 2375 for (bar = 0; bar <= 1; bar++) 2376 if (pci_resource_len(dev, bar) == 0x80 && 2377 (pci_resource_start(dev, bar) & 0x80)) { 2378 struct resource *r = &dev->resource[bar]; 2379 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n", 2380 bar); 2381 r->flags |= IORESOURCE_UNSET; 2382 resource_set_range(r, 0, SZ_256); 2383 } 2384 } 2385 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050, 2386 quirk_plx_pci9050); 2387 /* 2388 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others) 2389 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b, 2390 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c, 2391 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b. 2392 * 2393 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq" 2394 * driver. 2395 */ 2396 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050); 2397 DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050); 2398 2399 static void quirk_netmos(struct pci_dev *dev) 2400 { 2401 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4; 2402 unsigned int num_serial = dev->subsystem_device & 0xf; 2403 2404 /* 2405 * These Netmos parts are multiport serial devices with optional 2406 * parallel ports. Even when parallel ports are present, they 2407 * are identified as class SERIAL, which means the serial driver 2408 * will claim them. To prevent this, mark them as class OTHER. 2409 * These combo devices should be claimed by parport_serial. 2410 * 2411 * The subdevice ID is of the form 0x00PS, where <P> is the number 2412 * of parallel ports and <S> is the number of serial ports. 2413 */ 2414 switch (dev->device) { 2415 case PCI_DEVICE_ID_NETMOS_9835: 2416 /* Well, this rule doesn't hold for the following 9835 device */ 2417 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM && 2418 dev->subsystem_device == 0x0299) 2419 return; 2420 fallthrough; 2421 case PCI_DEVICE_ID_NETMOS_9735: 2422 case PCI_DEVICE_ID_NETMOS_9745: 2423 case PCI_DEVICE_ID_NETMOS_9845: 2424 case PCI_DEVICE_ID_NETMOS_9855: 2425 if (num_parallel) { 2426 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n", 2427 dev->device, num_parallel, num_serial); 2428 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) | 2429 (dev->class & 0xff); 2430 } 2431 } 2432 } 2433 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID, 2434 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos); 2435 2436 static void quirk_e100_interrupt(struct pci_dev *dev) 2437 { 2438 u16 command, pmcsr; 2439 u8 __iomem *csr; 2440 u8 cmd_hi; 2441 2442 switch (dev->device) { 2443 /* PCI IDs taken from drivers/net/e100.c */ 2444 case 0x1029: 2445 case 0x1030 ... 0x1034: 2446 case 0x1038 ... 0x103E: 2447 case 0x1050 ... 0x1057: 2448 case 0x1059: 2449 case 0x1064 ... 0x106B: 2450 case 0x1091 ... 0x1095: 2451 case 0x1209: 2452 case 0x1229: 2453 case 0x2449: 2454 case 0x2459: 2455 case 0x245D: 2456 case 0x27DC: 2457 break; 2458 default: 2459 return; 2460 } 2461 2462 /* 2463 * Some firmware hands off the e100 with interrupts enabled, 2464 * which can cause a flood of interrupts if packets are 2465 * received before the driver attaches to the device. So 2466 * disable all e100 interrupts here. The driver will 2467 * re-enable them when it's ready. 2468 */ 2469 pci_read_config_word(dev, PCI_COMMAND, &command); 2470 2471 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0)) 2472 return; 2473 2474 /* 2475 * Check that the device is in the D0 power state. If it's not, 2476 * there is no point to look any further. 2477 */ 2478 if (dev->pm_cap) { 2479 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); 2480 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0) 2481 return; 2482 } 2483 2484 /* Convert from PCI bus to resource space. */ 2485 csr = ioremap(pci_resource_start(dev, 0), 8); 2486 if (!csr) { 2487 pci_warn(dev, "Can't map e100 registers\n"); 2488 return; 2489 } 2490 2491 cmd_hi = readb(csr + 3); 2492 if (cmd_hi == 0) { 2493 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n"); 2494 writeb(1, csr + 3); 2495 } 2496 2497 iounmap(csr); 2498 } 2499 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 2500 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt); 2501 2502 /* 2503 * The 82575 and 82598 may experience data corruption issues when transitioning 2504 * out of L0S. To prevent this we need to disable L0S on the PCIe link. 2505 */ 2506 static void quirk_disable_aspm_l0s(struct pci_dev *dev) 2507 { 2508 pcie_aspm_remove_cap(dev, PCI_EXP_LNKCAP_ASPM_L0S); 2509 } 2510 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s); 2511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s); 2512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s); 2513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s); 2514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s); 2515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s); 2516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s); 2517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s); 2518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s); 2519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s); 2520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s); 2521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s); 2522 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s); 2523 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s); 2524 2525 static void quirk_disable_aspm_l0s_l1(struct pci_dev *dev) 2526 { 2527 pcie_aspm_remove_cap(dev, 2528 PCI_EXP_LNKCAP_ASPM_L0S | PCI_EXP_LNKCAP_ASPM_L1); 2529 } 2530 2531 /* 2532 * ASM1083/1085 PCIe-PCI bridge devices cause AER timeout errors on the 2533 * upstream PCIe root port when ASPM is enabled. At least L0s mode is affected; 2534 * disable both L0s and L1 for now to be safe. 2535 */ 2536 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, quirk_disable_aspm_l0s_l1); 2537 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_FREESCALE, 0x0451, quirk_disable_aspm_l0s_l1); 2538 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PASEMI, 0xa002, quirk_disable_aspm_l0s_l1); 2539 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HUAWEI, 0x1105, quirk_disable_aspm_l0s_l1); 2540 2541 /* 2542 * Some Pericom PCIe-to-PCI bridges in reverse mode need the PCIe Retrain 2543 * Link bit cleared after starting the link retrain process to allow this 2544 * process to finish. 2545 * 2546 * Affected devices: PI7C9X110, PI7C9X111SL, PI7C9X130. See also the 2547 * Pericom Errata Sheet PI7C9X111SLB_errata_rev1.2_102711.pdf. 2548 */ 2549 static void quirk_enable_clear_retrain_link(struct pci_dev *dev) 2550 { 2551 dev->clear_retrain_link = 1; 2552 pci_info(dev, "Enable PCIe Retrain Link quirk\n"); 2553 } 2554 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe110, quirk_enable_clear_retrain_link); 2555 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe111, quirk_enable_clear_retrain_link); 2556 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PERICOM, 0xe130, quirk_enable_clear_retrain_link); 2557 2558 static void fixup_rev1_53c810(struct pci_dev *dev) 2559 { 2560 u32 class = dev->class; 2561 2562 /* 2563 * rev 1 ncr53c810 chips don't set the class at all which means 2564 * they don't get their resources remapped. Fix that here. 2565 */ 2566 if (class) 2567 return; 2568 2569 dev->class = PCI_CLASS_STORAGE_SCSI << 8; 2570 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n", 2571 class, dev->class); 2572 } 2573 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810); 2574 2575 /* Enable 1k I/O space granularity on the Intel P64H2 */ 2576 static void quirk_p64h2_1k_io(struct pci_dev *dev) 2577 { 2578 u16 en1k; 2579 2580 pci_read_config_word(dev, 0x40, &en1k); 2581 2582 if (en1k & 0x200) { 2583 pci_info(dev, "Enable I/O Space to 1KB granularity\n"); 2584 dev->io_window_1k = 1; 2585 } 2586 } 2587 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io); 2588 2589 /* 2590 * Under some circumstances, AER is not linked with extended capabilities. 2591 * Force it to be linked by setting the corresponding control bit in the 2592 * config space. 2593 */ 2594 static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev) 2595 { 2596 uint8_t b; 2597 2598 if (pci_read_config_byte(dev, 0xf41, &b) == 0) { 2599 if (!(b & 0x20)) { 2600 pci_write_config_byte(dev, 0xf41, b | 0x20); 2601 pci_info(dev, "Linking AER extended capability\n"); 2602 } 2603 } 2604 } 2605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2606 quirk_nvidia_ck804_pcie_aer_ext_cap); 2607 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2608 quirk_nvidia_ck804_pcie_aer_ext_cap); 2609 2610 static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev) 2611 { 2612 /* 2613 * Disable PCI Bus Parking and PCI Master read caching on CX700 2614 * which causes unspecified timing errors with a VT6212L on the PCI 2615 * bus leading to USB2.0 packet loss. 2616 * 2617 * This quirk is only enabled if a second (on the external PCI bus) 2618 * VT6212L is found -- the CX700 core itself also contains a USB 2619 * host controller with the same PCI ID as the VT6212L. 2620 */ 2621 2622 /* Count VT6212L instances */ 2623 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA, 2624 PCI_DEVICE_ID_VIA_8235_USB_2, NULL); 2625 uint8_t b; 2626 2627 /* 2628 * p should contain the first (internal) VT6212L -- see if we have 2629 * an external one by searching again. 2630 */ 2631 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p); 2632 if (!p) 2633 return; 2634 pci_dev_put(p); 2635 2636 if (pci_read_config_byte(dev, 0x76, &b) == 0) { 2637 if (b & 0x40) { 2638 /* Turn off PCI Bus Parking */ 2639 pci_write_config_byte(dev, 0x76, b ^ 0x40); 2640 2641 pci_info(dev, "Disabling VIA CX700 PCI parking\n"); 2642 } 2643 } 2644 2645 if (pci_read_config_byte(dev, 0x72, &b) == 0) { 2646 if (b != 0) { 2647 /* Turn off PCI Master read caching */ 2648 pci_write_config_byte(dev, 0x72, 0x0); 2649 2650 /* Set PCI Master Bus time-out to "1x16 PCLK" */ 2651 pci_write_config_byte(dev, 0x75, 0x1); 2652 2653 /* Disable "Read FIFO Timer" */ 2654 pci_write_config_byte(dev, 0x77, 0x0); 2655 2656 pci_info(dev, "Disabling VIA CX700 PCI caching\n"); 2657 } 2658 } 2659 } 2660 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching); 2661 2662 static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev) 2663 { 2664 u32 rev; 2665 2666 pci_read_config_dword(dev, 0xf4, &rev); 2667 2668 /* Only CAP the MRRS if the device is a 5719 A0 */ 2669 if (rev == 0x05719000) { 2670 int readrq = pcie_get_readrq(dev); 2671 if (readrq > 2048) 2672 pcie_set_readrq(dev, 2048); 2673 } 2674 } 2675 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM, 2676 PCI_DEVICE_ID_TIGON3_5719, 2677 quirk_brcm_5719_limit_mrrs); 2678 2679 /* 2680 * Originally in EDAC sources for i82875P: Intel tells BIOS developers to 2681 * hide device 6 which configures the overflow device access containing the 2682 * DRBs - this is where we expose device 6. 2683 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm 2684 */ 2685 static void quirk_unhide_mch_dev6(struct pci_dev *dev) 2686 { 2687 u8 reg; 2688 2689 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) { 2690 pci_info(dev, "Enabling MCH 'Overflow' Device\n"); 2691 pci_write_config_byte(dev, 0xF4, reg | 0x02); 2692 } 2693 } 2694 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, 2695 quirk_unhide_mch_dev6); 2696 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, 2697 quirk_unhide_mch_dev6); 2698 2699 #ifdef CONFIG_PCI_MSI 2700 /* 2701 * Some chipsets do not support MSI. We cannot easily rely on setting 2702 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually some 2703 * other buses controlled by the chipset even if Linux is not aware of it. 2704 * Instead of setting the flag on all buses in the machine, simply disable 2705 * MSI globally. 2706 */ 2707 static void quirk_disable_all_msi(struct pci_dev *dev) 2708 { 2709 pci_no_msi(); 2710 pci_warn(dev, "MSI quirk detected; MSI disabled\n"); 2711 } 2712 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi); 2713 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi); 2714 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi); 2715 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi); 2716 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi); 2717 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi); 2718 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi); 2719 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi); 2720 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SAMSUNG, 0xa5e3, quirk_disable_all_msi); 2721 2722 /* Disable MSI on chipsets that are known to not support it */ 2723 static void quirk_disable_msi(struct pci_dev *dev) 2724 { 2725 if (dev->subordinate) { 2726 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n"); 2727 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI; 2728 } 2729 } 2730 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi); 2731 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi); 2732 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi); 2733 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_RDC, 0x1031, quirk_disable_msi); 2734 2735 /* 2736 * The APC bridge device in AMD 780 family northbridges has some random 2737 * OEM subsystem ID in its vendor ID register (erratum 18), so instead 2738 * we use the possible vendor/device IDs of the host bridge for the 2739 * declared quirk, and search for the APC bridge by slot number. 2740 */ 2741 static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge) 2742 { 2743 struct pci_dev *apc_bridge; 2744 2745 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0)); 2746 if (apc_bridge) { 2747 if (apc_bridge->device == 0x9602) 2748 quirk_disable_msi(apc_bridge); 2749 pci_dev_put(apc_bridge); 2750 } 2751 } 2752 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi); 2753 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi); 2754 2755 /* 2756 * Go through the list of HyperTransport capabilities and return 1 if a HT 2757 * MSI capability is found and enabled. 2758 */ 2759 static int msi_ht_cap_enabled(struct pci_dev *dev) 2760 { 2761 int pos, ttl = PCI_FIND_CAP_TTL; 2762 2763 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2764 while (pos && ttl--) { 2765 u8 flags; 2766 2767 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2768 &flags) == 0) { 2769 pci_info(dev, "Found %s HT MSI Mapping\n", 2770 flags & HT_MSI_FLAGS_ENABLE ? 2771 "enabled" : "disabled"); 2772 return (flags & HT_MSI_FLAGS_ENABLE) != 0; 2773 } 2774 2775 pos = pci_find_next_ht_capability(dev, pos, 2776 HT_CAPTYPE_MSI_MAPPING); 2777 } 2778 return 0; 2779 } 2780 2781 /* Check the HyperTransport MSI mapping to know whether MSI is enabled or not */ 2782 static void quirk_msi_ht_cap(struct pci_dev *dev) 2783 { 2784 if (!msi_ht_cap_enabled(dev)) 2785 quirk_disable_msi(dev); 2786 } 2787 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE, 2788 quirk_msi_ht_cap); 2789 2790 /* 2791 * The nVidia CK804 chipset may have 2 HT MSI mappings. MSI is supported 2792 * if the MSI capability is set in any of these mappings. 2793 */ 2794 static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev) 2795 { 2796 struct pci_dev *pdev; 2797 2798 /* 2799 * Check HT MSI cap on this chipset and the root one. A single one 2800 * having MSI is enough to be sure that MSI is supported. 2801 */ 2802 pdev = pci_get_slot(dev->bus, 0); 2803 if (!pdev) 2804 return; 2805 if (!msi_ht_cap_enabled(pdev)) 2806 quirk_msi_ht_cap(dev); 2807 pci_dev_put(pdev); 2808 } 2809 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE, 2810 quirk_nvidia_ck804_msi_ht_cap); 2811 2812 /* Force enable MSI mapping capability on HT bridges */ 2813 static void ht_enable_msi_mapping(struct pci_dev *dev) 2814 { 2815 int pos, ttl = PCI_FIND_CAP_TTL; 2816 2817 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2818 while (pos && ttl--) { 2819 u8 flags; 2820 2821 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2822 &flags) == 0) { 2823 pci_info(dev, "Enabling HT MSI Mapping\n"); 2824 2825 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 2826 flags | HT_MSI_FLAGS_ENABLE); 2827 } 2828 pos = pci_find_next_ht_capability(dev, pos, 2829 HT_CAPTYPE_MSI_MAPPING); 2830 } 2831 } 2832 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS, 2833 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB, 2834 ht_enable_msi_mapping); 2835 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, 2836 ht_enable_msi_mapping); 2837 2838 /* 2839 * The P5N32-SLI motherboards from Asus have a problem with MSI 2840 * for the MCP55 NIC. It is not yet determined whether the MSI problem 2841 * also affects other devices. As for now, turn off MSI for this device. 2842 */ 2843 static void nvenet_msi_disable(struct pci_dev *dev) 2844 { 2845 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME); 2846 2847 if (board_name && 2848 (strstr(board_name, "P5N32-SLI PREMIUM") || 2849 strstr(board_name, "P5N32-E SLI"))) { 2850 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n"); 2851 dev->no_msi = 1; 2852 } 2853 } 2854 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2855 PCI_DEVICE_ID_NVIDIA_NVENET_15, 2856 nvenet_msi_disable); 2857 2858 /* 2859 * PCIe spec r6.0 sec 6.1.4.3 says that if MSI/MSI-X is enabled, the device 2860 * can't use INTx interrupts. Tegra's PCIe Root Ports don't generate MSI 2861 * interrupts for PME and AER events; instead only INTx interrupts are 2862 * generated. Though Tegra's PCIe Root Ports can generate MSI interrupts 2863 * for other events, since PCIe specification doesn't support using a mix of 2864 * INTx and MSI/MSI-X, it is required to disable MSI interrupts to avoid port 2865 * service drivers registering their respective ISRs for MSIs. 2866 */ 2867 static void pci_quirk_nvidia_tegra_disable_rp_msi(struct pci_dev *dev) 2868 { 2869 dev->no_msi = 1; 2870 } 2871 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad0, 2872 PCI_CLASS_BRIDGE_PCI, 8, 2873 pci_quirk_nvidia_tegra_disable_rp_msi); 2874 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad1, 2875 PCI_CLASS_BRIDGE_PCI, 8, 2876 pci_quirk_nvidia_tegra_disable_rp_msi); 2877 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x1ad2, 2878 PCI_CLASS_BRIDGE_PCI, 8, 2879 pci_quirk_nvidia_tegra_disable_rp_msi); 2880 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf0, 2881 PCI_CLASS_BRIDGE_PCI, 8, 2882 pci_quirk_nvidia_tegra_disable_rp_msi); 2883 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0bf1, 2884 PCI_CLASS_BRIDGE_PCI, 8, 2885 pci_quirk_nvidia_tegra_disable_rp_msi); 2886 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1c, 2887 PCI_CLASS_BRIDGE_PCI, 8, 2888 pci_quirk_nvidia_tegra_disable_rp_msi); 2889 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e1d, 2890 PCI_CLASS_BRIDGE_PCI, 8, 2891 pci_quirk_nvidia_tegra_disable_rp_msi); 2892 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e12, 2893 PCI_CLASS_BRIDGE_PCI, 8, 2894 pci_quirk_nvidia_tegra_disable_rp_msi); 2895 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0e13, 2896 PCI_CLASS_BRIDGE_PCI, 8, 2897 pci_quirk_nvidia_tegra_disable_rp_msi); 2898 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0fae, 2899 PCI_CLASS_BRIDGE_PCI, 8, 2900 pci_quirk_nvidia_tegra_disable_rp_msi); 2901 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x0faf, 2902 PCI_CLASS_BRIDGE_PCI, 8, 2903 pci_quirk_nvidia_tegra_disable_rp_msi); 2904 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e5, 2905 PCI_CLASS_BRIDGE_PCI, 8, 2906 pci_quirk_nvidia_tegra_disable_rp_msi); 2907 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x10e6, 2908 PCI_CLASS_BRIDGE_PCI, 8, 2909 pci_quirk_nvidia_tegra_disable_rp_msi); 2910 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229a, 2911 PCI_CLASS_BRIDGE_PCI, 8, 2912 pci_quirk_nvidia_tegra_disable_rp_msi); 2913 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229c, 2914 PCI_CLASS_BRIDGE_PCI, 8, 2915 pci_quirk_nvidia_tegra_disable_rp_msi); 2916 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_NVIDIA, 0x229e, 2917 PCI_CLASS_BRIDGE_PCI, 8, 2918 pci_quirk_nvidia_tegra_disable_rp_msi); 2919 2920 /* 2921 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing 2922 * config register. This register controls the routing of legacy 2923 * interrupts from devices that route through the MCP55. If this register 2924 * is misprogrammed, interrupts are only sent to the BSP, unlike 2925 * conventional systems where the IRQ is broadcast to all online CPUs. Not 2926 * having this register set properly prevents kdump from booting up 2927 * properly, so let's make sure that we have it set correctly. 2928 * Note that this is an undocumented register. 2929 */ 2930 static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev) 2931 { 2932 u32 cfg; 2933 2934 if (!pci_find_capability(dev, PCI_CAP_ID_HT)) 2935 return; 2936 2937 pci_read_config_dword(dev, 0x74, &cfg); 2938 2939 if (cfg & ((1 << 2) | (1 << 15))) { 2940 pr_info("Rewriting IRQ routing register on MCP55\n"); 2941 cfg &= ~((1 << 2) | (1 << 15)); 2942 pci_write_config_dword(dev, 0x74, cfg); 2943 } 2944 } 2945 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2946 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0, 2947 nvbridge_check_legacy_irq_routing); 2948 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA, 2949 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4, 2950 nvbridge_check_legacy_irq_routing); 2951 2952 static int ht_check_msi_mapping(struct pci_dev *dev) 2953 { 2954 int pos, ttl = PCI_FIND_CAP_TTL; 2955 int found = 0; 2956 2957 /* Check if there is HT MSI cap or enabled on this device */ 2958 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 2959 while (pos && ttl--) { 2960 u8 flags; 2961 2962 if (found < 1) 2963 found = 1; 2964 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 2965 &flags) == 0) { 2966 if (flags & HT_MSI_FLAGS_ENABLE) { 2967 if (found < 2) { 2968 found = 2; 2969 break; 2970 } 2971 } 2972 } 2973 pos = pci_find_next_ht_capability(dev, pos, 2974 HT_CAPTYPE_MSI_MAPPING); 2975 } 2976 2977 return found; 2978 } 2979 2980 static int host_bridge_with_leaf(struct pci_dev *host_bridge) 2981 { 2982 struct pci_dev *dev; 2983 int pos; 2984 int i, dev_no; 2985 int found = 0; 2986 2987 dev_no = host_bridge->devfn >> 3; 2988 for (i = dev_no + 1; i < 0x20; i++) { 2989 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0)); 2990 if (!dev) 2991 continue; 2992 2993 /* found next host bridge? */ 2994 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 2995 if (pos != 0) { 2996 pci_dev_put(dev); 2997 break; 2998 } 2999 3000 if (ht_check_msi_mapping(dev)) { 3001 found = 1; 3002 pci_dev_put(dev); 3003 break; 3004 } 3005 pci_dev_put(dev); 3006 } 3007 3008 return found; 3009 } 3010 3011 #define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */ 3012 #define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */ 3013 3014 static int is_end_of_ht_chain(struct pci_dev *dev) 3015 { 3016 int pos, ctrl_off; 3017 int end = 0; 3018 u16 flags, ctrl; 3019 3020 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE); 3021 3022 if (!pos) 3023 goto out; 3024 3025 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags); 3026 3027 ctrl_off = ((flags >> 10) & 1) ? 3028 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1; 3029 pci_read_config_word(dev, pos + ctrl_off, &ctrl); 3030 3031 if (ctrl & (1 << 6)) 3032 end = 1; 3033 3034 out: 3035 return end; 3036 } 3037 3038 static void nv_ht_enable_msi_mapping(struct pci_dev *dev) 3039 { 3040 struct pci_dev *host_bridge; 3041 int pos; 3042 int i, dev_no; 3043 int found = 0; 3044 3045 dev_no = dev->devfn >> 3; 3046 for (i = dev_no; i >= 0; i--) { 3047 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0)); 3048 if (!host_bridge) 3049 continue; 3050 3051 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3052 if (pos != 0) { 3053 found = 1; 3054 break; 3055 } 3056 pci_dev_put(host_bridge); 3057 } 3058 3059 if (!found) 3060 return; 3061 3062 /* don't enable end_device/host_bridge with leaf directly here */ 3063 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) && 3064 host_bridge_with_leaf(host_bridge)) 3065 goto out; 3066 3067 /* root did that ! */ 3068 if (msi_ht_cap_enabled(host_bridge)) 3069 goto out; 3070 3071 ht_enable_msi_mapping(dev); 3072 3073 out: 3074 pci_dev_put(host_bridge); 3075 } 3076 3077 static void ht_disable_msi_mapping(struct pci_dev *dev) 3078 { 3079 int pos, ttl = PCI_FIND_CAP_TTL; 3080 3081 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING); 3082 while (pos && ttl--) { 3083 u8 flags; 3084 3085 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS, 3086 &flags) == 0) { 3087 pci_info(dev, "Disabling HT MSI Mapping\n"); 3088 3089 pci_write_config_byte(dev, pos + HT_MSI_FLAGS, 3090 flags & ~HT_MSI_FLAGS_ENABLE); 3091 } 3092 pos = pci_find_next_ht_capability(dev, pos, 3093 HT_CAPTYPE_MSI_MAPPING); 3094 } 3095 } 3096 3097 static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all) 3098 { 3099 struct pci_dev *host_bridge; 3100 int pos; 3101 int found; 3102 3103 if (!pci_msi_enabled()) 3104 return; 3105 3106 /* check if there is HT MSI cap or enabled on this device */ 3107 found = ht_check_msi_mapping(dev); 3108 3109 /* no HT MSI CAP */ 3110 if (found == 0) 3111 return; 3112 3113 /* 3114 * HT MSI mapping should be disabled on devices that are below 3115 * a non-HyperTransport host bridge. Locate the host bridge. 3116 */ 3117 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0, 3118 PCI_DEVFN(0, 0)); 3119 if (host_bridge == NULL) { 3120 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n"); 3121 return; 3122 } 3123 3124 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE); 3125 if (pos != 0) { 3126 /* Host bridge is to HT */ 3127 if (found == 1) { 3128 /* it is not enabled, try to enable it */ 3129 if (all) 3130 ht_enable_msi_mapping(dev); 3131 else 3132 nv_ht_enable_msi_mapping(dev); 3133 } 3134 goto out; 3135 } 3136 3137 /* HT MSI is not enabled */ 3138 if (found == 1) 3139 goto out; 3140 3141 /* Host bridge is not to HT, disable HT MSI mapping on this device */ 3142 ht_disable_msi_mapping(dev); 3143 3144 out: 3145 pci_dev_put(host_bridge); 3146 } 3147 3148 static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev) 3149 { 3150 return __nv_msi_ht_cap_quirk(dev, 1); 3151 } 3152 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3153 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all); 3154 3155 static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev) 3156 { 3157 return __nv_msi_ht_cap_quirk(dev, 0); 3158 } 3159 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3160 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf); 3161 3162 static void quirk_msi_intx_disable_bug(struct pci_dev *dev) 3163 { 3164 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3165 } 3166 3167 static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev) 3168 { 3169 struct pci_dev *p; 3170 3171 /* 3172 * SB700 MSI issue will be fixed at HW level from revision A21; 3173 * we need check PCI REVISION ID of SMBus controller to get SB700 3174 * revision. 3175 */ 3176 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS, 3177 NULL); 3178 if (!p) 3179 return; 3180 3181 if ((p->revision < 0x3B) && (p->revision >= 0x30)) 3182 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3183 pci_dev_put(p); 3184 } 3185 3186 static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev) 3187 { 3188 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */ 3189 if (dev->revision < 0x18) { 3190 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n"); 3191 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG; 3192 } 3193 } 3194 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3195 PCI_DEVICE_ID_TIGON3_5780, 3196 quirk_msi_intx_disable_bug); 3197 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3198 PCI_DEVICE_ID_TIGON3_5780S, 3199 quirk_msi_intx_disable_bug); 3200 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3201 PCI_DEVICE_ID_TIGON3_5714, 3202 quirk_msi_intx_disable_bug); 3203 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3204 PCI_DEVICE_ID_TIGON3_5714S, 3205 quirk_msi_intx_disable_bug); 3206 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3207 PCI_DEVICE_ID_TIGON3_5715, 3208 quirk_msi_intx_disable_bug); 3209 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM, 3210 PCI_DEVICE_ID_TIGON3_5715S, 3211 quirk_msi_intx_disable_bug); 3212 3213 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390, 3214 quirk_msi_intx_disable_ati_bug); 3215 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391, 3216 quirk_msi_intx_disable_ati_bug); 3217 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392, 3218 quirk_msi_intx_disable_ati_bug); 3219 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393, 3220 quirk_msi_intx_disable_ati_bug); 3221 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394, 3222 quirk_msi_intx_disable_ati_bug); 3223 3224 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373, 3225 quirk_msi_intx_disable_bug); 3226 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374, 3227 quirk_msi_intx_disable_bug); 3228 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375, 3229 quirk_msi_intx_disable_bug); 3230 3231 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062, 3232 quirk_msi_intx_disable_bug); 3233 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063, 3234 quirk_msi_intx_disable_bug); 3235 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060, 3236 quirk_msi_intx_disable_bug); 3237 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062, 3238 quirk_msi_intx_disable_bug); 3239 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073, 3240 quirk_msi_intx_disable_bug); 3241 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083, 3242 quirk_msi_intx_disable_bug); 3243 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090, 3244 quirk_msi_intx_disable_qca_bug); 3245 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091, 3246 quirk_msi_intx_disable_qca_bug); 3247 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0, 3248 quirk_msi_intx_disable_qca_bug); 3249 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1, 3250 quirk_msi_intx_disable_qca_bug); 3251 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091, 3252 quirk_msi_intx_disable_qca_bug); 3253 3254 /* 3255 * Amazon's Annapurna Labs 1c36:0031 Root Ports don't support MSI-X, so it 3256 * should be disabled on platforms where the device (mistakenly) advertises it. 3257 * 3258 * Notice that this quirk also disables MSI (which may work, but hasn't been 3259 * tested), since currently there is no standard way to disable only MSI-X. 3260 * 3261 * The 0031 device id is reused for other non Root Port device types, 3262 * therefore the quirk is registered for the PCI_CLASS_BRIDGE_PCI class. 3263 */ 3264 static void quirk_al_msi_disable(struct pci_dev *dev) 3265 { 3266 dev->no_msi = 1; 3267 pci_warn(dev, "Disabling MSI/MSI-X\n"); 3268 } 3269 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, 3270 PCI_CLASS_BRIDGE_PCI, 8, quirk_al_msi_disable); 3271 #endif /* CONFIG_PCI_MSI */ 3272 3273 /* 3274 * Allow manual resource allocation for PCI hotplug bridges via 3275 * pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For some PCI-PCI 3276 * hotplug bridges, like PLX 6254 (former HINT HB6), kernel fails to 3277 * allocate resources when hotplug device is inserted and PCI bus is 3278 * rescanned. 3279 */ 3280 static void quirk_hotplug_bridge(struct pci_dev *dev) 3281 { 3282 dev->is_hotplug_bridge = 1; 3283 } 3284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge); 3285 3286 /* 3287 * This is a quirk for the Ricoh MMC controller found as a part of some 3288 * multifunction chips. 3289 * 3290 * This is very similar and based on the ricoh_mmc driver written by 3291 * Philip Langdale. Thank you for these magic sequences. 3292 * 3293 * These chips implement the four main memory card controllers (SD, MMC, 3294 * MS, xD) and one or both of CardBus or FireWire. 3295 * 3296 * It happens that they implement SD and MMC support as separate 3297 * controllers (and PCI functions). The Linux SDHCI driver supports MMC 3298 * cards but the chip detects MMC cards in hardware and directs them to the 3299 * MMC controller - so the SDHCI driver never sees them. 3300 * 3301 * To get around this, we must disable the useless MMC controller. At that 3302 * point, the SDHCI controller will start seeing them. It seems to be the 3303 * case that the relevant PCI registers to deactivate the MMC controller 3304 * live on PCI function 0, which might be the CardBus controller or the 3305 * FireWire controller, depending on the particular chip in question 3306 * 3307 * This has to be done early, because as soon as we disable the MMC controller 3308 * other PCI functions shift up one level, e.g. function #2 becomes function 3309 * #1, and this will confuse the PCI core. 3310 */ 3311 #ifdef CONFIG_MMC_RICOH_MMC 3312 static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev) 3313 { 3314 u8 write_enable; 3315 u8 write_target; 3316 u8 disable; 3317 3318 /* 3319 * Disable via CardBus interface 3320 * 3321 * This must be done via function #0 3322 */ 3323 if (PCI_FUNC(dev->devfn)) 3324 return; 3325 3326 pci_read_config_byte(dev, 0xB7, &disable); 3327 if (disable & 0x02) 3328 return; 3329 3330 pci_read_config_byte(dev, 0x8E, &write_enable); 3331 pci_write_config_byte(dev, 0x8E, 0xAA); 3332 pci_read_config_byte(dev, 0x8D, &write_target); 3333 pci_write_config_byte(dev, 0x8D, 0xB7); 3334 pci_write_config_byte(dev, 0xB7, disable | 0x02); 3335 pci_write_config_byte(dev, 0x8E, write_enable); 3336 pci_write_config_byte(dev, 0x8D, write_target); 3337 3338 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via CardBus function)\n"); 3339 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3340 } 3341 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3342 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476); 3343 3344 static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev) 3345 { 3346 u8 write_enable; 3347 u8 disable; 3348 3349 /* 3350 * Disable via FireWire interface 3351 * 3352 * This must be done via function #0 3353 */ 3354 if (PCI_FUNC(dev->devfn)) 3355 return; 3356 /* 3357 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize 3358 * certain types of SD/MMC cards. Lowering the SD base clock 3359 * frequency from 200Mhz to 50Mhz fixes this issue. 3360 * 3361 * 0x150 - SD2.0 mode enable for changing base clock 3362 * frequency to 50Mhz 3363 * 0xe1 - Base clock frequency 3364 * 0x32 - 50Mhz new clock frequency 3365 * 0xf9 - Key register for 0x150 3366 * 0xfc - key register for 0xe1 3367 */ 3368 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 || 3369 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) { 3370 pci_write_config_byte(dev, 0xf9, 0xfc); 3371 pci_write_config_byte(dev, 0x150, 0x10); 3372 pci_write_config_byte(dev, 0xf9, 0x00); 3373 pci_write_config_byte(dev, 0xfc, 0x01); 3374 pci_write_config_byte(dev, 0xe1, 0x32); 3375 pci_write_config_byte(dev, 0xfc, 0x00); 3376 3377 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n"); 3378 } 3379 3380 pci_read_config_byte(dev, 0xCB, &disable); 3381 3382 if (disable & 0x02) 3383 return; 3384 3385 pci_read_config_byte(dev, 0xCA, &write_enable); 3386 pci_write_config_byte(dev, 0xCA, 0x57); 3387 pci_write_config_byte(dev, 0xCB, disable | 0x02); 3388 pci_write_config_byte(dev, 0xCA, write_enable); 3389 3390 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via FireWire function)\n"); 3391 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n"); 3392 3393 } 3394 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3395 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832); 3396 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3397 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832); 3398 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3399 DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832); 3400 #endif /*CONFIG_MMC_RICOH_MMC*/ 3401 3402 #ifdef CONFIG_DMAR_TABLE 3403 #define VTUNCERRMSK_REG 0x1ac 3404 #define VTD_MSK_SPEC_ERRORS (1 << 31) 3405 /* 3406 * This is a quirk for masking VT-d spec-defined errors to platform error 3407 * handling logic. Without this, platforms using Intel 7500, 5500 chipsets 3408 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based 3409 * on the RAS config settings of the platform) when a VT-d fault happens. 3410 * The resulting SMI caused the system to hang. 3411 * 3412 * VT-d spec-related errors are already handled by the VT-d OS code, so no 3413 * need to report the same error through other channels. 3414 */ 3415 static void vtd_mask_spec_errors(struct pci_dev *dev) 3416 { 3417 u32 word; 3418 3419 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word); 3420 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS); 3421 } 3422 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors); 3423 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors); 3424 #endif 3425 3426 static void fixup_ti816x_class(struct pci_dev *dev) 3427 { 3428 u32 class = dev->class; 3429 3430 /* TI 816x devices do not have class code set when in PCIe boot mode */ 3431 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8; 3432 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n", 3433 class, dev->class); 3434 } 3435 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800, 3436 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class); 3437 3438 /* 3439 * Some PCIe devices do not work reliably with the claimed maximum 3440 * payload size supported. 3441 */ 3442 static void fixup_mpss_256(struct pci_dev *dev) 3443 { 3444 dev->pcie_mpss = 1; /* 256 bytes */ 3445 } 3446 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3447 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256); 3448 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3449 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256); 3450 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLARFLARE, 3451 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256); 3452 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_ASMEDIA, 0x0612, fixup_mpss_256); 3453 3454 /* 3455 * Intel 5000 and 5100 Memory controllers have an erratum with read completion 3456 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B. 3457 * Since there is no way of knowing what the PCIe MPS on each fabric will be 3458 * until all of the devices are discovered and buses walked, read completion 3459 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because 3460 * it is possible to hotplug a device with MPS of 256B. 3461 */ 3462 static void quirk_intel_mc_errata(struct pci_dev *dev) 3463 { 3464 int err; 3465 u16 rcc; 3466 3467 if (pcie_bus_config == PCIE_BUS_TUNE_OFF || 3468 pcie_bus_config == PCIE_BUS_DEFAULT) 3469 return; 3470 3471 /* 3472 * Intel erratum specifies bits to change but does not say what 3473 * they are. Keeping them magical until such time as the registers 3474 * and values can be explained. 3475 */ 3476 err = pci_read_config_word(dev, 0x48, &rcc); 3477 if (err) { 3478 pci_err(dev, "Error attempting to read the read completion coalescing register\n"); 3479 return; 3480 } 3481 3482 if (!(rcc & (1 << 10))) 3483 return; 3484 3485 rcc &= ~(1 << 10); 3486 3487 err = pci_write_config_word(dev, 0x48, rcc); 3488 if (err) { 3489 pci_err(dev, "Error attempting to write the read completion coalescing register\n"); 3490 return; 3491 } 3492 3493 pr_info_once("Read completion coalescing disabled due to hardware erratum relating to 256B MPS\n"); 3494 } 3495 /* Intel 5000 series memory controllers and ports 2-7 */ 3496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata); 3497 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata); 3498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata); 3499 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata); 3500 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata); 3501 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata); 3502 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata); 3503 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata); 3504 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata); 3505 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata); 3506 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata); 3507 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata); 3508 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata); 3509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata); 3510 /* Intel 5100 series memory controllers and ports 2-7 */ 3511 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata); 3512 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata); 3513 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata); 3514 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata); 3515 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata); 3516 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata); 3517 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata); 3518 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata); 3519 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata); 3520 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata); 3521 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata); 3522 3523 /* 3524 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. 3525 * To work around this, query the size it should be configured to by the 3526 * device and modify the resource end to correspond to this new size. 3527 */ 3528 static void quirk_intel_ntb(struct pci_dev *dev) 3529 { 3530 int rc; 3531 u8 val; 3532 3533 rc = pci_read_config_byte(dev, 0x00D0, &val); 3534 if (rc) 3535 return; 3536 3537 resource_set_size(&dev->resource[2], (resource_size_t)1 << val); 3538 3539 rc = pci_read_config_byte(dev, 0x00D1, &val); 3540 if (rc) 3541 return; 3542 3543 resource_set_size(&dev->resource[4], (resource_size_t)1 << val); 3544 } 3545 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb); 3546 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb); 3547 3548 /* 3549 * Some BIOS implementations leave the Intel GPU interrupts enabled, even 3550 * though no one is handling them (e.g., if the i915 driver is never 3551 * loaded). Additionally the interrupt destination is not set up properly 3552 * and the interrupt ends up -somewhere-. 3553 * 3554 * These spurious interrupts are "sticky" and the kernel disables the 3555 * (shared) interrupt line after 100,000+ generated interrupts. 3556 * 3557 * Fix it by disabling the still enabled interrupts. This resolves crashes 3558 * often seen on monitor unplug. 3559 */ 3560 #define I915_DEIER_REG 0x4400c 3561 static void disable_igfx_irq(struct pci_dev *dev) 3562 { 3563 void __iomem *regs = pci_iomap(dev, 0, 0); 3564 if (regs == NULL) { 3565 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n"); 3566 return; 3567 } 3568 3569 /* Check if any interrupt line is still enabled */ 3570 if (readl(regs + I915_DEIER_REG) != 0) { 3571 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n"); 3572 3573 writel(0, regs + I915_DEIER_REG); 3574 } 3575 3576 pci_iounmap(dev, regs); 3577 } 3578 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq); 3579 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq); 3580 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq); 3581 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq); 3582 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq); 3583 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq); 3584 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq); 3585 3586 /* 3587 * PCI devices which are on Intel chips can skip the 10ms delay 3588 * before entering D3 mode. 3589 */ 3590 static void quirk_remove_d3hot_delay(struct pci_dev *dev) 3591 { 3592 dev->d3hot_delay = 0; 3593 } 3594 /* C600 Series devices do not need 10ms d3hot_delay */ 3595 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3hot_delay); 3596 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3hot_delay); 3597 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3hot_delay); 3598 /* Lynxpoint-H PCH devices do not need 10ms d3hot_delay */ 3599 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3hot_delay); 3600 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3hot_delay); 3601 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3hot_delay); 3602 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3hot_delay); 3603 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3hot_delay); 3604 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3hot_delay); 3605 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3hot_delay); 3606 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3hot_delay); 3607 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3hot_delay); 3608 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3hot_delay); 3609 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3hot_delay); 3610 /* Intel Cherrytrail devices do not need 10ms d3hot_delay */ 3611 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3hot_delay); 3612 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3hot_delay); 3613 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3hot_delay); 3614 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3hot_delay); 3615 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3hot_delay); 3616 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3hot_delay); 3617 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3hot_delay); 3618 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3hot_delay); 3619 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3hot_delay); 3620 3621 /* 3622 * Some devices may pass our check in pci_intx_mask_supported() if 3623 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly 3624 * support this feature. 3625 */ 3626 static void quirk_broken_intx_masking(struct pci_dev *dev) 3627 { 3628 dev->broken_intx_masking = 1; 3629 } 3630 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030, 3631 quirk_broken_intx_masking); 3632 DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */ 3633 quirk_broken_intx_masking); 3634 DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004, /* Ceton InfiniTV4 */ 3635 quirk_broken_intx_masking); 3636 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CREATIVE, PCI_DEVICE_ID_CREATIVE_20K2, 3637 quirk_broken_intx_masking); 3638 3639 /* 3640 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10) 3641 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC 3642 * 3643 * RTL8110SC - Fails under PCI device assignment using DisINTx masking. 3644 */ 3645 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169, 3646 quirk_broken_intx_masking); 3647 3648 /* 3649 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking, 3650 * DisINTx can be set but the interrupt status bit is non-functional. 3651 */ 3652 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572, quirk_broken_intx_masking); 3653 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574, quirk_broken_intx_masking); 3654 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580, quirk_broken_intx_masking); 3655 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581, quirk_broken_intx_masking); 3656 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583, quirk_broken_intx_masking); 3657 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584, quirk_broken_intx_masking); 3658 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585, quirk_broken_intx_masking); 3659 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586, quirk_broken_intx_masking); 3660 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587, quirk_broken_intx_masking); 3661 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588, quirk_broken_intx_masking); 3662 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589, quirk_broken_intx_masking); 3663 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a, quirk_broken_intx_masking); 3664 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b, quirk_broken_intx_masking); 3665 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0, quirk_broken_intx_masking); 3666 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1, quirk_broken_intx_masking); 3667 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2, quirk_broken_intx_masking); 3668 3669 static u16 mellanox_broken_intx_devs[] = { 3670 PCI_DEVICE_ID_MELLANOX_HERMON_SDR, 3671 PCI_DEVICE_ID_MELLANOX_HERMON_DDR, 3672 PCI_DEVICE_ID_MELLANOX_HERMON_QDR, 3673 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2, 3674 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2, 3675 PCI_DEVICE_ID_MELLANOX_HERMON_EN, 3676 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2, 3677 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN, 3678 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2, 3679 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2, 3680 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2, 3681 PCI_DEVICE_ID_MELLANOX_CONNECTX2, 3682 PCI_DEVICE_ID_MELLANOX_CONNECTX3, 3683 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO, 3684 }; 3685 3686 #define CONNECTX_4_CURR_MAX_MINOR 99 3687 #define CONNECTX_4_INTX_SUPPORT_MINOR 14 3688 3689 /* 3690 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts. 3691 * If so, don't mark it as broken. 3692 * FW minor > 99 means older FW version format and no INTx masking support. 3693 * FW minor < 14 means new FW version format and no INTx masking support. 3694 */ 3695 static void mellanox_check_broken_intx_masking(struct pci_dev *pdev) 3696 { 3697 __be32 __iomem *fw_ver; 3698 u16 fw_major; 3699 u16 fw_minor; 3700 u16 fw_subminor; 3701 u32 fw_maj_min; 3702 u32 fw_sub_min; 3703 int i; 3704 3705 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) { 3706 if (pdev->device == mellanox_broken_intx_devs[i]) { 3707 pdev->broken_intx_masking = 1; 3708 return; 3709 } 3710 } 3711 3712 /* 3713 * Getting here means Connect-IB cards and up. Connect-IB has no INTx 3714 * support so shouldn't be checked further 3715 */ 3716 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB) 3717 return; 3718 3719 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 && 3720 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) 3721 return; 3722 3723 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */ 3724 if (pci_enable_device_mem(pdev)) { 3725 pci_warn(pdev, "Can't enable device memory\n"); 3726 return; 3727 } 3728 3729 fw_ver = ioremap(pci_resource_start(pdev, 0), 4); 3730 if (!fw_ver) { 3731 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n"); 3732 goto out; 3733 } 3734 3735 /* Reading from resource space should be 32b aligned */ 3736 fw_maj_min = ioread32be(fw_ver); 3737 fw_sub_min = ioread32be(fw_ver + 1); 3738 fw_major = fw_maj_min & 0xffff; 3739 fw_minor = fw_maj_min >> 16; 3740 fw_subminor = fw_sub_min & 0xffff; 3741 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR || 3742 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) { 3743 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n", 3744 fw_major, fw_minor, fw_subminor, pdev->device == 3745 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14); 3746 pdev->broken_intx_masking = 1; 3747 } 3748 3749 iounmap(fw_ver); 3750 3751 out: 3752 pci_disable_device(pdev); 3753 } 3754 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID, 3755 mellanox_check_broken_intx_masking); 3756 3757 static void quirk_no_bus_reset(struct pci_dev *dev) 3758 { 3759 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET; 3760 } 3761 3762 /* 3763 * After asserting Secondary Bus Reset to downstream devices via a GB10 3764 * Root Port, the link may not retrain correctly. 3765 * https://lore.kernel.org/r/20251113084441.2124737-1-Johnny-CC.Chang@mediatek.com 3766 */ 3767 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x22CE, quirk_no_bus_reset); 3768 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, 0x22D0, quirk_no_bus_reset); 3769 3770 /* 3771 * Some NVIDIA GPU devices do not work with bus reset, SBR needs to be 3772 * prevented for those affected devices. 3773 */ 3774 static void quirk_nvidia_no_bus_reset(struct pci_dev *dev) 3775 { 3776 if ((dev->device & 0xffc0) == 0x2340) 3777 quirk_no_bus_reset(dev); 3778 } 3779 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 3780 quirk_nvidia_no_bus_reset); 3781 3782 /* 3783 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset. 3784 * The device will throw a Link Down error on AER-capable systems and 3785 * regardless of AER, config space of the device is never accessible again 3786 * and typically causes the system to hang or reset when access is attempted. 3787 * https://lore.kernel.org/r/20140923210318.498dacbd@dualc.maya.org/ 3788 */ 3789 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset); 3790 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset); 3791 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset); 3792 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset); 3793 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0034, quirk_no_bus_reset); 3794 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003e, quirk_no_bus_reset); 3795 3796 /* 3797 * Root port on some Cavium CN8xxx chips do not successfully complete a bus 3798 * reset when used with certain child devices. After the reset, config 3799 * accesses to the child may fail. 3800 */ 3801 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset); 3802 3803 /* 3804 * Some TI KeyStone C667X devices do not support bus/hot reset. The PCIESS 3805 * automatically disables LTSSM when Secondary Bus Reset is received and 3806 * the device stops working. Prevent bus reset for these devices. With 3807 * this change, the device can be assigned to VMs with VFIO, but it will 3808 * leak state between VMs. Reference 3809 * https://e2e.ti.com/support/processors/f/791/t/954382 3810 */ 3811 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TI, 0xb005, quirk_no_bus_reset); 3812 3813 /* 3814 * Reports from users making use of PCI device assignment with ASM1164 3815 * controllers indicate an issue with bus reset where the device fails to 3816 * retrain. The issue appears more common in configurations with multiple 3817 * controllers. The device does indicate PM reset support (NoSoftRst-), 3818 * therefore this still leaves a viable reset method. 3819 * https://forum.proxmox.com/threads/problems-with-pcie-passthrough-with-two-identical-devices.149003/ 3820 */ 3821 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1164, quirk_no_bus_reset); 3822 3823 static void quirk_no_pm_reset(struct pci_dev *dev) 3824 { 3825 /* 3826 * We can't do a bus reset on root bus devices, but an ineffective 3827 * PM reset may be better than nothing. 3828 */ 3829 if (!pci_is_root_bus(dev->bus)) 3830 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET; 3831 } 3832 3833 /* 3834 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition 3835 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems 3836 * to have no effect on the device: it retains the framebuffer contents and 3837 * monitor sync. Advertising this support makes other layers, like VFIO, 3838 * assume pci_reset_function() is viable for this device. Mark it as 3839 * unavailable to skip it when testing reset methods. 3840 */ 3841 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 3842 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset); 3843 3844 /* 3845 * Spectrum-{1,2,3,4} devices report that a D3hot->D0 transition causes a reset 3846 * (i.e., they advertise NoSoftRst-). However, this transition does not have 3847 * any effect on the device: It continues to be operational and network ports 3848 * remain up. Advertising this support makes it seem as if a PM reset is viable 3849 * for these devices. Mark it as unavailable to skip it when testing reset 3850 * methods. 3851 */ 3852 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcb84, quirk_no_pm_reset); 3853 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf6c, quirk_no_pm_reset); 3854 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf70, quirk_no_pm_reset); 3855 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MELLANOX, 0xcf80, quirk_no_pm_reset); 3856 3857 /* 3858 * Thunderbolt controllers with broken MSI hotplug signaling: 3859 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part 3860 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge). 3861 */ 3862 static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev) 3863 { 3864 if (pdev->is_pciehp && 3865 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C || 3866 pdev->revision <= 1)) 3867 pdev->no_msi = 1; 3868 } 3869 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 3870 quirk_thunderbolt_hotplug_msi); 3871 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE, 3872 quirk_thunderbolt_hotplug_msi); 3873 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK, 3874 quirk_thunderbolt_hotplug_msi); 3875 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3876 quirk_thunderbolt_hotplug_msi); 3877 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE, 3878 quirk_thunderbolt_hotplug_msi); 3879 3880 #ifdef CONFIG_ACPI 3881 /* 3882 * Apple: Shutdown Cactus Ridge Thunderbolt controller. 3883 * 3884 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be 3885 * shutdown before suspend. Otherwise the native host interface (NHI) will not 3886 * be present after resume if a device was plugged in before suspend. 3887 * 3888 * The Thunderbolt controller consists of a PCIe switch with downstream 3889 * bridges leading to the NHI and to the tunnel PCI bridges. 3890 * 3891 * This quirk cuts power to the whole chip. Therefore we have to apply it 3892 * during suspend_noirq of the upstream bridge. 3893 * 3894 * Power is automagically restored before resume. No action is needed. 3895 */ 3896 static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev) 3897 { 3898 acpi_handle bridge, SXIO, SXFP, SXLV; 3899 3900 if (!x86_apple_machine) 3901 return; 3902 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM) 3903 return; 3904 3905 /* 3906 * SXIO/SXFP/SXLF turns off power to the Thunderbolt controller. 3907 * We don't know how to turn it back on again, but firmware does, 3908 * so we can only use SXIO/SXFP/SXLF if we're suspending via 3909 * firmware. 3910 */ 3911 if (!pm_suspend_via_firmware()) 3912 return; 3913 3914 bridge = ACPI_HANDLE(&dev->dev); 3915 if (!bridge) 3916 return; 3917 3918 /* 3919 * SXIO and SXLV are present only on machines requiring this quirk. 3920 * Thunderbolt bridges in external devices might have the same 3921 * device ID as those on the host, but they will not have the 3922 * associated ACPI methods. This implicitly checks that we are at 3923 * the right bridge. 3924 */ 3925 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO)) 3926 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP)) 3927 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV))) 3928 return; 3929 pci_info(dev, "quirk: cutting power to Thunderbolt controller...\n"); 3930 3931 /* magic sequence */ 3932 acpi_execute_simple_method(SXIO, NULL, 1); 3933 acpi_execute_simple_method(SXFP, NULL, 0); 3934 msleep(300); 3935 acpi_execute_simple_method(SXLV, NULL, 0); 3936 acpi_execute_simple_method(SXIO, NULL, 0); 3937 acpi_execute_simple_method(SXLV, NULL, 0); 3938 } 3939 DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL, 3940 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 3941 quirk_apple_poweroff_thunderbolt); 3942 #endif 3943 3944 /* 3945 * Following are device-specific reset methods which can be used to 3946 * reset a single function if other methods (e.g. FLR, PM D0->D3) are 3947 * not available. 3948 */ 3949 static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, bool probe) 3950 { 3951 /* 3952 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf 3953 * 3954 * The 82599 supports FLR on VFs, but FLR support is reported only 3955 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5). 3956 * Thus we must call pcie_flr() directly without first checking if it is 3957 * supported. 3958 */ 3959 if (!probe) 3960 pcie_flr(dev); 3961 return 0; 3962 } 3963 3964 #define SOUTH_CHICKEN2 0xc2004 3965 #define PCH_PP_STATUS 0xc7200 3966 #define PCH_PP_CONTROL 0xc7204 3967 #define MSG_CTL 0x45010 3968 #define NSDE_PWR_STATE 0xd0100 3969 #define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */ 3970 3971 static int reset_ivb_igd(struct pci_dev *dev, bool probe) 3972 { 3973 void __iomem *mmio_base; 3974 unsigned long timeout; 3975 u32 val; 3976 3977 if (probe) 3978 return 0; 3979 3980 mmio_base = pci_iomap(dev, 0, 0); 3981 if (!mmio_base) 3982 return -ENOMEM; 3983 3984 iowrite32(0x00000002, mmio_base + MSG_CTL); 3985 3986 /* 3987 * Clobbering SOUTH_CHICKEN2 register is fine only if the next 3988 * driver loaded sets the right bits. However, this's a reset and 3989 * the bits have been set by i915 previously, so we clobber 3990 * SOUTH_CHICKEN2 register directly here. 3991 */ 3992 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2); 3993 3994 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe; 3995 iowrite32(val, mmio_base + PCH_PP_CONTROL); 3996 3997 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT); 3998 do { 3999 val = ioread32(mmio_base + PCH_PP_STATUS); 4000 if ((val & 0xb0000000) == 0) 4001 goto reset_complete; 4002 msleep(10); 4003 } while (time_before(jiffies, timeout)); 4004 pci_warn(dev, "timeout during reset\n"); 4005 4006 reset_complete: 4007 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE); 4008 4009 pci_iounmap(dev, mmio_base); 4010 return 0; 4011 } 4012 4013 /* Device-specific reset method for Chelsio T4-based adapters */ 4014 static int reset_chelsio_generic_dev(struct pci_dev *dev, bool probe) 4015 { 4016 u16 old_command; 4017 u16 msix_flags; 4018 4019 /* 4020 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating 4021 * that we have no device-specific reset method. 4022 */ 4023 if ((dev->device & 0xf000) != 0x4000) 4024 return -ENOTTY; 4025 4026 /* 4027 * If this is the "probe" phase, return 0 indicating that we can 4028 * reset this device. 4029 */ 4030 if (probe) 4031 return 0; 4032 4033 /* 4034 * T4 can wedge if there are DMAs in flight within the chip and Bus 4035 * Master has been disabled. We need to have it on till the Function 4036 * Level Reset completes. (BUS_MASTER is disabled in 4037 * pci_reset_function()). 4038 */ 4039 pci_read_config_word(dev, PCI_COMMAND, &old_command); 4040 pci_write_config_word(dev, PCI_COMMAND, 4041 old_command | PCI_COMMAND_MASTER); 4042 4043 /* 4044 * Perform the actual device function reset, saving and restoring 4045 * configuration information around the reset. 4046 */ 4047 pci_save_state(dev); 4048 4049 /* 4050 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts 4051 * are disabled when an MSI-X interrupt message needs to be delivered. 4052 * So we briefly re-enable MSI-X interrupts for the duration of the 4053 * FLR. The pci_restore_state() below will restore the original 4054 * MSI-X state. 4055 */ 4056 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags); 4057 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0) 4058 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, 4059 msix_flags | 4060 PCI_MSIX_FLAGS_ENABLE | 4061 PCI_MSIX_FLAGS_MASKALL); 4062 4063 pcie_flr(dev); 4064 4065 /* 4066 * Restore the configuration information (BAR values, etc.) including 4067 * the original PCI Configuration Space Command word, and return 4068 * success. 4069 */ 4070 pci_restore_state(dev); 4071 pci_write_config_word(dev, PCI_COMMAND, old_command); 4072 return 0; 4073 } 4074 4075 #define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed 4076 #define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156 4077 #define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166 4078 4079 /* 4080 * The Samsung SM961/PM961 controller can sometimes enter a fatal state after 4081 * FLR where config space reads from the device return -1. We seem to be 4082 * able to avoid this condition if we disable the NVMe controller prior to 4083 * FLR. This quirk is generic for any NVMe class device requiring similar 4084 * assistance to quiesce the device prior to FLR. 4085 * 4086 * NVMe specification: https://nvmexpress.org/resources/specifications/ 4087 * Revision 1.0e: 4088 * Chapter 2: Required and optional PCI config registers 4089 * Chapter 3: NVMe control registers 4090 * Chapter 7.3: Reset behavior 4091 */ 4092 static int nvme_disable_and_flr(struct pci_dev *dev, bool probe) 4093 { 4094 void __iomem *bar; 4095 u16 cmd; 4096 u32 cfg; 4097 4098 if (dev->class != PCI_CLASS_STORAGE_EXPRESS || 4099 pcie_reset_flr(dev, PCI_RESET_PROBE) || !pci_resource_start(dev, 0)) 4100 return -ENOTTY; 4101 4102 if (probe) 4103 return 0; 4104 4105 bar = pci_iomap(dev, 0, NVME_REG_CC + sizeof(cfg)); 4106 if (!bar) 4107 return -ENOTTY; 4108 4109 pci_read_config_word(dev, PCI_COMMAND, &cmd); 4110 pci_write_config_word(dev, PCI_COMMAND, cmd | PCI_COMMAND_MEMORY); 4111 4112 cfg = readl(bar + NVME_REG_CC); 4113 4114 /* Disable controller if enabled */ 4115 if (cfg & NVME_CC_ENABLE) { 4116 u32 cap = readl(bar + NVME_REG_CAP); 4117 unsigned long timeout; 4118 4119 /* 4120 * Per nvme_disable_ctrl() skip shutdown notification as it 4121 * could complete commands to the admin queue. We only intend 4122 * to quiesce the device before reset. 4123 */ 4124 cfg &= ~(NVME_CC_SHN_MASK | NVME_CC_ENABLE); 4125 4126 writel(cfg, bar + NVME_REG_CC); 4127 4128 /* 4129 * Some controllers require an additional delay here, see 4130 * NVME_QUIRK_DELAY_BEFORE_CHK_RDY. None of those are yet 4131 * supported by this quirk. 4132 */ 4133 4134 /* Cap register provides max timeout in 500ms increments */ 4135 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies; 4136 4137 for (;;) { 4138 u32 status = readl(bar + NVME_REG_CSTS); 4139 4140 /* Ready status becomes zero on disable complete */ 4141 if (!(status & NVME_CSTS_RDY)) 4142 break; 4143 4144 msleep(100); 4145 4146 if (time_after(jiffies, timeout)) { 4147 pci_warn(dev, "Timeout waiting for NVMe ready status to clear after disable\n"); 4148 break; 4149 } 4150 } 4151 } 4152 4153 pci_iounmap(dev, bar); 4154 4155 pcie_flr(dev); 4156 4157 return 0; 4158 } 4159 4160 /* 4161 * Some NVMe controllers such as Intel DC P3700 and Solidigm P44 Pro will 4162 * timeout waiting for ready status to change after NVMe enable if the driver 4163 * starts interacting with the device too soon after FLR. A 250ms delay after 4164 * FLR has heuristically proven to produce reliably working results for device 4165 * assignment cases. 4166 */ 4167 static int delay_250ms_after_flr(struct pci_dev *dev, bool probe) 4168 { 4169 if (probe) 4170 return pcie_reset_flr(dev, PCI_RESET_PROBE); 4171 4172 pcie_reset_flr(dev, PCI_RESET_DO_RESET); 4173 4174 msleep(250); 4175 4176 return 0; 4177 } 4178 4179 #define PCI_DEVICE_ID_HINIC_VF 0x375E 4180 #define HINIC_VF_FLR_TYPE 0x1000 4181 #define HINIC_VF_FLR_CAP_BIT (1UL << 30) 4182 #define HINIC_VF_OP 0xE80 4183 #define HINIC_VF_FLR_PROC_BIT (1UL << 18) 4184 #define HINIC_OPERATION_TIMEOUT 15000 /* 15 seconds */ 4185 4186 /* Device-specific reset method for Huawei Intelligent NIC virtual functions */ 4187 static int reset_hinic_vf_dev(struct pci_dev *pdev, bool probe) 4188 { 4189 unsigned long timeout; 4190 void __iomem *bar; 4191 u32 val; 4192 4193 if (probe) 4194 return 0; 4195 4196 bar = pci_iomap(pdev, 0, 0); 4197 if (!bar) 4198 return -ENOTTY; 4199 4200 /* Get and check firmware capabilities */ 4201 val = ioread32be(bar + HINIC_VF_FLR_TYPE); 4202 if (!(val & HINIC_VF_FLR_CAP_BIT)) { 4203 pci_iounmap(pdev, bar); 4204 return -ENOTTY; 4205 } 4206 4207 /* Set HINIC_VF_FLR_PROC_BIT for the start of FLR */ 4208 val = ioread32be(bar + HINIC_VF_OP); 4209 val = val | HINIC_VF_FLR_PROC_BIT; 4210 iowrite32be(val, bar + HINIC_VF_OP); 4211 4212 pcie_flr(pdev); 4213 4214 /* 4215 * The device must recapture its Bus and Device Numbers after FLR 4216 * in order generate Completions. Issue a config write to let the 4217 * device capture this information. 4218 */ 4219 pci_write_config_word(pdev, PCI_VENDOR_ID, 0); 4220 4221 /* Firmware clears HINIC_VF_FLR_PROC_BIT when reset is complete */ 4222 timeout = jiffies + msecs_to_jiffies(HINIC_OPERATION_TIMEOUT); 4223 do { 4224 val = ioread32be(bar + HINIC_VF_OP); 4225 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4226 goto reset_complete; 4227 msleep(20); 4228 } while (time_before(jiffies, timeout)); 4229 4230 val = ioread32be(bar + HINIC_VF_OP); 4231 if (!(val & HINIC_VF_FLR_PROC_BIT)) 4232 goto reset_complete; 4233 4234 pci_warn(pdev, "Reset dev timeout, FLR ack reg: %#010x\n", val); 4235 4236 reset_complete: 4237 pci_iounmap(pdev, bar); 4238 4239 return 0; 4240 } 4241 4242 static const struct pci_dev_reset_methods pci_dev_reset_methods[] = { 4243 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF, 4244 reset_intel_82599_sfp_virtfn }, 4245 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA, 4246 reset_ivb_igd }, 4247 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA, 4248 reset_ivb_igd }, 4249 { PCI_VENDOR_ID_SAMSUNG, 0xa804, nvme_disable_and_flr }, 4250 { PCI_VENDOR_ID_INTEL, 0x0953, delay_250ms_after_flr }, 4251 { PCI_VENDOR_ID_INTEL, 0x0a54, delay_250ms_after_flr }, 4252 { PCI_VENDOR_ID_SOLIDIGM, 0xf1ac, delay_250ms_after_flr }, 4253 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4254 reset_chelsio_generic_dev }, 4255 { PCI_VENDOR_ID_HUAWEI, PCI_DEVICE_ID_HINIC_VF, 4256 reset_hinic_vf_dev }, 4257 { 0 } 4258 }; 4259 4260 static int __pci_dev_specific_reset(struct pci_dev *dev, bool probe, 4261 const struct pci_dev_reset_methods *i) 4262 { 4263 int ret; 4264 4265 ret = pci_dev_reset_iommu_prepare(dev); 4266 if (ret) { 4267 pci_err(dev, "failed to stop IOMMU for a PCI reset: %d\n", ret); 4268 return ret; 4269 } 4270 4271 ret = i->reset(dev, probe); 4272 pci_dev_reset_iommu_done(dev); 4273 return ret; 4274 } 4275 4276 /* 4277 * These device-specific reset methods are here rather than in a driver 4278 * because when a host assigns a device to a guest VM, the host may need 4279 * to reset the device but probably doesn't have a driver for it. 4280 */ 4281 int pci_dev_specific_reset(struct pci_dev *dev, bool probe) 4282 { 4283 const struct pci_dev_reset_methods *i; 4284 4285 for (i = pci_dev_reset_methods; i->reset; i++) { 4286 if ((i->vendor == dev->vendor || 4287 i->vendor == (u16)PCI_ANY_ID) && 4288 (i->device == dev->device || 4289 i->device == (u16)PCI_ANY_ID)) 4290 return __pci_dev_specific_reset(dev, probe, i); 4291 } 4292 4293 return -ENOTTY; 4294 } 4295 4296 static void quirk_dma_func0_alias(struct pci_dev *dev) 4297 { 4298 if (PCI_FUNC(dev->devfn) != 0) 4299 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0), 1); 4300 } 4301 4302 /* 4303 * https://bugzilla.redhat.com/show_bug.cgi?id=605888 4304 * 4305 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA. 4306 */ 4307 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias); 4308 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias); 4309 4310 /* Some Glenfly chips use function 0 as the PCIe Requester ID for DMA */ 4311 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d40, quirk_dma_func0_alias); 4312 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_GLENFLY, 0x3d41, quirk_dma_func0_alias); 4313 4314 static void quirk_dma_func1_alias(struct pci_dev *dev) 4315 { 4316 if (PCI_FUNC(dev->devfn) != 1) 4317 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1), 1); 4318 } 4319 4320 /* 4321 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some 4322 * SKUs function 1 is present and is a legacy IDE controller, in other 4323 * SKUs this function is not present, making this a ghost requester. 4324 * https://bugzilla.kernel.org/show_bug.cgi?id=42679 4325 */ 4326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120, 4327 quirk_dma_func1_alias); 4328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123, 4329 quirk_dma_func1_alias); 4330 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c136 */ 4331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9125, 4332 quirk_dma_func1_alias); 4333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128, 4334 quirk_dma_func1_alias); 4335 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */ 4336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130, 4337 quirk_dma_func1_alias); 4338 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170, 4339 quirk_dma_func1_alias); 4340 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */ 4341 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172, 4342 quirk_dma_func1_alias); 4343 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */ 4344 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a, 4345 quirk_dma_func1_alias); 4346 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */ 4347 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182, 4348 quirk_dma_func1_alias); 4349 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c134 */ 4350 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9183, 4351 quirk_dma_func1_alias); 4352 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */ 4353 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0, 4354 quirk_dma_func1_alias); 4355 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135 */ 4356 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9215, 4357 quirk_dma_func1_alias); 4358 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */ 4359 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220, 4360 quirk_dma_func1_alias); 4361 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */ 4362 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230, 4363 quirk_dma_func1_alias); 4364 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9235, 4365 quirk_dma_func1_alias); 4366 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642, 4367 quirk_dma_func1_alias); 4368 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645, 4369 quirk_dma_func1_alias); 4370 /* https://bugs.gentoo.org/show_bug.cgi?id=497630 */ 4371 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON, 4372 PCI_DEVICE_ID_JMICRON_JMB388_ESD, 4373 quirk_dma_func1_alias); 4374 /* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */ 4375 DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */ 4376 0x0122, /* Plextor M6E (Marvell 88SS9183)*/ 4377 quirk_dma_func1_alias); 4378 4379 /* 4380 * Some devices DMA with the wrong devfn, not just the wrong function. 4381 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where 4382 * the alias is "fixed" and independent of the device devfn. 4383 * 4384 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O 4385 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a 4386 * single device on the secondary bus. In reality, the single exposed 4387 * device at 0e.0 is the Address Translation Unit (ATU) of the controller 4388 * that provides a bridge to the internal bus of the I/O processor. The 4389 * controller supports private devices, which can be hidden from PCI config 4390 * space. In the case of the Adaptec 3405, a private device at 01.0 4391 * appears to be the DMA engine, which therefore needs to become a DMA 4392 * alias for the device. 4393 */ 4394 static const struct pci_device_id fixed_dma_alias_tbl[] = { 4395 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4396 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */ 4397 .driver_data = PCI_DEVFN(1, 0) }, 4398 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285, 4399 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */ 4400 .driver_data = PCI_DEVFN(1, 0) }, 4401 { 0 } 4402 }; 4403 4404 static void quirk_fixed_dma_alias(struct pci_dev *dev) 4405 { 4406 const struct pci_device_id *id; 4407 4408 id = pci_match_id(fixed_dma_alias_tbl, dev); 4409 if (id) 4410 pci_add_dma_alias(dev, id->driver_data, 1); 4411 } 4412 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias); 4413 4414 /* 4415 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in 4416 * using the wrong DMA alias for the device. Some of these devices can be 4417 * used as either forward or reverse bridges, so we need to test whether the 4418 * device is operating in the correct mode. We could probably apply this 4419 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test 4420 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and 4421 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge. 4422 */ 4423 static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev) 4424 { 4425 if (!pci_is_root_bus(pdev->bus) && 4426 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE && 4427 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) && 4428 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE) 4429 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS; 4430 } 4431 /* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */ 4432 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080, 4433 quirk_use_pcie_bridge_dma_alias); 4434 /* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */ 4435 DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias); 4436 /* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */ 4437 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias); 4438 /* ITE 8893 has the same problem as the 8892 */ 4439 DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias); 4440 /* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */ 4441 DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias); 4442 4443 /* 4444 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to 4445 * be added as aliases to the DMA device in order to allow buffer access 4446 * when IOMMU is enabled. Following devfns have to match RIT-LUT table 4447 * programmed in the EEPROM. 4448 */ 4449 static void quirk_mic_x200_dma_alias(struct pci_dev *pdev) 4450 { 4451 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0), 1); 4452 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0), 1); 4453 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3), 1); 4454 } 4455 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias); 4456 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias); 4457 4458 /* 4459 * Intel Visual Compute Accelerator (VCA) is a family of PCIe add-in devices 4460 * exposing computational units via Non Transparent Bridges (NTB, PEX 87xx). 4461 * 4462 * Similarly to MIC x200, we need to add DMA aliases to allow buffer access 4463 * when IOMMU is enabled. These aliases allow computational unit access to 4464 * host memory. These aliases mark the whole VCA device as one IOMMU 4465 * group. 4466 * 4467 * All possible slot numbers (0x20) are used, since we are unable to tell 4468 * what slot is used on other side. This quirk is intended for both host 4469 * and computational unit sides. The VCA devices have up to five functions 4470 * (four for DMA channels and one additional). 4471 */ 4472 static void quirk_pex_vca_alias(struct pci_dev *pdev) 4473 { 4474 const unsigned int num_pci_slots = 0x20; 4475 unsigned int slot; 4476 4477 for (slot = 0; slot < num_pci_slots; slot++) 4478 pci_add_dma_alias(pdev, PCI_DEVFN(slot, 0x0), 5); 4479 } 4480 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2954, quirk_pex_vca_alias); 4481 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2955, quirk_pex_vca_alias); 4482 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2956, quirk_pex_vca_alias); 4483 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2958, quirk_pex_vca_alias); 4484 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2959, quirk_pex_vca_alias); 4485 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x295A, quirk_pex_vca_alias); 4486 4487 /* 4488 * The IOMMU and interrupt controller on Broadcom Vulcan/Cavium ThunderX2 are 4489 * associated not at the root bus, but at a bridge below. This quirk avoids 4490 * generating invalid DMA aliases. 4491 */ 4492 static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev) 4493 { 4494 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT; 4495 } 4496 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000, 4497 quirk_bridge_cavm_thrx2_pcie_root); 4498 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084, 4499 quirk_bridge_cavm_thrx2_pcie_root); 4500 4501 /* 4502 * AST1150 doesn't use a real PCI bus and always forwards the requester ID 4503 * from downstream devices. 4504 */ 4505 static void quirk_aspeed_pci_bridge_no_alias(struct pci_dev *pdev) 4506 { 4507 pdev->dev_flags |= PCI_DEV_FLAGS_PCI_BRIDGE_NO_ALIAS; 4508 } 4509 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASPEED, 0x1150, quirk_aspeed_pci_bridge_no_alias); 4510 4511 /* 4512 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero) 4513 * class code. Fix it. 4514 */ 4515 static void quirk_tw686x_class(struct pci_dev *pdev) 4516 { 4517 u32 class = pdev->class; 4518 4519 /* Use "Multimedia controller" class */ 4520 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01; 4521 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n", 4522 class, pdev->class); 4523 } 4524 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8, 4525 quirk_tw686x_class); 4526 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8, 4527 quirk_tw686x_class); 4528 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8, 4529 quirk_tw686x_class); 4530 DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8, 4531 quirk_tw686x_class); 4532 4533 /* 4534 * Some devices have problems with Transaction Layer Packets with the Relaxed 4535 * Ordering Attribute set. Such devices should mark themselves and other 4536 * device drivers should check before sending TLPs with RO set. 4537 */ 4538 static void quirk_relaxedordering_disable(struct pci_dev *dev) 4539 { 4540 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING; 4541 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n"); 4542 } 4543 4544 /* 4545 * Intel Xeon processors based on Broadwell/Haswell microarchitecture Root 4546 * Complex have a Flow Control Credit issue which can cause performance 4547 * problems with Upstream Transaction Layer Packets with Relaxed Ordering set. 4548 */ 4549 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8, 4550 quirk_relaxedordering_disable); 4551 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8, 4552 quirk_relaxedordering_disable); 4553 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8, 4554 quirk_relaxedordering_disable); 4555 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8, 4556 quirk_relaxedordering_disable); 4557 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8, 4558 quirk_relaxedordering_disable); 4559 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8, 4560 quirk_relaxedordering_disable); 4561 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8, 4562 quirk_relaxedordering_disable); 4563 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8, 4564 quirk_relaxedordering_disable); 4565 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8, 4566 quirk_relaxedordering_disable); 4567 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8, 4568 quirk_relaxedordering_disable); 4569 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8, 4570 quirk_relaxedordering_disable); 4571 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8, 4572 quirk_relaxedordering_disable); 4573 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8, 4574 quirk_relaxedordering_disable); 4575 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8, 4576 quirk_relaxedordering_disable); 4577 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8, 4578 quirk_relaxedordering_disable); 4579 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8, 4580 quirk_relaxedordering_disable); 4581 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8, 4582 quirk_relaxedordering_disable); 4583 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8, 4584 quirk_relaxedordering_disable); 4585 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8, 4586 quirk_relaxedordering_disable); 4587 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8, 4588 quirk_relaxedordering_disable); 4589 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8, 4590 quirk_relaxedordering_disable); 4591 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8, 4592 quirk_relaxedordering_disable); 4593 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8, 4594 quirk_relaxedordering_disable); 4595 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8, 4596 quirk_relaxedordering_disable); 4597 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8, 4598 quirk_relaxedordering_disable); 4599 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8, 4600 quirk_relaxedordering_disable); 4601 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8, 4602 quirk_relaxedordering_disable); 4603 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8, 4604 quirk_relaxedordering_disable); 4605 4606 /* 4607 * The AMD ARM A1100 (aka "SEATTLE") SoC has a bug in its PCIe Root Complex 4608 * where Upstream Transaction Layer Packets with the Relaxed Ordering 4609 * Attribute clear are allowed to bypass earlier TLPs with Relaxed Ordering 4610 * set. This is a violation of the PCIe 3.0 Transaction Ordering Rules 4611 * outlined in Section 2.4.1 (PCI Express(r) Base Specification Revision 3.0 4612 * November 10, 2010). As a result, on this platform we can't use Relaxed 4613 * Ordering for Upstream TLPs. 4614 */ 4615 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8, 4616 quirk_relaxedordering_disable); 4617 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8, 4618 quirk_relaxedordering_disable); 4619 DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8, 4620 quirk_relaxedordering_disable); 4621 4622 /* 4623 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same 4624 * values for the Attribute as were supplied in the header of the 4625 * corresponding Request, except as explicitly allowed when IDO is used." 4626 * 4627 * If a non-compliant device generates a completion with a different 4628 * attribute than the request, the receiver may accept it (which itself 4629 * seems non-compliant based on sec 2.3.2), or it may handle it as a 4630 * Malformed TLP or an Unexpected Completion, which will probably lead to a 4631 * device access timeout. 4632 * 4633 * If the non-compliant device generates completions with zero attributes 4634 * (instead of copying the attributes from the request), we can work around 4635 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in 4636 * upstream devices so they always generate requests with zero attributes. 4637 * 4638 * This affects other devices under the same Root Port, but since these 4639 * attributes are performance hints, there should be no functional problem. 4640 * 4641 * Note that Configuration Space accesses are never supposed to have TLP 4642 * Attributes, so we're safe waiting till after any Configuration Space 4643 * accesses to do the Root Port fixup. 4644 */ 4645 static void quirk_disable_root_port_attributes(struct pci_dev *pdev) 4646 { 4647 struct pci_dev *root_port = pcie_find_root_port(pdev); 4648 4649 if (!root_port) { 4650 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n"); 4651 return; 4652 } 4653 4654 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n", 4655 dev_name(&pdev->dev)); 4656 pcie_capability_clear_word(root_port, PCI_EXP_DEVCTL, 4657 PCI_EXP_DEVCTL_RELAX_EN | 4658 PCI_EXP_DEVCTL_NOSNOOP_EN); 4659 } 4660 4661 /* 4662 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the 4663 * Completion it generates. 4664 */ 4665 static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev) 4666 { 4667 /* 4668 * This mask/compare operation selects for Physical Function 4 on a 4669 * T5. We only need to fix up the Root Port once for any of the 4670 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely 4671 * 0x54xx so we use that one. 4672 */ 4673 if ((pdev->device & 0xff00) == 0x5400) 4674 quirk_disable_root_port_attributes(pdev); 4675 } 4676 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID, 4677 quirk_chelsio_T5_disable_root_port_attributes); 4678 4679 /* 4680 * pci_acs_ctrl_enabled - compare desired ACS controls with those provided 4681 * by a device 4682 * @acs_ctrl_req: Bitmask of desired ACS controls 4683 * @acs_ctrl_ena: Bitmask of ACS controls enabled or provided implicitly by 4684 * the hardware design 4685 * 4686 * Return 1 if all ACS controls in the @acs_ctrl_req bitmask are included 4687 * in @acs_ctrl_ena, i.e., the device provides all the access controls the 4688 * caller desires. Return 0 otherwise. 4689 */ 4690 static int pci_acs_ctrl_enabled(u16 acs_ctrl_req, u16 acs_ctrl_ena) 4691 { 4692 if ((acs_ctrl_req & acs_ctrl_ena) == acs_ctrl_req) 4693 return 1; 4694 return 0; 4695 } 4696 4697 /* 4698 * AMD has indicated that the devices below do not support peer-to-peer 4699 * in any system where they are found in the southbridge with an AMD 4700 * IOMMU in the system. Multifunction devices that do not support 4701 * peer-to-peer between functions can claim to support a subset of ACS. 4702 * Such devices effectively enable request redirect (RR) and completion 4703 * redirect (CR) since all transactions are redirected to the upstream 4704 * root complex. 4705 * 4706 * https://lore.kernel.org/r/201207111426.q6BEQTbh002928@mail.maya.org/ 4707 * https://lore.kernel.org/r/20120711165854.GM25282@amd.com/ 4708 * https://lore.kernel.org/r/20121005130857.GX4009@amd.com/ 4709 * 4710 * 1002:4385 SBx00 SMBus Controller 4711 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller 4712 * 1002:4383 SBx00 Azalia (Intel HDA) 4713 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller 4714 * 1002:4384 SBx00 PCI to PCI Bridge 4715 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller 4716 * 4717 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15 4718 * 4719 * 1022:780f [AMD] FCH PCI Bridge 4720 * 1022:7809 [AMD] FCH USB OHCI Controller 4721 */ 4722 static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags) 4723 { 4724 #ifdef CONFIG_ACPI 4725 struct acpi_table_header *header = NULL; 4726 acpi_status status; 4727 4728 /* Targeting multifunction devices on the SB (appears on root bus) */ 4729 if (!dev->multifunction || !pci_is_root_bus(dev->bus)) 4730 return -ENODEV; 4731 4732 /* The IVRS table describes the AMD IOMMU */ 4733 status = acpi_get_table("IVRS", 0, &header); 4734 if (ACPI_FAILURE(status)) 4735 return -ENODEV; 4736 4737 acpi_put_table(header); 4738 4739 /* Filter out flags not applicable to multifunction */ 4740 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT); 4741 4742 return pci_acs_ctrl_enabled(acs_flags, PCI_ACS_RR | PCI_ACS_CR); 4743 #else 4744 return -ENODEV; 4745 #endif 4746 } 4747 4748 static bool pci_quirk_cavium_acs_match(struct pci_dev *dev) 4749 { 4750 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4751 return false; 4752 4753 switch (dev->device) { 4754 /* 4755 * Effectively selects all downstream ports for whole ThunderX1 4756 * (which represents 8 SoCs). 4757 */ 4758 case 0xa000 ... 0xa7ff: /* ThunderX1 */ 4759 case 0xaf84: /* ThunderX2 */ 4760 case 0xb884: /* ThunderX3 */ 4761 return true; 4762 default: 4763 return false; 4764 } 4765 } 4766 4767 static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags) 4768 { 4769 if (!pci_quirk_cavium_acs_match(dev)) 4770 return -ENOTTY; 4771 4772 /* 4773 * Cavium Root Ports don't advertise an ACS capability. However, 4774 * the RTL internally implements similar protection as if ACS had 4775 * Source Validation, Request Redirection, Completion Redirection, 4776 * and Upstream Forwarding features enabled. Assert that the 4777 * hardware implements and enables equivalent ACS functionality for 4778 * these flags. 4779 */ 4780 return pci_acs_ctrl_enabled(acs_flags, 4781 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4782 } 4783 4784 static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags) 4785 { 4786 /* 4787 * X-Gene Root Ports matching this quirk do not allow peer-to-peer 4788 * transactions with others, allowing masking out these bits as if they 4789 * were unimplemented in the ACS capability. 4790 */ 4791 return pci_acs_ctrl_enabled(acs_flags, 4792 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4793 } 4794 4795 /* 4796 * Many Zhaoxin Root Ports and Switch Downstream Ports have no ACS capability. 4797 * But the implementation could block peer-to-peer transactions between them 4798 * and provide ACS-like functionality. 4799 */ 4800 static int pci_quirk_zhaoxin_pcie_ports_acs(struct pci_dev *dev, u16 acs_flags) 4801 { 4802 if (!pci_is_pcie(dev) || 4803 ((pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) && 4804 (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM))) 4805 return -ENOTTY; 4806 4807 /* 4808 * Future Zhaoxin Root Ports and Switch Downstream Ports will 4809 * implement ACS capability in accordance with the PCIe Spec. 4810 */ 4811 switch (dev->device) { 4812 case 0x0710 ... 0x071e: 4813 case 0x0721: 4814 case 0x0723 ... 0x0752: 4815 return pci_acs_ctrl_enabled(acs_flags, 4816 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4817 } 4818 4819 return false; 4820 } 4821 4822 /* 4823 * Many Intel PCH Root Ports do provide ACS-like features to disable peer 4824 * transactions and validate bus numbers in requests, but do not provide an 4825 * actual PCIe ACS capability. This is the list of device IDs known to fall 4826 * into that category as provided by Intel in Red Hat bugzilla 1037684. 4827 */ 4828 static const u16 pci_quirk_intel_pch_acs_ids[] = { 4829 /* Ibexpeak PCH */ 4830 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49, 4831 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51, 4832 /* Cougarpoint PCH */ 4833 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17, 4834 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f, 4835 /* Pantherpoint PCH */ 4836 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17, 4837 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f, 4838 /* Lynxpoint-H PCH */ 4839 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17, 4840 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f, 4841 /* Lynxpoint-LP PCH */ 4842 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17, 4843 0x9c18, 0x9c19, 0x9c1a, 0x9c1b, 4844 /* Wildcat PCH */ 4845 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97, 4846 0x9c98, 0x9c99, 0x9c9a, 0x9c9b, 4847 /* Patsburg (X79) PCH */ 4848 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e, 4849 /* Wellsburg (X99) PCH */ 4850 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17, 4851 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e, 4852 /* Lynx Point (9 series) PCH */ 4853 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e, 4854 }; 4855 4856 static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev) 4857 { 4858 int i; 4859 4860 /* Filter out a few obvious non-matches first */ 4861 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4862 return false; 4863 4864 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++) 4865 if (pci_quirk_intel_pch_acs_ids[i] == dev->device) 4866 return true; 4867 4868 return false; 4869 } 4870 4871 static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags) 4872 { 4873 if (!pci_quirk_intel_pch_acs_match(dev)) 4874 return -ENOTTY; 4875 4876 if (dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK) 4877 return pci_acs_ctrl_enabled(acs_flags, 4878 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4879 4880 return pci_acs_ctrl_enabled(acs_flags, 0); 4881 } 4882 4883 /* 4884 * These QCOM Root Ports do provide ACS-like features to disable peer 4885 * transactions and validate bus numbers in requests, but do not provide an 4886 * actual PCIe ACS capability. Hardware supports source validation but it 4887 * will report the issue as Completer Abort instead of ACS Violation. 4888 * Hardware doesn't support peer-to-peer and each Root Port is a Root 4889 * Complex with unique segment numbers. It is not possible for one Root 4890 * Port to pass traffic to another Root Port. All PCIe transactions are 4891 * terminated inside the Root Port. 4892 */ 4893 static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags) 4894 { 4895 return pci_acs_ctrl_enabled(acs_flags, 4896 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4897 } 4898 4899 /* 4900 * Each of these NXP Root Ports is in a Root Complex with a unique segment 4901 * number and does provide isolation features to disable peer transactions 4902 * and validate bus numbers in requests, but does not provide an ACS 4903 * capability. 4904 */ 4905 static int pci_quirk_nxp_rp_acs(struct pci_dev *dev, u16 acs_flags) 4906 { 4907 return pci_acs_ctrl_enabled(acs_flags, 4908 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4909 } 4910 4911 static int pci_quirk_al_acs(struct pci_dev *dev, u16 acs_flags) 4912 { 4913 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4914 return -ENOTTY; 4915 4916 /* 4917 * Amazon's Annapurna Labs root ports don't include an ACS capability, 4918 * but do include ACS-like functionality. The hardware doesn't support 4919 * peer-to-peer transactions via the root port and each has a unique 4920 * segment number. 4921 * 4922 * Additionally, the root ports cannot send traffic to each other. 4923 */ 4924 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 4925 4926 return acs_flags ? 0 : 1; 4927 } 4928 4929 /* 4930 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in 4931 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2, 4932 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and 4933 * control registers whereas the PCIe spec packs them into words (Rev 3.0, 4934 * 7.16 ACS Extended Capability). The bit definitions are correct, but the 4935 * control register is at offset 8 instead of 6 and we should probably use 4936 * dword accesses to them. This applies to the following PCI Device IDs, as 4937 * found in volume 1 of the datasheet[2]: 4938 * 4939 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16} 4940 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20} 4941 * 4942 * N.B. This doesn't fix what lspci shows. 4943 * 4944 * The 100 series chipset specification update includes this as errata #23[3]. 4945 * 4946 * The 200 series chipset (Union Point) has the same bug according to the 4947 * specification update (Intel 200 Series Chipset Family Platform Controller 4948 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001, 4949 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this 4950 * chipset include: 4951 * 4952 * 0xa290-0xa29f PCI Express Root port #{0-16} 4953 * 0xa2e7-0xa2ee PCI Express Root port #{17-24} 4954 * 4955 * Mobile chipsets are also affected, 7th & 8th Generation 4956 * Specification update confirms ACS errata 22, status no fix: (7th Generation 4957 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel 4958 * Processor Family I/O for U Quad Core Platforms Specification Update, 4959 * August 2017, Revision 002, Document#: 334660-002)[6] 4960 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O 4961 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U 4962 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7] 4963 * 4964 * 0x9d10-0x9d1b PCI Express Root port #{1-12} 4965 * 4966 * [1] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html 4967 * [2] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html 4968 * [3] https://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html 4969 * [4] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html 4970 * [5] https://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html 4971 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html 4972 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html 4973 */ 4974 static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev) 4975 { 4976 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT) 4977 return false; 4978 4979 switch (dev->device) { 4980 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */ 4981 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */ 4982 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */ 4983 return true; 4984 } 4985 4986 return false; 4987 } 4988 4989 #define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4) 4990 4991 static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags) 4992 { 4993 int pos; 4994 u32 cap, ctrl; 4995 4996 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 4997 return -ENOTTY; 4998 4999 pos = dev->acs_cap; 5000 if (!pos) 5001 return -ENOTTY; 5002 5003 /* see pci_acs_flags_enabled() */ 5004 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5005 acs_flags &= (cap | PCI_ACS_EC); 5006 5007 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5008 5009 return pci_acs_ctrl_enabled(acs_flags, ctrl); 5010 } 5011 5012 static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags) 5013 { 5014 /* 5015 * SV, TB, and UF are not relevant to multifunction endpoints. 5016 * 5017 * Multifunction devices are only required to implement RR, CR, and DT 5018 * in their ACS capability if they support peer-to-peer transactions. 5019 * Devices matching this quirk have been verified by the vendor to not 5020 * perform peer-to-peer with other functions, allowing us to mask out 5021 * these bits as if they were unimplemented in the ACS capability. 5022 */ 5023 return pci_acs_ctrl_enabled(acs_flags, 5024 PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR | 5025 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT); 5026 } 5027 5028 static int pci_quirk_rciep_acs(struct pci_dev *dev, u16 acs_flags) 5029 { 5030 /* 5031 * Intel RCiEP's are required to allow p2p only on translated 5032 * addresses. Refer to Intel VT-d specification, r3.1, sec 3.16, 5033 * "Root-Complex Peer to Peer Considerations". 5034 */ 5035 if (pci_pcie_type(dev) != PCI_EXP_TYPE_RC_END) 5036 return -ENOTTY; 5037 5038 return pci_acs_ctrl_enabled(acs_flags, 5039 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5040 } 5041 5042 static int pci_quirk_brcm_acs(struct pci_dev *dev, u16 acs_flags) 5043 { 5044 /* 5045 * iProc PAXB Root Ports don't advertise an ACS capability, but 5046 * they do not allow peer-to-peer transactions between Root Ports. 5047 * Allow each Root Port to be in a separate IOMMU group by masking 5048 * SV/RR/CR/UF bits. 5049 */ 5050 return pci_acs_ctrl_enabled(acs_flags, 5051 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5052 } 5053 5054 static int pci_quirk_loongson_acs(struct pci_dev *dev, u16 acs_flags) 5055 { 5056 /* 5057 * Loongson PCIe Root Ports don't advertise an ACS capability, but 5058 * they do not allow peer-to-peer transactions between Root Ports. 5059 * Allow each Root Port to be in a separate IOMMU group by masking 5060 * SV/RR/CR/UF bits. 5061 */ 5062 return pci_acs_ctrl_enabled(acs_flags, 5063 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5064 } 5065 5066 /* 5067 * Wangxun 40G/25G/10G/1G NICs have no ACS capability, but on 5068 * multi-function devices, the hardware isolates the functions by 5069 * directing all peer-to-peer traffic upstream as though PCI_ACS_RR and 5070 * PCI_ACS_CR were set. 5071 * SFxxx 1G NICs(em). 5072 * RP1000/RP2000 10G NICs(sp). 5073 * FF5xxx 40G/25G/10G NICs(aml). 5074 */ 5075 static int pci_quirk_wangxun_nic_acs(struct pci_dev *dev, u16 acs_flags) 5076 { 5077 switch (dev->device) { 5078 case 0x0100 ... 0x010F: /* EM */ 5079 case 0x1001: case 0x2001: /* SP */ 5080 case 0x5010: case 0x5025: case 0x5040: /* AML */ 5081 case 0x5110: case 0x5125: case 0x5140: /* AML */ 5082 return pci_acs_ctrl_enabled(acs_flags, 5083 PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF); 5084 } 5085 5086 return false; 5087 } 5088 5089 static const struct pci_dev_acs_enabled { 5090 u16 vendor; 5091 u16 device; 5092 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags); 5093 } pci_dev_acs_enabled[] = { 5094 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs }, 5095 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs }, 5096 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs }, 5097 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs }, 5098 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs }, 5099 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs }, 5100 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs }, 5101 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs }, 5102 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs }, 5103 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs }, 5104 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs }, 5105 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs }, 5106 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs }, 5107 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs }, 5108 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs }, 5109 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs }, 5110 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs }, 5111 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs }, 5112 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs }, 5113 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs }, 5114 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs }, 5115 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs }, 5116 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs }, 5117 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs }, 5118 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs }, 5119 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs }, 5120 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs }, 5121 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs }, 5122 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs }, 5123 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs }, 5124 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs }, 5125 /* 82580 */ 5126 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs }, 5127 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs }, 5128 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs }, 5129 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs }, 5130 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs }, 5131 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs }, 5132 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs }, 5133 /* 82576 */ 5134 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs }, 5135 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs }, 5136 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs }, 5137 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs }, 5138 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs }, 5139 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs }, 5140 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs }, 5141 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs }, 5142 /* 82575 */ 5143 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs }, 5144 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs }, 5145 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs }, 5146 /* I350 */ 5147 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs }, 5148 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs }, 5149 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs }, 5150 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs }, 5151 /* 82571 (Quads omitted due to non-ACS switch) */ 5152 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs }, 5153 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs }, 5154 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs }, 5155 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs }, 5156 /* I219 */ 5157 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs }, 5158 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs }, 5159 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_rciep_acs }, 5160 /* QCOM QDF2xxx root ports */ 5161 { PCI_VENDOR_ID_QCOM, 0x0400, pci_quirk_qcom_rp_acs }, 5162 { PCI_VENDOR_ID_QCOM, 0x0401, pci_quirk_qcom_rp_acs }, 5163 /* QCOM SA8775P root port */ 5164 { PCI_VENDOR_ID_QCOM, 0x0115, pci_quirk_qcom_rp_acs }, 5165 /* QCOM Hamoa root port */ 5166 { PCI_VENDOR_ID_QCOM, 0x0111, pci_quirk_qcom_rp_acs }, 5167 /* QCOM Glymur root port */ 5168 { PCI_VENDOR_ID_QCOM, 0x0120, pci_quirk_qcom_rp_acs }, 5169 /* HXT SD4800 root ports. The ACS design is same as QCOM QDF2xxx */ 5170 { PCI_VENDOR_ID_HXT, 0x0401, pci_quirk_qcom_rp_acs }, 5171 /* Intel PCH root ports */ 5172 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs }, 5173 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs }, 5174 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */ 5175 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */ 5176 /* Cavium ThunderX */ 5177 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs }, 5178 /* Cavium multi-function devices */ 5179 { PCI_VENDOR_ID_CAVIUM, 0xA026, pci_quirk_mf_endpoint_acs }, 5180 { PCI_VENDOR_ID_CAVIUM, 0xA059, pci_quirk_mf_endpoint_acs }, 5181 { PCI_VENDOR_ID_CAVIUM, 0xA060, pci_quirk_mf_endpoint_acs }, 5182 /* APM X-Gene */ 5183 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs }, 5184 /* Ampere Computing */ 5185 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs }, 5186 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs }, 5187 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs }, 5188 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs }, 5189 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs }, 5190 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs }, 5191 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs }, 5192 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs }, 5193 /* Broadcom multi-function device */ 5194 { PCI_VENDOR_ID_BROADCOM, 0x16D7, pci_quirk_mf_endpoint_acs }, 5195 { PCI_VENDOR_ID_BROADCOM, 0x1750, pci_quirk_mf_endpoint_acs }, 5196 { PCI_VENDOR_ID_BROADCOM, 0x1751, pci_quirk_mf_endpoint_acs }, 5197 { PCI_VENDOR_ID_BROADCOM, 0x1752, pci_quirk_mf_endpoint_acs }, 5198 { PCI_VENDOR_ID_BROADCOM, 0x1760, pci_quirk_mf_endpoint_acs }, 5199 { PCI_VENDOR_ID_BROADCOM, 0x1761, pci_quirk_mf_endpoint_acs }, 5200 { PCI_VENDOR_ID_BROADCOM, 0x1762, pci_quirk_mf_endpoint_acs }, 5201 { PCI_VENDOR_ID_BROADCOM, 0x1763, pci_quirk_mf_endpoint_acs }, 5202 { PCI_VENDOR_ID_BROADCOM, 0xD714, pci_quirk_brcm_acs }, 5203 /* Loongson PCIe Root Ports */ 5204 { PCI_VENDOR_ID_LOONGSON, 0x3C09, pci_quirk_loongson_acs }, 5205 { PCI_VENDOR_ID_LOONGSON, 0x3C19, pci_quirk_loongson_acs }, 5206 { PCI_VENDOR_ID_LOONGSON, 0x3C29, pci_quirk_loongson_acs }, 5207 { PCI_VENDOR_ID_LOONGSON, 0x7A09, pci_quirk_loongson_acs }, 5208 { PCI_VENDOR_ID_LOONGSON, 0x7A19, pci_quirk_loongson_acs }, 5209 { PCI_VENDOR_ID_LOONGSON, 0x7A29, pci_quirk_loongson_acs }, 5210 { PCI_VENDOR_ID_LOONGSON, 0x7A39, pci_quirk_loongson_acs }, 5211 { PCI_VENDOR_ID_LOONGSON, 0x7A49, pci_quirk_loongson_acs }, 5212 { PCI_VENDOR_ID_LOONGSON, 0x7A59, pci_quirk_loongson_acs }, 5213 { PCI_VENDOR_ID_LOONGSON, 0x7A69, pci_quirk_loongson_acs }, 5214 /* Amazon Annapurna Labs */ 5215 { PCI_VENDOR_ID_AMAZON_ANNAPURNA_LABS, 0x0031, pci_quirk_al_acs }, 5216 /* Zhaoxin multi-function devices */ 5217 { PCI_VENDOR_ID_ZHAOXIN, 0x3038, pci_quirk_mf_endpoint_acs }, 5218 { PCI_VENDOR_ID_ZHAOXIN, 0x3104, pci_quirk_mf_endpoint_acs }, 5219 { PCI_VENDOR_ID_ZHAOXIN, 0x9083, pci_quirk_mf_endpoint_acs }, 5220 /* NXP root ports, xx=16, 12, or 08 cores */ 5221 /* LX2xx0A : without security features + CAN-FD */ 5222 { PCI_VENDOR_ID_NXP, 0x8d81, pci_quirk_nxp_rp_acs }, 5223 { PCI_VENDOR_ID_NXP, 0x8da1, pci_quirk_nxp_rp_acs }, 5224 { PCI_VENDOR_ID_NXP, 0x8d83, pci_quirk_nxp_rp_acs }, 5225 /* LX2xx0C : security features + CAN-FD */ 5226 { PCI_VENDOR_ID_NXP, 0x8d80, pci_quirk_nxp_rp_acs }, 5227 { PCI_VENDOR_ID_NXP, 0x8da0, pci_quirk_nxp_rp_acs }, 5228 { PCI_VENDOR_ID_NXP, 0x8d82, pci_quirk_nxp_rp_acs }, 5229 /* LX2xx0E : security features + CAN */ 5230 { PCI_VENDOR_ID_NXP, 0x8d90, pci_quirk_nxp_rp_acs }, 5231 { PCI_VENDOR_ID_NXP, 0x8db0, pci_quirk_nxp_rp_acs }, 5232 { PCI_VENDOR_ID_NXP, 0x8d92, pci_quirk_nxp_rp_acs }, 5233 /* LX2xx0N : without security features + CAN */ 5234 { PCI_VENDOR_ID_NXP, 0x8d91, pci_quirk_nxp_rp_acs }, 5235 { PCI_VENDOR_ID_NXP, 0x8db1, pci_quirk_nxp_rp_acs }, 5236 { PCI_VENDOR_ID_NXP, 0x8d93, pci_quirk_nxp_rp_acs }, 5237 /* LX2xx2A : without security features + CAN-FD */ 5238 { PCI_VENDOR_ID_NXP, 0x8d89, pci_quirk_nxp_rp_acs }, 5239 { PCI_VENDOR_ID_NXP, 0x8da9, pci_quirk_nxp_rp_acs }, 5240 { PCI_VENDOR_ID_NXP, 0x8d8b, pci_quirk_nxp_rp_acs }, 5241 /* LX2xx2C : security features + CAN-FD */ 5242 { PCI_VENDOR_ID_NXP, 0x8d88, pci_quirk_nxp_rp_acs }, 5243 { PCI_VENDOR_ID_NXP, 0x8da8, pci_quirk_nxp_rp_acs }, 5244 { PCI_VENDOR_ID_NXP, 0x8d8a, pci_quirk_nxp_rp_acs }, 5245 /* LX2xx2E : security features + CAN */ 5246 { PCI_VENDOR_ID_NXP, 0x8d98, pci_quirk_nxp_rp_acs }, 5247 { PCI_VENDOR_ID_NXP, 0x8db8, pci_quirk_nxp_rp_acs }, 5248 { PCI_VENDOR_ID_NXP, 0x8d9a, pci_quirk_nxp_rp_acs }, 5249 /* LX2xx2N : without security features + CAN */ 5250 { PCI_VENDOR_ID_NXP, 0x8d99, pci_quirk_nxp_rp_acs }, 5251 { PCI_VENDOR_ID_NXP, 0x8db9, pci_quirk_nxp_rp_acs }, 5252 { PCI_VENDOR_ID_NXP, 0x8d9b, pci_quirk_nxp_rp_acs }, 5253 /* Zhaoxin Root/Downstream Ports */ 5254 { PCI_VENDOR_ID_ZHAOXIN, PCI_ANY_ID, pci_quirk_zhaoxin_pcie_ports_acs }, 5255 /* Wangxun nics */ 5256 { PCI_VENDOR_ID_WANGXUN, PCI_ANY_ID, pci_quirk_wangxun_nic_acs }, 5257 { 0 } 5258 }; 5259 5260 /* 5261 * pci_dev_specific_acs_enabled - check whether device provides ACS controls 5262 * @dev: PCI device 5263 * @acs_flags: Bitmask of desired ACS controls 5264 * 5265 * Returns: 5266 * -ENOTTY: No quirk applies to this device; we can't tell whether the 5267 * device provides the desired controls 5268 * 0: Device does not provide all the desired controls 5269 * >0: Device provides all the controls in @acs_flags 5270 */ 5271 int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags) 5272 { 5273 const struct pci_dev_acs_enabled *i; 5274 int ret; 5275 5276 /* 5277 * Allow devices that do not expose standard PCIe ACS capabilities 5278 * or control to indicate their support here. Multi-function express 5279 * devices which do not allow internal peer-to-peer between functions, 5280 * but do not implement PCIe ACS may wish to return true here. 5281 */ 5282 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) { 5283 if ((i->vendor == dev->vendor || 5284 i->vendor == (u16)PCI_ANY_ID) && 5285 (i->device == dev->device || 5286 i->device == (u16)PCI_ANY_ID)) { 5287 ret = i->acs_enabled(dev, acs_flags); 5288 if (ret >= 0) 5289 return ret; 5290 } 5291 } 5292 5293 return -ENOTTY; 5294 } 5295 5296 /* Config space offset of Root Complex Base Address register */ 5297 #define INTEL_LPC_RCBA_REG 0xf0 5298 /* 31:14 RCBA address */ 5299 #define INTEL_LPC_RCBA_MASK 0xffffc000 5300 /* RCBA Enable */ 5301 #define INTEL_LPC_RCBA_ENABLE (1 << 0) 5302 5303 /* Backbone Scratch Pad Register */ 5304 #define INTEL_BSPR_REG 0x1104 5305 /* Backbone Peer Non-Posted Disable */ 5306 #define INTEL_BSPR_REG_BPNPD (1 << 8) 5307 /* Backbone Peer Posted Disable */ 5308 #define INTEL_BSPR_REG_BPPD (1 << 9) 5309 5310 /* Upstream Peer Decode Configuration Register */ 5311 #define INTEL_UPDCR_REG 0x1014 5312 /* 5:0 Peer Decode Enable bits */ 5313 #define INTEL_UPDCR_REG_MASK 0x3f 5314 5315 static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev) 5316 { 5317 u32 rcba, bspr, updcr; 5318 void __iomem *rcba_mem; 5319 5320 /* 5321 * Read the RCBA register from the LPC (D31:F0). PCH root ports 5322 * are D28:F* and therefore get probed before LPC, thus we can't 5323 * use pci_get_slot()/pci_read_config_dword() here. 5324 */ 5325 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0), 5326 INTEL_LPC_RCBA_REG, &rcba); 5327 if (!(rcba & INTEL_LPC_RCBA_ENABLE)) 5328 return -EINVAL; 5329 5330 rcba_mem = ioremap(rcba & INTEL_LPC_RCBA_MASK, 5331 PAGE_ALIGN(INTEL_UPDCR_REG)); 5332 if (!rcba_mem) 5333 return -ENOMEM; 5334 5335 /* 5336 * The BSPR can disallow peer cycles, but it's set by soft strap and 5337 * therefore read-only. If both posted and non-posted peer cycles are 5338 * disallowed, we're ok. If either are allowed, then we need to use 5339 * the UPDCR to disable peer decodes for each port. This provides the 5340 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5341 */ 5342 bspr = readl(rcba_mem + INTEL_BSPR_REG); 5343 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD; 5344 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) { 5345 updcr = readl(rcba_mem + INTEL_UPDCR_REG); 5346 if (updcr & INTEL_UPDCR_REG_MASK) { 5347 pci_info(dev, "Disabling UPDCR peer decodes\n"); 5348 updcr &= ~INTEL_UPDCR_REG_MASK; 5349 writel(updcr, rcba_mem + INTEL_UPDCR_REG); 5350 } 5351 } 5352 5353 iounmap(rcba_mem); 5354 return 0; 5355 } 5356 5357 /* Miscellaneous Port Configuration register */ 5358 #define INTEL_MPC_REG 0xd8 5359 /* MPC: Invalid Receive Bus Number Check Enable */ 5360 #define INTEL_MPC_REG_IRBNCE (1 << 26) 5361 5362 static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev) 5363 { 5364 u32 mpc; 5365 5366 /* 5367 * When enabled, the IRBNCE bit of the MPC register enables the 5368 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which 5369 * ensures that requester IDs fall within the bus number range 5370 * of the bridge. Enable if not already. 5371 */ 5372 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc); 5373 if (!(mpc & INTEL_MPC_REG_IRBNCE)) { 5374 pci_info(dev, "Enabling MPC IRBNCE\n"); 5375 mpc |= INTEL_MPC_REG_IRBNCE; 5376 pci_write_config_word(dev, INTEL_MPC_REG, mpc); 5377 } 5378 } 5379 5380 /* 5381 * Currently this quirk does the equivalent of 5382 * PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF 5383 * 5384 * TODO: This quirk also needs to do equivalent of PCI_ACS_TB, 5385 * if dev->external_facing || dev->untrusted 5386 */ 5387 static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev) 5388 { 5389 if (!pci_quirk_intel_pch_acs_match(dev)) 5390 return -ENOTTY; 5391 5392 if (pci_quirk_enable_intel_lpc_acs(dev)) { 5393 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n"); 5394 return 0; 5395 } 5396 5397 pci_quirk_enable_intel_rp_mpc_acs(dev); 5398 5399 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK; 5400 5401 pci_info(dev, "Intel PCH root port ACS workaround enabled\n"); 5402 5403 return 0; 5404 } 5405 5406 static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev) 5407 { 5408 int pos; 5409 u32 cap, ctrl; 5410 5411 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5412 return -ENOTTY; 5413 5414 pos = dev->acs_cap; 5415 if (!pos) 5416 return -ENOTTY; 5417 5418 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5419 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5420 5421 ctrl |= (cap & PCI_ACS_SV); 5422 ctrl |= (cap & PCI_ACS_RR); 5423 ctrl |= (cap & PCI_ACS_CR); 5424 ctrl |= (cap & PCI_ACS_UF); 5425 5426 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) 5427 ctrl |= (cap & PCI_ACS_TB); 5428 5429 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5430 5431 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n"); 5432 5433 return 0; 5434 } 5435 5436 static int pci_quirk_disable_intel_spt_pch_acs_redir(struct pci_dev *dev) 5437 { 5438 int pos; 5439 u32 cap, ctrl; 5440 5441 if (!pci_quirk_intel_spt_pch_acs_match(dev)) 5442 return -ENOTTY; 5443 5444 pos = dev->acs_cap; 5445 if (!pos) 5446 return -ENOTTY; 5447 5448 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap); 5449 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl); 5450 5451 ctrl &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC); 5452 5453 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl); 5454 5455 pci_info(dev, "Intel SPT PCH root port workaround: disabled ACS redirect\n"); 5456 5457 return 0; 5458 } 5459 5460 static const struct pci_dev_acs_ops { 5461 u16 vendor; 5462 u16 device; 5463 int (*enable_acs)(struct pci_dev *dev); 5464 int (*disable_acs_redir)(struct pci_dev *dev); 5465 } pci_dev_acs_ops[] = { 5466 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5467 .enable_acs = pci_quirk_enable_intel_pch_acs, 5468 }, 5469 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, 5470 .enable_acs = pci_quirk_enable_intel_spt_pch_acs, 5471 .disable_acs_redir = pci_quirk_disable_intel_spt_pch_acs_redir, 5472 }, 5473 }; 5474 5475 int pci_dev_specific_enable_acs(struct pci_dev *dev) 5476 { 5477 const struct pci_dev_acs_ops *p; 5478 int i, ret; 5479 5480 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5481 p = &pci_dev_acs_ops[i]; 5482 if ((p->vendor == dev->vendor || 5483 p->vendor == (u16)PCI_ANY_ID) && 5484 (p->device == dev->device || 5485 p->device == (u16)PCI_ANY_ID) && 5486 p->enable_acs) { 5487 ret = p->enable_acs(dev); 5488 if (ret >= 0) 5489 return ret; 5490 } 5491 } 5492 5493 return -ENOTTY; 5494 } 5495 5496 int pci_dev_specific_disable_acs_redir(struct pci_dev *dev) 5497 { 5498 const struct pci_dev_acs_ops *p; 5499 int i, ret; 5500 5501 for (i = 0; i < ARRAY_SIZE(pci_dev_acs_ops); i++) { 5502 p = &pci_dev_acs_ops[i]; 5503 if ((p->vendor == dev->vendor || 5504 p->vendor == (u16)PCI_ANY_ID) && 5505 (p->device == dev->device || 5506 p->device == (u16)PCI_ANY_ID) && 5507 p->disable_acs_redir) { 5508 ret = p->disable_acs_redir(dev); 5509 if (ret >= 0) 5510 return ret; 5511 } 5512 } 5513 5514 return -ENOTTY; 5515 } 5516 5517 /* 5518 * The PCI capabilities list for Intel DH895xCC VFs (device ID 0x0443) with 5519 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The 5520 * Next Capability pointer in the MSI Capability Structure should point to 5521 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating 5522 * the list. 5523 */ 5524 static void quirk_intel_qat_vf_cap(struct pci_dev *pdev) 5525 { 5526 int pos, i = 0, ret; 5527 u8 next_cap; 5528 u16 reg16, *cap; 5529 struct pci_cap_saved_state *state; 5530 5531 /* Bail if the hardware bug is fixed */ 5532 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP)) 5533 return; 5534 5535 /* Bail if MSI Capability Structure is not found for some reason */ 5536 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI); 5537 if (!pos) 5538 return; 5539 5540 /* 5541 * Bail if Next Capability pointer in the MSI Capability Structure 5542 * is not the expected incorrect 0x00. 5543 */ 5544 pci_read_config_byte(pdev, pos + 1, &next_cap); 5545 if (next_cap) 5546 return; 5547 5548 /* 5549 * PCIe Capability Structure is expected to be at 0x50 and should 5550 * terminate the list (Next Capability pointer is 0x00). Verify 5551 * Capability Id and Next Capability pointer is as expected. 5552 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext() 5553 * to correctly set kernel data structures which have already been 5554 * set incorrectly due to the hardware bug. 5555 */ 5556 pos = 0x50; 5557 pci_read_config_word(pdev, pos, ®16); 5558 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) { 5559 u32 status; 5560 #ifndef PCI_EXP_SAVE_REGS 5561 #define PCI_EXP_SAVE_REGS 7 5562 #endif 5563 int size = PCI_EXP_SAVE_REGS * sizeof(u16); 5564 5565 pdev->pcie_cap = pos; 5566 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16); 5567 pdev->pcie_flags_reg = reg16; 5568 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16); 5569 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD; 5570 5571 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE; 5572 ret = pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status); 5573 if ((ret != PCIBIOS_SUCCESSFUL) || (PCI_POSSIBLE_ERROR(status))) 5574 pdev->cfg_size = PCI_CFG_SPACE_SIZE; 5575 5576 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP)) 5577 return; 5578 5579 /* Save PCIe cap */ 5580 state = kzalloc(sizeof(*state) + size, GFP_KERNEL); 5581 if (!state) 5582 return; 5583 5584 state->cap.cap_nr = PCI_CAP_ID_EXP; 5585 state->cap.cap_extended = 0; 5586 state->cap.size = size; 5587 cap = (u16 *)&state->cap.data[0]; 5588 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]); 5589 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]); 5590 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]); 5591 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]); 5592 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]); 5593 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]); 5594 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]); 5595 hlist_add_head(&state->next, &pdev->saved_cap_space); 5596 } 5597 } 5598 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap); 5599 5600 /* 5601 * FLR may cause the following to devices to hang: 5602 * 5603 * AMD Starship/Matisse HD Audio Controller 0x1487 5604 * AMD Starship USB 3.0 Host Controller 0x148c 5605 * AMD Matisse USB 3.0 Host Controller 0x149c 5606 * Intel 82579LM Gigabit Ethernet Controller 0x1502 5607 * Intel 82579V Gigabit Ethernet Controller 0x1503 5608 * Mediatek MT7922 802.11ax PCI Express Wireless Network Adapter 5609 */ 5610 static void quirk_no_flr(struct pci_dev *dev) 5611 { 5612 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET; 5613 } 5614 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x1487, quirk_no_flr); 5615 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x148c, quirk_no_flr); 5616 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x149c, quirk_no_flr); 5617 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_AMD, 0x7901, quirk_no_flr); 5618 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_no_flr); 5619 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_no_flr); 5620 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_MEDIATEK, 0x0616, quirk_no_flr); 5621 5622 /* FLR may cause the SolidRun SNET DPU (rev 0x1) to hang */ 5623 static void quirk_no_flr_snet(struct pci_dev *dev) 5624 { 5625 if (dev->revision == 0x1) 5626 quirk_no_flr(dev); 5627 } 5628 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SOLIDRUN, 0x1000, quirk_no_flr_snet); 5629 5630 static void quirk_no_ext_tags(struct pci_dev *pdev) 5631 { 5632 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus); 5633 5634 if (!bridge) 5635 return; 5636 5637 bridge->no_ext_tags = 1; 5638 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n"); 5639 5640 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL); 5641 } 5642 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1004, quirk_no_ext_tags); 5643 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_3WARE, 0x1005, quirk_no_ext_tags); 5644 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags); 5645 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags); 5646 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags); 5647 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags); 5648 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags); 5649 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags); 5650 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags); 5651 5652 #ifdef CONFIG_PCI_ATS 5653 static void quirk_no_ats(struct pci_dev *pdev) 5654 { 5655 pci_info(pdev, "disabling ATS\n"); 5656 pdev->ats_cap = 0; 5657 } 5658 5659 /* 5660 * Some devices require additional driver setup to enable ATS. Don't use 5661 * ATS for those devices as ATS will be enabled before the driver has had a 5662 * chance to load and configure the device. 5663 */ 5664 static void quirk_amd_harvest_no_ats(struct pci_dev *pdev) 5665 { 5666 if (pdev->device == 0x15d8) { 5667 if (pdev->revision == 0xcf && 5668 pdev->subsystem_vendor == 0xea50 && 5669 (pdev->subsystem_device == 0xce19 || 5670 pdev->subsystem_device == 0xcc10 || 5671 pdev->subsystem_device == 0xcc08)) 5672 quirk_no_ats(pdev); 5673 } else { 5674 quirk_no_ats(pdev); 5675 } 5676 } 5677 5678 /* AMD Stoney platform GPU */ 5679 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_amd_harvest_no_ats); 5680 /* AMD Iceland dGPU */ 5681 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6900, quirk_amd_harvest_no_ats); 5682 /* AMD Navi10 dGPU */ 5683 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7310, quirk_amd_harvest_no_ats); 5684 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7312, quirk_amd_harvest_no_ats); 5685 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7318, quirk_amd_harvest_no_ats); 5686 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7319, quirk_amd_harvest_no_ats); 5687 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731a, quirk_amd_harvest_no_ats); 5688 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731b, quirk_amd_harvest_no_ats); 5689 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731e, quirk_amd_harvest_no_ats); 5690 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x731f, quirk_amd_harvest_no_ats); 5691 /* AMD Navi14 dGPU */ 5692 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7340, quirk_amd_harvest_no_ats); 5693 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7341, quirk_amd_harvest_no_ats); 5694 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x7347, quirk_amd_harvest_no_ats); 5695 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x734f, quirk_amd_harvest_no_ats); 5696 /* AMD Raven platform iGPU */ 5697 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x15d8, quirk_amd_harvest_no_ats); 5698 5699 /* 5700 * Intel IPU E2000 revisions before C0 implement incorrect endianness 5701 * in ATS Invalidate Request message body. Disable ATS for those devices. 5702 */ 5703 static void quirk_intel_e2000_no_ats(struct pci_dev *pdev) 5704 { 5705 if (pdev->revision < 0x20) 5706 quirk_no_ats(pdev); 5707 } 5708 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1451, quirk_intel_e2000_no_ats); 5709 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1452, quirk_intel_e2000_no_ats); 5710 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1453, quirk_intel_e2000_no_ats); 5711 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1454, quirk_intel_e2000_no_ats); 5712 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1455, quirk_intel_e2000_no_ats); 5713 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1457, quirk_intel_e2000_no_ats); 5714 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1459, quirk_intel_e2000_no_ats); 5715 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145a, quirk_intel_e2000_no_ats); 5716 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x145c, quirk_intel_e2000_no_ats); 5717 #endif /* CONFIG_PCI_ATS */ 5718 5719 /* Freescale PCIe doesn't support MSI in RC mode */ 5720 static void quirk_fsl_no_msi(struct pci_dev *pdev) 5721 { 5722 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT) 5723 pdev->no_msi = 1; 5724 } 5725 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi); 5726 5727 /* 5728 * Although not allowed by the spec, some multi-function devices have 5729 * dependencies of one function (consumer) on another (supplier). For the 5730 * consumer to work in D0, the supplier must also be in D0. Create a 5731 * device link from the consumer to the supplier to enforce this 5732 * dependency. Runtime PM is allowed by default on the consumer to prevent 5733 * it from permanently keeping the supplier awake. 5734 */ 5735 static void pci_create_device_link(struct pci_dev *pdev, unsigned int consumer, 5736 unsigned int supplier, unsigned int class, 5737 unsigned int class_shift) 5738 { 5739 struct pci_dev *supplier_pdev; 5740 5741 if (PCI_FUNC(pdev->devfn) != consumer) 5742 return; 5743 5744 supplier_pdev = pci_get_domain_bus_and_slot(pci_domain_nr(pdev->bus), 5745 pdev->bus->number, 5746 PCI_DEVFN(PCI_SLOT(pdev->devfn), supplier)); 5747 if (!supplier_pdev || (supplier_pdev->class >> class_shift) != class) { 5748 pci_dev_put(supplier_pdev); 5749 return; 5750 } 5751 5752 if (device_link_add(&pdev->dev, &supplier_pdev->dev, 5753 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME)) 5754 pci_info(pdev, "D0 power state depends on %s\n", 5755 pci_name(supplier_pdev)); 5756 else 5757 pci_err(pdev, "Cannot enforce power dependency on %s\n", 5758 pci_name(supplier_pdev)); 5759 5760 pm_runtime_allow(&pdev->dev); 5761 pci_dev_put(supplier_pdev); 5762 } 5763 5764 /* 5765 * Create device link for GPUs with integrated HDA controller for streaming 5766 * audio to attached displays. 5767 */ 5768 static void quirk_gpu_hda(struct pci_dev *hda) 5769 { 5770 pci_create_device_link(hda, 1, 0, PCI_BASE_CLASS_DISPLAY, 16); 5771 } 5772 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5773 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5774 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID, 5775 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5776 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5777 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda); 5778 5779 /* 5780 * Create device link for GPUs with integrated USB xHCI Host 5781 * controller to VGA. 5782 */ 5783 static void quirk_gpu_usb(struct pci_dev *usb) 5784 { 5785 pci_create_device_link(usb, 2, 0, PCI_BASE_CLASS_DISPLAY, 16); 5786 } 5787 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5788 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5789 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5790 PCI_CLASS_SERIAL_USB, 8, quirk_gpu_usb); 5791 5792 /* 5793 * Create device link for GPUs with integrated Type-C UCSI controller 5794 * to VGA. Currently there is no class code defined for UCSI device over PCI 5795 * so using UNKNOWN class for now and it will be updated when UCSI 5796 * over PCI gets a class code. 5797 */ 5798 #define PCI_CLASS_SERIAL_UNKNOWN 0x0c80 5799 static void quirk_gpu_usb_typec_ucsi(struct pci_dev *ucsi) 5800 { 5801 pci_create_device_link(ucsi, 3, 0, PCI_BASE_CLASS_DISPLAY, 16); 5802 } 5803 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5804 PCI_CLASS_SERIAL_UNKNOWN, 8, 5805 quirk_gpu_usb_typec_ucsi); 5806 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID, 5807 PCI_CLASS_SERIAL_UNKNOWN, 8, 5808 quirk_gpu_usb_typec_ucsi); 5809 5810 /* 5811 * Enable the NVIDIA GPU integrated HDA controller if the BIOS left it 5812 * disabled. https://devtalk.nvidia.com/default/topic/1024022 5813 */ 5814 static void quirk_nvidia_hda(struct pci_dev *gpu) 5815 { 5816 u8 hdr_type; 5817 u32 val; 5818 5819 /* There was no integrated HDA controller before MCP89 */ 5820 if (gpu->device < PCI_DEVICE_ID_NVIDIA_GEFORCE_320M) 5821 return; 5822 5823 /* Bit 25 at offset 0x488 enables the HDA controller */ 5824 pci_read_config_dword(gpu, 0x488, &val); 5825 if (val & BIT(25)) 5826 return; 5827 5828 pci_info(gpu, "Enabling HDA controller\n"); 5829 pci_write_config_dword(gpu, 0x488, val | BIT(25)); 5830 5831 /* The GPU becomes a multi-function device when the HDA is enabled */ 5832 pci_read_config_byte(gpu, PCI_HEADER_TYPE, &hdr_type); 5833 gpu->multifunction = FIELD_GET(PCI_HEADER_TYPE_MFD, hdr_type); 5834 } 5835 DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5836 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5837 DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, 5838 PCI_BASE_CLASS_DISPLAY, 16, quirk_nvidia_hda); 5839 5840 /* 5841 * Some IDT switches incorrectly flag an ACS Source Validation error on 5842 * completions for config read requests even though PCIe r7.0, sec 5843 * 6.12.1.1, says that completions are never affected by ACS Source 5844 * Validation. Here's the text of IDT 89H32H8G3-YC, erratum #36: 5845 * 5846 * Item #36 - Downstream port applies ACS Source Validation to Completions 5847 * Section 6.12.1.1 of the PCI Express Base Specification 3.1 states that 5848 * completions are never affected by ACS Source Validation. However, 5849 * completions received by a downstream port of the PCIe switch from a 5850 * device that has not yet captured a PCIe bus number are incorrectly 5851 * dropped by ACS Source Validation by the switch downstream port. 5852 * 5853 * The workaround suggested by IDT is to issue a config write to the 5854 * downstream device before issuing the first config read. This allows the 5855 * downstream device to capture its bus and device numbers (see PCIe r7.0, 5856 * sec 2.2.9.1), thus avoiding the ACS error on the completion. 5857 * 5858 * However, we don't know when the device is ready to accept the config 5859 * write, and the issue affects resets of the switch as well as enumeration, 5860 * so disable use of ACS SV for these devices altogether. 5861 */ 5862 void pci_disable_broken_acs_cap(struct pci_dev *pdev) 5863 { 5864 if (pdev->vendor == PCI_VENDOR_ID_IDT && 5865 (pdev->device == 0x80b5 || pdev->device == 0x8090)) { 5866 pci_info(pdev, "Disabling broken ACS SV; downstream device isolation reduced\n"); 5867 pdev->acs_capabilities &= ~PCI_ACS_SV; 5868 } 5869 } 5870 5871 /* 5872 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between 5873 * NT endpoints via the internal switch fabric. These IDs replace the 5874 * originating Requester ID TLPs which access host memory on peer NTB 5875 * ports. Therefore, all proxy IDs must be aliased to the NTB device 5876 * to permit access when the IOMMU is turned on. 5877 */ 5878 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev) 5879 { 5880 void __iomem *mmio; 5881 struct ntb_info_regs __iomem *mmio_ntb; 5882 struct ntb_ctrl_regs __iomem *mmio_ctrl; 5883 u64 partition_map; 5884 u8 partition; 5885 int pp; 5886 5887 if (pci_enable_device(pdev)) { 5888 pci_err(pdev, "Cannot enable Switchtec device\n"); 5889 return; 5890 } 5891 5892 mmio = pci_iomap(pdev, 0, 0); 5893 if (mmio == NULL) { 5894 pci_disable_device(pdev); 5895 pci_err(pdev, "Cannot iomap Switchtec device\n"); 5896 return; 5897 } 5898 5899 pci_info(pdev, "Setting Switchtec proxy ID aliases\n"); 5900 5901 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET; 5902 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET; 5903 5904 partition = ioread8(&mmio_ntb->partition_id); 5905 5906 partition_map = ioread32(&mmio_ntb->ep_map); 5907 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32; 5908 partition_map &= ~(1ULL << partition); 5909 5910 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) { 5911 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl; 5912 u32 table_sz = 0; 5913 int te; 5914 5915 if (!(partition_map & (1ULL << pp))) 5916 continue; 5917 5918 pci_dbg(pdev, "Processing partition %d\n", pp); 5919 5920 mmio_peer_ctrl = &mmio_ctrl[pp]; 5921 5922 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size); 5923 if (!table_sz) { 5924 pci_warn(pdev, "Partition %d table_sz 0\n", pp); 5925 continue; 5926 } 5927 5928 if (table_sz > 512) { 5929 pci_warn(pdev, 5930 "Invalid Switchtec partition %d table_sz %d\n", 5931 pp, table_sz); 5932 continue; 5933 } 5934 5935 for (te = 0; te < table_sz; te++) { 5936 u32 rid_entry; 5937 u8 devfn; 5938 5939 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]); 5940 devfn = (rid_entry >> 1) & 0xFF; 5941 pci_dbg(pdev, 5942 "Aliasing Partition %d Proxy ID %02x.%d\n", 5943 pp, PCI_SLOT(devfn), PCI_FUNC(devfn)); 5944 pci_add_dma_alias(pdev, devfn, 1); 5945 } 5946 } 5947 5948 pci_iounmap(pdev, mmio); 5949 pci_disable_device(pdev); 5950 } 5951 #define SWITCHTEC_QUIRK(vid) \ 5952 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_MICROSEMI, vid, \ 5953 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 5954 5955 SWITCHTEC_QUIRK(0x8531); /* PFX 24xG3 */ 5956 SWITCHTEC_QUIRK(0x8532); /* PFX 32xG3 */ 5957 SWITCHTEC_QUIRK(0x8533); /* PFX 48xG3 */ 5958 SWITCHTEC_QUIRK(0x8534); /* PFX 64xG3 */ 5959 SWITCHTEC_QUIRK(0x8535); /* PFX 80xG3 */ 5960 SWITCHTEC_QUIRK(0x8536); /* PFX 96xG3 */ 5961 SWITCHTEC_QUIRK(0x8541); /* PSX 24xG3 */ 5962 SWITCHTEC_QUIRK(0x8542); /* PSX 32xG3 */ 5963 SWITCHTEC_QUIRK(0x8543); /* PSX 48xG3 */ 5964 SWITCHTEC_QUIRK(0x8544); /* PSX 64xG3 */ 5965 SWITCHTEC_QUIRK(0x8545); /* PSX 80xG3 */ 5966 SWITCHTEC_QUIRK(0x8546); /* PSX 96xG3 */ 5967 SWITCHTEC_QUIRK(0x8551); /* PAX 24XG3 */ 5968 SWITCHTEC_QUIRK(0x8552); /* PAX 32XG3 */ 5969 SWITCHTEC_QUIRK(0x8553); /* PAX 48XG3 */ 5970 SWITCHTEC_QUIRK(0x8554); /* PAX 64XG3 */ 5971 SWITCHTEC_QUIRK(0x8555); /* PAX 80XG3 */ 5972 SWITCHTEC_QUIRK(0x8556); /* PAX 96XG3 */ 5973 SWITCHTEC_QUIRK(0x8561); /* PFXL 24XG3 */ 5974 SWITCHTEC_QUIRK(0x8562); /* PFXL 32XG3 */ 5975 SWITCHTEC_QUIRK(0x8563); /* PFXL 48XG3 */ 5976 SWITCHTEC_QUIRK(0x8564); /* PFXL 64XG3 */ 5977 SWITCHTEC_QUIRK(0x8565); /* PFXL 80XG3 */ 5978 SWITCHTEC_QUIRK(0x8566); /* PFXL 96XG3 */ 5979 SWITCHTEC_QUIRK(0x8571); /* PFXI 24XG3 */ 5980 SWITCHTEC_QUIRK(0x8572); /* PFXI 32XG3 */ 5981 SWITCHTEC_QUIRK(0x8573); /* PFXI 48XG3 */ 5982 SWITCHTEC_QUIRK(0x8574); /* PFXI 64XG3 */ 5983 SWITCHTEC_QUIRK(0x8575); /* PFXI 80XG3 */ 5984 SWITCHTEC_QUIRK(0x8576); /* PFXI 96XG3 */ 5985 SWITCHTEC_QUIRK(0x4000); /* PFX 100XG4 */ 5986 SWITCHTEC_QUIRK(0x4084); /* PFX 84XG4 */ 5987 SWITCHTEC_QUIRK(0x4068); /* PFX 68XG4 */ 5988 SWITCHTEC_QUIRK(0x4052); /* PFX 52XG4 */ 5989 SWITCHTEC_QUIRK(0x4036); /* PFX 36XG4 */ 5990 SWITCHTEC_QUIRK(0x4028); /* PFX 28XG4 */ 5991 SWITCHTEC_QUIRK(0x4100); /* PSX 100XG4 */ 5992 SWITCHTEC_QUIRK(0x4184); /* PSX 84XG4 */ 5993 SWITCHTEC_QUIRK(0x4168); /* PSX 68XG4 */ 5994 SWITCHTEC_QUIRK(0x4152); /* PSX 52XG4 */ 5995 SWITCHTEC_QUIRK(0x4136); /* PSX 36XG4 */ 5996 SWITCHTEC_QUIRK(0x4128); /* PSX 28XG4 */ 5997 SWITCHTEC_QUIRK(0x4200); /* PAX 100XG4 */ 5998 SWITCHTEC_QUIRK(0x4284); /* PAX 84XG4 */ 5999 SWITCHTEC_QUIRK(0x4268); /* PAX 68XG4 */ 6000 SWITCHTEC_QUIRK(0x4252); /* PAX 52XG4 */ 6001 SWITCHTEC_QUIRK(0x4236); /* PAX 36XG4 */ 6002 SWITCHTEC_QUIRK(0x4228); /* PAX 28XG4 */ 6003 SWITCHTEC_QUIRK(0x4352); /* PFXA 52XG4 */ 6004 SWITCHTEC_QUIRK(0x4336); /* PFXA 36XG4 */ 6005 SWITCHTEC_QUIRK(0x4328); /* PFXA 28XG4 */ 6006 SWITCHTEC_QUIRK(0x4452); /* PSXA 52XG4 */ 6007 SWITCHTEC_QUIRK(0x4436); /* PSXA 36XG4 */ 6008 SWITCHTEC_QUIRK(0x4428); /* PSXA 28XG4 */ 6009 SWITCHTEC_QUIRK(0x4552); /* PAXA 52XG4 */ 6010 SWITCHTEC_QUIRK(0x4536); /* PAXA 36XG4 */ 6011 SWITCHTEC_QUIRK(0x4528); /* PAXA 28XG4 */ 6012 SWITCHTEC_QUIRK(0x5000); /* PFX 100XG5 */ 6013 SWITCHTEC_QUIRK(0x5084); /* PFX 84XG5 */ 6014 SWITCHTEC_QUIRK(0x5068); /* PFX 68XG5 */ 6015 SWITCHTEC_QUIRK(0x5052); /* PFX 52XG5 */ 6016 SWITCHTEC_QUIRK(0x5036); /* PFX 36XG5 */ 6017 SWITCHTEC_QUIRK(0x5028); /* PFX 28XG5 */ 6018 SWITCHTEC_QUIRK(0x5100); /* PSX 100XG5 */ 6019 SWITCHTEC_QUIRK(0x5184); /* PSX 84XG5 */ 6020 SWITCHTEC_QUIRK(0x5168); /* PSX 68XG5 */ 6021 SWITCHTEC_QUIRK(0x5152); /* PSX 52XG5 */ 6022 SWITCHTEC_QUIRK(0x5136); /* PSX 36XG5 */ 6023 SWITCHTEC_QUIRK(0x5128); /* PSX 28XG5 */ 6024 SWITCHTEC_QUIRK(0x5200); /* PAX 100XG5 */ 6025 SWITCHTEC_QUIRK(0x5284); /* PAX 84XG5 */ 6026 SWITCHTEC_QUIRK(0x5268); /* PAX 68XG5 */ 6027 SWITCHTEC_QUIRK(0x5252); /* PAX 52XG5 */ 6028 SWITCHTEC_QUIRK(0x5236); /* PAX 36XG5 */ 6029 SWITCHTEC_QUIRK(0x5228); /* PAX 28XG5 */ 6030 SWITCHTEC_QUIRK(0x5300); /* PFXA 100XG5 */ 6031 SWITCHTEC_QUIRK(0x5384); /* PFXA 84XG5 */ 6032 SWITCHTEC_QUIRK(0x5368); /* PFXA 68XG5 */ 6033 SWITCHTEC_QUIRK(0x5352); /* PFXA 52XG5 */ 6034 SWITCHTEC_QUIRK(0x5336); /* PFXA 36XG5 */ 6035 SWITCHTEC_QUIRK(0x5328); /* PFXA 28XG5 */ 6036 SWITCHTEC_QUIRK(0x5400); /* PSXA 100XG5 */ 6037 SWITCHTEC_QUIRK(0x5484); /* PSXA 84XG5 */ 6038 SWITCHTEC_QUIRK(0x5468); /* PSXA 68XG5 */ 6039 SWITCHTEC_QUIRK(0x5452); /* PSXA 52XG5 */ 6040 SWITCHTEC_QUIRK(0x5436); /* PSXA 36XG5 */ 6041 SWITCHTEC_QUIRK(0x5428); /* PSXA 28XG5 */ 6042 SWITCHTEC_QUIRK(0x5500); /* PAXA 100XG5 */ 6043 SWITCHTEC_QUIRK(0x5584); /* PAXA 84XG5 */ 6044 SWITCHTEC_QUIRK(0x5568); /* PAXA 68XG5 */ 6045 SWITCHTEC_QUIRK(0x5552); /* PAXA 52XG5 */ 6046 SWITCHTEC_QUIRK(0x5536); /* PAXA 36XG5 */ 6047 SWITCHTEC_QUIRK(0x5528); /* PAXA 28XG5 */ 6048 6049 #define SWITCHTEC_PCI100X_QUIRK(vid) \ 6050 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_EFAR, vid, \ 6051 PCI_CLASS_BRIDGE_OTHER, 8, quirk_switchtec_ntb_dma_alias) 6052 SWITCHTEC_PCI100X_QUIRK(0x1001); /* PCI1001XG4 */ 6053 SWITCHTEC_PCI100X_QUIRK(0x1002); /* PCI1002XG4 */ 6054 SWITCHTEC_PCI100X_QUIRK(0x1003); /* PCI1003XG4 */ 6055 SWITCHTEC_PCI100X_QUIRK(0x1004); /* PCI1004XG4 */ 6056 SWITCHTEC_PCI100X_QUIRK(0x1005); /* PCI1005XG4 */ 6057 SWITCHTEC_PCI100X_QUIRK(0x1006); /* PCI1006XG4 */ 6058 6059 6060 /* 6061 * The PLX NTB uses devfn proxy IDs to move TLPs between NT endpoints. 6062 * These IDs are used to forward responses to the originator on the other 6063 * side of the NTB. Alias all possible IDs to the NTB to permit access when 6064 * the IOMMU is turned on. 6065 */ 6066 static void quirk_plx_ntb_dma_alias(struct pci_dev *pdev) 6067 { 6068 pci_info(pdev, "Setting PLX NTB proxy ID aliases\n"); 6069 /* PLX NTB may use all 256 devfns */ 6070 pci_add_dma_alias(pdev, 0, 256); 6071 } 6072 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b0, quirk_plx_ntb_dma_alias); 6073 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, 0x87b1, quirk_plx_ntb_dma_alias); 6074 6075 /* 6076 * On Lenovo Thinkpad P50 SKUs with a Nvidia Quadro M1000M, the BIOS does 6077 * not always reset the secondary Nvidia GPU between reboots if the system 6078 * is configured to use Hybrid Graphics mode. This results in the GPU 6079 * being left in whatever state it was in during the *previous* boot, which 6080 * causes spurious interrupts from the GPU, which in turn causes us to 6081 * disable the wrong IRQ and end up breaking the touchpad. Unsurprisingly, 6082 * this also completely breaks nouveau. 6083 * 6084 * Luckily, it seems a simple reset of the Nvidia GPU brings it back to a 6085 * clean state and fixes all these issues. 6086 * 6087 * When the machine is configured in Dedicated display mode, the issue 6088 * doesn't occur. Fortunately the GPU advertises NoReset+ when in this 6089 * mode, so we can detect that and avoid resetting it. 6090 */ 6091 static void quirk_reset_lenovo_thinkpad_p50_nvgpu(struct pci_dev *pdev) 6092 { 6093 void __iomem *map; 6094 int ret; 6095 6096 if (pdev->subsystem_vendor != PCI_VENDOR_ID_LENOVO || 6097 pdev->subsystem_device != 0x222e || 6098 !pci_reset_supported(pdev)) 6099 return; 6100 6101 if (pci_enable_device_mem(pdev)) 6102 return; 6103 6104 /* 6105 * Based on nvkm_device_ctor() in 6106 * drivers/gpu/drm/nouveau/nvkm/engine/device/base.c 6107 */ 6108 map = pci_iomap(pdev, 0, 0x23000); 6109 if (!map) { 6110 pci_err(pdev, "Can't map MMIO space\n"); 6111 goto out_disable; 6112 } 6113 6114 /* 6115 * Make sure the GPU looks like it's been POSTed before resetting 6116 * it. 6117 */ 6118 if (ioread32(map + 0x2240c) & 0x2) { 6119 pci_info(pdev, FW_BUG "GPU left initialized by EFI, resetting\n"); 6120 ret = pci_reset_bus(pdev); 6121 if (ret < 0) 6122 pci_err(pdev, "Failed to reset GPU: %d\n", ret); 6123 } 6124 6125 iounmap(map); 6126 out_disable: 6127 pci_disable_device(pdev); 6128 } 6129 DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, 0x13b1, 6130 PCI_CLASS_DISPLAY_VGA, 8, 6131 quirk_reset_lenovo_thinkpad_p50_nvgpu); 6132 6133 /* 6134 * Device [1b21:2142] 6135 * When in D0, PME# doesn't get asserted when plugging USB 3.0 device. 6136 */ 6137 static void pci_fixup_no_d0_pme(struct pci_dev *dev) 6138 { 6139 pci_info(dev, "PME# does not work under D0, disabling it\n"); 6140 dev->pme_support &= ~(PCI_PM_CAP_PME_D0 >> PCI_PM_CAP_PME_SHIFT); 6141 } 6142 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ASMEDIA, 0x2142, pci_fixup_no_d0_pme); 6143 6144 /* 6145 * Device 12d8:0x400e [OHCI] and 12d8:0x400f [EHCI] 6146 * 6147 * These devices advertise PME# support in all power states but don't 6148 * reliably assert it. 6149 * 6150 * These devices also advertise MSI, but documentation (PI7C9X440SL.pdf) 6151 * says "The MSI Function is not implemented on this device" in chapters 6152 * 7.3.27, 7.3.29-7.3.31. 6153 */ 6154 static void pci_fixup_no_msi_no_pme(struct pci_dev *dev) 6155 { 6156 #ifdef CONFIG_PCI_MSI 6157 pci_info(dev, "MSI is not implemented on this device, disabling it\n"); 6158 dev->no_msi = 1; 6159 #endif 6160 pci_info(dev, "PME# is unreliable, disabling it\n"); 6161 dev->pme_support = 0; 6162 } 6163 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400e, pci_fixup_no_msi_no_pme); 6164 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_PERICOM, 0x400f, pci_fixup_no_msi_no_pme); 6165 6166 static void apex_pci_fixup_class(struct pci_dev *pdev) 6167 { 6168 pdev->class = (PCI_CLASS_SYSTEM_OTHER << 8) | pdev->class; 6169 } 6170 DECLARE_PCI_FIXUP_CLASS_HEADER(0x1ac1, 0x089a, 6171 PCI_CLASS_NOT_DEFINED, 8, apex_pci_fixup_class); 6172 6173 /* 6174 * Pericom PI7C9X2G404/PI7C9X2G304/PI7C9X2G303 switch erratum E5 - 6175 * ACS P2P Request Redirect is not functional 6176 * 6177 * When ACS P2P Request Redirect is enabled and bandwidth is not balanced 6178 * between upstream and downstream ports, packets are queued in an internal 6179 * buffer until CPLD packet. The workaround is to use the switch in store and 6180 * forward mode. 6181 */ 6182 #define PI7C9X2Gxxx_MODE_REG 0x74 6183 #define PI7C9X2Gxxx_STORE_FORWARD_MODE BIT(0) 6184 static void pci_fixup_pericom_acs_store_forward(struct pci_dev *pdev) 6185 { 6186 struct pci_dev *upstream; 6187 u16 val; 6188 6189 /* Downstream ports only */ 6190 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM) 6191 return; 6192 6193 /* Check for ACS P2P Request Redirect use */ 6194 if (!pdev->acs_cap) 6195 return; 6196 pci_read_config_word(pdev, pdev->acs_cap + PCI_ACS_CTRL, &val); 6197 if (!(val & PCI_ACS_RR)) 6198 return; 6199 6200 upstream = pci_upstream_bridge(pdev); 6201 if (!upstream) 6202 return; 6203 6204 pci_read_config_word(upstream, PI7C9X2Gxxx_MODE_REG, &val); 6205 if (!(val & PI7C9X2Gxxx_STORE_FORWARD_MODE)) { 6206 pci_info(upstream, "Setting PI7C9X2Gxxx store-forward mode to avoid ACS erratum\n"); 6207 pci_write_config_word(upstream, PI7C9X2Gxxx_MODE_REG, val | 6208 PI7C9X2Gxxx_STORE_FORWARD_MODE); 6209 } 6210 } 6211 /* 6212 * Apply fixup on enable and on resume, in order to apply the fix up whenever 6213 * ACS configuration changes or switch mode is reset 6214 */ 6215 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2404, 6216 pci_fixup_pericom_acs_store_forward); 6217 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2404, 6218 pci_fixup_pericom_acs_store_forward); 6219 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2304, 6220 pci_fixup_pericom_acs_store_forward); 6221 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2304, 6222 pci_fixup_pericom_acs_store_forward); 6223 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0x2303, 6224 pci_fixup_pericom_acs_store_forward); 6225 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0x2303, 6226 pci_fixup_pericom_acs_store_forward); 6227 DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_PERICOM, 0xb404, 6228 pci_fixup_pericom_acs_store_forward); 6229 DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_PERICOM, 0xb404, 6230 pci_fixup_pericom_acs_store_forward); 6231 6232 static void nvidia_ion_ahci_fixup(struct pci_dev *pdev) 6233 { 6234 pdev->dev_flags |= PCI_DEV_FLAGS_HAS_MSI_MASKING; 6235 } 6236 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, 0x0ab8, nvidia_ion_ahci_fixup); 6237 6238 static void rom_bar_overlap_defect(struct pci_dev *dev) 6239 { 6240 pci_info(dev, "working around ROM BAR overlap defect\n"); 6241 dev->rom_bar_overlap = 1; 6242 } 6243 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1533, rom_bar_overlap_defect); 6244 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1536, rom_bar_overlap_defect); 6245 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1537, rom_bar_overlap_defect); 6246 DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1538, rom_bar_overlap_defect); 6247 6248 #ifdef CONFIG_PCIEASPM 6249 /* 6250 * Several Intel DG2 graphics devices advertise that they can only tolerate 6251 * 1us latency when transitioning from L1 to L0, which may prevent ASPM L1 6252 * from being enabled. But in fact these devices can tolerate unlimited 6253 * latency. Override their Device Capabilities value to allow ASPM L1 to 6254 * be enabled. 6255 */ 6256 static void aspm_l1_acceptable_latency(struct pci_dev *dev) 6257 { 6258 u32 l1_lat = FIELD_GET(PCI_EXP_DEVCAP_L1, dev->devcap); 6259 6260 if (l1_lat < 7) { 6261 dev->devcap |= FIELD_PREP(PCI_EXP_DEVCAP_L1, 7); 6262 pci_info(dev, "ASPM: overriding L1 acceptable latency from %#x to 0x7\n", 6263 l1_lat); 6264 } 6265 } 6266 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f80, aspm_l1_acceptable_latency); 6267 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f81, aspm_l1_acceptable_latency); 6268 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f82, aspm_l1_acceptable_latency); 6269 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f83, aspm_l1_acceptable_latency); 6270 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f84, aspm_l1_acceptable_latency); 6271 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f85, aspm_l1_acceptable_latency); 6272 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f86, aspm_l1_acceptable_latency); 6273 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f87, aspm_l1_acceptable_latency); 6274 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x4f88, aspm_l1_acceptable_latency); 6275 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5690, aspm_l1_acceptable_latency); 6276 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5691, aspm_l1_acceptable_latency); 6277 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5692, aspm_l1_acceptable_latency); 6278 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5693, aspm_l1_acceptable_latency); 6279 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5694, aspm_l1_acceptable_latency); 6280 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x5695, aspm_l1_acceptable_latency); 6281 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a0, aspm_l1_acceptable_latency); 6282 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a1, aspm_l1_acceptable_latency); 6283 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a2, aspm_l1_acceptable_latency); 6284 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a3, aspm_l1_acceptable_latency); 6285 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a4, aspm_l1_acceptable_latency); 6286 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a5, aspm_l1_acceptable_latency); 6287 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56a6, aspm_l1_acceptable_latency); 6288 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b0, aspm_l1_acceptable_latency); 6289 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56b1, aspm_l1_acceptable_latency); 6290 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c0, aspm_l1_acceptable_latency); 6291 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x56c1, aspm_l1_acceptable_latency); 6292 #endif 6293 6294 #ifdef CONFIG_PCIE_DPC 6295 /* 6296 * Intel Ice Lake, Tiger Lake and Alder Lake BIOS has a bug that clears 6297 * the DPC RP PIO Log Size of the integrated Thunderbolt PCIe Root 6298 * Ports. 6299 */ 6300 static void dpc_log_size(struct pci_dev *dev) 6301 { 6302 u16 dpc, val; 6303 6304 dpc = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_DPC); 6305 if (!dpc) 6306 return; 6307 6308 pci_read_config_word(dev, dpc + PCI_EXP_DPC_CAP, &val); 6309 if (!(val & PCI_EXP_DPC_CAP_RP_EXT)) 6310 return; 6311 6312 if (FIELD_GET(PCI_EXP_DPC_RP_PIO_LOG_SIZE, val) == 0) { 6313 pci_info(dev, "Overriding RP PIO Log Size to %d\n", 6314 PCIE_STD_NUM_TLP_HEADERLOG); 6315 dev->dpc_rp_log_size = PCIE_STD_NUM_TLP_HEADERLOG; 6316 } 6317 } 6318 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x461f, dpc_log_size); 6319 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x462f, dpc_log_size); 6320 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x463f, dpc_log_size); 6321 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x466e, dpc_log_size); 6322 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1d, dpc_log_size); 6323 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a1f, dpc_log_size); 6324 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a21, dpc_log_size); 6325 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x8a23, dpc_log_size); 6326 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a23, dpc_log_size); 6327 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a25, dpc_log_size); 6328 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a27, dpc_log_size); 6329 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a29, dpc_log_size); 6330 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2b, dpc_log_size); 6331 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2d, dpc_log_size); 6332 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a2f, dpc_log_size); 6333 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x9a31, dpc_log_size); 6334 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa72f, dpc_log_size); 6335 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa73f, dpc_log_size); 6336 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0xa76e, dpc_log_size); 6337 #endif 6338 6339 /* 6340 * For a PCI device with multiple downstream devices, its driver may use 6341 * a flattened device tree to describe the downstream devices. 6342 * To overlay the flattened device tree, the PCI device and all its ancestor 6343 * devices need to have device tree nodes on system base device tree. Thus, 6344 * before driver probing, it might need to add a device tree node as the final 6345 * fixup. 6346 */ 6347 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5020, of_pci_make_dev_node); 6348 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_XILINX, 0x5021, of_pci_make_dev_node); 6349 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REDHAT, 0x0005, of_pci_make_dev_node); 6350 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_EFAR, 0x9660, of_pci_make_dev_node); 6351 6352 /* 6353 * Devices known to require a longer delay before first config space access 6354 * after reset recovery or resume from D3cold: 6355 * 6356 * VideoPropulsion (aka Genroco) Torrent QN16e MPEG QAM Modulator 6357 */ 6358 static void pci_fixup_d3cold_delay_1sec(struct pci_dev *pdev) 6359 { 6360 pdev->d3cold_delay = 1000; 6361 } 6362 DECLARE_PCI_FIXUP_FINAL(0x5555, 0x0004, pci_fixup_d3cold_delay_1sec); 6363 6364 #ifdef CONFIG_PCIEAER 6365 static void pci_mask_replay_timer_timeout(struct pci_dev *pdev) 6366 { 6367 struct pci_dev *parent = pci_upstream_bridge(pdev); 6368 u32 val; 6369 6370 if (!parent || !parent->aer_cap) 6371 return; 6372 6373 pci_info(parent, "mask Replay Timer Timeout Correctable Errors due to %s hardware defect", 6374 pci_name(pdev)); 6375 6376 pci_read_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, &val); 6377 val |= PCI_ERR_COR_REP_TIMER; 6378 pci_write_config_dword(parent, parent->aer_cap + PCI_ERR_COR_MASK, val); 6379 } 6380 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9750, pci_mask_replay_timer_timeout); 6381 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_GLI, 0x9755, pci_mask_replay_timer_timeout); 6382 #endif 6383