1 /* 2 * Copyright 2018 Advanced Micro Devices, Inc. 3 * All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the 7 * "Software"), to deal in the Software without restriction, including 8 * without limitation the rights to use, copy, modify, merge, publish, 9 * distribute, sub license, and/or sell copies of the Software, and to 10 * permit persons to whom the Software is furnished to do so, subject to 11 * the following conditions: 12 * 13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, 17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR 18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE 19 * USE OR OTHER DEALINGS IN THE SOFTWARE. 20 * 21 * The above copyright notice and this permission notice (including the 22 * next paragraph) shall be included in all copies or substantial portions 23 * of the Software. 24 * 25 */ 26 #ifndef __AMDGPU_GMC_H__ 27 #define __AMDGPU_GMC_H__ 28 29 #include <linux/types.h> 30 31 #include "amdgpu_irq.h" 32 #include "amdgpu_xgmi.h" 33 #include "amdgpu_ras.h" 34 35 /* VA hole for 48bit and 57bit addresses */ 36 #define AMDGPU_GMC_HOLE_START (adev->vm_manager.root_level == AMDGPU_VM_PDB3 ?\ 37 0x0100000000000000ULL : 0x0000800000000000ULL) 38 #define AMDGPU_GMC_HOLE_END (adev->vm_manager.root_level == AMDGPU_VM_PDB3 ?\ 39 0xff00000000000000ULL : 0xffff800000000000ULL) 40 41 /* 42 * Hardware is programmed as if the hole doesn't exists with start and end 43 * address values. 44 * 45 * This mask is used to remove the upper 16bits of the VA and so come up with 46 * the linear addr value. 47 */ 48 #define AMDGPU_GMC_HOLE_MASK (adev->vm_manager.root_level == AMDGPU_VM_PDB3 ?\ 49 0x00ffffffffffffffULL : 0x0000ffffffffffffULL) 50 51 /* 52 * Ring size as power of two for the log of recent faults. 53 */ 54 #define AMDGPU_GMC_FAULT_RING_ORDER 8 55 #define AMDGPU_GMC_FAULT_RING_SIZE (1 << AMDGPU_GMC_FAULT_RING_ORDER) 56 57 /* 58 * Hash size as power of two for the log of recent faults 59 */ 60 #define AMDGPU_GMC_FAULT_HASH_ORDER 8 61 #define AMDGPU_GMC_FAULT_HASH_SIZE (1 << AMDGPU_GMC_FAULT_HASH_ORDER) 62 63 /* 64 * Number of IH timestamp ticks until a fault is considered handled 65 */ 66 #define AMDGPU_GMC_FAULT_TIMEOUT 5000ULL 67 68 /* XNACK flags */ 69 #define AMDGPU_GMC_XNACK_FLAG_CHAIN BIT(0) 70 71 struct firmware; 72 73 enum amdgpu_memory_partition { 74 UNKNOWN_MEMORY_PARTITION_MODE = 0, 75 AMDGPU_NPS1_PARTITION_MODE = 1, 76 AMDGPU_NPS2_PARTITION_MODE = 2, 77 AMDGPU_NPS3_PARTITION_MODE = 3, 78 AMDGPU_NPS4_PARTITION_MODE = 4, 79 AMDGPU_NPS6_PARTITION_MODE = 6, 80 AMDGPU_NPS8_PARTITION_MODE = 8, 81 }; 82 83 #define AMDGPU_ALL_NPS_MASK \ 84 (BIT(AMDGPU_NPS1_PARTITION_MODE) | BIT(AMDGPU_NPS2_PARTITION_MODE) | \ 85 BIT(AMDGPU_NPS3_PARTITION_MODE) | BIT(AMDGPU_NPS4_PARTITION_MODE) | \ 86 BIT(AMDGPU_NPS6_PARTITION_MODE) | BIT(AMDGPU_NPS8_PARTITION_MODE)) 87 88 #define AMDGPU_GMC_INIT_RESET_NPS BIT(0) 89 90 #define AMDGPU_MAX_MEM_RANGES 8 91 92 #define AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY 0x80 93 #define AMDGPU_GMC9_FAULT_SOURCE_DATA_READ 0x40 94 #define AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE 0x20 95 #define AMDGPU_GMC9_FAULT_SOURCE_DATA_EXE 0x10 96 97 /* 98 * GMC page fault information 99 */ 100 struct amdgpu_gmc_fault { 101 uint64_t timestamp:48; 102 uint64_t next:AMDGPU_GMC_FAULT_RING_ORDER; 103 atomic64_t key; 104 uint64_t timestamp_expiry:48; 105 }; 106 107 /* 108 * VMHUB structures, functions & helpers 109 */ 110 struct amdgpu_vmhub_funcs { 111 void (*print_l2_protection_fault_status)(struct amdgpu_device *adev, 112 uint32_t status); 113 uint32_t (*get_invalidate_req)(unsigned int vmid, uint32_t flush_type); 114 }; 115 116 struct amdgpu_vmhub { 117 uint32_t ctx0_ptb_addr_lo32; 118 uint32_t ctx0_ptb_addr_hi32; 119 uint32_t vm_inv_eng0_sem; 120 uint32_t vm_inv_eng0_req; 121 uint32_t vm_inv_eng0_ack; 122 uint32_t vm_context0_cntl; 123 uint32_t vm_l2_pro_fault_status; 124 uint32_t vm_l2_pro_fault_cntl; 125 126 /* 127 * store the register distances between two continuous context domain 128 * and invalidation engine. 129 */ 130 uint32_t ctx_distance; 131 uint32_t ctx_addr_distance; /* include LO32/HI32 */ 132 uint32_t eng_distance; 133 uint32_t eng_addr_distance; /* include LO32/HI32 */ 134 135 uint32_t vm_cntx_cntl; 136 uint32_t vm_cntx_cntl_vm_fault; 137 uint32_t vm_l2_bank_select_reserved_cid2; 138 139 uint32_t vm_contexts_disable; 140 141 bool sdma_invalidation_workaround; 142 143 const struct amdgpu_vmhub_funcs *vmhub_funcs; 144 }; 145 146 /* 147 * GPU MC structures, functions & helpers 148 */ 149 struct amdgpu_gmc_funcs { 150 /* flush the vm tlb via mmio */ 151 void (*flush_gpu_tlb)(struct amdgpu_device *adev, uint32_t vmid, 152 uint32_t vmhub, uint32_t flush_type); 153 /* flush the vm tlb via pasid */ 154 void (*flush_gpu_tlb_pasid)(struct amdgpu_device *adev, uint16_t pasid, 155 uint32_t flush_type, bool all_hub, 156 uint32_t inst); 157 /* flush the vm tlb via ring */ 158 uint64_t (*emit_flush_gpu_tlb)(struct amdgpu_ring *ring, unsigned vmid, 159 uint64_t pd_addr); 160 /* Change the VMID -> PASID mapping */ 161 void (*emit_pasid_mapping)(struct amdgpu_ring *ring, unsigned vmid, 162 unsigned pasid); 163 /* enable/disable PRT support */ 164 void (*set_prt)(struct amdgpu_device *adev, bool enable); 165 /* get the pde for a given mc addr */ 166 void (*get_vm_pde)(struct amdgpu_device *adev, int level, 167 u64 *dst, u64 *flags); 168 /* get the pte flags to use for PTEs */ 169 void (*get_vm_pte)(struct amdgpu_device *adev, 170 struct amdgpu_vm *vm, 171 struct amdgpu_bo *bo, 172 uint32_t vm_flags, 173 uint64_t *pte_flags); 174 /* override per-page pte flags */ 175 void (*override_vm_pte_flags)(struct amdgpu_device *dev, 176 struct amdgpu_vm *vm, 177 uint64_t addr, uint64_t *flags); 178 /* get the amount of memory used by the vbios for pre-OS console */ 179 unsigned int (*get_vbios_fb_size)(struct amdgpu_device *adev); 180 /* get the DCC buffer alignment */ 181 unsigned int (*get_dcc_alignment)(struct amdgpu_device *adev); 182 183 enum amdgpu_memory_partition (*query_mem_partition_mode)( 184 struct amdgpu_device *adev); 185 /* Request NPS mode */ 186 int (*request_mem_partition_mode)(struct amdgpu_device *adev, 187 int nps_mode); 188 bool (*need_reset_on_init)(struct amdgpu_device *adev); 189 }; 190 191 struct amdgpu_mem_partition_info { 192 union { 193 struct { 194 uint32_t fpfn; 195 uint32_t lpfn; 196 } range; 197 struct { 198 int node; 199 } numa; 200 }; 201 uint64_t size; 202 }; 203 204 #define INVALID_PFN -1 205 206 struct amdgpu_gmc_memrange { 207 uint64_t base_address; 208 uint64_t limit_address; 209 uint32_t flags; 210 int nid_mask; 211 }; 212 213 enum amdgpu_gart_placement { 214 AMDGPU_GART_PLACEMENT_BEST_FIT = 0, 215 AMDGPU_GART_PLACEMENT_HIGH, 216 AMDGPU_GART_PLACEMENT_LOW, 217 }; 218 219 struct amdgpu_gmc { 220 /* FB's physical address in MMIO space (for CPU to 221 * map FB). This is different compared to the agp/ 222 * gart/vram_start/end field as the later is from 223 * GPU's view and aper_base is from CPU's view. 224 */ 225 resource_size_t aper_size; 226 resource_size_t aper_base; 227 /* for some chips with <= 32MB we need to lie 228 * about vram size near mc fb location */ 229 u64 mc_vram_size; 230 u64 visible_vram_size; 231 /* AGP aperture start and end in MC address space 232 * Driver find a hole in the MC address space 233 * to place AGP by setting MC_VM_AGP_BOT/TOP registers 234 * Under VMID0, logical address == MC address. AGP 235 * aperture maps to physical bus or IOVA addressed. 236 * AGP aperture is used to simulate FB in ZFB case. 237 * AGP aperture is also used for page table in system 238 * memory (mainly for APU). 239 * 240 */ 241 u64 agp_size; 242 u64 agp_start; 243 u64 agp_end; 244 /* GART aperture start and end in MC address space 245 * Driver find a hole in the MC address space 246 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR 247 * registers 248 * Under VMID0, logical address inside GART aperture will 249 * be translated through gpuvm gart page table to access 250 * paged system memory 251 */ 252 u64 gart_size; 253 u64 gart_start; 254 u64 gart_end; 255 /* Frame buffer aperture of this GPU device. Different from 256 * fb_start (see below), this only covers the local GPU device. 257 * If driver uses FB aperture to access FB, driver get fb_start from 258 * MC_VM_FB_LOCATION_BASE (set by vbios) and calculate vram_start 259 * of this local device by adding an offset inside the XGMI hive. 260 * If driver uses GART table for VMID0 FB access, driver finds a hole in 261 * VMID0's virtual address space to place the SYSVM aperture inside 262 * which the first part is vram and the second part is gart (covering 263 * system ram). 264 */ 265 u64 vram_start; 266 u64 vram_end; 267 /* FB region , it's same as local vram region in single GPU, in XGMI 268 * configuration, this region covers all GPUs in the same hive , 269 * each GPU in the hive has the same view of this FB region . 270 * GPU0's vram starts at offset (0 * segment size) , 271 * GPU1 starts at offset (1 * segment size), etc. 272 */ 273 u64 fb_start; 274 u64 fb_end; 275 unsigned vram_width; 276 u64 real_vram_size; 277 int vram_mtrr; 278 u64 mc_mask; 279 const struct firmware *fw; /* MC firmware */ 280 uint32_t fw_version; 281 struct amdgpu_irq_src vm_fault; 282 uint32_t vram_type; 283 uint8_t vram_vendor; 284 uint32_t srbm_soft_reset; 285 bool prt_warning; 286 uint32_t sdpif_register; 287 /* apertures */ 288 u64 shared_aperture_start; 289 u64 shared_aperture_end; 290 u64 private_aperture_start; 291 u64 private_aperture_end; 292 /* protects concurrent invalidation */ 293 spinlock_t invalidate_lock; 294 bool translate_further; 295 struct kfd_vm_fault_info *vm_fault_info; 296 atomic_t vm_fault_info_updated; 297 298 struct amdgpu_gmc_fault fault_ring[AMDGPU_GMC_FAULT_RING_SIZE]; 299 struct { 300 uint64_t idx:AMDGPU_GMC_FAULT_RING_ORDER; 301 } fault_hash[AMDGPU_GMC_FAULT_HASH_SIZE]; 302 uint64_t last_fault:AMDGPU_GMC_FAULT_RING_ORDER; 303 304 bool tmz_enabled; 305 bool is_app_apu; 306 307 struct amdgpu_mem_partition_info *mem_partitions; 308 uint8_t num_mem_partitions; 309 const struct amdgpu_gmc_funcs *gmc_funcs; 310 enum amdgpu_memory_partition requested_nps_mode; 311 uint32_t supported_nps_modes; 312 uint32_t reset_flags; 313 314 struct amdgpu_xgmi xgmi; 315 struct amdgpu_irq_src ecc_irq; 316 int noretry; 317 uint32_t xnack_flags; 318 319 uint32_t vmid0_page_table_block_size; 320 uint32_t vmid0_page_table_depth; 321 struct amdgpu_bo *pdb0_bo; 322 /* CPU kmapped address of pdb0*/ 323 void *ptr_pdb0; 324 325 /* MALL size */ 326 u64 mall_size; 327 uint32_t m_half_use; 328 329 /* number of UMC instances */ 330 int num_umc; 331 /* mode2 save restore */ 332 u64 VM_L2_CNTL; 333 u64 VM_L2_CNTL2; 334 u64 VM_DUMMY_PAGE_FAULT_CNTL; 335 u64 VM_DUMMY_PAGE_FAULT_ADDR_LO32; 336 u64 VM_DUMMY_PAGE_FAULT_ADDR_HI32; 337 u64 VM_L2_PROTECTION_FAULT_CNTL; 338 u64 VM_L2_PROTECTION_FAULT_CNTL2; 339 u64 VM_L2_PROTECTION_FAULT_MM_CNTL3; 340 u64 VM_L2_PROTECTION_FAULT_MM_CNTL4; 341 u64 VM_L2_PROTECTION_FAULT_ADDR_LO32; 342 u64 VM_L2_PROTECTION_FAULT_ADDR_HI32; 343 u64 VM_DEBUG; 344 u64 VM_L2_MM_GROUP_RT_CLASSES; 345 u64 VM_L2_BANK_SELECT_RESERVED_CID; 346 u64 VM_L2_BANK_SELECT_RESERVED_CID2; 347 u64 VM_L2_CACHE_PARITY_CNTL; 348 u64 VM_L2_IH_LOG_CNTL; 349 u64 VM_CONTEXT_CNTL[16]; 350 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_LO32[16]; 351 u64 VM_CONTEXT_PAGE_TABLE_BASE_ADDR_HI32[16]; 352 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_LO32[16]; 353 u64 VM_CONTEXT_PAGE_TABLE_START_ADDR_HI32[16]; 354 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_LO32[16]; 355 u64 VM_CONTEXT_PAGE_TABLE_END_ADDR_HI32[16]; 356 u64 MC_VM_MX_L1_TLB_CNTL; 357 358 u64 noretry_flags; 359 u64 init_pte_flags; 360 361 bool flush_tlb_needs_extra_type_0; 362 bool flush_tlb_needs_extra_type_2; 363 bool flush_pasid_uses_kiq; 364 }; 365 366 #define amdgpu_gmc_emit_flush_gpu_tlb(r, vmid, addr) (r)->adev->gmc.gmc_funcs->emit_flush_gpu_tlb((r), (vmid), (addr)) 367 #define amdgpu_gmc_emit_pasid_mapping(r, vmid, pasid) (r)->adev->gmc.gmc_funcs->emit_pasid_mapping((r), (vmid), (pasid)) 368 #define amdgpu_gmc_get_vm_pde(adev, level, dst, flags) (adev)->gmc.gmc_funcs->get_vm_pde((adev), (level), (dst), (flags)) 369 #define amdgpu_gmc_get_vm_pte(adev, vm, bo, vm_flags, pte_flags) \ 370 ((adev)->gmc.gmc_funcs->get_vm_pte((adev), (vm), (bo), (vm_flags), \ 371 (pte_flags))) 372 #define amdgpu_gmc_override_vm_pte_flags(adev, vm, addr, pte_flags) \ 373 (adev)->gmc.gmc_funcs->override_vm_pte_flags \ 374 ((adev), (vm), (addr), (pte_flags)) 375 #define amdgpu_gmc_get_vbios_fb_size(adev) (adev)->gmc.gmc_funcs->get_vbios_fb_size((adev)) 376 #define amdgpu_gmc_get_dcc_alignment(adev) ({ \ 377 typeof(adev) _adev = (adev); \ 378 _adev->gmc.gmc_funcs->get_dcc_alignment(_adev); \ 379 }) 380 381 /** 382 * amdgpu_gmc_vram_full_visible - Check if full VRAM is visible through the BAR 383 * 384 * @adev: amdgpu_device pointer 385 * 386 * Returns: 387 * True if full VRAM is visible through the BAR 388 */ 389 static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc) 390 { 391 WARN_ON(gmc->real_vram_size < gmc->visible_vram_size); 392 393 return (gmc->real_vram_size == gmc->visible_vram_size); 394 } 395 396 /** 397 * amdgpu_gmc_sign_extend - sign extend the given gmc address 398 * 399 * @addr: address to extend 400 */ 401 #define amdgpu_gmc_sign_extend(addr) ((addr) >= AMDGPU_GMC_HOLE_START ?\ 402 ((addr) | AMDGPU_GMC_HOLE_END) : (addr)) 403 404 bool amdgpu_gmc_is_pdb0_enabled(struct amdgpu_device *adev); 405 int amdgpu_gmc_pdb0_alloc(struct amdgpu_device *adev); 406 void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level, 407 uint64_t *addr, uint64_t *flags); 408 int amdgpu_gmc_set_pte_pde(struct amdgpu_device *adev, void *cpu_pt_addr, 409 uint32_t gpu_page_idx, uint64_t addr, 410 uint64_t flags); 411 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo); 412 uint64_t amdgpu_gmc_agp_addr(struct ttm_buffer_object *bo); 413 void amdgpu_gmc_sysvm_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc); 414 void amdgpu_gmc_vram_location(struct amdgpu_device *adev, struct amdgpu_gmc *mc, 415 u64 base); 416 void amdgpu_gmc_gart_location(struct amdgpu_device *adev, 417 struct amdgpu_gmc *mc, 418 enum amdgpu_gart_placement gart_placement); 419 void amdgpu_gmc_agp_location(struct amdgpu_device *adev, 420 struct amdgpu_gmc *mc); 421 void amdgpu_gmc_set_agp_default(struct amdgpu_device *adev, 422 struct amdgpu_gmc *mc); 423 bool amdgpu_gmc_filter_faults(struct amdgpu_device *adev, 424 struct amdgpu_ih_ring *ih, uint64_t addr, 425 uint16_t pasid, uint64_t timestamp); 426 void amdgpu_gmc_filter_faults_remove(struct amdgpu_device *adev, uint64_t addr, 427 uint16_t pasid); 428 int amdgpu_gmc_handle_retry_fault(struct amdgpu_device *adev, 429 struct amdgpu_iv_entry *entry, 430 u64 addr, 431 u32 cam_index, 432 u32 node_id, 433 bool write_fault); 434 int amdgpu_gmc_ras_sw_init(struct amdgpu_device *adev); 435 int amdgpu_gmc_ras_late_init(struct amdgpu_device *adev); 436 void amdgpu_gmc_ras_fini(struct amdgpu_device *adev); 437 int amdgpu_gmc_allocate_vm_inv_eng(struct amdgpu_device *adev); 438 void amdgpu_gmc_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid, 439 uint32_t vmhub, uint32_t flush_type); 440 int amdgpu_gmc_flush_gpu_tlb_pasid(struct amdgpu_device *adev, uint16_t pasid, 441 uint32_t flush_type, bool all_hub, 442 uint32_t inst); 443 void amdgpu_gmc_fw_reg_write_reg_wait(struct amdgpu_device *adev, 444 uint32_t reg0, uint32_t reg1, 445 uint32_t ref, uint32_t mask, 446 uint32_t xcc_inst); 447 448 extern void amdgpu_gmc_tmz_set(struct amdgpu_device *adev); 449 extern void amdgpu_gmc_noretry_set(struct amdgpu_device *adev); 450 451 extern void 452 amdgpu_gmc_set_vm_fault_masks(struct amdgpu_device *adev, int hub_type, 453 bool enable); 454 455 void amdgpu_gmc_get_vbios_allocations(struct amdgpu_device *adev); 456 457 void amdgpu_gmc_init_pdb0(struct amdgpu_device *adev); 458 uint64_t amdgpu_gmc_vram_mc2pa(struct amdgpu_device *adev, uint64_t mc_addr); 459 uint64_t amdgpu_gmc_vram_pa(struct amdgpu_device *adev, struct amdgpu_bo *bo); 460 int amdgpu_gmc_vram_checking(struct amdgpu_device *adev); 461 int amdgpu_gmc_sysfs_init(struct amdgpu_device *adev); 462 void amdgpu_gmc_sysfs_fini(struct amdgpu_device *adev); 463 464 int amdgpu_gmc_get_nps_memranges(struct amdgpu_device *adev, 465 struct amdgpu_mem_partition_info *mem_ranges, 466 uint8_t *exp_ranges); 467 468 int amdgpu_gmc_request_memory_partition(struct amdgpu_device *adev, 469 int nps_mode); 470 void amdgpu_gmc_prepare_nps_mode_change(struct amdgpu_device *adev); 471 bool amdgpu_gmc_need_reset_on_init(struct amdgpu_device *adev); 472 enum amdgpu_memory_partition 473 amdgpu_gmc_get_vf_memory_partition(struct amdgpu_device *adev); 474 enum amdgpu_memory_partition 475 amdgpu_gmc_get_memory_partition(struct amdgpu_device *adev, u32 *supp_modes); 476 enum amdgpu_memory_partition 477 amdgpu_gmc_query_memory_partition(struct amdgpu_device *adev); 478 int amdgpu_gmc_init_mem_ranges(struct amdgpu_device *adev); 479 void amdgpu_gmc_init_sw_mem_ranges(struct amdgpu_device *adev, 480 struct amdgpu_mem_partition_info *mem_ranges); 481 #endif 482