1 /*
2 * Copyright 2016 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #include <linux/firmware.h>
25 #include <linux/pci.h>
26
27 #include <drm/drm_cache.h>
28
29 #include "amdgpu.h"
30 #include "gmc_v9_0.h"
31 #include "amdgpu_atomfirmware.h"
32 #include "amdgpu_gem.h"
33
34 #include "gc/gc_9_0_sh_mask.h"
35 #include "dce/dce_12_0_offset.h"
36 #include "dce/dce_12_0_sh_mask.h"
37 #include "vega10_enum.h"
38 #include "mmhub/mmhub_1_0_offset.h"
39 #include "athub/athub_1_0_sh_mask.h"
40 #include "athub/athub_1_0_offset.h"
41 #include "oss/osssys_4_0_offset.h"
42
43 #include "soc15.h"
44 #include "soc15d.h"
45 #include "soc15_common.h"
46 #include "umc/umc_6_0_sh_mask.h"
47
48 #include "gfxhub_v1_0.h"
49 #include "mmhub_v1_0.h"
50 #include "athub_v1_0.h"
51 #include "gfxhub_v1_1.h"
52 #include "gfxhub_v1_2.h"
53 #include "mmhub_v9_4.h"
54 #include "mmhub_v1_7.h"
55 #include "mmhub_v1_8.h"
56 #include "umc_v6_1.h"
57 #include "umc_v6_0.h"
58 #include "umc_v6_7.h"
59 #include "umc_v12_0.h"
60 #include "hdp_v4_0.h"
61 #include "mca_v3_0.h"
62
63 #include "ivsrcid/vmc/irqsrcs_vmc_1_0.h"
64
65 #include "amdgpu_ras.h"
66 #include "amdgpu_xgmi.h"
67
68 /* add these here since we already include dce12 headers and these are for DCN */
69 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION 0x055d
70 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_BASE_IDX 2
71 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH__SHIFT 0x0
72 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT__SHIFT 0x10
73 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_WIDTH_MASK 0x00003FFFL
74 #define HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION__PRI_VIEWPORT_HEIGHT_MASK 0x3FFF0000L
75 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0 0x049d
76 #define mmDCHUBBUB_SDPIF_MMIO_CNTRL_0_BASE_IDX 2
77
78 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2 0x05ea
79 #define mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2_BASE_IDX 2
80
81 static const char * const gfxhub_client_ids[] = {
82 "CB",
83 "DB",
84 "IA",
85 "WD",
86 "CPF",
87 "CPC",
88 "CPG",
89 "RLC",
90 "TCP",
91 "SQC (inst)",
92 "SQC (data)",
93 "SQG",
94 "PA",
95 };
96
97 static const char *mmhub_client_ids_raven[][2] = {
98 [0][0] = "MP1",
99 [1][0] = "MP0",
100 [2][0] = "VCN",
101 [3][0] = "VCNU",
102 [4][0] = "HDP",
103 [5][0] = "DCE",
104 [13][0] = "UTCL2",
105 [19][0] = "TLS",
106 [26][0] = "OSS",
107 [27][0] = "SDMA0",
108 [0][1] = "MP1",
109 [1][1] = "MP0",
110 [2][1] = "VCN",
111 [3][1] = "VCNU",
112 [4][1] = "HDP",
113 [5][1] = "XDP",
114 [6][1] = "DBGU0",
115 [7][1] = "DCE",
116 [8][1] = "DCEDWB0",
117 [9][1] = "DCEDWB1",
118 [26][1] = "OSS",
119 [27][1] = "SDMA0",
120 };
121
122 static const char *mmhub_client_ids_renoir[][2] = {
123 [0][0] = "MP1",
124 [1][0] = "MP0",
125 [2][0] = "HDP",
126 [4][0] = "DCEDMC",
127 [5][0] = "DCEVGA",
128 [13][0] = "UTCL2",
129 [19][0] = "TLS",
130 [26][0] = "OSS",
131 [27][0] = "SDMA0",
132 [28][0] = "VCN",
133 [29][0] = "VCNU",
134 [30][0] = "JPEG",
135 [0][1] = "MP1",
136 [1][1] = "MP0",
137 [2][1] = "HDP",
138 [3][1] = "XDP",
139 [6][1] = "DBGU0",
140 [7][1] = "DCEDMC",
141 [8][1] = "DCEVGA",
142 [9][1] = "DCEDWB",
143 [26][1] = "OSS",
144 [27][1] = "SDMA0",
145 [28][1] = "VCN",
146 [29][1] = "VCNU",
147 [30][1] = "JPEG",
148 };
149
150 static const char *mmhub_client_ids_vega10[][2] = {
151 [0][0] = "MP0",
152 [1][0] = "UVD",
153 [2][0] = "UVDU",
154 [3][0] = "HDP",
155 [13][0] = "UTCL2",
156 [14][0] = "OSS",
157 [15][0] = "SDMA1",
158 [32+0][0] = "VCE0",
159 [32+1][0] = "VCE0U",
160 [32+2][0] = "XDMA",
161 [32+3][0] = "DCE",
162 [32+4][0] = "MP1",
163 [32+14][0] = "SDMA0",
164 [0][1] = "MP0",
165 [1][1] = "UVD",
166 [2][1] = "UVDU",
167 [3][1] = "DBGU0",
168 [4][1] = "HDP",
169 [5][1] = "XDP",
170 [14][1] = "OSS",
171 [15][1] = "SDMA0",
172 [32+0][1] = "VCE0",
173 [32+1][1] = "VCE0U",
174 [32+2][1] = "XDMA",
175 [32+3][1] = "DCE",
176 [32+4][1] = "DCEDWB",
177 [32+5][1] = "MP1",
178 [32+6][1] = "DBGU1",
179 [32+14][1] = "SDMA1",
180 };
181
182 static const char *mmhub_client_ids_vega12[][2] = {
183 [0][0] = "MP0",
184 [1][0] = "VCE0",
185 [2][0] = "VCE0U",
186 [3][0] = "HDP",
187 [13][0] = "UTCL2",
188 [14][0] = "OSS",
189 [15][0] = "SDMA1",
190 [32+0][0] = "DCE",
191 [32+1][0] = "XDMA",
192 [32+2][0] = "UVD",
193 [32+3][0] = "UVDU",
194 [32+4][0] = "MP1",
195 [32+15][0] = "SDMA0",
196 [0][1] = "MP0",
197 [1][1] = "VCE0",
198 [2][1] = "VCE0U",
199 [3][1] = "DBGU0",
200 [4][1] = "HDP",
201 [5][1] = "XDP",
202 [14][1] = "OSS",
203 [15][1] = "SDMA0",
204 [32+0][1] = "DCE",
205 [32+1][1] = "DCEDWB",
206 [32+2][1] = "XDMA",
207 [32+3][1] = "UVD",
208 [32+4][1] = "UVDU",
209 [32+5][1] = "MP1",
210 [32+6][1] = "DBGU1",
211 [32+15][1] = "SDMA1",
212 };
213
214 static const char *mmhub_client_ids_vega20[][2] = {
215 [0][0] = "XDMA",
216 [1][0] = "DCE",
217 [2][0] = "VCE0",
218 [3][0] = "VCE0U",
219 [4][0] = "UVD",
220 [5][0] = "UVD1U",
221 [13][0] = "OSS",
222 [14][0] = "HDP",
223 [15][0] = "SDMA0",
224 [32+0][0] = "UVD",
225 [32+1][0] = "UVDU",
226 [32+2][0] = "MP1",
227 [32+3][0] = "MP0",
228 [32+12][0] = "UTCL2",
229 [32+14][0] = "SDMA1",
230 [0][1] = "XDMA",
231 [1][1] = "DCE",
232 [2][1] = "DCEDWB",
233 [3][1] = "VCE0",
234 [4][1] = "VCE0U",
235 [5][1] = "UVD1",
236 [6][1] = "UVD1U",
237 [7][1] = "DBGU0",
238 [8][1] = "XDP",
239 [13][1] = "OSS",
240 [14][1] = "HDP",
241 [15][1] = "SDMA0",
242 [32+0][1] = "UVD",
243 [32+1][1] = "UVDU",
244 [32+2][1] = "DBGU1",
245 [32+3][1] = "MP1",
246 [32+4][1] = "MP0",
247 [32+14][1] = "SDMA1",
248 };
249
250 static const char *mmhub_client_ids_arcturus[][2] = {
251 [0][0] = "DBGU1",
252 [1][0] = "XDP",
253 [2][0] = "MP1",
254 [14][0] = "HDP",
255 [171][0] = "JPEG",
256 [172][0] = "VCN",
257 [173][0] = "VCNU",
258 [203][0] = "JPEG1",
259 [204][0] = "VCN1",
260 [205][0] = "VCN1U",
261 [256][0] = "SDMA0",
262 [257][0] = "SDMA1",
263 [258][0] = "SDMA2",
264 [259][0] = "SDMA3",
265 [260][0] = "SDMA4",
266 [261][0] = "SDMA5",
267 [262][0] = "SDMA6",
268 [263][0] = "SDMA7",
269 [384][0] = "OSS",
270 [0][1] = "DBGU1",
271 [1][1] = "XDP",
272 [2][1] = "MP1",
273 [14][1] = "HDP",
274 [171][1] = "JPEG",
275 [172][1] = "VCN",
276 [173][1] = "VCNU",
277 [203][1] = "JPEG1",
278 [204][1] = "VCN1",
279 [205][1] = "VCN1U",
280 [256][1] = "SDMA0",
281 [257][1] = "SDMA1",
282 [258][1] = "SDMA2",
283 [259][1] = "SDMA3",
284 [260][1] = "SDMA4",
285 [261][1] = "SDMA5",
286 [262][1] = "SDMA6",
287 [263][1] = "SDMA7",
288 [384][1] = "OSS",
289 };
290
291 static const char *mmhub_client_ids_aldebaran[][2] = {
292 [2][0] = "MP1",
293 [3][0] = "MP0",
294 [32+1][0] = "DBGU_IO0",
295 [32+2][0] = "DBGU_IO2",
296 [32+4][0] = "MPIO",
297 [96+11][0] = "JPEG0",
298 [96+12][0] = "VCN0",
299 [96+13][0] = "VCNU0",
300 [128+11][0] = "JPEG1",
301 [128+12][0] = "VCN1",
302 [128+13][0] = "VCNU1",
303 [160+1][0] = "XDP",
304 [160+14][0] = "HDP",
305 [256+0][0] = "SDMA0",
306 [256+1][0] = "SDMA1",
307 [256+2][0] = "SDMA2",
308 [256+3][0] = "SDMA3",
309 [256+4][0] = "SDMA4",
310 [384+0][0] = "OSS",
311 [2][1] = "MP1",
312 [3][1] = "MP0",
313 [32+1][1] = "DBGU_IO0",
314 [32+2][1] = "DBGU_IO2",
315 [32+4][1] = "MPIO",
316 [96+11][1] = "JPEG0",
317 [96+12][1] = "VCN0",
318 [96+13][1] = "VCNU0",
319 [128+11][1] = "JPEG1",
320 [128+12][1] = "VCN1",
321 [128+13][1] = "VCNU1",
322 [160+1][1] = "XDP",
323 [160+14][1] = "HDP",
324 [256+0][1] = "SDMA0",
325 [256+1][1] = "SDMA1",
326 [256+2][1] = "SDMA2",
327 [256+3][1] = "SDMA3",
328 [256+4][1] = "SDMA4",
329 [384+0][1] = "OSS",
330 };
331
332 static const struct soc15_reg_golden golden_settings_mmhub_1_0_0[] = {
333 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmDAGB1_WRCLI2, 0x00000007, 0xfe5fe0fa),
334 SOC15_REG_GOLDEN_VALUE(MMHUB, 0, mmMMEA1_DRAM_WR_CLI2GRP_MAP0, 0x00000030, 0x55555565)
335 };
336
337 static const struct soc15_reg_golden golden_settings_athub_1_0_0[] = {
338 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL, 0x0000ff00, 0x00000800),
339 SOC15_REG_GOLDEN_VALUE(ATHUB, 0, mmRPB_ARB_CNTL2, 0x00ff00ff, 0x00080008)
340 };
341
342 static const uint32_t ecc_umc_mcumc_ctrl_addrs[] = {
343 (0x000143c0 + 0x00000000),
344 (0x000143c0 + 0x00000800),
345 (0x000143c0 + 0x00001000),
346 (0x000143c0 + 0x00001800),
347 (0x000543c0 + 0x00000000),
348 (0x000543c0 + 0x00000800),
349 (0x000543c0 + 0x00001000),
350 (0x000543c0 + 0x00001800),
351 (0x000943c0 + 0x00000000),
352 (0x000943c0 + 0x00000800),
353 (0x000943c0 + 0x00001000),
354 (0x000943c0 + 0x00001800),
355 (0x000d43c0 + 0x00000000),
356 (0x000d43c0 + 0x00000800),
357 (0x000d43c0 + 0x00001000),
358 (0x000d43c0 + 0x00001800),
359 (0x001143c0 + 0x00000000),
360 (0x001143c0 + 0x00000800),
361 (0x001143c0 + 0x00001000),
362 (0x001143c0 + 0x00001800),
363 (0x001543c0 + 0x00000000),
364 (0x001543c0 + 0x00000800),
365 (0x001543c0 + 0x00001000),
366 (0x001543c0 + 0x00001800),
367 (0x001943c0 + 0x00000000),
368 (0x001943c0 + 0x00000800),
369 (0x001943c0 + 0x00001000),
370 (0x001943c0 + 0x00001800),
371 (0x001d43c0 + 0x00000000),
372 (0x001d43c0 + 0x00000800),
373 (0x001d43c0 + 0x00001000),
374 (0x001d43c0 + 0x00001800),
375 };
376
377 static const uint32_t ecc_umc_mcumc_ctrl_mask_addrs[] = {
378 (0x000143e0 + 0x00000000),
379 (0x000143e0 + 0x00000800),
380 (0x000143e0 + 0x00001000),
381 (0x000143e0 + 0x00001800),
382 (0x000543e0 + 0x00000000),
383 (0x000543e0 + 0x00000800),
384 (0x000543e0 + 0x00001000),
385 (0x000543e0 + 0x00001800),
386 (0x000943e0 + 0x00000000),
387 (0x000943e0 + 0x00000800),
388 (0x000943e0 + 0x00001000),
389 (0x000943e0 + 0x00001800),
390 (0x000d43e0 + 0x00000000),
391 (0x000d43e0 + 0x00000800),
392 (0x000d43e0 + 0x00001000),
393 (0x000d43e0 + 0x00001800),
394 (0x001143e0 + 0x00000000),
395 (0x001143e0 + 0x00000800),
396 (0x001143e0 + 0x00001000),
397 (0x001143e0 + 0x00001800),
398 (0x001543e0 + 0x00000000),
399 (0x001543e0 + 0x00000800),
400 (0x001543e0 + 0x00001000),
401 (0x001543e0 + 0x00001800),
402 (0x001943e0 + 0x00000000),
403 (0x001943e0 + 0x00000800),
404 (0x001943e0 + 0x00001000),
405 (0x001943e0 + 0x00001800),
406 (0x001d43e0 + 0x00000000),
407 (0x001d43e0 + 0x00000800),
408 (0x001d43e0 + 0x00001000),
409 (0x001d43e0 + 0x00001800),
410 };
411
gmc_v9_0_ecc_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)412 static int gmc_v9_0_ecc_interrupt_state(struct amdgpu_device *adev,
413 struct amdgpu_irq_src *src,
414 unsigned int type,
415 enum amdgpu_interrupt_state state)
416 {
417 u32 bits, i, tmp, reg;
418
419 /* Devices newer then VEGA10/12 shall have these programming
420 * sequences performed by PSP BL
421 */
422 if (adev->asic_type >= CHIP_VEGA20)
423 return 0;
424
425 bits = 0x7f;
426
427 switch (state) {
428 case AMDGPU_IRQ_STATE_DISABLE:
429 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
430 reg = ecc_umc_mcumc_ctrl_addrs[i];
431 tmp = RREG32(reg);
432 tmp &= ~bits;
433 WREG32(reg, tmp);
434 }
435 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
436 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
437 tmp = RREG32(reg);
438 tmp &= ~bits;
439 WREG32(reg, tmp);
440 }
441 break;
442 case AMDGPU_IRQ_STATE_ENABLE:
443 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_addrs); i++) {
444 reg = ecc_umc_mcumc_ctrl_addrs[i];
445 tmp = RREG32(reg);
446 tmp |= bits;
447 WREG32(reg, tmp);
448 }
449 for (i = 0; i < ARRAY_SIZE(ecc_umc_mcumc_ctrl_mask_addrs); i++) {
450 reg = ecc_umc_mcumc_ctrl_mask_addrs[i];
451 tmp = RREG32(reg);
452 tmp |= bits;
453 WREG32(reg, tmp);
454 }
455 break;
456 default:
457 break;
458 }
459
460 return 0;
461 }
462
gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device * adev,struct amdgpu_irq_src * src,unsigned int type,enum amdgpu_interrupt_state state)463 static int gmc_v9_0_vm_fault_interrupt_state(struct amdgpu_device *adev,
464 struct amdgpu_irq_src *src,
465 unsigned int type,
466 enum amdgpu_interrupt_state state)
467 {
468 struct amdgpu_vmhub *hub;
469 u32 tmp, reg, bits, i, j;
470
471 bits = VM_CONTEXT1_CNTL__RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
472 VM_CONTEXT1_CNTL__DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
473 VM_CONTEXT1_CNTL__PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
474 VM_CONTEXT1_CNTL__VALID_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
475 VM_CONTEXT1_CNTL__READ_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
476 VM_CONTEXT1_CNTL__WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK |
477 VM_CONTEXT1_CNTL__EXECUTE_PROTECTION_FAULT_ENABLE_INTERRUPT_MASK;
478
479 switch (state) {
480 case AMDGPU_IRQ_STATE_DISABLE:
481 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
482 hub = &adev->vmhub[j];
483 for (i = 0; i < 16; i++) {
484 reg = hub->vm_context0_cntl + i;
485
486 /* This works because this interrupt is only
487 * enabled at init/resume and disabled in
488 * fini/suspend, so the overall state doesn't
489 * change over the course of suspend/resume.
490 */
491 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0)))
492 continue;
493
494 if (j >= AMDGPU_MMHUB0(0))
495 tmp = RREG32_SOC15_IP(MMHUB, reg);
496 else
497 tmp = RREG32_XCC(reg, j);
498
499 tmp &= ~bits;
500
501 if (j >= AMDGPU_MMHUB0(0))
502 WREG32_SOC15_IP(MMHUB, reg, tmp);
503 else
504 WREG32_XCC(reg, tmp, j);
505 }
506 }
507 break;
508 case AMDGPU_IRQ_STATE_ENABLE:
509 for_each_set_bit(j, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
510 hub = &adev->vmhub[j];
511 for (i = 0; i < 16; i++) {
512 reg = hub->vm_context0_cntl + i;
513
514 /* This works because this interrupt is only
515 * enabled at init/resume and disabled in
516 * fini/suspend, so the overall state doesn't
517 * change over the course of suspend/resume.
518 */
519 if (adev->in_s0ix && (j == AMDGPU_GFXHUB(0)))
520 continue;
521
522 if (j >= AMDGPU_MMHUB0(0))
523 tmp = RREG32_SOC15_IP(MMHUB, reg);
524 else
525 tmp = RREG32_XCC(reg, j);
526
527 tmp |= bits;
528
529 if (j >= AMDGPU_MMHUB0(0))
530 WREG32_SOC15_IP(MMHUB, reg, tmp);
531 else
532 WREG32_XCC(reg, tmp, j);
533 }
534 }
535 break;
536 default:
537 break;
538 }
539
540 return 0;
541 }
542
gmc_v9_0_process_interrupt(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)543 static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
544 struct amdgpu_irq_src *source,
545 struct amdgpu_iv_entry *entry)
546 {
547 bool retry_fault = !!(entry->src_data[1] &
548 AMDGPU_GMC9_FAULT_SOURCE_DATA_RETRY);
549 bool write_fault = !!(entry->src_data[1] &
550 AMDGPU_GMC9_FAULT_SOURCE_DATA_WRITE);
551 uint32_t status = 0, cid = 0, rw = 0, fed = 0;
552 struct amdgpu_task_info *task_info;
553 struct amdgpu_vmhub *hub;
554 const char *mmhub_cid;
555 const char *hub_name;
556 unsigned int vmhub;
557 u64 addr;
558 uint32_t cam_index = 0;
559 int ret, xcc_id = 0;
560 uint32_t node_id;
561
562 node_id = entry->node_id;
563
564 addr = (u64)entry->src_data[0] << 12;
565 addr |= ((u64)entry->src_data[1] & 0xf) << 44;
566
567 if (entry->client_id == SOC15_IH_CLIENTID_VMC) {
568 hub_name = "mmhub0";
569 vmhub = AMDGPU_MMHUB0(node_id / 4);
570 } else if (entry->client_id == SOC15_IH_CLIENTID_VMC1) {
571 hub_name = "mmhub1";
572 vmhub = AMDGPU_MMHUB1(0);
573 } else {
574 hub_name = "gfxhub0";
575 if (adev->gfx.funcs->ih_node_to_logical_xcc) {
576 xcc_id = adev->gfx.funcs->ih_node_to_logical_xcc(adev,
577 node_id);
578 if (xcc_id < 0)
579 xcc_id = 0;
580 }
581 vmhub = xcc_id;
582 }
583 hub = &adev->vmhub[vmhub];
584
585 if (retry_fault) {
586 cam_index = entry->src_data[2] & 0x3ff;
587
588 ret = amdgpu_gmc_handle_retry_fault(adev, entry, addr, cam_index, node_id,
589 write_fault);
590 /* Returning 1 here also prevents sending the IV to the KFD */
591 if (ret == 1)
592 return 1;
593 }
594
595 if (kgd2kfd_vmfault_fast_path(adev, entry, retry_fault))
596 return 1;
597
598 if (!printk_ratelimit())
599 return 0;
600
601 dev_err(adev->dev,
602 "[%s] %s page fault (src_id:%u ring:%u vmid:%u pasid:%u)\n", hub_name,
603 retry_fault ? "retry" : "no-retry",
604 entry->src_id, entry->ring_id, entry->vmid, entry->pasid);
605
606 task_info = amdgpu_vm_get_task_info_pasid(adev, entry->pasid);
607 if (task_info) {
608 amdgpu_vm_print_task_info(adev, task_info);
609 amdgpu_vm_put_task_info(task_info);
610 }
611
612 dev_err(adev->dev, " in page starting at address 0x%016llx from IH client 0x%x (%s)\n",
613 addr, entry->client_id,
614 soc15_ih_clientid_name[entry->client_id]);
615
616 if (amdgpu_is_multi_aid(adev))
617 dev_err(adev->dev, " cookie node_id %d fault from die %s%d%s\n",
618 node_id, node_id % 4 == 3 ? "RSV" : "AID", node_id / 4,
619 node_id % 4 == 1 ? ".XCD0" : node_id % 4 == 2 ? ".XCD1" : "");
620
621 if (amdgpu_sriov_vf(adev))
622 return 0;
623
624 /*
625 * Issue a dummy read to wait for the status register to
626 * be updated to avoid reading an incorrect value due to
627 * the new fast GRBM interface.
628 */
629 if ((entry->vmid_src == AMDGPU_GFXHUB(0)) &&
630 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)))
631 RREG32(hub->vm_l2_pro_fault_status);
632
633 status = RREG32(hub->vm_l2_pro_fault_status);
634 cid = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, CID);
635 rw = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, RW);
636 fed = REG_GET_FIELD(status, VM_L2_PROTECTION_FAULT_STATUS, FED);
637
638 /* for fed error, kfd will handle it, return directly */
639 if (fed && amdgpu_ras_is_poison_mode_supported(adev) &&
640 (amdgpu_ip_version(adev, GC_HWIP, 0) >= IP_VERSION(9, 4, 2)))
641 return 0;
642
643 /* Only print L2 fault status if the status register could be read and
644 * contains useful information
645 */
646 if (!status)
647 return 0;
648
649 if (!amdgpu_sriov_vf(adev))
650 WREG32_P(hub->vm_l2_pro_fault_cntl, 1, ~1);
651
652 amdgpu_vm_update_fault_cache(adev, entry->pasid, addr, status, vmhub);
653
654 dev_err(adev->dev,
655 "VM_L2_PROTECTION_FAULT_STATUS:0x%08X\n",
656 status);
657 if (entry->vmid_src == AMDGPU_GFXHUB(0)) {
658 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
659 cid >= ARRAY_SIZE(gfxhub_client_ids) ? "unknown" :
660 gfxhub_client_ids[cid],
661 cid);
662 } else {
663 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
664 case IP_VERSION(9, 0, 0):
665 mmhub_cid = mmhub_client_ids_vega10[cid][rw];
666 break;
667 case IP_VERSION(9, 3, 0):
668 mmhub_cid = mmhub_client_ids_vega12[cid][rw];
669 break;
670 case IP_VERSION(9, 4, 0):
671 mmhub_cid = mmhub_client_ids_vega20[cid][rw];
672 break;
673 case IP_VERSION(9, 4, 1):
674 mmhub_cid = mmhub_client_ids_arcturus[cid][rw];
675 break;
676 case IP_VERSION(9, 1, 0):
677 case IP_VERSION(9, 2, 0):
678 mmhub_cid = mmhub_client_ids_raven[cid][rw];
679 break;
680 case IP_VERSION(1, 5, 0):
681 case IP_VERSION(2, 4, 0):
682 mmhub_cid = mmhub_client_ids_renoir[cid][rw];
683 break;
684 case IP_VERSION(1, 8, 0):
685 case IP_VERSION(9, 4, 2):
686 mmhub_cid = mmhub_client_ids_aldebaran[cid][rw];
687 break;
688 default:
689 mmhub_cid = NULL;
690 break;
691 }
692 dev_err(adev->dev, "\t Faulty UTCL2 client ID: %s (0x%x)\n",
693 mmhub_cid ? mmhub_cid : "unknown", cid);
694 }
695 dev_err(adev->dev, "\t MORE_FAULTS: 0x%lx\n",
696 REG_GET_FIELD(status,
697 VM_L2_PROTECTION_FAULT_STATUS, MORE_FAULTS));
698 dev_err(adev->dev, "\t WALKER_ERROR: 0x%lx\n",
699 REG_GET_FIELD(status,
700 VM_L2_PROTECTION_FAULT_STATUS, WALKER_ERROR));
701 dev_err(adev->dev, "\t PERMISSION_FAULTS: 0x%lx\n",
702 REG_GET_FIELD(status,
703 VM_L2_PROTECTION_FAULT_STATUS, PERMISSION_FAULTS));
704 dev_err(adev->dev, "\t MAPPING_ERROR: 0x%lx\n",
705 REG_GET_FIELD(status,
706 VM_L2_PROTECTION_FAULT_STATUS, MAPPING_ERROR));
707 dev_err(adev->dev, "\t RW: 0x%x\n", rw);
708 return 0;
709 }
710
711 static const struct amdgpu_irq_src_funcs gmc_v9_0_irq_funcs = {
712 .set = gmc_v9_0_vm_fault_interrupt_state,
713 .process = gmc_v9_0_process_interrupt,
714 };
715
716
717 static const struct amdgpu_irq_src_funcs gmc_v9_0_ecc_funcs = {
718 .set = gmc_v9_0_ecc_interrupt_state,
719 .process = amdgpu_umc_process_ecc_irq,
720 };
721
gmc_v9_0_set_irq_funcs(struct amdgpu_device * adev)722 static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
723 {
724 adev->gmc.vm_fault.num_types = 1;
725 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
726
727 if (!amdgpu_sriov_vf(adev) &&
728 !adev->gmc.xgmi.connected_to_cpu &&
729 !adev->gmc.is_app_apu) {
730 adev->gmc.ecc_irq.num_types = 1;
731 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs;
732 }
733 }
734
gmc_v9_0_get_invalidate_req(unsigned int vmid,uint32_t flush_type)735 static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid,
736 uint32_t flush_type)
737 {
738 u32 req = 0;
739
740 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
741 PER_VMID_INVALIDATE_REQ, 1 << vmid);
742 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, flush_type);
743 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
744 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);
745 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE1, 1);
746 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE2, 1);
747 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L1_PTES, 1);
748 req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
749 CLEAR_PROTECTION_FAULT_STATUS_ADDR, 0);
750
751 return req;
752 }
753
754 /**
755 * gmc_v9_0_use_invalidate_semaphore - judge whether to use semaphore
756 *
757 * @adev: amdgpu_device pointer
758 * @vmhub: vmhub type
759 *
760 */
gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device * adev,uint32_t vmhub)761 static bool gmc_v9_0_use_invalidate_semaphore(struct amdgpu_device *adev,
762 uint32_t vmhub)
763 {
764 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||
765 amdgpu_is_multi_aid(adev))
766 return false;
767
768 return ((vmhub == AMDGPU_MMHUB0(0) ||
769 vmhub == AMDGPU_MMHUB1(0)) &&
770 (!amdgpu_sriov_vf(adev)) &&
771 (!(!(adev->apu_flags & AMD_APU_IS_RAVEN2) &&
772 (adev->apu_flags & AMD_APU_IS_PICASSO))));
773 }
774
gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device * adev,uint8_t vmid,uint16_t * p_pasid)775 static bool gmc_v9_0_get_atc_vmid_pasid_mapping_info(struct amdgpu_device *adev,
776 uint8_t vmid, uint16_t *p_pasid)
777 {
778 uint32_t value;
779
780 value = RREG32(SOC15_REG_OFFSET(ATHUB, 0, mmATC_VMID0_PASID_MAPPING)
781 + vmid);
782 *p_pasid = value & ATC_VMID0_PASID_MAPPING__PASID_MASK;
783
784 return !!(value & ATC_VMID0_PASID_MAPPING__VALID_MASK);
785 }
786
787 /*
788 * GART
789 * VMID 0 is the physical GPU addresses as used by the kernel.
790 * VMIDs 1-15 are used for userspace clients and are handled
791 * by the amdgpu vm/hsa code.
792 */
793
794 /**
795 * gmc_v9_0_flush_gpu_tlb - tlb flush with certain type
796 *
797 * @adev: amdgpu_device pointer
798 * @vmid: vm instance to flush
799 * @vmhub: which hub to flush
800 * @flush_type: the flush type
801 *
802 * Flush the TLB for the requested page table using certain type.
803 */
gmc_v9_0_flush_gpu_tlb(struct amdgpu_device * adev,uint32_t vmid,uint32_t vmhub,uint32_t flush_type)804 static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
805 uint32_t vmhub, uint32_t flush_type)
806 {
807 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(adev, vmhub);
808 u32 j, inv_req, tmp, sem, req, ack, inst;
809 const unsigned int eng = 17;
810 struct amdgpu_vmhub *hub;
811
812 BUG_ON(vmhub >= AMDGPU_MAX_VMHUBS);
813
814 hub = &adev->vmhub[vmhub];
815 inv_req = gmc_v9_0_get_invalidate_req(vmid, flush_type);
816 sem = hub->vm_inv_eng0_sem + hub->eng_distance * eng;
817 req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
818 ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
819
820 if (vmhub >= AMDGPU_MMHUB0(0))
821 inst = 0;
822 else
823 inst = vmhub;
824
825 /* This is necessary for SRIOV as well as for GFXOFF to function
826 * properly under bare metal
827 */
828 if (adev->gfx.kiq[inst].ring.sched.ready &&
829 (amdgpu_sriov_runtime(adev) || !amdgpu_sriov_vf(adev))) {
830 uint32_t req = hub->vm_inv_eng0_req + hub->eng_distance * eng;
831 uint32_t ack = hub->vm_inv_eng0_ack + hub->eng_distance * eng;
832
833 amdgpu_gmc_fw_reg_write_reg_wait(adev, req, ack, inv_req,
834 1 << vmid, inst);
835 return;
836 }
837
838 /* This path is needed before KIQ/MES/GFXOFF are set up */
839 spin_lock(&adev->gmc.invalidate_lock);
840
841 /*
842 * It may lose gpuvm invalidate acknowldege state across power-gating
843 * off cycle, add semaphore acquire before invalidation and semaphore
844 * release after invalidation to avoid entering power gated state
845 * to WA the Issue
846 */
847
848 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
849 if (use_semaphore) {
850 for (j = 0; j < adev->usec_timeout; j++) {
851 /* a read return value of 1 means semaphore acquire */
852 if (vmhub >= AMDGPU_MMHUB0(0))
853 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, GET_INST(GC, inst));
854 else
855 tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, GET_INST(GC, inst));
856 if (tmp & 0x1)
857 break;
858 udelay(1);
859 }
860
861 if (j >= adev->usec_timeout)
862 DRM_ERROR("Timeout waiting for sem acquire in VM flush!\n");
863 }
864
865 if (vmhub >= AMDGPU_MMHUB0(0))
866 WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, GET_INST(GC, inst));
867 else
868 WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, GET_INST(GC, inst));
869
870 /*
871 * Issue a dummy read to wait for the ACK register to
872 * be cleared to avoid a false ACK due to the new fast
873 * GRBM interface.
874 */
875 if ((vmhub == AMDGPU_GFXHUB(0)) &&
876 (amdgpu_ip_version(adev, GC_HWIP, 0) < IP_VERSION(9, 4, 2)))
877 RREG32_NO_KIQ(req);
878
879 for (j = 0; j < adev->usec_timeout; j++) {
880 if (vmhub >= AMDGPU_MMHUB0(0))
881 tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, GET_INST(GC, inst));
882 else
883 tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, GET_INST(GC, inst));
884 if (tmp & (1 << vmid))
885 break;
886 udelay(1);
887 }
888
889 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
890 if (use_semaphore) {
891 /*
892 * add semaphore release after invalidation,
893 * write with 0 means semaphore release
894 */
895 if (vmhub >= AMDGPU_MMHUB0(0))
896 WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, GET_INST(GC, inst));
897 else
898 WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, GET_INST(GC, inst));
899 }
900
901 spin_unlock(&adev->gmc.invalidate_lock);
902
903 if (j < adev->usec_timeout)
904 return;
905
906 DRM_ERROR("Timeout waiting for VM flush ACK!\n");
907 }
908
909 /**
910 * gmc_v9_0_flush_gpu_tlb_pasid - tlb flush via pasid
911 *
912 * @adev: amdgpu_device pointer
913 * @pasid: pasid to be flush
914 * @flush_type: the flush type
915 * @all_hub: flush all hubs
916 * @inst: is used to select which instance of KIQ to use for the invalidation
917 *
918 * Flush the TLB for the requested pasid.
919 */
gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device * adev,uint16_t pasid,uint32_t flush_type,bool all_hub,uint32_t inst)920 static void gmc_v9_0_flush_gpu_tlb_pasid(struct amdgpu_device *adev,
921 uint16_t pasid, uint32_t flush_type,
922 bool all_hub, uint32_t inst)
923 {
924 uint16_t queried;
925 int i, vmid;
926
927 for (vmid = 1; vmid < 16; vmid++) {
928 bool valid;
929
930 valid = gmc_v9_0_get_atc_vmid_pasid_mapping_info(adev, vmid,
931 &queried);
932 if (!valid || queried != pasid)
933 continue;
934
935 if (all_hub) {
936 for_each_set_bit(i, adev->vmhubs_mask,
937 AMDGPU_MAX_VMHUBS)
938 gmc_v9_0_flush_gpu_tlb(adev, vmid, i,
939 flush_type);
940 } else {
941 gmc_v9_0_flush_gpu_tlb(adev, vmid,
942 AMDGPU_GFXHUB(0),
943 flush_type);
944 }
945 }
946 }
947
gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)948 static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
949 unsigned int vmid, uint64_t pd_addr)
950 {
951 bool use_semaphore = gmc_v9_0_use_invalidate_semaphore(ring->adev, ring->vm_hub);
952 struct amdgpu_device *adev = ring->adev;
953 struct amdgpu_vmhub *hub = &adev->vmhub[ring->vm_hub];
954 uint32_t req = gmc_v9_0_get_invalidate_req(vmid, 0);
955 unsigned int eng = ring->vm_inv_eng;
956
957 /*
958 * It may lose gpuvm invalidate acknowldege state across power-gating
959 * off cycle, add semaphore acquire before invalidation and semaphore
960 * release after invalidation to avoid entering power gated state
961 * to WA the Issue
962 */
963
964 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
965 if (use_semaphore)
966 /* a read return value of 1 means semaphore acuqire */
967 amdgpu_ring_emit_reg_wait(ring,
968 hub->vm_inv_eng0_sem +
969 hub->eng_distance * eng, 0x1, 0x1);
970
971 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 +
972 (hub->ctx_addr_distance * vmid),
973 lower_32_bits(pd_addr));
974
975 amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_hi32 +
976 (hub->ctx_addr_distance * vmid),
977 upper_32_bits(pd_addr));
978
979 amdgpu_ring_emit_reg_write_reg_wait(ring, hub->vm_inv_eng0_req +
980 hub->eng_distance * eng,
981 hub->vm_inv_eng0_ack +
982 hub->eng_distance * eng,
983 req, 1 << vmid);
984
985 /* TODO: It needs to continue working on debugging with semaphore for GFXHUB as well. */
986 if (use_semaphore)
987 /*
988 * add semaphore release after invalidation,
989 * write with 0 means semaphore release
990 */
991 amdgpu_ring_emit_wreg(ring, hub->vm_inv_eng0_sem +
992 hub->eng_distance * eng, 0);
993
994 return pd_addr;
995 }
996
gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring * ring,unsigned int vmid,unsigned int pasid)997 static void gmc_v9_0_emit_pasid_mapping(struct amdgpu_ring *ring, unsigned int vmid,
998 unsigned int pasid)
999 {
1000 struct amdgpu_device *adev = ring->adev;
1001 uint32_t reg;
1002
1003 /* Do nothing because there's no lut register for mmhub1. */
1004 if (ring->vm_hub == AMDGPU_MMHUB1(0))
1005 return;
1006
1007 if (ring->vm_hub == AMDGPU_GFXHUB(0))
1008 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT) + vmid;
1009 else
1010 reg = SOC15_REG_OFFSET(OSSSYS, 0, mmIH_VMID_0_LUT_MM) + vmid;
1011
1012 amdgpu_ring_emit_wreg(ring, reg, pasid);
1013 }
1014
1015 /*
1016 * PTE format on VEGA 10:
1017 * 63:59 reserved
1018 * 58:57 mtype
1019 * 56 F
1020 * 55 L
1021 * 54 P
1022 * 53 SW
1023 * 52 T
1024 * 50:48 reserved
1025 * 47:12 4k physical page base address
1026 * 11:7 fragment
1027 * 6 write
1028 * 5 read
1029 * 4 exe
1030 * 3 Z
1031 * 2 snooped
1032 * 1 system
1033 * 0 valid
1034 *
1035 * PDE format on VEGA 10:
1036 * 63:59 block fragment size
1037 * 58:55 reserved
1038 * 54 P
1039 * 53:48 reserved
1040 * 47:6 physical base address of PD or PTE
1041 * 5:3 reserved
1042 * 2 C
1043 * 1 system
1044 * 0 valid
1045 */
1046
gmc_v9_0_get_vm_pde(struct amdgpu_device * adev,int level,uint64_t * addr,uint64_t * flags)1047 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
1048 uint64_t *addr, uint64_t *flags)
1049 {
1050 if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
1051 *addr = amdgpu_gmc_vram_mc2pa(adev, *addr);
1052 BUG_ON(*addr & 0xFFFF00000000003FULL);
1053
1054 if (!adev->gmc.translate_further)
1055 return;
1056
1057 if (level == AMDGPU_VM_PDB1) {
1058 /* Set the block fragment size */
1059 if (!(*flags & AMDGPU_PDE_PTE))
1060 *flags |= AMDGPU_PDE_BFS(0x9);
1061
1062 } else if (level == AMDGPU_VM_PDB0) {
1063 if (*flags & AMDGPU_PDE_PTE) {
1064 *flags &= ~AMDGPU_PDE_PTE;
1065 if (!(*flags & AMDGPU_PTE_VALID))
1066 *addr |= 1 << PAGE_SHIFT;
1067 } else {
1068 *flags |= AMDGPU_PTE_TF;
1069 }
1070 }
1071 }
1072
gmc_v9_0_get_coherence_flags(struct amdgpu_device * adev,struct amdgpu_vm * vm,struct amdgpu_bo * bo,uint32_t vm_flags,uint64_t * flags)1073 static void gmc_v9_0_get_coherence_flags(struct amdgpu_device *adev,
1074 struct amdgpu_vm *vm,
1075 struct amdgpu_bo *bo,
1076 uint32_t vm_flags,
1077 uint64_t *flags)
1078 {
1079 struct amdgpu_device *bo_adev = amdgpu_ttm_adev(bo->tbo.bdev);
1080 bool is_vram = bo->tbo.resource &&
1081 bo->tbo.resource->mem_type == TTM_PL_VRAM;
1082 bool coherent = bo->flags & (AMDGPU_GEM_CREATE_COHERENT |
1083 AMDGPU_GEM_CREATE_EXT_COHERENT);
1084 bool ext_coherent = bo->flags & AMDGPU_GEM_CREATE_EXT_COHERENT;
1085 bool uncached = bo->flags & AMDGPU_GEM_CREATE_UNCACHED;
1086 unsigned int mtype_local, mtype;
1087 uint32_t gc_ip_version = amdgpu_ip_version(adev, GC_HWIP, 0);
1088 bool snoop = false;
1089 bool is_local;
1090
1091 dma_resv_assert_held(bo->tbo.base.resv);
1092
1093 switch (gc_ip_version) {
1094 case IP_VERSION(9, 4, 1):
1095 case IP_VERSION(9, 4, 2):
1096 if (is_vram) {
1097 if (bo_adev == adev) {
1098 if (uncached)
1099 mtype = MTYPE_UC;
1100 else if (coherent)
1101 mtype = MTYPE_CC;
1102 else
1103 mtype = MTYPE_RW;
1104 /* FIXME: is this still needed? Or does
1105 * amdgpu_ttm_tt_pde_flags already handle this?
1106 */
1107 if (gc_ip_version == IP_VERSION(9, 4, 2) &&
1108 adev->gmc.xgmi.connected_to_cpu)
1109 snoop = true;
1110 } else {
1111 if (uncached || coherent)
1112 mtype = MTYPE_UC;
1113 else
1114 mtype = MTYPE_NC;
1115 if (amdgpu_xgmi_same_hive(adev, bo_adev))
1116 snoop = true;
1117 }
1118 } else {
1119 if (uncached || coherent)
1120 mtype = MTYPE_UC;
1121 else
1122 mtype = MTYPE_NC;
1123 /* FIXME: is this still needed? Or does
1124 * amdgpu_ttm_tt_pde_flags already handle this?
1125 */
1126 snoop = true;
1127 }
1128 break;
1129 case IP_VERSION(9, 4, 3):
1130 case IP_VERSION(9, 4, 4):
1131 case IP_VERSION(9, 5, 0):
1132 /* Only local VRAM BOs or system memory on non-NUMA APUs
1133 * can be assumed to be local in their entirety. Choose
1134 * MTYPE_NC as safe fallback for all system memory BOs on
1135 * NUMA systems. Their MTYPE can be overridden per-page in
1136 * gmc_v9_0_override_vm_pte_flags.
1137 */
1138 mtype_local = MTYPE_RW;
1139 if (amdgpu_mtype_local == 1) {
1140 drm_info_once(adev_to_drm(adev), "Using MTYPE_NC for local memory\n");
1141 mtype_local = MTYPE_NC;
1142 } else if (amdgpu_mtype_local == 2) {
1143 drm_info_once(adev_to_drm(adev), "Using MTYPE_CC for local memory\n");
1144 mtype_local = MTYPE_CC;
1145 } else {
1146 drm_info_once(adev_to_drm(adev), "Using MTYPE_RW for local memory\n");
1147 }
1148 is_local = (!is_vram && (adev->flags & AMD_IS_APU) &&
1149 num_possible_nodes() <= 1) ||
1150 (is_vram && adev == bo_adev &&
1151 KFD_XCP_MEM_ID(adev, bo->xcp_id) == vm->mem_id);
1152 snoop = true;
1153 if (uncached) {
1154 mtype = MTYPE_UC;
1155 } else if (ext_coherent) {
1156 mtype = is_local ? MTYPE_CC : MTYPE_UC;
1157 } else if (adev->flags & AMD_IS_APU) {
1158 mtype = is_local ? mtype_local : MTYPE_NC;
1159 } else {
1160 /* dGPU */
1161 if (is_local)
1162 mtype = mtype_local;
1163 else if (gc_ip_version < IP_VERSION(9, 5, 0) && !is_vram)
1164 mtype = MTYPE_UC;
1165 else
1166 mtype = MTYPE_NC;
1167 }
1168
1169 break;
1170 default:
1171 if (uncached || coherent)
1172 mtype = MTYPE_UC;
1173 else
1174 mtype = MTYPE_NC;
1175
1176 /* FIXME: is this still needed? Or does
1177 * amdgpu_ttm_tt_pde_flags already handle this?
1178 */
1179 if (!is_vram)
1180 snoop = true;
1181 }
1182
1183 if (mtype != MTYPE_NC)
1184 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype);
1185
1186 *flags |= snoop ? AMDGPU_PTE_SNOOPED : 0;
1187 }
1188
gmc_v9_0_get_vm_pte(struct amdgpu_device * adev,struct amdgpu_vm * vm,struct amdgpu_bo * bo,uint32_t vm_flags,uint64_t * flags)1189 static void gmc_v9_0_get_vm_pte(struct amdgpu_device *adev,
1190 struct amdgpu_vm *vm,
1191 struct amdgpu_bo *bo,
1192 uint32_t vm_flags,
1193 uint64_t *flags)
1194 {
1195 if (vm_flags & AMDGPU_VM_PAGE_EXECUTABLE)
1196 *flags |= AMDGPU_PTE_EXECUTABLE;
1197 else
1198 *flags &= ~AMDGPU_PTE_EXECUTABLE;
1199
1200 switch (vm_flags & AMDGPU_VM_MTYPE_MASK) {
1201 case AMDGPU_VM_MTYPE_DEFAULT:
1202 case AMDGPU_VM_MTYPE_NC:
1203 default:
1204 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_NC);
1205 break;
1206 case AMDGPU_VM_MTYPE_WC:
1207 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_WC);
1208 break;
1209 case AMDGPU_VM_MTYPE_RW:
1210 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_RW);
1211 break;
1212 case AMDGPU_VM_MTYPE_CC:
1213 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC);
1214 break;
1215 case AMDGPU_VM_MTYPE_UC:
1216 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_UC);
1217 break;
1218 }
1219
1220 if (vm_flags & AMDGPU_VM_PAGE_PRT) {
1221 *flags |= AMDGPU_PTE_PRT;
1222 *flags &= ~AMDGPU_PTE_VALID;
1223 }
1224
1225 if ((*flags & AMDGPU_PTE_VALID) && bo)
1226 gmc_v9_0_get_coherence_flags(adev, vm, bo, vm_flags, flags);
1227 }
1228
gmc_v9_0_override_vm_pte_flags(struct amdgpu_device * adev,struct amdgpu_vm * vm,uint64_t addr,uint64_t * flags)1229 static void gmc_v9_0_override_vm_pte_flags(struct amdgpu_device *adev,
1230 struct amdgpu_vm *vm,
1231 uint64_t addr, uint64_t *flags)
1232 {
1233 int local_node, nid;
1234
1235 /* Only GFX 9.4.3 APUs associate GPUs with NUMA nodes. Local system
1236 * memory can use more efficient MTYPEs.
1237 */
1238 if (!(adev->flags & AMD_IS_APU) ||
1239 amdgpu_ip_version(adev, GC_HWIP, 0) != IP_VERSION(9, 4, 3))
1240 return;
1241
1242 /* Only direct-mapped memory allows us to determine the NUMA node from
1243 * the DMA address.
1244 */
1245 if (!adev->ram_is_direct_mapped) {
1246 dev_dbg_ratelimited(adev->dev, "RAM is not direct mapped\n");
1247 return;
1248 }
1249
1250 /* MTYPE_NC is the same default and can be overridden.
1251 * MTYPE_UC will be present if the memory is extended-coherent
1252 * and can also be overridden.
1253 */
1254 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) !=
1255 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC) &&
1256 (*flags & AMDGPU_PTE_MTYPE_VG10_MASK) !=
1257 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC)) {
1258 dev_dbg_ratelimited(adev->dev, "MTYPE is not NC or UC\n");
1259 return;
1260 }
1261
1262 /* FIXME: Only supported on native mode for now. For carve-out, the
1263 * NUMA affinity of the GPU/VM needs to come from the PCI info because
1264 * memory partitions are not associated with different NUMA nodes.
1265 */
1266 if (adev->gmc.is_app_apu && vm->mem_id >= 0) {
1267 local_node = adev->gmc.mem_partitions[vm->mem_id].numa.node;
1268 } else {
1269 dev_dbg_ratelimited(adev->dev, "Only native mode APU is supported.\n");
1270 return;
1271 }
1272
1273 /* Only handle real RAM. Mappings of PCIe resources don't have struct
1274 * page or NUMA nodes.
1275 */
1276 if (!page_is_ram(addr >> PAGE_SHIFT)) {
1277 dev_dbg_ratelimited(adev->dev, "Page is not RAM.\n");
1278 return;
1279 }
1280 nid = pfn_to_nid(addr >> PAGE_SHIFT);
1281 dev_dbg_ratelimited(adev->dev, "vm->mem_id=%d, local_node=%d, nid=%d\n",
1282 vm->mem_id, local_node, nid);
1283 if (nid == local_node) {
1284 uint64_t old_flags = *flags;
1285 if ((*flags & AMDGPU_PTE_MTYPE_VG10_MASK) ==
1286 AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_NC)) {
1287 unsigned int mtype_local = MTYPE_RW;
1288
1289 if (amdgpu_mtype_local == 1)
1290 mtype_local = MTYPE_NC;
1291 else if (amdgpu_mtype_local == 2)
1292 mtype_local = MTYPE_CC;
1293
1294 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, mtype_local);
1295 } else {
1296 /* MTYPE_UC case */
1297 *flags = AMDGPU_PTE_MTYPE_VG10(*flags, MTYPE_CC);
1298 }
1299
1300 dev_dbg_ratelimited(adev->dev, "flags updated from %llx to %llx\n",
1301 old_flags, *flags);
1302 }
1303 }
1304
gmc_v9_0_get_vbios_fb_size(struct amdgpu_device * adev)1305 static unsigned int gmc_v9_0_get_vbios_fb_size(struct amdgpu_device *adev)
1306 {
1307 u32 d1vga_control = RREG32_SOC15(DCE, 0, mmD1VGA_CONTROL);
1308 unsigned int size;
1309
1310 /* TODO move to DC so GMC doesn't need to hard-code DCN registers */
1311
1312 if (REG_GET_FIELD(d1vga_control, D1VGA_CONTROL, D1VGA_MODE_ENABLE)) {
1313 size = AMDGPU_VBIOS_VGA_ALLOCATION;
1314 } else {
1315 u32 viewport;
1316
1317 switch (amdgpu_ip_version(adev, DCE_HWIP, 0)) {
1318 case IP_VERSION(1, 0, 0):
1319 case IP_VERSION(1, 0, 1):
1320 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION);
1321 size = (REG_GET_FIELD(viewport,
1322 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1323 REG_GET_FIELD(viewport,
1324 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1325 4);
1326 break;
1327 case IP_VERSION(2, 1, 0):
1328 viewport = RREG32_SOC15(DCE, 0, mmHUBP0_DCSURF_PRI_VIEWPORT_DIMENSION_DCN2);
1329 size = (REG_GET_FIELD(viewport,
1330 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_HEIGHT) *
1331 REG_GET_FIELD(viewport,
1332 HUBP0_DCSURF_PRI_VIEWPORT_DIMENSION, PRI_VIEWPORT_WIDTH) *
1333 4);
1334 break;
1335 default:
1336 viewport = RREG32_SOC15(DCE, 0, mmSCL0_VIEWPORT_SIZE);
1337 size = (REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_HEIGHT) *
1338 REG_GET_FIELD(viewport, SCL0_VIEWPORT_SIZE, VIEWPORT_WIDTH) *
1339 4);
1340 break;
1341 }
1342 }
1343
1344 return size;
1345 }
1346
gmc_v9_0_need_reset_on_init(struct amdgpu_device * adev)1347 static bool gmc_v9_0_need_reset_on_init(struct amdgpu_device *adev)
1348 {
1349 if (adev->nbio.funcs && adev->nbio.funcs->is_nps_switch_requested &&
1350 adev->nbio.funcs->is_nps_switch_requested(adev)) {
1351 adev->gmc.reset_flags |= AMDGPU_GMC_INIT_RESET_NPS;
1352 return true;
1353 }
1354
1355 return false;
1356 }
1357
1358 static const struct amdgpu_gmc_funcs gmc_v9_0_gmc_funcs = {
1359 .flush_gpu_tlb = gmc_v9_0_flush_gpu_tlb,
1360 .flush_gpu_tlb_pasid = gmc_v9_0_flush_gpu_tlb_pasid,
1361 .emit_flush_gpu_tlb = gmc_v9_0_emit_flush_gpu_tlb,
1362 .emit_pasid_mapping = gmc_v9_0_emit_pasid_mapping,
1363 .get_vm_pde = gmc_v9_0_get_vm_pde,
1364 .get_vm_pte = gmc_v9_0_get_vm_pte,
1365 .override_vm_pte_flags = gmc_v9_0_override_vm_pte_flags,
1366 .get_vbios_fb_size = gmc_v9_0_get_vbios_fb_size,
1367 .query_mem_partition_mode = &amdgpu_gmc_query_memory_partition,
1368 .request_mem_partition_mode = &amdgpu_gmc_request_memory_partition,
1369 .need_reset_on_init = &gmc_v9_0_need_reset_on_init,
1370 };
1371
gmc_v9_0_set_gmc_funcs(struct amdgpu_device * adev)1372 static void gmc_v9_0_set_gmc_funcs(struct amdgpu_device *adev)
1373 {
1374 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs;
1375 }
1376
gmc_v9_0_set_umc_funcs(struct amdgpu_device * adev)1377 static void gmc_v9_0_set_umc_funcs(struct amdgpu_device *adev)
1378 {
1379 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
1380 case IP_VERSION(6, 0, 0):
1381 adev->umc.funcs = &umc_v6_0_funcs;
1382 break;
1383 case IP_VERSION(6, 1, 1):
1384 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1385 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1386 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1387 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_VG20;
1388 adev->umc.retire_unit = 1;
1389 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1390 adev->umc.ras = &umc_v6_1_ras;
1391 break;
1392 case IP_VERSION(6, 1, 2):
1393 adev->umc.max_ras_err_cnt_per_query = UMC_V6_1_TOTAL_CHANNEL_NUM;
1394 adev->umc.channel_inst_num = UMC_V6_1_CHANNEL_INSTANCE_NUM;
1395 adev->umc.umc_inst_num = UMC_V6_1_UMC_INSTANCE_NUM;
1396 adev->umc.channel_offs = UMC_V6_1_PER_CHANNEL_OFFSET_ARCT;
1397 adev->umc.retire_unit = 1;
1398 adev->umc.channel_idx_tbl = &umc_v6_1_channel_idx_tbl[0][0];
1399 adev->umc.ras = &umc_v6_1_ras;
1400 break;
1401 case IP_VERSION(6, 7, 0):
1402 adev->umc.max_ras_err_cnt_per_query =
1403 UMC_V6_7_TOTAL_CHANNEL_NUM * UMC_V6_7_BAD_PAGE_NUM_PER_CHANNEL;
1404 adev->umc.channel_inst_num = UMC_V6_7_CHANNEL_INSTANCE_NUM;
1405 adev->umc.umc_inst_num = UMC_V6_7_UMC_INSTANCE_NUM;
1406 adev->umc.channel_offs = UMC_V6_7_PER_CHANNEL_OFFSET;
1407 adev->umc.retire_unit = (UMC_V6_7_NA_MAP_PA_NUM * 2);
1408 if (!adev->gmc.xgmi.connected_to_cpu)
1409 adev->umc.ras = &umc_v6_7_ras;
1410 if (1 & adev->smuio.funcs->get_die_id(adev))
1411 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_first[0][0];
1412 else
1413 adev->umc.channel_idx_tbl = &umc_v6_7_channel_idx_tbl_second[0][0];
1414 break;
1415 case IP_VERSION(12, 0, 0):
1416 case IP_VERSION(12, 5, 0):
1417 adev->umc.max_ras_err_cnt_per_query =
1418 UMC_V12_0_TOTAL_CHANNEL_NUM(adev) * UMC_V12_0_BAD_PAGE_NUM_PER_CHANNEL;
1419 adev->umc.channel_inst_num = UMC_V12_0_CHANNEL_INSTANCE_NUM;
1420 adev->umc.umc_inst_num = UMC_V12_0_UMC_INSTANCE_NUM;
1421 adev->umc.node_inst_num /= UMC_V12_0_UMC_INSTANCE_NUM;
1422 adev->umc.channel_offs = UMC_V12_0_PER_CHANNEL_OFFSET;
1423 if (!adev->gmc.xgmi.connected_to_cpu && !adev->gmc.is_app_apu)
1424 adev->umc.ras = &umc_v12_0_ras;
1425 break;
1426 default:
1427 break;
1428 }
1429 }
1430
gmc_v9_0_set_mmhub_funcs(struct amdgpu_device * adev)1431 static void gmc_v9_0_set_mmhub_funcs(struct amdgpu_device *adev)
1432 {
1433 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
1434 case IP_VERSION(9, 4, 1):
1435 adev->mmhub.funcs = &mmhub_v9_4_funcs;
1436 break;
1437 case IP_VERSION(9, 4, 2):
1438 adev->mmhub.funcs = &mmhub_v1_7_funcs;
1439 break;
1440 case IP_VERSION(1, 8, 0):
1441 case IP_VERSION(1, 8, 1):
1442 adev->mmhub.funcs = &mmhub_v1_8_funcs;
1443 break;
1444 default:
1445 adev->mmhub.funcs = &mmhub_v1_0_funcs;
1446 break;
1447 }
1448 }
1449
gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device * adev)1450 static void gmc_v9_0_set_mmhub_ras_funcs(struct amdgpu_device *adev)
1451 {
1452 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
1453 case IP_VERSION(9, 4, 0):
1454 adev->mmhub.ras = &mmhub_v1_0_ras;
1455 break;
1456 case IP_VERSION(9, 4, 1):
1457 adev->mmhub.ras = &mmhub_v9_4_ras;
1458 break;
1459 case IP_VERSION(9, 4, 2):
1460 adev->mmhub.ras = &mmhub_v1_7_ras;
1461 break;
1462 case IP_VERSION(1, 8, 0):
1463 case IP_VERSION(1, 8, 1):
1464 adev->mmhub.ras = &mmhub_v1_8_ras;
1465 break;
1466 default:
1467 /* mmhub ras is not available */
1468 break;
1469 }
1470 }
1471
gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device * adev)1472 static void gmc_v9_0_set_gfxhub_funcs(struct amdgpu_device *adev)
1473 {
1474 if (amdgpu_is_multi_aid(adev))
1475 adev->gfxhub.funcs = &gfxhub_v1_2_funcs;
1476 else
1477 adev->gfxhub.funcs = &gfxhub_v1_0_funcs;
1478 }
1479
gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device * adev)1480 static void gmc_v9_0_set_hdp_ras_funcs(struct amdgpu_device *adev)
1481 {
1482 adev->hdp.ras = &hdp_v4_0_ras;
1483 }
1484
gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device * adev)1485 static void gmc_v9_0_set_mca_ras_funcs(struct amdgpu_device *adev)
1486 {
1487 struct amdgpu_mca *mca = &adev->mca;
1488
1489 /* is UMC the right IP to check for MCA? Maybe DF? */
1490 switch (amdgpu_ip_version(adev, UMC_HWIP, 0)) {
1491 case IP_VERSION(6, 7, 0):
1492 if (!adev->gmc.xgmi.connected_to_cpu) {
1493 mca->mp0.ras = &mca_v3_0_mp0_ras;
1494 mca->mp1.ras = &mca_v3_0_mp1_ras;
1495 mca->mpio.ras = &mca_v3_0_mpio_ras;
1496 }
1497 break;
1498 default:
1499 break;
1500 }
1501 }
1502
gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device * adev)1503 static void gmc_v9_0_set_xgmi_ras_funcs(struct amdgpu_device *adev)
1504 {
1505 if (!adev->gmc.xgmi.connected_to_cpu)
1506 adev->gmc.xgmi.ras = &xgmi_ras;
1507 }
1508
gmc_v9_0_init_nps_details(struct amdgpu_device * adev)1509 static void gmc_v9_0_init_nps_details(struct amdgpu_device *adev)
1510 {
1511 enum amdgpu_memory_partition mode;
1512 uint32_t supp_modes;
1513 int i;
1514
1515 adev->gmc.supported_nps_modes = 0;
1516
1517 if (amdgpu_sriov_vf(adev) || (adev->flags & AMD_IS_APU))
1518 return;
1519
1520 mode = amdgpu_gmc_get_memory_partition(adev, &supp_modes);
1521
1522 /* Mode detected by hardware and supported modes available */
1523 if ((mode != UNKNOWN_MEMORY_PARTITION_MODE) && supp_modes) {
1524 while ((i = ffs(supp_modes))) {
1525 if (AMDGPU_ALL_NPS_MASK & BIT(i))
1526 adev->gmc.supported_nps_modes |= BIT(i);
1527 supp_modes &= supp_modes - 1;
1528 }
1529 } else {
1530 /*TODO: Check PSP version also which supports NPS switch. Otherwise keep
1531 * supported modes as 0.
1532 */
1533 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1534 case IP_VERSION(9, 4, 3):
1535 case IP_VERSION(9, 4, 4):
1536 adev->gmc.supported_nps_modes =
1537 BIT(AMDGPU_NPS1_PARTITION_MODE) |
1538 BIT(AMDGPU_NPS4_PARTITION_MODE);
1539 break;
1540 default:
1541 break;
1542 }
1543 }
1544 }
1545
gmc_v9_0_early_init(struct amdgpu_ip_block * ip_block)1546 static int gmc_v9_0_early_init(struct amdgpu_ip_block *ip_block)
1547 {
1548 struct amdgpu_device *adev = ip_block->adev;
1549
1550 /*
1551 * 9.4.0, 9.4.1 and 9.4.3 don't have XGMI defined
1552 * in their IP discovery tables
1553 */
1554 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) ||
1555 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) ||
1556 amdgpu_is_multi_aid(adev))
1557 adev->gmc.xgmi.supported = true;
1558
1559 if (amdgpu_ip_version(adev, XGMI_HWIP, 0) == IP_VERSION(6, 1, 0)) {
1560 adev->gmc.xgmi.supported = true;
1561 adev->gmc.xgmi.connected_to_cpu =
1562 adev->smuio.funcs->is_host_gpu_xgmi_supported(adev);
1563 }
1564
1565 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 3)) {
1566 enum amdgpu_pkg_type pkg_type =
1567 adev->smuio.funcs->get_pkg_type(adev);
1568 /* On GFXIP 9.4.3. APU, there is no physical VRAM domain present
1569 * and the APU, can be in used two possible modes:
1570 * - carveout mode
1571 * - native APU mode
1572 * "is_app_apu" can be used to identify the APU in the native
1573 * mode.
1574 */
1575 adev->gmc.is_app_apu = (pkg_type == AMDGPU_PKG_TYPE_APU &&
1576 !pci_resource_len(adev->pdev, 0));
1577 }
1578
1579 gmc_v9_0_set_gmc_funcs(adev);
1580 gmc_v9_0_set_irq_funcs(adev);
1581 gmc_v9_0_set_umc_funcs(adev);
1582 gmc_v9_0_set_mmhub_funcs(adev);
1583 gmc_v9_0_set_mmhub_ras_funcs(adev);
1584 gmc_v9_0_set_gfxhub_funcs(adev);
1585 gmc_v9_0_set_hdp_ras_funcs(adev);
1586 gmc_v9_0_set_mca_ras_funcs(adev);
1587 gmc_v9_0_set_xgmi_ras_funcs(adev);
1588
1589 adev->gmc.shared_aperture_start = 0x2000000000000000ULL;
1590 adev->gmc.shared_aperture_end =
1591 adev->gmc.shared_aperture_start + (4ULL << 30) - 1;
1592 adev->gmc.private_aperture_start = 0x1000000000000000ULL;
1593 adev->gmc.private_aperture_end =
1594 adev->gmc.private_aperture_start + (4ULL << 30) - 1;
1595 adev->gmc.noretry_flags = AMDGPU_VM_NORETRY_FLAGS_TF;
1596
1597 return 0;
1598 }
1599
gmc_v9_0_late_init(struct amdgpu_ip_block * ip_block)1600 static int gmc_v9_0_late_init(struct amdgpu_ip_block *ip_block)
1601 {
1602 struct amdgpu_device *adev = ip_block->adev;
1603 int r;
1604
1605 r = amdgpu_gmc_allocate_vm_inv_eng(adev);
1606 if (r)
1607 return r;
1608
1609 /*
1610 * Workaround performance drop issue with VBIOS enables partial
1611 * writes, while disables HBM ECC for vega10.
1612 */
1613 if (!amdgpu_sriov_vf(adev) &&
1614 (amdgpu_ip_version(adev, UMC_HWIP, 0) == IP_VERSION(6, 0, 0))) {
1615 if (!(adev->ras_enabled & (1 << AMDGPU_RAS_BLOCK__UMC))) {
1616 if (adev->df.funcs &&
1617 adev->df.funcs->enable_ecc_force_par_wr_rmw)
1618 adev->df.funcs->enable_ecc_force_par_wr_rmw(adev, false);
1619 }
1620 }
1621
1622 if (!amdgpu_persistent_edc_harvesting_supported(adev)) {
1623 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__MMHUB);
1624 amdgpu_ras_reset_error_count(adev, AMDGPU_RAS_BLOCK__HDP);
1625 }
1626
1627 r = amdgpu_gmc_ras_late_init(adev);
1628 if (r)
1629 return r;
1630
1631 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0);
1632 }
1633
gmc_v9_0_vram_gtt_location(struct amdgpu_device * adev,struct amdgpu_gmc * mc)1634 static void gmc_v9_0_vram_gtt_location(struct amdgpu_device *adev,
1635 struct amdgpu_gmc *mc)
1636 {
1637 u64 base = adev->mmhub.funcs->get_fb_location(adev);
1638
1639 amdgpu_gmc_set_agp_default(adev, mc);
1640
1641 /* add the xgmi offset of the physical node */
1642 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1643 if (amdgpu_gmc_is_pdb0_enabled(adev)) {
1644 amdgpu_gmc_sysvm_location(adev, mc);
1645 } else {
1646 amdgpu_gmc_vram_location(adev, mc, base);
1647 amdgpu_gmc_gart_location(adev, mc, AMDGPU_GART_PLACEMENT_BEST_FIT);
1648 if (!amdgpu_sriov_vf(adev) && (amdgpu_agp == 1))
1649 amdgpu_gmc_agp_location(adev, mc);
1650 }
1651 /* base offset of vram pages */
1652 adev->vm_manager.vram_base_offset = adev->gfxhub.funcs->get_mc_fb_offset(adev);
1653
1654 /* XXX: add the xgmi offset of the physical node? */
1655 adev->vm_manager.vram_base_offset +=
1656 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size;
1657 }
1658
1659 /**
1660 * gmc_v9_0_mc_init - initialize the memory controller driver params
1661 *
1662 * @adev: amdgpu_device pointer
1663 *
1664 * Look up the amount of vram, vram width, and decide how to place
1665 * vram and gart within the GPU's physical address space.
1666 * Returns 0 for success.
1667 */
gmc_v9_0_mc_init(struct amdgpu_device * adev)1668 static int gmc_v9_0_mc_init(struct amdgpu_device *adev)
1669 {
1670 int r;
1671
1672 /* size in MB on si */
1673 if (!adev->gmc.is_app_apu) {
1674 adev->gmc.mc_vram_size =
1675 adev->nbio.funcs->get_memsize(adev) * 1024ULL * 1024ULL;
1676 } else {
1677 DRM_DEBUG("Set mc_vram_size = 0 for APP APU\n");
1678 adev->gmc.mc_vram_size = 0;
1679 }
1680 adev->gmc.real_vram_size = adev->gmc.mc_vram_size;
1681
1682 if (!(adev->flags & AMD_IS_APU) &&
1683 !adev->gmc.xgmi.connected_to_cpu) {
1684 r = amdgpu_device_resize_fb_bar(adev);
1685 if (r)
1686 return r;
1687 }
1688 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0);
1689 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0);
1690
1691 #ifdef CONFIG_X86_64
1692 /*
1693 * AMD Accelerated Processing Platform (APP) supporting GPU-HOST xgmi
1694 * interface can use VRAM through here as it appears system reserved
1695 * memory in host address space.
1696 *
1697 * For APUs, VRAM is just the stolen system memory and can be accessed
1698 * directly.
1699 *
1700 * Otherwise, use the legacy Host Data Path (HDP) through PCIe BAR.
1701 */
1702
1703 /* check whether both host-gpu and gpu-gpu xgmi links exist */
1704 if ((!amdgpu_sriov_vf(adev) &&
1705 (adev->flags & AMD_IS_APU) && !amdgpu_passthrough(adev)) ||
1706 (adev->gmc.xgmi.supported &&
1707 adev->gmc.xgmi.connected_to_cpu)) {
1708 adev->gmc.aper_base =
1709 adev->gfxhub.funcs->get_mc_fb_offset(adev) +
1710 adev->gmc.xgmi.physical_node_id *
1711 adev->gmc.xgmi.node_segment_size;
1712 adev->gmc.aper_size = adev->gmc.real_vram_size;
1713 }
1714
1715 #endif
1716 adev->gmc.visible_vram_size = adev->gmc.aper_size;
1717
1718 /* set the gart size */
1719 if (amdgpu_gart_size == -1) {
1720 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1721 case IP_VERSION(9, 0, 1): /* all engines support GPUVM */
1722 case IP_VERSION(9, 2, 1): /* all engines support GPUVM */
1723 case IP_VERSION(9, 4, 0):
1724 case IP_VERSION(9, 4, 1):
1725 case IP_VERSION(9, 4, 2):
1726 case IP_VERSION(9, 4, 3):
1727 case IP_VERSION(9, 4, 4):
1728 case IP_VERSION(9, 5, 0):
1729 default:
1730 adev->gmc.gart_size = 512ULL << 20;
1731 break;
1732 case IP_VERSION(9, 1, 0): /* DCE SG support */
1733 case IP_VERSION(9, 2, 2): /* DCE SG support */
1734 case IP_VERSION(9, 3, 0):
1735 adev->gmc.gart_size = 1024ULL << 20;
1736 break;
1737 }
1738 } else {
1739 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20;
1740 }
1741
1742 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size;
1743
1744 gmc_v9_0_vram_gtt_location(adev, &adev->gmc);
1745
1746 return 0;
1747 }
1748
gmc_v9_0_gart_init(struct amdgpu_device * adev)1749 static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
1750 {
1751 int r;
1752
1753 if (adev->gart.bo) {
1754 WARN(1, "VEGA10 PCIE GART already initialized\n");
1755 return 0;
1756 }
1757
1758 if (amdgpu_gmc_is_pdb0_enabled(adev)) {
1759 adev->gmc.vmid0_page_table_depth = 1;
1760 adev->gmc.vmid0_page_table_block_size = 12;
1761 } else {
1762 adev->gmc.vmid0_page_table_depth = 0;
1763 adev->gmc.vmid0_page_table_block_size = 0;
1764 }
1765
1766 /* Initialize common gart structure */
1767 r = amdgpu_gart_init(adev);
1768 if (r)
1769 return r;
1770 adev->gart.table_size = adev->gart.num_gpu_pages * 8;
1771 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) |
1772 AMDGPU_PTE_EXECUTABLE;
1773
1774 if (!adev->gmc.real_vram_size) {
1775 dev_info(adev->dev, "Put GART in system memory for APU\n");
1776 r = amdgpu_gart_table_ram_alloc(adev);
1777 if (r)
1778 dev_err(adev->dev, "Failed to allocate GART in system memory\n");
1779 } else {
1780 r = amdgpu_gart_table_vram_alloc(adev);
1781 if (r)
1782 return r;
1783
1784 if (amdgpu_gmc_is_pdb0_enabled(adev))
1785 r = amdgpu_gmc_pdb0_alloc(adev);
1786 }
1787
1788 return r;
1789 }
1790
1791 /**
1792 * gmc_v9_0_save_registers - saves regs
1793 *
1794 * @adev: amdgpu_device pointer
1795 *
1796 * This saves potential register values that should be
1797 * restored upon resume
1798 */
gmc_v9_0_save_registers(struct amdgpu_device * adev)1799 static void gmc_v9_0_save_registers(struct amdgpu_device *adev)
1800 {
1801 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) ||
1802 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1)))
1803 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0);
1804 }
1805
gmc_v9_4_3_init_vram_info(struct amdgpu_device * adev)1806 static void gmc_v9_4_3_init_vram_info(struct amdgpu_device *adev)
1807 {
1808 static const u32 regBIF_BIOS_SCRATCH_4 = 0x50;
1809 u32 vram_info;
1810
1811 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
1812 adev->gmc.vram_width = 128 * 64;
1813
1814 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 5, 0))
1815 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E;
1816
1817 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 4) &&
1818 adev->rev_id == 0x3)
1819 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM3E;
1820
1821 if (!(adev->flags & AMD_IS_APU) && !amdgpu_sriov_vf(adev)) {
1822 vram_info = RREG32(regBIF_BIOS_SCRATCH_4);
1823 adev->gmc.vram_vendor = vram_info & 0xF;
1824 }
1825 }
1826
gmc_v9_0_sw_init(struct amdgpu_ip_block * ip_block)1827 static int gmc_v9_0_sw_init(struct amdgpu_ip_block *ip_block)
1828 {
1829 int r, vram_width = 0, vram_type = 0, vram_vendor = 0, dma_addr_bits;
1830 struct amdgpu_device *adev = ip_block->adev;
1831 unsigned long inst_mask = adev->aid_mask;
1832
1833 adev->gfxhub.funcs->init(adev);
1834
1835 adev->mmhub.funcs->init(adev);
1836
1837 spin_lock_init(&adev->gmc.invalidate_lock);
1838
1839 if (amdgpu_is_multi_aid(adev)) {
1840 gmc_v9_4_3_init_vram_info(adev);
1841 } else if (!adev->bios) {
1842 if (adev->flags & AMD_IS_APU) {
1843 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_DDR4;
1844 adev->gmc.vram_width = 64 * 64;
1845 } else {
1846 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_HBM;
1847 adev->gmc.vram_width = 128 * 64;
1848 }
1849 } else {
1850 r = amdgpu_atomfirmware_get_vram_info(adev,
1851 &vram_width, &vram_type, &vram_vendor);
1852 if (amdgpu_sriov_vf(adev))
1853 /* For Vega10 SR-IOV, vram_width can't be read from ATOM as RAVEN,
1854 * and DF related registers is not readable, seems hardcord is the
1855 * only way to set the correct vram_width
1856 */
1857 adev->gmc.vram_width = 2048;
1858 else if (amdgpu_emu_mode != 1)
1859 adev->gmc.vram_width = vram_width;
1860
1861 if (!adev->gmc.vram_width) {
1862 int chansize, numchan;
1863
1864 /* hbm memory channel size */
1865 if (adev->flags & AMD_IS_APU)
1866 chansize = 64;
1867 else
1868 chansize = 128;
1869 if (adev->df.funcs &&
1870 adev->df.funcs->get_hbm_channel_number) {
1871 numchan = adev->df.funcs->get_hbm_channel_number(adev);
1872 adev->gmc.vram_width = numchan * chansize;
1873 }
1874 }
1875
1876 adev->gmc.vram_type = vram_type;
1877 adev->gmc.vram_vendor = vram_vendor;
1878 }
1879 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1880 case IP_VERSION(9, 1, 0):
1881 case IP_VERSION(9, 2, 2):
1882 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
1883 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
1884
1885 if (adev->rev_id == 0x0 || adev->rev_id == 0x1) {
1886 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1887 } else {
1888 /* vm_size is 128TB + 512GB for legacy 3-level page support */
1889 amdgpu_vm_adjust_size(adev, 128 * 1024 + 512, 9, 2, 48);
1890 adev->gmc.translate_further =
1891 adev->vm_manager.num_level > 1;
1892 }
1893 break;
1894 case IP_VERSION(9, 0, 1):
1895 case IP_VERSION(9, 2, 1):
1896 case IP_VERSION(9, 4, 0):
1897 case IP_VERSION(9, 3, 0):
1898 case IP_VERSION(9, 4, 2):
1899 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
1900 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
1901
1902 /*
1903 * To fulfill 4-level page support,
1904 * vm size is 256TB (48bit), maximum size of Vega10,
1905 * block size 512 (9bit)
1906 */
1907
1908 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1909 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2))
1910 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
1911 break;
1912 case IP_VERSION(9, 4, 1):
1913 set_bit(AMDGPU_GFXHUB(0), adev->vmhubs_mask);
1914 set_bit(AMDGPU_MMHUB0(0), adev->vmhubs_mask);
1915 set_bit(AMDGPU_MMHUB1(0), adev->vmhubs_mask);
1916
1917 /* Keep the vm size same with Vega20 */
1918 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1919 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
1920 break;
1921 case IP_VERSION(9, 4, 3):
1922 case IP_VERSION(9, 4, 4):
1923 case IP_VERSION(9, 5, 0):
1924 bitmap_set(adev->vmhubs_mask, AMDGPU_GFXHUB(0),
1925 NUM_XCC(adev->gfx.xcc_mask));
1926
1927 inst_mask <<= AMDGPU_MMHUB0(0);
1928 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32);
1929
1930 amdgpu_vm_adjust_size(adev, 256 * 1024, 9, 3, 48);
1931 adev->gmc.translate_further = adev->vm_manager.num_level > 1;
1932 break;
1933 default:
1934 break;
1935 }
1936
1937 /* This interrupt is VMC page fault.*/
1938 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC, VMC_1_0__SRCID__VM_FAULT,
1939 &adev->gmc.vm_fault);
1940 if (r)
1941 return r;
1942
1943 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1)) {
1944 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VMC1, VMC_1_0__SRCID__VM_FAULT,
1945 &adev->gmc.vm_fault);
1946 if (r)
1947 return r;
1948 }
1949
1950 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UTCL2, UTCL2_1_0__SRCID__FAULT,
1951 &adev->gmc.vm_fault);
1952
1953 if (r)
1954 return r;
1955
1956 if (!amdgpu_sriov_vf(adev) &&
1957 !adev->gmc.xgmi.connected_to_cpu &&
1958 !adev->gmc.is_app_apu) {
1959 /* interrupt sent to DF. */
1960 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_DF, 0,
1961 &adev->gmc.ecc_irq);
1962 if (r)
1963 return r;
1964 }
1965
1966 /* Set the internal MC address mask
1967 * This is the max address of the GPU's
1968 * internal address space.
1969 */
1970 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */
1971
1972 dma_addr_bits = amdgpu_ip_version(adev, GC_HWIP, 0) >=
1973 IP_VERSION(9, 4, 2) ?
1974 48 :
1975 44;
1976 r = dma_set_mask_and_coherent(adev->dev, DMA_BIT_MASK(dma_addr_bits));
1977 if (r) {
1978 drm_warn(adev_to_drm(adev), "No suitable DMA available.\n");
1979 return r;
1980 }
1981 adev->need_swiotlb = drm_need_swiotlb(dma_addr_bits);
1982
1983 r = gmc_v9_0_mc_init(adev);
1984 if (r)
1985 return r;
1986
1987 amdgpu_gmc_get_vbios_allocations(adev);
1988
1989 if (amdgpu_is_multi_aid(adev)) {
1990 r = amdgpu_gmc_init_mem_ranges(adev);
1991 if (r)
1992 return r;
1993 }
1994
1995 /* Memory manager */
1996 r = amdgpu_bo_init(adev);
1997 if (r)
1998 return r;
1999
2000 r = gmc_v9_0_gart_init(adev);
2001 if (r)
2002 return r;
2003
2004 gmc_v9_0_init_nps_details(adev);
2005 /*
2006 * number of VMs
2007 * VMID 0 is reserved for System
2008 * amdgpu graphics/compute will use VMIDs 1..n-1
2009 * amdkfd will use VMIDs n..15
2010 *
2011 * The first KFD VMID is 8 for GPUs with graphics, 3 for
2012 * compute-only GPUs. On compute-only GPUs that leaves 2 VMIDs
2013 * for video processing.
2014 */
2015 adev->vm_manager.first_kfd_vmid =
2016 (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 1) ||
2017 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 2) ||
2018 amdgpu_is_multi_aid(adev)) ?
2019 3 :
2020 8;
2021
2022 amdgpu_vm_manager_init(adev);
2023
2024 gmc_v9_0_save_registers(adev);
2025
2026 r = amdgpu_gmc_ras_sw_init(adev);
2027 if (r)
2028 return r;
2029
2030 if (amdgpu_is_multi_aid(adev))
2031 amdgpu_gmc_sysfs_init(adev);
2032
2033 return 0;
2034 }
2035
gmc_v9_0_sw_fini(struct amdgpu_ip_block * ip_block)2036 static int gmc_v9_0_sw_fini(struct amdgpu_ip_block *ip_block)
2037 {
2038 struct amdgpu_device *adev = ip_block->adev;
2039
2040 if (amdgpu_is_multi_aid(adev))
2041 amdgpu_gmc_sysfs_fini(adev);
2042
2043 amdgpu_gmc_ras_fini(adev);
2044 amdgpu_gem_force_release(adev);
2045 amdgpu_vm_manager_fini(adev);
2046 if (!adev->gmc.real_vram_size) {
2047 dev_info(adev->dev, "Put GART in system memory for APU free\n");
2048 amdgpu_gart_table_ram_free(adev);
2049 } else {
2050 amdgpu_gart_table_vram_free(adev);
2051 }
2052 amdgpu_bo_free_kernel(&adev->gmc.pdb0_bo, NULL, &adev->gmc.ptr_pdb0);
2053 amdgpu_bo_fini(adev);
2054
2055 adev->gmc.num_mem_partitions = 0;
2056 kfree(adev->gmc.mem_partitions);
2057
2058 return 0;
2059 }
2060
gmc_v9_0_init_golden_registers(struct amdgpu_device * adev)2061 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev)
2062 {
2063 switch (amdgpu_ip_version(adev, MMHUB_HWIP, 0)) {
2064 case IP_VERSION(9, 0, 0):
2065 if (amdgpu_sriov_vf(adev))
2066 break;
2067 fallthrough;
2068 case IP_VERSION(9, 4, 0):
2069 soc15_program_register_sequence(adev,
2070 golden_settings_mmhub_1_0_0,
2071 ARRAY_SIZE(golden_settings_mmhub_1_0_0));
2072 soc15_program_register_sequence(adev,
2073 golden_settings_athub_1_0_0,
2074 ARRAY_SIZE(golden_settings_athub_1_0_0));
2075 break;
2076 case IP_VERSION(9, 1, 0):
2077 case IP_VERSION(9, 2, 0):
2078 /* TODO for renoir */
2079 soc15_program_register_sequence(adev,
2080 golden_settings_athub_1_0_0,
2081 ARRAY_SIZE(golden_settings_athub_1_0_0));
2082 break;
2083 default:
2084 break;
2085 }
2086 }
2087
2088 /**
2089 * gmc_v9_0_restore_registers - restores regs
2090 *
2091 * @adev: amdgpu_device pointer
2092 *
2093 * This restores register values, saved at suspend.
2094 */
gmc_v9_0_restore_registers(struct amdgpu_device * adev)2095 void gmc_v9_0_restore_registers(struct amdgpu_device *adev)
2096 {
2097 if ((amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 0)) ||
2098 (amdgpu_ip_version(adev, DCE_HWIP, 0) == IP_VERSION(1, 0, 1))) {
2099 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register);
2100 WARN_ON(adev->gmc.sdpif_register !=
2101 RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0));
2102 }
2103 }
2104
2105 /**
2106 * gmc_v9_0_gart_enable - gart enable
2107 *
2108 * @adev: amdgpu_device pointer
2109 */
gmc_v9_0_gart_enable(struct amdgpu_device * adev)2110 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
2111 {
2112 int r;
2113
2114 if (amdgpu_gmc_is_pdb0_enabled(adev))
2115 amdgpu_gmc_init_pdb0(adev);
2116
2117 if (adev->gart.bo == NULL) {
2118 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
2119 return -EINVAL;
2120 }
2121
2122 amdgpu_gtt_mgr_recover(&adev->mman.gtt_mgr);
2123
2124 if (!adev->in_s0ix) {
2125 r = adev->gfxhub.funcs->gart_enable(adev);
2126 if (r)
2127 return r;
2128 }
2129
2130 r = adev->mmhub.funcs->gart_enable(adev);
2131 if (r)
2132 return r;
2133
2134 drm_info(adev_to_drm(adev), "PCIE GART of %uM enabled.\n",
2135 (unsigned int)(adev->gmc.gart_size >> 20));
2136 if (adev->gmc.pdb0_bo)
2137 drm_info(adev_to_drm(adev), "PDB0 located at 0x%016llX\n",
2138 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo));
2139 drm_info(adev_to_drm(adev), "PTB located at 0x%016llX\n",
2140 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
2141
2142 return 0;
2143 }
2144
gmc_v9_0_hw_init(struct amdgpu_ip_block * ip_block)2145 static int gmc_v9_0_hw_init(struct amdgpu_ip_block *ip_block)
2146 {
2147 struct amdgpu_device *adev = ip_block->adev;
2148 bool value;
2149 int i, r;
2150
2151 adev->gmc.flush_pasid_uses_kiq = true;
2152
2153 /* Vega20+XGMI caches PTEs in TC and TLB. Add a heavy-weight TLB flush
2154 * (type 2), which flushes both. Due to a race condition with
2155 * concurrent memory accesses using the same TLB cache line, we still
2156 * need a second TLB flush after this.
2157 */
2158 adev->gmc.flush_tlb_needs_extra_type_2 =
2159 amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(9, 4, 0) &&
2160 adev->gmc.xgmi.num_physical_nodes;
2161
2162 /* The sequence of these two function calls matters.*/
2163 gmc_v9_0_init_golden_registers(adev);
2164
2165 if (adev->mode_info.num_crtc) {
2166 /* Lockout access through VGA aperture*/
2167 WREG32_FIELD15(DCE, 0, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE, 1);
2168 /* disable VGA render */
2169 WREG32_FIELD15(DCE, 0, VGA_RENDER_CONTROL, VGA_VSTATUS_CNTL, 0);
2170 }
2171
2172 if (adev->mmhub.funcs->update_power_gating)
2173 adev->mmhub.funcs->update_power_gating(adev, true);
2174
2175 adev->hdp.funcs->init_registers(adev);
2176
2177 /* After HDP is initialized, flush HDP.*/
2178 amdgpu_device_flush_hdp(adev, NULL);
2179
2180 if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
2181 value = false;
2182 else
2183 value = true;
2184
2185 if (!amdgpu_sriov_vf(adev)) {
2186 if (!adev->in_s0ix)
2187 adev->gfxhub.funcs->set_fault_enable_default(adev, value);
2188 adev->mmhub.funcs->set_fault_enable_default(adev, value);
2189 }
2190 for_each_set_bit(i, adev->vmhubs_mask, AMDGPU_MAX_VMHUBS) {
2191 if (adev->in_s0ix && (i == AMDGPU_GFXHUB(0)))
2192 continue;
2193 gmc_v9_0_flush_gpu_tlb(adev, 0, i, 0);
2194 }
2195
2196 if (adev->umc.funcs && adev->umc.funcs->init_registers)
2197 adev->umc.funcs->init_registers(adev);
2198
2199 r = gmc_v9_0_gart_enable(adev);
2200 if (r)
2201 return r;
2202
2203 if (amdgpu_emu_mode == 1)
2204 return amdgpu_gmc_vram_checking(adev);
2205
2206 return 0;
2207 }
2208
2209 /**
2210 * gmc_v9_0_gart_disable - gart disable
2211 *
2212 * @adev: amdgpu_device pointer
2213 *
2214 * This disables all VM page table.
2215 */
gmc_v9_0_gart_disable(struct amdgpu_device * adev)2216 static void gmc_v9_0_gart_disable(struct amdgpu_device *adev)
2217 {
2218 if (!adev->in_s0ix)
2219 adev->gfxhub.funcs->gart_disable(adev);
2220 adev->mmhub.funcs->gart_disable(adev);
2221 }
2222
gmc_v9_0_hw_fini(struct amdgpu_ip_block * ip_block)2223 static int gmc_v9_0_hw_fini(struct amdgpu_ip_block *ip_block)
2224 {
2225 struct amdgpu_device *adev = ip_block->adev;
2226
2227 gmc_v9_0_gart_disable(adev);
2228
2229 if (amdgpu_sriov_vf(adev)) {
2230 /* full access mode, so don't touch any GMC register */
2231 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
2232 return 0;
2233 }
2234
2235 /*
2236 * Pair the operations did in gmc_v9_0_hw_init and thus maintain
2237 * a correct cached state for GMC. Otherwise, the "gate" again
2238 * operation on S3 resuming will fail due to wrong cached state.
2239 */
2240 if (adev->mmhub.funcs->update_power_gating)
2241 adev->mmhub.funcs->update_power_gating(adev, false);
2242
2243 /*
2244 * For minimal init, late_init is not called, hence VM fault/RAS irqs
2245 * are not enabled.
2246 */
2247 if (adev->init_lvl->level != AMDGPU_INIT_LEVEL_MINIMAL_XGMI) {
2248 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0);
2249
2250 if (adev->gmc.ecc_irq.funcs &&
2251 amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__UMC))
2252 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0);
2253 }
2254
2255 return 0;
2256 }
2257
gmc_v9_0_suspend(struct amdgpu_ip_block * ip_block)2258 static int gmc_v9_0_suspend(struct amdgpu_ip_block *ip_block)
2259 {
2260 return gmc_v9_0_hw_fini(ip_block);
2261 }
2262
gmc_v9_0_resume(struct amdgpu_ip_block * ip_block)2263 static int gmc_v9_0_resume(struct amdgpu_ip_block *ip_block)
2264 {
2265 struct amdgpu_device *adev = ip_block->adev;
2266 int r;
2267
2268 /* If a reset is done for NPS mode switch, read the memory range
2269 * information again.
2270 */
2271 if (adev->gmc.reset_flags & AMDGPU_GMC_INIT_RESET_NPS) {
2272 amdgpu_gmc_init_sw_mem_ranges(adev, adev->gmc.mem_partitions);
2273 adev->gmc.reset_flags &= ~AMDGPU_GMC_INIT_RESET_NPS;
2274 }
2275
2276 r = gmc_v9_0_hw_init(ip_block);
2277 if (r)
2278 return r;
2279
2280 amdgpu_vmid_reset_all(ip_block->adev);
2281
2282 return 0;
2283 }
2284
gmc_v9_0_is_idle(struct amdgpu_ip_block * ip_block)2285 static bool gmc_v9_0_is_idle(struct amdgpu_ip_block *ip_block)
2286 {
2287 /* MC is always ready in GMC v9.*/
2288 return true;
2289 }
2290
gmc_v9_0_wait_for_idle(struct amdgpu_ip_block * ip_block)2291 static int gmc_v9_0_wait_for_idle(struct amdgpu_ip_block *ip_block)
2292 {
2293 /* There is no need to wait for MC idle in GMC v9.*/
2294 return 0;
2295 }
2296
gmc_v9_0_soft_reset(struct amdgpu_ip_block * ip_block)2297 static int gmc_v9_0_soft_reset(struct amdgpu_ip_block *ip_block)
2298 {
2299 /* XXX for emulation.*/
2300 return 0;
2301 }
2302
gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)2303 static int gmc_v9_0_set_clockgating_state(struct amdgpu_ip_block *ip_block,
2304 enum amd_clockgating_state state)
2305 {
2306 struct amdgpu_device *adev = ip_block->adev;
2307
2308 adev->mmhub.funcs->set_clockgating(adev, state);
2309
2310 athub_v1_0_set_clockgating(adev, state);
2311
2312 return 0;
2313 }
2314
gmc_v9_0_get_clockgating_state(struct amdgpu_ip_block * ip_block,u64 * flags)2315 static void gmc_v9_0_get_clockgating_state(struct amdgpu_ip_block *ip_block, u64 *flags)
2316 {
2317 struct amdgpu_device *adev = ip_block->adev;
2318
2319 adev->mmhub.funcs->get_clockgating(adev, flags);
2320
2321 athub_v1_0_get_clockgating(adev, flags);
2322 }
2323
gmc_v9_0_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)2324 static int gmc_v9_0_set_powergating_state(struct amdgpu_ip_block *ip_block,
2325 enum amd_powergating_state state)
2326 {
2327 return 0;
2328 }
2329
2330 const struct amd_ip_funcs gmc_v9_0_ip_funcs = {
2331 .name = "gmc_v9_0",
2332 .early_init = gmc_v9_0_early_init,
2333 .late_init = gmc_v9_0_late_init,
2334 .sw_init = gmc_v9_0_sw_init,
2335 .sw_fini = gmc_v9_0_sw_fini,
2336 .hw_init = gmc_v9_0_hw_init,
2337 .hw_fini = gmc_v9_0_hw_fini,
2338 .suspend = gmc_v9_0_suspend,
2339 .resume = gmc_v9_0_resume,
2340 .is_idle = gmc_v9_0_is_idle,
2341 .wait_for_idle = gmc_v9_0_wait_for_idle,
2342 .soft_reset = gmc_v9_0_soft_reset,
2343 .set_clockgating_state = gmc_v9_0_set_clockgating_state,
2344 .set_powergating_state = gmc_v9_0_set_powergating_state,
2345 .get_clockgating_state = gmc_v9_0_get_clockgating_state,
2346 };
2347
2348 const struct amdgpu_ip_block_version gmc_v9_0_ip_block = {
2349 .type = AMD_IP_BLOCK_TYPE_GMC,
2350 .major = 9,
2351 .minor = 0,
2352 .rev = 0,
2353 .funcs = &gmc_v9_0_ip_funcs,
2354 };
2355