1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Texas Instruments CPSW Port's PHY Interface Mode selection Driver
4 *
5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com/
6 *
7 * Based on cpsw-phy-sel.c driver created by Mugunthan V N <mugunthanvnm@ti.com>
8 */
9
10 #include <linux/platform_device.h>
11 #include <linux/module.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/of.h>
14 #include <linux/of_address.h>
15 #include <linux/of_net.h>
16 #include <linux/phy.h>
17 #include <linux/phy/phy.h>
18 #include <linux/regmap.h>
19
20 /* AM33xx SoC specific definitions for the CONTROL port */
21 #define AM33XX_GMII_SEL_MODE_MII 0
22 #define AM33XX_GMII_SEL_MODE_RMII 1
23 #define AM33XX_GMII_SEL_MODE_RGMII 2
24
25 /* J72xx SoC specific definitions for the CONTROL port */
26 #define J72XX_GMII_SEL_MODE_SGMII 3
27 #define J72XX_GMII_SEL_MODE_QSGMII 4
28 #define J72XX_GMII_SEL_MODE_USXGMII 5
29 #define J72XX_GMII_SEL_MODE_QSGMII_SUB 6
30
31 #define PHY_GMII_PORT(n) BIT((n) - 1)
32
33 enum {
34 PHY_GMII_SEL_PORT_MODE = 0,
35 PHY_GMII_SEL_RGMII_ID_MODE,
36 PHY_GMII_SEL_RMII_IO_CLK_EN,
37 PHY_GMII_SEL_FIXED_TX_DELAY,
38 PHY_GMII_SEL_LAST,
39 };
40
41 struct phy_gmii_sel_phy_priv {
42 struct phy_gmii_sel_priv *priv;
43 u32 id;
44 struct phy *if_phy;
45 int rmii_clock_external;
46 int phy_if_mode;
47 struct regmap_field *fields[PHY_GMII_SEL_LAST];
48 };
49
50 struct phy_gmii_sel_soc_data {
51 u32 num_ports;
52 u32 features;
53 const struct reg_field (*regfields)[PHY_GMII_SEL_LAST];
54 bool use_of_data;
55 u64 extra_modes;
56 u32 num_qsgmii_main_ports;
57 };
58
59 struct phy_gmii_sel_priv {
60 struct device *dev;
61 const struct phy_gmii_sel_soc_data *soc_data;
62 struct regmap *regmap;
63 struct phy_provider *phy_provider;
64 struct phy_gmii_sel_phy_priv *if_phys;
65 u32 num_ports;
66 u32 reg_offset;
67 u32 qsgmii_main_ports;
68 bool no_offset;
69 };
70
phy_gmii_sel_mode(struct phy * phy,enum phy_mode mode,int submode)71 static int phy_gmii_sel_mode(struct phy *phy, enum phy_mode mode, int submode)
72 {
73 struct phy_gmii_sel_phy_priv *if_phy = phy_get_drvdata(phy);
74 const struct phy_gmii_sel_soc_data *soc_data = if_phy->priv->soc_data;
75 struct device *dev = if_phy->priv->dev;
76 struct regmap_field *regfield;
77 int ret, rgmii_id = 0;
78 u32 gmii_sel_mode = 0;
79
80 if (mode != PHY_MODE_ETHERNET)
81 return -EINVAL;
82
83 switch (submode) {
84 case PHY_INTERFACE_MODE_RMII:
85 gmii_sel_mode = AM33XX_GMII_SEL_MODE_RMII;
86 break;
87
88 case PHY_INTERFACE_MODE_RGMII:
89 case PHY_INTERFACE_MODE_RGMII_RXID:
90 gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII;
91 break;
92
93 case PHY_INTERFACE_MODE_RGMII_ID:
94 case PHY_INTERFACE_MODE_RGMII_TXID:
95 gmii_sel_mode = AM33XX_GMII_SEL_MODE_RGMII;
96 rgmii_id = 1;
97 break;
98
99 case PHY_INTERFACE_MODE_MII:
100 case PHY_INTERFACE_MODE_GMII:
101 gmii_sel_mode = AM33XX_GMII_SEL_MODE_MII;
102 break;
103
104 case PHY_INTERFACE_MODE_QSGMII:
105 if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_QSGMII)))
106 goto unsupported;
107 if (if_phy->priv->qsgmii_main_ports & BIT(if_phy->id - 1))
108 gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII;
109 else
110 gmii_sel_mode = J72XX_GMII_SEL_MODE_QSGMII_SUB;
111 break;
112
113 case PHY_INTERFACE_MODE_SGMII:
114 if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_SGMII)))
115 goto unsupported;
116 else
117 gmii_sel_mode = J72XX_GMII_SEL_MODE_SGMII;
118 break;
119
120 case PHY_INTERFACE_MODE_USXGMII:
121 if (!(soc_data->extra_modes & BIT(PHY_INTERFACE_MODE_USXGMII)))
122 goto unsupported;
123 else
124 gmii_sel_mode = J72XX_GMII_SEL_MODE_USXGMII;
125 break;
126
127 default:
128 goto unsupported;
129 }
130
131 /* With a fixed delay, some modes are not supported at all. */
132 if (soc_data->features & BIT(PHY_GMII_SEL_FIXED_TX_DELAY) &&
133 rgmii_id != 0)
134 return -EINVAL;
135
136 if_phy->phy_if_mode = submode;
137
138 dev_dbg(dev, "%s id:%u mode:%u rgmii_id:%d rmii_clk_ext:%d\n",
139 __func__, if_phy->id, submode, rgmii_id,
140 if_phy->rmii_clock_external);
141
142 regfield = if_phy->fields[PHY_GMII_SEL_PORT_MODE];
143 ret = regmap_field_write(regfield, gmii_sel_mode);
144 if (ret) {
145 dev_err(dev, "port%u: set mode fail %d", if_phy->id, ret);
146 return ret;
147 }
148
149 if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE) &&
150 if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE]) {
151 regfield = if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE];
152 ret = regmap_field_write(regfield, rgmii_id);
153 if (ret)
154 return ret;
155 }
156
157 if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) &&
158 if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN]) {
159 regfield = if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN];
160 ret = regmap_field_write(regfield,
161 if_phy->rmii_clock_external);
162 }
163
164 return 0;
165
166 unsupported:
167 dev_warn(dev, "port%u: unsupported mode: \"%s\"\n",
168 if_phy->id, phy_modes(submode));
169 return -EINVAL;
170 }
171
172 static const
173 struct reg_field phy_gmii_sel_fields_am33xx[][PHY_GMII_SEL_LAST] = {
174 {
175 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 0, 1),
176 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 4, 4),
177 [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 6, 6),
178 },
179 {
180 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x650, 2, 3),
181 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x650, 5, 5),
182 [PHY_GMII_SEL_RMII_IO_CLK_EN] = REG_FIELD(0x650, 7, 7),
183 },
184 };
185
186 static const
187 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am33xx = {
188 .num_ports = 2,
189 .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) |
190 BIT(PHY_GMII_SEL_RMII_IO_CLK_EN),
191 .regfields = phy_gmii_sel_fields_am33xx,
192 };
193
194 static const
195 struct reg_field phy_gmii_sel_fields_dra7[][PHY_GMII_SEL_LAST] = {
196 {
197 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 0, 1),
198 },
199 {
200 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x554, 4, 5),
201 },
202 };
203
204 static const
205 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dra7 = {
206 .num_ports = 2,
207 .regfields = phy_gmii_sel_fields_dra7,
208 };
209
210 static const
211 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_dm814 = {
212 .num_ports = 2,
213 .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE),
214 .regfields = phy_gmii_sel_fields_am33xx,
215 };
216
217 static const
218 struct reg_field phy_gmii_sel_fields_am654[][PHY_GMII_SEL_LAST] = {
219 {
220 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x0, 0, 2),
221 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x0, 4, 4),
222 }, {
223 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x4, 0, 2),
224 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x4, 4, 4),
225 }, {
226 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x8, 0, 2),
227 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x8, 4, 4),
228 }, {
229 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0xC, 0, 2),
230 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0xC, 4, 4),
231 }, {
232 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x10, 0, 2),
233 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x10, 4, 4),
234 }, {
235 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x14, 0, 2),
236 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x14, 4, 4),
237 }, {
238 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x18, 0, 2),
239 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x18, 4, 4),
240 }, {
241 [PHY_GMII_SEL_PORT_MODE] = REG_FIELD(0x1C, 0, 2),
242 [PHY_GMII_SEL_RGMII_ID_MODE] = REG_FIELD(0x1C, 4, 4),
243 },
244 };
245
246 static const
247 struct phy_gmii_sel_soc_data phy_gmii_sel_soc_am654 = {
248 .use_of_data = true,
249 .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) |
250 BIT(PHY_GMII_SEL_FIXED_TX_DELAY),
251 .regfields = phy_gmii_sel_fields_am654,
252 };
253
254 static const
255 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw5g_soc_j7200 = {
256 .use_of_data = true,
257 .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) |
258 BIT(PHY_GMII_SEL_FIXED_TX_DELAY),
259 .regfields = phy_gmii_sel_fields_am654,
260 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) |
261 BIT(PHY_INTERFACE_MODE_USXGMII),
262 .num_ports = 4,
263 .num_qsgmii_main_ports = 1,
264 };
265
266 static const
267 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j721e = {
268 .use_of_data = true,
269 .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) |
270 BIT(PHY_GMII_SEL_FIXED_TX_DELAY),
271 .regfields = phy_gmii_sel_fields_am654,
272 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII),
273 .num_ports = 8,
274 .num_qsgmii_main_ports = 2,
275 };
276
277 static const
278 struct phy_gmii_sel_soc_data phy_gmii_sel_cpsw9g_soc_j784s4 = {
279 .use_of_data = true,
280 .features = BIT(PHY_GMII_SEL_RGMII_ID_MODE) |
281 BIT(PHY_GMII_SEL_FIXED_TX_DELAY),
282 .regfields = phy_gmii_sel_fields_am654,
283 .extra_modes = BIT(PHY_INTERFACE_MODE_QSGMII) | BIT(PHY_INTERFACE_MODE_SGMII) |
284 BIT(PHY_INTERFACE_MODE_USXGMII),
285 .num_ports = 8,
286 .num_qsgmii_main_ports = 2,
287 };
288
289 static const struct of_device_id phy_gmii_sel_id_table[] = {
290 {
291 .compatible = "ti,am3352-phy-gmii-sel",
292 .data = &phy_gmii_sel_soc_am33xx,
293 },
294 {
295 .compatible = "ti,dra7xx-phy-gmii-sel",
296 .data = &phy_gmii_sel_soc_dra7,
297 },
298 {
299 .compatible = "ti,am43xx-phy-gmii-sel",
300 .data = &phy_gmii_sel_soc_am33xx,
301 },
302 {
303 .compatible = "ti,dm814-phy-gmii-sel",
304 .data = &phy_gmii_sel_soc_dm814,
305 },
306 {
307 .compatible = "ti,am654-phy-gmii-sel",
308 .data = &phy_gmii_sel_soc_am654,
309 },
310 {
311 .compatible = "ti,j7200-cpsw5g-phy-gmii-sel",
312 .data = &phy_gmii_sel_cpsw5g_soc_j7200,
313 },
314 {
315 .compatible = "ti,j721e-cpsw9g-phy-gmii-sel",
316 .data = &phy_gmii_sel_cpsw9g_soc_j721e,
317 },
318 {
319 .compatible = "ti,j784s4-cpsw9g-phy-gmii-sel",
320 .data = &phy_gmii_sel_cpsw9g_soc_j784s4,
321 },
322 {}
323 };
324 MODULE_DEVICE_TABLE(of, phy_gmii_sel_id_table);
325
326 static const struct phy_ops phy_gmii_sel_ops = {
327 .set_mode = phy_gmii_sel_mode,
328 .owner = THIS_MODULE,
329 };
330
phy_gmii_sel_of_xlate(struct device * dev,const struct of_phandle_args * args)331 static struct phy *phy_gmii_sel_of_xlate(struct device *dev,
332 const struct of_phandle_args *args)
333 {
334 struct phy_gmii_sel_priv *priv = dev_get_drvdata(dev);
335 int phy_id = args->args[0];
336
337 if (args->args_count < 1)
338 return ERR_PTR(-EINVAL);
339 if (!priv || !priv->if_phys)
340 return ERR_PTR(-ENODEV);
341 if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN) &&
342 args->args_count < 2)
343 return ERR_PTR(-EINVAL);
344 if (phy_id > priv->num_ports)
345 return ERR_PTR(-EINVAL);
346 if (phy_id != priv->if_phys[phy_id - 1].id)
347 return ERR_PTR(-EINVAL);
348
349 phy_id--;
350 if (priv->soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN))
351 priv->if_phys[phy_id].rmii_clock_external = args->args[1];
352 dev_dbg(dev, "%s id:%u ext:%d\n", __func__,
353 priv->if_phys[phy_id].id, args->args[1]);
354
355 return priv->if_phys[phy_id].if_phy;
356 }
357
phy_gmii_init_phy(struct phy_gmii_sel_priv * priv,int port,struct phy_gmii_sel_phy_priv * if_phy)358 static int phy_gmii_init_phy(struct phy_gmii_sel_priv *priv, int port,
359 struct phy_gmii_sel_phy_priv *if_phy)
360 {
361 const struct phy_gmii_sel_soc_data *soc_data = priv->soc_data;
362 struct device *dev = priv->dev;
363 const struct reg_field *fields;
364 struct regmap_field *regfield;
365 struct reg_field field;
366 int ret;
367
368 if_phy->id = port;
369 if_phy->priv = priv;
370
371 fields = soc_data->regfields[port - 1];
372 field = *fields++;
373 field.reg += priv->reg_offset;
374 dev_dbg(dev, "%s field %x %d %d\n", __func__,
375 field.reg, field.msb, field.lsb);
376
377 regfield = devm_regmap_field_alloc(dev, priv->regmap, field);
378 if (IS_ERR(regfield))
379 return PTR_ERR(regfield);
380 if_phy->fields[PHY_GMII_SEL_PORT_MODE] = regfield;
381
382 field = *fields++;
383 field.reg += priv->reg_offset;
384 if (soc_data->features & BIT(PHY_GMII_SEL_RGMII_ID_MODE)) {
385 regfield = devm_regmap_field_alloc(dev,
386 priv->regmap,
387 field);
388 if (IS_ERR(regfield))
389 return PTR_ERR(regfield);
390 if_phy->fields[PHY_GMII_SEL_RGMII_ID_MODE] = regfield;
391 dev_dbg(dev, "%s field %x %d %d\n", __func__,
392 field.reg, field.msb, field.lsb);
393 }
394
395 field = *fields;
396 field.reg += priv->reg_offset;
397 if (soc_data->features & BIT(PHY_GMII_SEL_RMII_IO_CLK_EN)) {
398 regfield = devm_regmap_field_alloc(dev,
399 priv->regmap,
400 field);
401 if (IS_ERR(regfield))
402 return PTR_ERR(regfield);
403 if_phy->fields[PHY_GMII_SEL_RMII_IO_CLK_EN] = regfield;
404 dev_dbg(dev, "%s field %x %d %d\n", __func__,
405 field.reg, field.msb, field.lsb);
406 }
407
408 if_phy->if_phy = devm_phy_create(dev,
409 priv->dev->of_node,
410 &phy_gmii_sel_ops);
411 if (IS_ERR(if_phy->if_phy)) {
412 ret = PTR_ERR(if_phy->if_phy);
413 dev_err(dev, "Failed to create phy%d %d\n", port, ret);
414 return ret;
415 }
416 phy_set_drvdata(if_phy->if_phy, if_phy);
417
418 return 0;
419 }
420
phy_gmii_sel_init_ports(struct phy_gmii_sel_priv * priv)421 static int phy_gmii_sel_init_ports(struct phy_gmii_sel_priv *priv)
422 {
423 const struct phy_gmii_sel_soc_data *soc_data = priv->soc_data;
424 struct phy_gmii_sel_phy_priv *if_phys;
425 struct device *dev = priv->dev;
426 int i, ret;
427
428 if (soc_data->use_of_data) {
429 const __be32 *offset;
430 u64 size;
431
432 offset = of_get_address(dev->of_node, 0, &size, NULL);
433 if (!offset)
434 return -EINVAL;
435 priv->num_ports = size / sizeof(u32);
436 if (!priv->num_ports)
437 return -EINVAL;
438 if (!priv->no_offset)
439 priv->reg_offset = __be32_to_cpu(*offset);
440 }
441
442 if_phys = devm_kcalloc(dev, priv->num_ports,
443 sizeof(*if_phys), GFP_KERNEL);
444 if (!if_phys)
445 return -ENOMEM;
446 dev_dbg(dev, "%s %d\n", __func__, priv->num_ports);
447
448 for (i = 0; i < priv->num_ports; i++) {
449 ret = phy_gmii_init_phy(priv, i + 1, &if_phys[i]);
450 if (ret)
451 return ret;
452 }
453
454 priv->if_phys = if_phys;
455 return 0;
456 }
457
458 static const struct regmap_config phy_gmii_sel_regmap_cfg = {
459 .reg_bits = 32,
460 .val_bits = 32,
461 .reg_stride = 4,
462 };
463
phy_gmii_sel_probe(struct platform_device * pdev)464 static int phy_gmii_sel_probe(struct platform_device *pdev)
465 {
466 struct device *dev = &pdev->dev;
467 const struct phy_gmii_sel_soc_data *soc_data;
468 struct device_node *node = dev->of_node;
469 const struct of_device_id *of_id;
470 struct phy_gmii_sel_priv *priv;
471 u32 main_ports = 1;
472 int ret;
473 u32 i;
474
475 of_id = of_match_node(phy_gmii_sel_id_table, pdev->dev.of_node);
476 if (!of_id)
477 return -EINVAL;
478
479 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
480 if (!priv)
481 return -ENOMEM;
482
483 priv->dev = &pdev->dev;
484 priv->soc_data = of_id->data;
485 soc_data = priv->soc_data;
486 priv->num_ports = priv->soc_data->num_ports;
487 priv->qsgmii_main_ports = 0;
488
489 /*
490 * Based on the compatible, try to read the appropriate number of
491 * QSGMII main ports from the "ti,qsgmii-main-ports" property from
492 * the device-tree node.
493 */
494 for (i = 0; i < soc_data->num_qsgmii_main_ports; i++) {
495 of_property_read_u32_index(node, "ti,qsgmii-main-ports", i, &main_ports);
496 /*
497 * Ensure that main_ports is within bounds.
498 */
499 if (main_ports < 1 || main_ports > soc_data->num_ports) {
500 dev_err(dev, "Invalid qsgmii main port provided\n");
501 return -EINVAL;
502 }
503 priv->qsgmii_main_ports |= PHY_GMII_PORT(main_ports);
504 }
505
506 priv->regmap = syscon_node_to_regmap(node->parent);
507 if (IS_ERR(priv->regmap)) {
508 void __iomem *base;
509
510 base = devm_platform_ioremap_resource(pdev, 0);
511 if (IS_ERR(base))
512 return dev_err_probe(dev, PTR_ERR(base),
513 "failed to get base memory resource\n");
514
515 priv->regmap = regmap_init_mmio(dev, base, &phy_gmii_sel_regmap_cfg);
516 if (IS_ERR(priv->regmap))
517 return dev_err_probe(dev, PTR_ERR(priv->regmap),
518 "Failed to get syscon\n");
519 priv->no_offset = true;
520 }
521
522 ret = phy_gmii_sel_init_ports(priv);
523 if (ret)
524 return ret;
525
526 dev_set_drvdata(&pdev->dev, priv);
527
528 priv->phy_provider =
529 devm_of_phy_provider_register(dev,
530 phy_gmii_sel_of_xlate);
531 if (IS_ERR(priv->phy_provider))
532 return dev_err_probe(dev, PTR_ERR(priv->phy_provider),
533 "Failed to create phy provider\n");
534
535 return 0;
536 }
537
phy_gmii_sel_resume_noirq(struct device * dev)538 static int phy_gmii_sel_resume_noirq(struct device *dev)
539 {
540 struct phy_gmii_sel_priv *priv = dev_get_drvdata(dev);
541 struct phy_gmii_sel_phy_priv *if_phys = priv->if_phys;
542 int ret, i;
543
544 for (i = 0; i < priv->num_ports; i++) {
545 if (if_phys[i].phy_if_mode) {
546 ret = phy_gmii_sel_mode(if_phys[i].if_phy,
547 PHY_MODE_ETHERNET, if_phys[i].phy_if_mode);
548 if (ret) {
549 dev_err(dev, "port%u: restore mode fail %d\n",
550 if_phys[i].if_phy->id, ret);
551 return ret;
552 }
553 }
554 }
555
556 return 0;
557 }
558
559 static DEFINE_NOIRQ_DEV_PM_OPS(phy_gmii_sel_pm_ops, NULL, phy_gmii_sel_resume_noirq);
560
561 static struct platform_driver phy_gmii_sel_driver = {
562 .probe = phy_gmii_sel_probe,
563 .driver = {
564 .name = "phy-gmii-sel",
565 .of_match_table = phy_gmii_sel_id_table,
566 .pm = pm_sleep_ptr(&phy_gmii_sel_pm_ops),
567 },
568 };
569 module_platform_driver(phy_gmii_sel_driver);
570
571 MODULE_LICENSE("GPL v2");
572 MODULE_AUTHOR("Grygorii Strashko <grygorii.strashko@ti.com>");
573 MODULE_DESCRIPTION("TI CPSW Port's PHY Interface Mode selection Driver");
574