1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 #include "qla_gbl.h" 8 9 #include <linux/delay.h> 10 #include <linux/slab.h> 11 #include <linux/vmalloc.h> 12 13 #include "qla_devtbl.h" 14 15 #ifdef CONFIG_SPARC 16 #include <asm/prom.h> 17 #endif 18 19 #include "qla_target.h" 20 21 /* 22 * QLogic ISP2x00 Hardware Support Function Prototypes. 23 */ 24 static int qla2x00_isp_firmware(scsi_qla_host_t *); 25 static int qla2x00_setup_chip(scsi_qla_host_t *); 26 static int qla2x00_fw_ready(scsi_qla_host_t *); 27 static int qla2x00_configure_hba(scsi_qla_host_t *); 28 static int qla2x00_configure_loop(scsi_qla_host_t *); 29 static int qla2x00_configure_local_loop(scsi_qla_host_t *); 30 static int qla2x00_configure_fabric(scsi_qla_host_t *); 31 static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *); 32 static int qla2x00_restart_isp(scsi_qla_host_t *); 33 34 static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *); 35 static int qla84xx_init_chip(scsi_qla_host_t *); 36 static int qla25xx_init_queues(struct qla_hw_data *); 37 static void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, 38 struct event_arg *ea); 39 static void qla24xx_handle_prli_done_event(struct scsi_qla_host *, 40 struct event_arg *); 41 static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *); 42 43 /* SRB Extensions ---------------------------------------------------------- */ 44 45 void 46 qla2x00_sp_timeout(struct timer_list *t) 47 { 48 srb_t *sp = timer_container_of(sp, t, u.iocb_cmd.timer); 49 struct srb_iocb *iocb; 50 scsi_qla_host_t *vha = sp->vha; 51 52 WARN_ON(irqs_disabled()); 53 iocb = &sp->u.iocb_cmd; 54 iocb->timeout(sp); 55 56 /* ref: TMR */ 57 kref_put(&sp->cmd_kref, qla2x00_sp_release); 58 59 if (vha && qla2x00_isp_reg_stat(vha->hw)) { 60 ql_log(ql_log_info, vha, 0x9008, 61 "PCI/Register disconnect.\n"); 62 qla_pci_set_eeh_busy(vha); 63 } 64 } 65 66 void qla2x00_sp_free(srb_t *sp) 67 { 68 struct srb_iocb *iocb = &sp->u.iocb_cmd; 69 70 timer_delete(&iocb->timer); 71 qla2x00_rel_sp(sp); 72 } 73 74 void qla2xxx_rel_done_warning(srb_t *sp, int res) 75 { 76 WARN_ONCE(1, "Calling done() of an already freed srb %p object\n", sp); 77 } 78 79 void qla2xxx_rel_free_warning(srb_t *sp) 80 { 81 WARN_ONCE(1, "Calling free() of an already freed srb %p object\n", sp); 82 } 83 84 /* Asynchronous Login/Logout Routines -------------------------------------- */ 85 86 unsigned long 87 qla2x00_get_async_timeout(struct scsi_qla_host *vha) 88 { 89 unsigned long tmo; 90 struct qla_hw_data *ha = vha->hw; 91 92 /* Firmware should use switch negotiated r_a_tov for timeout. */ 93 tmo = ha->r_a_tov / 10 * 2; 94 if (IS_QLAFX00(ha)) { 95 tmo = FX00_DEF_RATOV * 2; 96 } else if (!IS_FWI2_CAPABLE(ha)) { 97 /* 98 * Except for earlier ISPs where the timeout is seeded from the 99 * initialization control block. 100 */ 101 tmo = ha->login_timeout; 102 } 103 return tmo; 104 } 105 106 static void qla24xx_abort_iocb_timeout(void *data) 107 { 108 srb_t *sp = data; 109 struct srb_iocb *abt = &sp->u.iocb_cmd; 110 struct qla_qpair *qpair = sp->qpair; 111 u32 handle; 112 unsigned long flags; 113 int sp_found = 0, cmdsp_found = 0; 114 115 if (sp->cmd_sp) 116 ql_dbg(ql_dbg_async, sp->vha, 0x507c, 117 "Abort timeout - cmd hdl=%x, cmd type=%x hdl=%x, type=%x\n", 118 sp->cmd_sp->handle, sp->cmd_sp->type, 119 sp->handle, sp->type); 120 else 121 ql_dbg(ql_dbg_async, sp->vha, 0x507c, 122 "Abort timeout 2 - hdl=%x, type=%x\n", 123 sp->handle, sp->type); 124 125 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 126 for (handle = 1; handle < qpair->req->num_outstanding_cmds; handle++) { 127 if (sp->cmd_sp && (qpair->req->outstanding_cmds[handle] == 128 sp->cmd_sp)) { 129 qpair->req->outstanding_cmds[handle] = NULL; 130 cmdsp_found = 1; 131 qla_put_fw_resources(qpair, &sp->cmd_sp->iores); 132 } 133 134 /* removing the abort */ 135 if (qpair->req->outstanding_cmds[handle] == sp) { 136 qpair->req->outstanding_cmds[handle] = NULL; 137 sp_found = 1; 138 qla_put_fw_resources(qpair, &sp->iores); 139 break; 140 } 141 } 142 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 143 144 if (cmdsp_found && sp->cmd_sp) { 145 /* 146 * This done function should take care of 147 * original command ref: INIT 148 */ 149 sp->cmd_sp->done(sp->cmd_sp, QLA_OS_TIMER_EXPIRED); 150 } 151 152 if (sp_found) { 153 abt->u.abt.comp_status = cpu_to_le16(CS_TIMEOUT); 154 sp->done(sp, QLA_OS_TIMER_EXPIRED); 155 } 156 } 157 158 static void qla24xx_abort_sp_done(srb_t *sp, int res) 159 { 160 struct srb_iocb *abt = &sp->u.iocb_cmd; 161 srb_t *orig_sp = sp->cmd_sp; 162 163 if (orig_sp) 164 qla_wait_nvme_release_cmd_kref(orig_sp); 165 166 if (sp->flags & SRB_WAKEUP_ON_COMP) 167 complete(&abt->u.abt.comp); 168 else 169 /* ref: INIT */ 170 kref_put(&sp->cmd_kref, qla2x00_sp_release); 171 } 172 173 int qla24xx_async_abort_cmd(srb_t *cmd_sp, bool wait) 174 { 175 scsi_qla_host_t *vha = cmd_sp->vha; 176 struct srb_iocb *abt_iocb; 177 srb_t *sp; 178 int rval = QLA_FUNCTION_FAILED; 179 180 /* ref: INIT for ABTS command */ 181 sp = qla2xxx_get_qpair_sp(cmd_sp->vha, cmd_sp->qpair, cmd_sp->fcport, 182 GFP_ATOMIC); 183 if (!sp) 184 return QLA_MEMORY_ALLOC_FAILED; 185 186 qla_vha_mark_busy(vha); 187 abt_iocb = &sp->u.iocb_cmd; 188 sp->type = SRB_ABT_CMD; 189 sp->name = "abort"; 190 sp->qpair = cmd_sp->qpair; 191 sp->cmd_sp = cmd_sp; 192 if (wait) 193 sp->flags = SRB_WAKEUP_ON_COMP; 194 195 init_completion(&abt_iocb->u.abt.comp); 196 /* FW can send 2 x ABTS's timeout/20s */ 197 qla2x00_init_async_sp(sp, 42, qla24xx_abort_sp_done); 198 sp->u.iocb_cmd.timeout = qla24xx_abort_iocb_timeout; 199 200 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle; 201 abt_iocb->u.abt.req_que_no = cpu_to_le16(cmd_sp->qpair->req->id); 202 203 ql_dbg(ql_dbg_async, vha, 0x507c, 204 "Abort command issued - hdl=%x, type=%x\n", cmd_sp->handle, 205 cmd_sp->type); 206 207 rval = qla2x00_start_sp(sp); 208 if (rval != QLA_SUCCESS) { 209 /* ref: INIT */ 210 kref_put(&sp->cmd_kref, qla2x00_sp_release); 211 return rval; 212 } 213 214 if (wait) { 215 wait_for_completion(&abt_iocb->u.abt.comp); 216 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ? 217 QLA_SUCCESS : QLA_ERR_FROM_FW; 218 /* ref: INIT */ 219 kref_put(&sp->cmd_kref, qla2x00_sp_release); 220 } 221 222 return rval; 223 } 224 225 void 226 qla2x00_async_iocb_timeout(void *data) 227 { 228 srb_t *sp = data; 229 fc_port_t *fcport = sp->fcport; 230 struct srb_iocb *lio = &sp->u.iocb_cmd; 231 int rc, h; 232 unsigned long flags; 233 234 if (fcport) { 235 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071, 236 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n", 237 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name); 238 239 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 240 } else { 241 pr_info("Async-%s timeout - hdl=%x.\n", 242 sp->name, sp->handle); 243 } 244 245 switch (sp->type) { 246 case SRB_LOGIN_CMD: 247 rc = qla24xx_async_abort_cmd(sp, false); 248 if (rc) { 249 /* Retry as needed. */ 250 lio->u.logio.data[0] = MBS_COMMAND_ERROR; 251 lio->u.logio.data[1] = 252 lio->u.logio.flags & SRB_LOGIN_RETRIED ? 253 QLA_LOGIO_LOGIN_RETRIED : 0; 254 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 255 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; 256 h++) { 257 if (sp->qpair->req->outstanding_cmds[h] == 258 sp) { 259 sp->qpair->req->outstanding_cmds[h] = 260 NULL; 261 break; 262 } 263 } 264 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 265 sp->done(sp, QLA_FUNCTION_TIMEOUT); 266 } 267 break; 268 case SRB_LOGOUT_CMD: 269 case SRB_CT_PTHRU_CMD: 270 case SRB_MB_IOCB: 271 case SRB_NACK_PLOGI: 272 case SRB_NACK_PRLI: 273 case SRB_NACK_LOGO: 274 case SRB_CTRL_VP: 275 default: 276 rc = qla24xx_async_abort_cmd(sp, false); 277 if (rc) { 278 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 279 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; 280 h++) { 281 if (sp->qpair->req->outstanding_cmds[h] == 282 sp) { 283 sp->qpair->req->outstanding_cmds[h] = 284 NULL; 285 break; 286 } 287 } 288 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 289 sp->done(sp, QLA_FUNCTION_TIMEOUT); 290 } 291 break; 292 } 293 } 294 295 static void qla2x00_async_login_sp_done(srb_t *sp, int res) 296 { 297 struct scsi_qla_host *vha = sp->vha; 298 struct srb_iocb *lio = &sp->u.iocb_cmd; 299 struct event_arg ea; 300 301 ql_dbg(ql_dbg_disc, vha, 0x20dd, 302 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res); 303 304 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 305 306 if (!test_bit(UNLOADING, &vha->dpc_flags)) { 307 memset(&ea, 0, sizeof(ea)); 308 ea.fcport = sp->fcport; 309 ea.data[0] = lio->u.logio.data[0]; 310 ea.data[1] = lio->u.logio.data[1]; 311 ea.iop[0] = lio->u.logio.iop[0]; 312 ea.iop[1] = lio->u.logio.iop[1]; 313 ea.sp = sp; 314 if (res) 315 ea.data[0] = MBS_COMMAND_ERROR; 316 qla24xx_handle_plogi_done_event(vha, &ea); 317 } 318 319 /* ref: INIT */ 320 kref_put(&sp->cmd_kref, qla2x00_sp_release); 321 } 322 323 int 324 qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport, 325 uint16_t *data) 326 { 327 srb_t *sp; 328 struct srb_iocb *lio; 329 int rval = QLA_FUNCTION_FAILED; 330 331 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) || 332 fcport->loop_id == FC_NO_LOOP_ID) { 333 ql_log(ql_log_warn, vha, 0xffff, 334 "%s: %8phC - not sending command.\n", 335 __func__, fcport->port_name); 336 return rval; 337 } 338 339 /* ref: INIT */ 340 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 341 if (!sp) 342 goto done; 343 344 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND); 345 fcport->flags |= FCF_ASYNC_SENT; 346 fcport->logout_completed = 0; 347 348 sp->type = SRB_LOGIN_CMD; 349 sp->name = "login"; 350 sp->gen1 = fcport->rscn_gen; 351 sp->gen2 = fcport->login_gen; 352 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2, 353 qla2x00_async_login_sp_done); 354 355 lio = &sp->u.iocb_cmd; 356 if (N2N_TOPO(fcport->vha->hw) && fcport_is_bigger(fcport)) { 357 lio->u.logio.flags |= SRB_LOGIN_PRLI_ONLY; 358 } else { 359 if (vha->hw->flags.edif_enabled && 360 DBELL_ACTIVE(vha)) { 361 lio->u.logio.flags |= 362 (SRB_LOGIN_FCSP | SRB_LOGIN_SKIP_PRLI); 363 } else { 364 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI; 365 } 366 } 367 368 if (NVME_TARGET(vha->hw, fcport)) 369 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI; 370 371 rval = qla2x00_start_sp(sp); 372 373 ql_dbg(ql_dbg_disc, vha, 0x2072, 374 "Async-login - %8phC hdl=%x, loopid=%x portid=%06x retries=%d %s.\n", 375 fcport->port_name, sp->handle, fcport->loop_id, 376 fcport->d_id.b24, fcport->login_retry, 377 lio->u.logio.flags & SRB_LOGIN_FCSP ? "FCSP" : ""); 378 379 if (rval != QLA_SUCCESS) { 380 fcport->flags |= FCF_LOGIN_NEEDED; 381 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 382 goto done_free_sp; 383 } 384 385 return rval; 386 387 done_free_sp: 388 /* ref: INIT */ 389 kref_put(&sp->cmd_kref, qla2x00_sp_release); 390 fcport->flags &= ~FCF_ASYNC_SENT; 391 done: 392 fcport->flags &= ~FCF_ASYNC_ACTIVE; 393 394 /* 395 * async login failed. Could be due to iocb/exchange resource 396 * being low. Set state DELETED for re-login process to start again. 397 */ 398 qla2x00_set_fcport_disc_state(fcport, DSC_DELETED); 399 return rval; 400 } 401 402 static void qla2x00_async_logout_sp_done(srb_t *sp, int res) 403 { 404 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 405 sp->fcport->login_gen++; 406 qlt_logo_completion_handler(sp->fcport, sp->u.iocb_cmd.u.logio.data[0]); 407 /* ref: INIT */ 408 kref_put(&sp->cmd_kref, qla2x00_sp_release); 409 } 410 411 int 412 qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport) 413 { 414 srb_t *sp; 415 int rval = QLA_FUNCTION_FAILED; 416 417 fcport->flags |= FCF_ASYNC_SENT; 418 /* ref: INIT */ 419 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 420 if (!sp) 421 goto done; 422 423 sp->type = SRB_LOGOUT_CMD; 424 sp->name = "logout"; 425 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2, 426 qla2x00_async_logout_sp_done); 427 428 ql_dbg(ql_dbg_disc, vha, 0x2070, 429 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC explicit %d.\n", 430 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 431 fcport->d_id.b.area, fcport->d_id.b.al_pa, 432 fcport->port_name, fcport->explicit_logout); 433 434 rval = qla2x00_start_sp(sp); 435 if (rval != QLA_SUCCESS) 436 goto done_free_sp; 437 return rval; 438 439 done_free_sp: 440 /* ref: INIT */ 441 kref_put(&sp->cmd_kref, qla2x00_sp_release); 442 done: 443 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 444 return rval; 445 } 446 447 void 448 qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport, 449 uint16_t *data) 450 { 451 fcport->flags &= ~FCF_ASYNC_ACTIVE; 452 /* Don't re-login in target mode */ 453 if (!fcport->tgt_session) 454 qla2x00_mark_device_lost(vha, fcport, 1); 455 qlt_logo_completion_handler(fcport, data[0]); 456 } 457 458 static void qla2x00_async_prlo_sp_done(srb_t *sp, int res) 459 { 460 struct srb_iocb *lio = &sp->u.iocb_cmd; 461 struct scsi_qla_host *vha = sp->vha; 462 463 sp->fcport->flags &= ~FCF_ASYNC_ACTIVE; 464 if (!test_bit(UNLOADING, &vha->dpc_flags)) 465 qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport, 466 lio->u.logio.data); 467 /* ref: INIT */ 468 kref_put(&sp->cmd_kref, qla2x00_sp_release); 469 } 470 471 int 472 qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport) 473 { 474 srb_t *sp; 475 int rval; 476 477 rval = QLA_FUNCTION_FAILED; 478 /* ref: INIT */ 479 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 480 if (!sp) 481 goto done; 482 483 sp->type = SRB_PRLO_CMD; 484 sp->name = "prlo"; 485 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2, 486 qla2x00_async_prlo_sp_done); 487 488 ql_dbg(ql_dbg_disc, vha, 0x2070, 489 "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n", 490 sp->handle, fcport->loop_id, fcport->d_id.b.domain, 491 fcport->d_id.b.area, fcport->d_id.b.al_pa); 492 493 rval = qla2x00_start_sp(sp); 494 if (rval != QLA_SUCCESS) 495 goto done_free_sp; 496 497 return rval; 498 499 done_free_sp: 500 /* ref: INIT */ 501 kref_put(&sp->cmd_kref, qla2x00_sp_release); 502 done: 503 fcport->flags &= ~FCF_ASYNC_ACTIVE; 504 return rval; 505 } 506 507 static 508 void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea) 509 { 510 struct fc_port *fcport = ea->fcport; 511 unsigned long flags; 512 513 ql_dbg(ql_dbg_disc, vha, 0x20d2, 514 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n", 515 __func__, fcport->port_name, fcport->disc_state, 516 fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2, 517 fcport->rscn_gen, ea->sp->gen1, fcport->loop_id); 518 519 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 520 ea->data[0]); 521 522 if (ea->data[0] != MBS_COMMAND_COMPLETE) { 523 ql_dbg(ql_dbg_disc, vha, 0x2066, 524 "%s %8phC: adisc fail: post delete\n", 525 __func__, ea->fcport->port_name); 526 527 spin_lock_irqsave(&vha->work_lock, flags); 528 /* deleted = 0 & logout_on_delete = force fw cleanup */ 529 if (fcport->deleted == QLA_SESS_DELETED) 530 fcport->deleted = 0; 531 532 fcport->logout_on_delete = 1; 533 spin_unlock_irqrestore(&vha->work_lock, flags); 534 535 qlt_schedule_sess_for_deletion(ea->fcport); 536 return; 537 } 538 539 if (ea->fcport->disc_state == DSC_DELETE_PEND) 540 return; 541 542 if (ea->sp->gen2 != ea->fcport->login_gen) { 543 /* target side must have changed it. */ 544 ql_dbg(ql_dbg_disc, vha, 0x20d3, 545 "%s %8phC generation changed\n", 546 __func__, ea->fcport->port_name); 547 return; 548 } else if (ea->sp->gen1 != ea->fcport->rscn_gen) { 549 qla_rscn_replay(fcport); 550 qlt_schedule_sess_for_deletion(fcport); 551 return; 552 } 553 554 __qla24xx_handle_gpdb_event(vha, ea); 555 } 556 557 static int qla_post_els_plogi_work(struct scsi_qla_host *vha, fc_port_t *fcport) 558 { 559 struct qla_work_evt *e; 560 561 e = qla2x00_alloc_work(vha, QLA_EVT_ELS_PLOGI); 562 if (!e) 563 return QLA_FUNCTION_FAILED; 564 565 e->u.fcport.fcport = fcport; 566 fcport->flags |= FCF_ASYNC_ACTIVE; 567 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND); 568 return qla2x00_post_work(vha, e); 569 } 570 571 static void qla2x00_async_adisc_sp_done(srb_t *sp, int res) 572 { 573 struct scsi_qla_host *vha = sp->vha; 574 struct event_arg ea; 575 struct srb_iocb *lio = &sp->u.iocb_cmd; 576 577 ql_dbg(ql_dbg_disc, vha, 0x2066, 578 "Async done-%s res %x %8phC\n", 579 sp->name, res, sp->fcport->port_name); 580 581 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 582 583 memset(&ea, 0, sizeof(ea)); 584 ea.rc = res; 585 ea.data[0] = lio->u.logio.data[0]; 586 ea.data[1] = lio->u.logio.data[1]; 587 ea.iop[0] = lio->u.logio.iop[0]; 588 ea.iop[1] = lio->u.logio.iop[1]; 589 ea.fcport = sp->fcport; 590 ea.sp = sp; 591 if (res) 592 ea.data[0] = MBS_COMMAND_ERROR; 593 594 qla24xx_handle_adisc_event(vha, &ea); 595 /* ref: INIT */ 596 kref_put(&sp->cmd_kref, qla2x00_sp_release); 597 } 598 599 int 600 qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport, 601 uint16_t *data) 602 { 603 srb_t *sp; 604 struct srb_iocb *lio; 605 int rval = QLA_FUNCTION_FAILED; 606 607 if (IS_SESSION_DELETED(fcport)) { 608 ql_log(ql_log_warn, vha, 0xffff, 609 "%s: %8phC is being delete - not sending command.\n", 610 __func__, fcport->port_name); 611 fcport->flags &= ~FCF_ASYNC_ACTIVE; 612 return rval; 613 } 614 615 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT)) 616 return rval; 617 618 fcport->flags |= FCF_ASYNC_SENT; 619 /* ref: INIT */ 620 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 621 if (!sp) 622 goto done; 623 624 sp->type = SRB_ADISC_CMD; 625 sp->name = "adisc"; 626 sp->gen1 = fcport->rscn_gen; 627 sp->gen2 = fcport->login_gen; 628 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2, 629 qla2x00_async_adisc_sp_done); 630 631 if (data[1] & QLA_LOGIO_LOGIN_RETRIED) { 632 lio = &sp->u.iocb_cmd; 633 lio->u.logio.flags |= SRB_LOGIN_RETRIED; 634 } 635 636 ql_dbg(ql_dbg_disc, vha, 0x206f, 637 "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n", 638 sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name); 639 640 rval = qla2x00_start_sp(sp); 641 if (rval != QLA_SUCCESS) 642 goto done_free_sp; 643 644 return rval; 645 646 done_free_sp: 647 /* ref: INIT */ 648 kref_put(&sp->cmd_kref, qla2x00_sp_release); 649 done: 650 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 651 qla2x00_post_async_adisc_work(vha, fcport, data); 652 return rval; 653 } 654 655 static bool qla2x00_is_reserved_id(scsi_qla_host_t *vha, uint16_t loop_id) 656 { 657 struct qla_hw_data *ha = vha->hw; 658 659 if (IS_FWI2_CAPABLE(ha)) 660 return loop_id > NPH_LAST_HANDLE; 661 662 return (loop_id > ha->max_loop_id && loop_id < SNS_FIRST_LOOP_ID) || 663 loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST; 664 } 665 666 /** 667 * qla2x00_find_new_loop_id - scan through our port list and find a new usable loop ID 668 * @vha: adapter state pointer. 669 * @dev: port structure pointer. 670 * 671 * Returns: 672 * qla2x00 local function return status code. 673 * 674 * Context: 675 * Kernel context. 676 */ 677 static int qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev) 678 { 679 int rval; 680 struct qla_hw_data *ha = vha->hw; 681 unsigned long flags = 0; 682 683 rval = QLA_SUCCESS; 684 685 spin_lock_irqsave(&ha->vport_slock, flags); 686 687 dev->loop_id = find_first_zero_bit(ha->loop_id_map, LOOPID_MAP_SIZE); 688 if (dev->loop_id >= LOOPID_MAP_SIZE || 689 qla2x00_is_reserved_id(vha, dev->loop_id)) { 690 dev->loop_id = FC_NO_LOOP_ID; 691 rval = QLA_FUNCTION_FAILED; 692 } else { 693 set_bit(dev->loop_id, ha->loop_id_map); 694 } 695 spin_unlock_irqrestore(&ha->vport_slock, flags); 696 697 if (rval == QLA_SUCCESS) 698 ql_dbg(ql_dbg_disc, dev->vha, 0x2086, 699 "Assigning new loopid=%x, portid=%x.\n", 700 dev->loop_id, dev->d_id.b24); 701 else 702 ql_log(ql_log_warn, dev->vha, 0x2087, 703 "No loop_id's available, portid=%x.\n", 704 dev->d_id.b24); 705 706 return rval; 707 } 708 709 void qla2x00_clear_loop_id(fc_port_t *fcport) 710 { 711 struct qla_hw_data *ha = fcport->vha->hw; 712 713 if (fcport->loop_id == FC_NO_LOOP_ID || 714 qla2x00_is_reserved_id(fcport->vha, fcport->loop_id)) 715 return; 716 717 clear_bit(fcport->loop_id, ha->loop_id_map); 718 fcport->loop_id = FC_NO_LOOP_ID; 719 } 720 721 static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha, 722 struct event_arg *ea) 723 { 724 fc_port_t *fcport, *conflict_fcport; 725 struct get_name_list_extended *e; 726 u16 i, n, found = 0, loop_id; 727 port_id_t id; 728 u64 wwn; 729 u16 data[2]; 730 u8 current_login_state, nvme_cls; 731 732 fcport = ea->fcport; 733 ql_dbg(ql_dbg_disc, vha, 0xffff, 734 "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d edif %d\n", 735 __func__, fcport->port_name, fcport->disc_state, 736 fcport->fw_login_state, ea->rc, 737 fcport->login_gen, fcport->last_login_gen, 738 fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id, fcport->edif.enable); 739 740 if (fcport->disc_state == DSC_DELETE_PEND) 741 return; 742 743 if (ea->rc) { /* rval */ 744 if (fcport->login_retry == 0) { 745 ql_dbg(ql_dbg_disc, vha, 0x20de, 746 "GNL failed Port login retry %8phN, retry cnt=%d.\n", 747 fcport->port_name, fcport->login_retry); 748 } 749 return; 750 } 751 752 if (fcport->last_rscn_gen != fcport->rscn_gen) { 753 qla_rscn_replay(fcport); 754 qlt_schedule_sess_for_deletion(fcport); 755 return; 756 } else if (fcport->last_login_gen != fcport->login_gen) { 757 ql_dbg(ql_dbg_disc, vha, 0x20e0, 758 "%s %8phC login gen changed\n", 759 __func__, fcport->port_name); 760 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 761 return; 762 } 763 764 n = ea->data[0] / sizeof(struct get_name_list_extended); 765 766 ql_dbg(ql_dbg_disc, vha, 0x20e1, 767 "%s %d %8phC n %d %02x%02x%02x lid %d \n", 768 __func__, __LINE__, fcport->port_name, n, 769 fcport->d_id.b.domain, fcport->d_id.b.area, 770 fcport->d_id.b.al_pa, fcport->loop_id); 771 772 for (i = 0; i < n; i++) { 773 e = &vha->gnl.l[i]; 774 wwn = wwn_to_u64(e->port_name); 775 id.b.domain = e->port_id[2]; 776 id.b.area = e->port_id[1]; 777 id.b.al_pa = e->port_id[0]; 778 id.b.rsvd_1 = 0; 779 780 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE)) 781 continue; 782 783 if (IS_SW_RESV_ADDR(id)) 784 continue; 785 786 found = 1; 787 788 loop_id = le16_to_cpu(e->nport_handle); 789 loop_id = (loop_id & 0x7fff); 790 nvme_cls = e->current_login_state >> 4; 791 current_login_state = e->current_login_state & 0xf; 792 793 if (PRLI_PHASE(nvme_cls)) { 794 current_login_state = nvme_cls; 795 fcport->fc4_type &= ~FS_FC4TYPE_FCP; 796 fcport->fc4_type |= FS_FC4TYPE_NVME; 797 } else if (PRLI_PHASE(current_login_state)) { 798 fcport->fc4_type |= FS_FC4TYPE_FCP; 799 fcport->fc4_type &= ~FS_FC4TYPE_NVME; 800 } 801 802 ql_dbg(ql_dbg_disc, vha, 0x20e2, 803 "%s found %8phC CLS [%x|%x] fc4_type %d ID[%06x|%06x] lid[%d|%d]\n", 804 __func__, fcport->port_name, 805 e->current_login_state, fcport->fw_login_state, 806 fcport->fc4_type, id.b24, fcport->d_id.b24, 807 loop_id, fcport->loop_id); 808 809 switch (fcport->disc_state) { 810 case DSC_DELETE_PEND: 811 case DSC_DELETED: 812 break; 813 default: 814 if ((id.b24 != fcport->d_id.b24 && 815 fcport->d_id.b24 && 816 fcport->loop_id != FC_NO_LOOP_ID) || 817 (fcport->loop_id != FC_NO_LOOP_ID && 818 fcport->loop_id != loop_id)) { 819 ql_dbg(ql_dbg_disc, vha, 0x20e3, 820 "%s %d %8phC post del sess\n", 821 __func__, __LINE__, fcport->port_name); 822 if (fcport->n2n_flag) 823 fcport->d_id.b24 = 0; 824 qlt_schedule_sess_for_deletion(fcport); 825 return; 826 } 827 break; 828 } 829 830 fcport->loop_id = loop_id; 831 if (fcport->n2n_flag) 832 fcport->d_id.b24 = id.b24; 833 834 wwn = wwn_to_u64(fcport->port_name); 835 qlt_find_sess_invalidate_other(vha, wwn, 836 id, loop_id, &conflict_fcport); 837 838 if (conflict_fcport) { 839 /* 840 * Another share fcport share the same loop_id & 841 * nport id. Conflict fcport needs to finish 842 * cleanup before this fcport can proceed to login. 843 */ 844 conflict_fcport->conflict = fcport; 845 fcport->login_pause = 1; 846 } 847 848 switch (vha->hw->current_topology) { 849 default: 850 switch (current_login_state) { 851 case DSC_LS_PRLI_COMP: 852 ql_dbg(ql_dbg_disc, 853 vha, 0x20e4, "%s %d %8phC post gpdb\n", 854 __func__, __LINE__, fcport->port_name); 855 856 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0) 857 fcport->port_type = FCT_INITIATOR; 858 else 859 fcport->port_type = FCT_TARGET; 860 data[0] = data[1] = 0; 861 qla2x00_post_async_adisc_work(vha, fcport, 862 data); 863 break; 864 case DSC_LS_PLOGI_COMP: 865 if (vha->hw->flags.edif_enabled) { 866 /* check to see if App support Secure */ 867 qla24xx_post_gpdb_work(vha, fcport, 0); 868 break; 869 } 870 fallthrough; 871 case DSC_LS_PORT_UNAVAIL: 872 default: 873 if (fcport->loop_id == FC_NO_LOOP_ID) { 874 qla2x00_find_new_loop_id(vha, fcport); 875 fcport->fw_login_state = 876 DSC_LS_PORT_UNAVAIL; 877 } 878 ql_dbg(ql_dbg_disc, vha, 0x20e5, 879 "%s %d %8phC\n", __func__, __LINE__, 880 fcport->port_name); 881 qla24xx_fcport_handle_login(vha, fcport); 882 break; 883 } 884 break; 885 case ISP_CFG_N: 886 fcport->fw_login_state = current_login_state; 887 fcport->d_id = id; 888 switch (current_login_state) { 889 case DSC_LS_PRLI_PEND: 890 /* 891 * In the middle of PRLI. Let it finish. 892 * Allow relogin code to recheck state again 893 * with GNL. Push disc_state back to DELETED 894 * so GNL can go out again 895 */ 896 qla2x00_set_fcport_disc_state(fcport, 897 DSC_DELETED); 898 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 899 break; 900 case DSC_LS_PRLI_COMP: 901 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0) 902 fcport->port_type = FCT_INITIATOR; 903 else 904 fcport->port_type = FCT_TARGET; 905 906 data[0] = data[1] = 0; 907 qla2x00_post_async_adisc_work(vha, fcport, 908 data); 909 break; 910 case DSC_LS_PLOGI_COMP: 911 if (vha->hw->flags.edif_enabled && 912 DBELL_ACTIVE(vha)) { 913 /* check to see if App support secure or not */ 914 qla24xx_post_gpdb_work(vha, fcport, 0); 915 break; 916 } 917 if (fcport_is_bigger(fcport)) { 918 /* local adapter is smaller */ 919 if (fcport->loop_id != FC_NO_LOOP_ID) 920 qla2x00_clear_loop_id(fcport); 921 922 fcport->loop_id = loop_id; 923 qla24xx_fcport_handle_login(vha, 924 fcport); 925 break; 926 } 927 fallthrough; 928 default: 929 if (fcport_is_smaller(fcport)) { 930 /* local adapter is bigger */ 931 if (fcport->loop_id != FC_NO_LOOP_ID) 932 qla2x00_clear_loop_id(fcport); 933 934 fcport->loop_id = loop_id; 935 qla24xx_fcport_handle_login(vha, 936 fcport); 937 } 938 break; 939 } 940 break; 941 } /* switch (ha->current_topology) */ 942 } 943 944 if (!found) { 945 switch (vha->hw->current_topology) { 946 case ISP_CFG_F: 947 case ISP_CFG_FL: 948 for (i = 0; i < n; i++) { 949 e = &vha->gnl.l[i]; 950 id.b.domain = e->port_id[0]; 951 id.b.area = e->port_id[1]; 952 id.b.al_pa = e->port_id[2]; 953 id.b.rsvd_1 = 0; 954 loop_id = le16_to_cpu(e->nport_handle); 955 956 if (fcport->d_id.b24 == id.b24) { 957 conflict_fcport = 958 qla2x00_find_fcport_by_wwpn(vha, 959 e->port_name, 0); 960 if (conflict_fcport) { 961 ql_dbg(ql_dbg_disc + ql_dbg_verbose, 962 vha, 0x20e5, 963 "%s %d %8phC post del sess\n", 964 __func__, __LINE__, 965 conflict_fcport->port_name); 966 qlt_schedule_sess_for_deletion 967 (conflict_fcport); 968 } 969 } 970 /* 971 * FW already picked this loop id for 972 * another fcport 973 */ 974 if (fcport->loop_id == loop_id) 975 fcport->loop_id = FC_NO_LOOP_ID; 976 } 977 qla24xx_fcport_handle_login(vha, fcport); 978 break; 979 case ISP_CFG_N: 980 qla2x00_set_fcport_disc_state(fcport, DSC_DELETED); 981 if (time_after_eq(jiffies, fcport->dm_login_expire)) { 982 if (fcport->n2n_link_reset_cnt < 2) { 983 fcport->n2n_link_reset_cnt++; 984 /* 985 * remote port is not sending PLOGI. 986 * Reset link to kick start his state 987 * machine 988 */ 989 set_bit(N2N_LINK_RESET, 990 &vha->dpc_flags); 991 } else { 992 if (fcport->n2n_chip_reset < 1) { 993 ql_log(ql_log_info, vha, 0x705d, 994 "Chip reset to bring laser down"); 995 set_bit(ISP_ABORT_NEEDED, 996 &vha->dpc_flags); 997 fcport->n2n_chip_reset++; 998 } else { 999 ql_log(ql_log_info, vha, 0x705d, 1000 "Remote port %8ph is not coming back\n", 1001 fcport->port_name); 1002 fcport->scan_state = 0; 1003 } 1004 } 1005 qla2xxx_wake_dpc(vha); 1006 } else { 1007 /* 1008 * report port suppose to do PLOGI. Give him 1009 * more time. FW will catch it. 1010 */ 1011 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1012 } 1013 break; 1014 case ISP_CFG_NL: 1015 qla24xx_fcport_handle_login(vha, fcport); 1016 break; 1017 default: 1018 break; 1019 } 1020 } 1021 } /* gnl_event */ 1022 1023 static void qla24xx_async_gnl_sp_done(srb_t *sp, int res) 1024 { 1025 struct scsi_qla_host *vha = sp->vha; 1026 unsigned long flags; 1027 struct fc_port *fcport = NULL, *tf; 1028 u16 i, n = 0, loop_id; 1029 struct event_arg ea; 1030 struct get_name_list_extended *e; 1031 u64 wwn; 1032 struct list_head h; 1033 bool found = false; 1034 1035 ql_dbg(ql_dbg_disc, vha, 0x20e7, 1036 "Async done-%s res %x mb[1]=%x mb[2]=%x \n", 1037 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1], 1038 sp->u.iocb_cmd.u.mbx.in_mb[2]); 1039 1040 1041 sp->fcport->flags &= ~(FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE); 1042 memset(&ea, 0, sizeof(ea)); 1043 ea.sp = sp; 1044 ea.rc = res; 1045 1046 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >= 1047 sizeof(struct get_name_list_extended)) { 1048 n = sp->u.iocb_cmd.u.mbx.in_mb[1] / 1049 sizeof(struct get_name_list_extended); 1050 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1]; /* amnt xfered */ 1051 } 1052 1053 for (i = 0; i < n; i++) { 1054 e = &vha->gnl.l[i]; 1055 loop_id = le16_to_cpu(e->nport_handle); 1056 /* mask out reserve bit */ 1057 loop_id = (loop_id & 0x7fff); 1058 set_bit(loop_id, vha->hw->loop_id_map); 1059 wwn = wwn_to_u64(e->port_name); 1060 1061 ql_dbg(ql_dbg_disc, vha, 0x20e8, 1062 "%s %8phC %02x:%02x:%02x CLS %x/%x lid %x \n", 1063 __func__, &wwn, e->port_id[2], e->port_id[1], 1064 e->port_id[0], e->current_login_state, e->last_login_state, 1065 (loop_id & 0x7fff)); 1066 } 1067 1068 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1069 1070 INIT_LIST_HEAD(&h); 1071 fcport = tf = NULL; 1072 if (!list_empty(&vha->gnl.fcports)) 1073 list_splice_init(&vha->gnl.fcports, &h); 1074 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1075 1076 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) { 1077 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1078 list_del_init(&fcport->gnl_entry); 1079 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1080 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1081 ea.fcport = fcport; 1082 1083 qla24xx_handle_gnl_done_event(vha, &ea); 1084 } 1085 1086 /* create new fcport if fw has knowledge of new sessions */ 1087 for (i = 0; i < n; i++) { 1088 port_id_t id; 1089 u64 wwnn; 1090 1091 e = &vha->gnl.l[i]; 1092 wwn = wwn_to_u64(e->port_name); 1093 1094 found = false; 1095 list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) { 1096 if (!memcmp((u8 *)&wwn, fcport->port_name, 1097 WWN_SIZE)) { 1098 found = true; 1099 break; 1100 } 1101 } 1102 1103 id.b.domain = e->port_id[2]; 1104 id.b.area = e->port_id[1]; 1105 id.b.al_pa = e->port_id[0]; 1106 id.b.rsvd_1 = 0; 1107 1108 if (!found && wwn && !IS_SW_RESV_ADDR(id)) { 1109 ql_dbg(ql_dbg_disc, vha, 0x2065, 1110 "%s %d %8phC %06x post new sess\n", 1111 __func__, __LINE__, (u8 *)&wwn, id.b24); 1112 wwnn = wwn_to_u64(e->node_name); 1113 qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn, 1114 (u8 *)&wwnn, NULL, 0); 1115 } 1116 } 1117 1118 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1119 vha->gnl.sent = 0; 1120 if (!list_empty(&vha->gnl.fcports)) { 1121 /* retrigger gnl */ 1122 list_for_each_entry_safe(fcport, tf, &vha->gnl.fcports, 1123 gnl_entry) { 1124 list_del_init(&fcport->gnl_entry); 1125 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1126 if (qla24xx_post_gnl_work(vha, fcport) == QLA_SUCCESS) 1127 break; 1128 } 1129 } 1130 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1131 1132 /* ref: INIT */ 1133 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1134 } 1135 1136 int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport) 1137 { 1138 srb_t *sp; 1139 int rval = QLA_FUNCTION_FAILED; 1140 unsigned long flags; 1141 u16 *mb; 1142 1143 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT)) 1144 goto done; 1145 1146 ql_dbg(ql_dbg_disc, vha, 0x20d9, 1147 "Async-gnlist WWPN %8phC \n", fcport->port_name); 1148 1149 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1150 fcport->flags |= FCF_ASYNC_SENT; 1151 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 1152 fcport->last_rscn_gen = fcport->rscn_gen; 1153 fcport->last_login_gen = fcport->login_gen; 1154 1155 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports); 1156 if (vha->gnl.sent) { 1157 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1158 return QLA_SUCCESS; 1159 } 1160 vha->gnl.sent = 1; 1161 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1162 1163 /* ref: INIT */ 1164 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1165 if (!sp) 1166 goto done; 1167 1168 sp->type = SRB_MB_IOCB; 1169 sp->name = "gnlist"; 1170 sp->gen1 = fcport->rscn_gen; 1171 sp->gen2 = fcport->login_gen; 1172 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2, 1173 qla24xx_async_gnl_sp_done); 1174 1175 mb = sp->u.iocb_cmd.u.mbx.out_mb; 1176 mb[0] = MBC_PORT_NODE_NAME_LIST; 1177 mb[1] = BIT_2 | BIT_3; 1178 mb[2] = MSW(vha->gnl.ldma); 1179 mb[3] = LSW(vha->gnl.ldma); 1180 mb[6] = MSW(MSD(vha->gnl.ldma)); 1181 mb[7] = LSW(MSD(vha->gnl.ldma)); 1182 mb[8] = vha->gnl.size; 1183 mb[9] = vha->vp_idx; 1184 1185 ql_dbg(ql_dbg_disc, vha, 0x20da, 1186 "Async-%s - OUT WWPN %8phC hndl %x\n", 1187 sp->name, fcport->port_name, sp->handle); 1188 1189 rval = qla2x00_start_sp(sp); 1190 if (rval != QLA_SUCCESS) 1191 goto done_free_sp; 1192 1193 return rval; 1194 1195 done_free_sp: 1196 /* 1197 * use qla24xx_async_gnl_sp_done to purge all pending gnl request. 1198 * kref_put is call behind the scene. 1199 */ 1200 sp->u.iocb_cmd.u.mbx.in_mb[0] = MBS_COMMAND_ERROR; 1201 qla24xx_async_gnl_sp_done(sp, QLA_COMMAND_ERROR); 1202 fcport->flags &= ~(FCF_ASYNC_SENT); 1203 done: 1204 fcport->flags &= ~(FCF_ASYNC_ACTIVE); 1205 return rval; 1206 } 1207 1208 int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport) 1209 { 1210 struct qla_work_evt *e; 1211 1212 e = qla2x00_alloc_work(vha, QLA_EVT_GNL); 1213 if (!e) 1214 return QLA_FUNCTION_FAILED; 1215 1216 e->u.fcport.fcport = fcport; 1217 fcport->flags |= FCF_ASYNC_ACTIVE; 1218 return qla2x00_post_work(vha, e); 1219 } 1220 1221 static void qla24xx_async_gpdb_sp_done(srb_t *sp, int res) 1222 { 1223 struct scsi_qla_host *vha = sp->vha; 1224 struct qla_hw_data *ha = vha->hw; 1225 fc_port_t *fcport = sp->fcport; 1226 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb; 1227 struct event_arg ea; 1228 1229 ql_dbg(ql_dbg_disc, vha, 0x20db, 1230 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n", 1231 sp->name, res, fcport->port_name, mb[1], mb[2]); 1232 1233 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE); 1234 1235 if (res == QLA_FUNCTION_TIMEOUT) 1236 goto done; 1237 1238 memset(&ea, 0, sizeof(ea)); 1239 ea.fcport = fcport; 1240 ea.sp = sp; 1241 1242 qla24xx_handle_gpdb_event(vha, &ea); 1243 1244 done: 1245 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in, 1246 sp->u.iocb_cmd.u.mbx.in_dma); 1247 1248 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1249 } 1250 1251 int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport) 1252 { 1253 struct qla_work_evt *e; 1254 1255 if (vha->host->active_mode == MODE_TARGET) 1256 return QLA_FUNCTION_FAILED; 1257 1258 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI); 1259 if (!e) 1260 return QLA_FUNCTION_FAILED; 1261 1262 e->u.fcport.fcport = fcport; 1263 1264 return qla2x00_post_work(vha, e); 1265 } 1266 1267 static void qla2x00_async_prli_sp_done(srb_t *sp, int res) 1268 { 1269 struct scsi_qla_host *vha = sp->vha; 1270 struct srb_iocb *lio = &sp->u.iocb_cmd; 1271 struct event_arg ea; 1272 1273 ql_dbg(ql_dbg_disc, vha, 0x2129, 1274 "%s %8phC res %x\n", __func__, 1275 sp->fcport->port_name, res); 1276 1277 sp->fcport->flags &= ~FCF_ASYNC_SENT; 1278 1279 if (!test_bit(UNLOADING, &vha->dpc_flags)) { 1280 memset(&ea, 0, sizeof(ea)); 1281 ea.fcport = sp->fcport; 1282 ea.data[0] = lio->u.logio.data[0]; 1283 ea.data[1] = lio->u.logio.data[1]; 1284 ea.iop[0] = lio->u.logio.iop[0]; 1285 ea.iop[1] = lio->u.logio.iop[1]; 1286 ea.sp = sp; 1287 if (res == QLA_OS_TIMER_EXPIRED) 1288 ea.data[0] = QLA_OS_TIMER_EXPIRED; 1289 else if (res) 1290 ea.data[0] = MBS_COMMAND_ERROR; 1291 1292 qla24xx_handle_prli_done_event(vha, &ea); 1293 } 1294 1295 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1296 } 1297 1298 int 1299 qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport) 1300 { 1301 srb_t *sp; 1302 struct srb_iocb *lio; 1303 int rval = QLA_FUNCTION_FAILED; 1304 1305 if (!vha->flags.online) { 1306 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n", 1307 __func__, __LINE__, fcport->port_name); 1308 return rval; 1309 } 1310 1311 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND || 1312 fcport->fw_login_state == DSC_LS_PRLI_PEND) && 1313 qla_dual_mode_enabled(vha)) { 1314 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n", 1315 __func__, __LINE__, fcport->port_name); 1316 return rval; 1317 } 1318 1319 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1320 if (!sp) 1321 return rval; 1322 1323 fcport->flags |= FCF_ASYNC_SENT; 1324 fcport->logout_completed = 0; 1325 1326 sp->type = SRB_PRLI_CMD; 1327 sp->name = "prli"; 1328 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2, 1329 qla2x00_async_prli_sp_done); 1330 1331 lio = &sp->u.iocb_cmd; 1332 lio->u.logio.flags = 0; 1333 1334 if (NVME_TARGET(vha->hw, fcport)) 1335 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI; 1336 1337 ql_dbg(ql_dbg_disc, vha, 0x211b, 1338 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d fc4type %x priority %x %s.\n", 1339 fcport->port_name, sp->handle, fcport->loop_id, fcport->d_id.b24, 1340 fcport->login_retry, fcport->fc4_type, vha->hw->fc4_type_priority, 1341 NVME_TARGET(vha->hw, fcport) ? "nvme" : "fcp"); 1342 1343 rval = qla2x00_start_sp(sp); 1344 if (rval != QLA_SUCCESS) { 1345 fcport->flags |= FCF_LOGIN_NEEDED; 1346 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1347 goto done_free_sp; 1348 } 1349 1350 return rval; 1351 1352 done_free_sp: 1353 /* ref: INIT */ 1354 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1355 fcport->flags &= ~FCF_ASYNC_SENT; 1356 return rval; 1357 } 1358 1359 int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt) 1360 { 1361 struct qla_work_evt *e; 1362 1363 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB); 1364 if (!e) 1365 return QLA_FUNCTION_FAILED; 1366 1367 e->u.fcport.fcport = fcport; 1368 e->u.fcport.opt = opt; 1369 fcport->flags |= FCF_ASYNC_ACTIVE; 1370 return qla2x00_post_work(vha, e); 1371 } 1372 1373 int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt) 1374 { 1375 srb_t *sp; 1376 struct srb_iocb *mbx; 1377 int rval = QLA_FUNCTION_FAILED; 1378 u16 *mb; 1379 dma_addr_t pd_dma; 1380 struct port_database_24xx *pd; 1381 struct qla_hw_data *ha = vha->hw; 1382 1383 if (IS_SESSION_DELETED(fcport)) { 1384 ql_log(ql_log_warn, vha, 0xffff, 1385 "%s: %8phC is being delete - not sending command.\n", 1386 __func__, fcport->port_name); 1387 fcport->flags &= ~FCF_ASYNC_ACTIVE; 1388 return rval; 1389 } 1390 1391 if (!vha->flags.online || fcport->flags & FCF_ASYNC_SENT) { 1392 ql_log(ql_log_warn, vha, 0xffff, 1393 "%s: %8phC online %d flags %x - not sending command.\n", 1394 __func__, fcport->port_name, vha->flags.online, fcport->flags); 1395 goto done; 1396 } 1397 1398 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL); 1399 if (!sp) 1400 goto done; 1401 1402 qla2x00_set_fcport_disc_state(fcport, DSC_GPDB); 1403 1404 fcport->flags |= FCF_ASYNC_SENT; 1405 sp->type = SRB_MB_IOCB; 1406 sp->name = "gpdb"; 1407 sp->gen1 = fcport->rscn_gen; 1408 sp->gen2 = fcport->login_gen; 1409 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha) + 2, 1410 qla24xx_async_gpdb_sp_done); 1411 1412 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma); 1413 if (pd == NULL) { 1414 ql_log(ql_log_warn, vha, 0xd043, 1415 "Failed to allocate port database structure.\n"); 1416 goto done_free_sp; 1417 } 1418 1419 mb = sp->u.iocb_cmd.u.mbx.out_mb; 1420 mb[0] = MBC_GET_PORT_DATABASE; 1421 mb[1] = fcport->loop_id; 1422 mb[2] = MSW(pd_dma); 1423 mb[3] = LSW(pd_dma); 1424 mb[6] = MSW(MSD(pd_dma)); 1425 mb[7] = LSW(MSD(pd_dma)); 1426 mb[9] = vha->vp_idx; 1427 mb[10] = opt; 1428 1429 mbx = &sp->u.iocb_cmd; 1430 mbx->u.mbx.in = (void *)pd; 1431 mbx->u.mbx.in_dma = pd_dma; 1432 1433 ql_dbg(ql_dbg_disc, vha, 0x20dc, 1434 "Async-%s %8phC hndl %x opt %x\n", 1435 sp->name, fcport->port_name, sp->handle, opt); 1436 1437 rval = qla2x00_start_sp(sp); 1438 if (rval != QLA_SUCCESS) 1439 goto done_free_sp; 1440 return rval; 1441 1442 done_free_sp: 1443 if (pd) 1444 dma_pool_free(ha->s_dma_pool, pd, pd_dma); 1445 1446 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1447 fcport->flags &= ~FCF_ASYNC_SENT; 1448 done: 1449 fcport->flags &= ~FCF_ASYNC_ACTIVE; 1450 qla24xx_post_gpdb_work(vha, fcport, opt); 1451 return rval; 1452 } 1453 1454 static 1455 void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea) 1456 { 1457 unsigned long flags; 1458 1459 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1460 ea->fcport->login_gen++; 1461 ea->fcport->logout_on_delete = 1; 1462 1463 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) { 1464 vha->fcport_count++; 1465 ea->fcport->login_succ = 1; 1466 1467 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1468 qla24xx_sched_upd_fcport(ea->fcport); 1469 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 1470 } else if (ea->fcport->login_succ) { 1471 /* 1472 * We have an existing session. A late RSCN delivery 1473 * must have triggered the session to be re-validate. 1474 * Session is still valid. 1475 */ 1476 ql_dbg(ql_dbg_disc, vha, 0x20d6, 1477 "%s %d %8phC session revalidate success\n", 1478 __func__, __LINE__, ea->fcport->port_name); 1479 qla2x00_set_fcport_disc_state(ea->fcport, DSC_LOGIN_COMPLETE); 1480 } 1481 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 1482 } 1483 1484 static int qla_chk_secure_login(scsi_qla_host_t *vha, fc_port_t *fcport, 1485 struct port_database_24xx *pd) 1486 { 1487 int rc = 0; 1488 1489 if (pd->secure_login) { 1490 ql_dbg(ql_dbg_disc, vha, 0x104d, 1491 "Secure Login established on %8phC\n", 1492 fcport->port_name); 1493 fcport->flags |= FCF_FCSP_DEVICE; 1494 } else { 1495 ql_dbg(ql_dbg_disc, vha, 0x104d, 1496 "non-Secure Login %8phC", 1497 fcport->port_name); 1498 fcport->flags &= ~FCF_FCSP_DEVICE; 1499 } 1500 if (vha->hw->flags.edif_enabled) { 1501 if (fcport->flags & FCF_FCSP_DEVICE) { 1502 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_AUTH_PEND); 1503 /* Start edif prli timer & ring doorbell for app */ 1504 fcport->edif.rx_sa_set = 0; 1505 fcport->edif.tx_sa_set = 0; 1506 fcport->edif.rx_sa_pending = 0; 1507 fcport->edif.tx_sa_pending = 0; 1508 1509 qla2x00_post_aen_work(vha, FCH_EVT_PORT_ONLINE, 1510 fcport->d_id.b24); 1511 1512 if (DBELL_ACTIVE(vha)) { 1513 ql_dbg(ql_dbg_disc, vha, 0x20ef, 1514 "%s %d %8phC EDIF: post DB_AUTH: AUTH needed\n", 1515 __func__, __LINE__, fcport->port_name); 1516 fcport->edif.app_sess_online = 1; 1517 1518 qla_edb_eventcreate(vha, VND_CMD_AUTH_STATE_NEEDED, 1519 fcport->d_id.b24, 0, fcport); 1520 } 1521 1522 rc = 1; 1523 } else if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha)) { 1524 ql_dbg(ql_dbg_disc, vha, 0x2117, 1525 "%s %d %8phC post prli\n", 1526 __func__, __LINE__, fcport->port_name); 1527 qla24xx_post_prli_work(vha, fcport); 1528 rc = 1; 1529 } 1530 } 1531 return rc; 1532 } 1533 1534 static 1535 void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea) 1536 { 1537 fc_port_t *fcport = ea->fcport; 1538 struct port_database_24xx *pd; 1539 struct srb *sp = ea->sp; 1540 uint8_t ls; 1541 1542 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in; 1543 1544 fcport->flags &= ~FCF_ASYNC_SENT; 1545 1546 ql_dbg(ql_dbg_disc, vha, 0x20d2, 1547 "%s %8phC DS %d LS %x fc4_type %x rc %x\n", __func__, 1548 fcport->port_name, fcport->disc_state, pd->current_login_state, 1549 fcport->fc4_type, ea->rc); 1550 1551 if (fcport->disc_state == DSC_DELETE_PEND) { 1552 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC\n", 1553 __func__, __LINE__, fcport->port_name); 1554 return; 1555 } 1556 1557 if (NVME_TARGET(vha->hw, fcport)) 1558 ls = pd->current_login_state >> 4; 1559 else 1560 ls = pd->current_login_state & 0xf; 1561 1562 if (ea->sp->gen2 != fcport->login_gen) { 1563 /* target side must have changed it. */ 1564 1565 ql_dbg(ql_dbg_disc, vha, 0x20d3, 1566 "%s %8phC generation changed\n", 1567 __func__, fcport->port_name); 1568 return; 1569 } else if (ea->sp->gen1 != fcport->rscn_gen) { 1570 qla_rscn_replay(fcport); 1571 qlt_schedule_sess_for_deletion(fcport); 1572 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC, ls %x\n", 1573 __func__, __LINE__, fcport->port_name, ls); 1574 return; 1575 } 1576 1577 switch (ls) { 1578 case PDS_PRLI_COMPLETE: 1579 __qla24xx_parse_gpdb(vha, fcport, pd); 1580 break; 1581 case PDS_PLOGI_COMPLETE: 1582 if (qla_chk_secure_login(vha, fcport, pd)) { 1583 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC, ls %x\n", 1584 __func__, __LINE__, fcport->port_name, ls); 1585 return; 1586 } 1587 fallthrough; 1588 case PDS_PLOGI_PENDING: 1589 case PDS_PRLI_PENDING: 1590 case PDS_PRLI2_PENDING: 1591 /* Set discovery state back to GNL to Relogin attempt */ 1592 if (qla_dual_mode_enabled(vha) || 1593 qla_ini_mode_enabled(vha)) { 1594 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 1595 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1596 } 1597 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC, ls %x\n", 1598 __func__, __LINE__, fcport->port_name, ls); 1599 return; 1600 case PDS_LOGO_PENDING: 1601 case PDS_PORT_UNAVAILABLE: 1602 default: 1603 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n", 1604 __func__, __LINE__, fcport->port_name); 1605 qlt_schedule_sess_for_deletion(fcport); 1606 return; 1607 } 1608 __qla24xx_handle_gpdb_event(vha, ea); 1609 } /* gpdb event */ 1610 1611 static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport) 1612 { 1613 u8 login = 0; 1614 int rc; 1615 1616 ql_dbg(ql_dbg_disc, vha, 0x307b, 1617 "%s %8phC DS %d LS %d lid %d retries=%d\n", 1618 __func__, fcport->port_name, fcport->disc_state, 1619 fcport->fw_login_state, fcport->loop_id, fcport->login_retry); 1620 1621 if (qla_tgt_mode_enabled(vha)) 1622 return; 1623 1624 if (qla_dual_mode_enabled(vha)) { 1625 if (N2N_TOPO(vha->hw)) { 1626 u64 mywwn, wwn; 1627 1628 mywwn = wwn_to_u64(vha->port_name); 1629 wwn = wwn_to_u64(fcport->port_name); 1630 if (mywwn > wwn) 1631 login = 1; 1632 else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP) 1633 && time_after_eq(jiffies, 1634 fcport->plogi_nack_done_deadline)) 1635 login = 1; 1636 } else { 1637 login = 1; 1638 } 1639 } else { 1640 /* initiator mode */ 1641 login = 1; 1642 } 1643 1644 if (login && fcport->login_retry) { 1645 fcport->login_retry--; 1646 if (fcport->loop_id == FC_NO_LOOP_ID) { 1647 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL; 1648 rc = qla2x00_find_new_loop_id(vha, fcport); 1649 if (rc) { 1650 ql_dbg(ql_dbg_disc, vha, 0x20e6, 1651 "%s %d %8phC post del sess - out of loopid\n", 1652 __func__, __LINE__, fcport->port_name); 1653 fcport->scan_state = 0; 1654 qlt_schedule_sess_for_deletion(fcport); 1655 return; 1656 } 1657 } 1658 ql_dbg(ql_dbg_disc, vha, 0x20bf, 1659 "%s %d %8phC post login\n", 1660 __func__, __LINE__, fcport->port_name); 1661 qla2x00_post_async_login_work(vha, fcport, NULL); 1662 } 1663 } 1664 1665 int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport) 1666 { 1667 u16 data[2]; 1668 u16 sec; 1669 1670 ql_dbg(ql_dbg_disc, vha, 0x20d8, 1671 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d lid %d scan %d fc4type %x\n", 1672 __func__, fcport->port_name, fcport->disc_state, 1673 fcport->fw_login_state, fcport->login_pause, fcport->flags, 1674 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen, 1675 fcport->login_gen, fcport->loop_id, fcport->scan_state, 1676 fcport->fc4_type); 1677 1678 if (fcport->scan_state != QLA_FCPORT_FOUND || 1679 fcport->disc_state == DSC_DELETE_PEND) 1680 return 0; 1681 1682 if ((fcport->loop_id != FC_NO_LOOP_ID) && 1683 qla_dual_mode_enabled(vha) && 1684 ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) || 1685 (fcport->fw_login_state == DSC_LS_PRLI_PEND))) 1686 return 0; 1687 1688 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP && 1689 !N2N_TOPO(vha->hw)) { 1690 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) { 1691 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1692 return 0; 1693 } 1694 } 1695 1696 /* Target won't initiate port login if fabric is present */ 1697 if (vha->host->active_mode == MODE_TARGET && !N2N_TOPO(vha->hw)) 1698 return 0; 1699 1700 if (fcport->flags & (FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE)) { 1701 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1702 return 0; 1703 } 1704 1705 switch (fcport->disc_state) { 1706 case DSC_DELETED: 1707 switch (vha->hw->current_topology) { 1708 case ISP_CFG_N: 1709 if (fcport_is_smaller(fcport)) { 1710 /* this adapter is bigger */ 1711 if (fcport->login_retry) { 1712 if (fcport->loop_id == FC_NO_LOOP_ID) { 1713 qla2x00_find_new_loop_id(vha, 1714 fcport); 1715 fcport->fw_login_state = 1716 DSC_LS_PORT_UNAVAIL; 1717 } 1718 fcport->login_retry--; 1719 qla_post_els_plogi_work(vha, fcport); 1720 } else { 1721 ql_log(ql_log_info, vha, 0x705d, 1722 "Unable to reach remote port %8phC", 1723 fcport->port_name); 1724 } 1725 } else { 1726 qla24xx_post_gnl_work(vha, fcport); 1727 } 1728 break; 1729 default: 1730 if (fcport->loop_id == FC_NO_LOOP_ID) { 1731 ql_dbg(ql_dbg_disc, vha, 0x20bd, 1732 "%s %d %8phC post gnl\n", 1733 __func__, __LINE__, fcport->port_name); 1734 qla24xx_post_gnl_work(vha, fcport); 1735 } else { 1736 qla_chk_n2n_b4_login(vha, fcport); 1737 } 1738 break; 1739 } 1740 break; 1741 1742 case DSC_GNL: 1743 switch (vha->hw->current_topology) { 1744 case ISP_CFG_N: 1745 if ((fcport->current_login_state & 0xf) == 0x6) { 1746 ql_dbg(ql_dbg_disc, vha, 0x2118, 1747 "%s %d %8phC post GPDB work\n", 1748 __func__, __LINE__, fcport->port_name); 1749 fcport->chip_reset = 1750 vha->hw->base_qpair->chip_reset; 1751 qla24xx_post_gpdb_work(vha, fcport, 0); 1752 } else { 1753 ql_dbg(ql_dbg_disc, vha, 0x2118, 1754 "%s %d %8phC post %s PRLI\n", 1755 __func__, __LINE__, fcport->port_name, 1756 NVME_TARGET(vha->hw, fcport) ? "NVME" : 1757 "FC"); 1758 qla24xx_post_prli_work(vha, fcport); 1759 } 1760 break; 1761 default: 1762 if (fcport->login_pause) { 1763 ql_dbg(ql_dbg_disc, vha, 0x20d8, 1764 "%s %d %8phC exit\n", 1765 __func__, __LINE__, 1766 fcport->port_name); 1767 fcport->last_rscn_gen = fcport->rscn_gen; 1768 fcport->last_login_gen = fcport->login_gen; 1769 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1770 break; 1771 } 1772 qla_chk_n2n_b4_login(vha, fcport); 1773 break; 1774 } 1775 break; 1776 1777 case DSC_LOGIN_FAILED: 1778 if (N2N_TOPO(vha->hw)) 1779 qla_chk_n2n_b4_login(vha, fcport); 1780 else 1781 qlt_schedule_sess_for_deletion(fcport); 1782 break; 1783 1784 case DSC_LOGIN_COMPLETE: 1785 /* recheck login state */ 1786 data[0] = data[1] = 0; 1787 qla2x00_post_async_adisc_work(vha, fcport, data); 1788 break; 1789 1790 case DSC_LOGIN_PEND: 1791 if (vha->hw->flags.edif_enabled) 1792 break; 1793 1794 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP) { 1795 ql_dbg(ql_dbg_disc, vha, 0x2118, 1796 "%s %d %8phC post %s PRLI\n", 1797 __func__, __LINE__, fcport->port_name, 1798 NVME_TARGET(vha->hw, fcport) ? "NVME" : "FC"); 1799 qla24xx_post_prli_work(vha, fcport); 1800 } 1801 break; 1802 1803 case DSC_UPD_FCPORT: 1804 sec = jiffies_to_msecs(jiffies - 1805 fcport->jiffies_at_registration)/1000; 1806 if (fcport->sec_since_registration < sec && sec && 1807 !(sec % 60)) { 1808 fcport->sec_since_registration = sec; 1809 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff, 1810 "%s %8phC - Slow Rport registration(%d Sec)\n", 1811 __func__, fcport->port_name, sec); 1812 } 1813 1814 if (fcport->next_disc_state != DSC_DELETE_PEND) 1815 fcport->next_disc_state = DSC_ADISC; 1816 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 1817 break; 1818 1819 default: 1820 break; 1821 } 1822 1823 return 0; 1824 } 1825 1826 int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id, 1827 u8 *port_name, u8 *node_name, void *pla, u8 fc4_type) 1828 { 1829 struct qla_work_evt *e; 1830 1831 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS); 1832 if (!e) 1833 return QLA_FUNCTION_FAILED; 1834 1835 e->u.new_sess.id = *id; 1836 e->u.new_sess.pla = pla; 1837 e->u.new_sess.fc4_type = fc4_type; 1838 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE); 1839 if (node_name) 1840 memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE); 1841 1842 return qla2x00_post_work(vha, e); 1843 } 1844 1845 static void qla_rscn_gen_tick(scsi_qla_host_t *vha, u32 *ret_rscn_gen) 1846 { 1847 *ret_rscn_gen = atomic_inc_return(&vha->rscn_gen); 1848 /* memory barrier */ 1849 wmb(); 1850 } 1851 1852 void qla2x00_handle_rscn(scsi_qla_host_t *vha, struct event_arg *ea) 1853 { 1854 fc_port_t *fcport; 1855 unsigned long flags; 1856 u32 rscn_gen; 1857 1858 switch (ea->id.b.rsvd_1) { 1859 case RSCN_PORT_ADDR: 1860 fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1); 1861 if (fcport) { 1862 if (vha->hw->flags.edif_enabled && DBELL_ACTIVE(vha)) { 1863 /* 1864 * On ipsec start by remote port, Target port 1865 * may use RSCN to trigger initiator to 1866 * relogin. If driver is already in the 1867 * process of a relogin, then ignore the RSCN 1868 * and allow the current relogin to continue. 1869 * This reduces thrashing of the connection. 1870 */ 1871 if (atomic_read(&fcport->state) == FCS_ONLINE) { 1872 /* 1873 * If state = online, then set scan_needed=1 to do relogin. 1874 * Otherwise we're already in the middle of a relogin 1875 */ 1876 fcport->scan_needed = 1; 1877 qla_rscn_gen_tick(vha, &fcport->rscn_gen); 1878 } 1879 } else { 1880 fcport->scan_needed = 1; 1881 qla_rscn_gen_tick(vha, &fcport->rscn_gen); 1882 } 1883 } 1884 break; 1885 case RSCN_AREA_ADDR: 1886 qla_rscn_gen_tick(vha, &rscn_gen); 1887 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1888 if (fcport->flags & FCF_FCP2_DEVICE && 1889 atomic_read(&fcport->state) == FCS_ONLINE) 1890 continue; 1891 1892 if ((ea->id.b24 & 0xffff00) == (fcport->d_id.b24 & 0xffff00)) { 1893 fcport->scan_needed = 1; 1894 fcport->rscn_gen = rscn_gen; 1895 } 1896 } 1897 break; 1898 case RSCN_DOM_ADDR: 1899 qla_rscn_gen_tick(vha, &rscn_gen); 1900 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1901 if (fcport->flags & FCF_FCP2_DEVICE && 1902 atomic_read(&fcport->state) == FCS_ONLINE) 1903 continue; 1904 1905 if ((ea->id.b24 & 0xff0000) == (fcport->d_id.b24 & 0xff0000)) { 1906 fcport->scan_needed = 1; 1907 fcport->rscn_gen = rscn_gen; 1908 } 1909 } 1910 break; 1911 case RSCN_FAB_ADDR: 1912 default: 1913 qla_rscn_gen_tick(vha, &rscn_gen); 1914 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1915 if (fcport->flags & FCF_FCP2_DEVICE && 1916 atomic_read(&fcport->state) == FCS_ONLINE) 1917 continue; 1918 1919 fcport->scan_needed = 1; 1920 fcport->rscn_gen = rscn_gen; 1921 } 1922 break; 1923 } 1924 1925 spin_lock_irqsave(&vha->work_lock, flags); 1926 if (vha->scan.scan_flags == 0) { 1927 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s: schedule\n", __func__); 1928 vha->scan.scan_flags |= SF_QUEUED; 1929 vha->scan.rscn_gen_start = atomic_read(&vha->rscn_gen); 1930 schedule_delayed_work(&vha->scan.scan_work, 5); 1931 } 1932 spin_unlock_irqrestore(&vha->work_lock, flags); 1933 } 1934 1935 void qla24xx_handle_relogin_event(scsi_qla_host_t *vha, 1936 struct event_arg *ea) 1937 { 1938 fc_port_t *fcport = ea->fcport; 1939 1940 if (test_bit(UNLOADING, &vha->dpc_flags)) 1941 return; 1942 1943 ql_dbg(ql_dbg_disc, vha, 0x2102, 1944 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n", 1945 __func__, fcport->port_name, fcport->disc_state, 1946 fcport->fw_login_state, fcport->login_pause, 1947 fcport->deleted, fcport->conflict, 1948 fcport->last_rscn_gen, fcport->rscn_gen, 1949 fcport->last_login_gen, fcport->login_gen, 1950 fcport->flags); 1951 1952 if (fcport->last_rscn_gen != fcport->rscn_gen) { 1953 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gnl\n", 1954 __func__, __LINE__, fcport->port_name); 1955 qla24xx_post_gnl_work(vha, fcport); 1956 return; 1957 } 1958 1959 qla24xx_fcport_handle_login(vha, fcport); 1960 } 1961 1962 void qla_handle_els_plogi_done(scsi_qla_host_t *vha, 1963 struct event_arg *ea) 1964 { 1965 if (N2N_TOPO(vha->hw) && fcport_is_smaller(ea->fcport) && 1966 vha->hw->flags.edif_enabled) { 1967 /* check to see if App support Secure */ 1968 qla24xx_post_gpdb_work(vha, ea->fcport, 0); 1969 return; 1970 } 1971 1972 /* for pure Target Mode, PRLI will not be initiated */ 1973 if (vha->host->active_mode == MODE_TARGET) 1974 return; 1975 1976 ql_dbg(ql_dbg_disc, vha, 0x2118, 1977 "%s %d %8phC post PRLI\n", 1978 __func__, __LINE__, ea->fcport->port_name); 1979 qla24xx_post_prli_work(vha, ea->fcport); 1980 } 1981 1982 /* 1983 * RSCN(s) came in for this fcport, but the RSCN(s) was not able 1984 * to be consumed by the fcport 1985 */ 1986 void qla_rscn_replay(fc_port_t *fcport) 1987 { 1988 struct event_arg ea; 1989 1990 switch (fcport->disc_state) { 1991 case DSC_DELETE_PEND: 1992 return; 1993 default: 1994 break; 1995 } 1996 1997 if (fcport->scan_needed) { 1998 memset(&ea, 0, sizeof(ea)); 1999 ea.id = fcport->d_id; 2000 ea.id.b.rsvd_1 = RSCN_PORT_ADDR; 2001 qla2x00_handle_rscn(fcport->vha, &ea); 2002 } 2003 } 2004 2005 static void 2006 qla2x00_tmf_iocb_timeout(void *data) 2007 { 2008 srb_t *sp = data; 2009 struct srb_iocb *tmf = &sp->u.iocb_cmd; 2010 int rc, h; 2011 unsigned long flags; 2012 2013 if (sp->type == SRB_MARKER) 2014 rc = QLA_FUNCTION_FAILED; 2015 else 2016 rc = qla24xx_async_abort_cmd(sp, false); 2017 2018 if (rc) { 2019 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags); 2020 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; h++) { 2021 if (sp->qpair->req->outstanding_cmds[h] == sp) { 2022 sp->qpair->req->outstanding_cmds[h] = NULL; 2023 qla_put_fw_resources(sp->qpair, &sp->iores); 2024 break; 2025 } 2026 } 2027 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags); 2028 tmf->u.tmf.comp_status = cpu_to_le16(CS_TIMEOUT); 2029 tmf->u.tmf.data = QLA_FUNCTION_FAILED; 2030 complete(&tmf->u.tmf.comp); 2031 } 2032 } 2033 2034 static void qla_marker_sp_done(srb_t *sp, int res) 2035 { 2036 struct srb_iocb *tmf = &sp->u.iocb_cmd; 2037 2038 if (res != QLA_SUCCESS) 2039 ql_dbg(ql_dbg_taskm, sp->vha, 0x8004, 2040 "Async-marker fail hdl=%x portid=%06x ctrl=%x lun=%lld qp=%d.\n", 2041 sp->handle, sp->fcport->d_id.b24, sp->u.iocb_cmd.u.tmf.flags, 2042 sp->u.iocb_cmd.u.tmf.lun, sp->qpair->id); 2043 2044 sp->u.iocb_cmd.u.tmf.data = res; 2045 complete(&tmf->u.tmf.comp); 2046 } 2047 2048 #define START_SP_W_RETRIES(_sp, _rval, _chip_gen, _login_gen) \ 2049 {\ 2050 int cnt = 5; \ 2051 do { \ 2052 if (_chip_gen != sp->vha->hw->chip_reset || _login_gen != sp->fcport->login_gen) {\ 2053 _rval = -EINVAL; \ 2054 break; \ 2055 } \ 2056 _rval = qla2x00_start_sp(_sp); \ 2057 if (_rval == -EAGAIN) \ 2058 msleep(1); \ 2059 else \ 2060 break; \ 2061 cnt--; \ 2062 } while (cnt); \ 2063 } 2064 2065 /** 2066 * qla26xx_marker: send marker IOCB and wait for the completion of it. 2067 * @arg: pointer to argument list. 2068 * It is assume caller will provide an fcport pointer and modifier 2069 */ 2070 static int 2071 qla26xx_marker(struct tmf_arg *arg) 2072 { 2073 struct scsi_qla_host *vha = arg->vha; 2074 struct srb_iocb *tm_iocb; 2075 srb_t *sp; 2076 int rval = QLA_FUNCTION_FAILED; 2077 fc_port_t *fcport = arg->fcport; 2078 u32 chip_gen, login_gen; 2079 2080 if (TMF_NOT_READY(arg->fcport)) { 2081 ql_dbg(ql_dbg_taskm, vha, 0x8039, 2082 "FC port not ready for marker loop-id=%x portid=%06x modifier=%x lun=%lld qp=%d.\n", 2083 fcport->loop_id, fcport->d_id.b24, 2084 arg->modifier, arg->lun, arg->qpair->id); 2085 return QLA_SUSPENDED; 2086 } 2087 2088 chip_gen = vha->hw->chip_reset; 2089 login_gen = fcport->login_gen; 2090 2091 /* ref: INIT */ 2092 sp = qla2xxx_get_qpair_sp(vha, arg->qpair, fcport, GFP_KERNEL); 2093 if (!sp) 2094 goto done; 2095 2096 sp->type = SRB_MARKER; 2097 sp->name = "marker"; 2098 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha), qla_marker_sp_done); 2099 sp->u.iocb_cmd.timeout = qla2x00_tmf_iocb_timeout; 2100 2101 tm_iocb = &sp->u.iocb_cmd; 2102 init_completion(&tm_iocb->u.tmf.comp); 2103 tm_iocb->u.tmf.modifier = arg->modifier; 2104 tm_iocb->u.tmf.lun = arg->lun; 2105 tm_iocb->u.tmf.loop_id = fcport->loop_id; 2106 tm_iocb->u.tmf.vp_index = vha->vp_idx; 2107 2108 START_SP_W_RETRIES(sp, rval, chip_gen, login_gen); 2109 2110 ql_dbg(ql_dbg_taskm, vha, 0x8006, 2111 "Async-marker hdl=%x loop-id=%x portid=%06x modifier=%x lun=%lld qp=%d rval %d.\n", 2112 sp->handle, fcport->loop_id, fcport->d_id.b24, 2113 arg->modifier, arg->lun, sp->qpair->id, rval); 2114 2115 if (rval != QLA_SUCCESS) { 2116 ql_log(ql_log_warn, vha, 0x8031, 2117 "Marker IOCB send failure (%x).\n", rval); 2118 goto done_free_sp; 2119 } 2120 2121 wait_for_completion(&tm_iocb->u.tmf.comp); 2122 rval = tm_iocb->u.tmf.data; 2123 2124 if (rval != QLA_SUCCESS) { 2125 ql_log(ql_log_warn, vha, 0x8019, 2126 "Marker failed hdl=%x loop-id=%x portid=%06x modifier=%x lun=%lld qp=%d rval %d.\n", 2127 sp->handle, fcport->loop_id, fcport->d_id.b24, 2128 arg->modifier, arg->lun, sp->qpair->id, rval); 2129 } 2130 2131 done_free_sp: 2132 /* ref: INIT */ 2133 kref_put(&sp->cmd_kref, qla2x00_sp_release); 2134 done: 2135 return rval; 2136 } 2137 2138 static void qla2x00_tmf_sp_done(srb_t *sp, int res) 2139 { 2140 struct srb_iocb *tmf = &sp->u.iocb_cmd; 2141 2142 if (res) 2143 tmf->u.tmf.data = res; 2144 complete(&tmf->u.tmf.comp); 2145 } 2146 2147 static int qla_tmf_wait(struct tmf_arg *arg) 2148 { 2149 /* there are only 2 types of error handling that reaches here, lun or target reset */ 2150 if (arg->flags & (TCF_LUN_RESET | TCF_ABORT_TASK_SET | TCF_CLEAR_TASK_SET)) 2151 return qla2x00_eh_wait_for_pending_commands(arg->vha, 2152 arg->fcport->d_id.b24, arg->lun, WAIT_LUN); 2153 else 2154 return qla2x00_eh_wait_for_pending_commands(arg->vha, 2155 arg->fcport->d_id.b24, arg->lun, WAIT_TARGET); 2156 } 2157 2158 static int 2159 __qla2x00_async_tm_cmd(struct tmf_arg *arg) 2160 { 2161 struct scsi_qla_host *vha = arg->vha; 2162 struct srb_iocb *tm_iocb; 2163 srb_t *sp; 2164 int rval = QLA_FUNCTION_FAILED; 2165 fc_port_t *fcport = arg->fcport; 2166 u32 chip_gen, login_gen; 2167 u64 jif; 2168 2169 if (TMF_NOT_READY(arg->fcport)) { 2170 ql_dbg(ql_dbg_taskm, vha, 0x8032, 2171 "FC port not ready for TM command loop-id=%x portid=%06x modifier=%x lun=%lld qp=%d.\n", 2172 fcport->loop_id, fcport->d_id.b24, 2173 arg->modifier, arg->lun, arg->qpair->id); 2174 return QLA_SUSPENDED; 2175 } 2176 2177 chip_gen = vha->hw->chip_reset; 2178 login_gen = fcport->login_gen; 2179 2180 /* ref: INIT */ 2181 sp = qla2xxx_get_qpair_sp(vha, arg->qpair, fcport, GFP_KERNEL); 2182 if (!sp) 2183 goto done; 2184 2185 qla_vha_mark_busy(vha); 2186 sp->type = SRB_TM_CMD; 2187 sp->name = "tmf"; 2188 qla2x00_init_async_sp(sp, qla2x00_get_async_timeout(vha), 2189 qla2x00_tmf_sp_done); 2190 sp->u.iocb_cmd.timeout = qla2x00_tmf_iocb_timeout; 2191 2192 tm_iocb = &sp->u.iocb_cmd; 2193 init_completion(&tm_iocb->u.tmf.comp); 2194 tm_iocb->u.tmf.flags = arg->flags; 2195 tm_iocb->u.tmf.lun = arg->lun; 2196 2197 START_SP_W_RETRIES(sp, rval, chip_gen, login_gen); 2198 2199 ql_dbg(ql_dbg_taskm, vha, 0x802f, 2200 "Async-tmf hdl=%x loop-id=%x portid=%06x ctrl=%x lun=%lld qp=%d rval=%x.\n", 2201 sp->handle, fcport->loop_id, fcport->d_id.b24, 2202 arg->flags, arg->lun, sp->qpair->id, rval); 2203 2204 if (rval != QLA_SUCCESS) 2205 goto done_free_sp; 2206 wait_for_completion(&tm_iocb->u.tmf.comp); 2207 2208 rval = tm_iocb->u.tmf.data; 2209 2210 if (rval != QLA_SUCCESS) { 2211 ql_log(ql_log_warn, vha, 0x8030, 2212 "TM IOCB failed (%x).\n", rval); 2213 } 2214 2215 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) { 2216 jif = jiffies; 2217 if (qla_tmf_wait(arg)) { 2218 ql_log(ql_log_info, vha, 0x803e, 2219 "Waited %u ms Nexus=%ld:%06x:%llu.\n", 2220 jiffies_to_msecs(jiffies - jif), vha->host_no, 2221 fcport->d_id.b24, arg->lun); 2222 } 2223 2224 if (chip_gen == vha->hw->chip_reset && login_gen == fcport->login_gen) { 2225 rval = qla26xx_marker(arg); 2226 } else { 2227 ql_log(ql_log_info, vha, 0x803e, 2228 "Skip Marker due to disruption. Nexus=%ld:%06x:%llu.\n", 2229 vha->host_no, fcport->d_id.b24, arg->lun); 2230 rval = QLA_FUNCTION_FAILED; 2231 } 2232 } 2233 if (tm_iocb->u.tmf.data) 2234 rval = tm_iocb->u.tmf.data; 2235 2236 done_free_sp: 2237 /* ref: INIT */ 2238 kref_put(&sp->cmd_kref, qla2x00_sp_release); 2239 done: 2240 return rval; 2241 } 2242 2243 static void qla_put_tmf(struct tmf_arg *arg) 2244 { 2245 struct scsi_qla_host *vha = arg->vha; 2246 struct qla_hw_data *ha = vha->hw; 2247 unsigned long flags; 2248 2249 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 2250 ha->active_tmf--; 2251 list_del(&arg->tmf_elem); 2252 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 2253 } 2254 2255 static 2256 int qla_get_tmf(struct tmf_arg *arg) 2257 { 2258 struct scsi_qla_host *vha = arg->vha; 2259 struct qla_hw_data *ha = vha->hw; 2260 unsigned long flags; 2261 fc_port_t *fcport = arg->fcport; 2262 int rc = 0; 2263 struct tmf_arg *t; 2264 2265 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 2266 list_for_each_entry(t, &ha->tmf_active, tmf_elem) { 2267 if (t->fcport == arg->fcport && t->lun == arg->lun) { 2268 /* reject duplicate TMF */ 2269 ql_log(ql_log_warn, vha, 0x802c, 2270 "found duplicate TMF. Nexus=%ld:%06x:%llu.\n", 2271 vha->host_no, fcport->d_id.b24, arg->lun); 2272 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 2273 return -EINVAL; 2274 } 2275 } 2276 2277 list_add_tail(&arg->tmf_elem, &ha->tmf_pending); 2278 while (ha->active_tmf >= MAX_ACTIVE_TMF) { 2279 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 2280 2281 msleep(1); 2282 2283 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 2284 if (TMF_NOT_READY(fcport)) { 2285 ql_log(ql_log_warn, vha, 0x802c, 2286 "Unable to acquire TM resource due to disruption.\n"); 2287 rc = EIO; 2288 break; 2289 } 2290 if (ha->active_tmf < MAX_ACTIVE_TMF && 2291 list_is_first(&arg->tmf_elem, &ha->tmf_pending)) 2292 break; 2293 } 2294 2295 list_del(&arg->tmf_elem); 2296 2297 if (!rc) { 2298 ha->active_tmf++; 2299 list_add_tail(&arg->tmf_elem, &ha->tmf_active); 2300 } 2301 2302 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 2303 2304 return rc; 2305 } 2306 2307 int 2308 qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint64_t lun, 2309 uint32_t tag) 2310 { 2311 struct scsi_qla_host *vha = fcport->vha; 2312 struct tmf_arg a; 2313 int rval = QLA_SUCCESS; 2314 2315 if (TMF_NOT_READY(fcport)) 2316 return QLA_SUSPENDED; 2317 2318 a.vha = fcport->vha; 2319 a.fcport = fcport; 2320 a.lun = lun; 2321 a.flags = flags; 2322 INIT_LIST_HEAD(&a.tmf_elem); 2323 2324 if (flags & (TCF_LUN_RESET|TCF_ABORT_TASK_SET|TCF_CLEAR_TASK_SET|TCF_CLEAR_ACA)) { 2325 a.modifier = MK_SYNC_ID_LUN; 2326 } else { 2327 a.modifier = MK_SYNC_ID; 2328 } 2329 2330 if (qla_get_tmf(&a)) 2331 return QLA_FUNCTION_FAILED; 2332 2333 a.qpair = vha->hw->base_qpair; 2334 rval = __qla2x00_async_tm_cmd(&a); 2335 2336 qla_put_tmf(&a); 2337 return rval; 2338 } 2339 2340 int 2341 qla24xx_async_abort_command(srb_t *sp) 2342 { 2343 unsigned long flags = 0; 2344 2345 uint32_t handle; 2346 fc_port_t *fcport = sp->fcport; 2347 struct qla_qpair *qpair = sp->qpair; 2348 struct scsi_qla_host *vha = fcport->vha; 2349 struct req_que *req = qpair->req; 2350 2351 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 2352 for (handle = 1; handle < req->num_outstanding_cmds; handle++) { 2353 if (req->outstanding_cmds[handle] == sp) 2354 break; 2355 } 2356 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 2357 2358 if (handle == req->num_outstanding_cmds) { 2359 /* Command not found. */ 2360 return QLA_ERR_NOT_FOUND; 2361 } 2362 if (sp->type == SRB_FXIOCB_DCMD) 2363 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport, 2364 FXDISC_ABORT_IOCTL); 2365 2366 return qla24xx_async_abort_cmd(sp, true); 2367 } 2368 2369 static void 2370 qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea) 2371 { 2372 struct srb *sp; 2373 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 2374 ea->data[0]); 2375 2376 switch (ea->data[0]) { 2377 case MBS_COMMAND_COMPLETE: 2378 ql_dbg(ql_dbg_disc, vha, 0x2118, 2379 "%s %d %8phC post gpdb\n", 2380 __func__, __LINE__, ea->fcport->port_name); 2381 2382 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset; 2383 ea->fcport->logout_on_delete = 1; 2384 ea->fcport->nvme_prli_service_param = ea->iop[0]; 2385 if (ea->iop[0] & NVME_PRLI_SP_FIRST_BURST) 2386 ea->fcport->nvme_first_burst_size = 2387 (ea->iop[1] & 0xffff) * 512; 2388 else 2389 ea->fcport->nvme_first_burst_size = 0; 2390 qla24xx_post_gpdb_work(vha, ea->fcport, 0); 2391 break; 2392 default: 2393 sp = ea->sp; 2394 ql_dbg(ql_dbg_disc, vha, 0x2118, 2395 "%s %d %8phC priority %s, fc4type %x prev try %s\n", 2396 __func__, __LINE__, ea->fcport->port_name, 2397 vha->hw->fc4_type_priority == FC4_PRIORITY_FCP ? 2398 "FCP" : "NVMe", ea->fcport->fc4_type, 2399 (sp->u.iocb_cmd.u.logio.flags & SRB_LOGIN_NVME_PRLI) ? 2400 "NVME" : "FCP"); 2401 2402 if (NVME_FCP_TARGET(ea->fcport)) { 2403 if (sp->u.iocb_cmd.u.logio.flags & SRB_LOGIN_NVME_PRLI) 2404 ea->fcport->do_prli_nvme = 0; 2405 else 2406 ea->fcport->do_prli_nvme = 1; 2407 } else { 2408 ea->fcport->do_prli_nvme = 0; 2409 } 2410 2411 if (N2N_TOPO(vha->hw)) { 2412 if (ea->fcport->n2n_link_reset_cnt == 2413 vha->hw->login_retry_count && 2414 ea->fcport->flags & FCF_FCSP_DEVICE) { 2415 /* remote authentication app just started */ 2416 ea->fcport->n2n_link_reset_cnt = 0; 2417 } 2418 2419 if (ea->fcport->n2n_link_reset_cnt < 2420 vha->hw->login_retry_count) { 2421 ea->fcport->n2n_link_reset_cnt++; 2422 vha->relogin_jif = jiffies + 2 * HZ; 2423 /* 2424 * PRLI failed. Reset link to kick start 2425 * state machine 2426 */ 2427 set_bit(N2N_LINK_RESET, &vha->dpc_flags); 2428 qla2xxx_wake_dpc(vha); 2429 } else { 2430 ql_log(ql_log_warn, vha, 0x2119, 2431 "%s %d %8phC Unable to reconnect\n", 2432 __func__, __LINE__, 2433 ea->fcport->port_name); 2434 } 2435 } else { 2436 /* 2437 * switch connect. login failed. Take connection down 2438 * and allow relogin to retrigger 2439 */ 2440 ea->fcport->flags &= ~FCF_ASYNC_SENT; 2441 ea->fcport->keep_nport_handle = 0; 2442 ea->fcport->logout_on_delete = 1; 2443 qlt_schedule_sess_for_deletion(ea->fcport); 2444 } 2445 break; 2446 } 2447 } 2448 2449 void 2450 qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea) 2451 { 2452 port_id_t cid; /* conflict Nport id */ 2453 u16 lid; 2454 struct fc_port *conflict_fcport; 2455 unsigned long flags; 2456 struct fc_port *fcport = ea->fcport; 2457 2458 ql_dbg(ql_dbg_disc, vha, 0xffff, 2459 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n", 2460 __func__, fcport->port_name, fcport->disc_state, 2461 fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen, 2462 ea->sp->gen1, fcport->rscn_gen, 2463 ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]); 2464 2465 if (fcport->fw_login_state == DSC_LS_PLOGI_PEND) { 2466 ql_dbg(ql_dbg_disc, vha, 0x20ea, 2467 "%s %d %8phC Remote is trying to login\n", 2468 __func__, __LINE__, fcport->port_name); 2469 /* 2470 * If we get here, there is port thats already logged in, 2471 * but it's state has not moved ahead. Recheck with FW on 2472 * what state it is in and proceed ahead 2473 */ 2474 if (!N2N_TOPO(vha->hw)) { 2475 fcport->fw_login_state = DSC_LS_PRLI_COMP; 2476 qla24xx_post_gpdb_work(vha, fcport, 0); 2477 } 2478 return; 2479 } 2480 2481 if (fcport->fw_login_state == DSC_LS_PRLI_PEND) { 2482 ql_dbg(ql_dbg_disc, vha, 0x20ea, 2483 "%s %d %8phC Remote is trying to login\n", 2484 __func__, __LINE__, fcport->port_name); 2485 return; 2486 } 2487 2488 if ((fcport->disc_state == DSC_DELETE_PEND) || 2489 (fcport->disc_state == DSC_DELETED)) { 2490 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2491 return; 2492 } 2493 2494 if (ea->sp->gen2 != fcport->login_gen) { 2495 /* target side must have changed it. */ 2496 ql_dbg(ql_dbg_disc, vha, 0x20d3, 2497 "%s %8phC generation changed\n", 2498 __func__, fcport->port_name); 2499 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 2500 return; 2501 } else if (ea->sp->gen1 != fcport->rscn_gen) { 2502 ql_dbg(ql_dbg_disc, vha, 0x20d3, 2503 "%s %8phC RSCN generation changed\n", 2504 __func__, fcport->port_name); 2505 qla_rscn_replay(fcport); 2506 qlt_schedule_sess_for_deletion(fcport); 2507 return; 2508 } 2509 2510 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n", 2511 ea->data[0]); 2512 2513 switch (ea->data[0]) { 2514 case MBS_COMMAND_COMPLETE: 2515 /* 2516 * Driver must validate login state - If PRLI not complete, 2517 * force a relogin attempt via implicit LOGO, PLOGI, and PRLI 2518 * requests. 2519 */ 2520 if (vha->hw->flags.edif_enabled) { 2521 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map); 2522 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 2523 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset; 2524 ea->fcport->logout_on_delete = 1; 2525 ea->fcport->send_els_logo = 0; 2526 ea->fcport->fw_login_state = DSC_LS_PLOGI_COMP; 2527 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 2528 2529 qla24xx_post_gpdb_work(vha, ea->fcport, 0); 2530 } else { 2531 if (NVME_TARGET(vha->hw, fcport)) { 2532 ql_dbg(ql_dbg_disc, vha, 0x2117, 2533 "%s %d %8phC post prli\n", 2534 __func__, __LINE__, fcport->port_name); 2535 qla24xx_post_prli_work(vha, fcport); 2536 } else { 2537 ql_dbg(ql_dbg_disc, vha, 0x20ea, 2538 "%s %d %8phC LoopID 0x%x in use with %06x. post gpdb\n", 2539 __func__, __LINE__, fcport->port_name, 2540 fcport->loop_id, fcport->d_id.b24); 2541 2542 set_bit(fcport->loop_id, vha->hw->loop_id_map); 2543 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 2544 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 2545 fcport->logout_on_delete = 1; 2546 fcport->send_els_logo = 0; 2547 fcport->fw_login_state = DSC_LS_PRLI_COMP; 2548 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 2549 2550 qla24xx_post_gpdb_work(vha, fcport, 0); 2551 } 2552 } 2553 break; 2554 case MBS_COMMAND_ERROR: 2555 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n", 2556 __func__, __LINE__, ea->fcport->port_name, ea->data[1]); 2557 2558 qlt_schedule_sess_for_deletion(ea->fcport); 2559 break; 2560 case MBS_LOOP_ID_USED: 2561 /* data[1] = IO PARAM 1 = nport ID */ 2562 cid.b.domain = (ea->iop[1] >> 16) & 0xff; 2563 cid.b.area = (ea->iop[1] >> 8) & 0xff; 2564 cid.b.al_pa = ea->iop[1] & 0xff; 2565 cid.b.rsvd_1 = 0; 2566 2567 ql_dbg(ql_dbg_disc, vha, 0x20ec, 2568 "%s %d %8phC lid %#x in use with pid %06x post gnl\n", 2569 __func__, __LINE__, ea->fcport->port_name, 2570 ea->fcport->loop_id, cid.b24); 2571 2572 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map); 2573 ea->fcport->loop_id = FC_NO_LOOP_ID; 2574 qla24xx_post_gnl_work(vha, ea->fcport); 2575 break; 2576 case MBS_PORT_ID_USED: 2577 lid = ea->iop[1] & 0xffff; 2578 qlt_find_sess_invalidate_other(vha, 2579 wwn_to_u64(ea->fcport->port_name), 2580 ea->fcport->d_id, lid, &conflict_fcport); 2581 2582 if (conflict_fcport) { 2583 /* 2584 * Another fcport share the same loop_id/nport id. 2585 * Conflict fcport needs to finish cleanup before this 2586 * fcport can proceed to login. 2587 */ 2588 conflict_fcport->conflict = ea->fcport; 2589 ea->fcport->login_pause = 1; 2590 2591 ql_dbg(ql_dbg_disc, vha, 0x20ed, 2592 "%s %d %8phC NPortId %06x inuse with loopid 0x%x.\n", 2593 __func__, __LINE__, ea->fcport->port_name, 2594 ea->fcport->d_id.b24, lid); 2595 } else { 2596 ql_dbg(ql_dbg_disc, vha, 0x20ed, 2597 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n", 2598 __func__, __LINE__, ea->fcport->port_name, 2599 ea->fcport->d_id.b24, lid); 2600 2601 qla2x00_clear_loop_id(ea->fcport); 2602 set_bit(lid, vha->hw->loop_id_map); 2603 ea->fcport->loop_id = lid; 2604 ea->fcport->keep_nport_handle = 0; 2605 ea->fcport->logout_on_delete = 1; 2606 qlt_schedule_sess_for_deletion(ea->fcport); 2607 } 2608 break; 2609 } 2610 return; 2611 } 2612 2613 /****************************************************************************/ 2614 /* QLogic ISP2x00 Hardware Support Functions. */ 2615 /****************************************************************************/ 2616 2617 static int 2618 qla83xx_nic_core_fw_load(scsi_qla_host_t *vha) 2619 { 2620 int rval = QLA_SUCCESS; 2621 struct qla_hw_data *ha = vha->hw; 2622 uint32_t idc_major_ver, idc_minor_ver; 2623 uint16_t config[4]; 2624 2625 qla83xx_idc_lock(vha, 0); 2626 2627 /* SV: TODO: Assign initialization timeout from 2628 * flash-info / other param 2629 */ 2630 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT; 2631 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT; 2632 2633 /* Set our fcoe function presence */ 2634 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) { 2635 ql_dbg(ql_dbg_p3p, vha, 0xb077, 2636 "Error while setting DRV-Presence.\n"); 2637 rval = QLA_FUNCTION_FAILED; 2638 goto exit; 2639 } 2640 2641 /* Decide the reset ownership */ 2642 qla83xx_reset_ownership(vha); 2643 2644 /* 2645 * On first protocol driver load: 2646 * Init-Owner: Set IDC-Major-Version and Clear IDC-Lock-Recovery 2647 * register. 2648 * Others: Check compatibility with current IDC Major version. 2649 */ 2650 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver); 2651 if (ha->flags.nic_core_reset_owner) { 2652 /* Set IDC Major version */ 2653 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION; 2654 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver); 2655 2656 /* Clearing IDC-Lock-Recovery register */ 2657 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0); 2658 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) { 2659 /* 2660 * Clear further IDC participation if we are not compatible with 2661 * the current IDC Major Version. 2662 */ 2663 ql_log(ql_log_warn, vha, 0xb07d, 2664 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n", 2665 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION); 2666 __qla83xx_clear_drv_presence(vha); 2667 rval = QLA_FUNCTION_FAILED; 2668 goto exit; 2669 } 2670 /* Each function sets its supported Minor version. */ 2671 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver); 2672 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2)); 2673 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver); 2674 2675 if (ha->flags.nic_core_reset_owner) { 2676 memset(config, 0, sizeof(config)); 2677 if (!qla81xx_get_port_config(vha, config)) 2678 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 2679 QLA8XXX_DEV_READY); 2680 } 2681 2682 rval = qla83xx_idc_state_handler(vha); 2683 2684 exit: 2685 qla83xx_idc_unlock(vha, 0); 2686 2687 return rval; 2688 } 2689 2690 void qla_enable_fce_trace(scsi_qla_host_t *vha) 2691 { 2692 int rval; 2693 struct qla_hw_data *ha = vha->hw; 2694 2695 if (ha->fce) { 2696 ha->flags.fce_enabled = 1; 2697 memset(ha->fce, 0, fce_calc_size(ha->fce_bufs)); 2698 rval = qla2x00_enable_fce_trace(vha, 2699 ha->fce_dma, ha->fce_bufs, ha->fce_mb, &ha->fce_bufs); 2700 2701 if (rval) { 2702 ql_log(ql_log_warn, vha, 0x8033, 2703 "Unable to reinitialize FCE (%d).\n", rval); 2704 ha->flags.fce_enabled = 0; 2705 } 2706 } 2707 } 2708 2709 static void qla_enable_eft_trace(scsi_qla_host_t *vha) 2710 { 2711 int rval; 2712 struct qla_hw_data *ha = vha->hw; 2713 2714 if (ha->eft) { 2715 memset(ha->eft, 0, EFT_SIZE); 2716 rval = qla2x00_enable_eft_trace(vha, ha->eft_dma, EFT_NUM_BUFFERS); 2717 2718 if (rval) { 2719 ql_log(ql_log_warn, vha, 0x8034, 2720 "Unable to reinitialize EFT (%d).\n", rval); 2721 } 2722 } 2723 } 2724 /* 2725 * qla2x00_initialize_adapter 2726 * Initialize board. 2727 * 2728 * Input: 2729 * ha = adapter block pointer. 2730 * 2731 * Returns: 2732 * 0 = success 2733 */ 2734 int 2735 qla2x00_initialize_adapter(scsi_qla_host_t *vha) 2736 { 2737 int rval; 2738 struct qla_hw_data *ha = vha->hw; 2739 struct req_que *req = ha->req_q_map[0]; 2740 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2741 2742 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats)); 2743 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat)); 2744 2745 /* Clear adapter flags. */ 2746 vha->flags.online = 0; 2747 ha->flags.chip_reset_done = 0; 2748 vha->flags.reset_active = 0; 2749 ha->flags.pci_channel_io_perm_failure = 0; 2750 ha->flags.eeh_busy = 0; 2751 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64(); 2752 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 2753 atomic_set(&vha->loop_state, LOOP_DOWN); 2754 vha->device_flags = DFLG_NO_CABLE; 2755 vha->dpc_flags = 0; 2756 vha->flags.management_server_logged_in = 0; 2757 vha->marker_needed = 0; 2758 ha->isp_abort_cnt = 0; 2759 ha->beacon_blink_led = 0; 2760 2761 set_bit(0, ha->req_qid_map); 2762 set_bit(0, ha->rsp_qid_map); 2763 2764 ql_dbg(ql_dbg_init, vha, 0x0040, 2765 "Configuring PCI space...\n"); 2766 rval = ha->isp_ops->pci_config(vha); 2767 if (rval) { 2768 ql_log(ql_log_warn, vha, 0x0044, 2769 "Unable to configure PCI space.\n"); 2770 return (rval); 2771 } 2772 2773 ha->isp_ops->reset_chip(vha); 2774 2775 /* Check for secure flash support */ 2776 if (IS_QLA28XX(ha)) { 2777 if (rd_reg_word(®->mailbox12) & BIT_0) 2778 ha->flags.secure_adapter = 1; 2779 ql_log(ql_log_info, vha, 0xffff, "Secure Adapter: %s\n", 2780 (ha->flags.secure_adapter) ? "Yes" : "No"); 2781 } 2782 2783 2784 rval = qla2xxx_get_flash_info(vha); 2785 if (rval) { 2786 ql_log(ql_log_fatal, vha, 0x004f, 2787 "Unable to validate FLASH data.\n"); 2788 return rval; 2789 } 2790 2791 if (IS_QLA8044(ha)) { 2792 qla8044_read_reset_template(vha); 2793 2794 /* NOTE: If ql2xdontresethba==1, set IDC_CTRL DONTRESET_BIT0. 2795 * If DONRESET_BIT0 is set, drivers should not set dev_state 2796 * to NEED_RESET. But if NEED_RESET is set, drivers should 2797 * should honor the reset. */ 2798 if (ql2xdontresethba == 1) 2799 qla8044_set_idc_dontreset(vha); 2800 } 2801 2802 ha->isp_ops->get_flash_version(vha, req->ring); 2803 ql_dbg(ql_dbg_init, vha, 0x0061, 2804 "Configure NVRAM parameters...\n"); 2805 2806 /* Let priority default to FCP, can be overridden by nvram_config */ 2807 ha->fc4_type_priority = FC4_PRIORITY_FCP; 2808 2809 ha->isp_ops->nvram_config(vha); 2810 2811 if (ha->fc4_type_priority != FC4_PRIORITY_FCP && 2812 ha->fc4_type_priority != FC4_PRIORITY_NVME) 2813 ha->fc4_type_priority = FC4_PRIORITY_FCP; 2814 2815 ql_log(ql_log_info, vha, 0xffff, "FC4 priority set to %s\n", 2816 ha->fc4_type_priority == FC4_PRIORITY_FCP ? "FCP" : "NVMe"); 2817 2818 if (ha->flags.disable_serdes) { 2819 /* Mask HBA via NVRAM settings? */ 2820 ql_log(ql_log_info, vha, 0x0077, 2821 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name); 2822 return QLA_FUNCTION_FAILED; 2823 } 2824 2825 ql_dbg(ql_dbg_init, vha, 0x0078, 2826 "Verifying loaded RISC code...\n"); 2827 2828 /* If smartsan enabled then require fdmi and rdp enabled */ 2829 if (ql2xsmartsan) { 2830 ql2xfdmienable = 1; 2831 ql2xrdpenable = 1; 2832 } 2833 2834 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) { 2835 rval = ha->isp_ops->chip_diag(vha); 2836 if (rval) 2837 return (rval); 2838 rval = qla2x00_setup_chip(vha); 2839 if (rval) 2840 return (rval); 2841 } 2842 2843 if (IS_QLA84XX(ha)) { 2844 ha->cs84xx = qla84xx_get_chip(vha); 2845 if (!ha->cs84xx) { 2846 ql_log(ql_log_warn, vha, 0x00d0, 2847 "Unable to configure ISP84XX.\n"); 2848 return QLA_FUNCTION_FAILED; 2849 } 2850 } 2851 2852 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha)) 2853 rval = qla2x00_init_rings(vha); 2854 2855 /* No point in continuing if firmware initialization failed. */ 2856 if (rval != QLA_SUCCESS) 2857 return rval; 2858 2859 ha->flags.chip_reset_done = 1; 2860 2861 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) { 2862 /* Issue verify 84xx FW IOCB to complete 84xx initialization */ 2863 rval = qla84xx_init_chip(vha); 2864 if (rval != QLA_SUCCESS) { 2865 ql_log(ql_log_warn, vha, 0x00d4, 2866 "Unable to initialize ISP84XX.\n"); 2867 qla84xx_put_chip(vha); 2868 } 2869 } 2870 2871 /* Load the NIC Core f/w if we are the first protocol driver. */ 2872 if (IS_QLA8031(ha)) { 2873 rval = qla83xx_nic_core_fw_load(vha); 2874 if (rval) 2875 ql_log(ql_log_warn, vha, 0x0124, 2876 "Error in initializing NIC Core f/w.\n"); 2877 } 2878 2879 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha)) 2880 qla24xx_read_fcp_prio_cfg(vha); 2881 2882 if (IS_P3P_TYPE(ha)) 2883 qla82xx_set_driver_version(vha, QLA2XXX_VERSION); 2884 else 2885 qla25xx_set_driver_version(vha, QLA2XXX_VERSION); 2886 2887 return (rval); 2888 } 2889 2890 /** 2891 * qla2100_pci_config() - Setup ISP21xx PCI configuration registers. 2892 * @vha: HA context 2893 * 2894 * Returns 0 on success. 2895 */ 2896 int 2897 qla2100_pci_config(scsi_qla_host_t *vha) 2898 { 2899 uint16_t w; 2900 unsigned long flags; 2901 struct qla_hw_data *ha = vha->hw; 2902 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2903 2904 pci_set_master(ha->pdev); 2905 pci_try_set_mwi(ha->pdev); 2906 2907 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2908 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2909 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2910 2911 pci_disable_rom(ha->pdev); 2912 2913 /* Get PCI bus information. */ 2914 spin_lock_irqsave(&ha->hardware_lock, flags); 2915 ha->pci_attr = rd_reg_word(®->ctrl_status); 2916 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2917 2918 return QLA_SUCCESS; 2919 } 2920 2921 /** 2922 * qla2300_pci_config() - Setup ISP23xx PCI configuration registers. 2923 * @vha: HA context 2924 * 2925 * Returns 0 on success. 2926 */ 2927 int 2928 qla2300_pci_config(scsi_qla_host_t *vha) 2929 { 2930 uint16_t w; 2931 unsigned long flags = 0; 2932 uint32_t cnt; 2933 struct qla_hw_data *ha = vha->hw; 2934 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2935 2936 pci_set_master(ha->pdev); 2937 pci_try_set_mwi(ha->pdev); 2938 2939 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 2940 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 2941 2942 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 2943 w &= ~PCI_COMMAND_INTX_DISABLE; 2944 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 2945 2946 /* 2947 * If this is a 2300 card and not 2312, reset the 2948 * COMMAND_INVALIDATE due to a bug in the 2300. Unfortunately, 2949 * the 2310 also reports itself as a 2300 so we need to get the 2950 * fb revision level -- a 6 indicates it really is a 2300 and 2951 * not a 2310. 2952 */ 2953 if (IS_QLA2300(ha)) { 2954 spin_lock_irqsave(&ha->hardware_lock, flags); 2955 2956 /* Pause RISC. */ 2957 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 2958 for (cnt = 0; cnt < 30000; cnt++) { 2959 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0) 2960 break; 2961 2962 udelay(10); 2963 } 2964 2965 /* Select FPM registers. */ 2966 wrt_reg_word(®->ctrl_status, 0x20); 2967 rd_reg_word(®->ctrl_status); 2968 2969 /* Get the fb rev level */ 2970 ha->fb_rev = RD_FB_CMD_REG(ha, reg); 2971 2972 if (ha->fb_rev == FPM_2300) 2973 pci_clear_mwi(ha->pdev); 2974 2975 /* Deselect FPM registers. */ 2976 wrt_reg_word(®->ctrl_status, 0x0); 2977 rd_reg_word(®->ctrl_status); 2978 2979 /* Release RISC module. */ 2980 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 2981 for (cnt = 0; cnt < 30000; cnt++) { 2982 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0) 2983 break; 2984 2985 udelay(10); 2986 } 2987 2988 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2989 } 2990 2991 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 2992 2993 pci_disable_rom(ha->pdev); 2994 2995 /* Get PCI bus information. */ 2996 spin_lock_irqsave(&ha->hardware_lock, flags); 2997 ha->pci_attr = rd_reg_word(®->ctrl_status); 2998 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2999 3000 return QLA_SUCCESS; 3001 } 3002 3003 /** 3004 * qla24xx_pci_config() - Setup ISP24xx PCI configuration registers. 3005 * @vha: HA context 3006 * 3007 * Returns 0 on success. 3008 */ 3009 int 3010 qla24xx_pci_config(scsi_qla_host_t *vha) 3011 { 3012 uint16_t w; 3013 unsigned long flags = 0; 3014 struct qla_hw_data *ha = vha->hw; 3015 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 3016 3017 pci_set_master(ha->pdev); 3018 pci_try_set_mwi(ha->pdev); 3019 3020 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 3021 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 3022 w &= ~PCI_COMMAND_INTX_DISABLE; 3023 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 3024 3025 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80); 3026 3027 /* PCI-X -- adjust Maximum Memory Read Byte Count (2048). */ 3028 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX)) 3029 pcix_set_mmrbc(ha->pdev, 2048); 3030 3031 /* PCIe -- adjust Maximum Read Request Size (2048). */ 3032 if (pci_is_pcie(ha->pdev)) 3033 pcie_set_readrq(ha->pdev, 4096); 3034 3035 pci_disable_rom(ha->pdev); 3036 3037 ha->chip_revision = ha->pdev->revision; 3038 3039 /* Get PCI bus information. */ 3040 spin_lock_irqsave(&ha->hardware_lock, flags); 3041 ha->pci_attr = rd_reg_dword(®->ctrl_status); 3042 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3043 3044 return QLA_SUCCESS; 3045 } 3046 3047 /** 3048 * qla25xx_pci_config() - Setup ISP25xx PCI configuration registers. 3049 * @vha: HA context 3050 * 3051 * Returns 0 on success. 3052 */ 3053 int 3054 qla25xx_pci_config(scsi_qla_host_t *vha) 3055 { 3056 uint16_t w; 3057 struct qla_hw_data *ha = vha->hw; 3058 3059 pci_set_master(ha->pdev); 3060 pci_try_set_mwi(ha->pdev); 3061 3062 pci_read_config_word(ha->pdev, PCI_COMMAND, &w); 3063 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR); 3064 w &= ~PCI_COMMAND_INTX_DISABLE; 3065 pci_write_config_word(ha->pdev, PCI_COMMAND, w); 3066 3067 /* PCIe -- adjust Maximum Read Request Size (2048). */ 3068 if (pci_is_pcie(ha->pdev)) 3069 pcie_set_readrq(ha->pdev, 4096); 3070 3071 pci_disable_rom(ha->pdev); 3072 3073 ha->chip_revision = ha->pdev->revision; 3074 3075 return QLA_SUCCESS; 3076 } 3077 3078 /** 3079 * qla2x00_isp_firmware() - Choose firmware image. 3080 * @vha: HA context 3081 * 3082 * Returns 0 on success. 3083 */ 3084 static int 3085 qla2x00_isp_firmware(scsi_qla_host_t *vha) 3086 { 3087 int rval; 3088 uint16_t loop_id, topo, sw_cap; 3089 uint8_t domain, area, al_pa; 3090 struct qla_hw_data *ha = vha->hw; 3091 3092 /* Assume loading risc code */ 3093 rval = QLA_FUNCTION_FAILED; 3094 3095 if (ha->flags.disable_risc_code_load) { 3096 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n"); 3097 3098 /* Verify checksum of loaded RISC code. */ 3099 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address); 3100 if (rval == QLA_SUCCESS) { 3101 /* And, verify we are not in ROM code. */ 3102 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa, 3103 &area, &domain, &topo, &sw_cap); 3104 } 3105 } 3106 3107 if (rval) 3108 ql_dbg(ql_dbg_init, vha, 0x007a, 3109 "**** Load RISC code ****.\n"); 3110 3111 return (rval); 3112 } 3113 3114 /** 3115 * qla2x00_reset_chip() - Reset ISP chip. 3116 * @vha: HA context 3117 * 3118 * Returns 0 on success. 3119 */ 3120 int 3121 qla2x00_reset_chip(scsi_qla_host_t *vha) 3122 { 3123 unsigned long flags = 0; 3124 struct qla_hw_data *ha = vha->hw; 3125 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 3126 uint32_t cnt; 3127 uint16_t cmd; 3128 int rval = QLA_FUNCTION_FAILED; 3129 3130 if (unlikely(pci_channel_offline(ha->pdev))) 3131 return rval; 3132 3133 ha->isp_ops->disable_intrs(ha); 3134 3135 spin_lock_irqsave(&ha->hardware_lock, flags); 3136 3137 /* Turn off master enable */ 3138 cmd = 0; 3139 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd); 3140 cmd &= ~PCI_COMMAND_MASTER; 3141 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 3142 3143 if (!IS_QLA2100(ha)) { 3144 /* Pause RISC. */ 3145 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 3146 if (IS_QLA2200(ha) || IS_QLA2300(ha)) { 3147 for (cnt = 0; cnt < 30000; cnt++) { 3148 if ((rd_reg_word(®->hccr) & 3149 HCCR_RISC_PAUSE) != 0) 3150 break; 3151 udelay(100); 3152 } 3153 } else { 3154 rd_reg_word(®->hccr); /* PCI Posting. */ 3155 udelay(10); 3156 } 3157 3158 /* Select FPM registers. */ 3159 wrt_reg_word(®->ctrl_status, 0x20); 3160 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 3161 3162 /* FPM Soft Reset. */ 3163 wrt_reg_word(®->fpm_diag_config, 0x100); 3164 rd_reg_word(®->fpm_diag_config); /* PCI Posting. */ 3165 3166 /* Toggle Fpm Reset. */ 3167 if (!IS_QLA2200(ha)) { 3168 wrt_reg_word(®->fpm_diag_config, 0x0); 3169 rd_reg_word(®->fpm_diag_config); /* PCI Posting. */ 3170 } 3171 3172 /* Select frame buffer registers. */ 3173 wrt_reg_word(®->ctrl_status, 0x10); 3174 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 3175 3176 /* Reset frame buffer FIFOs. */ 3177 if (IS_QLA2200(ha)) { 3178 WRT_FB_CMD_REG(ha, reg, 0xa000); 3179 RD_FB_CMD_REG(ha, reg); /* PCI Posting. */ 3180 } else { 3181 WRT_FB_CMD_REG(ha, reg, 0x00fc); 3182 3183 /* Read back fb_cmd until zero or 3 seconds max */ 3184 for (cnt = 0; cnt < 3000; cnt++) { 3185 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0) 3186 break; 3187 udelay(100); 3188 } 3189 } 3190 3191 /* Select RISC module registers. */ 3192 wrt_reg_word(®->ctrl_status, 0); 3193 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 3194 3195 /* Reset RISC processor. */ 3196 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 3197 rd_reg_word(®->hccr); /* PCI Posting. */ 3198 3199 /* Release RISC processor. */ 3200 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 3201 rd_reg_word(®->hccr); /* PCI Posting. */ 3202 } 3203 3204 wrt_reg_word(®->hccr, HCCR_CLR_RISC_INT); 3205 wrt_reg_word(®->hccr, HCCR_CLR_HOST_INT); 3206 3207 /* Reset ISP chip. */ 3208 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 3209 3210 /* Wait for RISC to recover from reset. */ 3211 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 3212 /* 3213 * It is necessary to for a delay here since the card doesn't 3214 * respond to PCI reads during a reset. On some architectures 3215 * this will result in an MCA. 3216 */ 3217 udelay(20); 3218 for (cnt = 30000; cnt; cnt--) { 3219 if ((rd_reg_word(®->ctrl_status) & 3220 CSR_ISP_SOFT_RESET) == 0) 3221 break; 3222 udelay(100); 3223 } 3224 } else 3225 udelay(10); 3226 3227 /* Reset RISC processor. */ 3228 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 3229 3230 wrt_reg_word(®->semaphore, 0); 3231 3232 /* Release RISC processor. */ 3233 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 3234 rd_reg_word(®->hccr); /* PCI Posting. */ 3235 3236 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 3237 for (cnt = 0; cnt < 30000; cnt++) { 3238 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY) 3239 break; 3240 3241 udelay(100); 3242 } 3243 } else 3244 udelay(100); 3245 3246 /* Turn on master enable */ 3247 cmd |= PCI_COMMAND_MASTER; 3248 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd); 3249 3250 /* Disable RISC pause on FPM parity error. */ 3251 if (!IS_QLA2100(ha)) { 3252 wrt_reg_word(®->hccr, HCCR_DISABLE_PARITY_PAUSE); 3253 rd_reg_word(®->hccr); /* PCI Posting. */ 3254 } 3255 3256 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3257 3258 return QLA_SUCCESS; 3259 } 3260 3261 /** 3262 * qla81xx_reset_mpi() - Reset's MPI FW via Write MPI Register MBC. 3263 * @vha: HA context 3264 * 3265 * Returns 0 on success. 3266 */ 3267 static int 3268 qla81xx_reset_mpi(scsi_qla_host_t *vha) 3269 { 3270 uint16_t mb[4] = {0x1010, 0, 1, 0}; 3271 3272 if (!IS_QLA81XX(vha->hw)) 3273 return QLA_SUCCESS; 3274 3275 return qla81xx_write_mpi_register(vha, mb); 3276 } 3277 3278 static int 3279 qla_chk_risc_recovery(scsi_qla_host_t *vha) 3280 { 3281 struct qla_hw_data *ha = vha->hw; 3282 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 3283 __le16 __iomem *mbptr = ®->mailbox0; 3284 int i; 3285 u16 mb[32]; 3286 int rc = QLA_SUCCESS; 3287 3288 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 3289 return rc; 3290 3291 /* this check is only valid after RISC reset */ 3292 mb[0] = rd_reg_word(mbptr); 3293 mbptr++; 3294 if (mb[0] == 0xf) { 3295 rc = QLA_FUNCTION_FAILED; 3296 3297 for (i = 1; i < 32; i++) { 3298 mb[i] = rd_reg_word(mbptr); 3299 mbptr++; 3300 } 3301 3302 ql_log(ql_log_warn, vha, 0x1015, 3303 "RISC reset failed. mb[0-7] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 3304 mb[0], mb[1], mb[2], mb[3], mb[4], mb[5], mb[6], mb[7]); 3305 ql_log(ql_log_warn, vha, 0x1015, 3306 "RISC reset failed. mb[8-15] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 3307 mb[8], mb[9], mb[10], mb[11], mb[12], mb[13], mb[14], 3308 mb[15]); 3309 ql_log(ql_log_warn, vha, 0x1015, 3310 "RISC reset failed. mb[16-23] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 3311 mb[16], mb[17], mb[18], mb[19], mb[20], mb[21], mb[22], 3312 mb[23]); 3313 ql_log(ql_log_warn, vha, 0x1015, 3314 "RISC reset failed. mb[24-31] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n", 3315 mb[24], mb[25], mb[26], mb[27], mb[28], mb[29], mb[30], 3316 mb[31]); 3317 } 3318 return rc; 3319 } 3320 3321 /** 3322 * qla24xx_reset_risc() - Perform full reset of ISP24xx RISC. 3323 * @vha: HA context 3324 * 3325 * Returns 0 on success. 3326 */ 3327 static inline int 3328 qla24xx_reset_risc(scsi_qla_host_t *vha) 3329 { 3330 unsigned long flags = 0; 3331 struct qla_hw_data *ha = vha->hw; 3332 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 3333 uint32_t cnt; 3334 uint16_t wd; 3335 static int abts_cnt; /* ISP abort retry counts */ 3336 int rval = QLA_SUCCESS; 3337 int print = 1; 3338 3339 spin_lock_irqsave(&ha->hardware_lock, flags); 3340 3341 /* Reset RISC. */ 3342 wrt_reg_dword(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 3343 for (cnt = 0; cnt < 30000; cnt++) { 3344 if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0) 3345 break; 3346 3347 udelay(10); 3348 } 3349 3350 if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)) 3351 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags); 3352 3353 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e, 3354 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n", 3355 rd_reg_dword(®->hccr), 3356 rd_reg_dword(®->ctrl_status), 3357 (rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE)); 3358 3359 wrt_reg_dword(®->ctrl_status, 3360 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES); 3361 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 3362 3363 udelay(100); 3364 3365 /* Wait for firmware to complete NVRAM accesses. */ 3366 rd_reg_word(®->mailbox0); 3367 for (cnt = 10000; rd_reg_word(®->mailbox0) != 0 && 3368 rval == QLA_SUCCESS; cnt--) { 3369 barrier(); 3370 if (cnt) 3371 udelay(5); 3372 else 3373 rval = QLA_FUNCTION_TIMEOUT; 3374 } 3375 3376 if (rval == QLA_SUCCESS) 3377 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags); 3378 3379 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f, 3380 "HCCR: 0x%x, MailBox0 Status 0x%x\n", 3381 rd_reg_dword(®->hccr), 3382 rd_reg_word(®->mailbox0)); 3383 3384 /* Wait for soft-reset to complete. */ 3385 rd_reg_dword(®->ctrl_status); 3386 for (cnt = 0; cnt < 60; cnt++) { 3387 barrier(); 3388 if ((rd_reg_dword(®->ctrl_status) & 3389 CSRX_ISP_SOFT_RESET) == 0) 3390 break; 3391 3392 udelay(5); 3393 } 3394 if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET)) 3395 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags); 3396 3397 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d, 3398 "HCCR: 0x%x, Soft Reset status: 0x%x\n", 3399 rd_reg_dword(®->hccr), 3400 rd_reg_dword(®->ctrl_status)); 3401 3402 /* If required, do an MPI FW reset now */ 3403 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) { 3404 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) { 3405 if (++abts_cnt < 5) { 3406 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3407 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags); 3408 } else { 3409 /* 3410 * We exhausted the ISP abort retries. We have to 3411 * set the board offline. 3412 */ 3413 abts_cnt = 0; 3414 vha->flags.online = 0; 3415 } 3416 } 3417 } 3418 3419 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET); 3420 rd_reg_dword(®->hccr); 3421 3422 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE); 3423 rd_reg_dword(®->hccr); 3424 3425 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_RESET); 3426 mdelay(10); 3427 rd_reg_dword(®->hccr); 3428 3429 wd = rd_reg_word(®->mailbox0); 3430 for (cnt = 300; wd != 0 && rval == QLA_SUCCESS; cnt--) { 3431 barrier(); 3432 if (cnt) { 3433 mdelay(1); 3434 if (print && qla_chk_risc_recovery(vha)) 3435 print = 0; 3436 3437 wd = rd_reg_word(®->mailbox0); 3438 } else { 3439 rval = QLA_FUNCTION_TIMEOUT; 3440 3441 ql_log(ql_log_warn, vha, 0x015e, 3442 "RISC reset timeout\n"); 3443 } 3444 } 3445 3446 if (rval == QLA_SUCCESS) 3447 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags); 3448 3449 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e, 3450 "Host Risc 0x%x, mailbox0 0x%x\n", 3451 rd_reg_dword(®->hccr), 3452 rd_reg_word(®->mailbox0)); 3453 3454 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3455 3456 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f, 3457 "Driver in %s mode\n", 3458 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling"); 3459 3460 if (IS_NOPOLLING_TYPE(ha)) 3461 ha->isp_ops->enable_intrs(ha); 3462 3463 return rval; 3464 } 3465 3466 static void 3467 qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data) 3468 { 3469 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 3470 3471 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 3472 *data = rd_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET); 3473 } 3474 3475 static void 3476 qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data) 3477 { 3478 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24; 3479 3480 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET); 3481 wrt_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET, data); 3482 } 3483 3484 static void 3485 qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha) 3486 { 3487 uint32_t wd32 = 0; 3488 uint delta_msec = 100; 3489 uint elapsed_msec = 0; 3490 uint timeout_msec; 3491 ulong n; 3492 3493 if (vha->hw->pdev->subsystem_device != 0x0175 && 3494 vha->hw->pdev->subsystem_device != 0x0240) 3495 return; 3496 3497 wrt_reg_dword(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE); 3498 udelay(100); 3499 3500 attempt: 3501 timeout_msec = TIMEOUT_SEMAPHORE; 3502 n = timeout_msec / delta_msec; 3503 while (n--) { 3504 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET); 3505 qla25xx_read_risc_sema_reg(vha, &wd32); 3506 if (wd32 & RISC_SEMAPHORE) 3507 break; 3508 msleep(delta_msec); 3509 elapsed_msec += delta_msec; 3510 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 3511 goto force; 3512 } 3513 3514 if (!(wd32 & RISC_SEMAPHORE)) 3515 goto force; 3516 3517 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 3518 goto acquired; 3519 3520 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR); 3521 timeout_msec = TIMEOUT_SEMAPHORE_FORCE; 3522 n = timeout_msec / delta_msec; 3523 while (n--) { 3524 qla25xx_read_risc_sema_reg(vha, &wd32); 3525 if (!(wd32 & RISC_SEMAPHORE_FORCE)) 3526 break; 3527 msleep(delta_msec); 3528 elapsed_msec += delta_msec; 3529 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED) 3530 goto force; 3531 } 3532 3533 if (wd32 & RISC_SEMAPHORE_FORCE) 3534 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR); 3535 3536 goto attempt; 3537 3538 force: 3539 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET); 3540 3541 acquired: 3542 return; 3543 } 3544 3545 /** 3546 * qla24xx_reset_chip() - Reset ISP24xx chip. 3547 * @vha: HA context 3548 * 3549 * Returns 0 on success. 3550 */ 3551 int 3552 qla24xx_reset_chip(scsi_qla_host_t *vha) 3553 { 3554 struct qla_hw_data *ha = vha->hw; 3555 int rval = QLA_FUNCTION_FAILED; 3556 3557 if (pci_channel_offline(ha->pdev) && 3558 ha->flags.pci_channel_io_perm_failure) { 3559 return rval; 3560 } 3561 3562 ha->isp_ops->disable_intrs(ha); 3563 3564 qla25xx_manipulate_risc_semaphore(vha); 3565 3566 /* Perform RISC reset. */ 3567 rval = qla24xx_reset_risc(vha); 3568 3569 return rval; 3570 } 3571 3572 /** 3573 * qla2x00_chip_diag() - Test chip for proper operation. 3574 * @vha: HA context 3575 * 3576 * Returns 0 on success. 3577 */ 3578 int 3579 qla2x00_chip_diag(scsi_qla_host_t *vha) 3580 { 3581 int rval; 3582 struct qla_hw_data *ha = vha->hw; 3583 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 3584 unsigned long flags = 0; 3585 uint16_t data; 3586 uint32_t cnt; 3587 uint16_t mb[5]; 3588 struct req_que *req = ha->req_q_map[0]; 3589 3590 /* Assume a failed state */ 3591 rval = QLA_FUNCTION_FAILED; 3592 3593 ql_dbg(ql_dbg_init, vha, 0x007b, "Testing device at %p.\n", 3594 ®->flash_address); 3595 3596 spin_lock_irqsave(&ha->hardware_lock, flags); 3597 3598 /* Reset ISP chip. */ 3599 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 3600 3601 /* 3602 * We need to have a delay here since the card will not respond while 3603 * in reset causing an MCA on some architectures. 3604 */ 3605 udelay(20); 3606 data = qla2x00_debounce_register(®->ctrl_status); 3607 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) { 3608 udelay(5); 3609 data = rd_reg_word(®->ctrl_status); 3610 barrier(); 3611 } 3612 3613 if (!cnt) 3614 goto chip_diag_failed; 3615 3616 ql_dbg(ql_dbg_init, vha, 0x007c, 3617 "Reset register cleared by chip reset.\n"); 3618 3619 /* Reset RISC processor. */ 3620 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 3621 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 3622 3623 /* Workaround for QLA2312 PCI parity error */ 3624 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 3625 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0)); 3626 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) { 3627 udelay(5); 3628 data = RD_MAILBOX_REG(ha, reg, 0); 3629 barrier(); 3630 } 3631 } else 3632 udelay(10); 3633 3634 if (!cnt) 3635 goto chip_diag_failed; 3636 3637 /* Check product ID of chip */ 3638 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n"); 3639 3640 mb[1] = RD_MAILBOX_REG(ha, reg, 1); 3641 mb[2] = RD_MAILBOX_REG(ha, reg, 2); 3642 mb[3] = RD_MAILBOX_REG(ha, reg, 3); 3643 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4)); 3644 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) || 3645 mb[3] != PROD_ID_3) { 3646 ql_log(ql_log_warn, vha, 0x0062, 3647 "Wrong product ID = 0x%x,0x%x,0x%x.\n", 3648 mb[1], mb[2], mb[3]); 3649 3650 goto chip_diag_failed; 3651 } 3652 ha->product_id[0] = mb[1]; 3653 ha->product_id[1] = mb[2]; 3654 ha->product_id[2] = mb[3]; 3655 ha->product_id[3] = mb[4]; 3656 3657 /* Adjust fw RISC transfer size */ 3658 if (req->length > 1024) 3659 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024; 3660 else 3661 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 3662 req->length; 3663 3664 if (IS_QLA2200(ha) && 3665 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) { 3666 /* Limit firmware transfer size with a 2200A */ 3667 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n"); 3668 3669 ha->device_type |= DT_ISP2200A; 3670 ha->fw_transfer_size = 128; 3671 } 3672 3673 /* Wrap Incoming Mailboxes Test. */ 3674 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3675 3676 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n"); 3677 rval = qla2x00_mbx_reg_test(vha); 3678 if (rval) 3679 ql_log(ql_log_warn, vha, 0x0080, 3680 "Failed mailbox send register test.\n"); 3681 else 3682 /* Flag a successful rval */ 3683 rval = QLA_SUCCESS; 3684 spin_lock_irqsave(&ha->hardware_lock, flags); 3685 3686 chip_diag_failed: 3687 if (rval) 3688 ql_log(ql_log_info, vha, 0x0081, 3689 "Chip diagnostics **** FAILED ****.\n"); 3690 3691 spin_unlock_irqrestore(&ha->hardware_lock, flags); 3692 3693 return (rval); 3694 } 3695 3696 /** 3697 * qla24xx_chip_diag() - Test ISP24xx for proper operation. 3698 * @vha: HA context 3699 * 3700 * Returns 0 on success. 3701 */ 3702 int 3703 qla24xx_chip_diag(scsi_qla_host_t *vha) 3704 { 3705 int rval; 3706 struct qla_hw_data *ha = vha->hw; 3707 struct req_que *req = ha->req_q_map[0]; 3708 3709 if (IS_P3P_TYPE(ha)) 3710 return QLA_SUCCESS; 3711 3712 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length; 3713 3714 rval = qla2x00_mbx_reg_test(vha); 3715 if (rval) { 3716 ql_log(ql_log_warn, vha, 0x0082, 3717 "Failed mailbox send register test.\n"); 3718 } else { 3719 /* Flag a successful rval */ 3720 rval = QLA_SUCCESS; 3721 } 3722 3723 return rval; 3724 } 3725 3726 int qla2x00_alloc_fce_trace(scsi_qla_host_t *vha) 3727 { 3728 dma_addr_t tc_dma; 3729 void *tc; 3730 struct qla_hw_data *ha = vha->hw; 3731 3732 if (!IS_FWI2_CAPABLE(ha)) 3733 return -EINVAL; 3734 3735 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && 3736 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 3737 return -EINVAL; 3738 3739 if (ha->fce) { 3740 ql_dbg(ql_dbg_init, vha, 0x00bd, 3741 "%s: FCE Mem is already allocated.\n", 3742 __func__); 3743 return -EIO; 3744 } 3745 3746 /* Allocate memory for Fibre Channel Event Buffer. */ 3747 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma, 3748 GFP_KERNEL); 3749 if (!tc) { 3750 ql_log(ql_log_warn, vha, 0x00be, 3751 "Unable to allocate (%d KB) for FCE.\n", 3752 FCE_SIZE / 1024); 3753 return -ENOMEM; 3754 } 3755 3756 ql_dbg(ql_dbg_init, vha, 0x00c0, 3757 "Allocated (%d KB) for FCE...\n", FCE_SIZE / 1024); 3758 3759 ha->fce_dma = tc_dma; 3760 ha->fce = tc; 3761 ha->fce_bufs = FCE_NUM_BUFFERS; 3762 return 0; 3763 } 3764 3765 void qla2x00_free_fce_trace(struct qla_hw_data *ha) 3766 { 3767 if (!ha->fce) 3768 return; 3769 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, ha->fce, ha->fce_dma); 3770 ha->fce = NULL; 3771 ha->fce_dma = 0; 3772 } 3773 3774 static void 3775 qla2x00_alloc_eft_trace(scsi_qla_host_t *vha) 3776 { 3777 dma_addr_t tc_dma; 3778 void *tc; 3779 struct qla_hw_data *ha = vha->hw; 3780 3781 if (!IS_FWI2_CAPABLE(ha)) 3782 return; 3783 3784 if (ha->eft) { 3785 ql_dbg(ql_dbg_init, vha, 0x00bd, 3786 "%s: EFT Mem is already allocated.\n", 3787 __func__); 3788 return; 3789 } 3790 3791 /* Allocate memory for Extended Trace Buffer. */ 3792 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma, 3793 GFP_KERNEL); 3794 if (!tc) { 3795 ql_log(ql_log_warn, vha, 0x00c1, 3796 "Unable to allocate (%d KB) for EFT.\n", 3797 EFT_SIZE / 1024); 3798 return; 3799 } 3800 3801 ql_dbg(ql_dbg_init, vha, 0x00c3, 3802 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024); 3803 3804 ha->eft_dma = tc_dma; 3805 ha->eft = tc; 3806 } 3807 3808 void 3809 qla2x00_alloc_fw_dump(scsi_qla_host_t *vha) 3810 { 3811 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size, 3812 eft_size, fce_size, mq_size; 3813 struct qla_hw_data *ha = vha->hw; 3814 struct req_que *req = ha->req_q_map[0]; 3815 struct rsp_que *rsp = ha->rsp_q_map[0]; 3816 struct qla2xxx_fw_dump *fw_dump; 3817 3818 if (ha->fw_dump) { 3819 ql_dbg(ql_dbg_init, vha, 0x00bd, 3820 "Firmware dump already allocated.\n"); 3821 return; 3822 } 3823 3824 ha->fw_dumped = 0; 3825 ha->fw_dump_cap_flags = 0; 3826 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0; 3827 req_q_size = rsp_q_size = 0; 3828 3829 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 3830 fixed_size = sizeof(struct qla2100_fw_dump); 3831 } else if (IS_QLA23XX(ha)) { 3832 fixed_size = offsetof(struct qla2300_fw_dump, data_ram); 3833 mem_size = (ha->fw_memory_size - 0x11000 + 1) * 3834 sizeof(uint16_t); 3835 } else if (IS_FWI2_CAPABLE(ha)) { 3836 if (IS_QLA83XX(ha)) 3837 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem); 3838 else if (IS_QLA81XX(ha)) 3839 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem); 3840 else if (IS_QLA25XX(ha)) 3841 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem); 3842 else 3843 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem); 3844 3845 mem_size = (ha->fw_memory_size - 0x100000 + 1) * 3846 sizeof(uint32_t); 3847 if (ha->mqenable) { 3848 if (!IS_QLA83XX(ha)) 3849 mq_size = sizeof(struct qla2xxx_mq_chain); 3850 /* 3851 * Allocate maximum buffer size for all queues - Q0. 3852 * Resizing must be done at end-of-dump processing. 3853 */ 3854 mq_size += (ha->max_req_queues - 1) * 3855 (req->length * sizeof(request_t)); 3856 mq_size += (ha->max_rsp_queues - 1) * 3857 (rsp->length * sizeof(response_t)); 3858 } 3859 if (ha->tgt.atio_ring) 3860 mq_size += ha->tgt.atio_q_length * sizeof(request_t); 3861 3862 if (ha->fce) { 3863 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE; 3864 ha->flags.fce_dump_buf_alloced = 1; 3865 } 3866 qla2x00_alloc_eft_trace(vha); 3867 if (ha->eft) 3868 eft_size = EFT_SIZE; 3869 } 3870 3871 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3872 struct fwdt *fwdt = ha->fwdt; 3873 uint j; 3874 3875 for (j = 0; j < 2; j++, fwdt++) { 3876 if (!fwdt->template) { 3877 ql_dbg(ql_dbg_init, vha, 0x00ba, 3878 "-> fwdt%u no template\n", j); 3879 continue; 3880 } 3881 ql_dbg(ql_dbg_init, vha, 0x00fa, 3882 "-> fwdt%u calculating fwdump size...\n", j); 3883 fwdt->dump_size = qla27xx_fwdt_calculate_dump_size( 3884 vha, fwdt->template); 3885 ql_dbg(ql_dbg_init, vha, 0x00fa, 3886 "-> fwdt%u calculated fwdump size = %#lx bytes\n", 3887 j, fwdt->dump_size); 3888 dump_size += fwdt->dump_size; 3889 } 3890 /* Add space for spare MPI fw dump. */ 3891 dump_size += ha->fwdt[1].dump_size; 3892 } else { 3893 req_q_size = req->length * sizeof(request_t); 3894 rsp_q_size = rsp->length * sizeof(response_t); 3895 dump_size = offsetof(struct qla2xxx_fw_dump, isp); 3896 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size 3897 + eft_size; 3898 ha->chain_offset = dump_size; 3899 dump_size += mq_size + fce_size; 3900 if (ha->exchoffld_buf) 3901 dump_size += sizeof(struct qla2xxx_offld_chain) + 3902 ha->exchoffld_size; 3903 if (ha->exlogin_buf) 3904 dump_size += sizeof(struct qla2xxx_offld_chain) + 3905 ha->exlogin_size; 3906 } 3907 3908 if (!ha->fw_dump_len || dump_size > ha->fw_dump_alloc_len) { 3909 3910 ql_dbg(ql_dbg_init, vha, 0x00c5, 3911 "%s dump_size %d fw_dump_len %d fw_dump_alloc_len %d\n", 3912 __func__, dump_size, ha->fw_dump_len, 3913 ha->fw_dump_alloc_len); 3914 3915 fw_dump = vmalloc(dump_size); 3916 if (!fw_dump) { 3917 ql_log(ql_log_warn, vha, 0x00c4, 3918 "Unable to allocate (%d KB) for firmware dump.\n", 3919 dump_size / 1024); 3920 } else { 3921 mutex_lock(&ha->optrom_mutex); 3922 if (ha->fw_dumped) { 3923 memcpy(fw_dump, ha->fw_dump, ha->fw_dump_len); 3924 vfree(ha->fw_dump); 3925 ha->fw_dump = fw_dump; 3926 ha->fw_dump_alloc_len = dump_size; 3927 ql_dbg(ql_dbg_init, vha, 0x00c5, 3928 "Re-Allocated (%d KB) and save firmware dump.\n", 3929 dump_size / 1024); 3930 } else { 3931 vfree(ha->fw_dump); 3932 ha->fw_dump = fw_dump; 3933 3934 ha->fw_dump_len = ha->fw_dump_alloc_len = 3935 dump_size; 3936 ql_dbg(ql_dbg_init, vha, 0x00c5, 3937 "Allocated (%d KB) for firmware dump.\n", 3938 dump_size / 1024); 3939 3940 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3941 ha->mpi_fw_dump = (char *)fw_dump + 3942 ha->fwdt[1].dump_size; 3943 mutex_unlock(&ha->optrom_mutex); 3944 return; 3945 } 3946 3947 ha->fw_dump->signature[0] = 'Q'; 3948 ha->fw_dump->signature[1] = 'L'; 3949 ha->fw_dump->signature[2] = 'G'; 3950 ha->fw_dump->signature[3] = 'C'; 3951 ha->fw_dump->version = htonl(1); 3952 3953 ha->fw_dump->fixed_size = htonl(fixed_size); 3954 ha->fw_dump->mem_size = htonl(mem_size); 3955 ha->fw_dump->req_q_size = htonl(req_q_size); 3956 ha->fw_dump->rsp_q_size = htonl(rsp_q_size); 3957 3958 ha->fw_dump->eft_size = htonl(eft_size); 3959 ha->fw_dump->eft_addr_l = 3960 htonl(LSD(ha->eft_dma)); 3961 ha->fw_dump->eft_addr_h = 3962 htonl(MSD(ha->eft_dma)); 3963 3964 ha->fw_dump->header_size = 3965 htonl(offsetof 3966 (struct qla2xxx_fw_dump, isp)); 3967 } 3968 mutex_unlock(&ha->optrom_mutex); 3969 } 3970 } 3971 } 3972 3973 static int 3974 qla81xx_mpi_sync(scsi_qla_host_t *vha) 3975 { 3976 #define MPS_MASK 0xe0 3977 int rval; 3978 uint16_t dc; 3979 uint32_t dw; 3980 3981 if (!IS_QLA81XX(vha->hw)) 3982 return QLA_SUCCESS; 3983 3984 rval = qla2x00_write_ram_word(vha, 0x7c00, 1); 3985 if (rval != QLA_SUCCESS) { 3986 ql_log(ql_log_warn, vha, 0x0105, 3987 "Unable to acquire semaphore.\n"); 3988 goto done; 3989 } 3990 3991 pci_read_config_word(vha->hw->pdev, 0x54, &dc); 3992 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw); 3993 if (rval != QLA_SUCCESS) { 3994 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n"); 3995 goto done_release; 3996 } 3997 3998 dc &= MPS_MASK; 3999 if (dc == (dw & MPS_MASK)) 4000 goto done_release; 4001 4002 dw &= ~MPS_MASK; 4003 dw |= dc; 4004 rval = qla2x00_write_ram_word(vha, 0x7a15, dw); 4005 if (rval != QLA_SUCCESS) { 4006 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n"); 4007 } 4008 4009 done_release: 4010 rval = qla2x00_write_ram_word(vha, 0x7c00, 0); 4011 if (rval != QLA_SUCCESS) { 4012 ql_log(ql_log_warn, vha, 0x006d, 4013 "Unable to release semaphore.\n"); 4014 } 4015 4016 done: 4017 return rval; 4018 } 4019 4020 int 4021 qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req) 4022 { 4023 /* Don't try to reallocate the array */ 4024 if (req->outstanding_cmds) 4025 return QLA_SUCCESS; 4026 4027 if (!IS_FWI2_CAPABLE(ha)) 4028 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS; 4029 else { 4030 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count) 4031 req->num_outstanding_cmds = ha->cur_fw_xcb_count; 4032 else 4033 req->num_outstanding_cmds = ha->cur_fw_iocb_count; 4034 } 4035 4036 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds, 4037 sizeof(srb_t *), 4038 GFP_KERNEL); 4039 4040 if (!req->outstanding_cmds) { 4041 /* 4042 * Try to allocate a minimal size just so we can get through 4043 * initialization. 4044 */ 4045 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS; 4046 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds, 4047 sizeof(srb_t *), 4048 GFP_KERNEL); 4049 4050 if (!req->outstanding_cmds) { 4051 ql_log(ql_log_fatal, NULL, 0x0126, 4052 "Failed to allocate memory for " 4053 "outstanding_cmds for req_que %p.\n", req); 4054 req->num_outstanding_cmds = 0; 4055 return QLA_FUNCTION_FAILED; 4056 } 4057 } 4058 4059 return QLA_SUCCESS; 4060 } 4061 4062 #define PRINT_FIELD(_field, _flag, _str) { \ 4063 if (a0->_field & _flag) {\ 4064 if (p) {\ 4065 strcat(ptr, "|");\ 4066 ptr++;\ 4067 leftover--;\ 4068 } \ 4069 len = snprintf(ptr, leftover, "%s", _str); \ 4070 p = 1;\ 4071 leftover -= len;\ 4072 ptr += len; \ 4073 } \ 4074 } 4075 4076 static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha) 4077 { 4078 #define STR_LEN 64 4079 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data; 4080 u8 str[STR_LEN], *ptr, p; 4081 int leftover, len; 4082 4083 ql_dbg(ql_dbg_init, vha, 0x015a, 4084 "SFP: %.*s -> %.*s ->%s%s%s%s%s%s%s\n", 4085 (int)sizeof(a0->vendor_name), a0->vendor_name, 4086 (int)sizeof(a0->vendor_pn), a0->vendor_pn, 4087 a0->fc_sp_cc10 & FC_SP_2 ? a0->fiber_channel_speed2 & FC_SP_64 ? 4088 " 64G" : "" : "", 4089 a0->fc_sp_cc10 & FC_SP_32 ? " 32G" : "", 4090 a0->fc_sp_cc10 & FC_SP_16 ? " 16G" : "", 4091 a0->fc_sp_cc10 & FC_SP_8 ? " 8G" : "", 4092 a0->fc_sp_cc10 & FC_SP_4 ? " 4G" : "", 4093 a0->fc_sp_cc10 & FC_SP_2 ? " 2G" : "", 4094 a0->fc_sp_cc10 & FC_SP_1 ? " 1G" : ""); 4095 4096 if (!(ql2xextended_error_logging & ql_dbg_verbose)) 4097 return; 4098 4099 memset(str, 0, STR_LEN); 4100 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name); 4101 ql_dbg(ql_dbg_init, vha, 0x015a, 4102 "SFP MFG Name: %s\n", str); 4103 4104 memset(str, 0, STR_LEN); 4105 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn); 4106 ql_dbg(ql_dbg_init, vha, 0x015c, 4107 "SFP Part Name: %s\n", str); 4108 4109 /* media */ 4110 memset(str, 0, STR_LEN); 4111 ptr = str; 4112 leftover = STR_LEN; 4113 p = len = 0; 4114 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX"); 4115 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair"); 4116 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax"); 4117 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax"); 4118 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um"); 4119 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um"); 4120 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode"); 4121 ql_dbg(ql_dbg_init, vha, 0x0160, 4122 "SFP Media: %s\n", str); 4123 4124 /* link length */ 4125 memset(str, 0, STR_LEN); 4126 ptr = str; 4127 leftover = STR_LEN; 4128 p = len = 0; 4129 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long"); 4130 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short"); 4131 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate"); 4132 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long"); 4133 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium"); 4134 ql_dbg(ql_dbg_init, vha, 0x0196, 4135 "SFP Link Length: %s\n", str); 4136 4137 memset(str, 0, STR_LEN); 4138 ptr = str; 4139 leftover = STR_LEN; 4140 p = len = 0; 4141 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)"); 4142 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)"); 4143 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)"); 4144 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)"); 4145 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)"); 4146 ql_dbg(ql_dbg_init, vha, 0x016e, 4147 "SFP FC Link Tech: %s\n", str); 4148 4149 if (a0->length_km) 4150 ql_dbg(ql_dbg_init, vha, 0x016f, 4151 "SFP Distant: %d km\n", a0->length_km); 4152 if (a0->length_100m) 4153 ql_dbg(ql_dbg_init, vha, 0x0170, 4154 "SFP Distant: %d m\n", a0->length_100m*100); 4155 if (a0->length_50um_10m) 4156 ql_dbg(ql_dbg_init, vha, 0x0189, 4157 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10); 4158 if (a0->length_62um_10m) 4159 ql_dbg(ql_dbg_init, vha, 0x018a, 4160 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10); 4161 if (a0->length_om4_10m) 4162 ql_dbg(ql_dbg_init, vha, 0x0194, 4163 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10); 4164 if (a0->length_om3_10m) 4165 ql_dbg(ql_dbg_init, vha, 0x0195, 4166 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10); 4167 } 4168 4169 4170 /** 4171 * qla24xx_detect_sfp() 4172 * 4173 * @vha: adapter state pointer. 4174 * 4175 * @return 4176 * 0 -- Configure firmware to use short-range settings -- normal 4177 * buffer-to-buffer credits. 4178 * 4179 * 1 -- Configure firmware to use long-range settings -- extra 4180 * buffer-to-buffer credits should be allocated with 4181 * ha->lr_distance containing distance settings from NVRAM or SFP 4182 * (if supported). 4183 */ 4184 int 4185 qla24xx_detect_sfp(scsi_qla_host_t *vha) 4186 { 4187 int rc, used_nvram; 4188 struct sff_8247_a0 *a; 4189 struct qla_hw_data *ha = vha->hw; 4190 struct nvram_81xx *nv = ha->nvram; 4191 #define LR_DISTANCE_UNKNOWN 2 4192 static const char * const types[] = { "Short", "Long" }; 4193 static const char * const lengths[] = { "(10km)", "(5km)", "" }; 4194 u8 ll = 0; 4195 4196 /* Seed with NVRAM settings. */ 4197 used_nvram = 0; 4198 ha->flags.lr_detected = 0; 4199 if (IS_BPM_RANGE_CAPABLE(ha) && 4200 (nv->enhanced_features & NEF_LR_DIST_ENABLE)) { 4201 used_nvram = 1; 4202 ha->flags.lr_detected = 1; 4203 ha->lr_distance = 4204 (nv->enhanced_features >> LR_DIST_NV_POS) 4205 & LR_DIST_NV_MASK; 4206 } 4207 4208 if (!IS_BPM_ENABLED(vha)) 4209 goto out; 4210 /* Determine SR/LR capabilities of SFP/Transceiver. */ 4211 rc = qla2x00_read_sfp_dev(vha, NULL, 0); 4212 if (rc) 4213 goto out; 4214 4215 used_nvram = 0; 4216 a = (struct sff_8247_a0 *)vha->hw->sfp_data; 4217 qla2xxx_print_sfp_info(vha); 4218 4219 ha->flags.lr_detected = 0; 4220 ll = a->fc_ll_cc7; 4221 if (ll & FC_LL_VL || ll & FC_LL_L) { 4222 /* Long range, track length. */ 4223 ha->flags.lr_detected = 1; 4224 4225 if (a->length_km > 5 || a->length_100m > 50) 4226 ha->lr_distance = LR_DISTANCE_10K; 4227 else 4228 ha->lr_distance = LR_DISTANCE_5K; 4229 } 4230 4231 out: 4232 ql_dbg(ql_dbg_async, vha, 0x507b, 4233 "SFP detect: %s-Range SFP %s (nvr=%x ll=%x lr=%x lrd=%x).\n", 4234 types[ha->flags.lr_detected], 4235 ha->flags.lr_detected ? lengths[ha->lr_distance] : 4236 lengths[LR_DISTANCE_UNKNOWN], 4237 used_nvram, ll, ha->flags.lr_detected, ha->lr_distance); 4238 return ha->flags.lr_detected; 4239 } 4240 4241 static void __qla_adjust_iocb_limit(struct qla_qpair *qpair) 4242 { 4243 u8 num_qps; 4244 u16 limit; 4245 struct qla_hw_data *ha = qpair->vha->hw; 4246 4247 num_qps = ha->num_qpairs + 1; 4248 limit = (ha->orig_fw_iocb_count * QLA_IOCB_PCT_LIMIT) / 100; 4249 4250 qpair->fwres.iocbs_total = ha->orig_fw_iocb_count; 4251 qpair->fwres.iocbs_limit = limit; 4252 qpair->fwres.iocbs_qp_limit = limit / num_qps; 4253 4254 qpair->fwres.exch_total = ha->orig_fw_xcb_count; 4255 qpair->fwres.exch_limit = (ha->orig_fw_xcb_count * 4256 QLA_IOCB_PCT_LIMIT) / 100; 4257 } 4258 4259 void qla_init_iocb_limit(scsi_qla_host_t *vha) 4260 { 4261 u8 i; 4262 struct qla_hw_data *ha = vha->hw; 4263 4264 __qla_adjust_iocb_limit(ha->base_qpair); 4265 ha->base_qpair->fwres.iocbs_used = 0; 4266 ha->base_qpair->fwres.exch_used = 0; 4267 4268 for (i = 0; i < ha->max_qpairs; i++) { 4269 if (ha->queue_pair_map[i]) { 4270 __qla_adjust_iocb_limit(ha->queue_pair_map[i]); 4271 ha->queue_pair_map[i]->fwres.iocbs_used = 0; 4272 ha->queue_pair_map[i]->fwres.exch_used = 0; 4273 } 4274 } 4275 4276 ha->fwres.iocb_total = ha->orig_fw_iocb_count; 4277 ha->fwres.iocb_limit = (ha->orig_fw_iocb_count * QLA_IOCB_PCT_LIMIT) / 100; 4278 ha->fwres.exch_total = ha->orig_fw_xcb_count; 4279 ha->fwres.exch_limit = (ha->orig_fw_xcb_count * QLA_IOCB_PCT_LIMIT) / 100; 4280 4281 atomic_set(&ha->fwres.iocb_used, 0); 4282 atomic_set(&ha->fwres.exch_used, 0); 4283 } 4284 4285 void qla_adjust_iocb_limit(scsi_qla_host_t *vha) 4286 { 4287 u8 i; 4288 struct qla_hw_data *ha = vha->hw; 4289 4290 __qla_adjust_iocb_limit(ha->base_qpair); 4291 4292 for (i = 0; i < ha->max_qpairs; i++) { 4293 if (ha->queue_pair_map[i]) 4294 __qla_adjust_iocb_limit(ha->queue_pair_map[i]); 4295 } 4296 } 4297 4298 /** 4299 * qla2x00_setup_chip() - Load and start RISC firmware. 4300 * @vha: HA context 4301 * 4302 * Returns 0 on success. 4303 */ 4304 static int 4305 qla2x00_setup_chip(scsi_qla_host_t *vha) 4306 { 4307 int rval; 4308 uint32_t srisc_address = 0; 4309 struct qla_hw_data *ha = vha->hw; 4310 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4311 unsigned long flags; 4312 int done_once = 0; 4313 4314 if (IS_P3P_TYPE(ha)) { 4315 rval = ha->isp_ops->load_risc(vha, &srisc_address); 4316 if (rval == QLA_SUCCESS) { 4317 qla2x00_stop_firmware(vha); 4318 goto enable_82xx_npiv; 4319 } else 4320 goto failed; 4321 } 4322 4323 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 4324 /* Disable SRAM, Instruction RAM and GP RAM parity. */ 4325 spin_lock_irqsave(&ha->hardware_lock, flags); 4326 wrt_reg_word(®->hccr, (HCCR_ENABLE_PARITY + 0x0)); 4327 rd_reg_word(®->hccr); 4328 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4329 } 4330 4331 qla81xx_mpi_sync(vha); 4332 4333 execute_fw_with_lr: 4334 /* Load firmware sequences */ 4335 rval = ha->isp_ops->load_risc(vha, &srisc_address); 4336 if (rval == QLA_SUCCESS) { 4337 ql_dbg(ql_dbg_init, vha, 0x00c9, 4338 "Verifying Checksum of loaded RISC code.\n"); 4339 4340 rval = qla2x00_verify_checksum(vha, srisc_address); 4341 if (rval == QLA_SUCCESS) { 4342 /* Start firmware execution. */ 4343 ql_dbg(ql_dbg_init, vha, 0x00ca, 4344 "Starting firmware.\n"); 4345 4346 if (ql2xexlogins) 4347 ha->flags.exlogins_enabled = 1; 4348 4349 if (qla_is_exch_offld_enabled(vha)) 4350 ha->flags.exchoffld_enabled = 1; 4351 4352 rval = qla2x00_execute_fw(vha, srisc_address); 4353 /* Retrieve firmware information. */ 4354 if (rval == QLA_SUCCESS) { 4355 /* Enable BPM support? */ 4356 if (!done_once++ && qla24xx_detect_sfp(vha)) { 4357 ql_dbg(ql_dbg_init, vha, 0x00ca, 4358 "Re-starting firmware -- BPM.\n"); 4359 /* Best-effort - re-init. */ 4360 ha->isp_ops->reset_chip(vha); 4361 ha->isp_ops->chip_diag(vha); 4362 goto execute_fw_with_lr; 4363 } 4364 4365 if (IS_ZIO_THRESHOLD_CAPABLE(ha)) 4366 qla27xx_set_zio_threshold(vha, 4367 ha->last_zio_threshold); 4368 4369 rval = qla2x00_set_exlogins_buffer(vha); 4370 if (rval != QLA_SUCCESS) 4371 goto failed; 4372 4373 rval = qla2x00_set_exchoffld_buffer(vha); 4374 if (rval != QLA_SUCCESS) 4375 goto failed; 4376 4377 enable_82xx_npiv: 4378 if (IS_P3P_TYPE(ha)) 4379 qla82xx_check_md_needed(vha); 4380 else 4381 rval = qla2x00_get_fw_version(vha); 4382 if (rval != QLA_SUCCESS) 4383 goto failed; 4384 ha->flags.npiv_supported = 0; 4385 if (IS_QLA2XXX_MIDTYPE(ha) && 4386 (ha->fw_attributes & BIT_2)) { 4387 ha->flags.npiv_supported = 1; 4388 if ((!ha->max_npiv_vports) || 4389 ((ha->max_npiv_vports + 1) % 4390 MIN_MULTI_ID_FABRIC)) 4391 ha->max_npiv_vports = 4392 MIN_MULTI_ID_FABRIC - 1; 4393 } 4394 qlt_config_nvram_with_fw_version(vha); 4395 qla2x00_get_resource_cnts(vha); 4396 qla_init_iocb_limit(vha); 4397 4398 /* 4399 * Allocate the array of outstanding commands 4400 * now that we know the firmware resources. 4401 */ 4402 rval = qla2x00_alloc_outstanding_cmds(ha, 4403 vha->req); 4404 if (rval != QLA_SUCCESS) 4405 goto failed; 4406 4407 if (ql2xallocfwdump && !(IS_P3P_TYPE(ha))) 4408 qla2x00_alloc_fw_dump(vha); 4409 4410 qla_enable_fce_trace(vha); 4411 qla_enable_eft_trace(vha); 4412 } else { 4413 goto failed; 4414 } 4415 } else { 4416 ql_log(ql_log_fatal, vha, 0x00cd, 4417 "ISP Firmware failed checksum.\n"); 4418 goto failed; 4419 } 4420 4421 /* Enable PUREX PASSTHRU */ 4422 if (ql2xrdpenable || ha->flags.scm_supported_f || 4423 ha->flags.edif_enabled) 4424 qla25xx_set_els_cmds_supported(vha); 4425 } else 4426 goto failed; 4427 4428 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) { 4429 /* Enable proper parity. */ 4430 spin_lock_irqsave(&ha->hardware_lock, flags); 4431 if (IS_QLA2300(ha)) 4432 /* SRAM parity */ 4433 wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x1); 4434 else 4435 /* SRAM, Instruction RAM and GP RAM parity */ 4436 wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x7); 4437 rd_reg_word(®->hccr); 4438 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4439 } 4440 4441 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 4442 ha->flags.fac_supported = 1; 4443 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) { 4444 uint32_t size; 4445 4446 rval = qla81xx_fac_get_sector_size(vha, &size); 4447 if (rval == QLA_SUCCESS) { 4448 ha->flags.fac_supported = 1; 4449 ha->fdt_block_size = size << 2; 4450 } else { 4451 ql_log(ql_log_warn, vha, 0x00ce, 4452 "Unsupported FAC firmware (%d.%02d.%02d).\n", 4453 ha->fw_major_version, ha->fw_minor_version, 4454 ha->fw_subminor_version); 4455 4456 if (IS_QLA83XX(ha)) { 4457 ha->flags.fac_supported = 0; 4458 rval = QLA_SUCCESS; 4459 } 4460 } 4461 } 4462 failed: 4463 if (rval) { 4464 ql_log(ql_log_fatal, vha, 0x00cf, 4465 "Setup chip ****FAILED****.\n"); 4466 } 4467 4468 return (rval); 4469 } 4470 4471 /** 4472 * qla2x00_init_response_q_entries() - Initializes response queue entries. 4473 * @rsp: response queue 4474 * 4475 * Beginning of request ring has initialization control block already built 4476 * by nvram config routine. 4477 * 4478 * Returns 0 on success. 4479 */ 4480 void 4481 qla2x00_init_response_q_entries(struct rsp_que *rsp) 4482 { 4483 uint16_t cnt; 4484 response_t *pkt; 4485 4486 rsp->ring_ptr = rsp->ring; 4487 rsp->ring_index = 0; 4488 rsp->status_srb = NULL; 4489 pkt = rsp->ring_ptr; 4490 for (cnt = 0; cnt < rsp->length; cnt++) { 4491 pkt->signature = RESPONSE_PROCESSED; 4492 pkt++; 4493 } 4494 } 4495 4496 /** 4497 * qla2x00_update_fw_options() - Read and process firmware options. 4498 * @vha: HA context 4499 * 4500 * Returns 0 on success. 4501 */ 4502 void 4503 qla2x00_update_fw_options(scsi_qla_host_t *vha) 4504 { 4505 uint16_t swing, emphasis, tx_sens, rx_sens; 4506 struct qla_hw_data *ha = vha->hw; 4507 4508 memset(ha->fw_options, 0, sizeof(ha->fw_options)); 4509 qla2x00_get_fw_options(vha, ha->fw_options); 4510 4511 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 4512 return; 4513 4514 /* Serial Link options. */ 4515 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115, 4516 "Serial link options.\n"); 4517 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109, 4518 ha->fw_seriallink_options, sizeof(ha->fw_seriallink_options)); 4519 4520 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 4521 if (ha->fw_seriallink_options[3] & BIT_2) { 4522 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING; 4523 4524 /* 1G settings */ 4525 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0); 4526 emphasis = (ha->fw_seriallink_options[2] & 4527 (BIT_4 | BIT_3)) >> 3; 4528 tx_sens = ha->fw_seriallink_options[0] & 4529 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 4530 rx_sens = (ha->fw_seriallink_options[0] & 4531 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 4532 ha->fw_options[10] = (emphasis << 14) | (swing << 8); 4533 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 4534 if (rx_sens == 0x0) 4535 rx_sens = 0x3; 4536 ha->fw_options[10] |= (tx_sens << 4) | rx_sens; 4537 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 4538 ha->fw_options[10] |= BIT_5 | 4539 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 4540 (tx_sens & (BIT_1 | BIT_0)); 4541 4542 /* 2G settings */ 4543 swing = (ha->fw_seriallink_options[2] & 4544 (BIT_7 | BIT_6 | BIT_5)) >> 5; 4545 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0); 4546 tx_sens = ha->fw_seriallink_options[1] & 4547 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 4548 rx_sens = (ha->fw_seriallink_options[1] & 4549 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4; 4550 ha->fw_options[11] = (emphasis << 14) | (swing << 8); 4551 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 4552 if (rx_sens == 0x0) 4553 rx_sens = 0x3; 4554 ha->fw_options[11] |= (tx_sens << 4) | rx_sens; 4555 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) 4556 ha->fw_options[11] |= BIT_5 | 4557 ((rx_sens & (BIT_1 | BIT_0)) << 2) | 4558 (tx_sens & (BIT_1 | BIT_0)); 4559 } 4560 4561 /* FCP2 options. */ 4562 /* Return command IOCBs without waiting for an ABTS to complete. */ 4563 ha->fw_options[3] |= BIT_13; 4564 4565 /* LED scheme. */ 4566 if (ha->flags.enable_led_scheme) 4567 ha->fw_options[2] |= BIT_12; 4568 4569 /* Detect ISP6312. */ 4570 if (IS_QLA6312(ha)) 4571 ha->fw_options[2] |= BIT_13; 4572 4573 /* Set Retry FLOGI in case of P2P connection */ 4574 if (ha->operating_mode == P2P) { 4575 ha->fw_options[2] |= BIT_3; 4576 ql_dbg(ql_dbg_disc, vha, 0x2100, 4577 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n", 4578 __func__, ha->fw_options[2]); 4579 } 4580 4581 /* Update firmware options. */ 4582 qla2x00_set_fw_options(vha, ha->fw_options); 4583 } 4584 4585 void 4586 qla24xx_update_fw_options(scsi_qla_host_t *vha) 4587 { 4588 int rval; 4589 struct qla_hw_data *ha = vha->hw; 4590 4591 if (IS_P3P_TYPE(ha)) 4592 return; 4593 4594 /* Hold status IOCBs until ABTS response received. */ 4595 if (ql2xfwholdabts) 4596 ha->fw_options[3] |= BIT_12; 4597 4598 /* Set Retry FLOGI in case of P2P connection */ 4599 if (ha->operating_mode == P2P) { 4600 ha->fw_options[2] |= BIT_3; 4601 ql_dbg(ql_dbg_disc, vha, 0x2101, 4602 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n", 4603 __func__, ha->fw_options[2]); 4604 } 4605 4606 /* Move PUREX, ABTS RX & RIDA to ATIOQ */ 4607 if (ql2xmvasynctoatio && !ha->flags.edif_enabled && 4608 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) { 4609 if (qla_tgt_mode_enabled(vha) || 4610 qla_dual_mode_enabled(vha)) 4611 ha->fw_options[2] |= BIT_11; 4612 else 4613 ha->fw_options[2] &= ~BIT_11; 4614 } 4615 4616 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 4617 IS_QLA28XX(ha)) { 4618 /* 4619 * Tell FW to track each exchange to prevent 4620 * driver from using stale exchange. 4621 */ 4622 if (qla_tgt_mode_enabled(vha) || 4623 qla_dual_mode_enabled(vha)) 4624 ha->fw_options[2] |= BIT_4; 4625 else 4626 ha->fw_options[2] &= ~(BIT_4); 4627 4628 /* Reserve 1/2 of emergency exchanges for ELS.*/ 4629 if (qla2xuseresexchforels) 4630 ha->fw_options[2] |= BIT_8; 4631 else 4632 ha->fw_options[2] &= ~BIT_8; 4633 4634 /* 4635 * N2N: set Secure=1 for PLOGI ACC and 4636 * fw shal not send PRLI after PLOGI Acc 4637 */ 4638 if (ha->flags.edif_enabled && 4639 DBELL_ACTIVE(vha)) { 4640 ha->fw_options[3] |= BIT_15; 4641 ha->flags.n2n_fw_acc_sec = 1; 4642 } else { 4643 ha->fw_options[3] &= ~BIT_15; 4644 ha->flags.n2n_fw_acc_sec = 0; 4645 } 4646 } 4647 4648 if (ql2xrdpenable || ha->flags.scm_supported_f || 4649 ha->flags.edif_enabled) 4650 ha->fw_options[1] |= ADD_FO1_ENABLE_PUREX_IOCB; 4651 4652 /* Enable Async 8130/8131 events -- transceiver insertion/removal */ 4653 if (IS_BPM_RANGE_CAPABLE(ha)) 4654 ha->fw_options[3] |= BIT_10; 4655 4656 ql_dbg(ql_dbg_init, vha, 0x00e8, 4657 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n", 4658 __func__, ha->fw_options[1], ha->fw_options[2], 4659 ha->fw_options[3], vha->host->active_mode); 4660 4661 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3]) 4662 qla2x00_set_fw_options(vha, ha->fw_options); 4663 4664 /* Update Serial Link options. */ 4665 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0) 4666 return; 4667 4668 rval = qla2x00_set_serdes_params(vha, 4669 le16_to_cpu(ha->fw_seriallink_options24[1]), 4670 le16_to_cpu(ha->fw_seriallink_options24[2]), 4671 le16_to_cpu(ha->fw_seriallink_options24[3])); 4672 if (rval != QLA_SUCCESS) { 4673 ql_log(ql_log_warn, vha, 0x0104, 4674 "Unable to update Serial Link options (%x).\n", rval); 4675 } 4676 } 4677 4678 void 4679 qla2x00_config_rings(struct scsi_qla_host *vha) 4680 { 4681 struct qla_hw_data *ha = vha->hw; 4682 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 4683 struct req_que *req = ha->req_q_map[0]; 4684 struct rsp_que *rsp = ha->rsp_q_map[0]; 4685 4686 /* Setup ring parameters in initialization control block. */ 4687 ha->init_cb->request_q_outpointer = cpu_to_le16(0); 4688 ha->init_cb->response_q_inpointer = cpu_to_le16(0); 4689 ha->init_cb->request_q_length = cpu_to_le16(req->length); 4690 ha->init_cb->response_q_length = cpu_to_le16(rsp->length); 4691 put_unaligned_le64(req->dma, &ha->init_cb->request_q_address); 4692 put_unaligned_le64(rsp->dma, &ha->init_cb->response_q_address); 4693 4694 wrt_reg_word(ISP_REQ_Q_IN(ha, reg), 0); 4695 wrt_reg_word(ISP_REQ_Q_OUT(ha, reg), 0); 4696 wrt_reg_word(ISP_RSP_Q_IN(ha, reg), 0); 4697 wrt_reg_word(ISP_RSP_Q_OUT(ha, reg), 0); 4698 rd_reg_word(ISP_RSP_Q_OUT(ha, reg)); /* PCI Posting. */ 4699 } 4700 4701 void 4702 qla24xx_config_rings(struct scsi_qla_host *vha) 4703 { 4704 struct qla_hw_data *ha = vha->hw; 4705 device_reg_t *reg = ISP_QUE_REG(ha, 0); 4706 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp; 4707 struct qla_msix_entry *msix; 4708 struct init_cb_24xx *icb; 4709 uint16_t rid = 0; 4710 struct req_que *req = ha->req_q_map[0]; 4711 struct rsp_que *rsp = ha->rsp_q_map[0]; 4712 4713 /* Setup ring parameters in initialization control block. */ 4714 icb = (struct init_cb_24xx *)ha->init_cb; 4715 icb->request_q_outpointer = cpu_to_le16(0); 4716 icb->response_q_inpointer = cpu_to_le16(0); 4717 icb->request_q_length = cpu_to_le16(req->length); 4718 icb->response_q_length = cpu_to_le16(rsp->length); 4719 put_unaligned_le64(req->dma, &icb->request_q_address); 4720 put_unaligned_le64(rsp->dma, &icb->response_q_address); 4721 4722 /* Setup ATIO queue dma pointers for target mode */ 4723 icb->atio_q_inpointer = cpu_to_le16(0); 4724 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length); 4725 put_unaligned_le64(ha->tgt.atio_dma, &icb->atio_q_address); 4726 4727 if (IS_SHADOW_REG_CAPABLE(ha)) 4728 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29); 4729 4730 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 4731 IS_QLA28XX(ha)) { 4732 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS); 4733 icb->rid = cpu_to_le16(rid); 4734 if (ha->flags.msix_enabled) { 4735 msix = &ha->msix_entries[1]; 4736 ql_dbg(ql_dbg_init, vha, 0x0019, 4737 "Registering vector 0x%x for base que.\n", 4738 msix->entry); 4739 icb->msix = cpu_to_le16(msix->entry); 4740 } 4741 /* Use alternate PCI bus number */ 4742 if (MSB(rid)) 4743 icb->firmware_options_2 |= cpu_to_le32(BIT_19); 4744 /* Use alternate PCI devfn */ 4745 if (LSB(rid)) 4746 icb->firmware_options_2 |= cpu_to_le32(BIT_18); 4747 4748 /* Use Disable MSIX Handshake mode for capable adapters */ 4749 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) && 4750 (ha->flags.msix_enabled)) { 4751 icb->firmware_options_2 &= cpu_to_le32(~BIT_22); 4752 ha->flags.disable_msix_handshake = 1; 4753 ql_dbg(ql_dbg_init, vha, 0x00fe, 4754 "MSIX Handshake Disable Mode turned on.\n"); 4755 } else { 4756 icb->firmware_options_2 |= cpu_to_le32(BIT_22); 4757 } 4758 icb->firmware_options_2 |= cpu_to_le32(BIT_23); 4759 4760 wrt_reg_dword(®->isp25mq.req_q_in, 0); 4761 wrt_reg_dword(®->isp25mq.req_q_out, 0); 4762 wrt_reg_dword(®->isp25mq.rsp_q_in, 0); 4763 wrt_reg_dword(®->isp25mq.rsp_q_out, 0); 4764 } else { 4765 wrt_reg_dword(®->isp24.req_q_in, 0); 4766 wrt_reg_dword(®->isp24.req_q_out, 0); 4767 wrt_reg_dword(®->isp24.rsp_q_in, 0); 4768 wrt_reg_dword(®->isp24.rsp_q_out, 0); 4769 } 4770 4771 qlt_24xx_config_rings(vha); 4772 4773 /* If the user has configured the speed, set it here */ 4774 if (ha->set_data_rate) { 4775 ql_dbg(ql_dbg_init, vha, 0x00fd, 4776 "Speed set by user : %s Gbps \n", 4777 qla2x00_get_link_speed_str(ha, ha->set_data_rate)); 4778 icb->firmware_options_3 = cpu_to_le32(ha->set_data_rate << 13); 4779 } 4780 4781 /* PCI posting */ 4782 rd_reg_word(&ioreg->hccr); 4783 } 4784 4785 /** 4786 * qla2x00_init_rings() - Initializes firmware. 4787 * @vha: HA context 4788 * 4789 * Beginning of request ring has initialization control block already built 4790 * by nvram config routine. 4791 * 4792 * Returns 0 on success. 4793 */ 4794 int 4795 qla2x00_init_rings(scsi_qla_host_t *vha) 4796 { 4797 int rval; 4798 unsigned long flags = 0; 4799 int cnt, que; 4800 struct qla_hw_data *ha = vha->hw; 4801 struct req_que *req; 4802 struct rsp_que *rsp; 4803 struct mid_init_cb_24xx *mid_init_cb = 4804 (struct mid_init_cb_24xx *) ha->init_cb; 4805 4806 spin_lock_irqsave(&ha->hardware_lock, flags); 4807 4808 /* Clear outstanding commands array. */ 4809 for (que = 0; que < ha->max_req_queues; que++) { 4810 req = ha->req_q_map[que]; 4811 if (!req || !test_bit(que, ha->req_qid_map)) 4812 continue; 4813 req->out_ptr = (uint16_t *)(req->ring + req->length); 4814 *req->out_ptr = 0; 4815 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) 4816 req->outstanding_cmds[cnt] = NULL; 4817 4818 req->current_outstanding_cmd = 1; 4819 4820 /* Initialize firmware. */ 4821 req->ring_ptr = req->ring; 4822 req->ring_index = 0; 4823 req->cnt = req->length; 4824 } 4825 4826 for (que = 0; que < ha->max_rsp_queues; que++) { 4827 rsp = ha->rsp_q_map[que]; 4828 if (!rsp || !test_bit(que, ha->rsp_qid_map)) 4829 continue; 4830 rsp->in_ptr = (uint16_t *)(rsp->ring + rsp->length); 4831 *rsp->in_ptr = 0; 4832 /* Initialize response queue entries */ 4833 if (IS_QLAFX00(ha)) 4834 qlafx00_init_response_q_entries(rsp); 4835 else 4836 qla2x00_init_response_q_entries(rsp); 4837 } 4838 4839 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring; 4840 ha->tgt.atio_ring_index = 0; 4841 /* Initialize ATIO queue entries */ 4842 qlt_init_atio_q_entries(vha); 4843 4844 ha->isp_ops->config_rings(vha); 4845 4846 spin_unlock_irqrestore(&ha->hardware_lock, flags); 4847 4848 if (IS_QLAFX00(ha)) { 4849 rval = qlafx00_init_firmware(vha, ha->init_cb_size); 4850 goto next_check; 4851 } 4852 4853 /* Update any ISP specific firmware options before initialization. */ 4854 ha->isp_ops->update_fw_options(vha); 4855 4856 ql_dbg(ql_dbg_init, vha, 0x00d1, 4857 "Issue init firmware FW opt 1-3= %08x %08x %08x.\n", 4858 le32_to_cpu(mid_init_cb->init_cb.firmware_options_1), 4859 le32_to_cpu(mid_init_cb->init_cb.firmware_options_2), 4860 le32_to_cpu(mid_init_cb->init_cb.firmware_options_3)); 4861 4862 if (ha->flags.npiv_supported) { 4863 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha)) 4864 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1; 4865 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports); 4866 } 4867 4868 if (IS_FWI2_CAPABLE(ha)) { 4869 mid_init_cb->options = cpu_to_le16(BIT_1); 4870 mid_init_cb->init_cb.execution_throttle = 4871 cpu_to_le16(ha->cur_fw_xcb_count); 4872 ha->flags.dport_enabled = 4873 (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) & 4874 BIT_7) != 0; 4875 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n", 4876 (ha->flags.dport_enabled) ? "enabled" : "disabled"); 4877 /* FA-WWPN Status */ 4878 ha->flags.fawwpn_enabled = 4879 (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) & 4880 BIT_6) != 0; 4881 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n", 4882 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled"); 4883 /* Init_cb will be reused for other command(s). Save a backup copy of port_name */ 4884 memcpy(ha->port_name, ha->init_cb->port_name, WWN_SIZE); 4885 } 4886 4887 /* ELS pass through payload is limit by frame size. */ 4888 if (ha->flags.edif_enabled) 4889 mid_init_cb->init_cb.frame_payload_size = cpu_to_le16(ELS_MAX_PAYLOAD); 4890 4891 QLA_FW_STARTED(ha); 4892 rval = qla2x00_init_firmware(vha, ha->init_cb_size); 4893 next_check: 4894 if (rval) { 4895 QLA_FW_STOPPED(ha); 4896 ql_log(ql_log_fatal, vha, 0x00d2, 4897 "Init Firmware **** FAILED ****.\n"); 4898 } else { 4899 ql_dbg(ql_dbg_init, vha, 0x00d3, 4900 "Init Firmware -- success.\n"); 4901 vha->u_ql2xexchoffld = vha->u_ql2xiniexchg = 0; 4902 } 4903 4904 return (rval); 4905 } 4906 4907 /** 4908 * qla2x00_fw_ready() - Waits for firmware ready. 4909 * @vha: HA context 4910 * 4911 * Returns 0 on success. 4912 */ 4913 static int 4914 qla2x00_fw_ready(scsi_qla_host_t *vha) 4915 { 4916 int rval; 4917 unsigned long wtime, mtime, cs84xx_time; 4918 uint16_t min_wait; /* Minimum wait time if loop is down */ 4919 uint16_t wait_time; /* Wait time if loop is coming ready */ 4920 uint16_t state[6]; 4921 struct qla_hw_data *ha = vha->hw; 4922 4923 if (IS_QLAFX00(vha->hw)) 4924 return qlafx00_fw_ready(vha); 4925 4926 /* Time to wait for loop down */ 4927 if (IS_P3P_TYPE(ha)) 4928 min_wait = 30; 4929 else 4930 min_wait = 20; 4931 4932 /* 4933 * Firmware should take at most one RATOV to login, plus 5 seconds for 4934 * our own processing. 4935 */ 4936 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) { 4937 wait_time = min_wait; 4938 } 4939 4940 /* Min wait time if loop down */ 4941 mtime = jiffies + (min_wait * HZ); 4942 4943 /* wait time before firmware ready */ 4944 wtime = jiffies + (wait_time * HZ); 4945 4946 /* Wait for ISP to finish LIP */ 4947 if (!vha->flags.init_done) 4948 ql_log(ql_log_info, vha, 0x801e, 4949 "Waiting for LIP to complete.\n"); 4950 4951 do { 4952 memset(state, -1, sizeof(state)); 4953 rval = qla2x00_get_firmware_state(vha, state); 4954 if (rval == QLA_SUCCESS) { 4955 if (state[0] < FSTATE_LOSS_OF_SYNC) { 4956 vha->device_flags &= ~DFLG_NO_CABLE; 4957 } 4958 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) { 4959 ql_dbg(ql_dbg_taskm, vha, 0x801f, 4960 "fw_state=%x 84xx=%x.\n", state[0], 4961 state[2]); 4962 if ((state[2] & FSTATE_LOGGED_IN) && 4963 (state[2] & FSTATE_WAITING_FOR_VERIFY)) { 4964 ql_dbg(ql_dbg_taskm, vha, 0x8028, 4965 "Sending verify iocb.\n"); 4966 4967 cs84xx_time = jiffies; 4968 rval = qla84xx_init_chip(vha); 4969 if (rval != QLA_SUCCESS) { 4970 ql_log(ql_log_warn, 4971 vha, 0x8007, 4972 "Init chip failed.\n"); 4973 break; 4974 } 4975 4976 /* Add time taken to initialize. */ 4977 cs84xx_time = jiffies - cs84xx_time; 4978 wtime += cs84xx_time; 4979 mtime += cs84xx_time; 4980 ql_dbg(ql_dbg_taskm, vha, 0x8008, 4981 "Increasing wait time by %ld. " 4982 "New time %ld.\n", cs84xx_time, 4983 wtime); 4984 } 4985 } else if (state[0] == FSTATE_READY) { 4986 ql_dbg(ql_dbg_taskm, vha, 0x8037, 4987 "F/W Ready - OK.\n"); 4988 4989 qla2x00_get_retry_cnt(vha, &ha->retry_count, 4990 &ha->login_timeout, &ha->r_a_tov); 4991 4992 rval = QLA_SUCCESS; 4993 break; 4994 } 4995 4996 rval = QLA_FUNCTION_FAILED; 4997 4998 if (atomic_read(&vha->loop_down_timer) && 4999 state[0] != FSTATE_READY) { 5000 /* Loop down. Timeout on min_wait for states 5001 * other than Wait for Login. 5002 */ 5003 if (time_after_eq(jiffies, mtime)) { 5004 ql_log(ql_log_info, vha, 0x8038, 5005 "Cable is unplugged...\n"); 5006 5007 vha->device_flags |= DFLG_NO_CABLE; 5008 break; 5009 } 5010 } 5011 } else { 5012 /* Mailbox cmd failed. Timeout on min_wait. */ 5013 if (time_after_eq(jiffies, mtime) || 5014 ha->flags.isp82xx_fw_hung) 5015 break; 5016 } 5017 5018 if (time_after_eq(jiffies, wtime)) 5019 break; 5020 5021 /* Delay for a while */ 5022 msleep(500); 5023 } while (1); 5024 5025 ql_dbg(ql_dbg_taskm, vha, 0x803a, 5026 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0], 5027 state[1], state[2], state[3], state[4], state[5], jiffies); 5028 5029 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) { 5030 ql_log(ql_log_warn, vha, 0x803b, 5031 "Firmware ready **** FAILED ****.\n"); 5032 } 5033 5034 return (rval); 5035 } 5036 5037 /* 5038 * qla2x00_configure_hba 5039 * Setup adapter context. 5040 * 5041 * Input: 5042 * ha = adapter state pointer. 5043 * 5044 * Returns: 5045 * 0 = success 5046 * 5047 * Context: 5048 * Kernel context. 5049 */ 5050 static int 5051 qla2x00_configure_hba(scsi_qla_host_t *vha) 5052 { 5053 int rval; 5054 uint16_t loop_id; 5055 uint16_t topo; 5056 uint16_t sw_cap; 5057 uint8_t al_pa; 5058 uint8_t area; 5059 uint8_t domain; 5060 char connect_type[22]; 5061 struct qla_hw_data *ha = vha->hw; 5062 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5063 port_id_t id; 5064 unsigned long flags; 5065 5066 /* Get host addresses. */ 5067 rval = qla2x00_get_adapter_id(vha, 5068 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap); 5069 if (rval != QLA_SUCCESS) { 5070 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) || 5071 IS_CNA_CAPABLE(ha) || 5072 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) { 5073 ql_dbg(ql_dbg_disc, vha, 0x2008, 5074 "Loop is in a transition state.\n"); 5075 } else { 5076 ql_log(ql_log_warn, vha, 0x2009, 5077 "Unable to get host loop ID.\n"); 5078 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) && 5079 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) { 5080 ql_log(ql_log_warn, vha, 0x1151, 5081 "Doing link init.\n"); 5082 if (qla24xx_link_initialize(vha) == QLA_SUCCESS) 5083 return rval; 5084 } 5085 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 5086 } 5087 return (rval); 5088 } 5089 5090 if (topo == 4) { 5091 ql_log(ql_log_info, vha, 0x200a, 5092 "Cannot get topology - retrying.\n"); 5093 return (QLA_FUNCTION_FAILED); 5094 } 5095 5096 vha->loop_id = loop_id; 5097 5098 /* initialize */ 5099 ha->min_external_loopid = SNS_FIRST_LOOP_ID; 5100 ha->operating_mode = LOOP; 5101 5102 switch (topo) { 5103 case 0: 5104 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n"); 5105 ha->switch_cap = 0; 5106 ha->current_topology = ISP_CFG_NL; 5107 strcpy(connect_type, "(Loop)"); 5108 break; 5109 5110 case 1: 5111 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n"); 5112 ha->switch_cap = sw_cap; 5113 ha->current_topology = ISP_CFG_FL; 5114 strcpy(connect_type, "(FL_Port)"); 5115 break; 5116 5117 case 2: 5118 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n"); 5119 ha->switch_cap = 0; 5120 ha->operating_mode = P2P; 5121 ha->current_topology = ISP_CFG_N; 5122 strcpy(connect_type, "(N_Port-to-N_Port)"); 5123 break; 5124 5125 case 3: 5126 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n"); 5127 ha->switch_cap = sw_cap; 5128 ha->operating_mode = P2P; 5129 ha->current_topology = ISP_CFG_F; 5130 strcpy(connect_type, "(F_Port)"); 5131 break; 5132 5133 default: 5134 ql_dbg(ql_dbg_disc, vha, 0x200f, 5135 "HBA in unknown topology %x, using NL.\n", topo); 5136 ha->switch_cap = 0; 5137 ha->current_topology = ISP_CFG_NL; 5138 strcpy(connect_type, "(Loop)"); 5139 break; 5140 } 5141 5142 /* Save Host port and loop ID. */ 5143 /* byte order - Big Endian */ 5144 id.b.domain = domain; 5145 id.b.area = area; 5146 id.b.al_pa = al_pa; 5147 id.b.rsvd_1 = 0; 5148 spin_lock_irqsave(&ha->hardware_lock, flags); 5149 if (vha->hw->flags.edif_enabled) { 5150 if (topo != 2) 5151 qla_update_host_map(vha, id); 5152 } else if (!(topo == 2 && ha->flags.n2n_bigger)) 5153 qla_update_host_map(vha, id); 5154 spin_unlock_irqrestore(&ha->hardware_lock, flags); 5155 5156 if (!vha->flags.init_done) 5157 ql_log(ql_log_info, vha, 0x2010, 5158 "Topology - %s, Host Loop address 0x%x.\n", 5159 connect_type, vha->loop_id); 5160 5161 return(rval); 5162 } 5163 5164 inline void 5165 qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len, 5166 const char *def) 5167 { 5168 char *st, *en; 5169 uint16_t index; 5170 uint64_t zero[2] = { 0 }; 5171 struct qla_hw_data *ha = vha->hw; 5172 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 5173 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha); 5174 5175 if (len > sizeof(zero)) 5176 len = sizeof(zero); 5177 if (memcmp(model, &zero, len) != 0) { 5178 memcpy(ha->model_number, model, len); 5179 st = en = ha->model_number; 5180 en += len - 1; 5181 while (en > st) { 5182 if (*en != 0x20 && *en != 0x00) 5183 break; 5184 *en-- = '\0'; 5185 } 5186 5187 index = (ha->pdev->subsystem_device & 0xff); 5188 if (use_tbl && 5189 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 5190 index < QLA_MODEL_NAMES) 5191 strscpy(ha->model_desc, 5192 qla2x00_model_name[index * 2 + 1], 5193 sizeof(ha->model_desc)); 5194 } else { 5195 index = (ha->pdev->subsystem_device & 0xff); 5196 if (use_tbl && 5197 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC && 5198 index < QLA_MODEL_NAMES) { 5199 strscpy(ha->model_number, 5200 qla2x00_model_name[index * 2], 5201 sizeof(ha->model_number)); 5202 strscpy(ha->model_desc, 5203 qla2x00_model_name[index * 2 + 1], 5204 sizeof(ha->model_desc)); 5205 } else { 5206 strscpy(ha->model_number, def, 5207 sizeof(ha->model_number)); 5208 } 5209 } 5210 if (IS_FWI2_CAPABLE(ha)) 5211 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc, 5212 sizeof(ha->model_desc)); 5213 } 5214 5215 /* On sparc systems, obtain port and node WWN from firmware 5216 * properties. 5217 */ 5218 static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv) 5219 { 5220 #ifdef CONFIG_SPARC 5221 struct qla_hw_data *ha = vha->hw; 5222 struct pci_dev *pdev = ha->pdev; 5223 struct device_node *dp = pci_device_to_OF_node(pdev); 5224 const u8 *val; 5225 int len; 5226 5227 val = of_get_property(dp, "port-wwn", &len); 5228 if (val && len >= WWN_SIZE) 5229 memcpy(nv->port_name, val, WWN_SIZE); 5230 5231 val = of_get_property(dp, "node-wwn", &len); 5232 if (val && len >= WWN_SIZE) 5233 memcpy(nv->node_name, val, WWN_SIZE); 5234 #endif 5235 } 5236 5237 /* 5238 * NVRAM configuration for ISP 2xxx 5239 * 5240 * Input: 5241 * ha = adapter block pointer. 5242 * 5243 * Output: 5244 * initialization control block in response_ring 5245 * host adapters parameters in host adapter block 5246 * 5247 * Returns: 5248 * 0 = success. 5249 */ 5250 int 5251 qla2x00_nvram_config(scsi_qla_host_t *vha) 5252 { 5253 int rval; 5254 uint8_t chksum = 0; 5255 uint16_t cnt; 5256 uint8_t *dptr1, *dptr2; 5257 struct qla_hw_data *ha = vha->hw; 5258 init_cb_t *icb = ha->init_cb; 5259 nvram_t *nv = ha->nvram; 5260 uint8_t *ptr = ha->nvram; 5261 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 5262 5263 rval = QLA_SUCCESS; 5264 5265 /* Determine NVRAM starting address. */ 5266 ha->nvram_size = sizeof(*nv); 5267 ha->nvram_base = 0; 5268 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) 5269 if ((rd_reg_word(®->ctrl_status) >> 14) == 1) 5270 ha->nvram_base = 0x80; 5271 5272 /* Get NVRAM data and calculate checksum. */ 5273 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size); 5274 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++) 5275 chksum += *ptr++; 5276 5277 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f, 5278 "Contents of NVRAM.\n"); 5279 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110, 5280 nv, ha->nvram_size); 5281 5282 /* Bad NVRAM data, set defaults parameters. */ 5283 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 5284 nv->nvram_version < 1) { 5285 /* Reset NVRAM data. */ 5286 ql_log(ql_log_warn, vha, 0x0064, 5287 "Inconsistent NVRAM detected: checksum=%#x id=%.4s version=%#x.\n", 5288 chksum, nv->id, nv->nvram_version); 5289 ql_log(ql_log_warn, vha, 0x0065, 5290 "Falling back to " 5291 "functioning (yet invalid -- WWPN) defaults.\n"); 5292 5293 /* 5294 * Set default initialization control block. 5295 */ 5296 memset(nv, 0, ha->nvram_size); 5297 nv->parameter_block_version = ICB_VERSION; 5298 5299 if (IS_QLA23XX(ha)) { 5300 nv->firmware_options[0] = BIT_2 | BIT_1; 5301 nv->firmware_options[1] = BIT_7 | BIT_5; 5302 nv->add_firmware_options[0] = BIT_5; 5303 nv->add_firmware_options[1] = BIT_5 | BIT_4; 5304 nv->frame_payload_size = cpu_to_le16(2048); 5305 nv->special_options[1] = BIT_7; 5306 } else if (IS_QLA2200(ha)) { 5307 nv->firmware_options[0] = BIT_2 | BIT_1; 5308 nv->firmware_options[1] = BIT_7 | BIT_5; 5309 nv->add_firmware_options[0] = BIT_5; 5310 nv->add_firmware_options[1] = BIT_5 | BIT_4; 5311 nv->frame_payload_size = cpu_to_le16(1024); 5312 } else if (IS_QLA2100(ha)) { 5313 nv->firmware_options[0] = BIT_3 | BIT_1; 5314 nv->firmware_options[1] = BIT_5; 5315 nv->frame_payload_size = cpu_to_le16(1024); 5316 } 5317 5318 nv->max_iocb_allocation = cpu_to_le16(256); 5319 nv->execution_throttle = cpu_to_le16(16); 5320 nv->retry_count = 8; 5321 nv->retry_delay = 1; 5322 5323 nv->port_name[0] = 33; 5324 nv->port_name[3] = 224; 5325 nv->port_name[4] = 139; 5326 5327 qla2xxx_nvram_wwn_from_ofw(vha, nv); 5328 5329 nv->login_timeout = 4; 5330 5331 /* 5332 * Set default host adapter parameters 5333 */ 5334 nv->host_p[1] = BIT_2; 5335 nv->reset_delay = 5; 5336 nv->port_down_retry_count = 8; 5337 nv->max_luns_per_target = cpu_to_le16(8); 5338 nv->link_down_timeout = 60; 5339 5340 rval = 1; 5341 } 5342 5343 /* Reset Initialization control block */ 5344 memset(icb, 0, ha->init_cb_size); 5345 5346 /* 5347 * Setup driver NVRAM options. 5348 */ 5349 nv->firmware_options[0] |= (BIT_6 | BIT_1); 5350 nv->firmware_options[0] &= ~(BIT_5 | BIT_4); 5351 nv->firmware_options[1] |= (BIT_5 | BIT_0); 5352 nv->firmware_options[1] &= ~BIT_4; 5353 5354 if (IS_QLA23XX(ha)) { 5355 nv->firmware_options[0] |= BIT_2; 5356 nv->firmware_options[0] &= ~BIT_3; 5357 nv->special_options[0] &= ~BIT_6; 5358 nv->add_firmware_options[1] |= BIT_5 | BIT_4; 5359 5360 if (IS_QLA2300(ha)) { 5361 if (ha->fb_rev == FPM_2310) { 5362 strcpy(ha->model_number, "QLA2310"); 5363 } else { 5364 strcpy(ha->model_number, "QLA2300"); 5365 } 5366 } else { 5367 qla2x00_set_model_info(vha, nv->model_number, 5368 sizeof(nv->model_number), "QLA23xx"); 5369 } 5370 } else if (IS_QLA2200(ha)) { 5371 nv->firmware_options[0] |= BIT_2; 5372 /* 5373 * 'Point-to-point preferred, else loop' is not a safe 5374 * connection mode setting. 5375 */ 5376 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) == 5377 (BIT_5 | BIT_4)) { 5378 /* Force 'loop preferred, else point-to-point'. */ 5379 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4); 5380 nv->add_firmware_options[0] |= BIT_5; 5381 } 5382 strcpy(ha->model_number, "QLA22xx"); 5383 } else /*if (IS_QLA2100(ha))*/ { 5384 strcpy(ha->model_number, "QLA2100"); 5385 } 5386 5387 /* 5388 * Copy over NVRAM RISC parameter block to initialization control block. 5389 */ 5390 dptr1 = (uint8_t *)icb; 5391 dptr2 = (uint8_t *)&nv->parameter_block_version; 5392 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version; 5393 while (cnt--) 5394 *dptr1++ = *dptr2++; 5395 5396 /* Copy 2nd half. */ 5397 dptr1 = (uint8_t *)icb->add_firmware_options; 5398 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options; 5399 while (cnt--) 5400 *dptr1++ = *dptr2++; 5401 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 5402 /* Use alternate WWN? */ 5403 if (nv->host_p[1] & BIT_7) { 5404 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 5405 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 5406 } 5407 5408 /* Prepare nodename */ 5409 if ((icb->firmware_options[1] & BIT_6) == 0) { 5410 /* 5411 * Firmware will apply the following mask if the nodename was 5412 * not provided. 5413 */ 5414 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 5415 icb->node_name[0] &= 0xF0; 5416 } 5417 5418 /* 5419 * Set host adapter parameters. 5420 */ 5421 5422 /* 5423 * BIT_7 in the host-parameters section allows for modification to 5424 * internal driver logging. 5425 */ 5426 if (nv->host_p[0] & BIT_7) 5427 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 5428 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0); 5429 /* Always load RISC code on non ISP2[12]00 chips. */ 5430 if (!IS_QLA2100(ha) && !IS_QLA2200(ha)) 5431 ha->flags.disable_risc_code_load = 0; 5432 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0); 5433 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0); 5434 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0); 5435 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0; 5436 ha->flags.disable_serdes = 0; 5437 5438 ha->operating_mode = 5439 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4; 5440 5441 memcpy(ha->fw_seriallink_options, nv->seriallink_options, 5442 sizeof(ha->fw_seriallink_options)); 5443 5444 /* save HBA serial number */ 5445 ha->serial0 = icb->port_name[5]; 5446 ha->serial1 = icb->port_name[6]; 5447 ha->serial2 = icb->port_name[7]; 5448 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 5449 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 5450 5451 icb->execution_throttle = cpu_to_le16(0xFFFF); 5452 5453 ha->retry_count = nv->retry_count; 5454 5455 /* Set minimum login_timeout to 4 seconds. */ 5456 if (nv->login_timeout != ql2xlogintimeout) 5457 nv->login_timeout = ql2xlogintimeout; 5458 if (nv->login_timeout < 4) 5459 nv->login_timeout = 4; 5460 ha->login_timeout = nv->login_timeout; 5461 5462 /* Set minimum RATOV to 100 tenths of a second. */ 5463 ha->r_a_tov = 100; 5464 5465 ha->loop_reset_delay = nv->reset_delay; 5466 5467 /* Link Down Timeout = 0: 5468 * 5469 * When Port Down timer expires we will start returning 5470 * I/O's to OS with "DID_NO_CONNECT". 5471 * 5472 * Link Down Timeout != 0: 5473 * 5474 * The driver waits for the link to come up after link down 5475 * before returning I/Os to OS with "DID_NO_CONNECT". 5476 */ 5477 if (nv->link_down_timeout == 0) { 5478 ha->loop_down_abort_time = 5479 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 5480 } else { 5481 ha->link_down_timeout = nv->link_down_timeout; 5482 ha->loop_down_abort_time = 5483 (LOOP_DOWN_TIME - ha->link_down_timeout); 5484 } 5485 5486 /* 5487 * Need enough time to try and get the port back. 5488 */ 5489 ha->port_down_retry_count = nv->port_down_retry_count; 5490 if (qlport_down_retry) 5491 ha->port_down_retry_count = qlport_down_retry; 5492 /* Set login_retry_count */ 5493 ha->login_retry_count = nv->retry_count; 5494 if (ha->port_down_retry_count == nv->port_down_retry_count && 5495 ha->port_down_retry_count > 3) 5496 ha->login_retry_count = ha->port_down_retry_count; 5497 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 5498 ha->login_retry_count = ha->port_down_retry_count; 5499 if (ql2xloginretrycount) 5500 ha->login_retry_count = ql2xloginretrycount; 5501 5502 icb->lun_enables = cpu_to_le16(0); 5503 icb->command_resource_count = 0; 5504 icb->immediate_notify_resource_count = 0; 5505 icb->timeout = cpu_to_le16(0); 5506 5507 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 5508 /* Enable RIO */ 5509 icb->firmware_options[0] &= ~BIT_3; 5510 icb->add_firmware_options[0] &= 5511 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 5512 icb->add_firmware_options[0] |= BIT_2; 5513 icb->response_accumulation_timer = 3; 5514 icb->interrupt_delay_timer = 5; 5515 5516 vha->flags.process_response_queue = 1; 5517 } else { 5518 /* Enable ZIO. */ 5519 if (!vha->flags.init_done) { 5520 ha->zio_mode = icb->add_firmware_options[0] & 5521 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 5522 ha->zio_timer = icb->interrupt_delay_timer ? 5523 icb->interrupt_delay_timer : 2; 5524 } 5525 icb->add_firmware_options[0] &= 5526 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0); 5527 vha->flags.process_response_queue = 0; 5528 if (ha->zio_mode != QLA_ZIO_DISABLED) { 5529 ha->zio_mode = QLA_ZIO_MODE_6; 5530 5531 ql_log(ql_log_info, vha, 0x0068, 5532 "ZIO mode %d enabled; timer delay (%d us).\n", 5533 ha->zio_mode, ha->zio_timer * 100); 5534 5535 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode; 5536 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer; 5537 vha->flags.process_response_queue = 1; 5538 } 5539 } 5540 5541 if (rval) { 5542 ql_log(ql_log_warn, vha, 0x0069, 5543 "NVRAM configuration failed.\n"); 5544 } 5545 return (rval); 5546 } 5547 5548 void qla2x00_set_fcport_state(fc_port_t *fcport, int state) 5549 { 5550 int old_state; 5551 5552 old_state = atomic_read(&fcport->state); 5553 atomic_set(&fcport->state, state); 5554 5555 /* Don't print state transitions during initial allocation of fcport */ 5556 if (old_state && old_state != state) { 5557 ql_dbg(ql_dbg_disc, fcport->vha, 0x207d, 5558 "FCPort %8phC state transitioned from %s to %s - portid=%02x%02x%02x.\n", 5559 fcport->port_name, port_state_str[old_state], 5560 port_state_str[state], fcport->d_id.b.domain, 5561 fcport->d_id.b.area, fcport->d_id.b.al_pa); 5562 } 5563 } 5564 5565 /** 5566 * qla2x00_alloc_fcport() - Allocate a generic fcport. 5567 * @vha: HA context 5568 * @flags: allocation flags 5569 * 5570 * Returns a pointer to the allocated fcport, or NULL, if none available. 5571 */ 5572 fc_port_t * 5573 qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags) 5574 { 5575 fc_port_t *fcport; 5576 5577 fcport = kzalloc(sizeof(fc_port_t), flags); 5578 if (!fcport) 5579 return NULL; 5580 5581 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev, 5582 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma, 5583 flags); 5584 if (!fcport->ct_desc.ct_sns) { 5585 ql_log(ql_log_warn, vha, 0xd049, 5586 "Failed to allocate ct_sns request.\n"); 5587 kfree(fcport); 5588 return NULL; 5589 } 5590 5591 /* Setup fcport template structure. */ 5592 fcport->vha = vha; 5593 fcport->port_type = FCT_UNKNOWN; 5594 fcport->loop_id = FC_NO_LOOP_ID; 5595 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED); 5596 fcport->supported_classes = FC_COS_UNSPECIFIED; 5597 fcport->fp_speed = PORT_SPEED_UNKNOWN; 5598 5599 fcport->disc_state = DSC_DELETED; 5600 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL; 5601 fcport->deleted = QLA_SESS_DELETED; 5602 fcport->login_retry = vha->hw->login_retry_count; 5603 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5604 fcport->logout_on_delete = 1; 5605 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 5606 fcport->tgt_short_link_down_cnt = 0; 5607 fcport->dev_loss_tmo = 0; 5608 5609 if (!fcport->ct_desc.ct_sns) { 5610 ql_log(ql_log_warn, vha, 0xd049, 5611 "Failed to allocate ct_sns request.\n"); 5612 kfree(fcport); 5613 return NULL; 5614 } 5615 5616 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn); 5617 INIT_WORK(&fcport->free_work, qlt_free_session_done); 5618 INIT_WORK(&fcport->reg_work, qla_register_fcport_fn); 5619 INIT_LIST_HEAD(&fcport->gnl_entry); 5620 INIT_LIST_HEAD(&fcport->list); 5621 INIT_LIST_HEAD(&fcport->unsol_ctx_head); 5622 5623 INIT_LIST_HEAD(&fcport->sess_cmd_list); 5624 spin_lock_init(&fcport->sess_cmd_lock); 5625 5626 spin_lock_init(&fcport->edif.sa_list_lock); 5627 INIT_LIST_HEAD(&fcport->edif.tx_sa_list); 5628 INIT_LIST_HEAD(&fcport->edif.rx_sa_list); 5629 5630 spin_lock_init(&fcport->edif.indx_list_lock); 5631 INIT_LIST_HEAD(&fcport->edif.edif_indx_list); 5632 5633 return fcport; 5634 } 5635 5636 void 5637 qla2x00_free_fcport(fc_port_t *fcport) 5638 { 5639 if (fcport->ct_desc.ct_sns) { 5640 dma_free_coherent(&fcport->vha->hw->pdev->dev, 5641 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns, 5642 fcport->ct_desc.ct_sns_dma); 5643 5644 fcport->ct_desc.ct_sns = NULL; 5645 } 5646 5647 qla_edif_flush_sa_ctl_lists(fcport); 5648 list_del(&fcport->list); 5649 qla2x00_clear_loop_id(fcport); 5650 5651 qla_edif_list_del(fcport); 5652 5653 kfree(fcport); 5654 } 5655 5656 static void qla_get_login_template(scsi_qla_host_t *vha) 5657 { 5658 struct qla_hw_data *ha = vha->hw; 5659 int rval; 5660 u32 *bp, sz; 5661 __be32 *q; 5662 5663 memset(ha->init_cb, 0, ha->init_cb_size); 5664 sz = min_t(int, sizeof(struct fc_els_flogi), ha->init_cb_size); 5665 rval = qla24xx_get_port_login_templ(vha, ha->init_cb_dma, 5666 ha->init_cb, sz); 5667 if (rval != QLA_SUCCESS) { 5668 ql_dbg(ql_dbg_init, vha, 0x00d1, 5669 "PLOGI ELS param read fail.\n"); 5670 return; 5671 } 5672 q = (__be32 *)&ha->plogi_els_payld.fl_csp; 5673 5674 bp = (uint32_t *)ha->init_cb; 5675 cpu_to_be32_array(q, bp, sz / 4); 5676 ha->flags.plogi_template_valid = 1; 5677 } 5678 5679 /* 5680 * qla2x00_configure_loop 5681 * Updates Fibre Channel Device Database with what is actually on loop. 5682 * 5683 * Input: 5684 * ha = adapter block pointer. 5685 * 5686 * Returns: 5687 * 0 = success. 5688 * 1 = error. 5689 * 2 = database was full and device was not configured. 5690 */ 5691 static int 5692 qla2x00_configure_loop(scsi_qla_host_t *vha) 5693 { 5694 int rval; 5695 unsigned long flags, save_flags; 5696 struct qla_hw_data *ha = vha->hw; 5697 5698 rval = QLA_SUCCESS; 5699 5700 /* Get Initiator ID */ 5701 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) { 5702 rval = qla2x00_configure_hba(vha); 5703 if (rval != QLA_SUCCESS) { 5704 ql_dbg(ql_dbg_disc, vha, 0x2013, 5705 "Unable to configure HBA.\n"); 5706 return (rval); 5707 } 5708 } 5709 5710 save_flags = flags = vha->dpc_flags; 5711 ql_dbg(ql_dbg_disc, vha, 0x2014, 5712 "Configure loop -- dpc flags = 0x%lx.\n", flags); 5713 5714 /* 5715 * If we have both an RSCN and PORT UPDATE pending then handle them 5716 * both at the same time. 5717 */ 5718 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5719 clear_bit(RSCN_UPDATE, &vha->dpc_flags); 5720 5721 qla2x00_get_data_rate(vha); 5722 qla_get_login_template(vha); 5723 5724 /* Determine what we need to do */ 5725 if ((ha->current_topology == ISP_CFG_FL || 5726 ha->current_topology == ISP_CFG_F) && 5727 (test_bit(LOCAL_LOOP_UPDATE, &flags))) { 5728 5729 set_bit(RSCN_UPDATE, &flags); 5730 clear_bit(LOCAL_LOOP_UPDATE, &flags); 5731 5732 } else if (ha->current_topology == ISP_CFG_NL || 5733 ha->current_topology == ISP_CFG_N) { 5734 clear_bit(RSCN_UPDATE, &flags); 5735 set_bit(LOCAL_LOOP_UPDATE, &flags); 5736 } else if (!vha->flags.online || 5737 (test_bit(ABORT_ISP_ACTIVE, &flags))) { 5738 set_bit(RSCN_UPDATE, &flags); 5739 set_bit(LOCAL_LOOP_UPDATE, &flags); 5740 } 5741 5742 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) { 5743 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5744 ql_dbg(ql_dbg_disc, vha, 0x2015, 5745 "Loop resync needed, failing.\n"); 5746 rval = QLA_FUNCTION_FAILED; 5747 } else 5748 rval = qla2x00_configure_local_loop(vha); 5749 } 5750 5751 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) { 5752 if (LOOP_TRANSITION(vha)) { 5753 ql_dbg(ql_dbg_disc, vha, 0x2099, 5754 "Needs RSCN update and loop transition.\n"); 5755 rval = QLA_FUNCTION_FAILED; 5756 } 5757 else 5758 rval = qla2x00_configure_fabric(vha); 5759 } 5760 5761 if (rval == QLA_SUCCESS) { 5762 if (atomic_read(&vha->loop_down_timer) || 5763 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5764 rval = QLA_FUNCTION_FAILED; 5765 } else { 5766 atomic_set(&vha->loop_state, LOOP_READY); 5767 ql_dbg(ql_dbg_disc, vha, 0x2069, 5768 "LOOP READY.\n"); 5769 ha->flags.fw_init_done = 1; 5770 5771 /* 5772 * use link up to wake up app to get ready for 5773 * authentication. 5774 */ 5775 if (ha->flags.edif_enabled && DBELL_INACTIVE(vha)) 5776 qla2x00_post_aen_work(vha, FCH_EVT_LINKUP, 5777 ha->link_data_rate); 5778 5779 /* 5780 * Process any ATIO queue entries that came in 5781 * while we weren't online. 5782 */ 5783 if (qla_tgt_mode_enabled(vha) || 5784 qla_dual_mode_enabled(vha)) { 5785 spin_lock_irqsave(&ha->tgt.atio_lock, flags); 5786 qlt_24xx_process_atio_queue(vha, 0); 5787 spin_unlock_irqrestore(&ha->tgt.atio_lock, 5788 flags); 5789 } 5790 } 5791 } 5792 5793 if (rval) { 5794 ql_dbg(ql_dbg_disc, vha, 0x206a, 5795 "%s *** FAILED ***.\n", __func__); 5796 } else { 5797 ql_dbg(ql_dbg_disc, vha, 0x206b, 5798 "%s: exiting normally. local port wwpn %8phN id %06x)\n", 5799 __func__, vha->port_name, vha->d_id.b24); 5800 } 5801 5802 /* Restore state if a resync event occurred during processing */ 5803 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) { 5804 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags)) 5805 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5806 if (test_bit(RSCN_UPDATE, &save_flags)) { 5807 set_bit(RSCN_UPDATE, &vha->dpc_flags); 5808 } 5809 } 5810 5811 return (rval); 5812 } 5813 5814 static int qla2x00_configure_n2n_loop(scsi_qla_host_t *vha) 5815 { 5816 unsigned long flags; 5817 fc_port_t *fcport; 5818 5819 ql_dbg(ql_dbg_disc, vha, 0x206a, "%s %d.\n", __func__, __LINE__); 5820 5821 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags)) 5822 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5823 5824 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5825 if (fcport->n2n_flag) { 5826 qla24xx_fcport_handle_login(vha, fcport); 5827 return QLA_SUCCESS; 5828 } 5829 } 5830 5831 spin_lock_irqsave(&vha->work_lock, flags); 5832 vha->scan.scan_retry++; 5833 spin_unlock_irqrestore(&vha->work_lock, flags); 5834 5835 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) { 5836 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5837 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5838 } 5839 return QLA_FUNCTION_FAILED; 5840 } 5841 5842 static void 5843 qla_reinitialize_link(scsi_qla_host_t *vha) 5844 { 5845 int rval; 5846 5847 atomic_set(&vha->loop_state, LOOP_DOWN); 5848 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 5849 rval = qla2x00_full_login_lip(vha); 5850 if (rval == QLA_SUCCESS) { 5851 ql_dbg(ql_dbg_disc, vha, 0xd050, "Link reinitialized\n"); 5852 } else { 5853 ql_dbg(ql_dbg_disc, vha, 0xd051, 5854 "Link reinitialization failed (%d)\n", rval); 5855 } 5856 } 5857 5858 /* 5859 * qla2x00_configure_local_loop 5860 * Updates Fibre Channel Device Database with local loop devices. 5861 * 5862 * Input: 5863 * ha = adapter block pointer. 5864 * 5865 * Returns: 5866 * 0 = success. 5867 */ 5868 static int 5869 qla2x00_configure_local_loop(scsi_qla_host_t *vha) 5870 { 5871 int rval, rval2; 5872 int found; 5873 fc_port_t *fcport, *new_fcport; 5874 uint16_t index; 5875 uint16_t entries; 5876 struct gid_list_info *gid; 5877 uint16_t loop_id; 5878 uint8_t domain, area, al_pa; 5879 struct qla_hw_data *ha = vha->hw; 5880 unsigned long flags; 5881 5882 /* Inititae N2N login. */ 5883 if (N2N_TOPO(ha)) 5884 return qla2x00_configure_n2n_loop(vha); 5885 5886 new_fcport = NULL; 5887 entries = MAX_FIBRE_DEVICES_LOOP; 5888 5889 /* Get list of logged in devices. */ 5890 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha)); 5891 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma, 5892 &entries); 5893 if (rval != QLA_SUCCESS) 5894 goto err; 5895 5896 ql_dbg(ql_dbg_disc, vha, 0x2011, 5897 "Entries in ID list (%d).\n", entries); 5898 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075, 5899 ha->gid_list, entries * sizeof(*ha->gid_list)); 5900 5901 if (entries == 0) { 5902 spin_lock_irqsave(&vha->work_lock, flags); 5903 vha->scan.scan_retry++; 5904 spin_unlock_irqrestore(&vha->work_lock, flags); 5905 5906 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) { 5907 u8 loop_map_entries = 0; 5908 int rc; 5909 5910 rc = qla2x00_get_fcal_position_map(vha, NULL, 5911 &loop_map_entries); 5912 if (rc == QLA_SUCCESS && loop_map_entries > 1) { 5913 /* 5914 * There are devices that are still not logged 5915 * in. Reinitialize to give them a chance. 5916 */ 5917 qla_reinitialize_link(vha); 5918 return QLA_FUNCTION_FAILED; 5919 } 5920 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 5921 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5922 } 5923 } else { 5924 vha->scan.scan_retry = 0; 5925 } 5926 5927 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5928 fcport->scan_state = QLA_FCPORT_SCAN; 5929 } 5930 5931 /* Allocate temporary fcport for any new fcports discovered. */ 5932 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5933 if (new_fcport == NULL) { 5934 ql_log(ql_log_warn, vha, 0x2012, 5935 "Memory allocation failed for fcport.\n"); 5936 rval = QLA_MEMORY_ALLOC_FAILED; 5937 goto err; 5938 } 5939 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 5940 5941 /* Add devices to port list. */ 5942 gid = ha->gid_list; 5943 for (index = 0; index < entries; index++) { 5944 domain = gid->domain; 5945 area = gid->area; 5946 al_pa = gid->al_pa; 5947 if (IS_QLA2100(ha) || IS_QLA2200(ha)) 5948 loop_id = gid->loop_id_2100; 5949 else 5950 loop_id = le16_to_cpu(gid->loop_id); 5951 gid = (void *)gid + ha->gid_list_info_size; 5952 5953 /* Bypass reserved domain fields. */ 5954 if ((domain & 0xf0) == 0xf0) 5955 continue; 5956 5957 /* Bypass if not same domain and area of adapter. */ 5958 if (area && domain && ((area != vha->d_id.b.area) || 5959 (domain != vha->d_id.b.domain)) && 5960 (ha->current_topology == ISP_CFG_NL)) 5961 continue; 5962 5963 5964 /* Bypass invalid local loop ID. */ 5965 if (loop_id > LAST_LOCAL_LOOP_ID) 5966 continue; 5967 5968 memset(new_fcport->port_name, 0, WWN_SIZE); 5969 5970 /* Fill in member data. */ 5971 new_fcport->d_id.b.domain = domain; 5972 new_fcport->d_id.b.area = area; 5973 new_fcport->d_id.b.al_pa = al_pa; 5974 new_fcport->loop_id = loop_id; 5975 new_fcport->scan_state = QLA_FCPORT_FOUND; 5976 5977 rval2 = qla2x00_get_port_database(vha, new_fcport, 0); 5978 if (rval2 != QLA_SUCCESS) { 5979 ql_dbg(ql_dbg_disc, vha, 0x2097, 5980 "Failed to retrieve fcport information " 5981 "-- get_port_database=%x, loop_id=0x%04x.\n", 5982 rval2, new_fcport->loop_id); 5983 /* Skip retry if N2N */ 5984 if (ha->current_topology != ISP_CFG_N) { 5985 ql_dbg(ql_dbg_disc, vha, 0x2105, 5986 "Scheduling resync.\n"); 5987 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 5988 continue; 5989 } 5990 } 5991 5992 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5993 /* Check for matching device in port list. */ 5994 found = 0; 5995 fcport = NULL; 5996 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5997 if (memcmp(new_fcport->port_name, fcport->port_name, 5998 WWN_SIZE)) 5999 continue; 6000 6001 fcport->flags &= ~FCF_FABRIC_DEVICE; 6002 fcport->loop_id = new_fcport->loop_id; 6003 fcport->port_type = new_fcport->port_type; 6004 fcport->d_id.b24 = new_fcport->d_id.b24; 6005 memcpy(fcport->node_name, new_fcport->node_name, 6006 WWN_SIZE); 6007 fcport->scan_state = QLA_FCPORT_FOUND; 6008 if (fcport->login_retry == 0) { 6009 fcport->login_retry = vha->hw->login_retry_count; 6010 ql_dbg(ql_dbg_disc, vha, 0x2135, 6011 "Port login retry %8phN, lid 0x%04x retry cnt=%d.\n", 6012 fcport->port_name, fcport->loop_id, 6013 fcport->login_retry); 6014 } 6015 found++; 6016 break; 6017 } 6018 6019 if (!found) { 6020 /* New device, add to fcports list. */ 6021 list_add_tail(&new_fcport->list, &vha->vp_fcports); 6022 6023 /* Allocate a new replacement fcport. */ 6024 fcport = new_fcport; 6025 6026 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 6027 6028 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 6029 6030 if (new_fcport == NULL) { 6031 ql_log(ql_log_warn, vha, 0xd031, 6032 "Failed to allocate memory for fcport.\n"); 6033 rval = QLA_MEMORY_ALLOC_FAILED; 6034 goto err; 6035 } 6036 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 6037 new_fcport->flags &= ~FCF_FABRIC_DEVICE; 6038 } 6039 6040 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 6041 6042 /* Base iIDMA settings on HBA port speed. */ 6043 fcport->fp_speed = ha->link_data_rate; 6044 } 6045 6046 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6047 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6048 break; 6049 6050 if (fcport->scan_state == QLA_FCPORT_SCAN) { 6051 if ((qla_dual_mode_enabled(vha) || 6052 qla_ini_mode_enabled(vha)) && 6053 atomic_read(&fcport->state) == FCS_ONLINE) { 6054 qla2x00_mark_device_lost(vha, fcport, 6055 ql2xplogiabsentdevice); 6056 if (fcport->loop_id != FC_NO_LOOP_ID && 6057 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 6058 fcport->port_type != FCT_INITIATOR && 6059 fcport->port_type != FCT_BROADCAST) { 6060 ql_dbg(ql_dbg_disc, vha, 0x20f0, 6061 "%s %d %8phC post del sess\n", 6062 __func__, __LINE__, 6063 fcport->port_name); 6064 6065 qlt_schedule_sess_for_deletion(fcport); 6066 continue; 6067 } 6068 } 6069 } 6070 6071 if (fcport->scan_state == QLA_FCPORT_FOUND) 6072 qla24xx_fcport_handle_login(vha, fcport); 6073 } 6074 6075 qla2x00_free_fcport(new_fcport); 6076 6077 return rval; 6078 6079 err: 6080 ql_dbg(ql_dbg_disc, vha, 0x2098, 6081 "Configure local loop error exit: rval=%x.\n", rval); 6082 return rval; 6083 } 6084 6085 static void 6086 qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 6087 { 6088 int rval; 6089 uint16_t mb[MAILBOX_REGISTER_COUNT]; 6090 struct qla_hw_data *ha = vha->hw; 6091 6092 if (!IS_IIDMA_CAPABLE(ha)) 6093 return; 6094 6095 if (atomic_read(&fcport->state) != FCS_ONLINE) 6096 return; 6097 6098 if (fcport->fp_speed == PORT_SPEED_UNKNOWN || 6099 fcport->fp_speed > ha->link_data_rate || 6100 !ha->flags.gpsc_supported) 6101 return; 6102 6103 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed, 6104 mb); 6105 if (rval != QLA_SUCCESS) { 6106 ql_dbg(ql_dbg_disc, vha, 0x2004, 6107 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n", 6108 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]); 6109 } else { 6110 ql_dbg(ql_dbg_disc, vha, 0x2005, 6111 "iIDMA adjusted to %s GB/s (%X) on %8phN.\n", 6112 qla2x00_get_link_speed_str(ha, fcport->fp_speed), 6113 fcport->fp_speed, fcport->port_name); 6114 } 6115 } 6116 6117 void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport) 6118 { 6119 qla2x00_iidma_fcport(vha, fcport); 6120 qla24xx_update_fcport_fcp_prio(vha, fcport); 6121 } 6122 6123 int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport) 6124 { 6125 struct qla_work_evt *e; 6126 6127 e = qla2x00_alloc_work(vha, QLA_EVT_IIDMA); 6128 if (!e) 6129 return QLA_FUNCTION_FAILED; 6130 6131 e->u.fcport.fcport = fcport; 6132 return qla2x00_post_work(vha, e); 6133 } 6134 6135 /* qla2x00_reg_remote_port is reserved for Initiator Mode only.*/ 6136 static void 6137 qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport) 6138 { 6139 struct fc_rport_identifiers rport_ids; 6140 struct fc_rport *rport; 6141 unsigned long flags; 6142 6143 if (atomic_read(&fcport->state) == FCS_ONLINE) 6144 return; 6145 6146 rport_ids.node_name = wwn_to_u64(fcport->node_name); 6147 rport_ids.port_name = wwn_to_u64(fcport->port_name); 6148 rport_ids.port_id = fcport->d_id.b.domain << 16 | 6149 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa; 6150 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN; 6151 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids); 6152 if (!rport) { 6153 ql_log(ql_log_warn, vha, 0x2006, 6154 "Unable to allocate fc remote port.\n"); 6155 return; 6156 } 6157 6158 spin_lock_irqsave(fcport->vha->host->host_lock, flags); 6159 *((fc_port_t **)rport->dd_data) = fcport; 6160 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags); 6161 fcport->dev_loss_tmo = rport->dev_loss_tmo; 6162 6163 rport->supported_classes = fcport->supported_classes; 6164 6165 rport_ids.roles = FC_PORT_ROLE_UNKNOWN; 6166 if (fcport->port_type == FCT_INITIATOR) 6167 rport_ids.roles |= FC_PORT_ROLE_FCP_INITIATOR; 6168 if (fcport->port_type == FCT_TARGET) 6169 rport_ids.roles |= FC_PORT_ROLE_FCP_TARGET; 6170 if (fcport->port_type & FCT_NVME_INITIATOR) 6171 rport_ids.roles |= FC_PORT_ROLE_NVME_INITIATOR; 6172 if (fcport->port_type & FCT_NVME_TARGET) 6173 rport_ids.roles |= FC_PORT_ROLE_NVME_TARGET; 6174 if (fcport->port_type & FCT_NVME_DISCOVERY) 6175 rport_ids.roles |= FC_PORT_ROLE_NVME_DISCOVERY; 6176 6177 fc_remote_port_rolechg(rport, rport_ids.roles); 6178 6179 ql_dbg(ql_dbg_disc, vha, 0x20ee, 6180 "%s: %8phN. rport %ld:0:%d (%p) is %s mode\n", 6181 __func__, fcport->port_name, vha->host_no, 6182 rport->scsi_target_id, rport, 6183 (fcport->port_type == FCT_TARGET) ? "tgt" : 6184 ((fcport->port_type & FCT_NVME) ? "nvme" : "ini")); 6185 } 6186 6187 /* 6188 * qla2x00_update_fcport 6189 * Updates device on list. 6190 * 6191 * Input: 6192 * ha = adapter block pointer. 6193 * fcport = port structure pointer. 6194 * 6195 * Return: 6196 * 0 - Success 6197 * BIT_0 - error 6198 * 6199 * Context: 6200 * Kernel context. 6201 */ 6202 void 6203 qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport) 6204 { 6205 unsigned long flags; 6206 6207 if (IS_SW_RESV_ADDR(fcport->d_id)) 6208 return; 6209 6210 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n", 6211 __func__, fcport->port_name); 6212 6213 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 6214 fcport->login_retry = vha->hw->login_retry_count; 6215 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 6216 6217 spin_lock_irqsave(&vha->work_lock, flags); 6218 fcport->deleted = 0; 6219 spin_unlock_irqrestore(&vha->work_lock, flags); 6220 6221 if (vha->hw->current_topology == ISP_CFG_NL) 6222 fcport->logout_on_delete = 0; 6223 else 6224 fcport->logout_on_delete = 1; 6225 fcport->n2n_chip_reset = fcport->n2n_link_reset_cnt = 0; 6226 6227 if (fcport->tgt_link_down_time < fcport->dev_loss_tmo) { 6228 fcport->tgt_short_link_down_cnt++; 6229 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 6230 } 6231 6232 switch (vha->hw->current_topology) { 6233 case ISP_CFG_N: 6234 case ISP_CFG_NL: 6235 fcport->keep_nport_handle = 1; 6236 break; 6237 default: 6238 break; 6239 } 6240 6241 qla2x00_iidma_fcport(vha, fcport); 6242 6243 qla2x00_dfs_create_rport(vha, fcport); 6244 6245 qla24xx_update_fcport_fcp_prio(vha, fcport); 6246 6247 switch (vha->host->active_mode) { 6248 case MODE_INITIATOR: 6249 qla2x00_reg_remote_port(vha, fcport); 6250 break; 6251 case MODE_TARGET: 6252 if (!vha->vha_tgt.qla_tgt->tgt_stop && 6253 !vha->vha_tgt.qla_tgt->tgt_stopped) 6254 qlt_fc_port_added(vha, fcport); 6255 break; 6256 case MODE_DUAL: 6257 qla2x00_reg_remote_port(vha, fcport); 6258 if (!vha->vha_tgt.qla_tgt->tgt_stop && 6259 !vha->vha_tgt.qla_tgt->tgt_stopped) 6260 qlt_fc_port_added(vha, fcport); 6261 break; 6262 default: 6263 break; 6264 } 6265 6266 if (NVME_TARGET(vha->hw, fcport)) 6267 qla_nvme_register_remote(vha, fcport); 6268 6269 qla2x00_set_fcport_state(fcport, FCS_ONLINE); 6270 6271 if (IS_IIDMA_CAPABLE(vha->hw) && vha->hw->flags.gpsc_supported) { 6272 if (fcport->id_changed) { 6273 fcport->id_changed = 0; 6274 ql_dbg(ql_dbg_disc, vha, 0x20d7, 6275 "%s %d %8phC post gfpnid fcp_cnt %d\n", 6276 __func__, __LINE__, fcport->port_name, 6277 vha->fcport_count); 6278 qla24xx_post_gfpnid_work(vha, fcport); 6279 } else { 6280 ql_dbg(ql_dbg_disc, vha, 0x20d7, 6281 "%s %d %8phC post gpsc fcp_cnt %d\n", 6282 __func__, __LINE__, fcport->port_name, 6283 vha->fcport_count); 6284 qla24xx_post_gpsc_work(vha, fcport); 6285 } 6286 } 6287 6288 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_COMPLETE); 6289 } 6290 6291 void qla_register_fcport_fn(struct work_struct *work) 6292 { 6293 fc_port_t *fcport = container_of(work, struct fc_port, reg_work); 6294 u32 rscn_gen = fcport->rscn_gen; 6295 u16 data[2]; 6296 6297 if (IS_SW_RESV_ADDR(fcport->d_id)) 6298 return; 6299 6300 qla2x00_update_fcport(fcport->vha, fcport); 6301 6302 ql_dbg(ql_dbg_disc, fcport->vha, 0x911e, 6303 "%s rscn gen %d/%d next DS %d\n", __func__, 6304 rscn_gen, fcport->rscn_gen, fcport->next_disc_state); 6305 6306 if (rscn_gen != fcport->rscn_gen) { 6307 /* RSCN(s) came in while registration */ 6308 switch (fcport->next_disc_state) { 6309 case DSC_DELETE_PEND: 6310 qlt_schedule_sess_for_deletion(fcport); 6311 break; 6312 case DSC_ADISC: 6313 data[0] = data[1] = 0; 6314 qla2x00_post_async_adisc_work(fcport->vha, fcport, 6315 data); 6316 break; 6317 default: 6318 break; 6319 } 6320 } 6321 } 6322 6323 /* 6324 * qla2x00_configure_fabric 6325 * Setup SNS devices with loop ID's. 6326 * 6327 * Input: 6328 * ha = adapter block pointer. 6329 * 6330 * Returns: 6331 * 0 = success. 6332 * BIT_0 = error 6333 */ 6334 static int 6335 qla2x00_configure_fabric(scsi_qla_host_t *vha) 6336 { 6337 int rval; 6338 fc_port_t *fcport; 6339 uint16_t mb[MAILBOX_REGISTER_COUNT]; 6340 uint16_t loop_id; 6341 struct qla_hw_data *ha = vha->hw; 6342 int discovery_gen; 6343 6344 /* If FL port exists, then SNS is present */ 6345 if (IS_FWI2_CAPABLE(ha)) 6346 loop_id = NPH_F_PORT; 6347 else 6348 loop_id = SNS_FL_PORT; 6349 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1); 6350 if (rval != QLA_SUCCESS) { 6351 ql_dbg(ql_dbg_disc, vha, 0x20a0, 6352 "MBX_GET_PORT_NAME failed, No FL Port.\n"); 6353 6354 vha->device_flags &= ~SWITCH_FOUND; 6355 return (QLA_SUCCESS); 6356 } 6357 vha->device_flags |= SWITCH_FOUND; 6358 6359 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_port_name, 0); 6360 if (rval != QLA_SUCCESS) 6361 ql_dbg(ql_dbg_disc, vha, 0x20ff, 6362 "Failed to get Fabric Port Name\n"); 6363 6364 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) { 6365 rval = qla2x00_send_change_request(vha, 0x3, 0); 6366 if (rval != QLA_SUCCESS) 6367 ql_log(ql_log_warn, vha, 0x121, 6368 "Failed to enable receiving of RSCN requests: 0x%x.\n", 6369 rval); 6370 } 6371 6372 do { 6373 qla2x00_mgmt_svr_login(vha); 6374 6375 /* Ensure we are logged into the SNS. */ 6376 loop_id = NPH_SNS_LID(ha); 6377 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff, 6378 0xfc, mb, BIT_1|BIT_0); 6379 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { 6380 ql_dbg(ql_dbg_disc, vha, 0x20a1, 6381 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n", 6382 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval); 6383 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 6384 return rval; 6385 } 6386 6387 /* FDMI support. */ 6388 if (ql2xfdmienable && 6389 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags)) 6390 qla2x00_fdmi_register(vha); 6391 6392 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) { 6393 if (qla2x00_rft_id(vha)) { 6394 /* EMPTY */ 6395 ql_dbg(ql_dbg_disc, vha, 0x20a2, 6396 "Register FC-4 TYPE failed.\n"); 6397 if (test_bit(LOOP_RESYNC_NEEDED, 6398 &vha->dpc_flags)) 6399 break; 6400 } 6401 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) { 6402 /* EMPTY */ 6403 ql_dbg(ql_dbg_disc, vha, 0x209a, 6404 "Register FC-4 Features failed.\n"); 6405 if (test_bit(LOOP_RESYNC_NEEDED, 6406 &vha->dpc_flags)) 6407 break; 6408 } 6409 if (vha->flags.nvme_enabled) { 6410 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) { 6411 ql_dbg(ql_dbg_disc, vha, 0x2049, 6412 "Register NVME FC Type Features failed.\n"); 6413 } 6414 } 6415 if (qla2x00_rnn_id(vha)) { 6416 /* EMPTY */ 6417 ql_dbg(ql_dbg_disc, vha, 0x2104, 6418 "Register Node Name failed.\n"); 6419 if (test_bit(LOOP_RESYNC_NEEDED, 6420 &vha->dpc_flags)) 6421 break; 6422 } else if (qla2x00_rsnn_nn(vha)) { 6423 /* EMPTY */ 6424 ql_dbg(ql_dbg_disc, vha, 0x209b, 6425 "Register Symbolic Node Name failed.\n"); 6426 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6427 break; 6428 } 6429 } 6430 6431 6432 /* Mark the time right before querying FW for connected ports. 6433 * This process is long, asynchronous and by the time it's done, 6434 * collected information might not be accurate anymore. E.g. 6435 * disconnected port might have re-connected and a brand new 6436 * session has been created. In this case session's generation 6437 * will be newer than discovery_gen. */ 6438 qlt_do_generation_tick(vha, &discovery_gen); 6439 6440 if (USE_ASYNC_SCAN(ha)) { 6441 /* start of scan begins here */ 6442 vha->scan.rscn_gen_end = atomic_read(&vha->rscn_gen); 6443 qla_fab_scan_start(vha); 6444 } else { 6445 list_for_each_entry(fcport, &vha->vp_fcports, list) 6446 fcport->scan_state = QLA_FCPORT_SCAN; 6447 6448 rval = qla2x00_find_all_fabric_devs(vha); 6449 } 6450 if (rval != QLA_SUCCESS) 6451 break; 6452 } while (0); 6453 6454 if (!vha->nvme_local_port && vha->flags.nvme_enabled) 6455 qla_nvme_register_hba(vha); 6456 6457 if (rval) 6458 ql_dbg(ql_dbg_disc, vha, 0x2068, 6459 "Configure fabric error exit rval=%d.\n", rval); 6460 6461 return (rval); 6462 } 6463 6464 /* 6465 * qla2x00_find_all_fabric_devs 6466 * 6467 * Input: 6468 * ha = adapter block pointer. 6469 * dev = database device entry pointer. 6470 * 6471 * Returns: 6472 * 0 = success. 6473 * 6474 * Context: 6475 * Kernel context. 6476 */ 6477 static int 6478 qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha) 6479 { 6480 int rval; 6481 uint16_t loop_id; 6482 fc_port_t *fcport, *new_fcport; 6483 int found; 6484 6485 sw_info_t *swl; 6486 int swl_idx; 6487 int first_dev, last_dev; 6488 port_id_t wrap = {}, nxt_d_id; 6489 struct qla_hw_data *ha = vha->hw; 6490 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 6491 unsigned long flags; 6492 6493 rval = QLA_SUCCESS; 6494 6495 /* Try GID_PT to get device list, else GAN. */ 6496 if (!ha->swl) 6497 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t), 6498 GFP_KERNEL); 6499 swl = ha->swl; 6500 if (!swl) { 6501 /*EMPTY*/ 6502 ql_dbg(ql_dbg_disc, vha, 0x209c, 6503 "GID_PT allocations failed, fallback on GA_NXT.\n"); 6504 } else { 6505 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t)); 6506 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) { 6507 swl = NULL; 6508 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6509 return rval; 6510 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) { 6511 swl = NULL; 6512 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6513 return rval; 6514 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) { 6515 swl = NULL; 6516 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6517 return rval; 6518 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) { 6519 swl = NULL; 6520 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6521 return rval; 6522 } 6523 6524 /* If other queries succeeded probe for FC-4 type */ 6525 if (swl) { 6526 qla2x00_gff_id(vha, swl); 6527 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6528 return rval; 6529 } 6530 } 6531 swl_idx = 0; 6532 6533 /* Allocate temporary fcport for any new fcports discovered. */ 6534 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 6535 if (new_fcport == NULL) { 6536 ql_log(ql_log_warn, vha, 0x209d, 6537 "Failed to allocate memory for fcport.\n"); 6538 return (QLA_MEMORY_ALLOC_FAILED); 6539 } 6540 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 6541 /* Set start port ID scan at adapter ID. */ 6542 first_dev = 1; 6543 last_dev = 0; 6544 6545 /* Starting free loop ID. */ 6546 loop_id = ha->min_external_loopid; 6547 for (; loop_id <= ha->max_loop_id; loop_id++) { 6548 if (qla2x00_is_reserved_id(vha, loop_id)) 6549 continue; 6550 6551 if (ha->current_topology == ISP_CFG_FL && 6552 (atomic_read(&vha->loop_down_timer) || 6553 LOOP_TRANSITION(vha))) { 6554 atomic_set(&vha->loop_down_timer, 0); 6555 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 6556 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 6557 break; 6558 } 6559 6560 if (swl != NULL) { 6561 if (last_dev) { 6562 wrap.b24 = new_fcport->d_id.b24; 6563 } else { 6564 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24; 6565 memcpy(new_fcport->node_name, 6566 swl[swl_idx].node_name, WWN_SIZE); 6567 memcpy(new_fcport->port_name, 6568 swl[swl_idx].port_name, WWN_SIZE); 6569 memcpy(new_fcport->fabric_port_name, 6570 swl[swl_idx].fabric_port_name, WWN_SIZE); 6571 new_fcport->fp_speed = swl[swl_idx].fp_speed; 6572 new_fcport->fc4_type = swl[swl_idx].fc4_type; 6573 6574 new_fcport->nvme_flag = 0; 6575 if (vha->flags.nvme_enabled && 6576 swl[swl_idx].fc4_type & FS_FC4TYPE_NVME) { 6577 ql_log(ql_log_info, vha, 0x2131, 6578 "FOUND: NVME port %8phC as FC Type 28h\n", 6579 new_fcport->port_name); 6580 } 6581 6582 if (swl[swl_idx].d_id.b.rsvd_1 != 0) { 6583 last_dev = 1; 6584 } 6585 swl_idx++; 6586 } 6587 } else { 6588 /* Send GA_NXT to the switch */ 6589 rval = qla2x00_ga_nxt(vha, new_fcport); 6590 if (rval != QLA_SUCCESS) { 6591 ql_log(ql_log_warn, vha, 0x209e, 6592 "SNS scan failed -- assuming " 6593 "zero-entry result.\n"); 6594 rval = QLA_SUCCESS; 6595 break; 6596 } 6597 } 6598 6599 /* If wrap on switch device list, exit. */ 6600 if (first_dev) { 6601 wrap.b24 = new_fcport->d_id.b24; 6602 first_dev = 0; 6603 } else if (new_fcport->d_id.b24 == wrap.b24) { 6604 ql_dbg(ql_dbg_disc, vha, 0x209f, 6605 "Device wrap (%02x%02x%02x).\n", 6606 new_fcport->d_id.b.domain, 6607 new_fcport->d_id.b.area, 6608 new_fcport->d_id.b.al_pa); 6609 break; 6610 } 6611 6612 /* Bypass if same physical adapter. */ 6613 if (new_fcport->d_id.b24 == base_vha->d_id.b24) 6614 continue; 6615 6616 /* Bypass virtual ports of the same host. */ 6617 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24)) 6618 continue; 6619 6620 /* Bypass if same domain and area of adapter. */ 6621 if (((new_fcport->d_id.b24 & 0xffff00) == 6622 (vha->d_id.b24 & 0xffff00)) && ha->current_topology == 6623 ISP_CFG_FL) 6624 continue; 6625 6626 /* Bypass reserved domain fields. */ 6627 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0) 6628 continue; 6629 6630 /* Bypass ports whose FCP-4 type is not FCP_SCSI */ 6631 if (ql2xgffidenable && 6632 (!(new_fcport->fc4_type & FS_FC4TYPE_FCP) && 6633 new_fcport->fc4_type != 0)) 6634 continue; 6635 6636 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 6637 6638 /* Locate matching device in database. */ 6639 found = 0; 6640 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6641 if (memcmp(new_fcport->port_name, fcport->port_name, 6642 WWN_SIZE)) 6643 continue; 6644 6645 fcport->scan_state = QLA_FCPORT_FOUND; 6646 6647 found++; 6648 6649 /* Update port state. */ 6650 memcpy(fcport->fabric_port_name, 6651 new_fcport->fabric_port_name, WWN_SIZE); 6652 fcport->fp_speed = new_fcport->fp_speed; 6653 6654 /* 6655 * If address the same and state FCS_ONLINE 6656 * (or in target mode), nothing changed. 6657 */ 6658 if (fcport->d_id.b24 == new_fcport->d_id.b24 && 6659 (atomic_read(&fcport->state) == FCS_ONLINE || 6660 (vha->host->active_mode == MODE_TARGET))) { 6661 break; 6662 } 6663 6664 if (fcport->login_retry == 0) 6665 fcport->login_retry = 6666 vha->hw->login_retry_count; 6667 /* 6668 * If device was not a fabric device before. 6669 */ 6670 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) { 6671 fcport->d_id.b24 = new_fcport->d_id.b24; 6672 qla2x00_clear_loop_id(fcport); 6673 fcport->flags |= (FCF_FABRIC_DEVICE | 6674 FCF_LOGIN_NEEDED); 6675 break; 6676 } 6677 6678 /* 6679 * Port ID changed or device was marked to be updated; 6680 * Log it out if still logged in and mark it for 6681 * relogin later. 6682 */ 6683 if (qla_tgt_mode_enabled(base_vha)) { 6684 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080, 6685 "port changed FC ID, %8phC" 6686 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n", 6687 fcport->port_name, 6688 fcport->d_id.b.domain, 6689 fcport->d_id.b.area, 6690 fcport->d_id.b.al_pa, 6691 fcport->loop_id, 6692 new_fcport->d_id.b.domain, 6693 new_fcport->d_id.b.area, 6694 new_fcport->d_id.b.al_pa); 6695 fcport->d_id.b24 = new_fcport->d_id.b24; 6696 break; 6697 } 6698 6699 fcport->d_id.b24 = new_fcport->d_id.b24; 6700 fcport->flags |= FCF_LOGIN_NEEDED; 6701 break; 6702 } 6703 6704 if (found && NVME_TARGET(vha->hw, fcport)) { 6705 if (fcport->disc_state == DSC_DELETE_PEND) { 6706 qla2x00_set_fcport_disc_state(fcport, DSC_GNL); 6707 vha->fcport_count--; 6708 fcport->login_succ = 0; 6709 } 6710 } 6711 6712 if (found) { 6713 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 6714 continue; 6715 } 6716 /* If device was not in our fcports list, then add it. */ 6717 new_fcport->scan_state = QLA_FCPORT_FOUND; 6718 list_add_tail(&new_fcport->list, &vha->vp_fcports); 6719 6720 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 6721 6722 6723 /* Allocate a new replacement fcport. */ 6724 nxt_d_id.b24 = new_fcport->d_id.b24; 6725 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 6726 if (new_fcport == NULL) { 6727 ql_log(ql_log_warn, vha, 0xd032, 6728 "Memory allocation failed for fcport.\n"); 6729 return (QLA_MEMORY_ALLOC_FAILED); 6730 } 6731 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED); 6732 new_fcport->d_id.b24 = nxt_d_id.b24; 6733 } 6734 6735 qla2x00_free_fcport(new_fcport); 6736 6737 /* 6738 * Logout all previous fabric dev marked lost, except FCP2 devices. 6739 */ 6740 list_for_each_entry(fcport, &vha->vp_fcports, list) { 6741 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 6742 break; 6743 6744 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) 6745 continue; 6746 6747 if (fcport->scan_state == QLA_FCPORT_SCAN) { 6748 if ((qla_dual_mode_enabled(vha) || 6749 qla_ini_mode_enabled(vha)) && 6750 atomic_read(&fcport->state) == FCS_ONLINE) { 6751 qla2x00_mark_device_lost(vha, fcport, 6752 ql2xplogiabsentdevice); 6753 if (fcport->loop_id != FC_NO_LOOP_ID && 6754 (fcport->flags & FCF_FCP2_DEVICE) == 0 && 6755 fcport->port_type != FCT_INITIATOR && 6756 fcport->port_type != FCT_BROADCAST) { 6757 ql_dbg(ql_dbg_disc, vha, 0x20f0, 6758 "%s %d %8phC post del sess\n", 6759 __func__, __LINE__, 6760 fcport->port_name); 6761 qlt_schedule_sess_for_deletion(fcport); 6762 continue; 6763 } 6764 } 6765 } 6766 6767 if (fcport->scan_state == QLA_FCPORT_FOUND && 6768 (fcport->flags & FCF_LOGIN_NEEDED) != 0) 6769 qla24xx_fcport_handle_login(vha, fcport); 6770 } 6771 return (rval); 6772 } 6773 6774 /* FW does not set aside Loop id for MGMT Server/FFFFFAh */ 6775 int 6776 qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *vha) 6777 { 6778 int loop_id = FC_NO_LOOP_ID; 6779 int lid = NPH_MGMT_SERVER - vha->vp_idx; 6780 unsigned long flags; 6781 struct qla_hw_data *ha = vha->hw; 6782 6783 if (vha->vp_idx == 0) { 6784 set_bit(NPH_MGMT_SERVER, ha->loop_id_map); 6785 return NPH_MGMT_SERVER; 6786 } 6787 6788 /* pick id from high and work down to low */ 6789 spin_lock_irqsave(&ha->vport_slock, flags); 6790 for (; lid > 0; lid--) { 6791 if (!test_bit(lid, vha->hw->loop_id_map)) { 6792 set_bit(lid, vha->hw->loop_id_map); 6793 loop_id = lid; 6794 break; 6795 } 6796 } 6797 spin_unlock_irqrestore(&ha->vport_slock, flags); 6798 6799 return loop_id; 6800 } 6801 6802 /* 6803 * qla2x00_fabric_login 6804 * Issue fabric login command. 6805 * 6806 * Input: 6807 * ha = adapter block pointer. 6808 * device = pointer to FC device type structure. 6809 * 6810 * Returns: 6811 * 0 - Login successfully 6812 * 1 - Login failed 6813 * 2 - Initiator device 6814 * 3 - Fatal error 6815 */ 6816 int 6817 qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport, 6818 uint16_t *next_loopid) 6819 { 6820 int rval; 6821 int retry; 6822 uint16_t tmp_loopid; 6823 uint16_t mb[MAILBOX_REGISTER_COUNT]; 6824 struct qla_hw_data *ha = vha->hw; 6825 6826 retry = 0; 6827 tmp_loopid = 0; 6828 6829 for (;;) { 6830 ql_dbg(ql_dbg_disc, vha, 0x2000, 6831 "Trying Fabric Login w/loop id 0x%04x for port " 6832 "%02x%02x%02x.\n", 6833 fcport->loop_id, fcport->d_id.b.domain, 6834 fcport->d_id.b.area, fcport->d_id.b.al_pa); 6835 6836 /* Login fcport on switch. */ 6837 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id, 6838 fcport->d_id.b.domain, fcport->d_id.b.area, 6839 fcport->d_id.b.al_pa, mb, BIT_0); 6840 if (rval != QLA_SUCCESS) { 6841 return rval; 6842 } 6843 if (mb[0] == MBS_PORT_ID_USED) { 6844 /* 6845 * Device has another loop ID. The firmware team 6846 * recommends the driver perform an implicit login with 6847 * the specified ID again. The ID we just used is save 6848 * here so we return with an ID that can be tried by 6849 * the next login. 6850 */ 6851 retry++; 6852 tmp_loopid = fcport->loop_id; 6853 fcport->loop_id = mb[1]; 6854 6855 ql_dbg(ql_dbg_disc, vha, 0x2001, 6856 "Fabric Login: port in use - next loop " 6857 "id=0x%04x, port id= %02x%02x%02x.\n", 6858 fcport->loop_id, fcport->d_id.b.domain, 6859 fcport->d_id.b.area, fcport->d_id.b.al_pa); 6860 6861 } else if (mb[0] == MBS_COMMAND_COMPLETE) { 6862 /* 6863 * Login succeeded. 6864 */ 6865 if (retry) { 6866 /* A retry occurred before. */ 6867 *next_loopid = tmp_loopid; 6868 } else { 6869 /* 6870 * No retry occurred before. Just increment the 6871 * ID value for next login. 6872 */ 6873 *next_loopid = (fcport->loop_id + 1); 6874 } 6875 6876 if (mb[1] & BIT_0) { 6877 fcport->port_type = FCT_INITIATOR; 6878 } else { 6879 fcport->port_type = FCT_TARGET; 6880 if (mb[1] & BIT_1) { 6881 fcport->flags |= FCF_FCP2_DEVICE; 6882 } 6883 } 6884 6885 if (mb[10] & BIT_0) 6886 fcport->supported_classes |= FC_COS_CLASS2; 6887 if (mb[10] & BIT_1) 6888 fcport->supported_classes |= FC_COS_CLASS3; 6889 6890 if (IS_FWI2_CAPABLE(ha)) { 6891 if (mb[10] & BIT_7) 6892 fcport->flags |= 6893 FCF_CONF_COMP_SUPPORTED; 6894 } 6895 6896 rval = QLA_SUCCESS; 6897 break; 6898 } else if (mb[0] == MBS_LOOP_ID_USED) { 6899 /* 6900 * Loop ID already used, try next loop ID. 6901 */ 6902 fcport->loop_id++; 6903 rval = qla2x00_find_new_loop_id(vha, fcport); 6904 if (rval != QLA_SUCCESS) { 6905 /* Ran out of loop IDs to use */ 6906 break; 6907 } 6908 } else if (mb[0] == MBS_COMMAND_ERROR) { 6909 /* 6910 * Firmware possibly timed out during login. If NO 6911 * retries are left to do then the device is declared 6912 * dead. 6913 */ 6914 *next_loopid = fcport->loop_id; 6915 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 6916 fcport->d_id.b.domain, fcport->d_id.b.area, 6917 fcport->d_id.b.al_pa); 6918 qla2x00_mark_device_lost(vha, fcport, 1); 6919 6920 rval = 1; 6921 break; 6922 } else { 6923 /* 6924 * unrecoverable / not handled error 6925 */ 6926 ql_dbg(ql_dbg_disc, vha, 0x2002, 6927 "Failed=%x port_id=%02x%02x%02x loop_id=%x " 6928 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain, 6929 fcport->d_id.b.area, fcport->d_id.b.al_pa, 6930 fcport->loop_id, jiffies); 6931 6932 *next_loopid = fcport->loop_id; 6933 ha->isp_ops->fabric_logout(vha, fcport->loop_id, 6934 fcport->d_id.b.domain, fcport->d_id.b.area, 6935 fcport->d_id.b.al_pa); 6936 qla2x00_clear_loop_id(fcport); 6937 fcport->login_retry = 0; 6938 6939 rval = 3; 6940 break; 6941 } 6942 } 6943 6944 return (rval); 6945 } 6946 6947 /* 6948 * qla2x00_local_device_login 6949 * Issue local device login command. 6950 * 6951 * Input: 6952 * ha = adapter block pointer. 6953 * loop_id = loop id of device to login to. 6954 * 6955 * Returns (Where's the #define!!!!): 6956 * 0 - Login successfully 6957 * 1 - Login failed 6958 * 3 - Fatal error 6959 */ 6960 int 6961 qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport) 6962 { 6963 int rval; 6964 uint16_t mb[MAILBOX_REGISTER_COUNT]; 6965 6966 memset(mb, 0, sizeof(mb)); 6967 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0); 6968 if (rval == QLA_SUCCESS) { 6969 /* Interrogate mailbox registers for any errors */ 6970 if (mb[0] == MBS_COMMAND_ERROR) 6971 rval = 1; 6972 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR) 6973 /* device not in PCB table */ 6974 rval = 3; 6975 } 6976 6977 return (rval); 6978 } 6979 6980 /* 6981 * qla2x00_loop_resync 6982 * Resync with fibre channel devices. 6983 * 6984 * Input: 6985 * ha = adapter block pointer. 6986 * 6987 * Returns: 6988 * 0 = success 6989 */ 6990 int 6991 qla2x00_loop_resync(scsi_qla_host_t *vha) 6992 { 6993 int rval = QLA_SUCCESS; 6994 uint32_t wait_time; 6995 6996 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 6997 if (vha->flags.online) { 6998 if (!(rval = qla2x00_fw_ready(vha))) { 6999 /* Wait at most MAX_TARGET RSCNs for a stable link. */ 7000 wait_time = 256; 7001 do { 7002 if (!IS_QLAFX00(vha->hw)) { 7003 /* 7004 * Issue a marker after FW becomes 7005 * ready. 7006 */ 7007 qla2x00_marker(vha, vha->hw->base_qpair, 7008 0, 0, MK_SYNC_ALL); 7009 vha->marker_needed = 0; 7010 } 7011 7012 /* Remap devices on Loop. */ 7013 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 7014 7015 if (IS_QLAFX00(vha->hw)) 7016 qlafx00_configure_devices(vha); 7017 else 7018 qla2x00_configure_loop(vha); 7019 7020 wait_time--; 7021 } while (!atomic_read(&vha->loop_down_timer) && 7022 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 7023 && wait_time && (test_bit(LOOP_RESYNC_NEEDED, 7024 &vha->dpc_flags))); 7025 } 7026 } 7027 7028 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) 7029 return (QLA_FUNCTION_FAILED); 7030 7031 if (rval) 7032 ql_dbg(ql_dbg_disc, vha, 0x206c, 7033 "%s *** FAILED ***.\n", __func__); 7034 7035 return (rval); 7036 } 7037 7038 /* 7039 * qla2x00_perform_loop_resync 7040 * Description: This function will set the appropriate flags and call 7041 * qla2x00_loop_resync. If successful loop will be resynced 7042 * Arguments : scsi_qla_host_t pointer 7043 * returm : Success or Failure 7044 */ 7045 7046 int qla2x00_perform_loop_resync(scsi_qla_host_t *ha) 7047 { 7048 int32_t rval = 0; 7049 7050 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) { 7051 /*Configure the flags so that resync happens properly*/ 7052 atomic_set(&ha->loop_down_timer, 0); 7053 if (!(ha->device_flags & DFLG_NO_CABLE)) { 7054 atomic_set(&ha->loop_state, LOOP_UP); 7055 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags); 7056 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags); 7057 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags); 7058 7059 rval = qla2x00_loop_resync(ha); 7060 } else 7061 atomic_set(&ha->loop_state, LOOP_DEAD); 7062 7063 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags); 7064 } 7065 7066 return rval; 7067 } 7068 7069 /* Assumes idc_lock always held on entry */ 7070 void 7071 qla83xx_reset_ownership(scsi_qla_host_t *vha) 7072 { 7073 struct qla_hw_data *ha = vha->hw; 7074 uint32_t drv_presence, drv_presence_mask; 7075 uint32_t dev_part_info1, dev_part_info2, class_type; 7076 uint32_t class_type_mask = 0x3; 7077 uint16_t fcoe_other_function = 0xffff, i; 7078 7079 if (IS_QLA8044(ha)) { 7080 drv_presence = qla8044_rd_direct(vha, 7081 QLA8044_CRB_DRV_ACTIVE_INDEX); 7082 dev_part_info1 = qla8044_rd_direct(vha, 7083 QLA8044_CRB_DEV_PART_INFO_INDEX); 7084 dev_part_info2 = qla8044_rd_direct(vha, 7085 QLA8044_CRB_DEV_PART_INFO2); 7086 } else { 7087 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 7088 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1); 7089 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2); 7090 } 7091 for (i = 0; i < 8; i++) { 7092 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask); 7093 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 7094 (i != ha->portnum)) { 7095 fcoe_other_function = i; 7096 break; 7097 } 7098 } 7099 if (fcoe_other_function == 0xffff) { 7100 for (i = 0; i < 8; i++) { 7101 class_type = ((dev_part_info2 >> (i * 4)) & 7102 class_type_mask); 7103 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) && 7104 ((i + 8) != ha->portnum)) { 7105 fcoe_other_function = i + 8; 7106 break; 7107 } 7108 } 7109 } 7110 /* 7111 * Prepare drv-presence mask based on fcoe functions present. 7112 * However consider only valid physical fcoe function numbers (0-15). 7113 */ 7114 drv_presence_mask = ~((1 << (ha->portnum)) | 7115 ((fcoe_other_function == 0xffff) ? 7116 0 : (1 << (fcoe_other_function)))); 7117 7118 /* We are the reset owner iff: 7119 * - No other protocol drivers present. 7120 * - This is the lowest among fcoe functions. */ 7121 if (!(drv_presence & drv_presence_mask) && 7122 (ha->portnum < fcoe_other_function)) { 7123 ql_dbg(ql_dbg_p3p, vha, 0xb07f, 7124 "This host is Reset owner.\n"); 7125 ha->flags.nic_core_reset_owner = 1; 7126 } 7127 } 7128 7129 static int 7130 __qla83xx_set_drv_ack(scsi_qla_host_t *vha) 7131 { 7132 int rval = QLA_SUCCESS; 7133 struct qla_hw_data *ha = vha->hw; 7134 uint32_t drv_ack; 7135 7136 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 7137 if (rval == QLA_SUCCESS) { 7138 drv_ack |= (1 << ha->portnum); 7139 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 7140 } 7141 7142 return rval; 7143 } 7144 7145 static int 7146 __qla83xx_clear_drv_ack(scsi_qla_host_t *vha) 7147 { 7148 int rval = QLA_SUCCESS; 7149 struct qla_hw_data *ha = vha->hw; 7150 uint32_t drv_ack; 7151 7152 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 7153 if (rval == QLA_SUCCESS) { 7154 drv_ack &= ~(1 << ha->portnum); 7155 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack); 7156 } 7157 7158 return rval; 7159 } 7160 7161 /* Assumes idc-lock always held on entry */ 7162 void 7163 qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type) 7164 { 7165 struct qla_hw_data *ha = vha->hw; 7166 uint32_t idc_audit_reg = 0, duration_secs = 0; 7167 7168 switch (audit_type) { 7169 case IDC_AUDIT_TIMESTAMP: 7170 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000); 7171 idc_audit_reg = (ha->portnum) | 7172 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8); 7173 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 7174 break; 7175 7176 case IDC_AUDIT_COMPLETION: 7177 duration_secs = ((jiffies_to_msecs(jiffies) - 7178 jiffies_to_msecs(ha->idc_audit_ts)) / 1000); 7179 idc_audit_reg = (ha->portnum) | 7180 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8); 7181 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg); 7182 break; 7183 7184 default: 7185 ql_log(ql_log_warn, vha, 0xb078, 7186 "Invalid audit type specified.\n"); 7187 break; 7188 } 7189 } 7190 7191 /* Assumes idc_lock always held on entry */ 7192 static int 7193 qla83xx_initiating_reset(scsi_qla_host_t *vha) 7194 { 7195 struct qla_hw_data *ha = vha->hw; 7196 uint32_t idc_control, dev_state; 7197 7198 __qla83xx_get_idc_control(vha, &idc_control); 7199 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) { 7200 ql_log(ql_log_info, vha, 0xb080, 7201 "NIC Core reset has been disabled. idc-control=0x%x\n", 7202 idc_control); 7203 return QLA_FUNCTION_FAILED; 7204 } 7205 7206 /* Set NEED-RESET iff in READY state and we are the reset-owner */ 7207 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 7208 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) { 7209 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, 7210 QLA8XXX_DEV_NEED_RESET); 7211 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n"); 7212 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP); 7213 } else { 7214 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", 7215 qdev_state(dev_state)); 7216 7217 /* SV: XXX: Is timeout required here? */ 7218 /* Wait for IDC state change READY -> NEED_RESET */ 7219 while (dev_state == QLA8XXX_DEV_READY) { 7220 qla83xx_idc_unlock(vha, 0); 7221 msleep(200); 7222 qla83xx_idc_lock(vha, 0); 7223 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state); 7224 } 7225 } 7226 7227 /* Send IDC ack by writing to drv-ack register */ 7228 __qla83xx_set_drv_ack(vha); 7229 7230 return QLA_SUCCESS; 7231 } 7232 7233 int 7234 __qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control) 7235 { 7236 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 7237 } 7238 7239 int 7240 __qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control) 7241 { 7242 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control); 7243 } 7244 7245 static int 7246 qla83xx_check_driver_presence(scsi_qla_host_t *vha) 7247 { 7248 uint32_t drv_presence = 0; 7249 struct qla_hw_data *ha = vha->hw; 7250 7251 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 7252 if (drv_presence & (1 << ha->portnum)) 7253 return QLA_SUCCESS; 7254 else 7255 return QLA_TEST_FAILED; 7256 } 7257 7258 int 7259 qla83xx_nic_core_reset(scsi_qla_host_t *vha) 7260 { 7261 int rval = QLA_SUCCESS; 7262 struct qla_hw_data *ha = vha->hw; 7263 7264 ql_dbg(ql_dbg_p3p, vha, 0xb058, 7265 "Entered %s().\n", __func__); 7266 7267 if (vha->device_flags & DFLG_DEV_FAILED) { 7268 ql_log(ql_log_warn, vha, 0xb059, 7269 "Device in unrecoverable FAILED state.\n"); 7270 return QLA_FUNCTION_FAILED; 7271 } 7272 7273 qla83xx_idc_lock(vha, 0); 7274 7275 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) { 7276 ql_log(ql_log_warn, vha, 0xb05a, 7277 "Function=0x%x has been removed from IDC participation.\n", 7278 ha->portnum); 7279 rval = QLA_FUNCTION_FAILED; 7280 goto exit; 7281 } 7282 7283 qla83xx_reset_ownership(vha); 7284 7285 rval = qla83xx_initiating_reset(vha); 7286 7287 /* 7288 * Perform reset if we are the reset-owner, 7289 * else wait till IDC state changes to READY/FAILED. 7290 */ 7291 if (rval == QLA_SUCCESS) { 7292 rval = qla83xx_idc_state_handler(vha); 7293 7294 if (rval == QLA_SUCCESS) 7295 ha->flags.nic_core_hung = 0; 7296 __qla83xx_clear_drv_ack(vha); 7297 } 7298 7299 exit: 7300 qla83xx_idc_unlock(vha, 0); 7301 7302 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__); 7303 7304 return rval; 7305 } 7306 7307 int 7308 qla2xxx_mctp_dump(scsi_qla_host_t *vha) 7309 { 7310 struct qla_hw_data *ha = vha->hw; 7311 int rval = QLA_FUNCTION_FAILED; 7312 7313 if (!IS_MCTP_CAPABLE(ha)) { 7314 /* This message can be removed from the final version */ 7315 ql_log(ql_log_info, vha, 0x506d, 7316 "This board is not MCTP capable\n"); 7317 return rval; 7318 } 7319 7320 if (!ha->mctp_dump) { 7321 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev, 7322 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL); 7323 7324 if (!ha->mctp_dump) { 7325 ql_log(ql_log_warn, vha, 0x506e, 7326 "Failed to allocate memory for mctp dump\n"); 7327 return rval; 7328 } 7329 } 7330 7331 #define MCTP_DUMP_STR_ADDR 0x00000000 7332 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma, 7333 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4); 7334 if (rval != QLA_SUCCESS) { 7335 ql_log(ql_log_warn, vha, 0x506f, 7336 "Failed to capture mctp dump\n"); 7337 } else { 7338 ql_log(ql_log_info, vha, 0x5070, 7339 "Mctp dump capture for host (%ld/%p).\n", 7340 vha->host_no, ha->mctp_dump); 7341 ha->mctp_dumped = 1; 7342 } 7343 7344 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) { 7345 ha->flags.nic_core_reset_hdlr_active = 1; 7346 rval = qla83xx_restart_nic_firmware(vha); 7347 if (rval) 7348 /* NIC Core reset failed. */ 7349 ql_log(ql_log_warn, vha, 0x5071, 7350 "Failed to restart nic firmware\n"); 7351 else 7352 ql_dbg(ql_dbg_p3p, vha, 0xb084, 7353 "Restarted NIC firmware successfully.\n"); 7354 ha->flags.nic_core_reset_hdlr_active = 0; 7355 } 7356 7357 return rval; 7358 7359 } 7360 7361 /* 7362 * qla2x00_quiesce_io 7363 * Description: This function will block the new I/Os 7364 * Its not aborting any I/Os as context 7365 * is not destroyed during quiescence 7366 * Arguments: scsi_qla_host_t 7367 * return : void 7368 */ 7369 void 7370 qla2x00_quiesce_io(scsi_qla_host_t *vha) 7371 { 7372 struct qla_hw_data *ha = vha->hw; 7373 struct scsi_qla_host *vp, *tvp; 7374 unsigned long flags; 7375 7376 ql_dbg(ql_dbg_dpc, vha, 0x401d, 7377 "Quiescing I/O - ha=%p.\n", ha); 7378 7379 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME); 7380 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 7381 atomic_set(&vha->loop_state, LOOP_DOWN); 7382 qla2x00_mark_all_devices_lost(vha); 7383 7384 spin_lock_irqsave(&ha->vport_slock, flags); 7385 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7386 atomic_inc(&vp->vref_count); 7387 spin_unlock_irqrestore(&ha->vport_slock, flags); 7388 7389 qla2x00_mark_all_devices_lost(vp); 7390 7391 spin_lock_irqsave(&ha->vport_slock, flags); 7392 atomic_dec(&vp->vref_count); 7393 } 7394 spin_unlock_irqrestore(&ha->vport_slock, flags); 7395 } else { 7396 if (!atomic_read(&vha->loop_down_timer)) 7397 atomic_set(&vha->loop_down_timer, 7398 LOOP_DOWN_TIME); 7399 } 7400 /* Wait for pending cmds to complete */ 7401 WARN_ON_ONCE(qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) 7402 != QLA_SUCCESS); 7403 } 7404 7405 void 7406 qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha) 7407 { 7408 struct qla_hw_data *ha = vha->hw; 7409 struct scsi_qla_host *vp, *tvp; 7410 unsigned long flags; 7411 fc_port_t *fcport; 7412 u16 i; 7413 7414 /* For ISP82XX, driver waits for completion of the commands. 7415 * online flag should be set. 7416 */ 7417 if (!(IS_P3P_TYPE(ha))) 7418 vha->flags.online = 0; 7419 ha->flags.chip_reset_done = 0; 7420 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 7421 vha->qla_stats.total_isp_aborts++; 7422 7423 ql_log(ql_log_info, vha, 0x00af, 7424 "Performing ISP error recovery - ha=%p.\n", ha); 7425 7426 ha->flags.purge_mbox = 1; 7427 /* For ISP82XX, reset_chip is just disabling interrupts. 7428 * Driver waits for the completion of the commands. 7429 * the interrupts need to be enabled. 7430 */ 7431 if (!(IS_P3P_TYPE(ha))) 7432 ha->isp_ops->reset_chip(vha); 7433 7434 ha->link_data_rate = PORT_SPEED_UNKNOWN; 7435 SAVE_TOPO(ha); 7436 ha->flags.rida_fmt2 = 0; 7437 ha->flags.n2n_ae = 0; 7438 ha->flags.lip_ae = 0; 7439 ha->current_topology = 0; 7440 QLA_FW_STOPPED(ha); 7441 ha->flags.fw_init_done = 0; 7442 ha->chip_reset++; 7443 ha->base_qpair->chip_reset = ha->chip_reset; 7444 ha->base_qpair->cmd_cnt = ha->base_qpair->cmd_completion_cnt = 0; 7445 ha->base_qpair->prev_completion_cnt = 0; 7446 for (i = 0; i < ha->max_qpairs; i++) { 7447 if (ha->queue_pair_map[i]) { 7448 ha->queue_pair_map[i]->chip_reset = 7449 ha->base_qpair->chip_reset; 7450 ha->queue_pair_map[i]->cmd_cnt = 7451 ha->queue_pair_map[i]->cmd_completion_cnt = 0; 7452 ha->base_qpair->prev_completion_cnt = 0; 7453 } 7454 } 7455 7456 /* purge MBox commands */ 7457 spin_lock_irqsave(&ha->hardware_lock, flags); 7458 if (test_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags)) { 7459 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags); 7460 complete(&ha->mbx_intr_comp); 7461 } 7462 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7463 7464 i = 0; 7465 while (atomic_read(&ha->num_pend_mbx_stage2) || 7466 atomic_read(&ha->num_pend_mbx_stage1)) { 7467 msleep(20); 7468 i++; 7469 if (i > 50) 7470 break; 7471 } 7472 ha->flags.purge_mbox = 0; 7473 7474 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 7475 if (atomic_read(&vha->loop_state) != LOOP_DOWN) { 7476 atomic_set(&vha->loop_state, LOOP_DOWN); 7477 qla2x00_mark_all_devices_lost(vha); 7478 7479 spin_lock_irqsave(&ha->vport_slock, flags); 7480 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7481 atomic_inc(&vp->vref_count); 7482 spin_unlock_irqrestore(&ha->vport_slock, flags); 7483 7484 qla2x00_mark_all_devices_lost(vp); 7485 7486 spin_lock_irqsave(&ha->vport_slock, flags); 7487 atomic_dec(&vp->vref_count); 7488 } 7489 spin_unlock_irqrestore(&ha->vport_slock, flags); 7490 } else { 7491 if (!atomic_read(&vha->loop_down_timer)) 7492 atomic_set(&vha->loop_down_timer, 7493 LOOP_DOWN_TIME); 7494 } 7495 7496 /* Clear all async request states across all VPs. */ 7497 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7498 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7499 fcport->scan_state = 0; 7500 } 7501 spin_lock_irqsave(&ha->vport_slock, flags); 7502 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7503 atomic_inc(&vp->vref_count); 7504 spin_unlock_irqrestore(&ha->vport_slock, flags); 7505 7506 list_for_each_entry(fcport, &vp->vp_fcports, list) 7507 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7508 7509 spin_lock_irqsave(&ha->vport_slock, flags); 7510 atomic_dec(&vp->vref_count); 7511 } 7512 spin_unlock_irqrestore(&ha->vport_slock, flags); 7513 7514 /* Make sure for ISP 82XX IO DMA is complete */ 7515 if (IS_P3P_TYPE(ha)) { 7516 qla82xx_chip_reset_cleanup(vha); 7517 ql_log(ql_log_info, vha, 0x00b4, 7518 "Done chip reset cleanup.\n"); 7519 7520 /* Done waiting for pending commands. Reset online flag */ 7521 vha->flags.online = 0; 7522 } 7523 7524 /* Requeue all commands in outstanding command list. */ 7525 qla2x00_abort_all_cmds(vha, DID_RESET << 16); 7526 /* memory barrier */ 7527 wmb(); 7528 } 7529 7530 /* 7531 * qla2x00_abort_isp 7532 * Resets ISP and aborts all outstanding commands. 7533 * 7534 * Input: 7535 * ha = adapter block pointer. 7536 * 7537 * Returns: 7538 * 0 = success 7539 */ 7540 int 7541 qla2x00_abort_isp(scsi_qla_host_t *vha) 7542 { 7543 uint8_t status = 0; 7544 struct qla_hw_data *ha = vha->hw; 7545 struct scsi_qla_host *vp, *tvp; 7546 struct req_que *req = ha->req_q_map[0]; 7547 unsigned long flags; 7548 fc_port_t *fcport; 7549 7550 if (vha->flags.online) { 7551 qla2x00_abort_isp_cleanup(vha); 7552 7553 vha->dport_status |= DPORT_DIAG_CHIP_RESET_IN_PROGRESS; 7554 vha->dport_status &= ~DPORT_DIAG_IN_PROGRESS; 7555 7556 if (vha->hw->flags.port_isolated) 7557 return status; 7558 7559 if (qla2x00_isp_reg_stat(ha)) { 7560 ql_log(ql_log_info, vha, 0x803f, 7561 "ISP Abort - ISP reg disconnect, exiting.\n"); 7562 return status; 7563 } 7564 7565 if (test_and_clear_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags)) { 7566 ha->flags.chip_reset_done = 1; 7567 vha->flags.online = 1; 7568 status = 0; 7569 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7570 return status; 7571 } 7572 7573 if (IS_QLA8031(ha)) { 7574 ql_dbg(ql_dbg_p3p, vha, 0xb05c, 7575 "Clearing fcoe driver presence.\n"); 7576 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS) 7577 ql_dbg(ql_dbg_p3p, vha, 0xb073, 7578 "Error while clearing DRV-Presence.\n"); 7579 } 7580 7581 if (unlikely(pci_channel_offline(ha->pdev) && 7582 ha->flags.pci_channel_io_perm_failure)) { 7583 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7584 status = 0; 7585 return status; 7586 } 7587 7588 switch (vha->qlini_mode) { 7589 case QLA2XXX_INI_MODE_DISABLED: 7590 if (!qla_tgt_mode_enabled(vha)) 7591 return 0; 7592 break; 7593 case QLA2XXX_INI_MODE_DUAL: 7594 if (!qla_dual_mode_enabled(vha) && 7595 !qla_ini_mode_enabled(vha)) 7596 return 0; 7597 break; 7598 case QLA2XXX_INI_MODE_ENABLED: 7599 default: 7600 break; 7601 } 7602 7603 ha->isp_ops->get_flash_version(vha, req->ring); 7604 7605 if (qla2x00_isp_reg_stat(ha)) { 7606 ql_log(ql_log_info, vha, 0x803f, 7607 "ISP Abort - ISP reg disconnect pre nvram config, exiting.\n"); 7608 return status; 7609 } 7610 ha->isp_ops->nvram_config(vha); 7611 7612 if (qla2x00_isp_reg_stat(ha)) { 7613 ql_log(ql_log_info, vha, 0x803f, 7614 "ISP Abort - ISP reg disconnect post nvmram config, exiting.\n"); 7615 return status; 7616 } 7617 7618 /* User may have updated [fcp|nvme] prefer in flash */ 7619 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7620 if (NVME_PRIORITY(ha, fcport)) 7621 fcport->do_prli_nvme = 1; 7622 else 7623 fcport->do_prli_nvme = 0; 7624 } 7625 7626 if (!qla2x00_restart_isp(vha)) { 7627 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7628 7629 if (!atomic_read(&vha->loop_down_timer)) { 7630 /* 7631 * Issue marker command only when we are going 7632 * to start the I/O . 7633 */ 7634 vha->marker_needed = 1; 7635 } 7636 7637 vha->flags.online = 1; 7638 7639 ha->isp_ops->enable_intrs(ha); 7640 7641 ha->isp_abort_cnt = 0; 7642 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7643 7644 if (IS_QLA81XX(ha) || IS_QLA8031(ha)) 7645 qla2x00_get_fw_version(vha); 7646 7647 } else { /* failed the ISP abort */ 7648 vha->flags.online = 1; 7649 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) { 7650 if (ha->isp_abort_cnt == 0) { 7651 ql_log(ql_log_fatal, vha, 0x8035, 7652 "ISP error recover failed - " 7653 "board disabled.\n"); 7654 /* 7655 * The next call disables the board 7656 * completely. 7657 */ 7658 qla2x00_abort_isp_cleanup(vha); 7659 vha->flags.online = 0; 7660 clear_bit(ISP_ABORT_RETRY, 7661 &vha->dpc_flags); 7662 status = 0; 7663 } else { /* schedule another ISP abort */ 7664 ha->isp_abort_cnt--; 7665 ql_dbg(ql_dbg_taskm, vha, 0x8020, 7666 "ISP abort - retry remaining %d.\n", 7667 ha->isp_abort_cnt); 7668 status = 1; 7669 } 7670 } else { 7671 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT; 7672 ql_dbg(ql_dbg_taskm, vha, 0x8021, 7673 "ISP error recovery - retrying (%d) " 7674 "more times.\n", ha->isp_abort_cnt); 7675 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 7676 status = 1; 7677 } 7678 } 7679 7680 } 7681 7682 if (vha->hw->flags.port_isolated) { 7683 qla2x00_abort_isp_cleanup(vha); 7684 return status; 7685 } 7686 7687 if (!status) { 7688 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__); 7689 qla2x00_configure_hba(vha); 7690 spin_lock_irqsave(&ha->vport_slock, flags); 7691 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7692 if (vp->vp_idx) { 7693 atomic_inc(&vp->vref_count); 7694 spin_unlock_irqrestore(&ha->vport_slock, flags); 7695 7696 /* User may have updated [fcp|nvme] prefer in flash */ 7697 list_for_each_entry(fcport, &vp->vp_fcports, list) { 7698 if (NVME_PRIORITY(ha, fcport)) 7699 fcport->do_prli_nvme = 1; 7700 else 7701 fcport->do_prli_nvme = 0; 7702 } 7703 7704 qla2x00_vp_abort_isp(vp); 7705 7706 spin_lock_irqsave(&ha->vport_slock, flags); 7707 atomic_dec(&vp->vref_count); 7708 } 7709 } 7710 spin_unlock_irqrestore(&ha->vport_slock, flags); 7711 7712 if (IS_QLA8031(ha)) { 7713 ql_dbg(ql_dbg_p3p, vha, 0xb05d, 7714 "Setting back fcoe driver presence.\n"); 7715 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS) 7716 ql_dbg(ql_dbg_p3p, vha, 0xb074, 7717 "Error while setting DRV-Presence.\n"); 7718 } 7719 } else { 7720 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n", 7721 __func__); 7722 } 7723 7724 return(status); 7725 } 7726 7727 /* 7728 * qla2x00_restart_isp 7729 * restarts the ISP after a reset 7730 * 7731 * Input: 7732 * ha = adapter block pointer. 7733 * 7734 * Returns: 7735 * 0 = success 7736 */ 7737 static int 7738 qla2x00_restart_isp(scsi_qla_host_t *vha) 7739 { 7740 int status; 7741 struct qla_hw_data *ha = vha->hw; 7742 7743 /* If firmware needs to be loaded */ 7744 if (qla2x00_isp_firmware(vha)) { 7745 vha->flags.online = 0; 7746 status = ha->isp_ops->chip_diag(vha); 7747 if (status) 7748 return status; 7749 status = qla2x00_setup_chip(vha); 7750 if (status) 7751 return status; 7752 } 7753 7754 status = qla2x00_init_rings(vha); 7755 if (status) 7756 return status; 7757 7758 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7759 ha->flags.chip_reset_done = 1; 7760 7761 /* Initialize the queues in use */ 7762 qla25xx_init_queues(ha); 7763 7764 status = qla2x00_fw_ready(vha); 7765 if (status) { 7766 /* if no cable then assume it's good */ 7767 return vha->device_flags & DFLG_NO_CABLE ? 0 : status; 7768 } 7769 7770 /* Issue a marker after FW becomes ready. */ 7771 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 7772 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 7773 7774 return 0; 7775 } 7776 7777 static int 7778 qla25xx_init_queues(struct qla_hw_data *ha) 7779 { 7780 struct rsp_que *rsp = NULL; 7781 struct req_que *req = NULL; 7782 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7783 int ret = -1; 7784 int i; 7785 7786 for (i = 1; i < ha->max_rsp_queues; i++) { 7787 rsp = ha->rsp_q_map[i]; 7788 if (rsp && test_bit(i, ha->rsp_qid_map)) { 7789 rsp->options &= ~BIT_0; 7790 ret = qla25xx_init_rsp_que(base_vha, rsp); 7791 if (ret != QLA_SUCCESS) 7792 ql_dbg(ql_dbg_init, base_vha, 0x00ff, 7793 "%s Rsp que: %d init failed.\n", 7794 __func__, rsp->id); 7795 else 7796 ql_dbg(ql_dbg_init, base_vha, 0x0100, 7797 "%s Rsp que: %d inited.\n", 7798 __func__, rsp->id); 7799 } 7800 } 7801 for (i = 1; i < ha->max_req_queues; i++) { 7802 req = ha->req_q_map[i]; 7803 if (req && test_bit(i, ha->req_qid_map)) { 7804 /* Clear outstanding commands array. */ 7805 req->options &= ~BIT_0; 7806 ret = qla25xx_init_req_que(base_vha, req); 7807 if (ret != QLA_SUCCESS) 7808 ql_dbg(ql_dbg_init, base_vha, 0x0101, 7809 "%s Req que: %d init failed.\n", 7810 __func__, req->id); 7811 else 7812 ql_dbg(ql_dbg_init, base_vha, 0x0102, 7813 "%s Req que: %d inited.\n", 7814 __func__, req->id); 7815 } 7816 } 7817 return ret; 7818 } 7819 7820 /* 7821 * qla2x00_reset_adapter 7822 * Reset adapter. 7823 * 7824 * Input: 7825 * ha = adapter block pointer. 7826 */ 7827 int 7828 qla2x00_reset_adapter(scsi_qla_host_t *vha) 7829 { 7830 unsigned long flags = 0; 7831 struct qla_hw_data *ha = vha->hw; 7832 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7833 7834 vha->flags.online = 0; 7835 ha->isp_ops->disable_intrs(ha); 7836 7837 spin_lock_irqsave(&ha->hardware_lock, flags); 7838 wrt_reg_word(®->hccr, HCCR_RESET_RISC); 7839 rd_reg_word(®->hccr); /* PCI Posting. */ 7840 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC); 7841 rd_reg_word(®->hccr); /* PCI Posting. */ 7842 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7843 7844 return QLA_SUCCESS; 7845 } 7846 7847 int 7848 qla24xx_reset_adapter(scsi_qla_host_t *vha) 7849 { 7850 unsigned long flags = 0; 7851 struct qla_hw_data *ha = vha->hw; 7852 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 7853 7854 if (IS_P3P_TYPE(ha)) 7855 return QLA_SUCCESS; 7856 7857 vha->flags.online = 0; 7858 ha->isp_ops->disable_intrs(ha); 7859 7860 spin_lock_irqsave(&ha->hardware_lock, flags); 7861 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET); 7862 rd_reg_dword(®->hccr); 7863 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE); 7864 rd_reg_dword(®->hccr); 7865 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7866 7867 if (IS_NOPOLLING_TYPE(ha)) 7868 ha->isp_ops->enable_intrs(ha); 7869 7870 return QLA_SUCCESS; 7871 } 7872 7873 /* On sparc systems, obtain port and node WWN from firmware 7874 * properties. 7875 */ 7876 static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, 7877 struct nvram_24xx *nv) 7878 { 7879 #ifdef CONFIG_SPARC 7880 struct qla_hw_data *ha = vha->hw; 7881 struct pci_dev *pdev = ha->pdev; 7882 struct device_node *dp = pci_device_to_OF_node(pdev); 7883 const u8 *val; 7884 int len; 7885 7886 val = of_get_property(dp, "port-wwn", &len); 7887 if (val && len >= WWN_SIZE) 7888 memcpy(nv->port_name, val, WWN_SIZE); 7889 7890 val = of_get_property(dp, "node-wwn", &len); 7891 if (val && len >= WWN_SIZE) 7892 memcpy(nv->node_name, val, WWN_SIZE); 7893 #endif 7894 } 7895 7896 int 7897 qla24xx_nvram_config(scsi_qla_host_t *vha) 7898 { 7899 int rval; 7900 struct init_cb_24xx *icb; 7901 struct nvram_24xx *nv; 7902 __le32 *dptr; 7903 uint8_t *dptr1, *dptr2; 7904 uint32_t chksum; 7905 uint16_t cnt; 7906 struct qla_hw_data *ha = vha->hw; 7907 7908 rval = QLA_SUCCESS; 7909 icb = (struct init_cb_24xx *)ha->init_cb; 7910 nv = ha->nvram; 7911 7912 /* Determine NVRAM starting address. */ 7913 if (ha->port_no == 0) { 7914 ha->nvram_base = FA_NVRAM_FUNC0_ADDR; 7915 ha->vpd_base = FA_NVRAM_VPD0_ADDR; 7916 } else { 7917 ha->nvram_base = FA_NVRAM_FUNC1_ADDR; 7918 ha->vpd_base = FA_NVRAM_VPD1_ADDR; 7919 } 7920 7921 ha->nvram_size = sizeof(*nv); 7922 ha->vpd_size = FA_NVRAM_VPD_SIZE; 7923 7924 /* Get VPD data into cache */ 7925 ha->vpd = ha->nvram + VPD_OFFSET; 7926 ha->isp_ops->read_nvram(vha, ha->vpd, 7927 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4); 7928 7929 /* Get NVRAM data into cache and calculate checksum. */ 7930 dptr = (__force __le32 *)nv; 7931 ha->isp_ops->read_nvram(vha, dptr, ha->nvram_base, ha->nvram_size); 7932 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++) 7933 chksum += le32_to_cpu(*dptr); 7934 7935 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a, 7936 "Contents of NVRAM\n"); 7937 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d, 7938 nv, ha->nvram_size); 7939 7940 /* Bad NVRAM data, set defaults parameters. */ 7941 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 7942 le16_to_cpu(nv->nvram_version) < ICB_VERSION) { 7943 /* Reset NVRAM data. */ 7944 ql_log(ql_log_warn, vha, 0x006b, 7945 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n", 7946 chksum, nv->id, nv->nvram_version); 7947 ql_dump_buffer(ql_dbg_init, vha, 0x006b, nv, sizeof(*nv)); 7948 ql_log(ql_log_warn, vha, 0x006c, 7949 "Falling back to functioning (yet invalid -- WWPN) " 7950 "defaults.\n"); 7951 7952 /* 7953 * Set default initialization control block. 7954 */ 7955 memset(nv, 0, ha->nvram_size); 7956 nv->nvram_version = cpu_to_le16(ICB_VERSION); 7957 nv->version = cpu_to_le16(ICB_VERSION); 7958 nv->frame_payload_size = cpu_to_le16(2048); 7959 nv->execution_throttle = cpu_to_le16(0xFFFF); 7960 nv->exchange_count = cpu_to_le16(0); 7961 nv->hard_address = cpu_to_le16(124); 7962 nv->port_name[0] = 0x21; 7963 nv->port_name[1] = 0x00 + ha->port_no + 1; 7964 nv->port_name[2] = 0x00; 7965 nv->port_name[3] = 0xe0; 7966 nv->port_name[4] = 0x8b; 7967 nv->port_name[5] = 0x1c; 7968 nv->port_name[6] = 0x55; 7969 nv->port_name[7] = 0x86; 7970 nv->node_name[0] = 0x20; 7971 nv->node_name[1] = 0x00; 7972 nv->node_name[2] = 0x00; 7973 nv->node_name[3] = 0xe0; 7974 nv->node_name[4] = 0x8b; 7975 nv->node_name[5] = 0x1c; 7976 nv->node_name[6] = 0x55; 7977 nv->node_name[7] = 0x86; 7978 qla24xx_nvram_wwn_from_ofw(vha, nv); 7979 nv->login_retry_count = cpu_to_le16(8); 7980 nv->interrupt_delay_timer = cpu_to_le16(0); 7981 nv->login_timeout = cpu_to_le16(0); 7982 nv->firmware_options_1 = 7983 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 7984 nv->firmware_options_2 = cpu_to_le32(2 << 4); 7985 nv->firmware_options_2 |= cpu_to_le32(BIT_12); 7986 nv->firmware_options_3 = cpu_to_le32(2 << 13); 7987 nv->host_p = cpu_to_le32(BIT_11|BIT_10); 7988 nv->efi_parameters = cpu_to_le32(0); 7989 nv->reset_delay = 5; 7990 nv->max_luns_per_target = cpu_to_le16(128); 7991 nv->port_down_retry_count = cpu_to_le16(30); 7992 nv->link_down_timeout = cpu_to_le16(30); 7993 7994 rval = 1; 7995 } 7996 7997 if (qla_tgt_mode_enabled(vha)) { 7998 /* Don't enable full login after initial LIP */ 7999 nv->firmware_options_1 &= cpu_to_le32(~BIT_13); 8000 /* Don't enable LIP full login for initiator */ 8001 nv->host_p &= cpu_to_le32(~BIT_10); 8002 } 8003 8004 qlt_24xx_config_nvram_stage1(vha, nv); 8005 8006 /* Reset Initialization control block */ 8007 memset(icb, 0, ha->init_cb_size); 8008 8009 /* Copy 1st segment. */ 8010 dptr1 = (uint8_t *)icb; 8011 dptr2 = (uint8_t *)&nv->version; 8012 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 8013 while (cnt--) 8014 *dptr1++ = *dptr2++; 8015 8016 icb->login_retry_count = nv->login_retry_count; 8017 icb->link_down_on_nos = nv->link_down_on_nos; 8018 8019 /* Copy 2nd segment. */ 8020 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 8021 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 8022 cnt = (uint8_t *)&icb->reserved_3 - 8023 (uint8_t *)&icb->interrupt_delay_timer; 8024 while (cnt--) 8025 *dptr1++ = *dptr2++; 8026 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 8027 /* 8028 * Setup driver NVRAM options. 8029 */ 8030 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 8031 "QLA2462"); 8032 8033 qlt_24xx_config_nvram_stage2(vha, icb); 8034 8035 if (nv->host_p & cpu_to_le32(BIT_15)) { 8036 /* Use alternate WWN? */ 8037 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 8038 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 8039 } 8040 8041 /* Prepare nodename */ 8042 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) { 8043 /* 8044 * Firmware will apply the following mask if the nodename was 8045 * not provided. 8046 */ 8047 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 8048 icb->node_name[0] &= 0xF0; 8049 } 8050 8051 /* Set host adapter parameters. */ 8052 ha->flags.disable_risc_code_load = 0; 8053 ha->flags.enable_lip_reset = 0; 8054 ha->flags.enable_lip_full_login = 8055 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0; 8056 ha->flags.enable_target_reset = 8057 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0; 8058 ha->flags.enable_led_scheme = 0; 8059 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0; 8060 8061 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 8062 (BIT_6 | BIT_5 | BIT_4)) >> 4; 8063 8064 memcpy(ha->fw_seriallink_options24, nv->seriallink_options, 8065 sizeof(ha->fw_seriallink_options24)); 8066 8067 /* save HBA serial number */ 8068 ha->serial0 = icb->port_name[5]; 8069 ha->serial1 = icb->port_name[6]; 8070 ha->serial2 = icb->port_name[7]; 8071 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 8072 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 8073 8074 icb->execution_throttle = cpu_to_le16(0xFFFF); 8075 8076 ha->retry_count = le16_to_cpu(nv->login_retry_count); 8077 8078 /* Set minimum login_timeout to 4 seconds. */ 8079 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 8080 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 8081 if (le16_to_cpu(nv->login_timeout) < 4) 8082 nv->login_timeout = cpu_to_le16(4); 8083 ha->login_timeout = le16_to_cpu(nv->login_timeout); 8084 8085 /* Set minimum RATOV to 100 tenths of a second. */ 8086 ha->r_a_tov = 100; 8087 8088 ha->loop_reset_delay = nv->reset_delay; 8089 8090 /* Link Down Timeout = 0: 8091 * 8092 * When Port Down timer expires we will start returning 8093 * I/O's to OS with "DID_NO_CONNECT". 8094 * 8095 * Link Down Timeout != 0: 8096 * 8097 * The driver waits for the link to come up after link down 8098 * before returning I/Os to OS with "DID_NO_CONNECT". 8099 */ 8100 if (le16_to_cpu(nv->link_down_timeout) == 0) { 8101 ha->loop_down_abort_time = 8102 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 8103 } else { 8104 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 8105 ha->loop_down_abort_time = 8106 (LOOP_DOWN_TIME - ha->link_down_timeout); 8107 } 8108 8109 /* Need enough time to try and get the port back. */ 8110 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 8111 if (qlport_down_retry) 8112 ha->port_down_retry_count = qlport_down_retry; 8113 8114 /* Set login_retry_count */ 8115 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 8116 if (ha->port_down_retry_count == 8117 le16_to_cpu(nv->port_down_retry_count) && 8118 ha->port_down_retry_count > 3) 8119 ha->login_retry_count = ha->port_down_retry_count; 8120 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 8121 ha->login_retry_count = ha->port_down_retry_count; 8122 if (ql2xloginretrycount) 8123 ha->login_retry_count = ql2xloginretrycount; 8124 8125 /* N2N: driver will initiate Login instead of FW */ 8126 icb->firmware_options_3 |= cpu_to_le32(BIT_8); 8127 8128 /* Enable ZIO. */ 8129 if (!vha->flags.init_done) { 8130 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 8131 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 8132 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 8133 le16_to_cpu(icb->interrupt_delay_timer) : 2; 8134 } 8135 icb->firmware_options_2 &= cpu_to_le32( 8136 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 8137 if (ha->zio_mode != QLA_ZIO_DISABLED) { 8138 ha->zio_mode = QLA_ZIO_MODE_6; 8139 8140 ql_log(ql_log_info, vha, 0x006f, 8141 "ZIO mode %d enabled; timer delay (%d us).\n", 8142 ha->zio_mode, ha->zio_timer * 100); 8143 8144 icb->firmware_options_2 |= cpu_to_le32( 8145 (uint32_t)ha->zio_mode); 8146 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 8147 } 8148 8149 if (rval) { 8150 ql_log(ql_log_warn, vha, 0x0070, 8151 "NVRAM configuration failed.\n"); 8152 } 8153 return (rval); 8154 } 8155 8156 static void 8157 qla27xx_print_image(struct scsi_qla_host *vha, char *name, 8158 struct qla27xx_image_status *image_status) 8159 { 8160 ql_dbg(ql_dbg_init, vha, 0x018b, 8161 "%s %s: mask=%#02x gen=%#04x ver=%u.%u map=%#01x sum=%#08x sig=%#08x\n", 8162 name, "status", 8163 image_status->image_status_mask, 8164 le16_to_cpu(image_status->generation), 8165 image_status->ver_major, 8166 image_status->ver_minor, 8167 image_status->bitmap, 8168 le32_to_cpu(image_status->checksum), 8169 le32_to_cpu(image_status->signature)); 8170 } 8171 8172 static bool 8173 qla28xx_check_aux_image_status_signature( 8174 struct qla27xx_image_status *image_status) 8175 { 8176 ulong signature = le32_to_cpu(image_status->signature); 8177 8178 return signature != QLA28XX_AUX_IMG_STATUS_SIGN; 8179 } 8180 8181 static bool 8182 qla27xx_check_image_status_signature(struct qla27xx_image_status *image_status) 8183 { 8184 ulong signature = le32_to_cpu(image_status->signature); 8185 8186 return 8187 signature != QLA27XX_IMG_STATUS_SIGN && 8188 signature != QLA28XX_IMG_STATUS_SIGN; 8189 } 8190 8191 static ulong 8192 qla27xx_image_status_checksum(struct qla27xx_image_status *image_status) 8193 { 8194 __le32 *p = (__force __le32 *)image_status; 8195 uint n = sizeof(*image_status) / sizeof(*p); 8196 uint32_t sum = 0; 8197 8198 for ( ; n--; p++) 8199 sum += le32_to_cpup(p); 8200 8201 return sum; 8202 } 8203 8204 static inline uint 8205 qla28xx_component_bitmask(struct qla27xx_image_status *aux, uint bitmask) 8206 { 8207 return aux->bitmap & bitmask ? 8208 QLA27XX_SECONDARY_IMAGE : QLA27XX_PRIMARY_IMAGE; 8209 } 8210 8211 static void 8212 qla28xx_component_status( 8213 struct active_regions *active_regions, struct qla27xx_image_status *aux) 8214 { 8215 active_regions->aux.board_config = 8216 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_BOARD_CONFIG); 8217 8218 active_regions->aux.vpd_nvram = 8219 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_VPD_NVRAM); 8220 8221 active_regions->aux.npiv_config_0_1 = 8222 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_0_1); 8223 8224 active_regions->aux.npiv_config_2_3 = 8225 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_2_3); 8226 8227 active_regions->aux.nvme_params = 8228 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NVME_PARAMS); 8229 } 8230 8231 static int 8232 qla27xx_compare_image_generation( 8233 struct qla27xx_image_status *pri_image_status, 8234 struct qla27xx_image_status *sec_image_status) 8235 { 8236 /* calculate generation delta as uint16 (this accounts for wrap) */ 8237 int16_t delta = 8238 le16_to_cpu(pri_image_status->generation) - 8239 le16_to_cpu(sec_image_status->generation); 8240 8241 ql_dbg(ql_dbg_init, NULL, 0x0180, "generation delta = %d\n", delta); 8242 8243 return delta; 8244 } 8245 8246 void 8247 qla28xx_get_aux_images( 8248 struct scsi_qla_host *vha, struct active_regions *active_regions) 8249 { 8250 struct qla_hw_data *ha = vha->hw; 8251 struct qla27xx_image_status pri_aux_image_status, sec_aux_image_status; 8252 bool valid_pri_image = false, valid_sec_image = false; 8253 bool active_pri_image = false, active_sec_image = false; 8254 int rc; 8255 8256 if (!ha->flt_region_aux_img_status_pri) { 8257 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary aux image not addressed\n"); 8258 goto check_sec_image; 8259 } 8260 8261 rc = qla24xx_read_flash_data(vha, (uint32_t *)&pri_aux_image_status, 8262 ha->flt_region_aux_img_status_pri, 8263 sizeof(pri_aux_image_status) >> 2); 8264 if (rc) { 8265 ql_log(ql_log_info, vha, 0x01a1, 8266 "Unable to read Primary aux image(%x).\n", rc); 8267 goto check_sec_image; 8268 } 8269 qla27xx_print_image(vha, "Primary aux image", &pri_aux_image_status); 8270 8271 if (qla28xx_check_aux_image_status_signature(&pri_aux_image_status)) { 8272 ql_dbg(ql_dbg_init, vha, 0x018b, 8273 "Primary aux image signature (%#x) not valid\n", 8274 le32_to_cpu(pri_aux_image_status.signature)); 8275 goto check_sec_image; 8276 } 8277 8278 if (qla27xx_image_status_checksum(&pri_aux_image_status)) { 8279 ql_dbg(ql_dbg_init, vha, 0x018c, 8280 "Primary aux image checksum failed\n"); 8281 goto check_sec_image; 8282 } 8283 8284 valid_pri_image = true; 8285 8286 if (pri_aux_image_status.image_status_mask & 1) { 8287 ql_dbg(ql_dbg_init, vha, 0x018d, 8288 "Primary aux image is active\n"); 8289 active_pri_image = true; 8290 } 8291 8292 check_sec_image: 8293 if (!ha->flt_region_aux_img_status_sec) { 8294 ql_dbg(ql_dbg_init, vha, 0x018a, 8295 "Secondary aux image not addressed\n"); 8296 goto check_valid_image; 8297 } 8298 8299 rc = qla24xx_read_flash_data(vha, (uint32_t *)&sec_aux_image_status, 8300 ha->flt_region_aux_img_status_sec, 8301 sizeof(sec_aux_image_status) >> 2); 8302 if (rc) { 8303 ql_log(ql_log_info, vha, 0x01a2, 8304 "Unable to read Secondary aux image(%x).\n", rc); 8305 goto check_valid_image; 8306 } 8307 8308 qla27xx_print_image(vha, "Secondary aux image", &sec_aux_image_status); 8309 8310 if (qla28xx_check_aux_image_status_signature(&sec_aux_image_status)) { 8311 ql_dbg(ql_dbg_init, vha, 0x018b, 8312 "Secondary aux image signature (%#x) not valid\n", 8313 le32_to_cpu(sec_aux_image_status.signature)); 8314 goto check_valid_image; 8315 } 8316 8317 if (qla27xx_image_status_checksum(&sec_aux_image_status)) { 8318 ql_dbg(ql_dbg_init, vha, 0x018c, 8319 "Secondary aux image checksum failed\n"); 8320 goto check_valid_image; 8321 } 8322 8323 valid_sec_image = true; 8324 8325 if (sec_aux_image_status.image_status_mask & 1) { 8326 ql_dbg(ql_dbg_init, vha, 0x018d, 8327 "Secondary aux image is active\n"); 8328 active_sec_image = true; 8329 } 8330 8331 check_valid_image: 8332 if (valid_pri_image && active_pri_image && 8333 valid_sec_image && active_sec_image) { 8334 if (qla27xx_compare_image_generation(&pri_aux_image_status, 8335 &sec_aux_image_status) >= 0) { 8336 qla28xx_component_status(active_regions, 8337 &pri_aux_image_status); 8338 } else { 8339 qla28xx_component_status(active_regions, 8340 &sec_aux_image_status); 8341 } 8342 } else if (valid_pri_image && active_pri_image) { 8343 qla28xx_component_status(active_regions, &pri_aux_image_status); 8344 } else if (valid_sec_image && active_sec_image) { 8345 qla28xx_component_status(active_regions, &sec_aux_image_status); 8346 } 8347 8348 ql_dbg(ql_dbg_init, vha, 0x018f, 8349 "aux images active: BCFG=%u VPD/NVR=%u NPIV0/1=%u NPIV2/3=%u, NVME=%u\n", 8350 active_regions->aux.board_config, 8351 active_regions->aux.vpd_nvram, 8352 active_regions->aux.npiv_config_0_1, 8353 active_regions->aux.npiv_config_2_3, 8354 active_regions->aux.nvme_params); 8355 } 8356 8357 void 8358 qla27xx_get_active_image(struct scsi_qla_host *vha, 8359 struct active_regions *active_regions) 8360 { 8361 struct qla_hw_data *ha = vha->hw; 8362 struct qla27xx_image_status pri_image_status, sec_image_status; 8363 bool valid_pri_image = false, valid_sec_image = false; 8364 bool active_pri_image = false, active_sec_image = false; 8365 int rc; 8366 8367 if (!ha->flt_region_img_status_pri) { 8368 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary image not addressed\n"); 8369 goto check_sec_image; 8370 } 8371 8372 if (qla24xx_read_flash_data(vha, (uint32_t *)&pri_image_status, 8373 ha->flt_region_img_status_pri, sizeof(pri_image_status) >> 2) != 8374 QLA_SUCCESS) { 8375 WARN_ON_ONCE(true); 8376 goto check_sec_image; 8377 } 8378 qla27xx_print_image(vha, "Primary image", &pri_image_status); 8379 8380 if (qla27xx_check_image_status_signature(&pri_image_status)) { 8381 ql_dbg(ql_dbg_init, vha, 0x018b, 8382 "Primary image signature (%#x) not valid\n", 8383 le32_to_cpu(pri_image_status.signature)); 8384 goto check_sec_image; 8385 } 8386 8387 if (qla27xx_image_status_checksum(&pri_image_status)) { 8388 ql_dbg(ql_dbg_init, vha, 0x018c, 8389 "Primary image checksum failed\n"); 8390 goto check_sec_image; 8391 } 8392 8393 valid_pri_image = true; 8394 8395 if (pri_image_status.image_status_mask & 1) { 8396 ql_dbg(ql_dbg_init, vha, 0x018d, 8397 "Primary image is active\n"); 8398 active_pri_image = true; 8399 } 8400 8401 check_sec_image: 8402 if (!ha->flt_region_img_status_sec) { 8403 ql_dbg(ql_dbg_init, vha, 0x018a, "Secondary image not addressed\n"); 8404 goto check_valid_image; 8405 } 8406 8407 rc = qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status), 8408 ha->flt_region_img_status_sec, sizeof(sec_image_status) >> 2); 8409 if (rc) { 8410 ql_log(ql_log_info, vha, 0x01a3, 8411 "Unable to read Secondary image status(%x).\n", rc); 8412 goto check_valid_image; 8413 } 8414 8415 qla27xx_print_image(vha, "Secondary image", &sec_image_status); 8416 8417 if (qla27xx_check_image_status_signature(&sec_image_status)) { 8418 ql_dbg(ql_dbg_init, vha, 0x018b, 8419 "Secondary image signature (%#x) not valid\n", 8420 le32_to_cpu(sec_image_status.signature)); 8421 goto check_valid_image; 8422 } 8423 8424 if (qla27xx_image_status_checksum(&sec_image_status)) { 8425 ql_dbg(ql_dbg_init, vha, 0x018c, 8426 "Secondary image checksum failed\n"); 8427 goto check_valid_image; 8428 } 8429 8430 valid_sec_image = true; 8431 8432 if (sec_image_status.image_status_mask & 1) { 8433 ql_dbg(ql_dbg_init, vha, 0x018d, 8434 "Secondary image is active\n"); 8435 active_sec_image = true; 8436 } 8437 8438 check_valid_image: 8439 if (valid_pri_image && active_pri_image) 8440 active_regions->global = QLA27XX_PRIMARY_IMAGE; 8441 8442 if (valid_sec_image && active_sec_image) { 8443 if (!active_regions->global || 8444 qla27xx_compare_image_generation( 8445 &pri_image_status, &sec_image_status) < 0) { 8446 active_regions->global = QLA27XX_SECONDARY_IMAGE; 8447 } 8448 } 8449 8450 ql_dbg(ql_dbg_init, vha, 0x018f, "active image %s (%u)\n", 8451 active_regions->global == QLA27XX_DEFAULT_IMAGE ? 8452 "default (boot/fw)" : 8453 active_regions->global == QLA27XX_PRIMARY_IMAGE ? 8454 "primary" : 8455 active_regions->global == QLA27XX_SECONDARY_IMAGE ? 8456 "secondary" : "invalid", 8457 active_regions->global); 8458 } 8459 8460 bool qla24xx_risc_firmware_invalid(uint32_t *dword) 8461 { 8462 return 8463 !(dword[4] | dword[5] | dword[6] | dword[7]) || 8464 !(~dword[4] | ~dword[5] | ~dword[6] | ~dword[7]); 8465 } 8466 8467 static int 8468 qla28xx_get_srisc_addr(scsi_qla_host_t *vha, uint32_t *srisc_addr, 8469 uint32_t faddr) 8470 { 8471 struct qla_hw_data *ha = vha->hw; 8472 struct req_que *req = ha->req_q_map[0]; 8473 uint32_t *dcode; 8474 int rval; 8475 8476 *srisc_addr = 0; 8477 dcode = (uint32_t *)req->ring; 8478 8479 rval = qla24xx_read_flash_data(vha, dcode, faddr, 10); 8480 if (rval) { 8481 ql_log(ql_log_fatal, vha, 0x01aa, 8482 "-> Failed to read flash addr + size .\n"); 8483 return QLA_FUNCTION_FAILED; 8484 } 8485 8486 *srisc_addr = be32_to_cpu((__force __be32)dcode[2]); 8487 return QLA_SUCCESS; 8488 } 8489 8490 static int 8491 qla28xx_load_fw_template(scsi_qla_host_t *vha, uint32_t faddr) 8492 { 8493 struct qla_hw_data *ha = vha->hw; 8494 struct fwdt *fwdt = ha->fwdt; 8495 struct req_que *req = ha->req_q_map[0]; 8496 uint32_t risc_size, risc_attr = 0; 8497 uint templates, segments, fragment; 8498 uint32_t *dcode; 8499 ulong dlen; 8500 int rval; 8501 uint j; 8502 8503 dcode = (uint32_t *)req->ring; 8504 segments = FA_RISC_CODE_SEGMENTS; 8505 8506 for (j = 0; j < segments; j++) { 8507 rval = qla24xx_read_flash_data(vha, dcode, faddr, 10); 8508 if (rval) { 8509 ql_log(ql_log_fatal, vha, 0x01a1, 8510 "-> Failed to read flash addr + size .\n"); 8511 return QLA_FUNCTION_FAILED; 8512 } 8513 8514 risc_size = be32_to_cpu((__force __be32)dcode[3]); 8515 8516 if (risc_attr == 0) 8517 risc_attr = be32_to_cpu((__force __be32)dcode[9]); 8518 8519 dlen = ha->fw_transfer_size >> 2; 8520 for (fragment = 0; fragment < risc_size; fragment++) { 8521 if (dlen > risc_size) 8522 dlen = risc_size; 8523 8524 faddr += dlen; 8525 risc_size -= dlen; 8526 } 8527 } 8528 8529 templates = (risc_attr & BIT_9) ? 2 : 1; 8530 8531 ql_dbg(ql_dbg_init, vha, 0x01a1, "-> templates = %u\n", templates); 8532 8533 for (j = 0; j < templates; j++, fwdt++) { 8534 vfree(fwdt->template); 8535 fwdt->template = NULL; 8536 fwdt->length = 0; 8537 8538 dcode = (uint32_t *)req->ring; 8539 8540 rval = qla24xx_read_flash_data(vha, dcode, faddr, 7); 8541 if (rval) { 8542 ql_log(ql_log_fatal, vha, 0x01a2, 8543 "-> Unable to read template size.\n"); 8544 goto failed; 8545 } 8546 8547 risc_size = be32_to_cpu((__force __be32)dcode[2]); 8548 ql_dbg(ql_dbg_init, vha, 0x01a3, 8549 "-> fwdt%u template array at %#x (%#x dwords)\n", 8550 j, faddr, risc_size); 8551 if (!risc_size || !~risc_size) { 8552 ql_dbg(ql_dbg_init, vha, 0x01a4, 8553 "-> fwdt%u failed to read array\n", j); 8554 goto failed; 8555 } 8556 8557 /* skip header and ignore checksum */ 8558 faddr += 7; 8559 risc_size -= 8; 8560 8561 ql_dbg(ql_dbg_init, vha, 0x01a5, 8562 "-> fwdt%u template allocate template %#x words...\n", 8563 j, risc_size); 8564 fwdt->template = vmalloc(risc_size * sizeof(*dcode)); 8565 if (!fwdt->template) { 8566 ql_log(ql_log_warn, vha, 0x01a6, 8567 "-> fwdt%u failed allocate template.\n", j); 8568 goto failed; 8569 } 8570 8571 dcode = fwdt->template; 8572 rval = qla24xx_read_flash_data(vha, dcode, faddr, risc_size); 8573 8574 if (rval || !qla27xx_fwdt_template_valid(dcode)) { 8575 ql_log(ql_log_warn, vha, 0x01a7, 8576 "-> fwdt%u failed template validate (rval %x)\n", 8577 j, rval); 8578 goto failed; 8579 } 8580 8581 dlen = qla27xx_fwdt_template_size(dcode); 8582 ql_dbg(ql_dbg_init, vha, 0x01a7, 8583 "-> fwdt%u template size %#lx bytes (%#lx words)\n", 8584 j, dlen, dlen / sizeof(*dcode)); 8585 if (dlen > risc_size * sizeof(*dcode)) { 8586 ql_log(ql_log_warn, vha, 0x01a8, 8587 "-> fwdt%u template exceeds array (%-lu bytes)\n", 8588 j, dlen - risc_size * sizeof(*dcode)); 8589 goto failed; 8590 } 8591 8592 fwdt->length = dlen; 8593 ql_dbg(ql_dbg_init, vha, 0x01a9, 8594 "-> fwdt%u loaded template ok\n", j); 8595 8596 faddr += risc_size + 1; 8597 } 8598 8599 return QLA_SUCCESS; 8600 8601 failed: 8602 vfree(fwdt->template); 8603 fwdt->template = NULL; 8604 fwdt->length = 0; 8605 8606 return QLA_SUCCESS; 8607 } 8608 8609 static int 8610 qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr, 8611 uint32_t faddr) 8612 { 8613 int rval; 8614 uint templates, segments, fragment; 8615 ulong i; 8616 uint j; 8617 ulong dlen; 8618 uint32_t *dcode; 8619 uint32_t risc_addr, risc_size, risc_attr = 0; 8620 struct qla_hw_data *ha = vha->hw; 8621 struct req_que *req = ha->req_q_map[0]; 8622 struct fwdt *fwdt = ha->fwdt; 8623 8624 ql_dbg(ql_dbg_init, vha, 0x008b, 8625 "FW: Loading firmware from flash (%x).\n", faddr); 8626 8627 dcode = (uint32_t *)req->ring; 8628 rval = qla24xx_read_flash_data(vha, dcode, faddr, 8); 8629 if (rval || qla24xx_risc_firmware_invalid(dcode)) { 8630 ql_log(ql_log_fatal, vha, 0x008c, 8631 "Unable to verify the integrity of flash firmware image (rval %x).\n", rval); 8632 ql_log(ql_log_fatal, vha, 0x008d, 8633 "Firmware data: %08x %08x %08x %08x.\n", 8634 dcode[0], dcode[1], dcode[2], dcode[3]); 8635 8636 return QLA_FUNCTION_FAILED; 8637 } 8638 8639 dcode = (uint32_t *)req->ring; 8640 *srisc_addr = 0; 8641 segments = FA_RISC_CODE_SEGMENTS; 8642 for (j = 0; j < segments; j++) { 8643 ql_dbg(ql_dbg_init, vha, 0x008d, 8644 "-> Loading segment %u...\n", j); 8645 rval = qla24xx_read_flash_data(vha, dcode, faddr, 10); 8646 if (rval) { 8647 ql_log(ql_log_fatal, vha, 0x016a, 8648 "-> Unable to read segment addr + size .\n"); 8649 return QLA_FUNCTION_FAILED; 8650 } 8651 risc_addr = be32_to_cpu((__force __be32)dcode[2]); 8652 risc_size = be32_to_cpu((__force __be32)dcode[3]); 8653 if (!*srisc_addr) { 8654 *srisc_addr = risc_addr; 8655 risc_attr = be32_to_cpu((__force __be32)dcode[9]); 8656 } 8657 8658 dlen = ha->fw_transfer_size >> 2; 8659 for (fragment = 0; risc_size; fragment++) { 8660 if (dlen > risc_size) 8661 dlen = risc_size; 8662 8663 ql_dbg(ql_dbg_init, vha, 0x008e, 8664 "-> Loading fragment %u: %#x <- %#x (%#lx dwords)...\n", 8665 fragment, risc_addr, faddr, dlen); 8666 rval = qla24xx_read_flash_data(vha, dcode, faddr, dlen); 8667 if (rval) { 8668 ql_log(ql_log_fatal, vha, 0x016b, 8669 "-> Unable to read fragment(faddr %#x dlen %#lx).\n", 8670 faddr, dlen); 8671 return QLA_FUNCTION_FAILED; 8672 } 8673 for (i = 0; i < dlen; i++) 8674 dcode[i] = swab32(dcode[i]); 8675 8676 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen); 8677 if (rval) { 8678 ql_log(ql_log_fatal, vha, 0x008f, 8679 "-> Failed load firmware fragment %u.\n", 8680 fragment); 8681 return QLA_FUNCTION_FAILED; 8682 } 8683 8684 faddr += dlen; 8685 risc_addr += dlen; 8686 risc_size -= dlen; 8687 } 8688 } 8689 8690 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 8691 return QLA_SUCCESS; 8692 8693 templates = (risc_attr & BIT_9) ? 2 : 1; 8694 ql_dbg(ql_dbg_init, vha, 0x0160, "-> templates = %u\n", templates); 8695 for (j = 0; j < templates; j++, fwdt++) { 8696 vfree(fwdt->template); 8697 fwdt->template = NULL; 8698 fwdt->length = 0; 8699 8700 dcode = (uint32_t *)req->ring; 8701 8702 rval = qla24xx_read_flash_data(vha, dcode, faddr, 7); 8703 if (rval) { 8704 ql_log(ql_log_fatal, vha, 0x016c, 8705 "-> Unable to read template size.\n"); 8706 goto failed; 8707 } 8708 8709 risc_size = be32_to_cpu((__force __be32)dcode[2]); 8710 ql_dbg(ql_dbg_init, vha, 0x0161, 8711 "-> fwdt%u template array at %#x (%#x dwords)\n", 8712 j, faddr, risc_size); 8713 if (!risc_size || !~risc_size) { 8714 ql_dbg(ql_dbg_init, vha, 0x0162, 8715 "-> fwdt%u failed to read array\n", j); 8716 goto failed; 8717 } 8718 8719 /* skip header and ignore checksum */ 8720 faddr += 7; 8721 risc_size -= 8; 8722 8723 ql_dbg(ql_dbg_init, vha, 0x0163, 8724 "-> fwdt%u template allocate template %#x words...\n", 8725 j, risc_size); 8726 fwdt->template = vmalloc_array(risc_size, sizeof(*dcode)); 8727 if (!fwdt->template) { 8728 ql_log(ql_log_warn, vha, 0x0164, 8729 "-> fwdt%u failed allocate template.\n", j); 8730 goto failed; 8731 } 8732 8733 dcode = fwdt->template; 8734 rval = qla24xx_read_flash_data(vha, dcode, faddr, risc_size); 8735 8736 if (rval || !qla27xx_fwdt_template_valid(dcode)) { 8737 ql_log(ql_log_warn, vha, 0x0165, 8738 "-> fwdt%u failed template validate (rval %x)\n", 8739 j, rval); 8740 goto failed; 8741 } 8742 8743 dlen = qla27xx_fwdt_template_size(dcode); 8744 ql_dbg(ql_dbg_init, vha, 0x0166, 8745 "-> fwdt%u template size %#lx bytes (%#lx words)\n", 8746 j, dlen, dlen / sizeof(*dcode)); 8747 if (dlen > risc_size * sizeof(*dcode)) { 8748 ql_log(ql_log_warn, vha, 0x0167, 8749 "-> fwdt%u template exceeds array (%-lu bytes)\n", 8750 j, dlen - risc_size * sizeof(*dcode)); 8751 goto failed; 8752 } 8753 8754 fwdt->length = dlen; 8755 ql_dbg(ql_dbg_init, vha, 0x0168, 8756 "-> fwdt%u loaded template ok\n", j); 8757 8758 faddr += risc_size + 1; 8759 } 8760 8761 return QLA_SUCCESS; 8762 8763 failed: 8764 vfree(fwdt->template); 8765 fwdt->template = NULL; 8766 fwdt->length = 0; 8767 8768 return QLA_SUCCESS; 8769 } 8770 8771 int 8772 qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8773 { 8774 int rval; 8775 int i, fragment; 8776 uint16_t *wcode; 8777 __be16 *fwcode; 8778 uint32_t risc_addr, risc_size, fwclen, wlen, *seg; 8779 struct fw_blob *blob; 8780 struct qla_hw_data *ha = vha->hw; 8781 struct req_que *req = ha->req_q_map[0]; 8782 8783 /* Load firmware blob. */ 8784 blob = qla2x00_request_firmware(vha); 8785 if (!blob) { 8786 ql_log(ql_log_info, vha, 0x0083, 8787 "Firmware image unavailable.\n"); 8788 return QLA_FUNCTION_FAILED; 8789 } 8790 8791 rval = QLA_SUCCESS; 8792 8793 wcode = (uint16_t *)req->ring; 8794 *srisc_addr = 0; 8795 fwcode = (__force __be16 *)blob->fw->data; 8796 fwclen = 0; 8797 8798 /* Validate firmware image by checking version. */ 8799 if (blob->fw->size < 8 * sizeof(uint16_t)) { 8800 ql_log(ql_log_fatal, vha, 0x0085, 8801 "Unable to verify integrity of firmware image (%zd).\n", 8802 blob->fw->size); 8803 goto fail_fw_integrity; 8804 } 8805 for (i = 0; i < 4; i++) 8806 wcode[i] = be16_to_cpu(fwcode[i + 4]); 8807 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff && 8808 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 && 8809 wcode[2] == 0 && wcode[3] == 0)) { 8810 ql_log(ql_log_fatal, vha, 0x0086, 8811 "Unable to verify integrity of firmware image.\n"); 8812 ql_log(ql_log_fatal, vha, 0x0087, 8813 "Firmware data: %04x %04x %04x %04x.\n", 8814 wcode[0], wcode[1], wcode[2], wcode[3]); 8815 goto fail_fw_integrity; 8816 } 8817 8818 seg = blob->segs; 8819 while (*seg && rval == QLA_SUCCESS) { 8820 risc_addr = *seg; 8821 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr; 8822 risc_size = be16_to_cpu(fwcode[3]); 8823 8824 /* Validate firmware image size. */ 8825 fwclen += risc_size * sizeof(uint16_t); 8826 if (blob->fw->size < fwclen) { 8827 ql_log(ql_log_fatal, vha, 0x0088, 8828 "Unable to verify integrity of firmware image " 8829 "(%zd).\n", blob->fw->size); 8830 goto fail_fw_integrity; 8831 } 8832 8833 fragment = 0; 8834 while (risc_size > 0 && rval == QLA_SUCCESS) { 8835 wlen = (uint16_t)(ha->fw_transfer_size >> 1); 8836 if (wlen > risc_size) 8837 wlen = risc_size; 8838 ql_dbg(ql_dbg_init, vha, 0x0089, 8839 "Loading risc segment@ risc addr %x number of " 8840 "words 0x%x.\n", risc_addr, wlen); 8841 8842 for (i = 0; i < wlen; i++) 8843 wcode[i] = swab16((__force u32)fwcode[i]); 8844 8845 rval = qla2x00_load_ram(vha, req->dma, risc_addr, 8846 wlen); 8847 if (rval) { 8848 ql_log(ql_log_fatal, vha, 0x008a, 8849 "Failed to load segment %d of firmware.\n", 8850 fragment); 8851 break; 8852 } 8853 8854 fwcode += wlen; 8855 risc_addr += wlen; 8856 risc_size -= wlen; 8857 fragment++; 8858 } 8859 8860 /* Next segment. */ 8861 seg++; 8862 } 8863 return rval; 8864 8865 fail_fw_integrity: 8866 return QLA_FUNCTION_FAILED; 8867 } 8868 8869 static int 8870 qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr) 8871 { 8872 int rval; 8873 uint templates, segments, fragment; 8874 uint32_t *dcode; 8875 ulong dlen; 8876 uint32_t risc_addr, risc_size, risc_attr = 0; 8877 ulong i; 8878 uint j; 8879 struct fw_blob *blob; 8880 __be32 *fwcode; 8881 struct qla_hw_data *ha = vha->hw; 8882 struct req_que *req = ha->req_q_map[0]; 8883 struct fwdt *fwdt = ha->fwdt; 8884 8885 ql_dbg(ql_dbg_init, vha, 0x0090, 8886 "-> FW: Loading via request-firmware.\n"); 8887 8888 blob = qla2x00_request_firmware(vha); 8889 if (!blob) { 8890 ql_log(ql_log_warn, vha, 0x0092, 8891 "-> Firmware file not found.\n"); 8892 8893 return QLA_FUNCTION_FAILED; 8894 } 8895 8896 fwcode = (__force __be32 *)blob->fw->data; 8897 dcode = (__force uint32_t *)fwcode; 8898 if (qla24xx_risc_firmware_invalid(dcode)) { 8899 ql_log(ql_log_fatal, vha, 0x0093, 8900 "Unable to verify integrity of firmware image (%zd).\n", 8901 blob->fw->size); 8902 ql_log(ql_log_fatal, vha, 0x0095, 8903 "Firmware data: %08x %08x %08x %08x.\n", 8904 dcode[0], dcode[1], dcode[2], dcode[3]); 8905 return QLA_FUNCTION_FAILED; 8906 } 8907 8908 dcode = (uint32_t *)req->ring; 8909 *srisc_addr = 0; 8910 segments = FA_RISC_CODE_SEGMENTS; 8911 for (j = 0; j < segments; j++) { 8912 ql_dbg(ql_dbg_init, vha, 0x0096, 8913 "-> Loading segment %u...\n", j); 8914 risc_addr = be32_to_cpu(fwcode[2]); 8915 risc_size = be32_to_cpu(fwcode[3]); 8916 8917 if (!*srisc_addr) { 8918 *srisc_addr = risc_addr; 8919 risc_attr = be32_to_cpu(fwcode[9]); 8920 } 8921 8922 dlen = ha->fw_transfer_size >> 2; 8923 for (fragment = 0; risc_size; fragment++) { 8924 if (dlen > risc_size) 8925 dlen = risc_size; 8926 8927 ql_dbg(ql_dbg_init, vha, 0x0097, 8928 "-> Loading fragment %u: %#x <- %#x (%#lx words)...\n", 8929 fragment, risc_addr, 8930 (uint32_t)(fwcode - (typeof(fwcode))blob->fw->data), 8931 dlen); 8932 8933 for (i = 0; i < dlen; i++) 8934 dcode[i] = swab32((__force u32)fwcode[i]); 8935 8936 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen); 8937 if (rval) { 8938 ql_log(ql_log_fatal, vha, 0x0098, 8939 "-> Failed load firmware fragment %u.\n", 8940 fragment); 8941 return QLA_FUNCTION_FAILED; 8942 } 8943 8944 fwcode += dlen; 8945 risc_addr += dlen; 8946 risc_size -= dlen; 8947 } 8948 } 8949 8950 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 8951 return QLA_SUCCESS; 8952 8953 templates = (risc_attr & BIT_9) ? 2 : 1; 8954 ql_dbg(ql_dbg_init, vha, 0x0170, "-> templates = %u\n", templates); 8955 for (j = 0; j < templates; j++, fwdt++) { 8956 vfree(fwdt->template); 8957 fwdt->template = NULL; 8958 fwdt->length = 0; 8959 8960 risc_size = be32_to_cpu(fwcode[2]); 8961 ql_dbg(ql_dbg_init, vha, 0x0171, 8962 "-> fwdt%u template array at %#x (%#x dwords)\n", 8963 j, (uint32_t)((void *)fwcode - (void *)blob->fw->data), 8964 risc_size); 8965 if (!risc_size || !~risc_size) { 8966 ql_dbg(ql_dbg_init, vha, 0x0172, 8967 "-> fwdt%u failed to read array\n", j); 8968 goto failed; 8969 } 8970 8971 /* skip header and ignore checksum */ 8972 fwcode += 7; 8973 risc_size -= 8; 8974 8975 ql_dbg(ql_dbg_init, vha, 0x0173, 8976 "-> fwdt%u template allocate template %#x words...\n", 8977 j, risc_size); 8978 fwdt->template = vmalloc_array(risc_size, sizeof(*dcode)); 8979 if (!fwdt->template) { 8980 ql_log(ql_log_warn, vha, 0x0174, 8981 "-> fwdt%u failed allocate template.\n", j); 8982 goto failed; 8983 } 8984 8985 dcode = fwdt->template; 8986 for (i = 0; i < risc_size; i++) 8987 dcode[i] = (__force u32)fwcode[i]; 8988 8989 if (!qla27xx_fwdt_template_valid(dcode)) { 8990 ql_log(ql_log_warn, vha, 0x0175, 8991 "-> fwdt%u failed template validate\n", j); 8992 goto failed; 8993 } 8994 8995 dlen = qla27xx_fwdt_template_size(dcode); 8996 ql_dbg(ql_dbg_init, vha, 0x0176, 8997 "-> fwdt%u template size %#lx bytes (%#lx words)\n", 8998 j, dlen, dlen / sizeof(*dcode)); 8999 if (dlen > risc_size * sizeof(*dcode)) { 9000 ql_log(ql_log_warn, vha, 0x0177, 9001 "-> fwdt%u template exceeds array (%-lu bytes)\n", 9002 j, dlen - risc_size * sizeof(*dcode)); 9003 goto failed; 9004 } 9005 9006 fwdt->length = dlen; 9007 ql_dbg(ql_dbg_init, vha, 0x0178, 9008 "-> fwdt%u loaded template ok\n", j); 9009 9010 fwcode += risc_size + 1; 9011 } 9012 9013 return QLA_SUCCESS; 9014 9015 failed: 9016 vfree(fwdt->template); 9017 fwdt->template = NULL; 9018 fwdt->length = 0; 9019 9020 return QLA_SUCCESS; 9021 } 9022 9023 int 9024 qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 9025 { 9026 int rval; 9027 9028 if (ql2xfwloadbin == 1) 9029 return qla81xx_load_risc(vha, srisc_addr); 9030 9031 /* 9032 * FW Load priority: 9033 * 1) Firmware via request-firmware interface (.bin file). 9034 * 2) Firmware residing in flash. 9035 */ 9036 rval = qla24xx_load_risc_blob(vha, srisc_addr); 9037 if (rval == QLA_SUCCESS) 9038 return rval; 9039 9040 return qla24xx_load_risc_flash(vha, srisc_addr, 9041 vha->hw->flt_region_fw); 9042 } 9043 9044 int 9045 qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr) 9046 { 9047 int rval; 9048 uint32_t f_region = 0; 9049 struct qla_hw_data *ha = vha->hw; 9050 struct active_regions active_regions = { }; 9051 9052 if (ql2xfwloadbin == 2 && !IS_QLA28XX(ha)) 9053 goto try_blob_fw; 9054 9055 /* FW Load priority: 9056 * 1) If 28xxx, ROM cmd to load flash firmware. 9057 * 2) Firmware residing in flash. 9058 * 3) Firmware via request-firmware interface (.bin file). 9059 * 4) Golden-Firmware residing in flash -- (limited operation). 9060 */ 9061 9062 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 9063 goto try_primary_fw; 9064 9065 qla27xx_get_active_image(vha, &active_regions); 9066 9067 /* For 28XXX, always load the flash firmware using rom mbx */ 9068 if (IS_QLA28XX_SECURED(ha)) { 9069 rval = qla28xx_load_flash_firmware(vha); 9070 if (rval != QLA_SUCCESS) { 9071 ql_log(ql_log_fatal, vha, 0x019e, 9072 "Failed to load flash firmware.\n"); 9073 goto exit_load_risc; 9074 } 9075 9076 f_region = 9077 (active_regions.global != QLA27XX_SECONDARY_IMAGE) ? 9078 ha->flt_region_fw : ha->flt_region_fw_sec; 9079 9080 ql_log(ql_log_info, vha, 0x019f, 9081 "Load flash firmware successful (%s).\n", 9082 ((active_regions.global != QLA27XX_SECONDARY_IMAGE) ? 9083 "Primary" : "Secondary")); 9084 9085 rval = qla28xx_get_srisc_addr(vha, srisc_addr, f_region); 9086 if (rval != QLA_SUCCESS) { 9087 ql_log(ql_log_warn, vha, 0x019f, 9088 "failed to read srisc address\n"); 9089 goto exit_load_risc; 9090 } 9091 9092 rval = qla28xx_load_fw_template(vha, f_region); 9093 if (rval != QLA_SUCCESS) { 9094 ql_log(ql_log_warn, vha, 0x01a0, 9095 "failed to read firmware template\n"); 9096 } 9097 9098 goto exit_load_risc; 9099 } 9100 9101 if (active_regions.global != QLA27XX_SECONDARY_IMAGE) 9102 goto try_primary_fw; 9103 9104 ql_dbg(ql_dbg_init, vha, 0x008b, 9105 "Loading secondary firmware image.\n"); 9106 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw_sec); 9107 if (!rval) 9108 return rval; 9109 9110 try_primary_fw: 9111 ql_dbg(ql_dbg_init, vha, 0x008b, 9112 "Loading primary firmware image.\n"); 9113 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw); 9114 if (!rval) 9115 return rval; 9116 9117 try_blob_fw: 9118 rval = qla24xx_load_risc_blob(vha, srisc_addr); 9119 if (!rval || !ha->flt_region_gold_fw) 9120 return rval; 9121 9122 ql_log(ql_log_info, vha, 0x0099, 9123 "Attempting to fallback to golden firmware.\n"); 9124 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw); 9125 if (rval) 9126 return rval; 9127 9128 ql_log(ql_log_info, vha, 0x009a, "Need firmware flash update.\n"); 9129 ha->flags.running_gold_fw = 1; 9130 9131 exit_load_risc: 9132 return rval; 9133 } 9134 9135 void 9136 qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha) 9137 { 9138 int ret, retries; 9139 struct qla_hw_data *ha = vha->hw; 9140 9141 if (ha->flags.pci_channel_io_perm_failure) 9142 return; 9143 if (!IS_FWI2_CAPABLE(ha)) 9144 return; 9145 if (!ha->fw_major_version) 9146 return; 9147 if (!ha->flags.fw_started) 9148 return; 9149 9150 ret = qla2x00_stop_firmware(vha); 9151 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT && 9152 ret != QLA_INVALID_COMMAND && retries ; retries--) { 9153 ha->isp_ops->reset_chip(vha); 9154 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS) 9155 continue; 9156 if (qla2x00_setup_chip(vha) != QLA_SUCCESS) 9157 continue; 9158 ql_log(ql_log_info, vha, 0x8015, 9159 "Attempting retry of stop-firmware command.\n"); 9160 ret = qla2x00_stop_firmware(vha); 9161 } 9162 9163 QLA_FW_STOPPED(ha); 9164 ha->flags.fw_init_done = 0; 9165 } 9166 9167 int 9168 qla24xx_configure_vhba(scsi_qla_host_t *vha) 9169 { 9170 int rval = QLA_SUCCESS; 9171 int rval2; 9172 uint16_t mb[MAILBOX_REGISTER_COUNT]; 9173 struct qla_hw_data *ha = vha->hw; 9174 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 9175 9176 if (!vha->vp_idx) 9177 return -EINVAL; 9178 9179 rval = qla2x00_fw_ready(base_vha); 9180 9181 if (rval == QLA_SUCCESS) { 9182 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 9183 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 9184 } 9185 9186 vha->flags.management_server_logged_in = 0; 9187 9188 /* Login to SNS first */ 9189 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb, 9190 BIT_1); 9191 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) { 9192 if (rval2 == QLA_MEMORY_ALLOC_FAILED) 9193 ql_dbg(ql_dbg_init, vha, 0x0120, 9194 "Failed SNS login: loop_id=%x, rval2=%d\n", 9195 NPH_SNS, rval2); 9196 else 9197 ql_dbg(ql_dbg_init, vha, 0x0103, 9198 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x " 9199 "mb[2]=%x mb[6]=%x mb[7]=%x.\n", 9200 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]); 9201 return (QLA_FUNCTION_FAILED); 9202 } 9203 9204 atomic_set(&vha->loop_down_timer, 0); 9205 atomic_set(&vha->loop_state, LOOP_UP); 9206 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 9207 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 9208 rval = qla2x00_loop_resync(base_vha); 9209 9210 return rval; 9211 } 9212 9213 /* 84XX Support **************************************************************/ 9214 9215 static LIST_HEAD(qla_cs84xx_list); 9216 static DEFINE_MUTEX(qla_cs84xx_mutex); 9217 9218 static struct qla_chip_state_84xx * 9219 qla84xx_get_chip(struct scsi_qla_host *vha) 9220 { 9221 struct qla_chip_state_84xx *cs84xx; 9222 struct qla_hw_data *ha = vha->hw; 9223 9224 mutex_lock(&qla_cs84xx_mutex); 9225 9226 /* Find any shared 84xx chip. */ 9227 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) { 9228 if (cs84xx->bus == ha->pdev->bus) { 9229 kref_get(&cs84xx->kref); 9230 goto done; 9231 } 9232 } 9233 9234 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL); 9235 if (!cs84xx) 9236 goto done; 9237 9238 kref_init(&cs84xx->kref); 9239 spin_lock_init(&cs84xx->access_lock); 9240 mutex_init(&cs84xx->fw_update_mutex); 9241 cs84xx->bus = ha->pdev->bus; 9242 9243 list_add_tail(&cs84xx->list, &qla_cs84xx_list); 9244 done: 9245 mutex_unlock(&qla_cs84xx_mutex); 9246 return cs84xx; 9247 } 9248 9249 static void 9250 __qla84xx_chip_release(struct kref *kref) 9251 { 9252 struct qla_chip_state_84xx *cs84xx = 9253 container_of(kref, struct qla_chip_state_84xx, kref); 9254 9255 mutex_lock(&qla_cs84xx_mutex); 9256 list_del(&cs84xx->list); 9257 mutex_unlock(&qla_cs84xx_mutex); 9258 kfree(cs84xx); 9259 } 9260 9261 void 9262 qla84xx_put_chip(struct scsi_qla_host *vha) 9263 { 9264 struct qla_hw_data *ha = vha->hw; 9265 9266 if (ha->cs84xx) 9267 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release); 9268 } 9269 9270 static int 9271 qla84xx_init_chip(scsi_qla_host_t *vha) 9272 { 9273 int rval; 9274 uint16_t status[2]; 9275 struct qla_hw_data *ha = vha->hw; 9276 9277 mutex_lock(&ha->cs84xx->fw_update_mutex); 9278 9279 rval = qla84xx_verify_chip(vha, status); 9280 9281 mutex_unlock(&ha->cs84xx->fw_update_mutex); 9282 9283 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED : 9284 QLA_SUCCESS; 9285 } 9286 9287 /* 81XX Support **************************************************************/ 9288 9289 int 9290 qla81xx_nvram_config(scsi_qla_host_t *vha) 9291 { 9292 int rval; 9293 struct init_cb_81xx *icb; 9294 struct nvram_81xx *nv; 9295 __le32 *dptr; 9296 uint8_t *dptr1, *dptr2; 9297 uint32_t chksum; 9298 uint16_t cnt; 9299 struct qla_hw_data *ha = vha->hw; 9300 uint32_t faddr; 9301 struct active_regions active_regions = { }; 9302 9303 rval = QLA_SUCCESS; 9304 icb = (struct init_cb_81xx *)ha->init_cb; 9305 nv = ha->nvram; 9306 9307 /* Determine NVRAM starting address. */ 9308 ha->nvram_size = sizeof(*nv); 9309 ha->vpd_size = FA_NVRAM_VPD_SIZE; 9310 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 9311 ha->vpd_size = FA_VPD_SIZE_82XX; 9312 9313 if (IS_QLA28XX(ha) || IS_QLA27XX(ha)) 9314 qla28xx_get_aux_images(vha, &active_regions); 9315 9316 /* Get VPD data into cache */ 9317 ha->vpd = ha->nvram + VPD_OFFSET; 9318 9319 faddr = ha->flt_region_vpd; 9320 if (IS_QLA28XX(ha)) { 9321 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE) 9322 faddr = ha->flt_region_vpd_sec; 9323 ql_dbg(ql_dbg_init, vha, 0x0110, 9324 "Loading %s nvram image.\n", 9325 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ? 9326 "primary" : "secondary"); 9327 } 9328 ha->isp_ops->read_optrom(vha, ha->vpd, faddr << 2, ha->vpd_size); 9329 9330 /* Get NVRAM data into cache and calculate checksum. */ 9331 faddr = ha->flt_region_nvram; 9332 if (IS_QLA28XX(ha)) { 9333 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE) 9334 faddr = ha->flt_region_nvram_sec; 9335 } 9336 ql_dbg(ql_dbg_init, vha, 0x0110, 9337 "Loading %s nvram image.\n", 9338 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ? 9339 "primary" : "secondary"); 9340 ha->isp_ops->read_optrom(vha, ha->nvram, faddr << 2, ha->nvram_size); 9341 9342 dptr = (__force __le32 *)nv; 9343 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++) 9344 chksum += le32_to_cpu(*dptr); 9345 9346 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111, 9347 "Contents of NVRAM:\n"); 9348 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112, 9349 nv, ha->nvram_size); 9350 9351 /* Bad NVRAM data, set defaults parameters. */ 9352 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) || 9353 le16_to_cpu(nv->nvram_version) < ICB_VERSION) { 9354 /* Reset NVRAM data. */ 9355 ql_log(ql_log_info, vha, 0x0073, 9356 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n", 9357 chksum, nv->id, le16_to_cpu(nv->nvram_version)); 9358 ql_dump_buffer(ql_dbg_init, vha, 0x0073, nv, sizeof(*nv)); 9359 ql_log(ql_log_info, vha, 0x0074, 9360 "Falling back to functioning (yet invalid -- WWPN) " 9361 "defaults.\n"); 9362 9363 /* 9364 * Set default initialization control block. 9365 */ 9366 memset(nv, 0, ha->nvram_size); 9367 nv->nvram_version = cpu_to_le16(ICB_VERSION); 9368 nv->version = cpu_to_le16(ICB_VERSION); 9369 nv->frame_payload_size = cpu_to_le16(2048); 9370 nv->execution_throttle = cpu_to_le16(0xFFFF); 9371 nv->exchange_count = cpu_to_le16(0); 9372 nv->port_name[0] = 0x21; 9373 nv->port_name[1] = 0x00 + ha->port_no + 1; 9374 nv->port_name[2] = 0x00; 9375 nv->port_name[3] = 0xe0; 9376 nv->port_name[4] = 0x8b; 9377 nv->port_name[5] = 0x1c; 9378 nv->port_name[6] = 0x55; 9379 nv->port_name[7] = 0x86; 9380 nv->node_name[0] = 0x20; 9381 nv->node_name[1] = 0x00; 9382 nv->node_name[2] = 0x00; 9383 nv->node_name[3] = 0xe0; 9384 nv->node_name[4] = 0x8b; 9385 nv->node_name[5] = 0x1c; 9386 nv->node_name[6] = 0x55; 9387 nv->node_name[7] = 0x86; 9388 nv->login_retry_count = cpu_to_le16(8); 9389 nv->interrupt_delay_timer = cpu_to_le16(0); 9390 nv->login_timeout = cpu_to_le16(0); 9391 nv->firmware_options_1 = 9392 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1); 9393 nv->firmware_options_2 = cpu_to_le32(2 << 4); 9394 nv->firmware_options_2 |= cpu_to_le32(BIT_12); 9395 nv->firmware_options_3 = cpu_to_le32(2 << 13); 9396 nv->host_p = cpu_to_le32(BIT_11|BIT_10); 9397 nv->efi_parameters = cpu_to_le32(0); 9398 nv->reset_delay = 5; 9399 nv->max_luns_per_target = cpu_to_le16(128); 9400 nv->port_down_retry_count = cpu_to_le16(30); 9401 nv->link_down_timeout = cpu_to_le16(180); 9402 nv->enode_mac[0] = 0x00; 9403 nv->enode_mac[1] = 0xC0; 9404 nv->enode_mac[2] = 0xDD; 9405 nv->enode_mac[3] = 0x04; 9406 nv->enode_mac[4] = 0x05; 9407 nv->enode_mac[5] = 0x06 + ha->port_no + 1; 9408 9409 rval = 1; 9410 } 9411 9412 if (IS_T10_PI_CAPABLE(ha)) 9413 nv->frame_payload_size &= cpu_to_le16(~7); 9414 9415 qlt_81xx_config_nvram_stage1(vha, nv); 9416 9417 /* Reset Initialization control block */ 9418 memset(icb, 0, ha->init_cb_size); 9419 9420 /* Copy 1st segment. */ 9421 dptr1 = (uint8_t *)icb; 9422 dptr2 = (uint8_t *)&nv->version; 9423 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version; 9424 while (cnt--) 9425 *dptr1++ = *dptr2++; 9426 9427 icb->login_retry_count = nv->login_retry_count; 9428 9429 /* Copy 2nd segment. */ 9430 dptr1 = (uint8_t *)&icb->interrupt_delay_timer; 9431 dptr2 = (uint8_t *)&nv->interrupt_delay_timer; 9432 cnt = (uint8_t *)&icb->reserved_5 - 9433 (uint8_t *)&icb->interrupt_delay_timer; 9434 while (cnt--) 9435 *dptr1++ = *dptr2++; 9436 9437 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac)); 9438 /* Some boards (with valid NVRAMs) still have NULL enode_mac!! */ 9439 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) { 9440 icb->enode_mac[0] = 0x00; 9441 icb->enode_mac[1] = 0xC0; 9442 icb->enode_mac[2] = 0xDD; 9443 icb->enode_mac[3] = 0x04; 9444 icb->enode_mac[4] = 0x05; 9445 icb->enode_mac[5] = 0x06 + ha->port_no + 1; 9446 } 9447 9448 /* Use extended-initialization control block. */ 9449 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb)); 9450 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size); 9451 /* 9452 * Setup driver NVRAM options. 9453 */ 9454 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name), 9455 "QLE8XXX"); 9456 9457 qlt_81xx_config_nvram_stage2(vha, icb); 9458 9459 /* Use alternate WWN? */ 9460 if (nv->host_p & cpu_to_le32(BIT_15)) { 9461 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE); 9462 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE); 9463 } 9464 9465 /* Prepare nodename */ 9466 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) { 9467 /* 9468 * Firmware will apply the following mask if the nodename was 9469 * not provided. 9470 */ 9471 memcpy(icb->node_name, icb->port_name, WWN_SIZE); 9472 icb->node_name[0] &= 0xF0; 9473 } 9474 9475 if (IS_QLA28XX(ha) || IS_QLA27XX(ha)) { 9476 if ((nv->enhanced_features & BIT_7) == 0) 9477 ha->flags.scm_supported_a = 1; 9478 } 9479 9480 /* Set host adapter parameters. */ 9481 ha->flags.disable_risc_code_load = 0; 9482 ha->flags.enable_lip_reset = 0; 9483 ha->flags.enable_lip_full_login = 9484 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0; 9485 ha->flags.enable_target_reset = 9486 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0; 9487 ha->flags.enable_led_scheme = 0; 9488 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0; 9489 9490 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) & 9491 (BIT_6 | BIT_5 | BIT_4)) >> 4; 9492 9493 /* save HBA serial number */ 9494 ha->serial0 = icb->port_name[5]; 9495 ha->serial1 = icb->port_name[6]; 9496 ha->serial2 = icb->port_name[7]; 9497 memcpy(vha->node_name, icb->node_name, WWN_SIZE); 9498 memcpy(vha->port_name, icb->port_name, WWN_SIZE); 9499 9500 icb->execution_throttle = cpu_to_le16(0xFFFF); 9501 9502 ha->retry_count = le16_to_cpu(nv->login_retry_count); 9503 9504 /* Set minimum login_timeout to 4 seconds. */ 9505 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout) 9506 nv->login_timeout = cpu_to_le16(ql2xlogintimeout); 9507 if (le16_to_cpu(nv->login_timeout) < 4) 9508 nv->login_timeout = cpu_to_le16(4); 9509 ha->login_timeout = le16_to_cpu(nv->login_timeout); 9510 9511 /* Set minimum RATOV to 100 tenths of a second. */ 9512 ha->r_a_tov = 100; 9513 9514 ha->loop_reset_delay = nv->reset_delay; 9515 9516 /* Link Down Timeout = 0: 9517 * 9518 * When Port Down timer expires we will start returning 9519 * I/O's to OS with "DID_NO_CONNECT". 9520 * 9521 * Link Down Timeout != 0: 9522 * 9523 * The driver waits for the link to come up after link down 9524 * before returning I/Os to OS with "DID_NO_CONNECT". 9525 */ 9526 if (le16_to_cpu(nv->link_down_timeout) == 0) { 9527 ha->loop_down_abort_time = 9528 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT); 9529 } else { 9530 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout); 9531 ha->loop_down_abort_time = 9532 (LOOP_DOWN_TIME - ha->link_down_timeout); 9533 } 9534 9535 /* Need enough time to try and get the port back. */ 9536 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count); 9537 if (qlport_down_retry) 9538 ha->port_down_retry_count = qlport_down_retry; 9539 9540 /* Set login_retry_count */ 9541 ha->login_retry_count = le16_to_cpu(nv->login_retry_count); 9542 if (ha->port_down_retry_count == 9543 le16_to_cpu(nv->port_down_retry_count) && 9544 ha->port_down_retry_count > 3) 9545 ha->login_retry_count = ha->port_down_retry_count; 9546 else if (ha->port_down_retry_count > (int)ha->login_retry_count) 9547 ha->login_retry_count = ha->port_down_retry_count; 9548 if (ql2xloginretrycount) 9549 ha->login_retry_count = ql2xloginretrycount; 9550 9551 /* if not running MSI-X we need handshaking on interrupts */ 9552 if (!vha->hw->flags.msix_enabled && 9553 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) 9554 icb->firmware_options_2 |= cpu_to_le32(BIT_22); 9555 9556 /* Enable ZIO. */ 9557 if (!vha->flags.init_done) { 9558 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) & 9559 (BIT_3 | BIT_2 | BIT_1 | BIT_0); 9560 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ? 9561 le16_to_cpu(icb->interrupt_delay_timer) : 2; 9562 } 9563 icb->firmware_options_2 &= cpu_to_le32( 9564 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0)); 9565 vha->flags.process_response_queue = 0; 9566 if (ha->zio_mode != QLA_ZIO_DISABLED) { 9567 ha->zio_mode = QLA_ZIO_MODE_6; 9568 9569 ql_log(ql_log_info, vha, 0x0075, 9570 "ZIO mode %d enabled; timer delay (%d us).\n", 9571 ha->zio_mode, 9572 ha->zio_timer * 100); 9573 9574 icb->firmware_options_2 |= cpu_to_le32( 9575 (uint32_t)ha->zio_mode); 9576 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer); 9577 vha->flags.process_response_queue = 1; 9578 } 9579 9580 /* enable RIDA Format2 */ 9581 icb->firmware_options_3 |= cpu_to_le32(BIT_0); 9582 9583 /* N2N: driver will initiate Login instead of FW */ 9584 icb->firmware_options_3 |= cpu_to_le32(BIT_8); 9585 9586 /* Determine NVMe/FCP priority for target ports */ 9587 ha->fc4_type_priority = qla2xxx_get_fc4_priority(vha); 9588 9589 if (rval) { 9590 ql_log(ql_log_warn, vha, 0x0076, 9591 "NVRAM configuration failed.\n"); 9592 } 9593 return (rval); 9594 } 9595 9596 int 9597 qla82xx_restart_isp(scsi_qla_host_t *vha) 9598 { 9599 int status, rval; 9600 struct qla_hw_data *ha = vha->hw; 9601 struct scsi_qla_host *vp, *tvp; 9602 unsigned long flags; 9603 9604 status = qla2x00_init_rings(vha); 9605 if (!status) { 9606 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 9607 ha->flags.chip_reset_done = 1; 9608 9609 status = qla2x00_fw_ready(vha); 9610 if (!status) { 9611 /* Issue a marker after FW becomes ready. */ 9612 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL); 9613 vha->flags.online = 1; 9614 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 9615 } 9616 9617 /* if no cable then assume it's good */ 9618 if ((vha->device_flags & DFLG_NO_CABLE)) 9619 status = 0; 9620 } 9621 9622 if (!status) { 9623 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 9624 9625 if (!atomic_read(&vha->loop_down_timer)) { 9626 /* 9627 * Issue marker command only when we are going 9628 * to start the I/O . 9629 */ 9630 vha->marker_needed = 1; 9631 } 9632 9633 ha->isp_ops->enable_intrs(ha); 9634 9635 ha->isp_abort_cnt = 0; 9636 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags); 9637 9638 /* Update the firmware version */ 9639 status = qla82xx_check_md_needed(vha); 9640 9641 if (ha->fce) { 9642 ha->flags.fce_enabled = 1; 9643 memset(ha->fce, 0, 9644 fce_calc_size(ha->fce_bufs)); 9645 rval = qla2x00_enable_fce_trace(vha, 9646 ha->fce_dma, ha->fce_bufs, ha->fce_mb, 9647 &ha->fce_bufs); 9648 if (rval) { 9649 ql_log(ql_log_warn, vha, 0x8001, 9650 "Unable to reinitialize FCE (%d).\n", 9651 rval); 9652 ha->flags.fce_enabled = 0; 9653 } 9654 } 9655 9656 if (ha->eft) { 9657 memset(ha->eft, 0, EFT_SIZE); 9658 rval = qla2x00_enable_eft_trace(vha, 9659 ha->eft_dma, EFT_NUM_BUFFERS); 9660 if (rval) { 9661 ql_log(ql_log_warn, vha, 0x8010, 9662 "Unable to reinitialize EFT (%d).\n", 9663 rval); 9664 } 9665 } 9666 } 9667 9668 if (!status) { 9669 ql_dbg(ql_dbg_taskm, vha, 0x8011, 9670 "qla82xx_restart_isp succeeded.\n"); 9671 9672 spin_lock_irqsave(&ha->vport_slock, flags); 9673 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 9674 if (vp->vp_idx) { 9675 atomic_inc(&vp->vref_count); 9676 spin_unlock_irqrestore(&ha->vport_slock, flags); 9677 9678 qla2x00_vp_abort_isp(vp); 9679 9680 spin_lock_irqsave(&ha->vport_slock, flags); 9681 atomic_dec(&vp->vref_count); 9682 } 9683 } 9684 spin_unlock_irqrestore(&ha->vport_slock, flags); 9685 9686 } else { 9687 ql_log(ql_log_warn, vha, 0x8016, 9688 "qla82xx_restart_isp **** FAILED ****.\n"); 9689 } 9690 9691 return status; 9692 } 9693 9694 /* 9695 * qla24xx_get_fcp_prio 9696 * Gets the fcp cmd priority value for the logged in port. 9697 * Looks for a match of the port descriptors within 9698 * each of the fcp prio config entries. If a match is found, 9699 * the tag (priority) value is returned. 9700 * 9701 * Input: 9702 * vha = scsi host structure pointer. 9703 * fcport = port structure pointer. 9704 * 9705 * Return: 9706 * non-zero (if found) 9707 * -1 (if not found) 9708 * 9709 * Context: 9710 * Kernel context 9711 */ 9712 static int 9713 qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 9714 { 9715 int i, entries; 9716 uint8_t pid_match, wwn_match; 9717 int priority; 9718 uint32_t pid1, pid2; 9719 uint64_t wwn1, wwn2; 9720 struct qla_fcp_prio_entry *pri_entry; 9721 struct qla_hw_data *ha = vha->hw; 9722 9723 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled) 9724 return -1; 9725 9726 priority = -1; 9727 entries = ha->fcp_prio_cfg->num_entries; 9728 pri_entry = &ha->fcp_prio_cfg->entry[0]; 9729 9730 for (i = 0; i < entries; i++) { 9731 pid_match = wwn_match = 0; 9732 9733 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) { 9734 pri_entry++; 9735 continue; 9736 } 9737 9738 /* check source pid for a match */ 9739 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) { 9740 pid1 = pri_entry->src_pid & INVALID_PORT_ID; 9741 pid2 = vha->d_id.b24 & INVALID_PORT_ID; 9742 if (pid1 == INVALID_PORT_ID) 9743 pid_match++; 9744 else if (pid1 == pid2) 9745 pid_match++; 9746 } 9747 9748 /* check destination pid for a match */ 9749 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) { 9750 pid1 = pri_entry->dst_pid & INVALID_PORT_ID; 9751 pid2 = fcport->d_id.b24 & INVALID_PORT_ID; 9752 if (pid1 == INVALID_PORT_ID) 9753 pid_match++; 9754 else if (pid1 == pid2) 9755 pid_match++; 9756 } 9757 9758 /* check source WWN for a match */ 9759 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) { 9760 wwn1 = wwn_to_u64(vha->port_name); 9761 wwn2 = wwn_to_u64(pri_entry->src_wwpn); 9762 if (wwn2 == (uint64_t)-1) 9763 wwn_match++; 9764 else if (wwn1 == wwn2) 9765 wwn_match++; 9766 } 9767 9768 /* check destination WWN for a match */ 9769 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) { 9770 wwn1 = wwn_to_u64(fcport->port_name); 9771 wwn2 = wwn_to_u64(pri_entry->dst_wwpn); 9772 if (wwn2 == (uint64_t)-1) 9773 wwn_match++; 9774 else if (wwn1 == wwn2) 9775 wwn_match++; 9776 } 9777 9778 if (pid_match == 2 || wwn_match == 2) { 9779 /* Found a matching entry */ 9780 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID) 9781 priority = pri_entry->tag; 9782 break; 9783 } 9784 9785 pri_entry++; 9786 } 9787 9788 return priority; 9789 } 9790 9791 /* 9792 * qla24xx_update_fcport_fcp_prio 9793 * Activates fcp priority for the logged in fc port 9794 * 9795 * Input: 9796 * vha = scsi host structure pointer. 9797 * fcp = port structure pointer. 9798 * 9799 * Return: 9800 * QLA_SUCCESS or QLA_FUNCTION_FAILED 9801 * 9802 * Context: 9803 * Kernel context. 9804 */ 9805 int 9806 qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport) 9807 { 9808 int ret; 9809 int priority; 9810 uint16_t mb[5]; 9811 9812 if (fcport->port_type != FCT_TARGET || 9813 fcport->loop_id == FC_NO_LOOP_ID) 9814 return QLA_FUNCTION_FAILED; 9815 9816 priority = qla24xx_get_fcp_prio(vha, fcport); 9817 if (priority < 0) 9818 return QLA_FUNCTION_FAILED; 9819 9820 if (IS_P3P_TYPE(vha->hw)) { 9821 fcport->fcp_prio = priority & 0xf; 9822 return QLA_SUCCESS; 9823 } 9824 9825 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb); 9826 if (ret == QLA_SUCCESS) { 9827 if (fcport->fcp_prio != priority) 9828 ql_dbg(ql_dbg_user, vha, 0x709e, 9829 "Updated FCP_CMND priority - value=%d loop_id=%d " 9830 "port_id=%02x%02x%02x.\n", priority, 9831 fcport->loop_id, fcport->d_id.b.domain, 9832 fcport->d_id.b.area, fcport->d_id.b.al_pa); 9833 fcport->fcp_prio = priority & 0xf; 9834 } else 9835 ql_dbg(ql_dbg_user, vha, 0x704f, 9836 "Unable to update FCP_CMND priority - ret=0x%x for " 9837 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id, 9838 fcport->d_id.b.domain, fcport->d_id.b.area, 9839 fcport->d_id.b.al_pa); 9840 return ret; 9841 } 9842 9843 /* 9844 * qla24xx_update_all_fcp_prio 9845 * Activates fcp priority for all the logged in ports 9846 * 9847 * Input: 9848 * ha = adapter block pointer. 9849 * 9850 * Return: 9851 * QLA_SUCCESS or QLA_FUNCTION_FAILED 9852 * 9853 * Context: 9854 * Kernel context. 9855 */ 9856 int 9857 qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha) 9858 { 9859 int ret; 9860 fc_port_t *fcport; 9861 9862 ret = QLA_FUNCTION_FAILED; 9863 /* We need to set priority for all logged in ports */ 9864 list_for_each_entry(fcport, &vha->vp_fcports, list) 9865 ret = qla24xx_update_fcport_fcp_prio(vha, fcport); 9866 9867 return ret; 9868 } 9869 9870 struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos, 9871 int vp_idx, bool startqp) 9872 { 9873 int rsp_id = 0; 9874 int req_id = 0; 9875 int i; 9876 struct qla_hw_data *ha = vha->hw; 9877 uint16_t qpair_id = 0; 9878 struct qla_qpair *qpair = NULL; 9879 struct qla_msix_entry *msix; 9880 9881 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) { 9882 ql_log(ql_log_warn, vha, 0x00181, 9883 "FW/Driver is not multi-queue capable.\n"); 9884 return NULL; 9885 } 9886 9887 if (ql2xmqsupport || ql2xnvmeenable) { 9888 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 9889 if (qpair == NULL) { 9890 ql_log(ql_log_warn, vha, 0x0182, 9891 "Failed to allocate memory for queue pair.\n"); 9892 return NULL; 9893 } 9894 9895 qpair->hw = vha->hw; 9896 qpair->vha = vha; 9897 qpair->qp_lock_ptr = &qpair->qp_lock; 9898 spin_lock_init(&qpair->qp_lock); 9899 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 9900 9901 /* Assign available que pair id */ 9902 mutex_lock(&ha->mq_lock); 9903 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs); 9904 if (ha->num_qpairs >= ha->max_qpairs) { 9905 mutex_unlock(&ha->mq_lock); 9906 ql_log(ql_log_warn, vha, 0x0183, 9907 "No resources to create additional q pair.\n"); 9908 goto fail_qid_map; 9909 } 9910 ha->num_qpairs++; 9911 set_bit(qpair_id, ha->qpair_qid_map); 9912 ha->queue_pair_map[qpair_id] = qpair; 9913 qpair->id = qpair_id; 9914 qpair->vp_idx = vp_idx; 9915 qpair->fw_started = ha->flags.fw_started; 9916 INIT_LIST_HEAD(&qpair->hints_list); 9917 INIT_LIST_HEAD(&qpair->dsd_list); 9918 qpair->chip_reset = ha->base_qpair->chip_reset; 9919 qpair->enable_class_2 = ha->base_qpair->enable_class_2; 9920 qpair->enable_explicit_conf = 9921 ha->base_qpair->enable_explicit_conf; 9922 9923 for (i = 0; i < ha->msix_count; i++) { 9924 msix = &ha->msix_entries[i]; 9925 if (msix->in_use) 9926 continue; 9927 qpair->msix = msix; 9928 ql_dbg(ql_dbg_multiq, vha, 0xc00f, 9929 "Vector %x selected for qpair\n", msix->vector); 9930 break; 9931 } 9932 if (!qpair->msix) { 9933 ql_log(ql_log_warn, vha, 0x0184, 9934 "Out of MSI-X vectors!.\n"); 9935 goto fail_msix; 9936 } 9937 9938 qpair->msix->in_use = 1; 9939 list_add_tail(&qpair->qp_list_elem, &vha->qp_list); 9940 qpair->pdev = ha->pdev; 9941 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 9942 qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 9943 9944 mutex_unlock(&ha->mq_lock); 9945 9946 /* Create response queue first */ 9947 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp); 9948 if (!rsp_id) { 9949 ql_log(ql_log_warn, vha, 0x0185, 9950 "Failed to create response queue.\n"); 9951 goto fail_rsp; 9952 } 9953 9954 qpair->rsp = ha->rsp_q_map[rsp_id]; 9955 9956 /* Create request queue */ 9957 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos, 9958 startqp); 9959 if (!req_id) { 9960 ql_log(ql_log_warn, vha, 0x0186, 9961 "Failed to create request queue.\n"); 9962 goto fail_req; 9963 } 9964 9965 qpair->req = ha->req_q_map[req_id]; 9966 qpair->rsp->req = qpair->req; 9967 qpair->rsp->qpair = qpair; 9968 9969 if (!qpair->cpu_mapped) 9970 qla_cpu_update(qpair, raw_smp_processor_id()); 9971 9972 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 9973 if (ha->fw_attributes & BIT_4) 9974 qpair->difdix_supported = 1; 9975 } 9976 9977 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 9978 if (!qpair->srb_mempool) { 9979 ql_log(ql_log_warn, vha, 0xd036, 9980 "Failed to create srb mempool for qpair %d\n", 9981 qpair->id); 9982 goto fail_mempool; 9983 } 9984 9985 if (qla_create_buf_pool(vha, qpair)) { 9986 ql_log(ql_log_warn, vha, 0xd036, 9987 "Failed to initialize buf pool for qpair %d\n", 9988 qpair->id); 9989 goto fail_bufpool; 9990 } 9991 9992 /* Mark as online */ 9993 qpair->online = 1; 9994 9995 if (!vha->flags.qpairs_available) 9996 vha->flags.qpairs_available = 1; 9997 9998 ql_dbg(ql_dbg_multiq, vha, 0xc00d, 9999 "Request/Response queue pair created, id %d\n", 10000 qpair->id); 10001 ql_dbg(ql_dbg_init, vha, 0x0187, 10002 "Request/Response queue pair created, id %d\n", 10003 qpair->id); 10004 } 10005 return qpair; 10006 10007 fail_bufpool: 10008 mempool_destroy(qpair->srb_mempool); 10009 fail_mempool: 10010 qla25xx_delete_req_que(vha, qpair->req); 10011 fail_req: 10012 qla25xx_delete_rsp_que(vha, qpair->rsp); 10013 fail_rsp: 10014 mutex_lock(&ha->mq_lock); 10015 qpair->msix->in_use = 0; 10016 list_del(&qpair->qp_list_elem); 10017 if (list_empty(&vha->qp_list)) 10018 vha->flags.qpairs_available = 0; 10019 fail_msix: 10020 ha->queue_pair_map[qpair_id] = NULL; 10021 clear_bit(qpair_id, ha->qpair_qid_map); 10022 ha->num_qpairs--; 10023 mutex_unlock(&ha->mq_lock); 10024 fail_qid_map: 10025 kfree(qpair); 10026 return NULL; 10027 } 10028 10029 int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair) 10030 { 10031 int ret = QLA_FUNCTION_FAILED; 10032 struct qla_hw_data *ha = qpair->hw; 10033 10034 qpair->delete_in_progress = 1; 10035 10036 qla_free_buf_pool(qpair); 10037 10038 ret = qla25xx_delete_req_que(vha, qpair->req); 10039 if (ret != QLA_SUCCESS) 10040 goto fail; 10041 10042 ret = qla25xx_delete_rsp_que(vha, qpair->rsp); 10043 if (ret != QLA_SUCCESS) 10044 goto fail; 10045 10046 if (!list_empty(&qpair->dsd_list)) { 10047 struct dsd_dma *dsd_ptr, *tdsd_ptr; 10048 10049 /* clean up allocated prev pool */ 10050 list_for_each_entry_safe(dsd_ptr, tdsd_ptr, 10051 &qpair->dsd_list, list) { 10052 dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr, 10053 dsd_ptr->dsd_list_dma); 10054 list_del(&dsd_ptr->list); 10055 kfree(dsd_ptr); 10056 } 10057 } 10058 10059 mutex_lock(&ha->mq_lock); 10060 ha->queue_pair_map[qpair->id] = NULL; 10061 clear_bit(qpair->id, ha->qpair_qid_map); 10062 ha->num_qpairs--; 10063 list_del(&qpair->qp_list_elem); 10064 if (list_empty(&vha->qp_list)) { 10065 vha->flags.qpairs_available = 0; 10066 vha->flags.qpairs_req_created = 0; 10067 vha->flags.qpairs_rsp_created = 0; 10068 } 10069 mempool_destroy(qpair->srb_mempool); 10070 kfree(qpair); 10071 mutex_unlock(&ha->mq_lock); 10072 10073 return QLA_SUCCESS; 10074 fail: 10075 return ret; 10076 } 10077 10078 uint64_t 10079 qla2x00_count_set_bits(uint32_t num) 10080 { 10081 /* Brian Kernighan's Algorithm */ 10082 u64 count = 0; 10083 10084 while (num) { 10085 num &= (num - 1); 10086 count++; 10087 } 10088 return count; 10089 } 10090 10091 uint64_t 10092 qla2x00_get_num_tgts(scsi_qla_host_t *vha) 10093 { 10094 fc_port_t *f, *tf; 10095 u64 count = 0; 10096 10097 f = NULL; 10098 tf = NULL; 10099 10100 list_for_each_entry_safe(f, tf, &vha->vp_fcports, list) { 10101 if (f->port_type != FCT_TARGET) 10102 continue; 10103 count++; 10104 } 10105 return count; 10106 } 10107 10108 int qla2xxx_reset_stats(struct Scsi_Host *host, u32 flags) 10109 { 10110 scsi_qla_host_t *vha = shost_priv(host); 10111 fc_port_t *fcport = NULL; 10112 unsigned long int_flags; 10113 10114 if (flags & QLA2XX_HW_ERROR) 10115 vha->hw_err_cnt = 0; 10116 if (flags & QLA2XX_SHT_LNK_DWN) 10117 vha->short_link_down_cnt = 0; 10118 if (flags & QLA2XX_INT_ERR) 10119 vha->interface_err_cnt = 0; 10120 if (flags & QLA2XX_CMD_TIMEOUT) 10121 vha->cmd_timeout_cnt = 0; 10122 if (flags & QLA2XX_RESET_CMD_ERR) 10123 vha->reset_cmd_err_cnt = 0; 10124 if (flags & QLA2XX_TGT_SHT_LNK_DOWN) { 10125 spin_lock_irqsave(&vha->hw->tgt.sess_lock, int_flags); 10126 list_for_each_entry(fcport, &vha->vp_fcports, list) { 10127 fcport->tgt_short_link_down_cnt = 0; 10128 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 10129 } 10130 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, int_flags); 10131 } 10132 vha->link_down_time = QLA2XX_MAX_LINK_DOWN_TIME; 10133 return 0; 10134 } 10135 10136 int qla2xxx_start_stats(struct Scsi_Host *host, u32 flags) 10137 { 10138 return qla2xxx_reset_stats(host, flags); 10139 } 10140 10141 int qla2xxx_stop_stats(struct Scsi_Host *host, u32 flags) 10142 { 10143 return qla2xxx_reset_stats(host, flags); 10144 } 10145 10146 int qla2xxx_get_ini_stats(struct Scsi_Host *host, u32 flags, 10147 void *data, u64 size) 10148 { 10149 scsi_qla_host_t *vha = shost_priv(host); 10150 struct ql_vnd_host_stats_resp *resp = (struct ql_vnd_host_stats_resp *)data; 10151 struct ql_vnd_stats *rsp_data = &resp->stats; 10152 u64 ini_entry_count = 0; 10153 u64 i = 0; 10154 u64 entry_count = 0; 10155 u64 num_tgt = 0; 10156 u32 tmp_stat_type = 0; 10157 fc_port_t *fcport = NULL; 10158 unsigned long int_flags; 10159 10160 /* Copy stat type to work on it */ 10161 tmp_stat_type = flags; 10162 10163 if (tmp_stat_type & BIT_17) { 10164 num_tgt = qla2x00_get_num_tgts(vha); 10165 /* unset BIT_17 */ 10166 tmp_stat_type &= ~(1 << 17); 10167 } 10168 ini_entry_count = qla2x00_count_set_bits(tmp_stat_type); 10169 10170 entry_count = ini_entry_count + num_tgt; 10171 10172 rsp_data->entry_count = entry_count; 10173 10174 i = 0; 10175 if (flags & QLA2XX_HW_ERROR) { 10176 rsp_data->entry[i].stat_type = QLA2XX_HW_ERROR; 10177 rsp_data->entry[i].tgt_num = 0x0; 10178 rsp_data->entry[i].cnt = vha->hw_err_cnt; 10179 i++; 10180 } 10181 10182 if (flags & QLA2XX_SHT_LNK_DWN) { 10183 rsp_data->entry[i].stat_type = QLA2XX_SHT_LNK_DWN; 10184 rsp_data->entry[i].tgt_num = 0x0; 10185 rsp_data->entry[i].cnt = vha->short_link_down_cnt; 10186 i++; 10187 } 10188 10189 if (flags & QLA2XX_INT_ERR) { 10190 rsp_data->entry[i].stat_type = QLA2XX_INT_ERR; 10191 rsp_data->entry[i].tgt_num = 0x0; 10192 rsp_data->entry[i].cnt = vha->interface_err_cnt; 10193 i++; 10194 } 10195 10196 if (flags & QLA2XX_CMD_TIMEOUT) { 10197 rsp_data->entry[i].stat_type = QLA2XX_CMD_TIMEOUT; 10198 rsp_data->entry[i].tgt_num = 0x0; 10199 rsp_data->entry[i].cnt = vha->cmd_timeout_cnt; 10200 i++; 10201 } 10202 10203 if (flags & QLA2XX_RESET_CMD_ERR) { 10204 rsp_data->entry[i].stat_type = QLA2XX_RESET_CMD_ERR; 10205 rsp_data->entry[i].tgt_num = 0x0; 10206 rsp_data->entry[i].cnt = vha->reset_cmd_err_cnt; 10207 i++; 10208 } 10209 10210 /* i will continue from previous loop, as target 10211 * entries are after initiator 10212 */ 10213 if (flags & QLA2XX_TGT_SHT_LNK_DOWN) { 10214 spin_lock_irqsave(&vha->hw->tgt.sess_lock, int_flags); 10215 list_for_each_entry(fcport, &vha->vp_fcports, list) { 10216 if (fcport->port_type != FCT_TARGET) 10217 continue; 10218 if (!fcport->rport) 10219 continue; 10220 rsp_data->entry[i].stat_type = QLA2XX_TGT_SHT_LNK_DOWN; 10221 rsp_data->entry[i].tgt_num = fcport->rport->number; 10222 rsp_data->entry[i].cnt = fcport->tgt_short_link_down_cnt; 10223 i++; 10224 } 10225 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, int_flags); 10226 } 10227 resp->status = EXT_STATUS_OK; 10228 10229 return 0; 10230 } 10231 10232 int qla2xxx_get_tgt_stats(struct Scsi_Host *host, u32 flags, 10233 struct fc_rport *rport, void *data, u64 size) 10234 { 10235 struct ql_vnd_tgt_stats_resp *tgt_data = data; 10236 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 10237 10238 tgt_data->status = 0; 10239 tgt_data->stats.entry_count = 1; 10240 tgt_data->stats.entry[0].stat_type = flags; 10241 tgt_data->stats.entry[0].tgt_num = rport->number; 10242 tgt_data->stats.entry[0].cnt = fcport->tgt_short_link_down_cnt; 10243 10244 return 0; 10245 } 10246 10247 int qla2xxx_disable_port(struct Scsi_Host *host) 10248 { 10249 scsi_qla_host_t *vha = shost_priv(host); 10250 10251 vha->hw->flags.port_isolated = 1; 10252 10253 if (qla2x00_isp_reg_stat(vha->hw)) { 10254 ql_log(ql_log_info, vha, 0x9006, 10255 "PCI/Register disconnect, exiting.\n"); 10256 qla_pci_set_eeh_busy(vha); 10257 return FAILED; 10258 } 10259 if (qla2x00_chip_is_down(vha)) 10260 return 0; 10261 10262 if (vha->flags.online) { 10263 qla2x00_abort_isp_cleanup(vha); 10264 qla2x00_wait_for_sess_deletion(vha); 10265 } 10266 10267 return 0; 10268 } 10269 10270 int qla2xxx_enable_port(struct Scsi_Host *host) 10271 { 10272 scsi_qla_host_t *vha = shost_priv(host); 10273 10274 if (qla2x00_isp_reg_stat(vha->hw)) { 10275 ql_log(ql_log_info, vha, 0x9001, 10276 "PCI/Register disconnect, exiting.\n"); 10277 qla_pci_set_eeh_busy(vha); 10278 return FAILED; 10279 } 10280 10281 vha->hw->flags.port_isolated = 0; 10282 /* Set the flag to 1, so that isp_abort can proceed */ 10283 vha->flags.online = 1; 10284 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 10285 qla2xxx_wake_dpc(vha); 10286 10287 return 0; 10288 } 10289