1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (c) 2022, Qualcomm Innovation Center, Inc. All rights reserved.
4 *
5 */
6
7 #include <linux/device.h>
8 #include <linux/interconnect.h>
9 #include <linux/interconnect-provider.h>
10 #include <linux/module.h>
11 #include <linux/platform_device.h>
12 #include <dt-bindings/interconnect/qcom,qdu1000-rpmh.h>
13
14 #include "bcm-voter.h"
15 #include "icc-common.h"
16 #include "icc-rpmh.h"
17
18 static struct qcom_icc_node qup0_core_master;
19 static struct qcom_icc_node qup1_core_master;
20 static struct qcom_icc_node alm_sys_tcu;
21 static struct qcom_icc_node chm_apps;
22 static struct qcom_icc_node qnm_ecpri_dma;
23 static struct qcom_icc_node qnm_fec_2_gemnoc;
24 static struct qcom_icc_node qnm_pcie;
25 static struct qcom_icc_node qnm_snoc_gc;
26 static struct qcom_icc_node qnm_snoc_sf;
27 static struct qcom_icc_node qxm_mdsp;
28 static struct qcom_icc_node llcc_mc;
29 static struct qcom_icc_node qhm_gic;
30 static struct qcom_icc_node qhm_qdss_bam;
31 static struct qcom_icc_node qhm_qpic;
32 static struct qcom_icc_node qhm_qspi;
33 static struct qcom_icc_node qhm_qup0;
34 static struct qcom_icc_node qhm_qup1;
35 static struct qcom_icc_node qhm_system_noc_cfg;
36 static struct qcom_icc_node qnm_aggre_noc;
37 static struct qcom_icc_node qnm_aggre_noc_gsi;
38 static struct qcom_icc_node qnm_gemnoc_cnoc;
39 static struct qcom_icc_node qnm_gemnoc_modem_slave;
40 static struct qcom_icc_node qnm_gemnoc_pcie;
41 static struct qcom_icc_node qxm_crypto;
42 static struct qcom_icc_node qxm_ecpri_gsi;
43 static struct qcom_icc_node qxm_pimem;
44 static struct qcom_icc_node xm_ecpri_dma;
45 static struct qcom_icc_node xm_gic;
46 static struct qcom_icc_node xm_pcie;
47 static struct qcom_icc_node xm_qdss_etr0;
48 static struct qcom_icc_node xm_qdss_etr1;
49 static struct qcom_icc_node xm_sdc;
50 static struct qcom_icc_node xm_usb3;
51 static struct qcom_icc_node qup0_core_slave;
52 static struct qcom_icc_node qup1_core_slave;
53 static struct qcom_icc_node qns_gem_noc_cnoc;
54 static struct qcom_icc_node qns_llcc;
55 static struct qcom_icc_node qns_modem_slave;
56 static struct qcom_icc_node qns_pcie;
57 static struct qcom_icc_node ebi;
58 static struct qcom_icc_node qhs_ahb2phy0_south;
59 static struct qcom_icc_node qhs_ahb2phy1_north;
60 static struct qcom_icc_node qhs_ahb2phy2_east;
61 static struct qcom_icc_node qhs_aoss;
62 static struct qcom_icc_node qhs_clk_ctl;
63 static struct qcom_icc_node qhs_cpr_cx;
64 static struct qcom_icc_node qhs_cpr_mx;
65 static struct qcom_icc_node qhs_crypto_cfg;
66 static struct qcom_icc_node qhs_ecpri_cfg;
67 static struct qcom_icc_node qhs_imem_cfg;
68 static struct qcom_icc_node qhs_ipc_router;
69 static struct qcom_icc_node qhs_mss_cfg;
70 static struct qcom_icc_node qhs_pcie_cfg;
71 static struct qcom_icc_node qhs_pdm;
72 static struct qcom_icc_node qhs_pimem_cfg;
73 static struct qcom_icc_node qhs_prng;
74 static struct qcom_icc_node qhs_qdss_cfg;
75 static struct qcom_icc_node qhs_qpic;
76 static struct qcom_icc_node qhs_qspi;
77 static struct qcom_icc_node qhs_qup0;
78 static struct qcom_icc_node qhs_qup1;
79 static struct qcom_icc_node qhs_sdc2;
80 static struct qcom_icc_node qhs_smbus_cfg;
81 static struct qcom_icc_node qhs_system_noc_cfg;
82 static struct qcom_icc_node qhs_tcsr;
83 static struct qcom_icc_node qhs_tlmm;
84 static struct qcom_icc_node qhs_tme_cfg;
85 static struct qcom_icc_node qhs_tsc_cfg;
86 static struct qcom_icc_node qhs_usb3;
87 static struct qcom_icc_node qhs_vsense_ctrl_cfg;
88 static struct qcom_icc_node qns_a1noc_snoc;
89 static struct qcom_icc_node qns_anoc_snoc_gsi;
90 static struct qcom_icc_node qns_ddrss_cfg;
91 static struct qcom_icc_node qns_ecpri_gemnoc;
92 static struct qcom_icc_node qns_gemnoc_gc;
93 static struct qcom_icc_node qns_gemnoc_sf;
94 static struct qcom_icc_node qns_modem;
95 static struct qcom_icc_node qns_pcie_gemnoc;
96 static struct qcom_icc_node qxs_imem;
97 static struct qcom_icc_node qxs_pimem;
98 static struct qcom_icc_node srvc_system_noc;
99 static struct qcom_icc_node xs_ethernet_ss;
100 static struct qcom_icc_node xs_pcie;
101 static struct qcom_icc_node xs_qdss_stm;
102 static struct qcom_icc_node xs_sys_tcu_cfg;
103
104 static struct qcom_icc_node qup0_core_master = {
105 .name = "qup0_core_master",
106 .channels = 1,
107 .buswidth = 4,
108 .num_links = 1,
109 .link_nodes = { &qup0_core_slave },
110 };
111
112 static struct qcom_icc_node qup1_core_master = {
113 .name = "qup1_core_master",
114 .channels = 1,
115 .buswidth = 4,
116 .num_links = 1,
117 .link_nodes = { &qup1_core_slave },
118 };
119
120 static struct qcom_icc_node alm_sys_tcu = {
121 .name = "alm_sys_tcu",
122 .channels = 1,
123 .buswidth = 8,
124 .num_links = 2,
125 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
126 };
127
128 static struct qcom_icc_node chm_apps = {
129 .name = "chm_apps",
130 .channels = 1,
131 .buswidth = 16,
132 .num_links = 4,
133 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
134 &qns_modem_slave, &qns_pcie },
135 };
136
137 static struct qcom_icc_node qnm_ecpri_dma = {
138 .name = "qnm_ecpri_dma",
139 .channels = 2,
140 .buswidth = 32,
141 .num_links = 2,
142 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
143 };
144
145 static struct qcom_icc_node qnm_fec_2_gemnoc = {
146 .name = "qnm_fec_2_gemnoc",
147 .channels = 2,
148 .buswidth = 32,
149 .num_links = 2,
150 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc },
151 };
152
153 static struct qcom_icc_node qnm_pcie = {
154 .name = "qnm_pcie",
155 .channels = 1,
156 .buswidth = 64,
157 .num_links = 3,
158 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
159 &qns_modem_slave },
160 };
161
162 static struct qcom_icc_node qnm_snoc_gc = {
163 .name = "qnm_snoc_gc",
164 .channels = 1,
165 .buswidth = 8,
166 .num_links = 1,
167 .link_nodes = { &qns_llcc },
168 };
169
170 static struct qcom_icc_node qnm_snoc_sf = {
171 .name = "qnm_snoc_sf",
172 .channels = 1,
173 .buswidth = 16,
174 .num_links = 4,
175 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
176 &qns_modem_slave, &qns_pcie },
177 };
178
179 static struct qcom_icc_node qxm_mdsp = {
180 .name = "qxm_mdsp",
181 .channels = 1,
182 .buswidth = 16,
183 .num_links = 3,
184 .link_nodes = { &qns_gem_noc_cnoc, &qns_llcc,
185 &qns_pcie },
186 };
187
188 static struct qcom_icc_node llcc_mc = {
189 .name = "llcc_mc",
190 .channels = 8,
191 .buswidth = 4,
192 .num_links = 1,
193 .link_nodes = { &ebi },
194 };
195
196 static struct qcom_icc_node qhm_gic = {
197 .name = "qhm_gic",
198 .channels = 1,
199 .buswidth = 4,
200 .num_links = 1,
201 .link_nodes = { &qns_gemnoc_sf },
202 };
203
204 static struct qcom_icc_node qhm_qdss_bam = {
205 .name = "qhm_qdss_bam",
206 .channels = 1,
207 .buswidth = 4,
208 .num_links = 1,
209 .link_nodes = { &qns_gemnoc_sf },
210 };
211
212 static struct qcom_icc_node qhm_qpic = {
213 .name = "qhm_qpic",
214 .channels = 1,
215 .buswidth = 4,
216 .num_links = 1,
217 .link_nodes = { &qns_a1noc_snoc },
218 };
219
220 static struct qcom_icc_node qhm_qspi = {
221 .name = "qhm_qspi",
222 .channels = 1,
223 .buswidth = 4,
224 .num_links = 1,
225 .link_nodes = { &qns_a1noc_snoc },
226 };
227
228 static struct qcom_icc_node qhm_qup0 = {
229 .name = "qhm_qup0",
230 .channels = 1,
231 .buswidth = 4,
232 .num_links = 1,
233 .link_nodes = { &qns_a1noc_snoc },
234 };
235
236 static struct qcom_icc_node qhm_qup1 = {
237 .name = "qhm_qup1",
238 .channels = 1,
239 .buswidth = 4,
240 .num_links = 1,
241 .link_nodes = { &qns_a1noc_snoc },
242 };
243
244 static struct qcom_icc_node qhm_system_noc_cfg = {
245 .name = "qhm_system_noc_cfg",
246 .channels = 1,
247 .buswidth = 4,
248 .num_links = 1,
249 .link_nodes = { &srvc_system_noc },
250 };
251
252 static struct qcom_icc_node qnm_aggre_noc = {
253 .name = "qnm_aggre_noc",
254 .channels = 1,
255 .buswidth = 8,
256 .num_links = 1,
257 .link_nodes = { &qns_gemnoc_sf },
258 };
259
260 static struct qcom_icc_node qnm_aggre_noc_gsi = {
261 .name = "qnm_aggre_noc_gsi",
262 .channels = 1,
263 .buswidth = 8,
264 .num_links = 1,
265 .link_nodes = { &qns_gemnoc_gc },
266 };
267
268 static struct qcom_icc_node qnm_gemnoc_cnoc = {
269 .name = "qnm_gemnoc_cnoc",
270 .channels = 1,
271 .buswidth = 16,
272 .num_links = 36,
273 .link_nodes = { &qhs_ahb2phy0_south, &qhs_ahb2phy1_north,
274 &qhs_ahb2phy2_east, &qhs_aoss,
275 &qhs_clk_ctl, &qhs_cpr_cx,
276 &qhs_cpr_mx, &qhs_crypto_cfg,
277 &qhs_ecpri_cfg, &qhs_imem_cfg,
278 &qhs_ipc_router, &qhs_mss_cfg,
279 &qhs_pcie_cfg, &qhs_pdm,
280 &qhs_pimem_cfg, &qhs_prng,
281 &qhs_qdss_cfg, &qhs_qpic,
282 &qhs_qspi, &qhs_qup0,
283 &qhs_qup1, &qhs_sdc2,
284 &qhs_smbus_cfg, &qhs_system_noc_cfg,
285 &qhs_tcsr, &qhs_tlmm,
286 &qhs_tme_cfg, &qhs_tsc_cfg,
287 &qhs_usb3, &qhs_vsense_ctrl_cfg,
288 &qns_ddrss_cfg, &qxs_imem,
289 &qxs_pimem, &xs_ethernet_ss,
290 &xs_qdss_stm, &xs_sys_tcu_cfg },
291 };
292
293 static struct qcom_icc_node qnm_gemnoc_modem_slave = {
294 .name = "qnm_gemnoc_modem_slave",
295 .channels = 1,
296 .buswidth = 16,
297 .num_links = 1,
298 .link_nodes = { &qns_modem },
299 };
300
301 static struct qcom_icc_node qnm_gemnoc_pcie = {
302 .name = "qnm_gemnoc_pcie",
303 .channels = 1,
304 .buswidth = 16,
305 .num_links = 1,
306 .link_nodes = { &xs_pcie },
307 };
308
309 static struct qcom_icc_node qxm_crypto = {
310 .name = "qxm_crypto",
311 .channels = 1,
312 .buswidth = 8,
313 .num_links = 1,
314 .link_nodes = { &qns_a1noc_snoc },
315 };
316
317 static struct qcom_icc_node qxm_ecpri_gsi = {
318 .name = "qxm_ecpri_gsi",
319 .channels = 1,
320 .buswidth = 8,
321 .num_links = 2,
322 .link_nodes = { &qns_anoc_snoc_gsi, &xs_pcie },
323 };
324
325 static struct qcom_icc_node qxm_pimem = {
326 .name = "qxm_pimem",
327 .channels = 1,
328 .buswidth = 8,
329 .num_links = 1,
330 .link_nodes = { &qns_gemnoc_gc },
331 };
332
333 static struct qcom_icc_node xm_ecpri_dma = {
334 .name = "xm_ecpri_dma",
335 .channels = 2,
336 .buswidth = 32,
337 .num_links = 2,
338 .link_nodes = { &qns_ecpri_gemnoc, &xs_pcie },
339 };
340
341 static struct qcom_icc_node xm_gic = {
342 .name = "xm_gic",
343 .channels = 1,
344 .buswidth = 8,
345 .num_links = 1,
346 .link_nodes = { &qns_gemnoc_gc },
347 };
348
349 static struct qcom_icc_node xm_pcie = {
350 .name = "xm_pcie",
351 .channels = 1,
352 .buswidth = 64,
353 .num_links = 1,
354 .link_nodes = { &qns_pcie_gemnoc },
355 };
356
357 static struct qcom_icc_node xm_qdss_etr0 = {
358 .name = "xm_qdss_etr0",
359 .channels = 1,
360 .buswidth = 8,
361 .num_links = 1,
362 .link_nodes = { &qns_gemnoc_sf },
363 };
364
365 static struct qcom_icc_node xm_qdss_etr1 = {
366 .name = "xm_qdss_etr1",
367 .channels = 1,
368 .buswidth = 8,
369 .num_links = 1,
370 .link_nodes = { &qns_gemnoc_sf },
371 };
372
373 static struct qcom_icc_node xm_sdc = {
374 .name = "xm_sdc",
375 .channels = 1,
376 .buswidth = 8,
377 .num_links = 1,
378 .link_nodes = { &qns_a1noc_snoc },
379 };
380
381 static struct qcom_icc_node xm_usb3 = {
382 .name = "xm_usb3",
383 .channels = 1,
384 .buswidth = 8,
385 .num_links = 1,
386 .link_nodes = { &qns_a1noc_snoc },
387 };
388
389 static struct qcom_icc_node qup0_core_slave = {
390 .name = "qup0_core_slave",
391 .channels = 1,
392 .buswidth = 4,
393 };
394
395 static struct qcom_icc_node qup1_core_slave = {
396 .name = "qup1_core_slave",
397 .channels = 1,
398 .buswidth = 4,
399 };
400
401 static struct qcom_icc_node qns_gem_noc_cnoc = {
402 .name = "qns_gem_noc_cnoc",
403 .channels = 1,
404 .buswidth = 16,
405 .num_links = 1,
406 .link_nodes = { &qnm_gemnoc_cnoc },
407 };
408
409 static struct qcom_icc_node qns_llcc = {
410 .name = "qns_llcc",
411 .channels = 8,
412 .buswidth = 16,
413 .num_links = 1,
414 .link_nodes = { &llcc_mc },
415 };
416
417 static struct qcom_icc_node qns_modem_slave = {
418 .name = "qns_modem_slave",
419 .channels = 1,
420 .buswidth = 16,
421 .num_links = 1,
422 .link_nodes = { &qnm_gemnoc_modem_slave },
423 };
424
425 static struct qcom_icc_node qns_pcie = {
426 .name = "qns_pcie",
427 .channels = 1,
428 .buswidth = 16,
429 .num_links = 1,
430 .link_nodes = { &qnm_gemnoc_pcie },
431 };
432
433 static struct qcom_icc_node ebi = {
434 .name = "ebi",
435 .channels = 8,
436 .buswidth = 4,
437 };
438
439 static struct qcom_icc_node qhs_ahb2phy0_south = {
440 .name = "qhs_ahb2phy0_south",
441 .channels = 1,
442 .buswidth = 4,
443 };
444
445 static struct qcom_icc_node qhs_ahb2phy1_north = {
446 .name = "qhs_ahb2phy1_north",
447 .channels = 1,
448 .buswidth = 4,
449 };
450
451 static struct qcom_icc_node qhs_ahb2phy2_east = {
452 .name = "qhs_ahb2phy2_east",
453 .channels = 1,
454 .buswidth = 4,
455 };
456
457 static struct qcom_icc_node qhs_aoss = {
458 .name = "qhs_aoss",
459 .channels = 1,
460 .buswidth = 4,
461 };
462
463 static struct qcom_icc_node qhs_clk_ctl = {
464 .name = "qhs_clk_ctl",
465 .channels = 1,
466 .buswidth = 4,
467 };
468
469 static struct qcom_icc_node qhs_cpr_cx = {
470 .name = "qhs_cpr_cx",
471 .channels = 1,
472 .buswidth = 4,
473 };
474
475 static struct qcom_icc_node qhs_cpr_mx = {
476 .name = "qhs_cpr_mx",
477 .channels = 1,
478 .buswidth = 4,
479 };
480
481 static struct qcom_icc_node qhs_crypto_cfg = {
482 .name = "qhs_crypto_cfg",
483 .channels = 1,
484 .buswidth = 4,
485 };
486
487 static struct qcom_icc_node qhs_ecpri_cfg = {
488 .name = "qhs_ecpri_cfg",
489 .channels = 1,
490 .buswidth = 4,
491 };
492
493 static struct qcom_icc_node qhs_imem_cfg = {
494 .name = "qhs_imem_cfg",
495 .channels = 1,
496 .buswidth = 4,
497 };
498
499 static struct qcom_icc_node qhs_ipc_router = {
500 .name = "qhs_ipc_router",
501 .channels = 1,
502 .buswidth = 4,
503 };
504
505 static struct qcom_icc_node qhs_mss_cfg = {
506 .name = "qhs_mss_cfg",
507 .channels = 1,
508 .buswidth = 4,
509 };
510
511 static struct qcom_icc_node qhs_pcie_cfg = {
512 .name = "qhs_pcie_cfg",
513 .channels = 1,
514 .buswidth = 4,
515 };
516
517 static struct qcom_icc_node qhs_pdm = {
518 .name = "qhs_pdm",
519 .channels = 1,
520 .buswidth = 4,
521 };
522
523 static struct qcom_icc_node qhs_pimem_cfg = {
524 .name = "qhs_pimem_cfg",
525 .channels = 1,
526 .buswidth = 4,
527 };
528
529 static struct qcom_icc_node qhs_prng = {
530 .name = "qhs_prng",
531 .channels = 1,
532 .buswidth = 4,
533 };
534
535 static struct qcom_icc_node qhs_qdss_cfg = {
536 .name = "qhs_qdss_cfg",
537 .channels = 1,
538 .buswidth = 4,
539 };
540
541 static struct qcom_icc_node qhs_qpic = {
542 .name = "qhs_qpic",
543 .channels = 1,
544 .buswidth = 4,
545 };
546
547 static struct qcom_icc_node qhs_qspi = {
548 .name = "qhs_qspi",
549 .channels = 1,
550 .buswidth = 4,
551 };
552
553 static struct qcom_icc_node qhs_qup0 = {
554 .name = "qhs_qup0",
555 .channels = 1,
556 .buswidth = 4,
557 };
558
559 static struct qcom_icc_node qhs_qup1 = {
560 .name = "qhs_qup1",
561 .channels = 1,
562 .buswidth = 4,
563 };
564
565 static struct qcom_icc_node qhs_sdc2 = {
566 .name = "qhs_sdc2",
567 .channels = 1,
568 .buswidth = 4,
569 };
570
571 static struct qcom_icc_node qhs_smbus_cfg = {
572 .name = "qhs_smbus_cfg",
573 .channels = 1,
574 .buswidth = 4,
575 };
576
577 static struct qcom_icc_node qhs_system_noc_cfg = {
578 .name = "qhs_system_noc_cfg",
579 .channels = 1,
580 .buswidth = 4,
581 .num_links = 1,
582 .link_nodes = { &qhm_system_noc_cfg },
583 };
584
585 static struct qcom_icc_node qhs_tcsr = {
586 .name = "qhs_tcsr",
587 .channels = 1,
588 .buswidth = 4,
589 };
590
591 static struct qcom_icc_node qhs_tlmm = {
592 .name = "qhs_tlmm",
593 .channels = 1,
594 .buswidth = 4,
595 };
596
597 static struct qcom_icc_node qhs_tme_cfg = {
598 .name = "qhs_tme_cfg",
599 .channels = 1,
600 .buswidth = 4,
601 };
602
603 static struct qcom_icc_node qhs_tsc_cfg = {
604 .name = "qhs_tsc_cfg",
605 .channels = 1,
606 .buswidth = 4,
607 };
608
609 static struct qcom_icc_node qhs_usb3 = {
610 .name = "qhs_usb3",
611 .channels = 1,
612 .buswidth = 4,
613 };
614
615 static struct qcom_icc_node qhs_vsense_ctrl_cfg = {
616 .name = "qhs_vsense_ctrl_cfg",
617 .channels = 1,
618 .buswidth = 4,
619 };
620
621 static struct qcom_icc_node qns_a1noc_snoc = {
622 .name = "qns_a1noc_snoc",
623 .channels = 1,
624 .buswidth = 8,
625 .num_links = 1,
626 .link_nodes = { &qnm_aggre_noc },
627 };
628
629 static struct qcom_icc_node qns_anoc_snoc_gsi = {
630 .name = "qns_anoc_snoc_gsi",
631 .channels = 1,
632 .buswidth = 8,
633 .num_links = 1,
634 .link_nodes = { &qnm_aggre_noc_gsi },
635 };
636
637 static struct qcom_icc_node qns_ddrss_cfg = {
638 .name = "qns_ddrss_cfg",
639 .channels = 1,
640 .buswidth = 4,
641 };
642
643 static struct qcom_icc_node qns_ecpri_gemnoc = {
644 .name = "qns_ecpri_gemnoc",
645 .channels = 2,
646 .buswidth = 32,
647 .num_links = 1,
648 .link_nodes = { &qnm_ecpri_dma },
649 };
650
651 static struct qcom_icc_node qns_gemnoc_gc = {
652 .name = "qns_gemnoc_gc",
653 .channels = 1,
654 .buswidth = 8,
655 .num_links = 1,
656 .link_nodes = { &qnm_snoc_gc },
657 };
658
659 static struct qcom_icc_node qns_gemnoc_sf = {
660 .name = "qns_gemnoc_sf",
661 .channels = 1,
662 .buswidth = 16,
663 .num_links = 1,
664 .link_nodes = { &qnm_snoc_sf },
665 };
666
667 static struct qcom_icc_node qns_modem = {
668 .name = "qns_modem",
669 .channels = 1,
670 .buswidth = 32,
671 };
672
673 static struct qcom_icc_node qns_pcie_gemnoc = {
674 .name = "qns_pcie_gemnoc",
675 .channels = 1,
676 .buswidth = 64,
677 .num_links = 1,
678 .link_nodes = { &qnm_pcie },
679 };
680
681 static struct qcom_icc_node qxs_imem = {
682 .name = "qxs_imem",
683 .channels = 1,
684 .buswidth = 8,
685 };
686
687 static struct qcom_icc_node qxs_pimem = {
688 .name = "qxs_pimem",
689 .channels = 1,
690 .buswidth = 8,
691 };
692
693 static struct qcom_icc_node srvc_system_noc = {
694 .name = "srvc_system_noc",
695 .channels = 1,
696 .buswidth = 4,
697 };
698
699 static struct qcom_icc_node xs_ethernet_ss = {
700 .name = "xs_ethernet_ss",
701 .channels = 1,
702 .buswidth = 32,
703 };
704
705 static struct qcom_icc_node xs_pcie = {
706 .name = "xs_pcie",
707 .channels = 1,
708 .buswidth = 64,
709 };
710
711 static struct qcom_icc_node xs_qdss_stm = {
712 .name = "xs_qdss_stm",
713 .channels = 1,
714 .buswidth = 4,
715 };
716
717 static struct qcom_icc_node xs_sys_tcu_cfg = {
718 .name = "xs_sys_tcu_cfg",
719 .channels = 1,
720 .buswidth = 8,
721 };
722
723 static struct qcom_icc_bcm bcm_acv = {
724 .name = "ACV",
725 .enable_mask = BIT(3),
726 .num_nodes = 1,
727 .nodes = { &ebi },
728 };
729
730 static struct qcom_icc_bcm bcm_ce0 = {
731 .name = "CE0",
732 .num_nodes = 1,
733 .nodes = { &qxm_crypto },
734 };
735
736 static struct qcom_icc_bcm bcm_cn0 = {
737 .name = "CN0",
738 .num_nodes = 44,
739 .nodes = { &qhm_qpic, &qhm_qspi,
740 &qnm_gemnoc_cnoc, &qnm_gemnoc_modem_slave,
741 &qnm_gemnoc_pcie, &xm_sdc,
742 &xm_usb3, &qhs_ahb2phy0_south,
743 &qhs_ahb2phy1_north, &qhs_ahb2phy2_east,
744 &qhs_aoss, &qhs_clk_ctl,
745 &qhs_cpr_cx, &qhs_cpr_mx,
746 &qhs_crypto_cfg, &qhs_ecpri_cfg,
747 &qhs_imem_cfg, &qhs_ipc_router,
748 &qhs_mss_cfg, &qhs_pcie_cfg,
749 &qhs_pdm, &qhs_pimem_cfg,
750 &qhs_prng, &qhs_qdss_cfg,
751 &qhs_qpic, &qhs_qspi,
752 &qhs_qup0, &qhs_qup1,
753 &qhs_sdc2, &qhs_smbus_cfg,
754 &qhs_system_noc_cfg, &qhs_tcsr,
755 &qhs_tlmm, &qhs_tme_cfg,
756 &qhs_tsc_cfg, &qhs_usb3,
757 &qhs_vsense_ctrl_cfg, &qns_ddrss_cfg,
758 &qns_modem, &qxs_imem,
759 &qxs_pimem, &xs_ethernet_ss,
760 &xs_qdss_stm, &xs_sys_tcu_cfg
761 },
762 };
763
764 static struct qcom_icc_bcm bcm_mc0 = {
765 .name = "MC0",
766 .num_nodes = 1,
767 .nodes = { &ebi },
768 };
769
770 static struct qcom_icc_bcm bcm_qup0 = {
771 .name = "QUP0",
772 .num_nodes = 2,
773 .nodes = { &qup0_core_slave, &qup1_core_slave },
774 };
775
776 static struct qcom_icc_bcm bcm_sh0 = {
777 .name = "SH0",
778 .num_nodes = 1,
779 .nodes = { &qns_llcc },
780 };
781
782 static struct qcom_icc_bcm bcm_sh1 = {
783 .name = "SH1",
784 .num_nodes = 11,
785 .nodes = { &alm_sys_tcu, &chm_apps,
786 &qnm_ecpri_dma, &qnm_fec_2_gemnoc,
787 &qnm_pcie, &qnm_snoc_gc,
788 &qnm_snoc_sf, &qxm_mdsp,
789 &qns_gem_noc_cnoc, &qns_modem_slave,
790 &qns_pcie
791 },
792 };
793
794 static struct qcom_icc_bcm bcm_sn0 = {
795 .name = "SN0",
796 .num_nodes = 1,
797 .nodes = { &qns_gemnoc_sf },
798 };
799
800 static struct qcom_icc_bcm bcm_sn1 = {
801 .name = "SN1",
802 .num_nodes = 6,
803 .nodes = { &qhm_gic, &qxm_pimem,
804 &xm_gic, &xm_qdss_etr0,
805 &xm_qdss_etr1, &qns_gemnoc_gc
806 },
807 };
808
809 static struct qcom_icc_bcm bcm_sn2 = {
810 .name = "SN2",
811 .num_nodes = 5,
812 .nodes = { &qnm_aggre_noc, &qxm_ecpri_gsi,
813 &xm_ecpri_dma, &qns_anoc_snoc_gsi,
814 &qns_ecpri_gemnoc
815 },
816 };
817
818 static struct qcom_icc_bcm bcm_sn7 = {
819 .name = "SN7",
820 .num_nodes = 2,
821 .nodes = { &qns_pcie_gemnoc, &xs_pcie },
822 };
823
824 static struct qcom_icc_bcm * const clk_virt_bcms[] = {
825 &bcm_qup0,
826 };
827
828 static struct qcom_icc_node * const clk_virt_nodes[] = {
829 [MASTER_QUP_CORE_0] = &qup0_core_master,
830 [MASTER_QUP_CORE_1] = &qup1_core_master,
831 [SLAVE_QUP_CORE_0] = &qup0_core_slave,
832 [SLAVE_QUP_CORE_1] = &qup1_core_slave,
833 };
834
835 static const struct qcom_icc_desc qdu1000_clk_virt = {
836 .nodes = clk_virt_nodes,
837 .num_nodes = ARRAY_SIZE(clk_virt_nodes),
838 .bcms = clk_virt_bcms,
839 .num_bcms = ARRAY_SIZE(clk_virt_bcms),
840 };
841
842 static struct qcom_icc_bcm * const gem_noc_bcms[] = {
843 &bcm_sh0,
844 &bcm_sh1,
845 };
846
847 static struct qcom_icc_node * const gem_noc_nodes[] = {
848 [MASTER_SYS_TCU] = &alm_sys_tcu,
849 [MASTER_APPSS_PROC] = &chm_apps,
850 [MASTER_GEMNOC_ECPRI_DMA] = &qnm_ecpri_dma,
851 [MASTER_FEC_2_GEMNOC] = &qnm_fec_2_gemnoc,
852 [MASTER_ANOC_PCIE_GEM_NOC] = &qnm_pcie,
853 [MASTER_SNOC_GC_MEM_NOC] = &qnm_snoc_gc,
854 [MASTER_SNOC_SF_MEM_NOC] = &qnm_snoc_sf,
855 [MASTER_MSS_PROC] = &qxm_mdsp,
856 [SLAVE_GEM_NOC_CNOC] = &qns_gem_noc_cnoc,
857 [SLAVE_LLCC] = &qns_llcc,
858 [SLAVE_GEMNOC_MODEM_CNOC] = &qns_modem_slave,
859 [SLAVE_MEM_NOC_PCIE_SNOC] = &qns_pcie,
860 };
861
862 static const struct qcom_icc_desc qdu1000_gem_noc = {
863 .nodes = gem_noc_nodes,
864 .num_nodes = ARRAY_SIZE(gem_noc_nodes),
865 .bcms = gem_noc_bcms,
866 .num_bcms = ARRAY_SIZE(gem_noc_bcms),
867 };
868
869 static struct qcom_icc_bcm * const mc_virt_bcms[] = {
870 &bcm_acv,
871 &bcm_mc0,
872 };
873
874 static struct qcom_icc_node * const mc_virt_nodes[] = {
875 [MASTER_LLCC] = &llcc_mc,
876 [SLAVE_EBI1] = &ebi,
877 };
878
879 static const struct qcom_icc_desc qdu1000_mc_virt = {
880 .nodes = mc_virt_nodes,
881 .num_nodes = ARRAY_SIZE(mc_virt_nodes),
882 .bcms = mc_virt_bcms,
883 .num_bcms = ARRAY_SIZE(mc_virt_bcms),
884 };
885
886 static struct qcom_icc_bcm * const system_noc_bcms[] = {
887 &bcm_ce0,
888 &bcm_cn0,
889 &bcm_sn0,
890 &bcm_sn1,
891 &bcm_sn2,
892 &bcm_sn7,
893 };
894
895 static struct qcom_icc_node * const system_noc_nodes[] = {
896 [MASTER_GIC_AHB] = &qhm_gic,
897 [MASTER_QDSS_BAM] = &qhm_qdss_bam,
898 [MASTER_QPIC] = &qhm_qpic,
899 [MASTER_QSPI_0] = &qhm_qspi,
900 [MASTER_QUP_0] = &qhm_qup0,
901 [MASTER_QUP_1] = &qhm_qup1,
902 [MASTER_SNOC_CFG] = &qhm_system_noc_cfg,
903 [MASTER_ANOC_SNOC] = &qnm_aggre_noc,
904 [MASTER_ANOC_GSI] = &qnm_aggre_noc_gsi,
905 [MASTER_GEM_NOC_CNOC] = &qnm_gemnoc_cnoc,
906 [MASTER_GEMNOC_MODEM_CNOC] = &qnm_gemnoc_modem_slave,
907 [MASTER_GEM_NOC_PCIE_SNOC] = &qnm_gemnoc_pcie,
908 [MASTER_CRYPTO] = &qxm_crypto,
909 [MASTER_ECPRI_GSI] = &qxm_ecpri_gsi,
910 [MASTER_PIMEM] = &qxm_pimem,
911 [MASTER_SNOC_ECPRI_DMA] = &xm_ecpri_dma,
912 [MASTER_GIC] = &xm_gic,
913 [MASTER_PCIE] = &xm_pcie,
914 [MASTER_QDSS_ETR] = &xm_qdss_etr0,
915 [MASTER_QDSS_ETR_1] = &xm_qdss_etr1,
916 [MASTER_SDCC_1] = &xm_sdc,
917 [MASTER_USB3] = &xm_usb3,
918 [SLAVE_AHB2PHY_SOUTH] = &qhs_ahb2phy0_south,
919 [SLAVE_AHB2PHY_NORTH] = &qhs_ahb2phy1_north,
920 [SLAVE_AHB2PHY_EAST] = &qhs_ahb2phy2_east,
921 [SLAVE_AOSS] = &qhs_aoss,
922 [SLAVE_CLK_CTL] = &qhs_clk_ctl,
923 [SLAVE_RBCPR_CX_CFG] = &qhs_cpr_cx,
924 [SLAVE_RBCPR_MX_CFG] = &qhs_cpr_mx,
925 [SLAVE_CRYPTO_0_CFG] = &qhs_crypto_cfg,
926 [SLAVE_ECPRI_CFG] = &qhs_ecpri_cfg,
927 [SLAVE_IMEM_CFG] = &qhs_imem_cfg,
928 [SLAVE_IPC_ROUTER_CFG] = &qhs_ipc_router,
929 [SLAVE_CNOC_MSS] = &qhs_mss_cfg,
930 [SLAVE_PCIE_CFG] = &qhs_pcie_cfg,
931 [SLAVE_PDM] = &qhs_pdm,
932 [SLAVE_PIMEM_CFG] = &qhs_pimem_cfg,
933 [SLAVE_PRNG] = &qhs_prng,
934 [SLAVE_QDSS_CFG] = &qhs_qdss_cfg,
935 [SLAVE_QPIC] = &qhs_qpic,
936 [SLAVE_QSPI_0] = &qhs_qspi,
937 [SLAVE_QUP_0] = &qhs_qup0,
938 [SLAVE_QUP_1] = &qhs_qup1,
939 [SLAVE_SDCC_2] = &qhs_sdc2,
940 [SLAVE_SMBUS_CFG] = &qhs_smbus_cfg,
941 [SLAVE_SNOC_CFG] = &qhs_system_noc_cfg,
942 [SLAVE_TCSR] = &qhs_tcsr,
943 [SLAVE_TLMM] = &qhs_tlmm,
944 [SLAVE_TME_CFG] = &qhs_tme_cfg,
945 [SLAVE_TSC_CFG] = &qhs_tsc_cfg,
946 [SLAVE_USB3_0] = &qhs_usb3,
947 [SLAVE_VSENSE_CTRL_CFG] = &qhs_vsense_ctrl_cfg,
948 [SLAVE_A1NOC_SNOC] = &qns_a1noc_snoc,
949 [SLAVE_ANOC_SNOC_GSI] = &qns_anoc_snoc_gsi,
950 [SLAVE_DDRSS_CFG] = &qns_ddrss_cfg,
951 [SLAVE_ECPRI_GEMNOC] = &qns_ecpri_gemnoc,
952 [SLAVE_SNOC_GEM_NOC_GC] = &qns_gemnoc_gc,
953 [SLAVE_SNOC_GEM_NOC_SF] = &qns_gemnoc_sf,
954 [SLAVE_MODEM_OFFLINE] = &qns_modem,
955 [SLAVE_ANOC_PCIE_GEM_NOC] = &qns_pcie_gemnoc,
956 [SLAVE_IMEM] = &qxs_imem,
957 [SLAVE_PIMEM] = &qxs_pimem,
958 [SLAVE_SERVICE_SNOC] = &srvc_system_noc,
959 [SLAVE_ETHERNET_SS] = &xs_ethernet_ss,
960 [SLAVE_PCIE_0] = &xs_pcie,
961 [SLAVE_QDSS_STM] = &xs_qdss_stm,
962 [SLAVE_TCU] = &xs_sys_tcu_cfg,
963 };
964
965 static const struct qcom_icc_desc qdu1000_system_noc = {
966 .nodes = system_noc_nodes,
967 .num_nodes = ARRAY_SIZE(system_noc_nodes),
968 .bcms = system_noc_bcms,
969 .num_bcms = ARRAY_SIZE(system_noc_bcms),
970 };
971
qnoc_probe(struct platform_device * pdev)972 static int qnoc_probe(struct platform_device *pdev)
973 {
974 int ret;
975
976 ret = qcom_icc_rpmh_probe(pdev);
977 if (ret)
978 dev_err(&pdev->dev, "failed to register ICC provider\n");
979
980 return ret;
981 }
982
983 static const struct of_device_id qnoc_of_match[] = {
984 { .compatible = "qcom,qdu1000-clk-virt",
985 .data = &qdu1000_clk_virt
986 },
987 { .compatible = "qcom,qdu1000-gem-noc",
988 .data = &qdu1000_gem_noc
989 },
990 { .compatible = "qcom,qdu1000-mc-virt",
991 .data = &qdu1000_mc_virt
992 },
993 { .compatible = "qcom,qdu1000-system-noc",
994 .data = &qdu1000_system_noc
995 },
996 { }
997 };
998 MODULE_DEVICE_TABLE(of, qnoc_of_match);
999
1000 static struct platform_driver qnoc_driver = {
1001 .probe = qnoc_probe,
1002 .remove = qcom_icc_rpmh_remove,
1003 .driver = {
1004 .name = "qnoc-qdu1000",
1005 .of_match_table = qnoc_of_match,
1006 },
1007 };
1008
qnoc_driver_init(void)1009 static int __init qnoc_driver_init(void)
1010 {
1011 return platform_driver_register(&qnoc_driver);
1012 }
1013 core_initcall(qnoc_driver_init);
1014
qnoc_driver_exit(void)1015 static void __exit qnoc_driver_exit(void)
1016 {
1017 platform_driver_unregister(&qnoc_driver);
1018 }
1019 module_exit(qnoc_driver_exit);
1020
1021 MODULE_DESCRIPTION("QDU1000 NoC driver");
1022 MODULE_LICENSE("GPL");
1023