1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
21
22 #include "phy-qcom-qmp-common.h"
23
24 #include "phy-qcom-qmp.h"
25 #include "phy-qcom-qmp-pcs-misc-v3.h"
26 #include "phy-qcom-qmp-pcs-misc-v4.h"
27 #include "phy-qcom-qmp-pcs-usb-v4.h"
28 #include "phy-qcom-qmp-pcs-usb-v5.h"
29 #include "phy-qcom-qmp-pcs-usb-v6.h"
30 #include "phy-qcom-qmp-pcs-usb-v7.h"
31
32 #define PHY_INIT_COMPLETE_TIMEOUT 10000
33
34 /* set of registers with offsets different per-PHY */
35 enum qphy_reg_layout {
36 /* PCS registers */
37 QPHY_SW_RESET,
38 QPHY_START_CTRL,
39 QPHY_PCS_STATUS,
40 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
41 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
42 QPHY_PCS_POWER_DOWN_CONTROL,
43 QPHY_PCS_MISC_CLAMP_ENABLE,
44 /* Keep last to ensure regs_layout arrays are properly initialized */
45 QPHY_LAYOUT_SIZE
46 };
47
48 static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
49 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET,
50 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL,
51 [QPHY_PCS_STATUS] = QPHY_V2_PCS_USB_PCS_STATUS,
52 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL,
53 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR,
54 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL,
55 };
56
57 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
58 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
59 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
60 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
61 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
62 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
63 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
64 [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V3_PCS_MISC_CLAMP_ENABLE,
65 };
66
67 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
68 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
69 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
70 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
71 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
72
73 /* In PCS_USB */
74 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
75 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
76 [QPHY_PCS_MISC_CLAMP_ENABLE] = QPHY_V4_PCS_MISC_CLAMP_ENABLE,
77 };
78
79 static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
80 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
81 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
82 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
83 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
84
85 /* In PCS_USB */
86 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
87 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
88 };
89
90 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
91 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET,
92 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL,
93 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1,
94 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,
95
96 /* In PCS_USB */
97 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
98 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
99 };
100
101 static const unsigned int qmp_v7_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
102 [QPHY_SW_RESET] = QPHY_V7_PCS_SW_RESET,
103 [QPHY_START_CTRL] = QPHY_V7_PCS_START_CONTROL,
104 [QPHY_PCS_STATUS] = QPHY_V7_PCS_PCS_STATUS1,
105 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V7_PCS_POWER_DOWN_CONTROL,
106
107 /* In PCS_USB */
108 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V7_PCS_USB3_AUTONOMOUS_MODE_CTRL,
109 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V7_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
110 };
111
112 static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
113 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
114 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
115 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
116 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
117 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
118 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
119 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
120 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
121 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
122 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
123 /* PLL and Loop filter settings */
124 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
125 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
126 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
127 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
128 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
129 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
130 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
131 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
132 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
133 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
134 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
135 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
136 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
137 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
138 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
139 /* SSC settings */
140 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
141 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
142 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
143 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
144 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
145 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
146 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
147 };
148
149 static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
150 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
151 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
152 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
153 };
154
155 static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
156 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
157 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
158 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
159 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
160 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
161 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
162 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
163 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
164 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
165 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
166 };
167
168 static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
169 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
170 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
171 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
172 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
173 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
174 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
175 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
176 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
177 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
178 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
179 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
180 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
181 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
182 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
183 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
184 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
185 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
186 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
187 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
188 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
189 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
192 };
193
194 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
195 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
196 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
197 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
198 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
199 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
200 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
201 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
202 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
203 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
204 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
205 /* PLL and Loop filter settings */
206 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
207 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
208 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
209 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
210 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
211 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
212 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
213 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
214 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
215 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
216 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
217 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
218 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
219 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
220 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
221 /* SSC settings */
222 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
223 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
224 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
225 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
226 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
227 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
228 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
229 };
230
231 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
232 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
233 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
234 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
235 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
236 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
237 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
238 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
239 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
240 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
241 };
242
243 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
244 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
245 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
246 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
247 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
248 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
249 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
250 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
251 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
252 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
253 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
254 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
255 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
256 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
257 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
258 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
259 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
260 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
261 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
262 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
263 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
264 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
265 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
266 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
267 };
268
269 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
270 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
271 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
272 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
273 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
274 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
275 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
276 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
277 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
278 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
279 /* PLL and Loop filter settings */
280 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
281 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
282 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
283 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
284 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
285 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
286 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
287 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
288 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
289 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
290 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
291 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
292 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
293 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
294 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
295 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
296 /* SSC settings */
297 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
298 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
299 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
300 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
301 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
302 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
303 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
304 };
305
306 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
307 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
308 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
309 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
310 };
311
312 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
313 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
314 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
315 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
316 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
317 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
318 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
319 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
320 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
321 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
322 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
323 };
324
325 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
326 /* FLL settings */
327 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),
328 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),
329 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),
330 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),
331 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),
332
333 /* Lock Det settings */
334 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
335 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
336 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
337 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
338 };
339
340 static const struct qmp_phy_init_tbl qdu1000_usb3_uniphy_pcs_tbl[] = {
341 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xc4),
342 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x89),
343 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
344 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
345 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
346 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
347 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
348 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
349 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
350 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
351 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
352 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
353 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
354 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
355 };
356
357 static const struct qmp_phy_init_tbl qdu1000_usb3_uniphy_pcs_usb_tbl[] = {
358 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
359 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
360 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1, 0x6f),
361 };
362
363 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
364 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
365 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
366 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
367 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
368 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
369 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
370 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
371 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
372 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
373 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
374 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
375 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
376 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
377 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
378 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
379 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
380 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
381 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
382 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
383 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
384 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
385 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
386 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
387 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
388 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
389 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
390 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
391 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
392 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
393 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
394 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
395 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
396 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
397 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
398 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
400 };
401
402 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
403 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
404 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
405 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
406 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
407 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
408 };
409
410 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
411 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
412 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
413 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
414 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
415 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
416 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
417 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
418 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
419 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
420 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
421 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
422 };
423
424 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
425 /* FLL settings */
426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
428 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
429 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
430 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
431
432 /* Lock Det settings */
433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
434 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
435 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
436 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
437
438 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
439 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
440 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
441 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
442 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
443 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
444 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
445 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
446 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
447 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
448 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
449 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
454 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
457
458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
459 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
467 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
469
470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
472 };
473
474 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
475 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
476 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
477 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
478 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
479 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
480 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
481 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
482 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
483 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
484 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
485 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
486 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
487 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
488 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
489 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
490 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
491 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
492 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
493 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
494 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
495 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
496 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
497 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
498 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
499 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
500 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
501 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
502 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
503 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
504 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
505 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
506 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
507 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
508 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
509 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
510 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
511 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
512 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
513 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
514 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
515 };
516
517 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
518 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
519 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
520 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
521 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
522 };
523
524 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
525 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
526 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
527 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
528 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
529 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
530 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
531 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
532 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
533 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
534 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
535 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
536 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
537 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
538 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
539 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
540 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
541 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
542 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
543 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
544 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
545 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
546 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
547 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
548 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
549 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
550 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
551 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
552 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
553 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
554 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
555 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
556 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
557 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
558 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
559 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
560 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
561 };
562
563 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
564 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
565 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
566 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
567 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
568 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
569 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
570 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
571 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
572 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
573 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
574 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
575 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
576 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
577 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
578 };
579
580 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {
581 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
582 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
583 };
584
585 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
586 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
587 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
588 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
589 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
590 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
591 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
592 };
593
594 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
595 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
596 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
597 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
598 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
599 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
600 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
601 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
602 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
603 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
604 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
606 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
607 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
608 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
609 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
610 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
611 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
612 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
613 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
614 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
615 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
616 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
617 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
618 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
619 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
620 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
621 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
622 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
623 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
624 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
625 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
626 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
627 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
628 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
629 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
630 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
631 };
632
633 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
634 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
635 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
636 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
637 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
638 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
639 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
640 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
641 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
642 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
643 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
644 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
645 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
646 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
647 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
648 };
649
650 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {
651 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
652 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
653 };
654
655 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
656 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
657 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
658 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
659 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
660 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
661 };
662
663 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
700 };
701
702 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
703 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
704 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
705 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
706 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
707 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
708 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
709 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
710 };
711
712 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
713 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
714 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
715 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
716 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
717 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
718 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
719 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
720 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
721 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
722 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
723 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
724 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
725 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
726 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
727 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
728 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
729 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
730 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
731 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
732 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
733 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
734 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
735 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
736 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
737 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
738 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
739 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
740 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
741 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
742 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
743 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
744 };
745
746 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_serdes_tbl[] = {
747 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x9e),
748 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x06),
749 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
750 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
751 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
752 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
753 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e),
754 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82),
755 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82),
756 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0xab),
757 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xea),
758 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x02),
759 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
760 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
761 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
762 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7),
763 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
764 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7),
765 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
766 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x9e),
767 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x06),
768 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
769 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
770 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
771 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12),
772 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34),
773 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
774 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0xab),
775 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xea),
776 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x02),
777 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
778 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
779 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
780 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
781 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31),
782 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01),
783 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a),
784 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
785 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
786 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
787 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
788 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
789 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
790 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
791 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
792 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
793 };
794
795 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_tx_tbl[] = {
796 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
797 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
798 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
799 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
800 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
801 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
802 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
803 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
804 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),
805 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PI_QEC_CTRL, 0x21),
806 };
807
808 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_rx_tbl[] = {
809 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),
810 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),
811 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
812 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
813 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
814 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
815 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),
816 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
817 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
818 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),
819 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),
820 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
821 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),
822 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
823 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),
824 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
825 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
826 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
827 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
828 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
829 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
830 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),
831 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
832 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f),
833 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf),
834 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff),
835 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf),
836 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed),
837 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
838 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
839 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
840 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),
841 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),
842 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),
843 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
844 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),
845 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),
846 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),
847 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
848 };
849
850 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_tbl[] = {
851 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
852 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
853 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
854 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
855 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
856 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0xaa),
857 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
858 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
859 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),
860 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),
861 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),
862 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
863 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),
864 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),
865 };
866
867 static const struct qmp_phy_init_tbl sdx75_usb3_uniphy_pcs_usb_tbl[] = {
868 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
869 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
870 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
871 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
872 };
873
874 static const struct qmp_phy_init_tbl qcs8300_usb3_uniphy_tx_tbl[] = {
875 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
876 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0xf2),
877 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
878 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
879 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
880 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
881 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
882 };
883
884 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
885 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
886 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
887 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
888 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
889 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
890 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
891 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
892 };
893
894 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
895 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
896 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
897 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
898 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
899 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
900 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
901 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
902 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
903 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
904 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
905 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
906 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
907 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
908 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
909 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
910 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
911 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
912 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
913 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
914 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
915 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
916 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
917 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
918 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
919 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
920 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
921 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
922 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
923 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
924 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
925 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
926 };
927
928 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
929 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
930 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
931 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
932 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
933 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
934 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
935 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
936 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
937 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
938 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
939 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
940 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
941 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
942 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
943 };
944
945 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {
946 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
947 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
948 };
949
950 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {
951 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
952 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
953 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
954 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
955 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab),
956 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea),
957 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02),
958 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
959 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
960 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
961 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
962 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
963 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
964 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
965 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
966 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
967 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
968 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02),
969 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24),
970 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
971 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82),
972 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
973 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea),
974 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
975 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
976 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
977 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
978 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
979 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
980 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
981 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
982 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
983 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
984 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
985 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde),
986 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07),
987 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
988 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
989 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
990 };
991
992 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = {
993 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
994 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
995 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
996 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
997 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
998 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
999 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1000 };
1001
1002 static const struct qmp_phy_init_tbl qcs8300_usb3_uniphy_rx_tbl[] = {
1003 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xec),
1004 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1005 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0x7f),
1006 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x3f),
1007 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0x3f),
1008 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1009 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1010 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1011 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1012 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1013 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1014 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1015 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1016 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1017 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1018 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1019 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1020 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1021 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x09),
1022 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1023 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1024 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1025 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1026 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1027 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1028 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1029 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1030 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1031 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x06),
1032 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x19),
1033 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1034 };
1035
1036 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = {
1037 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1038 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1039 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1040 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1041 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1042 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1043 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1044 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1045 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1046 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1047 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1048 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1049 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1050 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1051 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1052 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1053 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1054 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1055 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
1056 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1057 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1058 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1059 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1060 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1061 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1062 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1063 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1064 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1065 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1066 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1067 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1068 };
1069
1070 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = {
1071 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1072 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1073 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1074 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1075 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1076 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1077 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1078 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1079 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1080 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1081 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1082 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1083 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1084 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1085 };
1086
1087 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_usb_tbl[] = {
1088 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1089 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1090 };
1091
1092 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = {
1093 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1094 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x89),
1095 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1096 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1097 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1098 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1099 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1100 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1101 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1102 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1103 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1104 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1105 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1106 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1107 };
1108
1109 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_usb_tbl[] = {
1110 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1111 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1112 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f),
1113 };
1114
1115 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_serdes_tbl[] = {
1116 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
1117 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE1, 0x01),
1118 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE1, 0x02),
1119 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE1, 0x16),
1120 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE1, 0x36),
1121 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORECLK_DIV_MODE1, 0x04),
1122 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE1, 0x16),
1123 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE1, 0x41),
1124 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE1, 0x41),
1125 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE1, 0x55),
1126 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE1, 0x75),
1127 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE1, 0x01),
1128 QMP_PHY_INIT_CFG(QSERDES_V7_COM_HSCLK_SEL_1, 0x01),
1129 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE1, 0x25),
1130 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE1, 0x02),
1131 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
1132 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
1133 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
1134 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
1135 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
1136 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1137 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CP_CTRL_MODE0, 0x02),
1138 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_RCTRL_MODE0, 0x16),
1139 QMP_PHY_INIT_CFG(QSERDES_V7_COM_PLL_CCTRL_MODE0, 0x36),
1140 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP1_MODE0, 0x08),
1141 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP2_MODE0, 0x1a),
1142 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DEC_START_MODE0, 0x41),
1143 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START1_MODE0, 0x55),
1144 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START2_MODE0, 0x75),
1145 QMP_PHY_INIT_CFG(QSERDES_V7_COM_DIV_FRAC_START3_MODE0, 0x01),
1146 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE1_MODE0, 0x25),
1147 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE2_MODE0, 0x02),
1148 QMP_PHY_INIT_CFG(QSERDES_V7_COM_BG_TIMER, 0x0a),
1149 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_EN_CENTER, 0x01),
1150 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER1, 0x62),
1151 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SSC_PER2, 0x02),
1152 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_BUF_ENABLE, 0x0a),
1153 QMP_PHY_INIT_CFG(QSERDES_V7_COM_SYSCLK_EN_SEL, 0x1a),
1154 QMP_PHY_INIT_CFG(QSERDES_V7_COM_LOCK_CMP_CFG, 0x14),
1155 QMP_PHY_INIT_CFG(QSERDES_V7_COM_VCO_TUNE_MAP, 0x04),
1156 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CORE_CLK_EN, 0x20),
1157 QMP_PHY_INIT_CFG(QSERDES_V7_COM_CMN_CONFIG_1, 0x16),
1158 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
1159 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
1160 QMP_PHY_INIT_CFG(QSERDES_V7_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
1161 QMP_PHY_INIT_CFG(QSERDES_V7_COM_ADDITIONAL_MISC, 0x0c),
1162 };
1163
1164 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_tx_tbl[] = {
1165 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_TX, 0x00),
1166 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_RX, 0x00),
1167 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1168 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
1169 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_1, 0xf5),
1170 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_3, 0x3f),
1171 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_4, 0x3f),
1172 QMP_PHY_INIT_CFG(QSERDES_V7_TX_LANE_MODE_5, 0x5f),
1173 QMP_PHY_INIT_CFG(QSERDES_V7_TX_RCV_DETECT_LVL_2, 0x12),
1174 QMP_PHY_INIT_CFG(QSERDES_V7_TX_PI_QEC_CTRL, 0x21),
1175 };
1176
1177 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_rx_tbl[] = {
1178 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FO_GAIN, 0x0a),
1179 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_GAIN, 0x06),
1180 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1181 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1182 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1183 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1184 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_PI_CONTROLS, 0x99),
1185 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH1, 0x08),
1186 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_THRESH2, 0x08),
1187 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN1, 0x00),
1188 QMP_PHY_INIT_CFG(QSERDES_V7_RX_UCDR_SB2_GAIN2, 0x0a),
1189 QMP_PHY_INIT_CFG(QSERDES_V7_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1190 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL1, 0x54),
1191 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VGA_CAL_CNTRL2, 0x0f),
1192 QMP_PHY_INIT_CFG(QSERDES_V7_RX_GM_CAL, 0x13),
1193 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1194 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1195 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1196 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_LOW, 0x07),
1197 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1198 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1199 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CNTRL, 0x04),
1200 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1201 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_LOW, 0x3f),
1202 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH, 0xbf),
1203 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH2, 0xff),
1204 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH3, 0xdf),
1205 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_00_HIGH4, 0xed),
1206 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_LOW, 0xdc),
1207 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH, 0x5c),
1208 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH2, 0x9c),
1209 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH3, 0x1d),
1210 QMP_PHY_INIT_CFG(QSERDES_V7_RX_RX_MODE_01_HIGH4, 0x09),
1211 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_EN_TIMER, 0x04),
1212 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1213 QMP_PHY_INIT_CFG(QSERDES_V7_RX_DCC_CTRL1, 0x0c),
1214 QMP_PHY_INIT_CFG(QSERDES_V7_RX_VTH_CODE, 0x10),
1215 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_CTRL1, 0x14),
1216 QMP_PHY_INIT_CFG(QSERDES_V7_RX_SIGDET_CAL_TRIM, 0x08),
1217 };
1218
1219 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_tbl[] = {
1220 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1221 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG2, 0x89),
1222 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG3, 0x20),
1223 QMP_PHY_INIT_CFG(QPHY_V7_PCS_LOCK_DETECT_CONFIG6, 0x13),
1224 QMP_PHY_INIT_CFG(QPHY_V7_PCS_REFGEN_REQ_CONFIG1, 0x21),
1225 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RX_SIGDET_LVL, 0xaa),
1226 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1227 QMP_PHY_INIT_CFG(QPHY_V7_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1228 QMP_PHY_INIT_CFG(QPHY_V7_PCS_CDR_RESET_TIME, 0x0a),
1229 QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1230 QMP_PHY_INIT_CFG(QPHY_V7_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1231 QMP_PHY_INIT_CFG(QPHY_V7_PCS_PCS_TX_RX_CONFIG, 0x0c),
1232 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG1, 0x4b),
1233 QMP_PHY_INIT_CFG(QPHY_V7_PCS_EQ_CONFIG5, 0x10),
1234 };
1235
1236 static const struct qmp_phy_init_tbl x1e80100_usb3_uniphy_pcs_usb_tbl[] = {
1237 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1238 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1239 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
1240 QMP_PHY_INIT_CFG(QPHY_V7_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
1241 };
1242
1243 struct qmp_usb_offsets {
1244 u16 serdes;
1245 u16 pcs;
1246 u16 pcs_misc;
1247 u16 pcs_usb;
1248 u16 tx;
1249 u16 rx;
1250 };
1251
1252 /* struct qmp_phy_cfg - per-PHY initialization config */
1253 struct qmp_phy_cfg {
1254 const struct qmp_usb_offsets *offsets;
1255
1256 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1257 const struct qmp_phy_init_tbl *serdes_tbl;
1258 int serdes_tbl_num;
1259 const struct qmp_phy_init_tbl *tx_tbl;
1260 int tx_tbl_num;
1261 const struct qmp_phy_init_tbl *rx_tbl;
1262 int rx_tbl_num;
1263 const struct qmp_phy_init_tbl *pcs_tbl;
1264 int pcs_tbl_num;
1265 const struct qmp_phy_init_tbl *pcs_usb_tbl;
1266 int pcs_usb_tbl_num;
1267
1268 /* regulators to be requested */
1269 const char * const *vreg_list;
1270 int num_vregs;
1271
1272 /* array of registers with different offsets */
1273 const unsigned int *regs;
1274
1275 /* true, if PHY needs delay after POWER_DOWN */
1276 bool has_pwrdn_delay;
1277
1278 /* Offset from PCS to PCS_USB region */
1279 unsigned int pcs_usb_offset;
1280 };
1281
1282 struct qmp_usb {
1283 struct device *dev;
1284
1285 const struct qmp_phy_cfg *cfg;
1286
1287 void __iomem *serdes;
1288 void __iomem *pcs;
1289 void __iomem *pcs_misc;
1290 void __iomem *pcs_usb;
1291 void __iomem *tx;
1292 void __iomem *rx;
1293
1294 struct clk *pipe_clk;
1295 struct clk_bulk_data *clks;
1296 int num_clks;
1297 int num_resets;
1298 struct reset_control_bulk_data *resets;
1299 struct regulator_bulk_data *vregs;
1300
1301 enum phy_mode mode;
1302
1303 struct phy *phy;
1304
1305 struct clk_fixed_rate pipe_clk_fixed;
1306 };
1307
qphy_setbits(void __iomem * base,u32 offset,u32 val)1308 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1309 {
1310 u32 reg;
1311
1312 reg = readl(base + offset);
1313 reg |= val;
1314 writel(reg, base + offset);
1315
1316 /* ensure that above write is through */
1317 readl(base + offset);
1318 }
1319
qphy_clrbits(void __iomem * base,u32 offset,u32 val)1320 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1321 {
1322 u32 reg;
1323
1324 reg = readl(base + offset);
1325 reg &= ~val;
1326 writel(reg, base + offset);
1327
1328 /* ensure that above write is through */
1329 readl(base + offset);
1330 }
1331
1332 /* list of clocks required by phy */
1333 static const char * const qmp_usb_phy_clk_l[] = {
1334 "aux", "cfg_ahb", "ref", "com_aux",
1335 };
1336
1337 /* list of resets */
1338 static const char * const usb3phy_legacy_reset_l[] = {
1339 "phy", "common",
1340 };
1341
1342 static const char * const usb3phy_reset_l[] = {
1343 "phy_phy", "phy",
1344 };
1345
1346 /* list of regulators */
1347 static const char * const qmp_phy_vreg_l[] = {
1348 "vdda-phy", "vdda-pll",
1349 };
1350
1351 static const struct qmp_usb_offsets qmp_usb_offsets_v3 = {
1352 .serdes = 0,
1353 .pcs = 0x800,
1354 .pcs_misc = 0x600,
1355 .tx = 0x200,
1356 .rx = 0x400,
1357 };
1358
1359 static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
1360 .serdes = 0,
1361 .pcs = 0x800,
1362 .pcs_usb = 0x800,
1363 .tx = 0x200,
1364 .rx = 0x400,
1365 };
1366
1367 static const struct qmp_usb_offsets qmp_usb_offsets_v3_msm8996 = {
1368 .serdes = 0,
1369 .pcs = 0x600,
1370 .tx = 0x200,
1371 .rx = 0x400,
1372 };
1373
1374 static const struct qmp_usb_offsets qmp_usb_offsets_v4 = {
1375 .serdes = 0,
1376 .pcs = 0x0800,
1377 .pcs_usb = 0x0e00,
1378 .tx = 0x0200,
1379 .rx = 0x0400,
1380 };
1381
1382 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
1383 .serdes = 0,
1384 .pcs = 0x0200,
1385 .pcs_usb = 0x1200,
1386 .tx = 0x0e00,
1387 .rx = 0x1000,
1388 };
1389
1390 static const struct qmp_usb_offsets qmp_usb_offsets_v6 = {
1391 .serdes = 0,
1392 .pcs = 0x0200,
1393 .pcs_usb = 0x1200,
1394 .tx = 0x0e00,
1395 .rx = 0x1000,
1396 };
1397
1398 static const struct qmp_usb_offsets qmp_usb_offsets_v7 = {
1399 .serdes = 0,
1400 .pcs = 0x0200,
1401 .pcs_usb = 0x1200,
1402 .tx = 0x0e00,
1403 .rx = 0x1000,
1404 };
1405
1406 static const struct qmp_phy_cfg ipq6018_usb3phy_cfg = {
1407 .offsets = &qmp_usb_offsets_v3,
1408
1409 .serdes_tbl = ipq9574_usb3_serdes_tbl,
1410 .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
1411 .tx_tbl = msm8996_usb3_tx_tbl,
1412 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1413 .rx_tbl = ipq8074_usb3_rx_tbl,
1414 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1415 .pcs_tbl = ipq8074_usb3_pcs_tbl,
1416 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1417 .vreg_list = qmp_phy_vreg_l,
1418 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1419 .regs = qmp_v3_usb3phy_regs_layout,
1420 };
1421
1422 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
1423 .offsets = &qmp_usb_offsets_v3,
1424
1425 .serdes_tbl = ipq8074_usb3_serdes_tbl,
1426 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
1427 .tx_tbl = msm8996_usb3_tx_tbl,
1428 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1429 .rx_tbl = ipq8074_usb3_rx_tbl,
1430 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1431 .pcs_tbl = ipq8074_usb3_pcs_tbl,
1432 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1433 .vreg_list = qmp_phy_vreg_l,
1434 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1435 .regs = qmp_v3_usb3phy_regs_layout,
1436 };
1437
1438 static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
1439 .offsets = &qmp_usb_offsets_ipq9574,
1440
1441 .serdes_tbl = ipq9574_usb3_serdes_tbl,
1442 .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
1443 .tx_tbl = ipq9574_usb3_tx_tbl,
1444 .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl),
1445 .rx_tbl = ipq9574_usb3_rx_tbl,
1446 .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl),
1447 .pcs_tbl = ipq9574_usb3_pcs_tbl,
1448 .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
1449 .vreg_list = qmp_phy_vreg_l,
1450 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1451 .regs = qmp_v3_usb3phy_regs_layout,
1452 };
1453
1454 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1455 .offsets = &qmp_usb_offsets_v3_msm8996,
1456
1457 .serdes_tbl = msm8996_usb3_serdes_tbl,
1458 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1459 .tx_tbl = msm8996_usb3_tx_tbl,
1460 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1461 .rx_tbl = msm8996_usb3_rx_tbl,
1462 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1463 .pcs_tbl = msm8996_usb3_pcs_tbl,
1464 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1465 .vreg_list = qmp_phy_vreg_l,
1466 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1467 .regs = qmp_v2_usb3phy_regs_layout,
1468 };
1469
1470 static const struct qmp_phy_cfg qdu1000_usb3_uniphy_cfg = {
1471 .offsets = &qmp_usb_offsets_v5,
1472
1473 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1474 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1475 .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
1476 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
1477 .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
1478 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
1479 .pcs_tbl = qdu1000_usb3_uniphy_pcs_tbl,
1480 .pcs_tbl_num = ARRAY_SIZE(qdu1000_usb3_uniphy_pcs_tbl),
1481 .pcs_usb_tbl = qdu1000_usb3_uniphy_pcs_usb_tbl,
1482 .pcs_usb_tbl_num = ARRAY_SIZE(qdu1000_usb3_uniphy_pcs_usb_tbl),
1483 .vreg_list = qmp_phy_vreg_l,
1484 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1485 .regs = qmp_v4_usb3phy_regs_layout,
1486 .pcs_usb_offset = 0x1000,
1487
1488 .has_pwrdn_delay = true,
1489 };
1490
1491 static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = {
1492 .offsets = &qmp_usb_offsets_v5,
1493
1494 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
1495 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1496 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl,
1497 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1498 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl,
1499 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1500 .pcs_tbl = sa8775p_usb3_uniphy_pcs_tbl,
1501 .pcs_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl),
1502 .pcs_usb_tbl = sa8775p_usb3_uniphy_pcs_usb_tbl,
1503 .pcs_usb_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_usb_tbl),
1504 .vreg_list = qmp_phy_vreg_l,
1505 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1506 .regs = qmp_v5_usb3phy_regs_layout,
1507 };
1508
1509 static const struct qmp_phy_cfg qcs8300_usb3_uniphy_cfg = {
1510 .offsets = &qmp_usb_offsets_v5,
1511
1512 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
1513 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1514 .tx_tbl = qcs8300_usb3_uniphy_tx_tbl,
1515 .tx_tbl_num = ARRAY_SIZE(qcs8300_usb3_uniphy_tx_tbl),
1516 .rx_tbl = qcs8300_usb3_uniphy_rx_tbl,
1517 .rx_tbl_num = ARRAY_SIZE(qcs8300_usb3_uniphy_rx_tbl),
1518 .pcs_tbl = sa8775p_usb3_uniphy_pcs_tbl,
1519 .pcs_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl),
1520 .pcs_usb_tbl = sa8775p_usb3_uniphy_pcs_usb_tbl,
1521 .pcs_usb_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_usb_tbl),
1522 .vreg_list = qmp_phy_vreg_l,
1523 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1524 .regs = qmp_v5_usb3phy_regs_layout,
1525 };
1526
1527 static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
1528 .offsets = &qmp_usb_offsets_v5,
1529
1530 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl,
1531 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1532 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl,
1533 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1534 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl,
1535 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1536 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl,
1537 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl),
1538 .pcs_usb_tbl = sc8280xp_usb3_uniphy_pcs_usb_tbl,
1539 .pcs_usb_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_usb_tbl),
1540 .vreg_list = qmp_phy_vreg_l,
1541 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1542 .regs = qmp_v5_usb3phy_regs_layout,
1543 };
1544
1545 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1546 .offsets = &qmp_usb_offsets_v3,
1547
1548 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl,
1549 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1550 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl,
1551 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1552 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl,
1553 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1554 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl,
1555 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1556 .vreg_list = qmp_phy_vreg_l,
1557 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1558 .regs = qmp_v3_usb3phy_regs_layout,
1559
1560 .has_pwrdn_delay = true,
1561 };
1562
1563 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
1564 .offsets = &qmp_usb_offsets_v4,
1565
1566 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1567 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1568 .tx_tbl = sm8150_usb3_uniphy_tx_tbl,
1569 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
1570 .rx_tbl = sm8150_usb3_uniphy_rx_tbl,
1571 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
1572 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl,
1573 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
1574 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl,
1575 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),
1576 .vreg_list = qmp_phy_vreg_l,
1577 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1578 .regs = qmp_v4_usb3phy_regs_layout,
1579 .pcs_usb_offset = 0x600,
1580
1581 .has_pwrdn_delay = true,
1582 };
1583
1584 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
1585 .offsets = &qmp_usb_offsets_v4,
1586
1587 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1588 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1589 .tx_tbl = sm8250_usb3_uniphy_tx_tbl,
1590 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
1591 .rx_tbl = sm8250_usb3_uniphy_rx_tbl,
1592 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
1593 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
1594 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1595 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
1596 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1597 .vreg_list = qmp_phy_vreg_l,
1598 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1599 .regs = qmp_v4_usb3phy_regs_layout,
1600 .pcs_usb_offset = 0x600,
1601
1602 .has_pwrdn_delay = true,
1603 };
1604
1605 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
1606 .offsets = &qmp_usb_offsets_v4,
1607
1608 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1609 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1610 .tx_tbl = sdx55_usb3_uniphy_tx_tbl,
1611 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
1612 .rx_tbl = sdx55_usb3_uniphy_rx_tbl,
1613 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
1614 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl,
1615 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1616 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl,
1617 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1618 .vreg_list = qmp_phy_vreg_l,
1619 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1620 .regs = qmp_v4_usb3phy_regs_layout,
1621 .pcs_usb_offset = 0x600,
1622
1623 .has_pwrdn_delay = true,
1624 };
1625
1626 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
1627 .offsets = &qmp_usb_offsets_v5,
1628
1629 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1630 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1631 .tx_tbl = sdx65_usb3_uniphy_tx_tbl,
1632 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
1633 .rx_tbl = sdx65_usb3_uniphy_rx_tbl,
1634 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
1635 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
1636 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1637 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
1638 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1639 .vreg_list = qmp_phy_vreg_l,
1640 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1641 .regs = qmp_v5_usb3phy_regs_layout,
1642 .pcs_usb_offset = 0x1000,
1643
1644 .has_pwrdn_delay = true,
1645 };
1646
1647 static const struct qmp_phy_cfg sdx75_usb3_uniphy_cfg = {
1648 .offsets = &qmp_usb_offsets_v6,
1649
1650 .serdes_tbl = sdx75_usb3_uniphy_serdes_tbl,
1651 .serdes_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_serdes_tbl),
1652 .tx_tbl = sdx75_usb3_uniphy_tx_tbl,
1653 .tx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_tx_tbl),
1654 .rx_tbl = sdx75_usb3_uniphy_rx_tbl,
1655 .rx_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_rx_tbl),
1656 .pcs_tbl = sdx75_usb3_uniphy_pcs_tbl,
1657 .pcs_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_tbl),
1658 .pcs_usb_tbl = sdx75_usb3_uniphy_pcs_usb_tbl,
1659 .pcs_usb_tbl_num = ARRAY_SIZE(sdx75_usb3_uniphy_pcs_usb_tbl),
1660 .vreg_list = qmp_phy_vreg_l,
1661 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1662 .regs = qmp_v6_usb3phy_regs_layout,
1663 .pcs_usb_offset = 0x1000,
1664
1665 .has_pwrdn_delay = true,
1666 };
1667
1668 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
1669 .offsets = &qmp_usb_offsets_v5,
1670
1671 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl,
1672 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1673 .tx_tbl = sm8350_usb3_uniphy_tx_tbl,
1674 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
1675 .rx_tbl = sm8350_usb3_uniphy_rx_tbl,
1676 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
1677 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl,
1678 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1679 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl,
1680 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1681 .vreg_list = qmp_phy_vreg_l,
1682 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1683 .regs = qmp_v5_usb3phy_regs_layout,
1684 .pcs_usb_offset = 0x1000,
1685
1686 .has_pwrdn_delay = true,
1687 };
1688
1689 static const struct qmp_phy_cfg x1e80100_usb3_uniphy_cfg = {
1690 .offsets = &qmp_usb_offsets_v7,
1691
1692 .serdes_tbl = x1e80100_usb3_uniphy_serdes_tbl,
1693 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_serdes_tbl),
1694 .tx_tbl = x1e80100_usb3_uniphy_tx_tbl,
1695 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_tx_tbl),
1696 .rx_tbl = x1e80100_usb3_uniphy_rx_tbl,
1697 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_rx_tbl),
1698 .pcs_tbl = x1e80100_usb3_uniphy_pcs_tbl,
1699 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_tbl),
1700 .pcs_usb_tbl = x1e80100_usb3_uniphy_pcs_usb_tbl,
1701 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb3_uniphy_pcs_usb_tbl),
1702 .vreg_list = qmp_phy_vreg_l,
1703 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
1704 .regs = qmp_v7_usb3phy_regs_layout,
1705 };
1706
qmp_usb_serdes_init(struct qmp_usb * qmp)1707 static int qmp_usb_serdes_init(struct qmp_usb *qmp)
1708 {
1709 const struct qmp_phy_cfg *cfg = qmp->cfg;
1710 void __iomem *serdes = qmp->serdes;
1711 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
1712 int serdes_tbl_num = cfg->serdes_tbl_num;
1713
1714 qmp_configure(qmp->dev, serdes, serdes_tbl, serdes_tbl_num);
1715
1716 return 0;
1717 }
1718
qmp_usb_init(struct phy * phy)1719 static int qmp_usb_init(struct phy *phy)
1720 {
1721 struct qmp_usb *qmp = phy_get_drvdata(phy);
1722 const struct qmp_phy_cfg *cfg = qmp->cfg;
1723 void __iomem *pcs = qmp->pcs;
1724 int ret;
1725
1726 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1727 if (ret) {
1728 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1729 return ret;
1730 }
1731
1732 ret = reset_control_bulk_assert(qmp->num_resets, qmp->resets);
1733 if (ret) {
1734 dev_err(qmp->dev, "reset assert failed\n");
1735 goto err_disable_regulators;
1736 }
1737
1738 ret = reset_control_bulk_deassert(qmp->num_resets, qmp->resets);
1739 if (ret) {
1740 dev_err(qmp->dev, "reset deassert failed\n");
1741 goto err_disable_regulators;
1742 }
1743
1744 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
1745 if (ret)
1746 goto err_assert_reset;
1747
1748 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
1749
1750 return 0;
1751
1752 err_assert_reset:
1753 reset_control_bulk_assert(qmp->num_resets, qmp->resets);
1754 err_disable_regulators:
1755 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1756
1757 return ret;
1758 }
1759
qmp_usb_exit(struct phy * phy)1760 static int qmp_usb_exit(struct phy *phy)
1761 {
1762 struct qmp_usb *qmp = phy_get_drvdata(phy);
1763 const struct qmp_phy_cfg *cfg = qmp->cfg;
1764
1765 reset_control_bulk_assert(qmp->num_resets, qmp->resets);
1766
1767 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1768
1769 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1770
1771 return 0;
1772 }
1773
qmp_usb_power_on(struct phy * phy)1774 static int qmp_usb_power_on(struct phy *phy)
1775 {
1776 struct qmp_usb *qmp = phy_get_drvdata(phy);
1777 const struct qmp_phy_cfg *cfg = qmp->cfg;
1778 void __iomem *tx = qmp->tx;
1779 void __iomem *rx = qmp->rx;
1780 void __iomem *pcs = qmp->pcs;
1781 void __iomem *pcs_usb = qmp->pcs_usb;
1782 void __iomem *status;
1783 unsigned int val;
1784 int ret;
1785
1786 qmp_usb_serdes_init(qmp);
1787
1788 ret = clk_prepare_enable(qmp->pipe_clk);
1789 if (ret) {
1790 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
1791 return ret;
1792 }
1793
1794 /* Tx, Rx, and PCS configurations */
1795 qmp_configure_lane(qmp->dev, tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
1796 qmp_configure_lane(qmp->dev, rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
1797
1798 qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
1799
1800 if (pcs_usb)
1801 qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
1802
1803 if (cfg->has_pwrdn_delay)
1804 usleep_range(10, 20);
1805
1806 /* Pull PHY out of reset state */
1807 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1808
1809 /* start SerDes and Phy-Coding-Sublayer */
1810 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
1811
1812 status = pcs + cfg->regs[QPHY_PCS_STATUS];
1813 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
1814 PHY_INIT_COMPLETE_TIMEOUT);
1815 if (ret) {
1816 dev_err(qmp->dev, "phy initialization timed-out\n");
1817 goto err_disable_pipe_clk;
1818 }
1819
1820 return 0;
1821
1822 err_disable_pipe_clk:
1823 clk_disable_unprepare(qmp->pipe_clk);
1824
1825 return ret;
1826 }
1827
qmp_usb_power_off(struct phy * phy)1828 static int qmp_usb_power_off(struct phy *phy)
1829 {
1830 struct qmp_usb *qmp = phy_get_drvdata(phy);
1831 const struct qmp_phy_cfg *cfg = qmp->cfg;
1832
1833 clk_disable_unprepare(qmp->pipe_clk);
1834
1835 /* PHY reset */
1836 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1837
1838 /* stop SerDes and Phy-Coding-Sublayer */
1839 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
1840 SERDES_START | PCS_START);
1841
1842 /* Put PHY into POWER DOWN state: active low */
1843 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
1844 SW_PWRDN);
1845
1846 return 0;
1847 }
1848
qmp_usb_enable(struct phy * phy)1849 static int qmp_usb_enable(struct phy *phy)
1850 {
1851 int ret;
1852
1853 ret = qmp_usb_init(phy);
1854 if (ret)
1855 return ret;
1856
1857 ret = qmp_usb_power_on(phy);
1858 if (ret)
1859 qmp_usb_exit(phy);
1860
1861 return ret;
1862 }
1863
qmp_usb_disable(struct phy * phy)1864 static int qmp_usb_disable(struct phy *phy)
1865 {
1866 int ret;
1867
1868 ret = qmp_usb_power_off(phy);
1869 if (ret)
1870 return ret;
1871 return qmp_usb_exit(phy);
1872 }
1873
qmp_usb_set_mode(struct phy * phy,enum phy_mode mode,int submode)1874 static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1875 {
1876 struct qmp_usb *qmp = phy_get_drvdata(phy);
1877
1878 qmp->mode = mode;
1879
1880 return 0;
1881 }
1882
1883 static const struct phy_ops qmp_usb_phy_ops = {
1884 .init = qmp_usb_enable,
1885 .exit = qmp_usb_disable,
1886 .set_mode = qmp_usb_set_mode,
1887 .owner = THIS_MODULE,
1888 };
1889
qmp_usb_enable_autonomous_mode(struct qmp_usb * qmp)1890 static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp)
1891 {
1892 const struct qmp_phy_cfg *cfg = qmp->cfg;
1893 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
1894 void __iomem *pcs_misc = qmp->pcs_misc;
1895 u32 intr_mask;
1896
1897 if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1898 qmp->mode == PHY_MODE_USB_DEVICE_SS)
1899 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1900 else
1901 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1902
1903 /* Clear any pending interrupts status */
1904 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1905 /* Writing 1 followed by 0 clears the interrupt */
1906 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1907
1908 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1909 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1910
1911 /* Enable required PHY autonomous mode interrupts */
1912 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1913
1914 /* Enable i/o clamp_n for autonomous mode */
1915 if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])
1916 qphy_clrbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);
1917 }
1918
qmp_usb_disable_autonomous_mode(struct qmp_usb * qmp)1919 static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp)
1920 {
1921 const struct qmp_phy_cfg *cfg = qmp->cfg;
1922 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
1923 void __iomem *pcs_misc = qmp->pcs_misc;
1924
1925 /* Disable i/o clamp_n on resume for normal mode */
1926 if (pcs_misc && cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE])
1927 qphy_setbits(pcs_misc, cfg->regs[QPHY_PCS_MISC_CLAMP_ENABLE], CLAMP_EN);
1928
1929 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1930 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1931
1932 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1933 /* Writing 1 followed by 0 clears the interrupt */
1934 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1935 }
1936
qmp_usb_runtime_suspend(struct device * dev)1937 static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev)
1938 {
1939 struct qmp_usb *qmp = dev_get_drvdata(dev);
1940
1941 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
1942
1943 if (!qmp->phy->init_count) {
1944 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1945 return 0;
1946 }
1947
1948 qmp_usb_enable_autonomous_mode(qmp);
1949
1950 clk_disable_unprepare(qmp->pipe_clk);
1951 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1952
1953 return 0;
1954 }
1955
qmp_usb_runtime_resume(struct device * dev)1956 static int __maybe_unused qmp_usb_runtime_resume(struct device *dev)
1957 {
1958 struct qmp_usb *qmp = dev_get_drvdata(dev);
1959 int ret = 0;
1960
1961 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
1962
1963 if (!qmp->phy->init_count) {
1964 dev_vdbg(dev, "PHY not initialized, bailing out\n");
1965 return 0;
1966 }
1967
1968 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
1969 if (ret)
1970 return ret;
1971
1972 ret = clk_prepare_enable(qmp->pipe_clk);
1973 if (ret) {
1974 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
1975 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
1976 return ret;
1977 }
1978
1979 qmp_usb_disable_autonomous_mode(qmp);
1980
1981 return 0;
1982 }
1983
1984 static const struct dev_pm_ops qmp_usb_pm_ops = {
1985 SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend,
1986 qmp_usb_runtime_resume, NULL)
1987 };
1988
qmp_usb_vreg_init(struct qmp_usb * qmp)1989 static int qmp_usb_vreg_init(struct qmp_usb *qmp)
1990 {
1991 const struct qmp_phy_cfg *cfg = qmp->cfg;
1992 struct device *dev = qmp->dev;
1993 int num = cfg->num_vregs;
1994 int i;
1995
1996 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1997 if (!qmp->vregs)
1998 return -ENOMEM;
1999
2000 for (i = 0; i < num; i++)
2001 qmp->vregs[i].supply = cfg->vreg_list[i];
2002
2003 return devm_regulator_bulk_get(dev, num, qmp->vregs);
2004 }
2005
qmp_usb_reset_init(struct qmp_usb * qmp,const char * const * reset_list,int num_resets)2006 static int qmp_usb_reset_init(struct qmp_usb *qmp,
2007 const char *const *reset_list,
2008 int num_resets)
2009 {
2010 struct device *dev = qmp->dev;
2011 int i;
2012 int ret;
2013
2014 qmp->resets = devm_kcalloc(dev, num_resets,
2015 sizeof(*qmp->resets), GFP_KERNEL);
2016 if (!qmp->resets)
2017 return -ENOMEM;
2018
2019 for (i = 0; i < num_resets; i++)
2020 qmp->resets[i].id = reset_list[i];
2021
2022 qmp->num_resets = num_resets;
2023
2024 ret = devm_reset_control_bulk_get_exclusive(dev, num_resets, qmp->resets);
2025 if (ret)
2026 return dev_err_probe(dev, ret, "failed to get resets\n");
2027
2028 return 0;
2029 }
2030
qmp_usb_clk_init(struct qmp_usb * qmp)2031 static int qmp_usb_clk_init(struct qmp_usb *qmp)
2032 {
2033 struct device *dev = qmp->dev;
2034 int num = ARRAY_SIZE(qmp_usb_phy_clk_l);
2035 int i;
2036
2037 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2038 if (!qmp->clks)
2039 return -ENOMEM;
2040
2041 for (i = 0; i < num; i++)
2042 qmp->clks[i].id = qmp_usb_phy_clk_l[i];
2043
2044 qmp->num_clks = num;
2045
2046 return devm_clk_bulk_get_optional(dev, num, qmp->clks);
2047 }
2048
phy_clk_release_provider(void * res)2049 static void phy_clk_release_provider(void *res)
2050 {
2051 of_clk_del_provider(res);
2052 }
2053
2054 /*
2055 * Register a fixed rate pipe clock.
2056 *
2057 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2058 * controls it. The <s>_pipe_clk coming out of the GCC is requested
2059 * by the PHY driver for its operations.
2060 * We register the <s>_pipe_clksrc here. The gcc driver takes care
2061 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2062 * Below picture shows this relationship.
2063 *
2064 * +---------------+
2065 * | PHY block |<<---------------------------------------+
2066 * | | |
2067 * | +-------+ | +-----+ |
2068 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2069 * clk | +-------+ | +-----+
2070 * +---------------+
2071 */
phy_pipe_clk_register(struct qmp_usb * qmp,struct device_node * np)2072 static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np)
2073 {
2074 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
2075 struct clk_init_data init = { };
2076 int ret;
2077
2078 ret = of_property_read_string(np, "clock-output-names", &init.name);
2079 if (ret) {
2080 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2081 return ret;
2082 }
2083
2084 init.ops = &clk_fixed_rate_ops;
2085
2086 /* controllers using QMP phys use 125MHz pipe clock interface */
2087 fixed->fixed_rate = 125000000;
2088 fixed->hw.init = &init;
2089
2090 ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2091 if (ret)
2092 return ret;
2093
2094 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2095 if (ret)
2096 return ret;
2097
2098 /*
2099 * Roll a devm action because the clock provider is the child node, but
2100 * the child node is not actually a device.
2101 */
2102 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
2103 }
2104
qmp_usb_iomap(struct device * dev,struct device_node * np,int index,bool exclusive)2105 static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np,
2106 int index, bool exclusive)
2107 {
2108 struct resource res;
2109
2110 if (!exclusive) {
2111 if (of_address_to_resource(np, index, &res))
2112 return IOMEM_ERR_PTR(-EINVAL);
2113
2114 return devm_ioremap(dev, res.start, resource_size(&res));
2115 }
2116
2117 return devm_of_iomap(dev, np, index, NULL);
2118 }
2119
qmp_usb_parse_dt_legacy(struct qmp_usb * qmp,struct device_node * np)2120 static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np)
2121 {
2122 struct platform_device *pdev = to_platform_device(qmp->dev);
2123 const struct qmp_phy_cfg *cfg = qmp->cfg;
2124 struct device *dev = qmp->dev;
2125 bool exclusive = true;
2126 int ret;
2127
2128 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
2129 if (IS_ERR(qmp->serdes))
2130 return PTR_ERR(qmp->serdes);
2131
2132 /*
2133 * FIXME: These bindings should be fixed to not rely on overlapping
2134 * mappings for PCS.
2135 */
2136 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy"))
2137 exclusive = false;
2138 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy"))
2139 exclusive = false;
2140
2141 /*
2142 * Get memory resources for the PHY:
2143 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2144 * For single lane PHYs: pcs_misc (optional) -> 3.
2145 */
2146 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
2147 if (IS_ERR(qmp->tx))
2148 return PTR_ERR(qmp->tx);
2149
2150 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2151 if (IS_ERR(qmp->rx))
2152 return PTR_ERR(qmp->rx);
2153
2154 qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive);
2155 if (IS_ERR(qmp->pcs))
2156 return PTR_ERR(qmp->pcs);
2157
2158 if (cfg->pcs_usb_offset)
2159 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
2160
2161 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
2162
2163 if (IS_ERR(qmp->pcs_misc)) {
2164 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2165 qmp->pcs_misc = NULL;
2166 }
2167
2168 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
2169 if (IS_ERR(qmp->pipe_clk)) {
2170 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2171 "failed to get pipe clock\n");
2172 }
2173
2174 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks);
2175 if (ret < 0)
2176 return ret;
2177
2178 qmp->num_clks = ret;
2179
2180 ret = qmp_usb_reset_init(qmp, usb3phy_legacy_reset_l,
2181 ARRAY_SIZE(usb3phy_legacy_reset_l));
2182 if (ret)
2183 return ret;
2184
2185 return 0;
2186 }
2187
qmp_usb_parse_dt(struct qmp_usb * qmp)2188 static int qmp_usb_parse_dt(struct qmp_usb *qmp)
2189 {
2190 struct platform_device *pdev = to_platform_device(qmp->dev);
2191 const struct qmp_phy_cfg *cfg = qmp->cfg;
2192 const struct qmp_usb_offsets *offs = cfg->offsets;
2193 struct device *dev = qmp->dev;
2194 void __iomem *base;
2195 int ret;
2196
2197 if (!offs)
2198 return -EINVAL;
2199
2200 base = devm_platform_ioremap_resource(pdev, 0);
2201 if (IS_ERR(base))
2202 return PTR_ERR(base);
2203
2204 qmp->serdes = base + offs->serdes;
2205 qmp->pcs = base + offs->pcs;
2206 if (offs->pcs_usb)
2207 qmp->pcs_usb = base + offs->pcs_usb;
2208 if (offs->pcs_misc)
2209 qmp->pcs_misc = base + offs->pcs_misc;
2210 qmp->tx = base + offs->tx;
2211 qmp->rx = base + offs->rx;
2212
2213 ret = qmp_usb_clk_init(qmp);
2214 if (ret)
2215 return ret;
2216
2217 qmp->pipe_clk = devm_clk_get(dev, "pipe");
2218 if (IS_ERR(qmp->pipe_clk)) {
2219 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2220 "failed to get pipe clock\n");
2221 }
2222
2223 ret = qmp_usb_reset_init(qmp, usb3phy_reset_l,
2224 ARRAY_SIZE(usb3phy_reset_l));
2225 if (ret)
2226 return ret;
2227
2228 return 0;
2229 }
2230
qmp_usb_probe(struct platform_device * pdev)2231 static int qmp_usb_probe(struct platform_device *pdev)
2232 {
2233 struct device *dev = &pdev->dev;
2234 struct phy_provider *phy_provider;
2235 struct device_node *np;
2236 struct qmp_usb *qmp;
2237 int ret;
2238
2239 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2240 if (!qmp)
2241 return -ENOMEM;
2242
2243 qmp->dev = dev;
2244 dev_set_drvdata(dev, qmp);
2245
2246 qmp->cfg = of_device_get_match_data(dev);
2247 if (!qmp->cfg)
2248 return -EINVAL;
2249
2250 ret = qmp_usb_vreg_init(qmp);
2251 if (ret)
2252 return ret;
2253
2254 /* Check for legacy binding with child node. */
2255 np = of_get_next_available_child(dev->of_node, NULL);
2256 if (np) {
2257 ret = qmp_usb_parse_dt_legacy(qmp, np);
2258 } else {
2259 np = of_node_get(dev->of_node);
2260 ret = qmp_usb_parse_dt(qmp);
2261 }
2262 if (ret)
2263 goto err_node_put;
2264
2265 pm_runtime_set_active(dev);
2266 ret = devm_pm_runtime_enable(dev);
2267 if (ret)
2268 goto err_node_put;
2269 /*
2270 * Prevent runtime pm from being ON by default. Users can enable
2271 * it using power/control in sysfs.
2272 */
2273 pm_runtime_forbid(dev);
2274
2275 ret = phy_pipe_clk_register(qmp, np);
2276 if (ret)
2277 goto err_node_put;
2278
2279 qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops);
2280 if (IS_ERR(qmp->phy)) {
2281 ret = PTR_ERR(qmp->phy);
2282 dev_err(dev, "failed to create PHY: %d\n", ret);
2283 goto err_node_put;
2284 }
2285
2286 phy_set_drvdata(qmp->phy, qmp);
2287
2288 of_node_put(np);
2289
2290 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2291
2292 return PTR_ERR_OR_ZERO(phy_provider);
2293
2294 err_node_put:
2295 of_node_put(np);
2296 return ret;
2297 }
2298
2299 static const struct of_device_id qmp_usb_of_match_table[] = {
2300 {
2301 .compatible = "qcom,ipq6018-qmp-usb3-phy",
2302 .data = &ipq6018_usb3phy_cfg,
2303 }, {
2304 .compatible = "qcom,ipq8074-qmp-usb3-phy",
2305 .data = &ipq8074_usb3phy_cfg,
2306 }, {
2307 .compatible = "qcom,ipq9574-qmp-usb3-phy",
2308 .data = &ipq9574_usb3phy_cfg,
2309 }, {
2310 .compatible = "qcom,msm8996-qmp-usb3-phy",
2311 .data = &msm8996_usb3phy_cfg,
2312 }, {
2313 .compatible = "qcom,qcs8300-qmp-usb3-uni-phy",
2314 .data = &qcs8300_usb3_uniphy_cfg,
2315 }, {
2316 .compatible = "qcom,qdu1000-qmp-usb3-uni-phy",
2317 .data = &qdu1000_usb3_uniphy_cfg,
2318 }, {
2319 .compatible = "qcom,sa8775p-qmp-usb3-uni-phy",
2320 .data = &sa8775p_usb3_uniphy_cfg,
2321 }, {
2322 .compatible = "qcom,sc8180x-qmp-usb3-uni-phy",
2323 .data = &sm8150_usb3_uniphy_cfg,
2324 }, {
2325 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
2326 .data = &sc8280xp_usb3_uniphy_cfg,
2327 }, {
2328 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2329 .data = &qmp_v3_usb3_uniphy_cfg,
2330 }, {
2331 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
2332 .data = &sdx55_usb3_uniphy_cfg,
2333 }, {
2334 .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
2335 .data = &sdx65_usb3_uniphy_cfg,
2336 }, {
2337 .compatible = "qcom,sdx75-qmp-usb3-uni-phy",
2338 .data = &sdx75_usb3_uniphy_cfg,
2339 }, {
2340 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
2341 .data = &sm8150_usb3_uniphy_cfg,
2342 }, {
2343 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
2344 .data = &sm8250_usb3_uniphy_cfg,
2345 }, {
2346 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
2347 .data = &sm8350_usb3_uniphy_cfg,
2348 }, {
2349 .compatible = "qcom,x1e80100-qmp-usb3-uni-phy",
2350 .data = &x1e80100_usb3_uniphy_cfg,
2351 },
2352 { },
2353 };
2354 MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table);
2355
2356 static struct platform_driver qmp_usb_driver = {
2357 .probe = qmp_usb_probe,
2358 .driver = {
2359 .name = "qcom-qmp-usb-phy",
2360 .pm = &qmp_usb_pm_ops,
2361 .of_match_table = qmp_usb_of_match_table,
2362 },
2363 };
2364
2365 module_platform_driver(qmp_usb_driver);
2366
2367 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2368 MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
2369 MODULE_LICENSE("GPL v2");
2370