1 /* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2 /* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7 #ifndef ATH12K_HW_H 8 #define ATH12K_HW_H 9 10 #include <linux/mhi.h> 11 #include <linux/uuid.h> 12 13 #include "wmi.h" 14 #include "hal.h" 15 16 /* Target configuration defines */ 17 18 /* Num VDEVS per radio */ 19 #define TARGET_NUM_VDEVS(ab) ((ab)->profile_param->num_vdevs) 20 21 /* Max num of stations for Single Radio mode */ 22 #define TARGET_NUM_STATIONS_SINGLE(ab) ((ab)->profile_param->max_client_single) 23 24 /* Max num of stations for DBS */ 25 #define TARGET_NUM_STATIONS_DBS(ab) ((ab)->profile_param->max_client_dbs) 26 27 /* Max num of stations for DBS_SBS */ 28 #define TARGET_NUM_STATIONS_DBS_SBS(ab) \ 29 ((ab)->profile_param->max_client_dbs_sbs) 30 31 #define TARGET_NUM_STATIONS(ab, x) TARGET_NUM_STATIONS_##x(ab) 32 33 #define TARGET_NUM_PEER_KEYS 2 34 35 #define TARGET_AST_SKID_LIMIT 16 36 #define TARGET_NUM_OFFLD_PEERS 4 37 #define TARGET_NUM_OFFLD_REORDER_BUFFS 4 38 39 #define TARGET_TX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 40 #define TARGET_RX_CHAIN_MASK (BIT(0) | BIT(1) | BIT(2) | BIT(4)) 41 #define TARGET_RX_TIMEOUT_LO_PRI 100 42 #define TARGET_RX_TIMEOUT_HI_PRI 40 43 44 #define TARGET_DECAP_MODE_RAW 0 45 #define TARGET_DECAP_MODE_NATIVE_WIFI 1 46 #define TARGET_DECAP_MODE_ETH 2 47 48 #define TARGET_SCAN_MAX_PENDING_REQS 4 49 #define TARGET_BMISS_OFFLOAD_MAX_VDEV 3 50 #define TARGET_ROAM_OFFLOAD_MAX_VDEV 3 51 #define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES 8 52 #define TARGET_GTK_OFFLOAD_MAX_VDEV 3 53 #define TARGET_NUM_MCAST_GROUPS 12 54 #define TARGET_NUM_MCAST_TABLE_ELEMS 64 55 #define TARGET_MCAST2UCAST_MODE 2 56 #define TARGET_TX_DBG_LOG_SIZE 1024 57 #define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1 58 #define TARGET_VOW_CONFIG 0 59 #define TARGET_NUM_MSDU_DESC (2500) 60 #define TARGET_MAX_FRAG_ENTRIES 6 61 #define TARGET_MAX_BCN_OFFLD 16 62 #define TARGET_NUM_WDS_ENTRIES 32 63 #define TARGET_DMA_BURST_SIZE 1 64 #define TARGET_RX_BATCHMODE 1 65 #define TARGET_EMA_MAX_PROFILE_PERIOD 8 66 67 #define ATH12K_HW_DEFAULT_QUEUE 0 68 #define ATH12K_HW_MAX_QUEUES 4 69 #define ATH12K_QUEUE_LEN 4096 70 71 #define ATH12K_HW_RATECODE_CCK_SHORT_PREAM_MASK 0x4 72 73 #define ATH12K_FW_DIR "ath12k" 74 75 #define ATH12K_BOARD_MAGIC "QCA-ATH12K-BOARD" 76 #define ATH12K_BOARD_API2_FILE "board-2.bin" 77 #define ATH12K_DEFAULT_BOARD_FILE "board.bin" 78 #define ATH12K_DEFAULT_CAL_FILE "caldata.bin" 79 #define ATH12K_AMSS_FILE "amss.bin" 80 #define ATH12K_M3_FILE "m3.bin" 81 #define ATH12K_AUX_UC_FILE "aux_ucode.bin" 82 #define ATH12K_REGDB_FILE_NAME "regdb.bin" 83 84 #define ATH12K_PCIE_MAX_PAYLOAD_SIZE 128 85 #define ATH12K_IPQ5332_USERPD_ID 1 86 87 enum ath12k_hw_rate_cck { 88 ATH12K_HW_RATE_CCK_LP_11M = 0, 89 ATH12K_HW_RATE_CCK_LP_5_5M, 90 ATH12K_HW_RATE_CCK_LP_2M, 91 ATH12K_HW_RATE_CCK_LP_1M, 92 ATH12K_HW_RATE_CCK_SP_11M, 93 ATH12K_HW_RATE_CCK_SP_5_5M, 94 ATH12K_HW_RATE_CCK_SP_2M, 95 }; 96 97 enum ath12k_hw_rate_ofdm { 98 ATH12K_HW_RATE_OFDM_48M = 0, 99 ATH12K_HW_RATE_OFDM_24M, 100 ATH12K_HW_RATE_OFDM_12M, 101 ATH12K_HW_RATE_OFDM_6M, 102 ATH12K_HW_RATE_OFDM_54M, 103 ATH12K_HW_RATE_OFDM_36M, 104 ATH12K_HW_RATE_OFDM_18M, 105 ATH12K_HW_RATE_OFDM_9M, 106 }; 107 108 enum ath12k_bus { 109 ATH12K_BUS_PCI, 110 ATH12K_BUS_AHB, 111 }; 112 113 #define ATH12K_EXT_IRQ_GRP_NUM_MAX 11 114 115 struct hal_rx_desc; 116 struct hal_tcl_data_cmd; 117 struct htt_rx_ring_tlv_filter; 118 enum hal_encrypt_type; 119 120 struct ath12k_hw_ring_mask { 121 u8 tx[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 122 u8 rx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 123 u8 rx_mon_status[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 124 u8 rx[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 125 u8 rx_err[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 126 u8 rx_wbm_rel[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 127 u8 reo_status[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 128 u8 host2rxdma[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 129 u8 tx_mon_dest[ATH12K_EXT_IRQ_GRP_NUM_MAX]; 130 }; 131 132 enum ath12k_m3_fw_loaders { 133 ath12k_m3_fw_loader_driver, 134 ath12k_m3_fw_loader_remoteproc, 135 }; 136 137 struct ath12k_hw_params { 138 const char *name; 139 u16 hw_rev; 140 141 struct { 142 const char *dir; 143 size_t board_size; 144 size_t cal_offset; 145 enum ath12k_m3_fw_loaders m3_loader; 146 bool download_aux_ucode:1; 147 } fw; 148 149 u8 max_radios; 150 bool single_pdev_only:1; 151 u32 qmi_service_ins_id; 152 bool internal_sleep_clock:1; 153 154 const struct ath12k_hw_ops *hw_ops; 155 const struct ath12k_hw_ring_mask *ring_mask; 156 157 const struct ce_attr *host_ce_config; 158 u32 ce_count; 159 const struct ce_pipe_config *target_ce_config; 160 u32 target_ce_count; 161 const struct service_to_pipe *svc_to_ce_map; 162 u32 svc_to_ce_map_len; 163 164 bool rxdma1_enable:1; 165 int num_rxdma_per_pdev; 166 int num_rxdma_dst_ring; 167 bool rx_mac_buf_ring:1; 168 bool vdev_start_delay:1; 169 170 u16 interface_modes; 171 bool supports_monitor:1; 172 173 bool idle_ps:1; 174 bool download_calib:1; 175 bool supports_suspend:1; 176 bool tcl_ring_retry:1; 177 bool reoq_lut_support:1; 178 bool supports_shadow_regs:1; 179 bool supports_aspm:1; 180 bool current_cc_support:1; 181 182 u32 num_tcl_banks; 183 u32 max_tx_ring; 184 185 const struct mhi_controller_config *mhi_config; 186 187 void (*wmi_init)(struct ath12k_base *ab, 188 struct ath12k_wmi_resource_config_arg *config); 189 190 u64 qmi_cnss_feature_bitmap; 191 192 u32 rfkill_pin; 193 u32 rfkill_cfg; 194 u32 rfkill_on_level; 195 196 u32 rddm_size; 197 198 u8 def_num_link; 199 u16 max_mlo_peer; 200 201 u32 otp_board_id_register; 202 203 bool supports_sta_ps; 204 205 const guid_t *acpi_guid; 206 bool supports_dynamic_smps_6ghz; 207 208 u32 iova_mask; 209 210 const struct ce_ie_addr *ce_ie_addr; 211 const struct ce_remap *ce_remap; 212 u32 bdf_addr_offset; 213 214 /* setup REO queue, frag etc only for primary link peer */ 215 bool dp_primary_link_only:1; 216 }; 217 218 struct ath12k_hw_ops { 219 u8 (*get_hw_mac_from_pdev_id)(int pdev_id); 220 int (*mac_id_to_pdev_id)(const struct ath12k_hw_params *hw, int mac_id); 221 int (*mac_id_to_srng_id)(const struct ath12k_hw_params *hw, int mac_id); 222 int (*rxdma_ring_sel_config)(struct ath12k_base *ab); 223 u8 (*get_ring_selector)(struct sk_buff *skb); 224 bool (*dp_srng_is_tx_comp_ring)(int ring_num); 225 bool (*is_frame_link_agnostic)(struct ath12k_link_vif *arvif, 226 struct ieee80211_mgmt *mgmt); 227 }; 228 229 static inline 230 int ath12k_hw_get_mac_from_pdev_id(const struct ath12k_hw_params *hw, 231 int pdev_idx) 232 { 233 if (hw->hw_ops->get_hw_mac_from_pdev_id) 234 return hw->hw_ops->get_hw_mac_from_pdev_id(pdev_idx); 235 236 return 0; 237 } 238 239 static inline int ath12k_hw_mac_id_to_pdev_id(const struct ath12k_hw_params *hw, 240 int mac_id) 241 { 242 if (hw->hw_ops->mac_id_to_pdev_id) 243 return hw->hw_ops->mac_id_to_pdev_id(hw, mac_id); 244 245 return 0; 246 } 247 248 static inline int ath12k_hw_mac_id_to_srng_id(const struct ath12k_hw_params *hw, 249 int mac_id) 250 { 251 if (hw->hw_ops->mac_id_to_srng_id) 252 return hw->hw_ops->mac_id_to_srng_id(hw, mac_id); 253 254 return 0; 255 } 256 257 struct ath12k_fw_ie { 258 __le32 id; 259 __le32 len; 260 u8 data[]; 261 }; 262 263 enum ath12k_bd_ie_board_type { 264 ATH12K_BD_IE_BOARD_NAME = 0, 265 ATH12K_BD_IE_BOARD_DATA = 1, 266 }; 267 268 enum ath12k_bd_ie_regdb_type { 269 ATH12K_BD_IE_REGDB_NAME = 0, 270 ATH12K_BD_IE_REGDB_DATA = 1, 271 }; 272 273 enum ath12k_bd_ie_type { 274 /* contains sub IEs of enum ath12k_bd_ie_board_type */ 275 ATH12K_BD_IE_BOARD = 0, 276 /* contains sub IEs of enum ath12k_bd_ie_regdb_type */ 277 ATH12K_BD_IE_REGDB = 1, 278 }; 279 280 static inline const char *ath12k_bd_ie_type_str(enum ath12k_bd_ie_type type) 281 { 282 switch (type) { 283 case ATH12K_BD_IE_BOARD: 284 return "board data"; 285 case ATH12K_BD_IE_REGDB: 286 return "regdb data"; 287 } 288 289 return "unknown"; 290 } 291 292 #endif 293