1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * QLogic Fibre Channel HBA Driver
4 * Copyright (c) 2003-2014 QLogic Corporation
5 */
6 #include "qla_def.h"
7 #include <linux/delay.h>
8 #include <linux/io-64-nonatomic-lo-hi.h>
9 #include <linux/pci.h>
10 #include <linux/ratelimit.h>
11 #include <linux/vmalloc.h>
12 #include <scsi/scsi_tcq.h>
13
14 #define MASK(n) ((1ULL<<(n))-1)
15 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | \
16 ((addr >> 25) & 0x3ff))
17 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | \
18 ((addr >> 25) & 0x3ff))
19 #define MS_WIN(addr) (addr & 0x0ffc0000)
20 #define QLA82XX_PCI_MN_2M (0)
21 #define QLA82XX_PCI_MS_2M (0x80000)
22 #define QLA82XX_PCI_OCM0_2M (0xc0000)
23 #define VALID_OCM_ADDR(addr) (((addr) & 0x3f800) != 0x3f800)
24 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
25 #define BLOCK_PROTECT_BITS 0x0F
26
27 /* CRB window related */
28 #define CRB_BLK(off) ((off >> 20) & 0x3f)
29 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
30 #define CRB_WINDOW_2M (0x130060)
31 #define QLA82XX_PCI_CAMQM_2M_END (0x04800800UL)
32 #define CRB_HI(off) ((qla82xx_crb_hub_agt[CRB_BLK(off)] << 20) | \
33 ((off) & 0xf0000))
34 #define QLA82XX_PCI_CAMQM_2M_BASE (0x000ff800UL)
35 #define CRB_INDIRECT_2M (0x1e0000UL)
36
37 #define MAX_CRB_XFORM 60
38 static unsigned long crb_addr_xform[MAX_CRB_XFORM];
39 static int qla82xx_crb_table_initialized;
40
41 #define qla82xx_crb_addr_transform(name) \
42 (crb_addr_xform[QLA82XX_HW_PX_MAP_CRB_##name] = \
43 QLA82XX_HW_CRB_HUB_AGT_ADR_##name << 20)
44
45 const int MD_MIU_TEST_AGT_RDDATA[] = {
46 0x410000A8, 0x410000AC,
47 0x410000B8, 0x410000BC
48 };
49
qla82xx_crb_addr_transform_setup(void)50 static void qla82xx_crb_addr_transform_setup(void)
51 {
52 qla82xx_crb_addr_transform(XDMA);
53 qla82xx_crb_addr_transform(TIMR);
54 qla82xx_crb_addr_transform(SRE);
55 qla82xx_crb_addr_transform(SQN3);
56 qla82xx_crb_addr_transform(SQN2);
57 qla82xx_crb_addr_transform(SQN1);
58 qla82xx_crb_addr_transform(SQN0);
59 qla82xx_crb_addr_transform(SQS3);
60 qla82xx_crb_addr_transform(SQS2);
61 qla82xx_crb_addr_transform(SQS1);
62 qla82xx_crb_addr_transform(SQS0);
63 qla82xx_crb_addr_transform(RPMX7);
64 qla82xx_crb_addr_transform(RPMX6);
65 qla82xx_crb_addr_transform(RPMX5);
66 qla82xx_crb_addr_transform(RPMX4);
67 qla82xx_crb_addr_transform(RPMX3);
68 qla82xx_crb_addr_transform(RPMX2);
69 qla82xx_crb_addr_transform(RPMX1);
70 qla82xx_crb_addr_transform(RPMX0);
71 qla82xx_crb_addr_transform(ROMUSB);
72 qla82xx_crb_addr_transform(SN);
73 qla82xx_crb_addr_transform(QMN);
74 qla82xx_crb_addr_transform(QMS);
75 qla82xx_crb_addr_transform(PGNI);
76 qla82xx_crb_addr_transform(PGND);
77 qla82xx_crb_addr_transform(PGN3);
78 qla82xx_crb_addr_transform(PGN2);
79 qla82xx_crb_addr_transform(PGN1);
80 qla82xx_crb_addr_transform(PGN0);
81 qla82xx_crb_addr_transform(PGSI);
82 qla82xx_crb_addr_transform(PGSD);
83 qla82xx_crb_addr_transform(PGS3);
84 qla82xx_crb_addr_transform(PGS2);
85 qla82xx_crb_addr_transform(PGS1);
86 qla82xx_crb_addr_transform(PGS0);
87 qla82xx_crb_addr_transform(PS);
88 qla82xx_crb_addr_transform(PH);
89 qla82xx_crb_addr_transform(NIU);
90 qla82xx_crb_addr_transform(I2Q);
91 qla82xx_crb_addr_transform(EG);
92 qla82xx_crb_addr_transform(MN);
93 qla82xx_crb_addr_transform(MS);
94 qla82xx_crb_addr_transform(CAS2);
95 qla82xx_crb_addr_transform(CAS1);
96 qla82xx_crb_addr_transform(CAS0);
97 qla82xx_crb_addr_transform(CAM);
98 qla82xx_crb_addr_transform(C2C1);
99 qla82xx_crb_addr_transform(C2C0);
100 qla82xx_crb_addr_transform(SMB);
101 qla82xx_crb_addr_transform(OCM0);
102 /*
103 * Used only in P3 just define it for P2 also.
104 */
105 qla82xx_crb_addr_transform(I2C0);
106
107 qla82xx_crb_table_initialized = 1;
108 }
109
110 static struct crb_128M_2M_block_map crb_128M_2M_map[64] = {
111 {{{0, 0, 0, 0} } },
112 {{{1, 0x0100000, 0x0102000, 0x120000},
113 {1, 0x0110000, 0x0120000, 0x130000},
114 {1, 0x0120000, 0x0122000, 0x124000},
115 {1, 0x0130000, 0x0132000, 0x126000},
116 {1, 0x0140000, 0x0142000, 0x128000},
117 {1, 0x0150000, 0x0152000, 0x12a000},
118 {1, 0x0160000, 0x0170000, 0x110000},
119 {1, 0x0170000, 0x0172000, 0x12e000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x01e0000, 0x01e0800, 0x122000},
127 {0, 0x0000000, 0x0000000, 0x000000} } } ,
128 {{{1, 0x0200000, 0x0210000, 0x180000} } },
129 {{{0, 0, 0, 0} } },
130 {{{1, 0x0400000, 0x0401000, 0x169000} } },
131 {{{1, 0x0500000, 0x0510000, 0x140000} } },
132 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },
133 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },
134 {{{1, 0x0800000, 0x0802000, 0x170000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {0, 0x0000000, 0x0000000, 0x000000},
144 {0, 0x0000000, 0x0000000, 0x000000},
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {1, 0x08f0000, 0x08f2000, 0x172000} } },
150 {{{1, 0x0900000, 0x0902000, 0x174000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {0, 0x0000000, 0x0000000, 0x000000},
160 {0, 0x0000000, 0x0000000, 0x000000},
161 {0, 0x0000000, 0x0000000, 0x000000},
162 {0, 0x0000000, 0x0000000, 0x000000},
163 {0, 0x0000000, 0x0000000, 0x000000},
164 {0, 0x0000000, 0x0000000, 0x000000},
165 {1, 0x09f0000, 0x09f2000, 0x176000} } },
166 {{{0, 0x0a00000, 0x0a02000, 0x178000},
167 {0, 0x0000000, 0x0000000, 0x000000},
168 {0, 0x0000000, 0x0000000, 0x000000},
169 {0, 0x0000000, 0x0000000, 0x000000},
170 {0, 0x0000000, 0x0000000, 0x000000},
171 {0, 0x0000000, 0x0000000, 0x000000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000},
180 {0, 0x0000000, 0x0000000, 0x000000},
181 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
182 {{{0, 0x0b00000, 0x0b02000, 0x17c000},
183 {0, 0x0000000, 0x0000000, 0x000000},
184 {0, 0x0000000, 0x0000000, 0x000000},
185 {0, 0x0000000, 0x0000000, 0x000000},
186 {0, 0x0000000, 0x0000000, 0x000000},
187 {0, 0x0000000, 0x0000000, 0x000000},
188 {0, 0x0000000, 0x0000000, 0x000000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000},
197 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
198 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },
199 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },
200 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },
201 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },
202 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },
203 {{{1, 0x1100000, 0x1101000, 0x160000} } },
204 {{{1, 0x1200000, 0x1201000, 0x161000} } },
205 {{{1, 0x1300000, 0x1301000, 0x162000} } },
206 {{{1, 0x1400000, 0x1401000, 0x163000} } },
207 {{{1, 0x1500000, 0x1501000, 0x165000} } },
208 {{{1, 0x1600000, 0x1601000, 0x166000} } },
209 {{{0, 0, 0, 0} } },
210 {{{0, 0, 0, 0} } },
211 {{{0, 0, 0, 0} } },
212 {{{0, 0, 0, 0} } },
213 {{{0, 0, 0, 0} } },
214 {{{0, 0, 0, 0} } },
215 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },
216 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },
217 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },
218 {{{0} } },
219 {{{1, 0x2100000, 0x2102000, 0x120000},
220 {1, 0x2110000, 0x2120000, 0x130000},
221 {1, 0x2120000, 0x2122000, 0x124000},
222 {1, 0x2130000, 0x2132000, 0x126000},
223 {1, 0x2140000, 0x2142000, 0x128000},
224 {1, 0x2150000, 0x2152000, 0x12a000},
225 {1, 0x2160000, 0x2170000, 0x110000},
226 {1, 0x2170000, 0x2172000, 0x12e000},
227 {0, 0x0000000, 0x0000000, 0x000000},
228 {0, 0x0000000, 0x0000000, 0x000000},
229 {0, 0x0000000, 0x0000000, 0x000000},
230 {0, 0x0000000, 0x0000000, 0x000000},
231 {0, 0x0000000, 0x0000000, 0x000000},
232 {0, 0x0000000, 0x0000000, 0x000000},
233 {0, 0x0000000, 0x0000000, 0x000000},
234 {0, 0x0000000, 0x0000000, 0x000000} } },
235 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },
236 {{{0} } },
237 {{{0} } },
238 {{{0} } },
239 {{{0} } },
240 {{{0} } },
241 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },
242 {{{1, 0x2900000, 0x2901000, 0x16b000} } },
243 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },
244 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },
245 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },
246 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },
247 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },
248 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },
249 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },
250 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },
251 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },
252 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },
253 {{{0} } },
254 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },
255 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },
256 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },
257 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },
258 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },
259 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },
260 {{{0} } },
261 {{{0} } },
262 {{{1, 0x3d00000, 0x3d04000, 0x1dc000} } },
263 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },
264 {{{1, 0x3f00000, 0x3f01000, 0x168000} } }
265 };
266
267 /*
268 * top 12 bits of crb internal address (hub, agent)
269 */
270 static unsigned qla82xx_crb_hub_agt[64] = {
271 0,
272 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
273 QLA82XX_HW_CRB_HUB_AGT_ADR_MN,
274 QLA82XX_HW_CRB_HUB_AGT_ADR_MS,
275 0,
276 QLA82XX_HW_CRB_HUB_AGT_ADR_SRE,
277 QLA82XX_HW_CRB_HUB_AGT_ADR_NIU,
278 QLA82XX_HW_CRB_HUB_AGT_ADR_QMN,
279 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN0,
280 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN1,
281 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN2,
282 QLA82XX_HW_CRB_HUB_AGT_ADR_SQN3,
283 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
284 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
285 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
286 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN4,
287 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
288 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN0,
289 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN1,
290 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN2,
291 QLA82XX_HW_CRB_HUB_AGT_ADR_PGN3,
292 QLA82XX_HW_CRB_HUB_AGT_ADR_PGND,
293 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNI,
294 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS0,
295 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS1,
296 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS2,
297 QLA82XX_HW_CRB_HUB_AGT_ADR_PGS3,
298 0,
299 QLA82XX_HW_CRB_HUB_AGT_ADR_PGSI,
300 QLA82XX_HW_CRB_HUB_AGT_ADR_SN,
301 0,
302 QLA82XX_HW_CRB_HUB_AGT_ADR_EG,
303 0,
304 QLA82XX_HW_CRB_HUB_AGT_ADR_PS,
305 QLA82XX_HW_CRB_HUB_AGT_ADR_CAM,
306 0,
307 0,
308 0,
309 0,
310 0,
311 QLA82XX_HW_CRB_HUB_AGT_ADR_TIMR,
312 0,
313 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX1,
314 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX2,
315 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX3,
316 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX4,
317 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX5,
318 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX6,
319 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX7,
320 QLA82XX_HW_CRB_HUB_AGT_ADR_XDMA,
321 QLA82XX_HW_CRB_HUB_AGT_ADR_I2Q,
322 QLA82XX_HW_CRB_HUB_AGT_ADR_ROMUSB,
323 0,
324 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX0,
325 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX8,
326 QLA82XX_HW_CRB_HUB_AGT_ADR_RPMX9,
327 QLA82XX_HW_CRB_HUB_AGT_ADR_OCM0,
328 0,
329 QLA82XX_HW_CRB_HUB_AGT_ADR_SMB,
330 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C0,
331 QLA82XX_HW_CRB_HUB_AGT_ADR_I2C1,
332 0,
333 QLA82XX_HW_CRB_HUB_AGT_ADR_PGNC,
334 0,
335 };
336
337 /* Device states */
338 static const char *const q_dev_state[] = {
339 [QLA8XXX_DEV_UNKNOWN] = "Unknown",
340 [QLA8XXX_DEV_COLD] = "Cold/Re-init",
341 [QLA8XXX_DEV_INITIALIZING] = "Initializing",
342 [QLA8XXX_DEV_READY] = "Ready",
343 [QLA8XXX_DEV_NEED_RESET] = "Need Reset",
344 [QLA8XXX_DEV_NEED_QUIESCENT] = "Need Quiescent",
345 [QLA8XXX_DEV_FAILED] = "Failed",
346 [QLA8XXX_DEV_QUIESCENT] = "Quiescent",
347 };
348
qdev_state(uint32_t dev_state)349 const char *qdev_state(uint32_t dev_state)
350 {
351 return (dev_state < MAX_STATES) ? q_dev_state[dev_state] : "Unknown";
352 }
353
354 /*
355 * In: 'off_in' is offset from CRB space in 128M pci map
356 * Out: 'off_out' is 2M pci map addr
357 * side effect: lock crb window
358 */
359 static void
qla82xx_pci_set_crbwindow_2M(struct qla_hw_data * ha,ulong off_in,void __iomem ** off_out)360 qla82xx_pci_set_crbwindow_2M(struct qla_hw_data *ha, ulong off_in,
361 void __iomem **off_out)
362 {
363 u32 win_read;
364 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
365
366 ha->crb_win = CRB_HI(off_in);
367 writel(ha->crb_win, CRB_WINDOW_2M + ha->nx_pcibase);
368
369 /* Read back value to make sure write has gone through before trying
370 * to use it.
371 */
372 win_read = rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase);
373 if (win_read != ha->crb_win) {
374 ql_dbg(ql_dbg_p3p, vha, 0xb000,
375 "%s: Written crbwin (0x%x) "
376 "!= Read crbwin (0x%x), off=0x%lx.\n",
377 __func__, ha->crb_win, win_read, off_in);
378 }
379 *off_out = (off_in & MASK(16)) + CRB_INDIRECT_2M + ha->nx_pcibase;
380 }
381
382 static int
qla82xx_pci_get_crb_addr_2M(struct qla_hw_data * ha,ulong off_in,void __iomem ** off_out)383 qla82xx_pci_get_crb_addr_2M(struct qla_hw_data *ha, ulong off_in,
384 void __iomem **off_out)
385 {
386 struct crb_128M_2M_sub_block_map *m;
387
388 if (off_in >= QLA82XX_CRB_MAX)
389 return -1;
390
391 if (off_in >= QLA82XX_PCI_CAMQM && off_in < QLA82XX_PCI_CAMQM_2M_END) {
392 *off_out = (off_in - QLA82XX_PCI_CAMQM) +
393 QLA82XX_PCI_CAMQM_2M_BASE + ha->nx_pcibase;
394 return 0;
395 }
396
397 if (off_in < QLA82XX_PCI_CRBSPACE)
398 return -1;
399
400 off_in -= QLA82XX_PCI_CRBSPACE;
401
402 /* Try direct map */
403 m = &crb_128M_2M_map[CRB_BLK(off_in)].sub_block[CRB_SUBBLK(off_in)];
404
405 if (m->valid && (m->start_128M <= off_in) && (m->end_128M > off_in)) {
406 *off_out = off_in + m->start_2M - m->start_128M + ha->nx_pcibase;
407 return 0;
408 }
409 /* Not in direct map, use crb window */
410 *off_out = (void __iomem *)off_in;
411 return 1;
412 }
413
414 #define CRB_WIN_LOCK_TIMEOUT 100000000
qla82xx_crb_win_lock(struct qla_hw_data * ha)415 static int qla82xx_crb_win_lock(struct qla_hw_data *ha)
416 {
417 int done = 0, timeout = 0;
418
419 while (!done) {
420 /* acquire semaphore3 from PCI HW block */
421 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_LOCK));
422 if (done == 1)
423 break;
424 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
425 return -1;
426 timeout++;
427 }
428 qla82xx_wr_32(ha, QLA82XX_CRB_WIN_LOCK_ID, ha->portnum);
429 return 0;
430 }
431
432 int
qla82xx_wr_32(struct qla_hw_data * ha,ulong off_in,u32 data)433 qla82xx_wr_32(struct qla_hw_data *ha, ulong off_in, u32 data)
434 {
435 void __iomem *off;
436 unsigned long flags = 0;
437 int rv;
438
439 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
440
441 BUG_ON(rv == -1);
442
443 if (rv == 1) {
444 #ifndef __CHECKER__
445 write_lock_irqsave(&ha->hw_lock, flags);
446 #endif
447 qla82xx_crb_win_lock(ha);
448 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
449 }
450
451 writel(data, (void __iomem *)off);
452
453 if (rv == 1) {
454 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
455 #ifndef __CHECKER__
456 write_unlock_irqrestore(&ha->hw_lock, flags);
457 #endif
458 }
459 return 0;
460 }
461
462 int
qla82xx_rd_32(struct qla_hw_data * ha,ulong off_in)463 qla82xx_rd_32(struct qla_hw_data *ha, ulong off_in)
464 {
465 void __iomem *off;
466 unsigned long flags = 0;
467 int rv;
468 u32 data;
469
470 rv = qla82xx_pci_get_crb_addr_2M(ha, off_in, &off);
471
472 BUG_ON(rv == -1);
473
474 if (rv == 1) {
475 #ifndef __CHECKER__
476 write_lock_irqsave(&ha->hw_lock, flags);
477 #endif
478 qla82xx_crb_win_lock(ha);
479 qla82xx_pci_set_crbwindow_2M(ha, off_in, &off);
480 }
481 data = rd_reg_dword(off);
482
483 if (rv == 1) {
484 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM7_UNLOCK));
485 #ifndef __CHECKER__
486 write_unlock_irqrestore(&ha->hw_lock, flags);
487 #endif
488 }
489 return data;
490 }
491
492 /*
493 * Context: task, might sleep
494 */
qla82xx_idc_lock(struct qla_hw_data * ha)495 int qla82xx_idc_lock(struct qla_hw_data *ha)
496 {
497 const int delay_ms = 100, timeout_ms = 2000;
498 int done, total = 0;
499
500 might_sleep();
501
502 while (true) {
503 /* acquire semaphore5 from PCI HW block */
504 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_LOCK));
505 if (done == 1)
506 break;
507 if (WARN_ON_ONCE(total >= timeout_ms))
508 return -1;
509
510 total += delay_ms;
511 msleep(delay_ms);
512 }
513
514 return 0;
515 }
516
qla82xx_idc_unlock(struct qla_hw_data * ha)517 void qla82xx_idc_unlock(struct qla_hw_data *ha)
518 {
519 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM5_UNLOCK));
520 }
521
522 /*
523 * check memory access boundary.
524 * used by test agent. support ddr access only for now
525 */
526 static unsigned long
qla82xx_pci_mem_bound_check(struct qla_hw_data * ha,unsigned long long addr,int size)527 qla82xx_pci_mem_bound_check(struct qla_hw_data *ha,
528 unsigned long long addr, int size)
529 {
530 if (!addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
531 QLA82XX_ADDR_DDR_NET_MAX) ||
532 !addr_in_range(addr + size - 1, QLA82XX_ADDR_DDR_NET,
533 QLA82XX_ADDR_DDR_NET_MAX) ||
534 ((size != 1) && (size != 2) && (size != 4) && (size != 8)))
535 return 0;
536 else
537 return 1;
538 }
539
540 static int qla82xx_pci_set_window_warning_count;
541
542 static unsigned long
qla82xx_pci_set_window(struct qla_hw_data * ha,unsigned long long addr)543 qla82xx_pci_set_window(struct qla_hw_data *ha, unsigned long long addr)
544 {
545 int window;
546 u32 win_read;
547 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
548
549 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
550 QLA82XX_ADDR_DDR_NET_MAX)) {
551 /* DDR network side */
552 window = MN_WIN(addr);
553 ha->ddr_mn_window = window;
554 qla82xx_wr_32(ha,
555 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
556 win_read = qla82xx_rd_32(ha,
557 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
558 if ((win_read << 17) != window) {
559 ql_dbg(ql_dbg_p3p, vha, 0xb003,
560 "%s: Written MNwin (0x%x) != Read MNwin (0x%x).\n",
561 __func__, window, win_read);
562 }
563 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_DDR_NET;
564 } else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
565 QLA82XX_ADDR_OCM0_MAX)) {
566 unsigned int temp1;
567
568 if ((addr & 0x00ff800) == 0xff800) {
569 ql_log(ql_log_warn, vha, 0xb004,
570 "%s: QM access not handled.\n", __func__);
571 addr = -1UL;
572 }
573 window = OCM_WIN(addr);
574 ha->ddr_mn_window = window;
575 qla82xx_wr_32(ha,
576 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE, window);
577 win_read = qla82xx_rd_32(ha,
578 ha->mn_win_crb | QLA82XX_PCI_CRBSPACE);
579 temp1 = ((window & 0x1FF) << 7) |
580 ((window & 0x0FFFE0000) >> 17);
581 if (win_read != temp1) {
582 ql_log(ql_log_warn, vha, 0xb005,
583 "%s: Written OCMwin (0x%x) != Read OCMwin (0x%x).\n",
584 __func__, temp1, win_read);
585 }
586 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_OCM0_2M;
587
588 } else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET,
589 QLA82XX_P3_ADDR_QDR_NET_MAX)) {
590 /* QDR network side */
591 window = MS_WIN(addr);
592 ha->qdr_sn_window = window;
593 qla82xx_wr_32(ha,
594 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE, window);
595 win_read = qla82xx_rd_32(ha,
596 ha->ms_win_crb | QLA82XX_PCI_CRBSPACE);
597 if (win_read != window) {
598 ql_log(ql_log_warn, vha, 0xb006,
599 "%s: Written MSwin (0x%x) != Read MSwin (0x%x).\n",
600 __func__, window, win_read);
601 }
602 addr = GET_MEM_OFFS_2M(addr) + QLA82XX_PCI_QDR_NET;
603 } else {
604 /*
605 * peg gdb frequently accesses memory that doesn't exist,
606 * this limits the chit chat so debugging isn't slowed down.
607 */
608 if ((qla82xx_pci_set_window_warning_count++ < 8) ||
609 (qla82xx_pci_set_window_warning_count%64 == 0)) {
610 ql_log(ql_log_warn, vha, 0xb007,
611 "%s: Warning:%s Unknown address range!.\n",
612 __func__, QLA2XXX_DRIVER_NAME);
613 }
614 addr = -1UL;
615 }
616 return addr;
617 }
618
619 /* check if address is in the same windows as the previous access */
qla82xx_pci_is_same_window(struct qla_hw_data * ha,unsigned long long addr)620 static int qla82xx_pci_is_same_window(struct qla_hw_data *ha,
621 unsigned long long addr)
622 {
623 int window;
624 unsigned long long qdr_max;
625
626 qdr_max = QLA82XX_P3_ADDR_QDR_NET_MAX;
627
628 /* DDR network side */
629 if (addr_in_range(addr, QLA82XX_ADDR_DDR_NET,
630 QLA82XX_ADDR_DDR_NET_MAX))
631 BUG();
632 else if (addr_in_range(addr, QLA82XX_ADDR_OCM0,
633 QLA82XX_ADDR_OCM0_MAX))
634 return 1;
635 else if (addr_in_range(addr, QLA82XX_ADDR_OCM1,
636 QLA82XX_ADDR_OCM1_MAX))
637 return 1;
638 else if (addr_in_range(addr, QLA82XX_ADDR_QDR_NET, qdr_max)) {
639 /* QDR network side */
640 window = ((addr - QLA82XX_ADDR_QDR_NET) >> 22) & 0x3f;
641 if (ha->qdr_sn_window == window)
642 return 1;
643 }
644 return 0;
645 }
646
qla82xx_pci_mem_read_direct(struct qla_hw_data * ha,u64 off,void * data,int size)647 static int qla82xx_pci_mem_read_direct(struct qla_hw_data *ha,
648 u64 off, void *data, int size)
649 {
650 unsigned long flags;
651 void __iomem *addr = NULL;
652 int ret = 0;
653 u64 start;
654 uint8_t __iomem *mem_ptr = NULL;
655 unsigned long mem_base;
656 unsigned long mem_page;
657 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
658
659 write_lock_irqsave(&ha->hw_lock, flags);
660
661 /*
662 * If attempting to access unknown address or straddle hw windows,
663 * do not access.
664 */
665 start = qla82xx_pci_set_window(ha, off);
666 if ((start == -1UL) ||
667 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
668 write_unlock_irqrestore(&ha->hw_lock, flags);
669 ql_log(ql_log_fatal, vha, 0xb008,
670 "%s out of bound pci memory "
671 "access, offset is 0x%llx.\n",
672 QLA2XXX_DRIVER_NAME, off);
673 return -1;
674 }
675
676 write_unlock_irqrestore(&ha->hw_lock, flags);
677 mem_base = pci_resource_start(ha->pdev, 0);
678 mem_page = start & PAGE_MASK;
679 /* Map two pages whenever user tries to access addresses in two
680 * consecutive pages.
681 */
682 if (mem_page != ((start + size - 1) & PAGE_MASK))
683 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
684 else
685 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
686 if (mem_ptr == NULL) {
687 *(u8 *)data = 0;
688 return -1;
689 }
690 addr = mem_ptr;
691 addr += start & (PAGE_SIZE - 1);
692 write_lock_irqsave(&ha->hw_lock, flags);
693
694 switch (size) {
695 case 1:
696 *(u8 *)data = readb(addr);
697 break;
698 case 2:
699 *(u16 *)data = readw(addr);
700 break;
701 case 4:
702 *(u32 *)data = readl(addr);
703 break;
704 case 8:
705 *(u64 *)data = readq(addr);
706 break;
707 default:
708 ret = -1;
709 break;
710 }
711 write_unlock_irqrestore(&ha->hw_lock, flags);
712
713 if (mem_ptr)
714 iounmap(mem_ptr);
715 return ret;
716 }
717
718 static int
qla82xx_pci_mem_write_direct(struct qla_hw_data * ha,u64 off,void * data,int size)719 qla82xx_pci_mem_write_direct(struct qla_hw_data *ha,
720 u64 off, void *data, int size)
721 {
722 unsigned long flags;
723 void __iomem *addr = NULL;
724 int ret = 0;
725 u64 start;
726 uint8_t __iomem *mem_ptr = NULL;
727 unsigned long mem_base;
728 unsigned long mem_page;
729 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
730
731 write_lock_irqsave(&ha->hw_lock, flags);
732
733 /*
734 * If attempting to access unknown address or straddle hw windows,
735 * do not access.
736 */
737 start = qla82xx_pci_set_window(ha, off);
738 if ((start == -1UL) ||
739 (qla82xx_pci_is_same_window(ha, off + size - 1) == 0)) {
740 write_unlock_irqrestore(&ha->hw_lock, flags);
741 ql_log(ql_log_fatal, vha, 0xb009,
742 "%s out of bound memory "
743 "access, offset is 0x%llx.\n",
744 QLA2XXX_DRIVER_NAME, off);
745 return -1;
746 }
747
748 write_unlock_irqrestore(&ha->hw_lock, flags);
749 mem_base = pci_resource_start(ha->pdev, 0);
750 mem_page = start & PAGE_MASK;
751 /* Map two pages whenever user tries to access addresses in two
752 * consecutive pages.
753 */
754 if (mem_page != ((start + size - 1) & PAGE_MASK))
755 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
756 else
757 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
758 if (mem_ptr == NULL)
759 return -1;
760
761 addr = mem_ptr;
762 addr += start & (PAGE_SIZE - 1);
763 write_lock_irqsave(&ha->hw_lock, flags);
764
765 switch (size) {
766 case 1:
767 writeb(*(u8 *)data, addr);
768 break;
769 case 2:
770 writew(*(u16 *)data, addr);
771 break;
772 case 4:
773 writel(*(u32 *)data, addr);
774 break;
775 case 8:
776 writeq(*(u64 *)data, addr);
777 break;
778 default:
779 ret = -1;
780 break;
781 }
782 write_unlock_irqrestore(&ha->hw_lock, flags);
783 if (mem_ptr)
784 iounmap(mem_ptr);
785 return ret;
786 }
787
788 #define MTU_FUDGE_FACTOR 100
789 static unsigned long
qla82xx_decode_crb_addr(unsigned long addr)790 qla82xx_decode_crb_addr(unsigned long addr)
791 {
792 int i;
793 unsigned long base_addr, offset, pci_base;
794
795 if (!qla82xx_crb_table_initialized)
796 qla82xx_crb_addr_transform_setup();
797
798 pci_base = ADDR_ERROR;
799 base_addr = addr & 0xfff00000;
800 offset = addr & 0x000fffff;
801
802 for (i = 0; i < MAX_CRB_XFORM; i++) {
803 if (crb_addr_xform[i] == base_addr) {
804 pci_base = i << 20;
805 break;
806 }
807 }
808 if (pci_base == ADDR_ERROR)
809 return pci_base;
810 return pci_base + offset;
811 }
812
813 static long rom_max_timeout = 100;
814 static long qla82xx_rom_lock_timeout = 100;
815
816 static int
qla82xx_rom_lock(struct qla_hw_data * ha)817 qla82xx_rom_lock(struct qla_hw_data *ha)
818 {
819 int done = 0, timeout = 0;
820 uint32_t lock_owner = 0;
821 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
822
823 while (!done) {
824 /* acquire semaphore2 from PCI HW block */
825 done = qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_LOCK));
826 if (done == 1)
827 break;
828 if (timeout >= qla82xx_rom_lock_timeout) {
829 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
830 ql_dbg(ql_dbg_p3p, vha, 0xb157,
831 "%s: Simultaneous flash access by following ports, active port = %d: accessing port = %d",
832 __func__, ha->portnum, lock_owner);
833 return -1;
834 }
835 timeout++;
836 }
837 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, ha->portnum);
838 return 0;
839 }
840
841 static void
qla82xx_rom_unlock(struct qla_hw_data * ha)842 qla82xx_rom_unlock(struct qla_hw_data *ha)
843 {
844 qla82xx_wr_32(ha, QLA82XX_ROM_LOCK_ID, 0xffffffff);
845 qla82xx_rd_32(ha, QLA82XX_PCIE_REG(PCIE_SEM2_UNLOCK));
846 }
847
848 static int
qla82xx_wait_rom_busy(struct qla_hw_data * ha)849 qla82xx_wait_rom_busy(struct qla_hw_data *ha)
850 {
851 long timeout = 0;
852 long done = 0 ;
853 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
854
855 while (done == 0) {
856 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
857 done &= 4;
858 timeout++;
859 if (timeout >= rom_max_timeout) {
860 ql_dbg(ql_dbg_p3p, vha, 0xb00a,
861 "%s: Timeout reached waiting for rom busy.\n",
862 QLA2XXX_DRIVER_NAME);
863 return -1;
864 }
865 }
866 return 0;
867 }
868
869 static int
qla82xx_wait_rom_done(struct qla_hw_data * ha)870 qla82xx_wait_rom_done(struct qla_hw_data *ha)
871 {
872 long timeout = 0;
873 long done = 0 ;
874 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
875
876 while (done == 0) {
877 done = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_STATUS);
878 done &= 2;
879 timeout++;
880 if (timeout >= rom_max_timeout) {
881 ql_dbg(ql_dbg_p3p, vha, 0xb00b,
882 "%s: Timeout reached waiting for rom done.\n",
883 QLA2XXX_DRIVER_NAME);
884 return -1;
885 }
886 }
887 return 0;
888 }
889
890 static int
qla82xx_md_rw_32(struct qla_hw_data * ha,uint32_t off,u32 data,uint8_t flag)891 qla82xx_md_rw_32(struct qla_hw_data *ha, uint32_t off, u32 data, uint8_t flag)
892 {
893 uint32_t off_value, rval = 0;
894
895 wrt_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase, off & 0xFFFF0000);
896
897 /* Read back value to make sure write has gone through */
898 rd_reg_dword(CRB_WINDOW_2M + ha->nx_pcibase);
899 off_value = (off & 0x0000FFFF);
900
901 if (flag)
902 wrt_reg_dword(off_value + CRB_INDIRECT_2M + ha->nx_pcibase,
903 data);
904 else
905 rval = rd_reg_dword(off_value + CRB_INDIRECT_2M +
906 ha->nx_pcibase);
907
908 return rval;
909 }
910
911 static int
qla82xx_do_rom_fast_read(struct qla_hw_data * ha,int addr,int * valp)912 qla82xx_do_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
913 {
914 /* Dword reads to flash. */
915 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW, (addr & 0xFFFF0000), 1);
916 *valp = qla82xx_md_rw_32(ha, MD_DIRECT_ROM_READ_BASE +
917 (addr & 0x0000FFFF), 0, 0);
918
919 return 0;
920 }
921
922 static int
qla82xx_rom_fast_read(struct qla_hw_data * ha,int addr,int * valp)923 qla82xx_rom_fast_read(struct qla_hw_data *ha, int addr, int *valp)
924 {
925 int ret, loops = 0;
926 uint32_t lock_owner = 0;
927 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
928
929 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
930 udelay(100);
931 schedule();
932 loops++;
933 }
934 if (loops >= 50000) {
935 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
936 ql_log(ql_log_fatal, vha, 0x00b9,
937 "Failed to acquire SEM2 lock, Lock Owner %u.\n",
938 lock_owner);
939 return -1;
940 }
941 ret = qla82xx_do_rom_fast_read(ha, addr, valp);
942 qla82xx_rom_unlock(ha);
943 return ret;
944 }
945
946 static int
qla82xx_read_status_reg(struct qla_hw_data * ha,uint32_t * val)947 qla82xx_read_status_reg(struct qla_hw_data *ha, uint32_t *val)
948 {
949 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
950
951 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_RDSR);
952 qla82xx_wait_rom_busy(ha);
953 if (qla82xx_wait_rom_done(ha)) {
954 ql_log(ql_log_warn, vha, 0xb00c,
955 "Error waiting for rom done.\n");
956 return -1;
957 }
958 *val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_ROM_RDATA);
959 return 0;
960 }
961
962 static int
qla82xx_flash_wait_write_finish(struct qla_hw_data * ha)963 qla82xx_flash_wait_write_finish(struct qla_hw_data *ha)
964 {
965 uint32_t val = 0;
966 int i, ret;
967 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
968
969 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
970 for (i = 0; i < 50000; i++) {
971 ret = qla82xx_read_status_reg(ha, &val);
972 if (ret < 0 || (val & 1) == 0)
973 return ret;
974 udelay(10);
975 cond_resched();
976 }
977 ql_log(ql_log_warn, vha, 0xb00d,
978 "Timeout reached waiting for write finish.\n");
979 return -1;
980 }
981
982 static int
qla82xx_flash_set_write_enable(struct qla_hw_data * ha)983 qla82xx_flash_set_write_enable(struct qla_hw_data *ha)
984 {
985 uint32_t val;
986
987 qla82xx_wait_rom_busy(ha);
988 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 0);
989 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WREN);
990 qla82xx_wait_rom_busy(ha);
991 if (qla82xx_wait_rom_done(ha))
992 return -1;
993 if (qla82xx_read_status_reg(ha, &val) != 0)
994 return -1;
995 if ((val & 2) != 2)
996 return -1;
997 return 0;
998 }
999
1000 static int
qla82xx_write_status_reg(struct qla_hw_data * ha,uint32_t val)1001 qla82xx_write_status_reg(struct qla_hw_data *ha, uint32_t val)
1002 {
1003 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1004
1005 if (qla82xx_flash_set_write_enable(ha))
1006 return -1;
1007 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, val);
1008 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, 0x1);
1009 if (qla82xx_wait_rom_done(ha)) {
1010 ql_log(ql_log_warn, vha, 0xb00e,
1011 "Error waiting for rom done.\n");
1012 return -1;
1013 }
1014 return qla82xx_flash_wait_write_finish(ha);
1015 }
1016
1017 static int
qla82xx_write_disable_flash(struct qla_hw_data * ha)1018 qla82xx_write_disable_flash(struct qla_hw_data *ha)
1019 {
1020 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1021
1022 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_WRDI);
1023 if (qla82xx_wait_rom_done(ha)) {
1024 ql_log(ql_log_warn, vha, 0xb00f,
1025 "Error waiting for rom done.\n");
1026 return -1;
1027 }
1028 return 0;
1029 }
1030
1031 static int
ql82xx_rom_lock_d(struct qla_hw_data * ha)1032 ql82xx_rom_lock_d(struct qla_hw_data *ha)
1033 {
1034 int loops = 0;
1035 uint32_t lock_owner = 0;
1036 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1037
1038 while ((qla82xx_rom_lock(ha) != 0) && (loops < 50000)) {
1039 udelay(100);
1040 cond_resched();
1041 loops++;
1042 }
1043 if (loops >= 50000) {
1044 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
1045 ql_log(ql_log_warn, vha, 0xb010,
1046 "ROM lock failed, Lock Owner %u.\n", lock_owner);
1047 return -1;
1048 }
1049 return 0;
1050 }
1051
1052 static int
qla82xx_write_flash_dword(struct qla_hw_data * ha,uint32_t flashaddr,uint32_t data)1053 qla82xx_write_flash_dword(struct qla_hw_data *ha, uint32_t flashaddr,
1054 uint32_t data)
1055 {
1056 int ret = 0;
1057 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1058
1059 ret = ql82xx_rom_lock_d(ha);
1060 if (ret < 0) {
1061 ql_log(ql_log_warn, vha, 0xb011,
1062 "ROM lock failed.\n");
1063 return ret;
1064 }
1065
1066 ret = qla82xx_flash_set_write_enable(ha);
1067 if (ret < 0)
1068 goto done_write;
1069
1070 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_WDATA, data);
1071 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, flashaddr);
1072 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
1073 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_PP);
1074 qla82xx_wait_rom_busy(ha);
1075 if (qla82xx_wait_rom_done(ha)) {
1076 ql_log(ql_log_warn, vha, 0xb012,
1077 "Error waiting for rom done.\n");
1078 ret = -1;
1079 goto done_write;
1080 }
1081
1082 ret = qla82xx_flash_wait_write_finish(ha);
1083
1084 done_write:
1085 qla82xx_rom_unlock(ha);
1086 return ret;
1087 }
1088
1089 /* This routine does CRB initialize sequence
1090 * to put the ISP into operational state
1091 */
1092 static int
qla82xx_pinit_from_rom(scsi_qla_host_t * vha)1093 qla82xx_pinit_from_rom(scsi_qla_host_t *vha)
1094 {
1095 int addr, val;
1096 int i ;
1097 struct crb_addr_pair *buf;
1098 unsigned long off;
1099 unsigned offset, n;
1100 struct qla_hw_data *ha = vha->hw;
1101
1102 /* Halt all the individual PEGs and other blocks of the ISP */
1103 qla82xx_rom_lock(ha);
1104
1105 /* disable all I2Q */
1106 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x10, 0x0);
1107 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x14, 0x0);
1108 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x18, 0x0);
1109 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x1c, 0x0);
1110 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x20, 0x0);
1111 qla82xx_wr_32(ha, QLA82XX_CRB_I2Q + 0x24, 0x0);
1112
1113 /* disable all niu interrupts */
1114 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x40, 0xff);
1115 /* disable xge rx/tx */
1116 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x70000, 0x00);
1117 /* disable xg1 rx/tx */
1118 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x80000, 0x00);
1119 /* disable sideband mac */
1120 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x90000, 0x00);
1121 /* disable ap0 mac */
1122 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xa0000, 0x00);
1123 /* disable ap1 mac */
1124 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0xb0000, 0x00);
1125
1126 /* halt sre */
1127 val = qla82xx_rd_32(ha, QLA82XX_CRB_SRE + 0x1000);
1128 qla82xx_wr_32(ha, QLA82XX_CRB_SRE + 0x1000, val & (~(0x1)));
1129
1130 /* halt epg */
1131 qla82xx_wr_32(ha, QLA82XX_CRB_EPG + 0x1300, 0x1);
1132
1133 /* halt timers */
1134 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x0, 0x0);
1135 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x8, 0x0);
1136 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x10, 0x0);
1137 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x18, 0x0);
1138 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x100, 0x0);
1139 qla82xx_wr_32(ha, QLA82XX_CRB_TIMER + 0x200, 0x0);
1140
1141 /* halt pegs */
1142 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x3c, 1);
1143 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1 + 0x3c, 1);
1144 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2 + 0x3c, 1);
1145 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3 + 0x3c, 1);
1146 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_4 + 0x3c, 1);
1147 msleep(20);
1148
1149 /* big hammer */
1150 if (test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
1151 /* don't reset CAM block on reset */
1152 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xfeffffff);
1153 else
1154 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0xffffffff);
1155 qla82xx_rom_unlock(ha);
1156
1157 /* Read the signature value from the flash.
1158 * Offset 0: Contain signature (0xcafecafe)
1159 * Offset 4: Offset and number of addr/value pairs
1160 * that present in CRB initialize sequence
1161 */
1162 n = 0;
1163 if (qla82xx_rom_fast_read(ha, 0, &n) != 0 || n != 0xcafecafeUL ||
1164 qla82xx_rom_fast_read(ha, 4, &n) != 0) {
1165 ql_log(ql_log_fatal, vha, 0x006e,
1166 "Error Reading crb_init area: n: %08x.\n", n);
1167 return -1;
1168 }
1169
1170 /* Offset in flash = lower 16 bits
1171 * Number of entries = upper 16 bits
1172 */
1173 offset = n & 0xffffU;
1174 n = (n >> 16) & 0xffffU;
1175
1176 /* number of addr/value pair should not exceed 1024 entries */
1177 if (n >= 1024) {
1178 ql_log(ql_log_fatal, vha, 0x0071,
1179 "Card flash not initialized:n=0x%x.\n", n);
1180 return -1;
1181 }
1182
1183 ql_log(ql_log_info, vha, 0x0072,
1184 "%d CRB init values found in ROM.\n", n);
1185
1186 buf = kmalloc_array(n, sizeof(struct crb_addr_pair), GFP_KERNEL);
1187 if (buf == NULL) {
1188 ql_log(ql_log_fatal, vha, 0x010c,
1189 "Unable to allocate memory.\n");
1190 return -ENOMEM;
1191 }
1192
1193 for (i = 0; i < n; i++) {
1194 if (qla82xx_rom_fast_read(ha, 8*i + 4*offset, &val) != 0 ||
1195 qla82xx_rom_fast_read(ha, 8*i + 4*offset + 4, &addr) != 0) {
1196 kfree(buf);
1197 return -1;
1198 }
1199
1200 buf[i].addr = addr;
1201 buf[i].data = val;
1202 }
1203
1204 for (i = 0; i < n; i++) {
1205 /* Translate internal CRB initialization
1206 * address to PCI bus address
1207 */
1208 off = qla82xx_decode_crb_addr((unsigned long)buf[i].addr) +
1209 QLA82XX_PCI_CRBSPACE;
1210 /* Not all CRB addr/value pair to be written,
1211 * some of them are skipped
1212 */
1213
1214 /* skipping cold reboot MAGIC */
1215 if (off == QLA82XX_CAM_RAM(0x1fc))
1216 continue;
1217
1218 /* do not reset PCI */
1219 if (off == (ROMUSB_GLB + 0xbc))
1220 continue;
1221
1222 /* skip core clock, so that firmware can increase the clock */
1223 if (off == (ROMUSB_GLB + 0xc8))
1224 continue;
1225
1226 /* skip the function enable register */
1227 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION))
1228 continue;
1229
1230 if (off == QLA82XX_PCIE_REG(PCIE_SETUP_FUNCTION2))
1231 continue;
1232
1233 if ((off & 0x0ff00000) == QLA82XX_CRB_SMB)
1234 continue;
1235
1236 if ((off & 0x0ff00000) == QLA82XX_CRB_DDR_NET)
1237 continue;
1238
1239 if (off == ADDR_ERROR) {
1240 ql_log(ql_log_fatal, vha, 0x0116,
1241 "Unknown addr: 0x%08lx.\n", buf[i].addr);
1242 continue;
1243 }
1244
1245 qla82xx_wr_32(ha, off, buf[i].data);
1246
1247 /* ISP requires much bigger delay to settle down,
1248 * else crb_window returns 0xffffffff
1249 */
1250 if (off == QLA82XX_ROMUSB_GLB_SW_RESET)
1251 msleep(1000);
1252
1253 /* ISP requires millisec delay between
1254 * successive CRB register updation
1255 */
1256 msleep(1);
1257 }
1258
1259 kfree(buf);
1260
1261 /* Resetting the data and instruction cache */
1262 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0xec, 0x1e);
1263 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_D+0x4c, 8);
1264 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_I+0x4c, 8);
1265
1266 /* Clear all protocol processing engines */
1267 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0x8, 0);
1268 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0+0xc, 0);
1269 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0x8, 0);
1270 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_1+0xc, 0);
1271 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0x8, 0);
1272 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_2+0xc, 0);
1273 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0x8, 0);
1274 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_3+0xc, 0);
1275 return 0;
1276 }
1277
1278 static int
qla82xx_pci_mem_write_2M(struct qla_hw_data * ha,u64 off,void * data,int size)1279 qla82xx_pci_mem_write_2M(struct qla_hw_data *ha,
1280 u64 off, void *data, int size)
1281 {
1282 int i, j, ret = 0, loop, sz[2], off0;
1283 int scale, shift_amount, startword;
1284 uint32_t temp;
1285 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1286
1287 /*
1288 * If not MN, go check for MS or invalid.
1289 */
1290 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1291 mem_crb = QLA82XX_CRB_QDR_NET;
1292 else {
1293 mem_crb = QLA82XX_CRB_DDR_NET;
1294 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1295 return qla82xx_pci_mem_write_direct(ha,
1296 off, data, size);
1297 }
1298
1299 off0 = off & 0x7;
1300 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1301 sz[1] = size - sz[0];
1302
1303 off8 = off & 0xfffffff0;
1304 loop = (((off & 0xf) + size - 1) >> 4) + 1;
1305 shift_amount = 4;
1306 scale = 2;
1307 startword = (off & 0xf)/8;
1308
1309 for (i = 0; i < loop; i++) {
1310 if (qla82xx_pci_mem_read_2M(ha, off8 +
1311 (i << shift_amount), &word[i * scale], 8))
1312 return -1;
1313 }
1314
1315 switch (size) {
1316 case 1:
1317 tmpw = *((uint8_t *)data);
1318 break;
1319 case 2:
1320 tmpw = *((uint16_t *)data);
1321 break;
1322 case 4:
1323 tmpw = *((uint32_t *)data);
1324 break;
1325 case 8:
1326 default:
1327 tmpw = *((uint64_t *)data);
1328 break;
1329 }
1330
1331 if (sz[0] == 8) {
1332 word[startword] = tmpw;
1333 } else {
1334 word[startword] &=
1335 ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1336 word[startword] |= tmpw << (off0 * 8);
1337 }
1338 if (sz[1] != 0) {
1339 word[startword+1] &= ~(~0ULL << (sz[1] * 8));
1340 word[startword+1] |= tmpw >> (sz[0] * 8);
1341 }
1342
1343 for (i = 0; i < loop; i++) {
1344 temp = off8 + (i << shift_amount);
1345 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_LO, temp);
1346 temp = 0;
1347 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_ADDR_HI, temp);
1348 temp = word[i * scale] & 0xffffffff;
1349 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_LO, temp);
1350 temp = (word[i * scale] >> 32) & 0xffffffff;
1351 qla82xx_wr_32(ha, mem_crb+MIU_TEST_AGT_WRDATA_HI, temp);
1352 temp = word[i*scale + 1] & 0xffffffff;
1353 qla82xx_wr_32(ha, mem_crb +
1354 MIU_TEST_AGT_WRDATA_UPPER_LO, temp);
1355 temp = (word[i*scale + 1] >> 32) & 0xffffffff;
1356 qla82xx_wr_32(ha, mem_crb +
1357 MIU_TEST_AGT_WRDATA_UPPER_HI, temp);
1358
1359 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1360 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1361 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1362 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1363
1364 for (j = 0; j < MAX_CTL_CHECK; j++) {
1365 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1366 if ((temp & MIU_TA_CTL_BUSY) == 0)
1367 break;
1368 }
1369
1370 if (j >= MAX_CTL_CHECK) {
1371 if (printk_ratelimit())
1372 dev_err(&ha->pdev->dev,
1373 "failed to write through agent.\n");
1374 ret = -1;
1375 break;
1376 }
1377 }
1378
1379 return ret;
1380 }
1381
1382 static int
qla82xx_fw_load_from_flash(struct qla_hw_data * ha)1383 qla82xx_fw_load_from_flash(struct qla_hw_data *ha)
1384 {
1385 int i;
1386 long size = 0;
1387 long flashaddr = ha->flt_region_bootload << 2;
1388 long memaddr = BOOTLD_START;
1389 u64 data;
1390 u32 high, low;
1391
1392 size = (IMAGE_START - BOOTLD_START) / 8;
1393
1394 for (i = 0; i < size; i++) {
1395 if ((qla82xx_rom_fast_read(ha, flashaddr, (int *)&low)) ||
1396 (qla82xx_rom_fast_read(ha, flashaddr + 4, (int *)&high))) {
1397 return -1;
1398 }
1399 data = ((u64)high << 32) | low ;
1400 qla82xx_pci_mem_write_2M(ha, memaddr, &data, 8);
1401 flashaddr += 8;
1402 memaddr += 8;
1403
1404 if (i % 0x1000 == 0)
1405 msleep(1);
1406 }
1407 udelay(100);
1408 read_lock(&ha->hw_lock);
1409 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1410 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1411 read_unlock(&ha->hw_lock);
1412 return 0;
1413 }
1414
1415 int
qla82xx_pci_mem_read_2M(struct qla_hw_data * ha,u64 off,void * data,int size)1416 qla82xx_pci_mem_read_2M(struct qla_hw_data *ha,
1417 u64 off, void *data, int size)
1418 {
1419 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1420 int shift_amount;
1421 uint32_t temp;
1422 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1423
1424 /*
1425 * If not MN, go check for MS or invalid.
1426 */
1427
1428 if (off >= QLA82XX_ADDR_QDR_NET && off <= QLA82XX_P3_ADDR_QDR_NET_MAX)
1429 mem_crb = QLA82XX_CRB_QDR_NET;
1430 else {
1431 mem_crb = QLA82XX_CRB_DDR_NET;
1432 if (qla82xx_pci_mem_bound_check(ha, off, size) == 0)
1433 return qla82xx_pci_mem_read_direct(ha,
1434 off, data, size);
1435 }
1436
1437 off8 = off & 0xfffffff0;
1438 off0[0] = off & 0xf;
1439 sz[0] = (size < (16 - off0[0])) ? size : (16 - off0[0]);
1440 shift_amount = 4;
1441 loop = ((off0[0] + size - 1) >> shift_amount) + 1;
1442 off0[1] = 0;
1443 sz[1] = size - sz[0];
1444
1445 for (i = 0; i < loop; i++) {
1446 temp = off8 + (i << shift_amount);
1447 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_LO, temp);
1448 temp = 0;
1449 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_ADDR_HI, temp);
1450 temp = MIU_TA_CTL_ENABLE;
1451 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1452 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1453 qla82xx_wr_32(ha, mem_crb + MIU_TEST_AGT_CTRL, temp);
1454
1455 for (j = 0; j < MAX_CTL_CHECK; j++) {
1456 temp = qla82xx_rd_32(ha, mem_crb + MIU_TEST_AGT_CTRL);
1457 if ((temp & MIU_TA_CTL_BUSY) == 0)
1458 break;
1459 }
1460
1461 if (j >= MAX_CTL_CHECK) {
1462 if (printk_ratelimit())
1463 dev_err(&ha->pdev->dev,
1464 "failed to read through agent.\n");
1465 break;
1466 }
1467
1468 start = off0[i] >> 2;
1469 end = (off0[i] + sz[i] - 1) >> 2;
1470 for (k = start; k <= end; k++) {
1471 temp = qla82xx_rd_32(ha,
1472 mem_crb + MIU_TEST_AGT_RDDATA(k));
1473 word[i] |= ((uint64_t)temp << (32 * (k & 1)));
1474 }
1475 }
1476
1477 if (j >= MAX_CTL_CHECK)
1478 return -1;
1479
1480 if ((off0[0] & 7) == 0) {
1481 val = word[0];
1482 } else {
1483 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1484 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1485 }
1486
1487 switch (size) {
1488 case 1:
1489 *(uint8_t *)data = val;
1490 break;
1491 case 2:
1492 *(uint16_t *)data = val;
1493 break;
1494 case 4:
1495 *(uint32_t *)data = val;
1496 break;
1497 case 8:
1498 *(uint64_t *)data = val;
1499 break;
1500 }
1501 return 0;
1502 }
1503
1504
1505 static struct qla82xx_uri_table_desc *
qla82xx_get_table_desc(const u8 * unirom,int section)1506 qla82xx_get_table_desc(const u8 *unirom, int section)
1507 {
1508 uint32_t i;
1509 struct qla82xx_uri_table_desc *directory =
1510 (struct qla82xx_uri_table_desc *)&unirom[0];
1511 uint32_t offset;
1512 uint32_t tab_type;
1513 uint32_t entries = le32_to_cpu(directory->num_entries);
1514
1515 for (i = 0; i < entries; i++) {
1516 offset = le32_to_cpu(directory->findex) +
1517 (i * le32_to_cpu(directory->entry_size));
1518 tab_type = get_unaligned_le32((u32 *)&unirom[offset] + 8);
1519
1520 if (tab_type == section)
1521 return (struct qla82xx_uri_table_desc *)&unirom[offset];
1522 }
1523
1524 return NULL;
1525 }
1526
1527 static struct qla82xx_uri_data_desc *
qla82xx_get_data_desc(struct qla_hw_data * ha,u32 section,u32 idx_offset)1528 qla82xx_get_data_desc(struct qla_hw_data *ha,
1529 u32 section, u32 idx_offset)
1530 {
1531 const u8 *unirom = ha->hablob->fw->data;
1532 int idx = get_unaligned_le32((u32 *)&unirom[ha->file_prd_off] +
1533 idx_offset);
1534 struct qla82xx_uri_table_desc *tab_desc = NULL;
1535 uint32_t offset;
1536
1537 tab_desc = qla82xx_get_table_desc(unirom, section);
1538 if (!tab_desc)
1539 return NULL;
1540
1541 offset = le32_to_cpu(tab_desc->findex) +
1542 (le32_to_cpu(tab_desc->entry_size) * idx);
1543
1544 return (struct qla82xx_uri_data_desc *)&unirom[offset];
1545 }
1546
1547 static u8 *
qla82xx_get_bootld_offset(struct qla_hw_data * ha)1548 qla82xx_get_bootld_offset(struct qla_hw_data *ha)
1549 {
1550 u32 offset = BOOTLD_START;
1551 struct qla82xx_uri_data_desc *uri_desc = NULL;
1552
1553 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1554 uri_desc = qla82xx_get_data_desc(ha,
1555 QLA82XX_URI_DIR_SECT_BOOTLD, QLA82XX_URI_BOOTLD_IDX_OFF);
1556 if (uri_desc)
1557 offset = le32_to_cpu(uri_desc->findex);
1558 }
1559
1560 return (u8 *)&ha->hablob->fw->data[offset];
1561 }
1562
qla82xx_get_fw_size(struct qla_hw_data * ha)1563 static u32 qla82xx_get_fw_size(struct qla_hw_data *ha)
1564 {
1565 struct qla82xx_uri_data_desc *uri_desc = NULL;
1566
1567 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1568 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1569 QLA82XX_URI_FIRMWARE_IDX_OFF);
1570 if (uri_desc)
1571 return le32_to_cpu(uri_desc->size);
1572 }
1573
1574 return get_unaligned_le32(&ha->hablob->fw->data[FW_SIZE_OFFSET]);
1575 }
1576
1577 static u8 *
qla82xx_get_fw_offs(struct qla_hw_data * ha)1578 qla82xx_get_fw_offs(struct qla_hw_data *ha)
1579 {
1580 u32 offset = IMAGE_START;
1581 struct qla82xx_uri_data_desc *uri_desc = NULL;
1582
1583 if (ha->fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1584 uri_desc = qla82xx_get_data_desc(ha, QLA82XX_URI_DIR_SECT_FW,
1585 QLA82XX_URI_FIRMWARE_IDX_OFF);
1586 if (uri_desc)
1587 offset = le32_to_cpu(uri_desc->findex);
1588 }
1589
1590 return (u8 *)&ha->hablob->fw->data[offset];
1591 }
1592
1593 int
qla82xx_iospace_config(struct qla_hw_data * ha)1594 qla82xx_iospace_config(struct qla_hw_data *ha)
1595 {
1596 uint32_t len = 0;
1597
1598 if (pci_request_regions(ha->pdev, QLA2XXX_DRIVER_NAME)) {
1599 ql_log_pci(ql_log_fatal, ha->pdev, 0x000c,
1600 "Failed to reserver selected regions.\n");
1601 goto iospace_error_exit;
1602 }
1603
1604 /* Use MMIO operations for all accesses. */
1605 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) {
1606 ql_log_pci(ql_log_fatal, ha->pdev, 0x000d,
1607 "Region #0 not an MMIO resource, aborting.\n");
1608 goto iospace_error_exit;
1609 }
1610
1611 len = pci_resource_len(ha->pdev, 0);
1612 ha->nx_pcibase = ioremap(pci_resource_start(ha->pdev, 0), len);
1613 if (!ha->nx_pcibase) {
1614 ql_log_pci(ql_log_fatal, ha->pdev, 0x000e,
1615 "Cannot remap pcibase MMIO, aborting.\n");
1616 goto iospace_error_exit;
1617 }
1618
1619 /* Mapping of IO base pointer */
1620 if (IS_QLA8044(ha)) {
1621 ha->iobase = ha->nx_pcibase;
1622 } else if (IS_QLA82XX(ha)) {
1623 ha->iobase = ha->nx_pcibase + 0xbc000 + (ha->pdev->devfn << 11);
1624 }
1625
1626 if (!ql2xdbwr) {
1627 ha->nxdb_wr_ptr = ioremap((pci_resource_start(ha->pdev, 4) +
1628 (ha->pdev->devfn << 12)), 4);
1629 if (!ha->nxdb_wr_ptr) {
1630 ql_log_pci(ql_log_fatal, ha->pdev, 0x000f,
1631 "Cannot remap MMIO, aborting.\n");
1632 goto iospace_error_exit;
1633 }
1634
1635 /* Mapping of IO base pointer,
1636 * door bell read and write pointer
1637 */
1638 ha->nxdb_rd_ptr = ha->nx_pcibase + (512 * 1024) +
1639 (ha->pdev->devfn * 8);
1640 } else {
1641 ha->nxdb_wr_ptr = (void __iomem *)(ha->pdev->devfn == 6 ?
1642 QLA82XX_CAMRAM_DB1 :
1643 QLA82XX_CAMRAM_DB2);
1644 }
1645
1646 ha->max_req_queues = ha->max_rsp_queues = 1;
1647 ha->msix_count = ha->max_rsp_queues + 1;
1648 ql_dbg_pci(ql_dbg_multiq, ha->pdev, 0xc006,
1649 "nx_pci_base=%p iobase=%p "
1650 "max_req_queues=%d msix_count=%d.\n",
1651 ha->nx_pcibase, ha->iobase,
1652 ha->max_req_queues, ha->msix_count);
1653 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0010,
1654 "nx_pci_base=%p iobase=%p "
1655 "max_req_queues=%d msix_count=%d.\n",
1656 ha->nx_pcibase, ha->iobase,
1657 ha->max_req_queues, ha->msix_count);
1658 return 0;
1659
1660 iospace_error_exit:
1661 return -ENOMEM;
1662 }
1663
1664 /* GS related functions */
1665
1666 /* Initialization related functions */
1667
1668 /**
1669 * qla82xx_pci_config() - Setup ISP82xx PCI configuration registers.
1670 * @vha: HA context
1671 *
1672 * Returns 0 on success.
1673 */
1674 int
qla82xx_pci_config(scsi_qla_host_t * vha)1675 qla82xx_pci_config(scsi_qla_host_t *vha)
1676 {
1677 struct qla_hw_data *ha = vha->hw;
1678 int ret;
1679
1680 pci_set_master(ha->pdev);
1681 ret = pci_set_mwi(ha->pdev);
1682 ha->chip_revision = ha->pdev->revision;
1683 ql_dbg(ql_dbg_init, vha, 0x0043,
1684 "Chip revision:%d; pci_set_mwi() returned %d.\n",
1685 ha->chip_revision, ret);
1686 return 0;
1687 }
1688
1689 /**
1690 * qla82xx_reset_chip() - Setup ISP82xx PCI configuration registers.
1691 * @vha: HA context
1692 *
1693 * Returns 0 on success.
1694 */
1695 int
qla82xx_reset_chip(scsi_qla_host_t * vha)1696 qla82xx_reset_chip(scsi_qla_host_t *vha)
1697 {
1698 struct qla_hw_data *ha = vha->hw;
1699
1700 ha->isp_ops->disable_intrs(ha);
1701
1702 return QLA_SUCCESS;
1703 }
1704
qla82xx_config_rings(struct scsi_qla_host * vha)1705 void qla82xx_config_rings(struct scsi_qla_host *vha)
1706 {
1707 struct qla_hw_data *ha = vha->hw;
1708 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1709 struct init_cb_81xx *icb;
1710 struct req_que *req = ha->req_q_map[0];
1711 struct rsp_que *rsp = ha->rsp_q_map[0];
1712
1713 /* Setup ring parameters in initialization control block. */
1714 icb = (struct init_cb_81xx *)ha->init_cb;
1715 icb->request_q_outpointer = cpu_to_le16(0);
1716 icb->response_q_inpointer = cpu_to_le16(0);
1717 icb->request_q_length = cpu_to_le16(req->length);
1718 icb->response_q_length = cpu_to_le16(rsp->length);
1719 put_unaligned_le64(req->dma, &icb->request_q_address);
1720 put_unaligned_le64(rsp->dma, &icb->response_q_address);
1721
1722 wrt_reg_dword(®->req_q_out[0], 0);
1723 wrt_reg_dword(®->rsp_q_in[0], 0);
1724 wrt_reg_dword(®->rsp_q_out[0], 0);
1725 }
1726
1727 static int
qla82xx_fw_load_from_blob(struct qla_hw_data * ha)1728 qla82xx_fw_load_from_blob(struct qla_hw_data *ha)
1729 {
1730 u64 *ptr64;
1731 u32 i, flashaddr, size;
1732 __le64 data;
1733
1734 size = (IMAGE_START - BOOTLD_START) / 8;
1735
1736 ptr64 = (u64 *)qla82xx_get_bootld_offset(ha);
1737 flashaddr = BOOTLD_START;
1738
1739 for (i = 0; i < size; i++) {
1740 data = cpu_to_le64(ptr64[i]);
1741 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1742 return -EIO;
1743 flashaddr += 8;
1744 }
1745
1746 flashaddr = FLASH_ADDR_START;
1747 size = qla82xx_get_fw_size(ha) / 8;
1748 ptr64 = (u64 *)qla82xx_get_fw_offs(ha);
1749
1750 for (i = 0; i < size; i++) {
1751 data = cpu_to_le64(ptr64[i]);
1752
1753 if (qla82xx_pci_mem_write_2M(ha, flashaddr, &data, 8))
1754 return -EIO;
1755 flashaddr += 8;
1756 }
1757 udelay(100);
1758
1759 /* Write a magic value to CAMRAM register
1760 * at a specified offset to indicate
1761 * that all data is written and
1762 * ready for firmware to initialize.
1763 */
1764 qla82xx_wr_32(ha, QLA82XX_CAM_RAM(0x1fc), QLA82XX_BDINFO_MAGIC);
1765
1766 read_lock(&ha->hw_lock);
1767 qla82xx_wr_32(ha, QLA82XX_CRB_PEG_NET_0 + 0x18, 0x1020);
1768 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, 0x80001e);
1769 read_unlock(&ha->hw_lock);
1770 return 0;
1771 }
1772
1773 static int
qla82xx_set_product_offset(struct qla_hw_data * ha)1774 qla82xx_set_product_offset(struct qla_hw_data *ha)
1775 {
1776 struct qla82xx_uri_table_desc *ptab_desc = NULL;
1777 const uint8_t *unirom = ha->hablob->fw->data;
1778 uint32_t i;
1779 uint32_t entries;
1780 uint32_t flags, file_chiprev, offset;
1781 uint8_t chiprev = ha->chip_revision;
1782 /* Hardcoding mn_present flag for P3P */
1783 int mn_present = 0;
1784 uint32_t flagbit;
1785
1786 ptab_desc = qla82xx_get_table_desc(unirom,
1787 QLA82XX_URI_DIR_SECT_PRODUCT_TBL);
1788 if (!ptab_desc)
1789 return -1;
1790
1791 entries = le32_to_cpu(ptab_desc->num_entries);
1792
1793 for (i = 0; i < entries; i++) {
1794 offset = le32_to_cpu(ptab_desc->findex) +
1795 (i * le32_to_cpu(ptab_desc->entry_size));
1796 flags = le32_to_cpu(*((__le32 *)&unirom[offset] +
1797 QLA82XX_URI_FLAGS_OFF));
1798 file_chiprev = le32_to_cpu(*((__le32 *)&unirom[offset] +
1799 QLA82XX_URI_CHIP_REV_OFF));
1800
1801 flagbit = mn_present ? 1 : 2;
1802
1803 if ((chiprev == file_chiprev) && ((1ULL << flagbit) & flags)) {
1804 ha->file_prd_off = offset;
1805 return 0;
1806 }
1807 }
1808 return -1;
1809 }
1810
1811 static int
qla82xx_validate_firmware_blob(scsi_qla_host_t * vha,uint8_t fw_type)1812 qla82xx_validate_firmware_blob(scsi_qla_host_t *vha, uint8_t fw_type)
1813 {
1814 uint32_t val;
1815 uint32_t min_size;
1816 struct qla_hw_data *ha = vha->hw;
1817 const struct firmware *fw = ha->hablob->fw;
1818
1819 ha->fw_type = fw_type;
1820
1821 if (fw_type == QLA82XX_UNIFIED_ROMIMAGE) {
1822 if (qla82xx_set_product_offset(ha))
1823 return -EINVAL;
1824
1825 min_size = QLA82XX_URI_FW_MIN_SIZE;
1826 } else {
1827 val = get_unaligned_le32(&fw->data[QLA82XX_FW_MAGIC_OFFSET]);
1828 if (val != QLA82XX_BDINFO_MAGIC)
1829 return -EINVAL;
1830
1831 min_size = QLA82XX_FW_MIN_SIZE;
1832 }
1833
1834 if (fw->size < min_size)
1835 return -EINVAL;
1836 return 0;
1837 }
1838
1839 static int
qla82xx_check_cmdpeg_state(struct qla_hw_data * ha)1840 qla82xx_check_cmdpeg_state(struct qla_hw_data *ha)
1841 {
1842 u32 val = 0;
1843 int retries = 60;
1844 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1845
1846 do {
1847 read_lock(&ha->hw_lock);
1848 val = qla82xx_rd_32(ha, CRB_CMDPEG_STATE);
1849 read_unlock(&ha->hw_lock);
1850
1851 switch (val) {
1852 case PHAN_INITIALIZE_COMPLETE:
1853 case PHAN_INITIALIZE_ACK:
1854 return QLA_SUCCESS;
1855 case PHAN_INITIALIZE_FAILED:
1856 break;
1857 default:
1858 break;
1859 }
1860 ql_log(ql_log_info, vha, 0x00a8,
1861 "CRB_CMDPEG_STATE: 0x%x and retries:0x%x.\n",
1862 val, retries);
1863
1864 msleep(500);
1865
1866 } while (--retries);
1867
1868 ql_log(ql_log_fatal, vha, 0x00a9,
1869 "Cmd Peg initialization failed: 0x%x.\n", val);
1870
1871 val = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_PEGTUNE_DONE);
1872 read_lock(&ha->hw_lock);
1873 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, PHAN_INITIALIZE_FAILED);
1874 read_unlock(&ha->hw_lock);
1875 return QLA_FUNCTION_FAILED;
1876 }
1877
1878 static int
qla82xx_check_rcvpeg_state(struct qla_hw_data * ha)1879 qla82xx_check_rcvpeg_state(struct qla_hw_data *ha)
1880 {
1881 u32 val = 0;
1882 int retries = 60;
1883 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
1884
1885 do {
1886 read_lock(&ha->hw_lock);
1887 val = qla82xx_rd_32(ha, CRB_RCVPEG_STATE);
1888 read_unlock(&ha->hw_lock);
1889
1890 switch (val) {
1891 case PHAN_INITIALIZE_COMPLETE:
1892 case PHAN_INITIALIZE_ACK:
1893 return QLA_SUCCESS;
1894 case PHAN_INITIALIZE_FAILED:
1895 break;
1896 default:
1897 break;
1898 }
1899 ql_log(ql_log_info, vha, 0x00ab,
1900 "CRB_RCVPEG_STATE: 0x%x and retries: 0x%x.\n",
1901 val, retries);
1902
1903 msleep(500);
1904
1905 } while (--retries);
1906
1907 ql_log(ql_log_fatal, vha, 0x00ac,
1908 "Rcv Peg initialization failed: 0x%x.\n", val);
1909 read_lock(&ha->hw_lock);
1910 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, PHAN_INITIALIZE_FAILED);
1911 read_unlock(&ha->hw_lock);
1912 return QLA_FUNCTION_FAILED;
1913 }
1914
1915 /* ISR related functions */
1916 static struct qla82xx_legacy_intr_set legacy_intr[] =
1917 QLA82XX_LEGACY_INTR_CONFIG;
1918
1919 /*
1920 * qla82xx_mbx_completion() - Process mailbox command completions.
1921 * @ha: SCSI driver HA context
1922 * @mb0: Mailbox0 register
1923 */
1924 void
qla82xx_mbx_completion(scsi_qla_host_t * vha,uint16_t mb0)1925 qla82xx_mbx_completion(scsi_qla_host_t *vha, uint16_t mb0)
1926 {
1927 uint16_t cnt;
1928 __le16 __iomem *wptr;
1929 struct qla_hw_data *ha = vha->hw;
1930 struct device_reg_82xx __iomem *reg = &ha->iobase->isp82;
1931
1932 wptr = ®->mailbox_out[1];
1933
1934 /* Load return mailbox registers. */
1935 ha->flags.mbox_int = 1;
1936 ha->mailbox_out[0] = mb0;
1937
1938 for (cnt = 1; cnt < ha->mbx_count; cnt++) {
1939 ha->mailbox_out[cnt] = rd_reg_word(wptr);
1940 wptr++;
1941 }
1942
1943 if (!ha->mcp)
1944 ql_dbg(ql_dbg_async, vha, 0x5053,
1945 "MBX pointer ERROR.\n");
1946 }
1947
1948 /**
1949 * qla82xx_intr_handler() - Process interrupts for the ISP23xx and ISP63xx.
1950 * @irq: interrupt number
1951 * @dev_id: SCSI driver HA context
1952 *
1953 * Called by system whenever the host adapter generates an interrupt.
1954 *
1955 * Returns handled flag.
1956 */
1957 irqreturn_t
qla82xx_intr_handler(int irq,void * dev_id)1958 qla82xx_intr_handler(int irq, void *dev_id)
1959 {
1960 scsi_qla_host_t *vha;
1961 struct qla_hw_data *ha;
1962 struct rsp_que *rsp;
1963 struct device_reg_82xx __iomem *reg;
1964 int status = 0, status1 = 0;
1965 unsigned long flags;
1966 unsigned long iter;
1967 uint32_t stat = 0;
1968 uint16_t mb[8];
1969
1970 rsp = (struct rsp_que *) dev_id;
1971 if (!rsp) {
1972 ql_log(ql_log_info, NULL, 0xb053,
1973 "%s: NULL response queue pointer.\n", __func__);
1974 return IRQ_NONE;
1975 }
1976 ha = rsp->hw;
1977
1978 if (!ha->flags.msi_enabled) {
1979 status = qla82xx_rd_32(ha, ISR_INT_VECTOR);
1980 if (!(status & ha->nx_legacy_intr.int_vec_bit))
1981 return IRQ_NONE;
1982
1983 status1 = qla82xx_rd_32(ha, ISR_INT_STATE_REG);
1984 if (!ISR_IS_LEGACY_INTR_TRIGGERED(status1))
1985 return IRQ_NONE;
1986 }
1987
1988 /* clear the interrupt */
1989 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_status_reg, 0xffffffff);
1990
1991 /* read twice to ensure write is flushed */
1992 qla82xx_rd_32(ha, ISR_INT_VECTOR);
1993 qla82xx_rd_32(ha, ISR_INT_VECTOR);
1994
1995 reg = &ha->iobase->isp82;
1996
1997 spin_lock_irqsave(&ha->hardware_lock, flags);
1998 vha = pci_get_drvdata(ha->pdev);
1999 for (iter = 1; iter--; ) {
2000
2001 if (rd_reg_dword(®->host_int)) {
2002 stat = rd_reg_dword(®->host_status);
2003
2004 switch (stat & 0xff) {
2005 case 0x1:
2006 case 0x2:
2007 case 0x10:
2008 case 0x11:
2009 qla82xx_mbx_completion(vha, MSW(stat));
2010 status |= MBX_INTERRUPT;
2011 break;
2012 case 0x12:
2013 mb[0] = MSW(stat);
2014 mb[1] = rd_reg_word(®->mailbox_out[1]);
2015 mb[2] = rd_reg_word(®->mailbox_out[2]);
2016 mb[3] = rd_reg_word(®->mailbox_out[3]);
2017 qla2x00_async_event(vha, rsp, mb);
2018 break;
2019 case 0x13:
2020 qla24xx_process_response_queue(vha, rsp);
2021 break;
2022 default:
2023 ql_dbg(ql_dbg_async, vha, 0x5054,
2024 "Unrecognized interrupt type (%d).\n",
2025 stat & 0xff);
2026 break;
2027 }
2028 }
2029 wrt_reg_dword(®->host_int, 0);
2030 }
2031
2032 qla2x00_handle_mbx_completion(ha, status);
2033 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2034
2035 if (!ha->flags.msi_enabled)
2036 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2037
2038 return IRQ_HANDLED;
2039 }
2040
2041 irqreturn_t
qla82xx_msix_default(int irq,void * dev_id)2042 qla82xx_msix_default(int irq, void *dev_id)
2043 {
2044 scsi_qla_host_t *vha;
2045 struct qla_hw_data *ha;
2046 struct rsp_que *rsp;
2047 struct device_reg_82xx __iomem *reg;
2048 int status = 0;
2049 unsigned long flags;
2050 uint32_t stat = 0;
2051 uint32_t host_int = 0;
2052 uint16_t mb[8];
2053
2054 rsp = (struct rsp_que *) dev_id;
2055 if (!rsp) {
2056 printk(KERN_INFO
2057 "%s(): NULL response queue pointer.\n", __func__);
2058 return IRQ_NONE;
2059 }
2060 ha = rsp->hw;
2061
2062 reg = &ha->iobase->isp82;
2063
2064 spin_lock_irqsave(&ha->hardware_lock, flags);
2065 vha = pci_get_drvdata(ha->pdev);
2066 do {
2067 host_int = rd_reg_dword(®->host_int);
2068 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2069 break;
2070 if (host_int) {
2071 stat = rd_reg_dword(®->host_status);
2072
2073 switch (stat & 0xff) {
2074 case 0x1:
2075 case 0x2:
2076 case 0x10:
2077 case 0x11:
2078 qla82xx_mbx_completion(vha, MSW(stat));
2079 status |= MBX_INTERRUPT;
2080 break;
2081 case 0x12:
2082 mb[0] = MSW(stat);
2083 mb[1] = rd_reg_word(®->mailbox_out[1]);
2084 mb[2] = rd_reg_word(®->mailbox_out[2]);
2085 mb[3] = rd_reg_word(®->mailbox_out[3]);
2086 qla2x00_async_event(vha, rsp, mb);
2087 break;
2088 case 0x13:
2089 qla24xx_process_response_queue(vha, rsp);
2090 break;
2091 default:
2092 ql_dbg(ql_dbg_async, vha, 0x5041,
2093 "Unrecognized interrupt type (%d).\n",
2094 stat & 0xff);
2095 break;
2096 }
2097 }
2098 wrt_reg_dword(®->host_int, 0);
2099 } while (0);
2100
2101 qla2x00_handle_mbx_completion(ha, status);
2102 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2103
2104 return IRQ_HANDLED;
2105 }
2106
2107 irqreturn_t
qla82xx_msix_rsp_q(int irq,void * dev_id)2108 qla82xx_msix_rsp_q(int irq, void *dev_id)
2109 {
2110 scsi_qla_host_t *vha;
2111 struct qla_hw_data *ha;
2112 struct rsp_que *rsp;
2113 struct device_reg_82xx __iomem *reg;
2114 unsigned long flags;
2115 uint32_t host_int = 0;
2116
2117 rsp = (struct rsp_que *) dev_id;
2118 if (!rsp) {
2119 printk(KERN_INFO
2120 "%s(): NULL response queue pointer.\n", __func__);
2121 return IRQ_NONE;
2122 }
2123
2124 ha = rsp->hw;
2125 reg = &ha->iobase->isp82;
2126 spin_lock_irqsave(&ha->hardware_lock, flags);
2127 vha = pci_get_drvdata(ha->pdev);
2128 host_int = rd_reg_dword(®->host_int);
2129 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2130 goto out;
2131 qla24xx_process_response_queue(vha, rsp);
2132 wrt_reg_dword(®->host_int, 0);
2133 out:
2134 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2135 return IRQ_HANDLED;
2136 }
2137
2138 void
qla82xx_poll(int irq,void * dev_id)2139 qla82xx_poll(int irq, void *dev_id)
2140 {
2141 scsi_qla_host_t *vha;
2142 struct qla_hw_data *ha;
2143 struct rsp_que *rsp;
2144 struct device_reg_82xx __iomem *reg;
2145 uint32_t stat;
2146 uint32_t host_int = 0;
2147 uint16_t mb[8];
2148 unsigned long flags;
2149
2150 rsp = (struct rsp_que *) dev_id;
2151 if (!rsp) {
2152 printk(KERN_INFO
2153 "%s(): NULL response queue pointer.\n", __func__);
2154 return;
2155 }
2156 ha = rsp->hw;
2157
2158 reg = &ha->iobase->isp82;
2159 spin_lock_irqsave(&ha->hardware_lock, flags);
2160 vha = pci_get_drvdata(ha->pdev);
2161
2162 host_int = rd_reg_dword(®->host_int);
2163 if (qla2x00_check_reg32_for_disconnect(vha, host_int))
2164 goto out;
2165 if (host_int) {
2166 stat = rd_reg_dword(®->host_status);
2167 switch (stat & 0xff) {
2168 case 0x1:
2169 case 0x2:
2170 case 0x10:
2171 case 0x11:
2172 qla82xx_mbx_completion(vha, MSW(stat));
2173 break;
2174 case 0x12:
2175 mb[0] = MSW(stat);
2176 mb[1] = rd_reg_word(®->mailbox_out[1]);
2177 mb[2] = rd_reg_word(®->mailbox_out[2]);
2178 mb[3] = rd_reg_word(®->mailbox_out[3]);
2179 qla2x00_async_event(vha, rsp, mb);
2180 break;
2181 case 0x13:
2182 qla24xx_process_response_queue(vha, rsp);
2183 break;
2184 default:
2185 ql_dbg(ql_dbg_p3p, vha, 0xb013,
2186 "Unrecognized interrupt type (%d).\n",
2187 stat * 0xff);
2188 break;
2189 }
2190 wrt_reg_dword(®->host_int, 0);
2191 }
2192 out:
2193 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2194 }
2195
2196 void
qla82xx_enable_intrs(struct qla_hw_data * ha)2197 qla82xx_enable_intrs(struct qla_hw_data *ha)
2198 {
2199 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2200
2201 qla82xx_mbx_intr_enable(vha);
2202 spin_lock_irq(&ha->hardware_lock);
2203 if (IS_QLA8044(ha))
2204 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 0);
2205 else
2206 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0xfbff);
2207 spin_unlock_irq(&ha->hardware_lock);
2208 ha->interrupts_on = 1;
2209 }
2210
2211 void
qla82xx_disable_intrs(struct qla_hw_data * ha)2212 qla82xx_disable_intrs(struct qla_hw_data *ha)
2213 {
2214 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2215
2216 if (ha->interrupts_on)
2217 qla82xx_mbx_intr_disable(vha);
2218
2219 spin_lock_irq(&ha->hardware_lock);
2220 if (IS_QLA8044(ha))
2221 qla8044_wr_reg(ha, LEG_INTR_MASK_OFFSET, 1);
2222 else
2223 qla82xx_wr_32(ha, ha->nx_legacy_intr.tgt_mask_reg, 0x0400);
2224 spin_unlock_irq(&ha->hardware_lock);
2225 ha->interrupts_on = 0;
2226 }
2227
qla82xx_init_flags(struct qla_hw_data * ha)2228 void qla82xx_init_flags(struct qla_hw_data *ha)
2229 {
2230 struct qla82xx_legacy_intr_set *nx_legacy_intr;
2231
2232 /* ISP 8021 initializations */
2233 rwlock_init(&ha->hw_lock);
2234 ha->qdr_sn_window = -1;
2235 ha->ddr_mn_window = -1;
2236 ha->curr_window = 255;
2237 ha->portnum = PCI_FUNC(ha->pdev->devfn);
2238 nx_legacy_intr = &legacy_intr[ha->portnum];
2239 ha->nx_legacy_intr.int_vec_bit = nx_legacy_intr->int_vec_bit;
2240 ha->nx_legacy_intr.tgt_status_reg = nx_legacy_intr->tgt_status_reg;
2241 ha->nx_legacy_intr.tgt_mask_reg = nx_legacy_intr->tgt_mask_reg;
2242 ha->nx_legacy_intr.pci_int_reg = nx_legacy_intr->pci_int_reg;
2243 }
2244
2245 static inline void
qla82xx_set_idc_version(scsi_qla_host_t * vha)2246 qla82xx_set_idc_version(scsi_qla_host_t *vha)
2247 {
2248 int idc_ver;
2249 uint32_t drv_active;
2250 struct qla_hw_data *ha = vha->hw;
2251
2252 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2253 if (drv_active == (QLA82XX_DRV_ACTIVE << (ha->portnum * 4))) {
2254 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_IDC_VERSION,
2255 QLA82XX_IDC_VERSION);
2256 ql_log(ql_log_info, vha, 0xb082,
2257 "IDC version updated to %d\n", QLA82XX_IDC_VERSION);
2258 } else {
2259 idc_ver = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_IDC_VERSION);
2260 if (idc_ver != QLA82XX_IDC_VERSION)
2261 ql_log(ql_log_info, vha, 0xb083,
2262 "qla2xxx driver IDC version %d is not compatible "
2263 "with IDC version %d of the other drivers\n",
2264 QLA82XX_IDC_VERSION, idc_ver);
2265 }
2266 }
2267
2268 inline void
qla82xx_set_drv_active(scsi_qla_host_t * vha)2269 qla82xx_set_drv_active(scsi_qla_host_t *vha)
2270 {
2271 uint32_t drv_active;
2272 struct qla_hw_data *ha = vha->hw;
2273
2274 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2275
2276 /* If reset value is all FF's, initialize DRV_ACTIVE */
2277 if (drv_active == 0xffffffff) {
2278 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE,
2279 QLA82XX_DRV_NOT_ACTIVE);
2280 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2281 }
2282 drv_active |= (QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2283 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2284 }
2285
2286 inline void
qla82xx_clear_drv_active(struct qla_hw_data * ha)2287 qla82xx_clear_drv_active(struct qla_hw_data *ha)
2288 {
2289 uint32_t drv_active;
2290
2291 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2292 drv_active &= ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2293 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_ACTIVE, drv_active);
2294 }
2295
2296 static inline int
qla82xx_need_reset(struct qla_hw_data * ha)2297 qla82xx_need_reset(struct qla_hw_data *ha)
2298 {
2299 uint32_t drv_state;
2300 int rval;
2301
2302 if (ha->flags.nic_core_reset_owner)
2303 return 1;
2304 else {
2305 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2306 rval = drv_state & (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2307 return rval;
2308 }
2309 }
2310
2311 static inline void
qla82xx_set_rst_ready(struct qla_hw_data * ha)2312 qla82xx_set_rst_ready(struct qla_hw_data *ha)
2313 {
2314 uint32_t drv_state;
2315 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2316
2317 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2318
2319 /* If reset value is all FF's, initialize DRV_STATE */
2320 if (drv_state == 0xffffffff) {
2321 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, QLA82XX_DRVST_NOT_RDY);
2322 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2323 }
2324 drv_state |= (QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2325 ql_dbg(ql_dbg_init, vha, 0x00bb,
2326 "drv_state = 0x%08x.\n", drv_state);
2327 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2328 }
2329
2330 static inline void
qla82xx_clear_rst_ready(struct qla_hw_data * ha)2331 qla82xx_clear_rst_ready(struct qla_hw_data *ha)
2332 {
2333 uint32_t drv_state;
2334
2335 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2336 drv_state &= ~(QLA82XX_DRVST_RST_RDY << (ha->portnum * 4));
2337 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, drv_state);
2338 }
2339
2340 static inline void
qla82xx_set_qsnt_ready(struct qla_hw_data * ha)2341 qla82xx_set_qsnt_ready(struct qla_hw_data *ha)
2342 {
2343 uint32_t qsnt_state;
2344
2345 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2346 qsnt_state |= (QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2347 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2348 }
2349
2350 void
qla82xx_clear_qsnt_ready(scsi_qla_host_t * vha)2351 qla82xx_clear_qsnt_ready(scsi_qla_host_t *vha)
2352 {
2353 struct qla_hw_data *ha = vha->hw;
2354 uint32_t qsnt_state;
2355
2356 qsnt_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2357 qsnt_state &= ~(QLA82XX_DRVST_QSNT_RDY << (ha->portnum * 4));
2358 qla82xx_wr_32(ha, QLA82XX_CRB_DRV_STATE, qsnt_state);
2359 }
2360
2361 static int
qla82xx_load_fw(scsi_qla_host_t * vha)2362 qla82xx_load_fw(scsi_qla_host_t *vha)
2363 {
2364 int rst;
2365 struct fw_blob *blob;
2366 struct qla_hw_data *ha = vha->hw;
2367
2368 if (qla82xx_pinit_from_rom(vha) != QLA_SUCCESS) {
2369 ql_log(ql_log_fatal, vha, 0x009f,
2370 "Error during CRB initialization.\n");
2371 return QLA_FUNCTION_FAILED;
2372 }
2373 udelay(500);
2374
2375 /* Bring QM and CAMRAM out of reset */
2376 rst = qla82xx_rd_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET);
2377 rst &= ~((1 << 28) | (1 << 24));
2378 qla82xx_wr_32(ha, QLA82XX_ROMUSB_GLB_SW_RESET, rst);
2379
2380 /*
2381 * FW Load priority:
2382 * 1) Operational firmware residing in flash.
2383 * 2) Firmware via request-firmware interface (.bin file).
2384 */
2385 if (ql2xfwloadbin == 2)
2386 goto try_blob_fw;
2387
2388 ql_log(ql_log_info, vha, 0x00a0,
2389 "Attempting to load firmware from flash.\n");
2390
2391 if (qla82xx_fw_load_from_flash(ha) == QLA_SUCCESS) {
2392 ql_log(ql_log_info, vha, 0x00a1,
2393 "Firmware loaded successfully from flash.\n");
2394 return QLA_SUCCESS;
2395 } else {
2396 ql_log(ql_log_warn, vha, 0x0108,
2397 "Firmware load from flash failed.\n");
2398 }
2399
2400 try_blob_fw:
2401 ql_log(ql_log_info, vha, 0x00a2,
2402 "Attempting to load firmware from blob.\n");
2403
2404 /* Load firmware blob. */
2405 blob = ha->hablob = qla2x00_request_firmware(vha);
2406 if (!blob) {
2407 ql_log(ql_log_fatal, vha, 0x00a3,
2408 "Firmware image not present.\n");
2409 goto fw_load_failed;
2410 }
2411
2412 /* Validating firmware blob */
2413 if (qla82xx_validate_firmware_blob(vha,
2414 QLA82XX_FLASH_ROMIMAGE)) {
2415 /* Fallback to URI format */
2416 if (qla82xx_validate_firmware_blob(vha,
2417 QLA82XX_UNIFIED_ROMIMAGE)) {
2418 ql_log(ql_log_fatal, vha, 0x00a4,
2419 "No valid firmware image found.\n");
2420 return QLA_FUNCTION_FAILED;
2421 }
2422 }
2423
2424 if (qla82xx_fw_load_from_blob(ha) == QLA_SUCCESS) {
2425 ql_log(ql_log_info, vha, 0x00a5,
2426 "Firmware loaded successfully from binary blob.\n");
2427 return QLA_SUCCESS;
2428 }
2429
2430 ql_log(ql_log_fatal, vha, 0x00a6,
2431 "Firmware load failed for binary blob.\n");
2432 blob->fw = NULL;
2433 blob = NULL;
2434
2435 fw_load_failed:
2436 return QLA_FUNCTION_FAILED;
2437 }
2438
2439 int
qla82xx_start_firmware(scsi_qla_host_t * vha)2440 qla82xx_start_firmware(scsi_qla_host_t *vha)
2441 {
2442 uint16_t lnk;
2443 struct qla_hw_data *ha = vha->hw;
2444
2445 /* scrub dma mask expansion register */
2446 qla82xx_wr_32(ha, CRB_DMA_SHIFT, QLA82XX_DMA_SHIFT_VALUE);
2447
2448 /* Put both the PEG CMD and RCV PEG to default state
2449 * of 0 before resetting the hardware
2450 */
2451 qla82xx_wr_32(ha, CRB_CMDPEG_STATE, 0);
2452 qla82xx_wr_32(ha, CRB_RCVPEG_STATE, 0);
2453
2454 /* Overwrite stale initialization register values */
2455 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS1, 0);
2456 qla82xx_wr_32(ha, QLA82XX_PEG_HALT_STATUS2, 0);
2457
2458 if (qla82xx_load_fw(vha) != QLA_SUCCESS) {
2459 ql_log(ql_log_fatal, vha, 0x00a7,
2460 "Error trying to start fw.\n");
2461 return QLA_FUNCTION_FAILED;
2462 }
2463
2464 /* Handshake with the card before we register the devices. */
2465 if (qla82xx_check_cmdpeg_state(ha) != QLA_SUCCESS) {
2466 ql_log(ql_log_fatal, vha, 0x00aa,
2467 "Error during card handshake.\n");
2468 return QLA_FUNCTION_FAILED;
2469 }
2470
2471 /* Negotiated Link width */
2472 pcie_capability_read_word(ha->pdev, PCI_EXP_LNKSTA, &lnk);
2473 ha->link_width = (lnk >> 4) & 0x3f;
2474
2475 /* Synchronize with Receive peg */
2476 return qla82xx_check_rcvpeg_state(ha);
2477 }
2478
2479 static __le32 *
qla82xx_read_flash_data(scsi_qla_host_t * vha,__le32 * dwptr,uint32_t faddr,uint32_t length)2480 qla82xx_read_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr,
2481 uint32_t length)
2482 {
2483 uint32_t i;
2484 uint32_t val;
2485 struct qla_hw_data *ha = vha->hw;
2486
2487 /* Dword reads to flash. */
2488 for (i = 0; i < length/4; i++, faddr += 4) {
2489 if (qla82xx_rom_fast_read(ha, faddr, &val)) {
2490 ql_log(ql_log_warn, vha, 0x0106,
2491 "Do ROM fast read failed.\n");
2492 goto done_read;
2493 }
2494 dwptr[i] = cpu_to_le32(val);
2495 }
2496 done_read:
2497 return dwptr;
2498 }
2499
2500 static int
qla82xx_unprotect_flash(struct qla_hw_data * ha)2501 qla82xx_unprotect_flash(struct qla_hw_data *ha)
2502 {
2503 int ret;
2504 uint32_t val;
2505 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2506
2507 ret = ql82xx_rom_lock_d(ha);
2508 if (ret < 0) {
2509 ql_log(ql_log_warn, vha, 0xb014,
2510 "ROM Lock failed.\n");
2511 return ret;
2512 }
2513
2514 ret = qla82xx_read_status_reg(ha, &val);
2515 if (ret < 0)
2516 goto done_unprotect;
2517
2518 val &= ~(BLOCK_PROTECT_BITS << 2);
2519 ret = qla82xx_write_status_reg(ha, val);
2520 if (ret < 0) {
2521 val |= (BLOCK_PROTECT_BITS << 2);
2522 qla82xx_write_status_reg(ha, val);
2523 }
2524
2525 if (qla82xx_write_disable_flash(ha) != 0)
2526 ql_log(ql_log_warn, vha, 0xb015,
2527 "Write disable failed.\n");
2528
2529 done_unprotect:
2530 qla82xx_rom_unlock(ha);
2531 return ret;
2532 }
2533
2534 static int
qla82xx_protect_flash(struct qla_hw_data * ha)2535 qla82xx_protect_flash(struct qla_hw_data *ha)
2536 {
2537 int ret;
2538 uint32_t val;
2539 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2540
2541 ret = ql82xx_rom_lock_d(ha);
2542 if (ret < 0) {
2543 ql_log(ql_log_warn, vha, 0xb016,
2544 "ROM Lock failed.\n");
2545 return ret;
2546 }
2547
2548 ret = qla82xx_read_status_reg(ha, &val);
2549 if (ret < 0)
2550 goto done_protect;
2551
2552 val |= (BLOCK_PROTECT_BITS << 2);
2553 /* LOCK all sectors */
2554 ret = qla82xx_write_status_reg(ha, val);
2555 if (ret < 0)
2556 ql_log(ql_log_warn, vha, 0xb017,
2557 "Write status register failed.\n");
2558
2559 if (qla82xx_write_disable_flash(ha) != 0)
2560 ql_log(ql_log_warn, vha, 0xb018,
2561 "Write disable failed.\n");
2562 done_protect:
2563 qla82xx_rom_unlock(ha);
2564 return ret;
2565 }
2566
2567 static int
qla82xx_erase_sector(struct qla_hw_data * ha,int addr)2568 qla82xx_erase_sector(struct qla_hw_data *ha, int addr)
2569 {
2570 int ret = 0;
2571 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2572
2573 ret = ql82xx_rom_lock_d(ha);
2574 if (ret < 0) {
2575 ql_log(ql_log_warn, vha, 0xb019,
2576 "ROM Lock failed.\n");
2577 return ret;
2578 }
2579
2580 qla82xx_flash_set_write_enable(ha);
2581 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ADDRESS, addr);
2582 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_ABYTE_CNT, 3);
2583 qla82xx_wr_32(ha, QLA82XX_ROMUSB_ROM_INSTR_OPCODE, M25P_INSTR_SE);
2584
2585 if (qla82xx_wait_rom_done(ha)) {
2586 ql_log(ql_log_warn, vha, 0xb01a,
2587 "Error waiting for rom done.\n");
2588 ret = -1;
2589 goto done;
2590 }
2591 ret = qla82xx_flash_wait_write_finish(ha);
2592 done:
2593 qla82xx_rom_unlock(ha);
2594 return ret;
2595 }
2596
2597 /*
2598 * Address and length are byte address
2599 */
2600 void *
qla82xx_read_optrom_data(struct scsi_qla_host * vha,void * buf,uint32_t offset,uint32_t length)2601 qla82xx_read_optrom_data(struct scsi_qla_host *vha, void *buf,
2602 uint32_t offset, uint32_t length)
2603 {
2604 scsi_block_requests(vha->host);
2605 qla82xx_read_flash_data(vha, buf, offset, length);
2606 scsi_unblock_requests(vha->host);
2607 return buf;
2608 }
2609
2610 static int
qla82xx_write_flash_data(struct scsi_qla_host * vha,__le32 * dwptr,uint32_t faddr,uint32_t dwords)2611 qla82xx_write_flash_data(struct scsi_qla_host *vha, __le32 *dwptr,
2612 uint32_t faddr, uint32_t dwords)
2613 {
2614 int ret;
2615 uint32_t liter;
2616 uint32_t rest_addr;
2617 dma_addr_t optrom_dma;
2618 void *optrom = NULL;
2619 int page_mode = 0;
2620 struct qla_hw_data *ha = vha->hw;
2621
2622 ret = -1;
2623
2624 /* Prepare burst-capable write on supported ISPs. */
2625 if (page_mode && !(faddr & 0xfff) &&
2626 dwords > OPTROM_BURST_DWORDS) {
2627 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE,
2628 &optrom_dma, GFP_KERNEL);
2629 if (!optrom) {
2630 ql_log(ql_log_warn, vha, 0xb01b,
2631 "Unable to allocate memory "
2632 "for optrom burst write (%x KB).\n",
2633 OPTROM_BURST_SIZE / 1024);
2634 }
2635 }
2636
2637 rest_addr = ha->fdt_block_size - 1;
2638
2639 ret = qla82xx_unprotect_flash(ha);
2640 if (ret) {
2641 ql_log(ql_log_warn, vha, 0xb01c,
2642 "Unable to unprotect flash for update.\n");
2643 goto write_done;
2644 }
2645
2646 for (liter = 0; liter < dwords; liter++, faddr += 4, dwptr++) {
2647 /* Are we at the beginning of a sector? */
2648 if ((faddr & rest_addr) == 0) {
2649
2650 ret = qla82xx_erase_sector(ha, faddr);
2651 if (ret) {
2652 ql_log(ql_log_warn, vha, 0xb01d,
2653 "Unable to erase sector: address=%x.\n",
2654 faddr);
2655 break;
2656 }
2657 }
2658
2659 /* Go with burst-write. */
2660 if (optrom && (liter + OPTROM_BURST_DWORDS) <= dwords) {
2661 /* Copy data to DMA'ble buffer. */
2662 memcpy(optrom, dwptr, OPTROM_BURST_SIZE);
2663
2664 ret = qla2x00_load_ram(vha, optrom_dma,
2665 (ha->flash_data_off | faddr),
2666 OPTROM_BURST_DWORDS);
2667 if (ret != QLA_SUCCESS) {
2668 ql_log(ql_log_warn, vha, 0xb01e,
2669 "Unable to burst-write optrom segment "
2670 "(%x/%x/%llx).\n", ret,
2671 (ha->flash_data_off | faddr),
2672 (unsigned long long)optrom_dma);
2673 ql_log(ql_log_warn, vha, 0xb01f,
2674 "Reverting to slow-write.\n");
2675
2676 dma_free_coherent(&ha->pdev->dev,
2677 OPTROM_BURST_SIZE, optrom, optrom_dma);
2678 optrom = NULL;
2679 } else {
2680 liter += OPTROM_BURST_DWORDS - 1;
2681 faddr += OPTROM_BURST_DWORDS - 1;
2682 dwptr += OPTROM_BURST_DWORDS - 1;
2683 continue;
2684 }
2685 }
2686
2687 ret = qla82xx_write_flash_dword(ha, faddr,
2688 le32_to_cpu(*dwptr));
2689 if (ret) {
2690 ql_dbg(ql_dbg_p3p, vha, 0xb020,
2691 "Unable to program flash address=%x data=%x.\n",
2692 faddr, *dwptr);
2693 break;
2694 }
2695 }
2696
2697 ret = qla82xx_protect_flash(ha);
2698 if (ret)
2699 ql_log(ql_log_warn, vha, 0xb021,
2700 "Unable to protect flash after update.\n");
2701 write_done:
2702 if (optrom)
2703 dma_free_coherent(&ha->pdev->dev,
2704 OPTROM_BURST_SIZE, optrom, optrom_dma);
2705 return ret;
2706 }
2707
2708 int
qla82xx_write_optrom_data(struct scsi_qla_host * vha,void * buf,uint32_t offset,uint32_t length)2709 qla82xx_write_optrom_data(struct scsi_qla_host *vha, void *buf,
2710 uint32_t offset, uint32_t length)
2711 {
2712 int rval;
2713
2714 /* Suspend HBA. */
2715 scsi_block_requests(vha->host);
2716 rval = qla82xx_write_flash_data(vha, buf, offset, length >> 2);
2717 scsi_unblock_requests(vha->host);
2718
2719 /* Convert return ISP82xx to generic */
2720 if (rval)
2721 rval = QLA_FUNCTION_FAILED;
2722 else
2723 rval = QLA_SUCCESS;
2724 return rval;
2725 }
2726
2727 void
qla82xx_start_iocbs(scsi_qla_host_t * vha)2728 qla82xx_start_iocbs(scsi_qla_host_t *vha)
2729 {
2730 struct qla_hw_data *ha = vha->hw;
2731 struct req_que *req = ha->req_q_map[0];
2732 uint32_t dbval;
2733
2734 /* Adjust ring index. */
2735 req->ring_index++;
2736 if (req->ring_index == req->length) {
2737 req->ring_index = 0;
2738 req->ring_ptr = req->ring;
2739 } else
2740 req->ring_ptr++;
2741
2742 dbval = 0x04 | (ha->portnum << 5);
2743
2744 dbval = dbval | (req->id << 8) | (req->ring_index << 16);
2745 if (ql2xdbwr)
2746 qla82xx_wr_32(ha, (unsigned long)ha->nxdb_wr_ptr, dbval);
2747 else {
2748 wrt_reg_dword(ha->nxdb_wr_ptr, dbval);
2749 wmb();
2750 while (rd_reg_dword(ha->nxdb_rd_ptr) != dbval) {
2751 wrt_reg_dword(ha->nxdb_wr_ptr, dbval);
2752 wmb();
2753 }
2754 }
2755 }
2756
2757 static void
qla82xx_rom_lock_recovery(struct qla_hw_data * ha)2758 qla82xx_rom_lock_recovery(struct qla_hw_data *ha)
2759 {
2760 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev);
2761 uint32_t lock_owner = 0;
2762
2763 if (qla82xx_rom_lock(ha)) {
2764 lock_owner = qla82xx_rd_32(ha, QLA82XX_ROM_LOCK_ID);
2765 /* Someone else is holding the lock. */
2766 ql_log(ql_log_info, vha, 0xb022,
2767 "Resetting rom_lock, Lock Owner %u.\n", lock_owner);
2768 }
2769 /*
2770 * Either we got the lock, or someone
2771 * else died while holding it.
2772 * In either case, unlock.
2773 */
2774 qla82xx_rom_unlock(ha);
2775 }
2776
2777 /*
2778 * qla82xx_device_bootstrap
2779 * Initialize device, set DEV_READY, start fw
2780 *
2781 * Note:
2782 * IDC lock must be held upon entry
2783 *
2784 * Return:
2785 * Success : 0
2786 * Failed : 1
2787 */
2788 static int
qla82xx_device_bootstrap(scsi_qla_host_t * vha)2789 qla82xx_device_bootstrap(scsi_qla_host_t *vha)
2790 {
2791 int rval = QLA_SUCCESS;
2792 int i;
2793 uint32_t old_count, count;
2794 struct qla_hw_data *ha = vha->hw;
2795 int need_reset = 0;
2796
2797 need_reset = qla82xx_need_reset(ha);
2798
2799 if (need_reset) {
2800 /* We are trying to perform a recovery here. */
2801 if (ha->flags.isp82xx_fw_hung)
2802 qla82xx_rom_lock_recovery(ha);
2803 } else {
2804 old_count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2805 for (i = 0; i < 10; i++) {
2806 msleep(200);
2807 count = qla82xx_rd_32(ha, QLA82XX_PEG_ALIVE_COUNTER);
2808 if (count != old_count) {
2809 rval = QLA_SUCCESS;
2810 goto dev_ready;
2811 }
2812 }
2813 qla82xx_rom_lock_recovery(ha);
2814 }
2815
2816 /* set to DEV_INITIALIZING */
2817 ql_log(ql_log_info, vha, 0x009e,
2818 "HW State: INITIALIZING.\n");
2819 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_INITIALIZING);
2820
2821 qla82xx_idc_unlock(ha);
2822 rval = qla82xx_start_firmware(vha);
2823 qla82xx_idc_lock(ha);
2824
2825 if (rval != QLA_SUCCESS) {
2826 ql_log(ql_log_fatal, vha, 0x00ad,
2827 "HW State: FAILED.\n");
2828 qla82xx_clear_drv_active(ha);
2829 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_FAILED);
2830 return rval;
2831 }
2832
2833 dev_ready:
2834 ql_log(ql_log_info, vha, 0x00ae,
2835 "HW State: READY.\n");
2836 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_READY);
2837
2838 return QLA_SUCCESS;
2839 }
2840
2841 /*
2842 * qla82xx_need_qsnt_handler
2843 * Code to start quiescence sequence
2844 *
2845 * Note:
2846 * IDC lock must be held upon entry
2847 *
2848 * Return: void
2849 */
2850
2851 static void
qla82xx_need_qsnt_handler(scsi_qla_host_t * vha)2852 qla82xx_need_qsnt_handler(scsi_qla_host_t *vha)
2853 {
2854 struct qla_hw_data *ha = vha->hw;
2855 uint32_t dev_state, drv_state, drv_active;
2856 unsigned long reset_timeout;
2857
2858 if (vha->flags.online) {
2859 /*Block any further I/O and wait for pending cmnds to complete*/
2860 qla2x00_quiesce_io(vha);
2861 }
2862
2863 /* Set the quiescence ready bit */
2864 qla82xx_set_qsnt_ready(ha);
2865
2866 /*wait for 30 secs for other functions to ack */
2867 reset_timeout = jiffies + (30 * HZ);
2868
2869 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2870 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2871 /* Its 2 that is written when qsnt is acked, moving one bit */
2872 drv_active = drv_active << 0x01;
2873
2874 while (drv_state != drv_active) {
2875
2876 if (time_after_eq(jiffies, reset_timeout)) {
2877 /* quiescence timeout, other functions didn't ack
2878 * changing the state to DEV_READY
2879 */
2880 ql_log(ql_log_info, vha, 0xb023,
2881 "%s : QUIESCENT TIMEOUT DRV_ACTIVE:%d "
2882 "DRV_STATE:%d.\n", QLA2XXX_DRIVER_NAME,
2883 drv_active, drv_state);
2884 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
2885 QLA8XXX_DEV_READY);
2886 ql_log(ql_log_info, vha, 0xb025,
2887 "HW State: DEV_READY.\n");
2888 qla82xx_idc_unlock(ha);
2889 qla2x00_perform_loop_resync(vha);
2890 qla82xx_idc_lock(ha);
2891
2892 qla82xx_clear_qsnt_ready(vha);
2893 return;
2894 }
2895
2896 qla82xx_idc_unlock(ha);
2897 msleep(1000);
2898 qla82xx_idc_lock(ha);
2899
2900 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2901 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2902 drv_active = drv_active << 0x01;
2903 }
2904 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2905 /* everyone acked so set the state to DEV_QUIESCENCE */
2906 if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT) {
2907 ql_log(ql_log_info, vha, 0xb026,
2908 "HW State: DEV_QUIESCENT.\n");
2909 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_QUIESCENT);
2910 }
2911 }
2912
2913 void
qla8xxx_dev_failed_handler(scsi_qla_host_t * vha)2914 qla8xxx_dev_failed_handler(scsi_qla_host_t *vha)
2915 {
2916 struct qla_hw_data *ha = vha->hw;
2917
2918 /* Disable the board */
2919 ql_log(ql_log_fatal, vha, 0x00b8,
2920 "Disabling the board.\n");
2921
2922 if (IS_QLA82XX(ha)) {
2923 qla82xx_clear_drv_active(ha);
2924 qla82xx_idc_unlock(ha);
2925 } else if (IS_QLA8044(ha)) {
2926 qla8044_clear_drv_active(ha);
2927 qla8044_idc_unlock(ha);
2928 }
2929
2930 /* Set DEV_FAILED flag to disable timer */
2931 vha->device_flags |= DFLG_DEV_FAILED;
2932 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16);
2933 qla2x00_mark_all_devices_lost(vha);
2934 vha->flags.online = 0;
2935 vha->flags.init_done = 0;
2936 }
2937
2938 /*
2939 * qla82xx_need_reset_handler
2940 * Code to start reset sequence
2941 *
2942 * Note:
2943 * IDC lock must be held upon entry
2944 *
2945 * Return:
2946 * Success : 0
2947 * Failed : 1
2948 */
2949 static void
qla82xx_need_reset_handler(scsi_qla_host_t * vha)2950 qla82xx_need_reset_handler(scsi_qla_host_t *vha)
2951 {
2952 uint32_t dev_state, drv_state, drv_active;
2953 uint32_t active_mask = 0;
2954 unsigned long reset_timeout;
2955 struct qla_hw_data *ha = vha->hw;
2956 struct req_que *req = ha->req_q_map[0];
2957
2958 if (vha->flags.online) {
2959 qla82xx_idc_unlock(ha);
2960 qla2x00_abort_isp_cleanup(vha);
2961 ha->isp_ops->get_flash_version(vha, req->ring);
2962 ha->isp_ops->nvram_config(vha);
2963 qla82xx_idc_lock(ha);
2964 }
2965
2966 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2967 if (!ha->flags.nic_core_reset_owner) {
2968 ql_dbg(ql_dbg_p3p, vha, 0xb028,
2969 "reset_acknowledged by 0x%x\n", ha->portnum);
2970 qla82xx_set_rst_ready(ha);
2971 } else {
2972 active_mask = ~(QLA82XX_DRV_ACTIVE << (ha->portnum * 4));
2973 drv_active &= active_mask;
2974 ql_dbg(ql_dbg_p3p, vha, 0xb029,
2975 "active_mask: 0x%08x\n", active_mask);
2976 }
2977
2978 /* wait for 10 seconds for reset ack from all functions */
2979 reset_timeout = jiffies + (ha->fcoe_reset_timeout * HZ);
2980
2981 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
2982 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
2983 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
2984
2985 ql_dbg(ql_dbg_p3p, vha, 0xb02a,
2986 "drv_state: 0x%08x, drv_active: 0x%08x, "
2987 "dev_state: 0x%08x, active_mask: 0x%08x\n",
2988 drv_state, drv_active, dev_state, active_mask);
2989
2990 while (drv_state != drv_active &&
2991 dev_state != QLA8XXX_DEV_INITIALIZING) {
2992 if (time_after_eq(jiffies, reset_timeout)) {
2993 ql_log(ql_log_warn, vha, 0x00b5,
2994 "Reset timeout.\n");
2995 break;
2996 }
2997 qla82xx_idc_unlock(ha);
2998 msleep(1000);
2999 qla82xx_idc_lock(ha);
3000 drv_state = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_STATE);
3001 drv_active = qla82xx_rd_32(ha, QLA82XX_CRB_DRV_ACTIVE);
3002 if (ha->flags.nic_core_reset_owner)
3003 drv_active &= active_mask;
3004 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3005 }
3006
3007 ql_dbg(ql_dbg_p3p, vha, 0xb02b,
3008 "drv_state: 0x%08x, drv_active: 0x%08x, "
3009 "dev_state: 0x%08x, active_mask: 0x%08x\n",
3010 drv_state, drv_active, dev_state, active_mask);
3011
3012 ql_log(ql_log_info, vha, 0x00b6,
3013 "Device state is 0x%x = %s.\n",
3014 dev_state, qdev_state(dev_state));
3015
3016 /* Force to DEV_COLD unless someone else is starting a reset */
3017 if (dev_state != QLA8XXX_DEV_INITIALIZING &&
3018 dev_state != QLA8XXX_DEV_COLD) {
3019 ql_log(ql_log_info, vha, 0x00b7,
3020 "HW State: COLD/RE-INIT.\n");
3021 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, QLA8XXX_DEV_COLD);
3022 qla82xx_set_rst_ready(ha);
3023 if (ql2xmdenable) {
3024 if (qla82xx_md_collect(vha))
3025 ql_log(ql_log_warn, vha, 0xb02c,
3026 "Minidump not collected.\n");
3027 } else
3028 ql_log(ql_log_warn, vha, 0xb04f,
3029 "Minidump disabled.\n");
3030 }
3031 }
3032
3033 int
qla82xx_check_md_needed(scsi_qla_host_t * vha)3034 qla82xx_check_md_needed(scsi_qla_host_t *vha)
3035 {
3036 struct qla_hw_data *ha = vha->hw;
3037 uint16_t fw_major_version, fw_minor_version, fw_subminor_version;
3038 int rval = QLA_SUCCESS;
3039
3040 fw_major_version = ha->fw_major_version;
3041 fw_minor_version = ha->fw_minor_version;
3042 fw_subminor_version = ha->fw_subminor_version;
3043
3044 rval = qla2x00_get_fw_version(vha);
3045 if (rval != QLA_SUCCESS)
3046 return rval;
3047
3048 if (ql2xmdenable) {
3049 if (!ha->fw_dumped) {
3050 if ((fw_major_version != ha->fw_major_version ||
3051 fw_minor_version != ha->fw_minor_version ||
3052 fw_subminor_version != ha->fw_subminor_version) ||
3053 (ha->prev_minidump_failed)) {
3054 ql_dbg(ql_dbg_p3p, vha, 0xb02d,
3055 "Firmware version differs Previous version: %d:%d:%d - New version: %d:%d:%d, prev_minidump_failed: %d.\n",
3056 fw_major_version, fw_minor_version,
3057 fw_subminor_version,
3058 ha->fw_major_version,
3059 ha->fw_minor_version,
3060 ha->fw_subminor_version,
3061 ha->prev_minidump_failed);
3062 /* Release MiniDump resources */
3063 qla82xx_md_free(vha);
3064 /* ALlocate MiniDump resources */
3065 qla82xx_md_prep(vha);
3066 }
3067 } else
3068 ql_log(ql_log_info, vha, 0xb02e,
3069 "Firmware dump available to retrieve\n");
3070 }
3071 return rval;
3072 }
3073
3074
3075 static int
qla82xx_check_fw_alive(scsi_qla_host_t * vha)3076 qla82xx_check_fw_alive(scsi_qla_host_t *vha)
3077 {
3078 uint32_t fw_heartbeat_counter;
3079 int status = 0;
3080
3081 fw_heartbeat_counter = qla82xx_rd_32(vha->hw,
3082 QLA82XX_PEG_ALIVE_COUNTER);
3083 /* all 0xff, assume AER/EEH in progress, ignore */
3084 if (fw_heartbeat_counter == 0xffffffff) {
3085 ql_dbg(ql_dbg_timer, vha, 0x6003,
3086 "FW heartbeat counter is 0xffffffff, "
3087 "returning status=%d.\n", status);
3088 return status;
3089 }
3090 if (vha->fw_heartbeat_counter == fw_heartbeat_counter) {
3091 vha->seconds_since_last_heartbeat++;
3092 /* FW not alive after 2 seconds */
3093 if (vha->seconds_since_last_heartbeat == 2) {
3094 vha->seconds_since_last_heartbeat = 0;
3095 status = 1;
3096 }
3097 } else
3098 vha->seconds_since_last_heartbeat = 0;
3099 vha->fw_heartbeat_counter = fw_heartbeat_counter;
3100 if (status)
3101 ql_dbg(ql_dbg_timer, vha, 0x6004,
3102 "Returning status=%d.\n", status);
3103 return status;
3104 }
3105
3106 /*
3107 * qla82xx_device_state_handler
3108 * Main state handler
3109 *
3110 * Note:
3111 * IDC lock must be held upon entry
3112 *
3113 * Return:
3114 * Success : 0
3115 * Failed : 1
3116 */
3117 int
qla82xx_device_state_handler(scsi_qla_host_t * vha)3118 qla82xx_device_state_handler(scsi_qla_host_t *vha)
3119 {
3120 uint32_t dev_state;
3121 uint32_t old_dev_state;
3122 int rval = QLA_SUCCESS;
3123 unsigned long dev_init_timeout;
3124 struct qla_hw_data *ha = vha->hw;
3125 int loopcount = 0;
3126
3127 qla82xx_idc_lock(ha);
3128 if (!vha->flags.init_done) {
3129 qla82xx_set_drv_active(vha);
3130 qla82xx_set_idc_version(vha);
3131 }
3132
3133 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3134 old_dev_state = dev_state;
3135 ql_log(ql_log_info, vha, 0x009b,
3136 "Device state is 0x%x = %s.\n",
3137 dev_state, qdev_state(dev_state));
3138
3139 /* wait for 30 seconds for device to go ready */
3140 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ);
3141
3142 while (1) {
3143
3144 if (time_after_eq(jiffies, dev_init_timeout)) {
3145 ql_log(ql_log_fatal, vha, 0x009c,
3146 "Device init failed.\n");
3147 rval = QLA_FUNCTION_FAILED;
3148 break;
3149 }
3150 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3151 if (old_dev_state != dev_state) {
3152 loopcount = 0;
3153 old_dev_state = dev_state;
3154 }
3155 if (loopcount < 5) {
3156 ql_log(ql_log_info, vha, 0x009d,
3157 "Device state is 0x%x = %s.\n",
3158 dev_state, qdev_state(dev_state));
3159 }
3160
3161 switch (dev_state) {
3162 case QLA8XXX_DEV_READY:
3163 ha->flags.nic_core_reset_owner = 0;
3164 goto rel_lock;
3165 case QLA8XXX_DEV_COLD:
3166 rval = qla82xx_device_bootstrap(vha);
3167 break;
3168 case QLA8XXX_DEV_INITIALIZING:
3169 qla82xx_idc_unlock(ha);
3170 msleep(1000);
3171 qla82xx_idc_lock(ha);
3172 break;
3173 case QLA8XXX_DEV_NEED_RESET:
3174 if (!ql2xdontresethba)
3175 qla82xx_need_reset_handler(vha);
3176 else {
3177 qla82xx_idc_unlock(ha);
3178 msleep(1000);
3179 qla82xx_idc_lock(ha);
3180 }
3181 dev_init_timeout = jiffies +
3182 (ha->fcoe_dev_init_timeout * HZ);
3183 break;
3184 case QLA8XXX_DEV_NEED_QUIESCENT:
3185 qla82xx_need_qsnt_handler(vha);
3186 /* Reset timeout value after quiescence handler */
3187 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout
3188 * HZ);
3189 break;
3190 case QLA8XXX_DEV_QUIESCENT:
3191 /* Owner will exit and other will wait for the state
3192 * to get changed
3193 */
3194 if (ha->flags.quiesce_owner)
3195 goto rel_lock;
3196
3197 qla82xx_idc_unlock(ha);
3198 msleep(1000);
3199 qla82xx_idc_lock(ha);
3200
3201 /* Reset timeout value after quiescence handler */
3202 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout
3203 * HZ);
3204 break;
3205 case QLA8XXX_DEV_FAILED:
3206 qla8xxx_dev_failed_handler(vha);
3207 rval = QLA_FUNCTION_FAILED;
3208 goto exit;
3209 default:
3210 qla82xx_idc_unlock(ha);
3211 msleep(1000);
3212 qla82xx_idc_lock(ha);
3213 }
3214 loopcount++;
3215 }
3216 rel_lock:
3217 qla82xx_idc_unlock(ha);
3218 exit:
3219 return rval;
3220 }
3221
qla82xx_check_temp(scsi_qla_host_t * vha)3222 static int qla82xx_check_temp(scsi_qla_host_t *vha)
3223 {
3224 uint32_t temp, temp_state, temp_val;
3225 struct qla_hw_data *ha = vha->hw;
3226
3227 temp = qla82xx_rd_32(ha, CRB_TEMP_STATE);
3228 temp_state = qla82xx_get_temp_state(temp);
3229 temp_val = qla82xx_get_temp_val(temp);
3230
3231 if (temp_state == QLA82XX_TEMP_PANIC) {
3232 ql_log(ql_log_warn, vha, 0x600e,
3233 "Device temperature %d degrees C exceeds "
3234 " maximum allowed. Hardware has been shut down.\n",
3235 temp_val);
3236 return 1;
3237 } else if (temp_state == QLA82XX_TEMP_WARN) {
3238 ql_log(ql_log_warn, vha, 0x600f,
3239 "Device temperature %d degrees C exceeds "
3240 "operating range. Immediate action needed.\n",
3241 temp_val);
3242 }
3243 return 0;
3244 }
3245
qla82xx_read_temperature(scsi_qla_host_t * vha)3246 int qla82xx_read_temperature(scsi_qla_host_t *vha)
3247 {
3248 uint32_t temp;
3249
3250 temp = qla82xx_rd_32(vha->hw, CRB_TEMP_STATE);
3251 return qla82xx_get_temp_val(temp);
3252 }
3253
qla82xx_clear_pending_mbx(scsi_qla_host_t * vha)3254 void qla82xx_clear_pending_mbx(scsi_qla_host_t *vha)
3255 {
3256 struct qla_hw_data *ha = vha->hw;
3257
3258 if (ha->flags.mbox_busy) {
3259 ha->flags.mbox_int = 1;
3260 ha->flags.mbox_busy = 0;
3261 ql_log(ql_log_warn, vha, 0x6010,
3262 "Doing premature completion of mbx command.\n");
3263 if (test_and_clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags))
3264 complete(&ha->mbx_intr_comp);
3265 }
3266 }
3267
qla82xx_watchdog(scsi_qla_host_t * vha)3268 void qla82xx_watchdog(scsi_qla_host_t *vha)
3269 {
3270 uint32_t dev_state, halt_status;
3271 struct qla_hw_data *ha = vha->hw;
3272
3273 /* don't poll if reset is going on */
3274 if (!ha->flags.nic_core_reset_hdlr_active) {
3275 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3276 if (qla82xx_check_temp(vha)) {
3277 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3278 ha->flags.isp82xx_fw_hung = 1;
3279 qla82xx_clear_pending_mbx(vha);
3280 } else if (dev_state == QLA8XXX_DEV_NEED_RESET &&
3281 !test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags)) {
3282 ql_log(ql_log_warn, vha, 0x6001,
3283 "Adapter reset needed.\n");
3284 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
3285 } else if (dev_state == QLA8XXX_DEV_NEED_QUIESCENT &&
3286 !test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) {
3287 ql_log(ql_log_warn, vha, 0x6002,
3288 "Quiescent needed.\n");
3289 set_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags);
3290 } else if (dev_state == QLA8XXX_DEV_FAILED &&
3291 !test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) &&
3292 vha->flags.online == 1) {
3293 ql_log(ql_log_warn, vha, 0xb055,
3294 "Adapter state is failed. Offlining.\n");
3295 set_bit(ISP_UNRECOVERABLE, &vha->dpc_flags);
3296 ha->flags.isp82xx_fw_hung = 1;
3297 qla82xx_clear_pending_mbx(vha);
3298 } else {
3299 if (qla82xx_check_fw_alive(vha)) {
3300 ql_dbg(ql_dbg_timer, vha, 0x6011,
3301 "disabling pause transmit on port 0 & 1.\n");
3302 qla82xx_wr_32(ha, QLA82XX_CRB_NIU + 0x98,
3303 CRB_NIU_XG_PAUSE_CTL_P0|CRB_NIU_XG_PAUSE_CTL_P1);
3304 halt_status = qla82xx_rd_32(ha,
3305 QLA82XX_PEG_HALT_STATUS1);
3306 ql_log(ql_log_info, vha, 0x6005,
3307 "dumping hw/fw registers:.\n "
3308 " PEG_HALT_STATUS1: 0x%x, PEG_HALT_STATUS2: 0x%x,.\n "
3309 " PEG_NET_0_PC: 0x%x, PEG_NET_1_PC: 0x%x,.\n "
3310 " PEG_NET_2_PC: 0x%x, PEG_NET_3_PC: 0x%x,.\n "
3311 " PEG_NET_4_PC: 0x%x.\n", halt_status,
3312 qla82xx_rd_32(ha, QLA82XX_PEG_HALT_STATUS2),
3313 qla82xx_rd_32(ha,
3314 QLA82XX_CRB_PEG_NET_0 + 0x3c),
3315 qla82xx_rd_32(ha,
3316 QLA82XX_CRB_PEG_NET_1 + 0x3c),
3317 qla82xx_rd_32(ha,
3318 QLA82XX_CRB_PEG_NET_2 + 0x3c),
3319 qla82xx_rd_32(ha,
3320 QLA82XX_CRB_PEG_NET_3 + 0x3c),
3321 qla82xx_rd_32(ha,
3322 QLA82XX_CRB_PEG_NET_4 + 0x3c));
3323 if (((halt_status & 0x1fffff00) >> 8) == 0x67)
3324 ql_log(ql_log_warn, vha, 0xb052,
3325 "Firmware aborted with "
3326 "error code 0x00006700. Device is "
3327 "being reset.\n");
3328 if (halt_status & HALT_STATUS_UNRECOVERABLE) {
3329 set_bit(ISP_UNRECOVERABLE,
3330 &vha->dpc_flags);
3331 } else {
3332 ql_log(ql_log_info, vha, 0x6006,
3333 "Detect abort needed.\n");
3334 set_bit(ISP_ABORT_NEEDED,
3335 &vha->dpc_flags);
3336 }
3337 ha->flags.isp82xx_fw_hung = 1;
3338 ql_log(ql_log_warn, vha, 0x6007, "Firmware hung.\n");
3339 qla82xx_clear_pending_mbx(vha);
3340 }
3341 }
3342 }
3343 }
3344
qla82xx_load_risc(scsi_qla_host_t * vha,uint32_t * srisc_addr)3345 int qla82xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
3346 {
3347 int rval = -1;
3348 struct qla_hw_data *ha = vha->hw;
3349
3350 if (IS_QLA82XX(ha))
3351 rval = qla82xx_device_state_handler(vha);
3352 else if (IS_QLA8044(ha)) {
3353 qla8044_idc_lock(ha);
3354 /* Decide the reset ownership */
3355 qla83xx_reset_ownership(vha);
3356 qla8044_idc_unlock(ha);
3357 rval = qla8044_device_state_handler(vha);
3358 }
3359 return rval;
3360 }
3361
3362 void
qla82xx_set_reset_owner(scsi_qla_host_t * vha)3363 qla82xx_set_reset_owner(scsi_qla_host_t *vha)
3364 {
3365 struct qla_hw_data *ha = vha->hw;
3366 uint32_t dev_state = 0;
3367
3368 if (IS_QLA82XX(ha))
3369 dev_state = qla82xx_rd_32(ha, QLA82XX_CRB_DEV_STATE);
3370 else if (IS_QLA8044(ha))
3371 dev_state = qla8044_rd_direct(vha, QLA8044_CRB_DEV_STATE_INDEX);
3372
3373 if (dev_state == QLA8XXX_DEV_READY) {
3374 ql_log(ql_log_info, vha, 0xb02f,
3375 "HW State: NEED RESET\n");
3376 if (IS_QLA82XX(ha)) {
3377 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE,
3378 QLA8XXX_DEV_NEED_RESET);
3379 ha->flags.nic_core_reset_owner = 1;
3380 ql_dbg(ql_dbg_p3p, vha, 0xb030,
3381 "reset_owner is 0x%x\n", ha->portnum);
3382 } else if (IS_QLA8044(ha))
3383 qla8044_wr_direct(vha, QLA8044_CRB_DEV_STATE_INDEX,
3384 QLA8XXX_DEV_NEED_RESET);
3385 } else
3386 ql_log(ql_log_info, vha, 0xb031,
3387 "Device state is 0x%x = %s.\n",
3388 dev_state, qdev_state(dev_state));
3389 }
3390
3391 /*
3392 * qla82xx_abort_isp
3393 * Resets ISP and aborts all outstanding commands.
3394 *
3395 * Input:
3396 * ha = adapter block pointer.
3397 *
3398 * Returns:
3399 * 0 = success
3400 */
3401 int
qla82xx_abort_isp(scsi_qla_host_t * vha)3402 qla82xx_abort_isp(scsi_qla_host_t *vha)
3403 {
3404 int rval = -1;
3405 struct qla_hw_data *ha = vha->hw;
3406
3407 if (vha->device_flags & DFLG_DEV_FAILED) {
3408 ql_log(ql_log_warn, vha, 0x8024,
3409 "Device in failed state, exiting.\n");
3410 return QLA_SUCCESS;
3411 }
3412 ha->flags.nic_core_reset_hdlr_active = 1;
3413
3414 qla82xx_idc_lock(ha);
3415 qla82xx_set_reset_owner(vha);
3416 qla82xx_idc_unlock(ha);
3417
3418 if (IS_QLA82XX(ha))
3419 rval = qla82xx_device_state_handler(vha);
3420 else if (IS_QLA8044(ha)) {
3421 qla8044_idc_lock(ha);
3422 /* Decide the reset ownership */
3423 qla83xx_reset_ownership(vha);
3424 qla8044_idc_unlock(ha);
3425 rval = qla8044_device_state_handler(vha);
3426 }
3427
3428 qla82xx_idc_lock(ha);
3429 qla82xx_clear_rst_ready(ha);
3430 qla82xx_idc_unlock(ha);
3431
3432 if (rval == QLA_SUCCESS) {
3433 ha->flags.isp82xx_fw_hung = 0;
3434 ha->flags.nic_core_reset_hdlr_active = 0;
3435 qla82xx_restart_isp(vha);
3436 }
3437
3438 if (rval) {
3439 vha->flags.online = 1;
3440 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
3441 if (ha->isp_abort_cnt == 0) {
3442 ql_log(ql_log_warn, vha, 0x8027,
3443 "ISP error recover failed - board "
3444 "disabled.\n");
3445 /*
3446 * The next call disables the board
3447 * completely.
3448 */
3449 ha->isp_ops->reset_adapter(vha);
3450 vha->flags.online = 0;
3451 clear_bit(ISP_ABORT_RETRY,
3452 &vha->dpc_flags);
3453 rval = QLA_SUCCESS;
3454 } else { /* schedule another ISP abort */
3455 ha->isp_abort_cnt--;
3456 ql_log(ql_log_warn, vha, 0x8036,
3457 "ISP abort - retry remaining %d.\n",
3458 ha->isp_abort_cnt);
3459 rval = QLA_FUNCTION_FAILED;
3460 }
3461 } else {
3462 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
3463 ql_dbg(ql_dbg_taskm, vha, 0x8029,
3464 "ISP error recovery - retrying (%d) more times.\n",
3465 ha->isp_abort_cnt);
3466 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
3467 rval = QLA_FUNCTION_FAILED;
3468 }
3469 }
3470 return rval;
3471 }
3472
3473 /*
3474 * qla82xx_fcoe_ctx_reset
3475 * Perform a quick reset and aborts all outstanding commands.
3476 * This will only perform an FCoE context reset and avoids a full blown
3477 * chip reset.
3478 *
3479 * Input:
3480 * ha = adapter block pointer.
3481 * is_reset_path = flag for identifying the reset path.
3482 *
3483 * Returns:
3484 * 0 = success
3485 */
qla82xx_fcoe_ctx_reset(scsi_qla_host_t * vha)3486 int qla82xx_fcoe_ctx_reset(scsi_qla_host_t *vha)
3487 {
3488 int rval = QLA_FUNCTION_FAILED;
3489
3490 if (vha->flags.online) {
3491 /* Abort all outstanding commands, so as to be requeued later */
3492 qla2x00_abort_isp_cleanup(vha);
3493 }
3494
3495 /* Stop currently executing firmware.
3496 * This will destroy existing FCoE context at the F/W end.
3497 */
3498 qla2x00_try_to_stop_firmware(vha);
3499
3500 /* Restart. Creates a new FCoE context on INIT_FIRMWARE. */
3501 rval = qla82xx_restart_isp(vha);
3502
3503 return rval;
3504 }
3505
3506 /*
3507 * qla2x00_wait_for_fcoe_ctx_reset
3508 * Wait till the FCoE context is reset.
3509 *
3510 * Note:
3511 * Does context switching here.
3512 * Release SPIN_LOCK (if any) before calling this routine.
3513 *
3514 * Return:
3515 * Success (fcoe_ctx reset is done) : 0
3516 * Failed (fcoe_ctx reset not completed within max loop timout ) : 1
3517 */
qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t * vha)3518 int qla2x00_wait_for_fcoe_ctx_reset(scsi_qla_host_t *vha)
3519 {
3520 int status = QLA_FUNCTION_FAILED;
3521 unsigned long wait_reset;
3522
3523 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ);
3524 while ((test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) ||
3525 test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))
3526 && time_before(jiffies, wait_reset)) {
3527
3528 set_current_state(TASK_UNINTERRUPTIBLE);
3529 schedule_timeout(HZ);
3530
3531 if (!test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) &&
3532 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) {
3533 status = QLA_SUCCESS;
3534 break;
3535 }
3536 }
3537 ql_dbg(ql_dbg_p3p, vha, 0xb027,
3538 "%s: status=%d.\n", __func__, status);
3539
3540 return status;
3541 }
3542
3543 void
qla82xx_chip_reset_cleanup(scsi_qla_host_t * vha)3544 qla82xx_chip_reset_cleanup(scsi_qla_host_t *vha)
3545 {
3546 int i, fw_state = 0;
3547 unsigned long flags;
3548 struct qla_hw_data *ha = vha->hw;
3549
3550 /* Check if 82XX firmware is alive or not
3551 * We may have arrived here from NEED_RESET
3552 * detection only
3553 */
3554 if (!ha->flags.isp82xx_fw_hung) {
3555 for (i = 0; i < 2; i++) {
3556 msleep(1000);
3557 if (IS_QLA82XX(ha))
3558 fw_state = qla82xx_check_fw_alive(vha);
3559 else if (IS_QLA8044(ha))
3560 fw_state = qla8044_check_fw_alive(vha);
3561 if (fw_state) {
3562 ha->flags.isp82xx_fw_hung = 1;
3563 qla82xx_clear_pending_mbx(vha);
3564 break;
3565 }
3566 }
3567 }
3568 ql_dbg(ql_dbg_init, vha, 0x00b0,
3569 "Entered %s fw_hung=%d.\n",
3570 __func__, ha->flags.isp82xx_fw_hung);
3571
3572 /* Abort all commands gracefully if fw NOT hung */
3573 if (!ha->flags.isp82xx_fw_hung) {
3574 int cnt, que;
3575 srb_t *sp;
3576 struct req_que *req;
3577
3578 spin_lock_irqsave(&ha->hardware_lock, flags);
3579 for (que = 0; que < ha->max_req_queues; que++) {
3580 req = ha->req_q_map[que];
3581 if (!req)
3582 continue;
3583 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) {
3584 sp = req->outstanding_cmds[cnt];
3585 if (sp) {
3586 if ((!sp->u.scmd.crc_ctx ||
3587 (sp->flags &
3588 SRB_FCP_CMND_DMA_VALID)) &&
3589 !ha->flags.isp82xx_fw_hung) {
3590 spin_unlock_irqrestore(
3591 &ha->hardware_lock, flags);
3592 if (ha->isp_ops->abort_command(sp)) {
3593 ql_log(ql_log_info, vha,
3594 0x00b1,
3595 "mbx abort failed.\n");
3596 } else {
3597 ql_log(ql_log_info, vha,
3598 0x00b2,
3599 "mbx abort success.\n");
3600 }
3601 spin_lock_irqsave(&ha->hardware_lock, flags);
3602 }
3603 }
3604 }
3605 }
3606 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3607
3608 /* Wait for pending cmds (physical and virtual) to complete */
3609 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0,
3610 WAIT_HOST) == QLA_SUCCESS) {
3611 ql_dbg(ql_dbg_init, vha, 0x00b3,
3612 "Done wait for "
3613 "pending commands.\n");
3614 } else {
3615 WARN_ON_ONCE(true);
3616 }
3617 }
3618 }
3619
3620 /* Minidump related functions */
3621 static int
qla82xx_minidump_process_control(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,__le32 ** d_ptr)3622 qla82xx_minidump_process_control(scsi_qla_host_t *vha,
3623 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3624 {
3625 struct qla_hw_data *ha = vha->hw;
3626 struct qla82xx_md_entry_crb *crb_entry;
3627 uint32_t read_value, opcode, poll_time;
3628 uint32_t addr, index, crb_addr;
3629 unsigned long wtime;
3630 struct qla82xx_md_template_hdr *tmplt_hdr;
3631 uint32_t rval = QLA_SUCCESS;
3632 int i;
3633
3634 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
3635 crb_entry = (struct qla82xx_md_entry_crb *)entry_hdr;
3636 crb_addr = crb_entry->addr;
3637
3638 for (i = 0; i < crb_entry->op_count; i++) {
3639 opcode = crb_entry->crb_ctrl.opcode;
3640 if (opcode & QLA82XX_DBG_OPCODE_WR) {
3641 qla82xx_md_rw_32(ha, crb_addr,
3642 crb_entry->value_1, 1);
3643 opcode &= ~QLA82XX_DBG_OPCODE_WR;
3644 }
3645
3646 if (opcode & QLA82XX_DBG_OPCODE_RW) {
3647 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3648 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3649 opcode &= ~QLA82XX_DBG_OPCODE_RW;
3650 }
3651
3652 if (opcode & QLA82XX_DBG_OPCODE_AND) {
3653 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3654 read_value &= crb_entry->value_2;
3655 opcode &= ~QLA82XX_DBG_OPCODE_AND;
3656 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3657 read_value |= crb_entry->value_3;
3658 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3659 }
3660 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3661 }
3662
3663 if (opcode & QLA82XX_DBG_OPCODE_OR) {
3664 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3665 read_value |= crb_entry->value_3;
3666 qla82xx_md_rw_32(ha, crb_addr, read_value, 1);
3667 opcode &= ~QLA82XX_DBG_OPCODE_OR;
3668 }
3669
3670 if (opcode & QLA82XX_DBG_OPCODE_POLL) {
3671 poll_time = crb_entry->crb_strd.poll_timeout;
3672 wtime = jiffies + poll_time;
3673 read_value = qla82xx_md_rw_32(ha, crb_addr, 0, 0);
3674
3675 do {
3676 if ((read_value & crb_entry->value_2)
3677 == crb_entry->value_1)
3678 break;
3679 else if (time_after_eq(jiffies, wtime)) {
3680 /* capturing dump failed */
3681 rval = QLA_FUNCTION_FAILED;
3682 break;
3683 } else
3684 read_value = qla82xx_md_rw_32(ha,
3685 crb_addr, 0, 0);
3686 } while (1);
3687 opcode &= ~QLA82XX_DBG_OPCODE_POLL;
3688 }
3689
3690 if (opcode & QLA82XX_DBG_OPCODE_RDSTATE) {
3691 if (crb_entry->crb_strd.state_index_a) {
3692 index = crb_entry->crb_strd.state_index_a;
3693 addr = tmplt_hdr->saved_state_array[index];
3694 } else
3695 addr = crb_addr;
3696
3697 read_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3698 index = crb_entry->crb_ctrl.state_index_v;
3699 tmplt_hdr->saved_state_array[index] = read_value;
3700 opcode &= ~QLA82XX_DBG_OPCODE_RDSTATE;
3701 }
3702
3703 if (opcode & QLA82XX_DBG_OPCODE_WRSTATE) {
3704 if (crb_entry->crb_strd.state_index_a) {
3705 index = crb_entry->crb_strd.state_index_a;
3706 addr = tmplt_hdr->saved_state_array[index];
3707 } else
3708 addr = crb_addr;
3709
3710 if (crb_entry->crb_ctrl.state_index_v) {
3711 index = crb_entry->crb_ctrl.state_index_v;
3712 read_value =
3713 tmplt_hdr->saved_state_array[index];
3714 } else
3715 read_value = crb_entry->value_1;
3716
3717 qla82xx_md_rw_32(ha, addr, read_value, 1);
3718 opcode &= ~QLA82XX_DBG_OPCODE_WRSTATE;
3719 }
3720
3721 if (opcode & QLA82XX_DBG_OPCODE_MDSTATE) {
3722 index = crb_entry->crb_ctrl.state_index_v;
3723 read_value = tmplt_hdr->saved_state_array[index];
3724 read_value <<= crb_entry->crb_ctrl.shl;
3725 read_value >>= crb_entry->crb_ctrl.shr;
3726 if (crb_entry->value_2)
3727 read_value &= crb_entry->value_2;
3728 read_value |= crb_entry->value_3;
3729 read_value += crb_entry->value_1;
3730 tmplt_hdr->saved_state_array[index] = read_value;
3731 opcode &= ~QLA82XX_DBG_OPCODE_MDSTATE;
3732 }
3733 crb_addr += crb_entry->crb_strd.addr_stride;
3734 }
3735 return rval;
3736 }
3737
3738 static void
qla82xx_minidump_process_rdocm(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,__le32 ** d_ptr)3739 qla82xx_minidump_process_rdocm(scsi_qla_host_t *vha,
3740 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3741 {
3742 struct qla_hw_data *ha = vha->hw;
3743 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3744 struct qla82xx_md_entry_rdocm *ocm_hdr;
3745 __le32 *data_ptr = *d_ptr;
3746
3747 ocm_hdr = (struct qla82xx_md_entry_rdocm *)entry_hdr;
3748 r_addr = ocm_hdr->read_addr;
3749 r_stride = ocm_hdr->read_addr_stride;
3750 loop_cnt = ocm_hdr->op_count;
3751
3752 for (i = 0; i < loop_cnt; i++) {
3753 r_value = rd_reg_dword(r_addr + ha->nx_pcibase);
3754 *data_ptr++ = cpu_to_le32(r_value);
3755 r_addr += r_stride;
3756 }
3757 *d_ptr = data_ptr;
3758 }
3759
3760 static void
qla82xx_minidump_process_rdmux(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,__le32 ** d_ptr)3761 qla82xx_minidump_process_rdmux(scsi_qla_host_t *vha,
3762 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3763 {
3764 struct qla_hw_data *ha = vha->hw;
3765 uint32_t r_addr, s_stride, s_addr, s_value, loop_cnt, i, r_value;
3766 struct qla82xx_md_entry_mux *mux_hdr;
3767 __le32 *data_ptr = *d_ptr;
3768
3769 mux_hdr = (struct qla82xx_md_entry_mux *)entry_hdr;
3770 r_addr = mux_hdr->read_addr;
3771 s_addr = mux_hdr->select_addr;
3772 s_stride = mux_hdr->select_value_stride;
3773 s_value = mux_hdr->select_value;
3774 loop_cnt = mux_hdr->op_count;
3775
3776 for (i = 0; i < loop_cnt; i++) {
3777 qla82xx_md_rw_32(ha, s_addr, s_value, 1);
3778 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3779 *data_ptr++ = cpu_to_le32(s_value);
3780 *data_ptr++ = cpu_to_le32(r_value);
3781 s_value += s_stride;
3782 }
3783 *d_ptr = data_ptr;
3784 }
3785
3786 static void
qla82xx_minidump_process_rdcrb(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,__le32 ** d_ptr)3787 qla82xx_minidump_process_rdcrb(scsi_qla_host_t *vha,
3788 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3789 {
3790 struct qla_hw_data *ha = vha->hw;
3791 uint32_t r_addr, r_stride, loop_cnt, i, r_value;
3792 struct qla82xx_md_entry_crb *crb_hdr;
3793 __le32 *data_ptr = *d_ptr;
3794
3795 crb_hdr = (struct qla82xx_md_entry_crb *)entry_hdr;
3796 r_addr = crb_hdr->addr;
3797 r_stride = crb_hdr->crb_strd.addr_stride;
3798 loop_cnt = crb_hdr->op_count;
3799
3800 for (i = 0; i < loop_cnt; i++) {
3801 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3802 *data_ptr++ = cpu_to_le32(r_addr);
3803 *data_ptr++ = cpu_to_le32(r_value);
3804 r_addr += r_stride;
3805 }
3806 *d_ptr = data_ptr;
3807 }
3808
3809 static int
qla82xx_minidump_process_l2tag(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,__le32 ** d_ptr)3810 qla82xx_minidump_process_l2tag(scsi_qla_host_t *vha,
3811 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3812 {
3813 struct qla_hw_data *ha = vha->hw;
3814 uint32_t addr, r_addr, c_addr, t_r_addr;
3815 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3816 unsigned long p_wait, w_time, p_mask;
3817 uint32_t c_value_w, c_value_r;
3818 struct qla82xx_md_entry_cache *cache_hdr;
3819 int rval = QLA_FUNCTION_FAILED;
3820 __le32 *data_ptr = *d_ptr;
3821
3822 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3823 loop_count = cache_hdr->op_count;
3824 r_addr = cache_hdr->read_addr;
3825 c_addr = cache_hdr->control_addr;
3826 c_value_w = cache_hdr->cache_ctrl.write_value;
3827
3828 t_r_addr = cache_hdr->tag_reg_addr;
3829 t_value = cache_hdr->addr_ctrl.init_tag_value;
3830 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3831 p_wait = cache_hdr->cache_ctrl.poll_wait;
3832 p_mask = cache_hdr->cache_ctrl.poll_mask;
3833
3834 for (i = 0; i < loop_count; i++) {
3835 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3836 if (c_value_w)
3837 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3838
3839 if (p_mask) {
3840 w_time = jiffies + p_wait;
3841 do {
3842 c_value_r = qla82xx_md_rw_32(ha, c_addr, 0, 0);
3843 if ((c_value_r & p_mask) == 0)
3844 break;
3845 else if (time_after_eq(jiffies, w_time)) {
3846 /* capturing dump failed */
3847 ql_dbg(ql_dbg_p3p, vha, 0xb032,
3848 "c_value_r: 0x%x, poll_mask: 0x%lx, "
3849 "w_time: 0x%lx\n",
3850 c_value_r, p_mask, w_time);
3851 return rval;
3852 }
3853 } while (1);
3854 }
3855
3856 addr = r_addr;
3857 for (k = 0; k < r_cnt; k++) {
3858 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3859 *data_ptr++ = cpu_to_le32(r_value);
3860 addr += cache_hdr->read_ctrl.read_addr_stride;
3861 }
3862 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3863 }
3864 *d_ptr = data_ptr;
3865 return QLA_SUCCESS;
3866 }
3867
3868 static void
qla82xx_minidump_process_l1cache(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,__le32 ** d_ptr)3869 qla82xx_minidump_process_l1cache(scsi_qla_host_t *vha,
3870 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3871 {
3872 struct qla_hw_data *ha = vha->hw;
3873 uint32_t addr, r_addr, c_addr, t_r_addr;
3874 uint32_t i, k, loop_count, t_value, r_cnt, r_value;
3875 uint32_t c_value_w;
3876 struct qla82xx_md_entry_cache *cache_hdr;
3877 __le32 *data_ptr = *d_ptr;
3878
3879 cache_hdr = (struct qla82xx_md_entry_cache *)entry_hdr;
3880 loop_count = cache_hdr->op_count;
3881 r_addr = cache_hdr->read_addr;
3882 c_addr = cache_hdr->control_addr;
3883 c_value_w = cache_hdr->cache_ctrl.write_value;
3884
3885 t_r_addr = cache_hdr->tag_reg_addr;
3886 t_value = cache_hdr->addr_ctrl.init_tag_value;
3887 r_cnt = cache_hdr->read_ctrl.read_addr_cnt;
3888
3889 for (i = 0; i < loop_count; i++) {
3890 qla82xx_md_rw_32(ha, t_r_addr, t_value, 1);
3891 qla82xx_md_rw_32(ha, c_addr, c_value_w, 1);
3892 addr = r_addr;
3893 for (k = 0; k < r_cnt; k++) {
3894 r_value = qla82xx_md_rw_32(ha, addr, 0, 0);
3895 *data_ptr++ = cpu_to_le32(r_value);
3896 addr += cache_hdr->read_ctrl.read_addr_stride;
3897 }
3898 t_value += cache_hdr->addr_ctrl.tag_value_stride;
3899 }
3900 *d_ptr = data_ptr;
3901 }
3902
3903 static void
qla82xx_minidump_process_queue(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,__le32 ** d_ptr)3904 qla82xx_minidump_process_queue(scsi_qla_host_t *vha,
3905 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3906 {
3907 struct qla_hw_data *ha = vha->hw;
3908 uint32_t s_addr, r_addr;
3909 uint32_t r_stride, r_value, r_cnt, qid = 0;
3910 uint32_t i, k, loop_cnt;
3911 struct qla82xx_md_entry_queue *q_hdr;
3912 __le32 *data_ptr = *d_ptr;
3913
3914 q_hdr = (struct qla82xx_md_entry_queue *)entry_hdr;
3915 s_addr = q_hdr->select_addr;
3916 r_cnt = q_hdr->rd_strd.read_addr_cnt;
3917 r_stride = q_hdr->rd_strd.read_addr_stride;
3918 loop_cnt = q_hdr->op_count;
3919
3920 for (i = 0; i < loop_cnt; i++) {
3921 qla82xx_md_rw_32(ha, s_addr, qid, 1);
3922 r_addr = q_hdr->read_addr;
3923 for (k = 0; k < r_cnt; k++) {
3924 r_value = qla82xx_md_rw_32(ha, r_addr, 0, 0);
3925 *data_ptr++ = cpu_to_le32(r_value);
3926 r_addr += r_stride;
3927 }
3928 qid += q_hdr->q_strd.queue_id_stride;
3929 }
3930 *d_ptr = data_ptr;
3931 }
3932
3933 static void
qla82xx_minidump_process_rdrom(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,__le32 ** d_ptr)3934 qla82xx_minidump_process_rdrom(scsi_qla_host_t *vha,
3935 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3936 {
3937 struct qla_hw_data *ha = vha->hw;
3938 uint32_t r_addr, r_value;
3939 uint32_t i, loop_cnt;
3940 struct qla82xx_md_entry_rdrom *rom_hdr;
3941 __le32 *data_ptr = *d_ptr;
3942
3943 rom_hdr = (struct qla82xx_md_entry_rdrom *)entry_hdr;
3944 r_addr = rom_hdr->read_addr;
3945 loop_cnt = rom_hdr->read_data_size/sizeof(uint32_t);
3946
3947 for (i = 0; i < loop_cnt; i++) {
3948 qla82xx_md_rw_32(ha, MD_DIRECT_ROM_WINDOW,
3949 (r_addr & 0xFFFF0000), 1);
3950 r_value = qla82xx_md_rw_32(ha,
3951 MD_DIRECT_ROM_READ_BASE +
3952 (r_addr & 0x0000FFFF), 0, 0);
3953 *data_ptr++ = cpu_to_le32(r_value);
3954 r_addr += sizeof(uint32_t);
3955 }
3956 *d_ptr = data_ptr;
3957 }
3958
3959 static int
qla82xx_minidump_process_rdmem(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,__le32 ** d_ptr)3960 qla82xx_minidump_process_rdmem(scsi_qla_host_t *vha,
3961 qla82xx_md_entry_hdr_t *entry_hdr, __le32 **d_ptr)
3962 {
3963 struct qla_hw_data *ha = vha->hw;
3964 uint32_t r_addr, r_value, r_data;
3965 uint32_t i, j, loop_cnt;
3966 struct qla82xx_md_entry_rdmem *m_hdr;
3967 unsigned long flags;
3968 int rval = QLA_FUNCTION_FAILED;
3969 __le32 *data_ptr = *d_ptr;
3970
3971 m_hdr = (struct qla82xx_md_entry_rdmem *)entry_hdr;
3972 r_addr = m_hdr->read_addr;
3973 loop_cnt = m_hdr->read_data_size/16;
3974
3975 if (r_addr & 0xf) {
3976 ql_log(ql_log_warn, vha, 0xb033,
3977 "Read addr 0x%x not 16 bytes aligned\n", r_addr);
3978 return rval;
3979 }
3980
3981 if (m_hdr->read_data_size % 16) {
3982 ql_log(ql_log_warn, vha, 0xb034,
3983 "Read data[0x%x] not multiple of 16 bytes\n",
3984 m_hdr->read_data_size);
3985 return rval;
3986 }
3987
3988 ql_dbg(ql_dbg_p3p, vha, 0xb035,
3989 "[%s]: rdmem_addr: 0x%x, read_data_size: 0x%x, loop_cnt: 0x%x\n",
3990 __func__, r_addr, m_hdr->read_data_size, loop_cnt);
3991
3992 write_lock_irqsave(&ha->hw_lock, flags);
3993 for (i = 0; i < loop_cnt; i++) {
3994 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_LO, r_addr, 1);
3995 r_value = 0;
3996 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_ADDR_HI, r_value, 1);
3997 r_value = MIU_TA_CTL_ENABLE;
3998 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
3999 r_value = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
4000 qla82xx_md_rw_32(ha, MD_MIU_TEST_AGT_CTRL, r_value, 1);
4001
4002 for (j = 0; j < MAX_CTL_CHECK; j++) {
4003 r_value = qla82xx_md_rw_32(ha,
4004 MD_MIU_TEST_AGT_CTRL, 0, 0);
4005 if ((r_value & MIU_TA_CTL_BUSY) == 0)
4006 break;
4007 }
4008
4009 if (j >= MAX_CTL_CHECK) {
4010 printk_ratelimited(KERN_ERR
4011 "failed to read through agent\n");
4012 write_unlock_irqrestore(&ha->hw_lock, flags);
4013 return rval;
4014 }
4015
4016 for (j = 0; j < 4; j++) {
4017 r_data = qla82xx_md_rw_32(ha,
4018 MD_MIU_TEST_AGT_RDDATA[j], 0, 0);
4019 *data_ptr++ = cpu_to_le32(r_data);
4020 }
4021 r_addr += 16;
4022 }
4023 write_unlock_irqrestore(&ha->hw_lock, flags);
4024 *d_ptr = data_ptr;
4025 return QLA_SUCCESS;
4026 }
4027
4028 int
qla82xx_validate_template_chksum(scsi_qla_host_t * vha)4029 qla82xx_validate_template_chksum(scsi_qla_host_t *vha)
4030 {
4031 struct qla_hw_data *ha = vha->hw;
4032 uint64_t chksum = 0;
4033 uint32_t *d_ptr = (uint32_t *)ha->md_tmplt_hdr;
4034 int count = ha->md_template_size/sizeof(uint32_t);
4035
4036 while (count-- > 0)
4037 chksum += *d_ptr++;
4038 while (chksum >> 32)
4039 chksum = (chksum & 0xFFFFFFFF) + (chksum >> 32);
4040 return ~chksum;
4041 }
4042
4043 static void
qla82xx_mark_entry_skipped(scsi_qla_host_t * vha,qla82xx_md_entry_hdr_t * entry_hdr,int index)4044 qla82xx_mark_entry_skipped(scsi_qla_host_t *vha,
4045 qla82xx_md_entry_hdr_t *entry_hdr, int index)
4046 {
4047 entry_hdr->d_ctrl.driver_flags |= QLA82XX_DBG_SKIPPED_FLAG;
4048 ql_dbg(ql_dbg_p3p, vha, 0xb036,
4049 "Skipping entry[%d]: "
4050 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4051 index, entry_hdr->entry_type,
4052 entry_hdr->d_ctrl.entry_capture_mask);
4053 }
4054
4055 int
qla82xx_md_collect(scsi_qla_host_t * vha)4056 qla82xx_md_collect(scsi_qla_host_t *vha)
4057 {
4058 struct qla_hw_data *ha = vha->hw;
4059 int no_entry_hdr = 0;
4060 qla82xx_md_entry_hdr_t *entry_hdr;
4061 struct qla82xx_md_template_hdr *tmplt_hdr;
4062 __le32 *data_ptr;
4063 uint32_t total_data_size = 0, f_capture_mask, data_collected = 0;
4064 int i = 0, rval = QLA_FUNCTION_FAILED;
4065
4066 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4067 data_ptr = ha->md_dump;
4068
4069 if (ha->fw_dumped) {
4070 ql_log(ql_log_warn, vha, 0xb037,
4071 "Firmware has been previously dumped (%p) "
4072 "-- ignoring request.\n", ha->fw_dump);
4073 goto md_failed;
4074 }
4075
4076 ha->fw_dumped = false;
4077
4078 if (!ha->md_tmplt_hdr || !ha->md_dump) {
4079 ql_log(ql_log_warn, vha, 0xb038,
4080 "Memory not allocated for minidump capture\n");
4081 goto md_failed;
4082 }
4083
4084 if (ha->flags.isp82xx_no_md_cap) {
4085 ql_log(ql_log_warn, vha, 0xb054,
4086 "Forced reset from application, "
4087 "ignore minidump capture\n");
4088 ha->flags.isp82xx_no_md_cap = 0;
4089 goto md_failed;
4090 }
4091
4092 if (qla82xx_validate_template_chksum(vha)) {
4093 ql_log(ql_log_info, vha, 0xb039,
4094 "Template checksum validation error\n");
4095 goto md_failed;
4096 }
4097
4098 no_entry_hdr = tmplt_hdr->num_of_entries;
4099 ql_dbg(ql_dbg_p3p, vha, 0xb03a,
4100 "No of entry headers in Template: 0x%x\n", no_entry_hdr);
4101
4102 ql_dbg(ql_dbg_p3p, vha, 0xb03b,
4103 "Capture Mask obtained: 0x%x\n", tmplt_hdr->capture_debug_level);
4104
4105 f_capture_mask = tmplt_hdr->capture_debug_level & 0xFF;
4106
4107 /* Validate whether required debug level is set */
4108 if ((f_capture_mask & 0x3) != 0x3) {
4109 ql_log(ql_log_warn, vha, 0xb03c,
4110 "Minimum required capture mask[0x%x] level not set\n",
4111 f_capture_mask);
4112 goto md_failed;
4113 }
4114 tmplt_hdr->driver_capture_mask = ql2xmdcapmask;
4115
4116 tmplt_hdr->driver_info[0] = vha->host_no;
4117 tmplt_hdr->driver_info[1] = (QLA_DRIVER_MAJOR_VER << 24) |
4118 (QLA_DRIVER_MINOR_VER << 16) | (QLA_DRIVER_PATCH_VER << 8) |
4119 QLA_DRIVER_BETA_VER;
4120
4121 total_data_size = ha->md_dump_size;
4122
4123 ql_dbg(ql_dbg_p3p, vha, 0xb03d,
4124 "Total minidump data_size 0x%x to be captured\n", total_data_size);
4125
4126 /* Check whether template obtained is valid */
4127 if (tmplt_hdr->entry_type != QLA82XX_TLHDR) {
4128 ql_log(ql_log_warn, vha, 0xb04e,
4129 "Bad template header entry type: 0x%x obtained\n",
4130 tmplt_hdr->entry_type);
4131 goto md_failed;
4132 }
4133
4134 entry_hdr = (qla82xx_md_entry_hdr_t *)
4135 (((uint8_t *)ha->md_tmplt_hdr) + tmplt_hdr->first_entry_offset);
4136
4137 /* Walk through the entry headers */
4138 for (i = 0; i < no_entry_hdr; i++) {
4139
4140 if (data_collected > total_data_size) {
4141 ql_log(ql_log_warn, vha, 0xb03e,
4142 "More MiniDump data collected: [0x%x]\n",
4143 data_collected);
4144 goto md_failed;
4145 }
4146
4147 if (!(entry_hdr->d_ctrl.entry_capture_mask &
4148 ql2xmdcapmask)) {
4149 entry_hdr->d_ctrl.driver_flags |=
4150 QLA82XX_DBG_SKIPPED_FLAG;
4151 ql_dbg(ql_dbg_p3p, vha, 0xb03f,
4152 "Skipping entry[%d]: "
4153 "ETYPE[0x%x]-ELEVEL[0x%x]\n",
4154 i, entry_hdr->entry_type,
4155 entry_hdr->d_ctrl.entry_capture_mask);
4156 goto skip_nxt_entry;
4157 }
4158
4159 ql_dbg(ql_dbg_p3p, vha, 0xb040,
4160 "[%s]: data ptr[%d]: %p, entry_hdr: %p\n"
4161 "entry_type: 0x%x, capture_mask: 0x%x\n",
4162 __func__, i, data_ptr, entry_hdr,
4163 entry_hdr->entry_type,
4164 entry_hdr->d_ctrl.entry_capture_mask);
4165
4166 ql_dbg(ql_dbg_p3p, vha, 0xb041,
4167 "Data collected: [0x%x], Dump size left:[0x%x]\n",
4168 data_collected, (ha->md_dump_size - data_collected));
4169
4170 /* Decode the entry type and take
4171 * required action to capture debug data */
4172 switch (entry_hdr->entry_type) {
4173 case QLA82XX_RDEND:
4174 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4175 break;
4176 case QLA82XX_CNTRL:
4177 rval = qla82xx_minidump_process_control(vha,
4178 entry_hdr, &data_ptr);
4179 if (rval != QLA_SUCCESS) {
4180 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4181 goto md_failed;
4182 }
4183 break;
4184 case QLA82XX_RDCRB:
4185 qla82xx_minidump_process_rdcrb(vha,
4186 entry_hdr, &data_ptr);
4187 break;
4188 case QLA82XX_RDMEM:
4189 rval = qla82xx_minidump_process_rdmem(vha,
4190 entry_hdr, &data_ptr);
4191 if (rval != QLA_SUCCESS) {
4192 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4193 goto md_failed;
4194 }
4195 break;
4196 case QLA82XX_BOARD:
4197 case QLA82XX_RDROM:
4198 qla82xx_minidump_process_rdrom(vha,
4199 entry_hdr, &data_ptr);
4200 break;
4201 case QLA82XX_L2DTG:
4202 case QLA82XX_L2ITG:
4203 case QLA82XX_L2DAT:
4204 case QLA82XX_L2INS:
4205 rval = qla82xx_minidump_process_l2tag(vha,
4206 entry_hdr, &data_ptr);
4207 if (rval != QLA_SUCCESS) {
4208 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4209 goto md_failed;
4210 }
4211 break;
4212 case QLA82XX_L1DAT:
4213 case QLA82XX_L1INS:
4214 qla82xx_minidump_process_l1cache(vha,
4215 entry_hdr, &data_ptr);
4216 break;
4217 case QLA82XX_RDOCM:
4218 qla82xx_minidump_process_rdocm(vha,
4219 entry_hdr, &data_ptr);
4220 break;
4221 case QLA82XX_RDMUX:
4222 qla82xx_minidump_process_rdmux(vha,
4223 entry_hdr, &data_ptr);
4224 break;
4225 case QLA82XX_QUEUE:
4226 qla82xx_minidump_process_queue(vha,
4227 entry_hdr, &data_ptr);
4228 break;
4229 case QLA82XX_RDNOP:
4230 default:
4231 qla82xx_mark_entry_skipped(vha, entry_hdr, i);
4232 break;
4233 }
4234
4235 ql_dbg(ql_dbg_p3p, vha, 0xb042,
4236 "[%s]: data ptr[%d]: %p\n", __func__, i, data_ptr);
4237
4238 data_collected = (uint8_t *)data_ptr -
4239 (uint8_t *)ha->md_dump;
4240 skip_nxt_entry:
4241 entry_hdr = (qla82xx_md_entry_hdr_t *)
4242 (((uint8_t *)entry_hdr) + entry_hdr->entry_size);
4243 }
4244
4245 if (data_collected != total_data_size) {
4246 ql_dbg(ql_dbg_p3p, vha, 0xb043,
4247 "MiniDump data mismatch: Data collected: [0x%x],"
4248 "total_data_size:[0x%x]\n",
4249 data_collected, total_data_size);
4250 goto md_failed;
4251 }
4252
4253 ql_log(ql_log_info, vha, 0xb044,
4254 "Firmware dump saved to temp buffer (%ld/%p %ld/%p).\n",
4255 vha->host_no, ha->md_tmplt_hdr, vha->host_no, ha->md_dump);
4256 ha->fw_dumped = true;
4257 qla2x00_post_uevent_work(vha, QLA_UEVENT_CODE_FW_DUMP);
4258
4259 md_failed:
4260 return rval;
4261 }
4262
4263 int
qla82xx_md_alloc(scsi_qla_host_t * vha)4264 qla82xx_md_alloc(scsi_qla_host_t *vha)
4265 {
4266 struct qla_hw_data *ha = vha->hw;
4267 int i, k;
4268 struct qla82xx_md_template_hdr *tmplt_hdr;
4269
4270 tmplt_hdr = (struct qla82xx_md_template_hdr *)ha->md_tmplt_hdr;
4271
4272 if (ql2xmdcapmask < 0x3 || ql2xmdcapmask > 0x7F) {
4273 ql2xmdcapmask = tmplt_hdr->capture_debug_level & 0xFF;
4274 ql_log(ql_log_info, vha, 0xb045,
4275 "Forcing driver capture mask to firmware default capture mask: 0x%x.\n",
4276 ql2xmdcapmask);
4277 }
4278
4279 for (i = 0x2, k = 1; (i & QLA82XX_DEFAULT_CAP_MASK); i <<= 1, k++) {
4280 if (i & ql2xmdcapmask)
4281 ha->md_dump_size += tmplt_hdr->capture_size_array[k];
4282 }
4283
4284 if (ha->md_dump) {
4285 ql_log(ql_log_warn, vha, 0xb046,
4286 "Firmware dump previously allocated.\n");
4287 return 1;
4288 }
4289
4290 ha->md_dump = vmalloc(ha->md_dump_size);
4291 if (ha->md_dump == NULL) {
4292 ql_log(ql_log_warn, vha, 0xb047,
4293 "Unable to allocate memory for Minidump size "
4294 "(0x%x).\n", ha->md_dump_size);
4295 return 1;
4296 }
4297 return 0;
4298 }
4299
4300 void
qla82xx_md_free(scsi_qla_host_t * vha)4301 qla82xx_md_free(scsi_qla_host_t *vha)
4302 {
4303 struct qla_hw_data *ha = vha->hw;
4304
4305 /* Release the template header allocated */
4306 if (ha->md_tmplt_hdr) {
4307 ql_log(ql_log_info, vha, 0xb048,
4308 "Free MiniDump template: %p, size (%d KB)\n",
4309 ha->md_tmplt_hdr, ha->md_template_size / 1024);
4310 dma_free_coherent(&ha->pdev->dev, ha->md_template_size,
4311 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4312 ha->md_tmplt_hdr = NULL;
4313 }
4314
4315 /* Release the template data buffer allocated */
4316 if (ha->md_dump) {
4317 ql_log(ql_log_info, vha, 0xb049,
4318 "Free MiniDump memory: %p, size (%d KB)\n",
4319 ha->md_dump, ha->md_dump_size / 1024);
4320 vfree(ha->md_dump);
4321 ha->md_dump_size = 0;
4322 ha->md_dump = NULL;
4323 }
4324 }
4325
4326 void
qla82xx_md_prep(scsi_qla_host_t * vha)4327 qla82xx_md_prep(scsi_qla_host_t *vha)
4328 {
4329 struct qla_hw_data *ha = vha->hw;
4330 int rval;
4331
4332 /* Get Minidump template size */
4333 rval = qla82xx_md_get_template_size(vha);
4334 if (rval == QLA_SUCCESS) {
4335 ql_log(ql_log_info, vha, 0xb04a,
4336 "MiniDump Template size obtained (%d KB)\n",
4337 ha->md_template_size / 1024);
4338
4339 /* Get Minidump template */
4340 if (IS_QLA8044(ha))
4341 rval = qla8044_md_get_template(vha);
4342 else
4343 rval = qla82xx_md_get_template(vha);
4344
4345 if (rval == QLA_SUCCESS) {
4346 ql_dbg(ql_dbg_p3p, vha, 0xb04b,
4347 "MiniDump Template obtained\n");
4348
4349 /* Allocate memory for minidump */
4350 rval = qla82xx_md_alloc(vha);
4351 if (rval == QLA_SUCCESS)
4352 ql_log(ql_log_info, vha, 0xb04c,
4353 "MiniDump memory allocated (%d KB)\n",
4354 ha->md_dump_size / 1024);
4355 else {
4356 ql_log(ql_log_info, vha, 0xb04d,
4357 "Free MiniDump template: %p, size: (%d KB)\n",
4358 ha->md_tmplt_hdr,
4359 ha->md_template_size / 1024);
4360 dma_free_coherent(&ha->pdev->dev,
4361 ha->md_template_size,
4362 ha->md_tmplt_hdr, ha->md_tmplt_hdr_dma);
4363 ha->md_tmplt_hdr = NULL;
4364 }
4365
4366 }
4367 }
4368 }
4369
4370 int
qla82xx_beacon_on(struct scsi_qla_host * vha)4371 qla82xx_beacon_on(struct scsi_qla_host *vha)
4372 {
4373
4374 int rval;
4375 struct qla_hw_data *ha = vha->hw;
4376
4377 qla82xx_idc_lock(ha);
4378 rval = qla82xx_mbx_beacon_ctl(vha, 1);
4379
4380 if (rval) {
4381 ql_log(ql_log_warn, vha, 0xb050,
4382 "mbx set led config failed in %s\n", __func__);
4383 goto exit;
4384 }
4385 ha->beacon_blink_led = 1;
4386 exit:
4387 qla82xx_idc_unlock(ha);
4388 return rval;
4389 }
4390
4391 int
qla82xx_beacon_off(struct scsi_qla_host * vha)4392 qla82xx_beacon_off(struct scsi_qla_host *vha)
4393 {
4394
4395 int rval;
4396 struct qla_hw_data *ha = vha->hw;
4397
4398 qla82xx_idc_lock(ha);
4399 rval = qla82xx_mbx_beacon_ctl(vha, 0);
4400
4401 if (rval) {
4402 ql_log(ql_log_warn, vha, 0xb051,
4403 "mbx set led config failed in %s\n", __func__);
4404 goto exit;
4405 }
4406 ha->beacon_blink_led = 0;
4407 exit:
4408 qla82xx_idc_unlock(ha);
4409 return rval;
4410 }
4411
4412 void
qla82xx_fw_dump(scsi_qla_host_t * vha)4413 qla82xx_fw_dump(scsi_qla_host_t *vha)
4414 {
4415 struct qla_hw_data *ha = vha->hw;
4416
4417 if (!ha->allow_cna_fw_dump)
4418 return;
4419
4420 scsi_block_requests(vha->host);
4421 ha->flags.isp82xx_no_md_cap = 1;
4422 qla82xx_idc_lock(ha);
4423 qla82xx_set_reset_owner(vha);
4424 qla82xx_idc_unlock(ha);
4425 qla2x00_wait_for_chip_reset(vha);
4426 scsi_unblock_requests(vha->host);
4427 }
4428