1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/bitfield.h> 9 #include <linux/moduleparam.h> 10 #include <linux/vmalloc.h> 11 #include <linux/delay.h> 12 #include <linux/kthread.h> 13 #include <linux/mutex.h> 14 #include <linux/kobject.h> 15 #include <linux/slab.h> 16 #include <linux/refcount.h> 17 #include <linux/crash_dump.h> 18 #include <linux/trace_events.h> 19 #include <linux/trace.h> 20 #include <linux/irq.h> 21 22 #include <scsi/scsi_tcq.h> 23 #include <scsi/scsicam.h> 24 #include <scsi/scsi_transport.h> 25 #include <scsi/scsi_transport_fc.h> 26 27 #include "qla_target.h" 28 29 /* 30 * Driver version 31 */ 32 char qla2x00_version_str[40]; 33 34 static int apidev_major; 35 36 /* 37 * SRB allocation cache 38 */ 39 struct kmem_cache *srb_cachep; 40 41 static struct trace_array *qla_trc_array; 42 43 int ql2xfulldump_on_mpifail; 44 module_param(ql2xfulldump_on_mpifail, int, S_IRUGO | S_IWUSR); 45 MODULE_PARM_DESC(ql2xfulldump_on_mpifail, 46 "Set this to take full dump on MPI hang."); 47 48 int ql2xenforce_iocb_limit = 2; 49 module_param(ql2xenforce_iocb_limit, int, S_IRUGO | S_IWUSR); 50 MODULE_PARM_DESC(ql2xenforce_iocb_limit, 51 "Enforce IOCB throttling, to avoid FW congestion. (default: 2) " 52 "1: track usage per queue, 2: track usage per adapter"); 53 54 /* 55 * CT6 CTX allocation cache 56 */ 57 static struct kmem_cache *ctx_cachep; 58 /* 59 * error level for logging 60 */ 61 uint ql_errlev = 0x8001; 62 63 int ql2xsecenable; 64 module_param(ql2xsecenable, int, S_IRUGO); 65 MODULE_PARM_DESC(ql2xsecenable, 66 "Enable/disable security. 0(Default) - Security disabled. 1 - Security enabled."); 67 68 static int ql2xenableclass2; 69 module_param(ql2xenableclass2, int, S_IRUGO|S_IRUSR); 70 MODULE_PARM_DESC(ql2xenableclass2, 71 "Specify if Class 2 operations are supported from the very " 72 "beginning. Default is 0 - class 2 not supported."); 73 74 75 int ql2xlogintimeout = 20; 76 module_param(ql2xlogintimeout, int, S_IRUGO); 77 MODULE_PARM_DESC(ql2xlogintimeout, 78 "Login timeout value in seconds."); 79 80 int qlport_down_retry; 81 module_param(qlport_down_retry, int, S_IRUGO); 82 MODULE_PARM_DESC(qlport_down_retry, 83 "Maximum number of command retries to a port that returns " 84 "a PORT-DOWN status."); 85 86 int ql2xplogiabsentdevice; 87 module_param(ql2xplogiabsentdevice, int, S_IRUGO|S_IWUSR); 88 MODULE_PARM_DESC(ql2xplogiabsentdevice, 89 "Option to enable PLOGI to devices that are not present after " 90 "a Fabric scan. This is needed for several broken switches. " 91 "Default is 0 - no PLOGI. 1 - perform PLOGI."); 92 93 int ql2xloginretrycount; 94 module_param(ql2xloginretrycount, int, S_IRUGO); 95 MODULE_PARM_DESC(ql2xloginretrycount, 96 "Specify an alternate value for the NVRAM login retry count."); 97 98 int ql2xallocfwdump = 1; 99 module_param(ql2xallocfwdump, int, S_IRUGO); 100 MODULE_PARM_DESC(ql2xallocfwdump, 101 "Option to enable allocation of memory for a firmware dump " 102 "during HBA initialization. Memory allocation requirements " 103 "vary by ISP type. Default is 1 - allocate memory."); 104 105 int ql2xextended_error_logging; 106 module_param(ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 107 module_param_named(logging, ql2xextended_error_logging, int, S_IRUGO|S_IWUSR); 108 MODULE_PARM_DESC(ql2xextended_error_logging, 109 "Option to enable extended error logging,\n" 110 "\t\tDefault is 0 - no logging. 0x40000000 - Module Init & Probe.\n" 111 "\t\t0x20000000 - Mailbox Cmnds. 0x10000000 - Device Discovery.\n" 112 "\t\t0x08000000 - IO tracing. 0x04000000 - DPC Thread.\n" 113 "\t\t0x02000000 - Async events. 0x01000000 - Timer routines.\n" 114 "\t\t0x00800000 - User space. 0x00400000 - Task Management.\n" 115 "\t\t0x00200000 - AER/EEH. 0x00100000 - Multi Q.\n" 116 "\t\t0x00080000 - P3P Specific. 0x00040000 - Virtual Port.\n" 117 "\t\t0x00020000 - Buffer Dump. 0x00010000 - Misc.\n" 118 "\t\t0x00008000 - Verbose. 0x00004000 - Target.\n" 119 "\t\t0x00002000 - Target Mgmt. 0x00001000 - Target TMF.\n" 120 "\t\t0x7fffffff - For enabling all logs, can be too many logs.\n" 121 "\t\t0x1e400000 - Preferred value for capturing essential " 122 "debug information (equivalent to old " 123 "ql2xextended_error_logging=1).\n" 124 "\t\tDo LOGICAL OR of the value to enable more than one level"); 125 126 int ql2xextended_error_logging_ktrace = 1; 127 module_param(ql2xextended_error_logging_ktrace, int, S_IRUGO|S_IWUSR); 128 MODULE_PARM_DESC(ql2xextended_error_logging_ktrace, 129 "Same BIT definition as ql2xextended_error_logging, but used to control logging to kernel trace buffer (default=1).\n"); 130 131 int ql2xshiftctondsd = 6; 132 module_param(ql2xshiftctondsd, int, S_IRUGO); 133 MODULE_PARM_DESC(ql2xshiftctondsd, 134 "Set to control shifting of command type processing " 135 "based on total number of SG elements."); 136 137 int ql2xfdmienable = 1; 138 module_param(ql2xfdmienable, int, S_IRUGO|S_IWUSR); 139 module_param_named(fdmi, ql2xfdmienable, int, S_IRUGO|S_IWUSR); 140 MODULE_PARM_DESC(ql2xfdmienable, 141 "Enables FDMI registrations. " 142 "0 - no FDMI registrations. " 143 "1 - provide FDMI registrations (default)."); 144 145 #define MAX_Q_DEPTH 64 146 static int ql2xmaxqdepth = MAX_Q_DEPTH; 147 module_param(ql2xmaxqdepth, int, S_IRUGO|S_IWUSR); 148 MODULE_PARM_DESC(ql2xmaxqdepth, 149 "Maximum queue depth to set for each LUN. " 150 "Default is 64."); 151 152 int ql2xenabledif = 2; 153 module_param(ql2xenabledif, int, S_IRUGO); 154 MODULE_PARM_DESC(ql2xenabledif, 155 " Enable T10-CRC-DIF:\n" 156 " Default is 2.\n" 157 " 0 -- No DIF Support\n" 158 " 1 -- Enable DIF for all types\n" 159 " 2 -- Enable DIF for all types, except Type 0.\n"); 160 161 #if (IS_ENABLED(CONFIG_NVME_FC)) 162 int ql2xnvmeenable = 1; 163 #else 164 int ql2xnvmeenable; 165 #endif 166 module_param(ql2xnvmeenable, int, 0644); 167 MODULE_PARM_DESC(ql2xnvmeenable, 168 "Enables NVME support. " 169 "0 - no NVMe. Default is Y"); 170 171 int ql2xenablehba_err_chk = 2; 172 module_param(ql2xenablehba_err_chk, int, S_IRUGO|S_IWUSR); 173 MODULE_PARM_DESC(ql2xenablehba_err_chk, 174 " Enable T10-CRC-DIF Error isolation by HBA:\n" 175 " Default is 2.\n" 176 " 0 -- Error isolation disabled\n" 177 " 1 -- Error isolation enabled only for DIX Type 0\n" 178 " 2 -- Error isolation enabled for all Types\n"); 179 180 int ql2xmqsupport = 1; 181 module_param(ql2xmqsupport, int, S_IRUGO); 182 MODULE_PARM_DESC(ql2xmqsupport, 183 "Enable on demand multiple queue pairs support " 184 "Default is 1 for supported. " 185 "Set it to 0 to turn off mq qpair support."); 186 187 int ql2xfwloadbin; 188 module_param(ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 189 module_param_named(fwload, ql2xfwloadbin, int, S_IRUGO|S_IWUSR); 190 MODULE_PARM_DESC(ql2xfwloadbin, 191 "Option to specify location from which to load ISP firmware:.\n" 192 " 2 -- load firmware via the request_firmware() (hotplug).\n" 193 " interface.\n" 194 " 1 -- load firmware from flash.\n" 195 " 0 -- use default semantics.\n"); 196 197 int ql2xdbwr = 1; 198 module_param(ql2xdbwr, int, S_IRUGO|S_IWUSR); 199 MODULE_PARM_DESC(ql2xdbwr, 200 "Option to specify scheme for request queue posting.\n" 201 " 0 -- Regular doorbell.\n" 202 " 1 -- CAMRAM doorbell (faster).\n"); 203 204 int ql2xgffidenable; 205 module_param(ql2xgffidenable, int, S_IRUGO); 206 MODULE_PARM_DESC(ql2xgffidenable, 207 "Enables GFF_ID checks of port type. " 208 "Default is 0 - Do not use GFF_ID information."); 209 210 int ql2xasynctmfenable = 1; 211 module_param(ql2xasynctmfenable, int, S_IRUGO); 212 MODULE_PARM_DESC(ql2xasynctmfenable, 213 "Enables issue of TM IOCBs asynchronously via IOCB mechanism" 214 "Default is 1 - Issue TM IOCBs via mailbox mechanism."); 215 216 int ql2xdontresethba; 217 module_param(ql2xdontresethba, int, S_IRUGO|S_IWUSR); 218 MODULE_PARM_DESC(ql2xdontresethba, 219 "Option to specify reset behaviour.\n" 220 " 0 (Default) -- Reset on failure.\n" 221 " 1 -- Do not reset on failure.\n"); 222 223 uint64_t ql2xmaxlun = MAX_LUNS; 224 module_param(ql2xmaxlun, ullong, S_IRUGO); 225 MODULE_PARM_DESC(ql2xmaxlun, 226 "Defines the maximum LU number to register with the SCSI " 227 "midlayer. Default is 65535."); 228 229 int ql2xmdcapmask = 0x1F; 230 module_param(ql2xmdcapmask, int, S_IRUGO); 231 MODULE_PARM_DESC(ql2xmdcapmask, 232 "Set the Minidump driver capture mask level. " 233 "Default is 0x1F - Can be set to 0x3, 0x7, 0xF, 0x1F, 0x7F."); 234 235 int ql2xmdenable = 1; 236 module_param(ql2xmdenable, int, S_IRUGO); 237 MODULE_PARM_DESC(ql2xmdenable, 238 "Enable/disable MiniDump. " 239 "0 - MiniDump disabled. " 240 "1 (Default) - MiniDump enabled."); 241 242 int ql2xexlogins; 243 module_param(ql2xexlogins, uint, S_IRUGO|S_IWUSR); 244 MODULE_PARM_DESC(ql2xexlogins, 245 "Number of extended Logins. " 246 "0 (Default)- Disabled."); 247 248 int ql2xexchoffld = 1024; 249 module_param(ql2xexchoffld, uint, 0644); 250 MODULE_PARM_DESC(ql2xexchoffld, 251 "Number of target exchanges."); 252 253 int ql2xiniexchg = 1024; 254 module_param(ql2xiniexchg, uint, 0644); 255 MODULE_PARM_DESC(ql2xiniexchg, 256 "Number of initiator exchanges."); 257 258 int ql2xfwholdabts; 259 module_param(ql2xfwholdabts, int, S_IRUGO); 260 MODULE_PARM_DESC(ql2xfwholdabts, 261 "Allow FW to hold status IOCB until ABTS rsp received. " 262 "0 (Default) Do not set fw option. " 263 "1 - Set fw option to hold ABTS."); 264 265 int ql2xmvasynctoatio = 1; 266 module_param(ql2xmvasynctoatio, int, S_IRUGO|S_IWUSR); 267 MODULE_PARM_DESC(ql2xmvasynctoatio, 268 "Move PUREX, ABTS RX and RIDA IOCBs to ATIOQ" 269 "0 (Default). Do not move IOCBs" 270 "1 - Move IOCBs."); 271 272 int ql2xautodetectsfp = 1; 273 module_param(ql2xautodetectsfp, int, 0444); 274 MODULE_PARM_DESC(ql2xautodetectsfp, 275 "Detect SFP range and set appropriate distance.\n" 276 "1 (Default): Enable\n"); 277 278 int ql2xenablemsix = 1; 279 module_param(ql2xenablemsix, int, 0444); 280 MODULE_PARM_DESC(ql2xenablemsix, 281 "Set to enable MSI or MSI-X interrupt mechanism.\n" 282 " Default is 1, enable MSI-X interrupt mechanism.\n" 283 " 0 -- enable traditional pin-based mechanism.\n" 284 " 1 -- enable MSI-X interrupt mechanism.\n" 285 " 2 -- enable MSI interrupt mechanism.\n"); 286 287 int qla2xuseresexchforels; 288 module_param(qla2xuseresexchforels, int, 0444); 289 MODULE_PARM_DESC(qla2xuseresexchforels, 290 "Reserve 1/2 of emergency exchanges for ELS.\n" 291 " 0 (default): disabled"); 292 293 static int ql2xprotmask; 294 module_param(ql2xprotmask, int, 0644); 295 MODULE_PARM_DESC(ql2xprotmask, 296 "Override DIF/DIX protection capabilities mask\n" 297 "Default is 0 which sets protection mask based on " 298 "capabilities reported by HBA firmware.\n"); 299 300 static int ql2xprotguard; 301 module_param(ql2xprotguard, int, 0644); 302 MODULE_PARM_DESC(ql2xprotguard, "Override choice of DIX checksum\n" 303 " 0 -- Let HBA firmware decide\n" 304 " 1 -- Force T10 CRC\n" 305 " 2 -- Force IP checksum\n"); 306 307 int ql2xdifbundlinginternalbuffers; 308 module_param(ql2xdifbundlinginternalbuffers, int, 0644); 309 MODULE_PARM_DESC(ql2xdifbundlinginternalbuffers, 310 "Force using internal buffers for DIF information\n" 311 "0 (Default). Based on check.\n" 312 "1 Force using internal buffers\n"); 313 314 int ql2xsmartsan; 315 module_param(ql2xsmartsan, int, 0444); 316 module_param_named(smartsan, ql2xsmartsan, int, 0444); 317 MODULE_PARM_DESC(ql2xsmartsan, 318 "Send SmartSAN Management Attributes for FDMI Registration." 319 " Default is 0 - No SmartSAN registration," 320 " 1 - Register SmartSAN Management Attributes."); 321 322 int ql2xrdpenable; 323 module_param(ql2xrdpenable, int, 0444); 324 module_param_named(rdpenable, ql2xrdpenable, int, 0444); 325 MODULE_PARM_DESC(ql2xrdpenable, 326 "Enables RDP responses. " 327 "0 - no RDP responses (default). " 328 "1 - provide RDP responses."); 329 int ql2xabts_wait_nvme = 1; 330 module_param(ql2xabts_wait_nvme, int, 0444); 331 MODULE_PARM_DESC(ql2xabts_wait_nvme, 332 "To wait for ABTS response on I/O timeouts for NVMe. (default: 1)"); 333 334 335 static u32 ql2xdelay_before_pci_error_handling = 5; 336 module_param(ql2xdelay_before_pci_error_handling, uint, 0644); 337 MODULE_PARM_DESC(ql2xdelay_before_pci_error_handling, 338 "Number of seconds delayed before qla begin PCI error self-handling (default: 5).\n"); 339 340 static void qla2x00_clear_drv_active(struct qla_hw_data *); 341 static void qla2x00_free_device(scsi_qla_host_t *); 342 static void qla2xxx_map_queues(struct Scsi_Host *shost); 343 static void qla2x00_destroy_deferred_work(struct qla_hw_data *); 344 345 u32 ql2xnvme_queues = DEF_NVME_HW_QUEUES; 346 module_param(ql2xnvme_queues, uint, S_IRUGO); 347 MODULE_PARM_DESC(ql2xnvme_queues, 348 "Number of NVMe Queues that can be configured.\n" 349 "Final value will be min(ql2xnvme_queues, num_cpus,num_chip_queues)\n" 350 "1 - Minimum number of queues supported\n" 351 "8 - Default value"); 352 353 int ql2xfc2target = 1; 354 module_param(ql2xfc2target, int, 0444); 355 MODULE_PARM_DESC(qla2xfc2target, 356 "Enables FC2 Target support. " 357 "0 - FC2 Target support is disabled. " 358 "1 - FC2 Target support is enabled (default)."); 359 360 static struct scsi_transport_template *qla2xxx_transport_template = NULL; 361 struct scsi_transport_template *qla2xxx_transport_vport_template = NULL; 362 363 /* TODO Convert to inlines 364 * 365 * Timer routines 366 */ 367 368 __inline__ void 369 qla2x00_start_timer(scsi_qla_host_t *vha, unsigned long interval) 370 { 371 timer_setup(&vha->timer, qla2x00_timer, 0); 372 vha->timer.expires = jiffies + interval * HZ; 373 add_timer(&vha->timer); 374 vha->timer_active = 1; 375 } 376 377 static inline void 378 qla2x00_restart_timer(scsi_qla_host_t *vha, unsigned long interval) 379 { 380 /* Currently used for 82XX only. */ 381 if (vha->device_flags & DFLG_DEV_FAILED) { 382 ql_dbg(ql_dbg_timer, vha, 0x600d, 383 "Device in a failed state, returning.\n"); 384 return; 385 } 386 387 mod_timer(&vha->timer, jiffies + interval * HZ); 388 } 389 390 static __inline__ void 391 qla2x00_stop_timer(scsi_qla_host_t *vha) 392 { 393 timer_delete_sync(&vha->timer); 394 vha->timer_active = 0; 395 } 396 397 static int qla2x00_do_dpc(void *data); 398 399 static void qla2x00_rst_aen(scsi_qla_host_t *); 400 401 static int qla2x00_mem_alloc(struct qla_hw_data *, uint16_t, uint16_t, 402 struct req_que **, struct rsp_que **); 403 static void qla2x00_free_fw_dump(struct qla_hw_data *); 404 static void qla2x00_mem_free(struct qla_hw_data *); 405 static enum scsi_qc_status qla2xxx_mqueuecommand(struct Scsi_Host *host, 406 struct scsi_cmnd *cmd, 407 struct qla_qpair *qpair); 408 409 /* -------------------------------------------------------------------------- */ 410 static void qla_init_base_qpair(struct scsi_qla_host *vha, struct req_que *req, 411 struct rsp_que *rsp) 412 { 413 struct qla_hw_data *ha = vha->hw; 414 415 rsp->qpair = ha->base_qpair; 416 rsp->req = req; 417 ha->base_qpair->hw = ha; 418 ha->base_qpair->req = req; 419 ha->base_qpair->rsp = rsp; 420 ha->base_qpair->vha = vha; 421 ha->base_qpair->qp_lock_ptr = &ha->hardware_lock; 422 ha->base_qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0; 423 ha->base_qpair->msix = &ha->msix_entries[QLA_MSIX_RSP_Q]; 424 ha->base_qpair->srb_mempool = ha->srb_mempool; 425 INIT_LIST_HEAD(&ha->base_qpair->hints_list); 426 INIT_LIST_HEAD(&ha->base_qpair->dsd_list); 427 ha->base_qpair->enable_class_2 = ql2xenableclass2; 428 /* init qpair to this cpu. Will adjust at run time. */ 429 qla_cpu_update(rsp->qpair, raw_smp_processor_id()); 430 ha->base_qpair->pdev = ha->pdev; 431 432 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha)) 433 ha->base_qpair->reqq_start_iocbs = qla_83xx_start_iocbs; 434 } 435 436 static int qla2x00_alloc_queues(struct qla_hw_data *ha, struct req_que *req, 437 struct rsp_que *rsp) 438 { 439 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 440 441 ha->req_q_map = kcalloc(ha->max_req_queues, sizeof(struct req_que *), 442 GFP_KERNEL); 443 if (!ha->req_q_map) { 444 ql_log(ql_log_fatal, vha, 0x003b, 445 "Unable to allocate memory for request queue ptrs.\n"); 446 goto fail_req_map; 447 } 448 449 ha->rsp_q_map = kcalloc(ha->max_rsp_queues, sizeof(struct rsp_que *), 450 GFP_KERNEL); 451 if (!ha->rsp_q_map) { 452 ql_log(ql_log_fatal, vha, 0x003c, 453 "Unable to allocate memory for response queue ptrs.\n"); 454 goto fail_rsp_map; 455 } 456 457 ha->base_qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL); 458 if (ha->base_qpair == NULL) { 459 ql_log(ql_log_warn, vha, 0x00e0, 460 "Failed to allocate base queue pair memory.\n"); 461 goto fail_base_qpair; 462 } 463 464 qla_init_base_qpair(vha, req, rsp); 465 466 if ((ql2xmqsupport || ql2xnvmeenable) && ha->max_qpairs) { 467 ha->queue_pair_map = kcalloc(ha->max_qpairs, sizeof(struct qla_qpair *), 468 GFP_KERNEL); 469 if (!ha->queue_pair_map) { 470 ql_log(ql_log_fatal, vha, 0x0180, 471 "Unable to allocate memory for queue pair ptrs.\n"); 472 goto fail_qpair_map; 473 } 474 if (qla_mapq_alloc_qp_cpu_map(ha) != 0) { 475 kfree(ha->queue_pair_map); 476 ha->queue_pair_map = NULL; 477 goto fail_qpair_map; 478 } 479 } 480 481 /* 482 * Make sure we record at least the request and response queue zero in 483 * case we need to free them if part of the probe fails. 484 */ 485 ha->rsp_q_map[0] = rsp; 486 ha->req_q_map[0] = req; 487 set_bit(0, ha->rsp_qid_map); 488 set_bit(0, ha->req_qid_map); 489 return 0; 490 491 fail_qpair_map: 492 kfree(ha->base_qpair); 493 ha->base_qpair = NULL; 494 fail_base_qpair: 495 kfree(ha->rsp_q_map); 496 ha->rsp_q_map = NULL; 497 fail_rsp_map: 498 kfree(ha->req_q_map); 499 ha->req_q_map = NULL; 500 fail_req_map: 501 return -ENOMEM; 502 } 503 504 static void qla2x00_free_req_que(struct qla_hw_data *ha, struct req_que *req) 505 { 506 if (IS_QLAFX00(ha)) { 507 if (req && req->ring_fx00) 508 dma_free_coherent(&ha->pdev->dev, 509 (req->length_fx00 + 1) * sizeof(request_t), 510 req->ring_fx00, req->dma_fx00); 511 } else if (req && req->ring) 512 dma_free_coherent(&ha->pdev->dev, 513 (req->length + 1) * sizeof(request_t), 514 req->ring, req->dma); 515 516 if (req) 517 kfree(req->outstanding_cmds); 518 519 kfree(req); 520 } 521 522 static void qla2x00_free_rsp_que(struct qla_hw_data *ha, struct rsp_que *rsp) 523 { 524 if (IS_QLAFX00(ha)) { 525 if (rsp && rsp->ring_fx00) 526 dma_free_coherent(&ha->pdev->dev, 527 (rsp->length_fx00 + 1) * sizeof(request_t), 528 rsp->ring_fx00, rsp->dma_fx00); 529 } else if (rsp && rsp->ring) { 530 dma_free_coherent(&ha->pdev->dev, 531 (rsp->length + 1) * sizeof(response_t), 532 rsp->ring, rsp->dma); 533 } 534 kfree(rsp); 535 } 536 537 static void qla2x00_free_queues(struct qla_hw_data *ha) 538 { 539 struct req_que *req; 540 struct rsp_que *rsp; 541 int cnt; 542 unsigned long flags; 543 544 if (ha->queue_pair_map) { 545 kfree(ha->queue_pair_map); 546 ha->queue_pair_map = NULL; 547 } 548 if (ha->base_qpair) { 549 kfree(ha->base_qpair); 550 ha->base_qpair = NULL; 551 } 552 553 qla_mapq_free_qp_cpu_map(ha); 554 spin_lock_irqsave(&ha->hardware_lock, flags); 555 for (cnt = 0; cnt < ha->max_req_queues; cnt++) { 556 if (!test_bit(cnt, ha->req_qid_map)) 557 continue; 558 559 req = ha->req_q_map[cnt]; 560 clear_bit(cnt, ha->req_qid_map); 561 ha->req_q_map[cnt] = NULL; 562 563 spin_unlock_irqrestore(&ha->hardware_lock, flags); 564 qla2x00_free_req_que(ha, req); 565 spin_lock_irqsave(&ha->hardware_lock, flags); 566 } 567 spin_unlock_irqrestore(&ha->hardware_lock, flags); 568 569 kfree(ha->req_q_map); 570 ha->req_q_map = NULL; 571 572 573 spin_lock_irqsave(&ha->hardware_lock, flags); 574 for (cnt = 0; cnt < ha->max_rsp_queues; cnt++) { 575 if (!test_bit(cnt, ha->rsp_qid_map)) 576 continue; 577 578 rsp = ha->rsp_q_map[cnt]; 579 clear_bit(cnt, ha->rsp_qid_map); 580 ha->rsp_q_map[cnt] = NULL; 581 spin_unlock_irqrestore(&ha->hardware_lock, flags); 582 qla2x00_free_rsp_que(ha, rsp); 583 spin_lock_irqsave(&ha->hardware_lock, flags); 584 } 585 spin_unlock_irqrestore(&ha->hardware_lock, flags); 586 587 kfree(ha->rsp_q_map); 588 ha->rsp_q_map = NULL; 589 } 590 591 static char * 592 qla2x00_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 593 { 594 struct qla_hw_data *ha = vha->hw; 595 static const char *const pci_bus_modes[] = { 596 "33", "66", "100", "133", 597 }; 598 uint16_t pci_bus; 599 600 pci_bus = (ha->pci_attr & (BIT_9 | BIT_10)) >> 9; 601 if (pci_bus) { 602 snprintf(str, str_len, "PCI-X (%s MHz)", 603 pci_bus_modes[pci_bus]); 604 } else { 605 pci_bus = (ha->pci_attr & BIT_8) >> 8; 606 snprintf(str, str_len, "PCI (%s MHz)", pci_bus_modes[pci_bus]); 607 } 608 609 return str; 610 } 611 612 static char * 613 qla24xx_pci_info_str(struct scsi_qla_host *vha, char *str, size_t str_len) 614 { 615 static const char *const pci_bus_modes[] = { 616 "33", "66", "100", "133", 617 }; 618 struct qla_hw_data *ha = vha->hw; 619 uint32_t pci_bus; 620 621 if (pci_is_pcie(ha->pdev)) { 622 uint32_t lstat, lspeed, lwidth; 623 const char *speed_str; 624 625 pcie_capability_read_dword(ha->pdev, PCI_EXP_LNKCAP, &lstat); 626 lspeed = FIELD_GET(PCI_EXP_LNKCAP_SLS, lstat); 627 lwidth = FIELD_GET(PCI_EXP_LNKCAP_MLW, lstat); 628 629 switch (lspeed) { 630 case 1: 631 speed_str = "2.5GT/s"; 632 break; 633 case 2: 634 speed_str = "5.0GT/s"; 635 break; 636 case 3: 637 speed_str = "8.0GT/s"; 638 break; 639 case 4: 640 speed_str = "16.0GT/s"; 641 break; 642 default: 643 speed_str = "<unknown>"; 644 break; 645 } 646 snprintf(str, str_len, "PCIe (%s x%d)", speed_str, lwidth); 647 648 return str; 649 } 650 651 pci_bus = (ha->pci_attr & CSRX_PCIX_BUS_MODE_MASK) >> 8; 652 if (pci_bus == 0 || pci_bus == 8) 653 snprintf(str, str_len, "PCI (%s MHz)", 654 pci_bus_modes[pci_bus >> 3]); 655 else 656 snprintf(str, str_len, "PCI-X Mode %d (%s MHz)", 657 pci_bus & 4 ? 2 : 1, 658 pci_bus_modes[pci_bus & 3]); 659 660 return str; 661 } 662 663 static char * 664 qla2x00_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 665 { 666 char un_str[10]; 667 struct qla_hw_data *ha = vha->hw; 668 669 snprintf(str, size, "%d.%02d.%02d ", ha->fw_major_version, 670 ha->fw_minor_version, ha->fw_subminor_version); 671 672 if (ha->fw_attributes & BIT_9) { 673 strcat(str, "FLX"); 674 return (str); 675 } 676 677 switch (ha->fw_attributes & 0xFF) { 678 case 0x7: 679 strcat(str, "EF"); 680 break; 681 case 0x17: 682 strcat(str, "TP"); 683 break; 684 case 0x37: 685 strcat(str, "IP"); 686 break; 687 case 0x77: 688 strcat(str, "VI"); 689 break; 690 default: 691 sprintf(un_str, "(%x)", ha->fw_attributes); 692 strcat(str, un_str); 693 break; 694 } 695 if (ha->fw_attributes & 0x100) 696 strcat(str, "X"); 697 698 return (str); 699 } 700 701 static char * 702 qla24xx_fw_version_str(struct scsi_qla_host *vha, char *str, size_t size) 703 { 704 struct qla_hw_data *ha = vha->hw; 705 706 snprintf(str, size, "%d.%02d.%02d (%x)", ha->fw_major_version, 707 ha->fw_minor_version, ha->fw_subminor_version, ha->fw_attributes); 708 return str; 709 } 710 711 void qla2x00_sp_free_dma(srb_t *sp) 712 { 713 struct qla_hw_data *ha = sp->vha->hw; 714 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 715 716 if (sp->flags & SRB_DMA_VALID) { 717 scsi_dma_unmap(cmd); 718 sp->flags &= ~SRB_DMA_VALID; 719 } 720 721 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 722 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 723 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 724 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 725 } 726 727 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 728 /* List assured to be having elements */ 729 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 730 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 731 } 732 733 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 734 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 735 736 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 737 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 738 } 739 740 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 741 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 742 743 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 744 ctx1->fcp_cmnd_dma); 745 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list); 746 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt; 747 sp->qpair->dsd_avail += ctx1->dsd_use_cnt; 748 } 749 750 if (sp->flags & SRB_GOT_BUF) 751 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 752 } 753 754 void qla2x00_sp_compl(srb_t *sp, int res) 755 { 756 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 757 struct completion *comp = sp->comp; 758 759 /* kref: INIT */ 760 kref_put(&sp->cmd_kref, qla2x00_sp_release); 761 cmd->result = res; 762 sp->type = 0; 763 scsi_done(cmd); 764 if (comp) 765 complete(comp); 766 } 767 768 void qla2xxx_qpair_sp_free_dma(srb_t *sp) 769 { 770 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 771 struct qla_hw_data *ha = sp->fcport->vha->hw; 772 773 if (sp->flags & SRB_DMA_VALID) { 774 scsi_dma_unmap(cmd); 775 sp->flags &= ~SRB_DMA_VALID; 776 } 777 778 if (sp->flags & SRB_CRC_PROT_DMA_VALID) { 779 dma_unmap_sg(&ha->pdev->dev, scsi_prot_sglist(cmd), 780 scsi_prot_sg_count(cmd), cmd->sc_data_direction); 781 sp->flags &= ~SRB_CRC_PROT_DMA_VALID; 782 } 783 784 if (sp->flags & SRB_CRC_CTX_DSD_VALID) { 785 /* List assured to be having elements */ 786 qla2x00_clean_dsd_pool(ha, sp->u.scmd.crc_ctx); 787 sp->flags &= ~SRB_CRC_CTX_DSD_VALID; 788 } 789 790 if (sp->flags & SRB_DIF_BUNDL_DMA_VALID) { 791 struct crc_context *difctx = sp->u.scmd.crc_ctx; 792 struct dsd_dma *dif_dsd, *nxt_dsd; 793 794 list_for_each_entry_safe(dif_dsd, nxt_dsd, 795 &difctx->ldif_dma_hndl_list, list) { 796 list_del(&dif_dsd->list); 797 dma_pool_free(ha->dif_bundl_pool, dif_dsd->dsd_addr, 798 dif_dsd->dsd_list_dma); 799 kfree(dif_dsd); 800 difctx->no_dif_bundl--; 801 } 802 803 list_for_each_entry_safe(dif_dsd, nxt_dsd, 804 &difctx->ldif_dsd_list, list) { 805 list_del(&dif_dsd->list); 806 dma_pool_free(ha->dl_dma_pool, dif_dsd->dsd_addr, 807 dif_dsd->dsd_list_dma); 808 kfree(dif_dsd); 809 difctx->no_ldif_dsd--; 810 } 811 812 if (difctx->no_ldif_dsd) { 813 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 814 "%s: difctx->no_ldif_dsd=%x\n", 815 __func__, difctx->no_ldif_dsd); 816 } 817 818 if (difctx->no_dif_bundl) { 819 ql_dbg(ql_dbg_tgt+ql_dbg_verbose, sp->vha, 0xe022, 820 "%s: difctx->no_dif_bundl=%x\n", 821 __func__, difctx->no_dif_bundl); 822 } 823 sp->flags &= ~SRB_DIF_BUNDL_DMA_VALID; 824 } 825 826 if (sp->flags & SRB_FCP_CMND_DMA_VALID) { 827 struct ct6_dsd *ctx1 = &sp->u.scmd.ct6_ctx; 828 829 dma_pool_free(ha->fcp_cmnd_dma_pool, ctx1->fcp_cmnd, 830 ctx1->fcp_cmnd_dma); 831 list_splice(&ctx1->dsd_list, &sp->qpair->dsd_list); 832 sp->qpair->dsd_inuse -= ctx1->dsd_use_cnt; 833 sp->qpair->dsd_avail += ctx1->dsd_use_cnt; 834 sp->flags &= ~SRB_FCP_CMND_DMA_VALID; 835 } 836 837 if (sp->flags & SRB_CRC_CTX_DMA_VALID) { 838 struct crc_context *ctx0 = sp->u.scmd.crc_ctx; 839 840 dma_pool_free(ha->dl_dma_pool, ctx0, ctx0->crc_ctx_dma); 841 sp->flags &= ~SRB_CRC_CTX_DMA_VALID; 842 } 843 844 if (sp->flags & SRB_GOT_BUF) 845 qla_put_buf(sp->qpair, &sp->u.scmd.buf_dsc); 846 } 847 848 void qla2xxx_qpair_sp_compl(srb_t *sp, int res) 849 { 850 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 851 struct completion *comp = sp->comp; 852 853 /* ref: INIT */ 854 kref_put(&sp->cmd_kref, qla2x00_sp_release); 855 cmd->result = res; 856 sp->type = 0; 857 scsi_done(cmd); 858 if (comp) 859 complete(comp); 860 } 861 862 static enum scsi_qc_status qla2xxx_queuecommand(struct Scsi_Host *host, 863 struct scsi_cmnd *cmd) 864 { 865 scsi_qla_host_t *vha = shost_priv(host); 866 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 867 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 868 struct qla_hw_data *ha = vha->hw; 869 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 870 srb_t *sp; 871 int rval; 872 873 if (unlikely(test_bit(UNLOADING, &base_vha->dpc_flags)) || 874 WARN_ON_ONCE(!rport)) { 875 cmd->result = DID_NO_CONNECT << 16; 876 goto qc24_fail_command; 877 } 878 879 if (ha->mqenable) { 880 uint32_t tag; 881 uint16_t hwq; 882 struct qla_qpair *qpair = NULL; 883 884 tag = blk_mq_unique_tag(scsi_cmd_to_rq(cmd)); 885 hwq = blk_mq_unique_tag_to_hwq(tag); 886 qpair = ha->queue_pair_map[hwq]; 887 888 if (qpair) 889 return qla2xxx_mqueuecommand(host, cmd, qpair); 890 } 891 892 if (ha->flags.eeh_busy) { 893 if (ha->flags.pci_channel_io_perm_failure) { 894 ql_dbg(ql_dbg_aer, vha, 0x9010, 895 "PCI Channel IO permanent failure, exiting " 896 "cmd=%p.\n", cmd); 897 cmd->result = DID_NO_CONNECT << 16; 898 } else { 899 ql_dbg(ql_dbg_aer, vha, 0x9011, 900 "EEH_Busy, Requeuing the cmd=%p.\n", cmd); 901 cmd->result = DID_REQUEUE << 16; 902 } 903 goto qc24_fail_command; 904 } 905 906 rval = fc_remote_port_chkready(rport); 907 if (rval) { 908 cmd->result = rval; 909 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3003, 910 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 911 cmd, rval); 912 goto qc24_fail_command; 913 } 914 915 if (!vha->flags.difdix_supported && 916 scsi_get_prot_op(cmd) != SCSI_PROT_NORMAL) { 917 ql_dbg(ql_dbg_io, vha, 0x3004, 918 "DIF Cap not reg, fail DIF capable cmd's:%p.\n", 919 cmd); 920 cmd->result = DID_NO_CONNECT << 16; 921 goto qc24_fail_command; 922 } 923 924 if (!fcport || fcport->deleted) { 925 cmd->result = DID_IMM_RETRY << 16; 926 goto qc24_fail_command; 927 } 928 929 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 930 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 931 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 932 ql_dbg(ql_dbg_io, vha, 0x3005, 933 "Returning DNC, fcport_state=%d loop_state=%d.\n", 934 atomic_read(&fcport->state), 935 atomic_read(&base_vha->loop_state)); 936 cmd->result = DID_NO_CONNECT << 16; 937 goto qc24_fail_command; 938 } 939 goto qc24_target_busy; 940 } 941 942 /* 943 * Return target busy if we've received a non-zero retry_delay_timer 944 * in a FCP_RSP. 945 */ 946 if (fcport->retry_delay_timestamp == 0) { 947 /* retry delay not set */ 948 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 949 fcport->retry_delay_timestamp = 0; 950 else 951 goto qc24_target_busy; 952 953 sp = scsi_cmd_priv(cmd); 954 /* ref: INIT */ 955 qla2xxx_init_sp(sp, vha, vha->hw->base_qpair, fcport); 956 957 sp->u.scmd.cmd = cmd; 958 sp->type = SRB_SCSI_CMD; 959 sp->free = qla2x00_sp_free_dma; 960 sp->done = qla2x00_sp_compl; 961 962 rval = ha->isp_ops->start_scsi(sp); 963 if (rval != QLA_SUCCESS) { 964 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3013, 965 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 966 goto qc24_host_busy_free_sp; 967 } 968 969 return 0; 970 971 qc24_host_busy_free_sp: 972 /* ref: INIT */ 973 kref_put(&sp->cmd_kref, qla2x00_sp_release); 974 975 qc24_target_busy: 976 return SCSI_MLQUEUE_TARGET_BUSY; 977 978 qc24_fail_command: 979 scsi_done(cmd); 980 981 return 0; 982 } 983 984 /* For MQ supported I/O */ 985 static enum scsi_qc_status 986 qla2xxx_mqueuecommand(struct Scsi_Host *host, struct scsi_cmnd *cmd, 987 struct qla_qpair *qpair) 988 { 989 scsi_qla_host_t *vha = shost_priv(host); 990 fc_port_t *fcport = (struct fc_port *) cmd->device->hostdata; 991 struct fc_rport *rport = starget_to_rport(scsi_target(cmd->device)); 992 struct qla_hw_data *ha = vha->hw; 993 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 994 srb_t *sp; 995 int rval; 996 997 rval = rport ? fc_remote_port_chkready(rport) : (DID_NO_CONNECT << 16); 998 if (rval) { 999 cmd->result = rval; 1000 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3076, 1001 "fc_remote_port_chkready failed for cmd=%p, rval=0x%x.\n", 1002 cmd, rval); 1003 goto qc24_fail_command; 1004 } 1005 1006 if (!qpair->online) { 1007 ql_dbg(ql_dbg_io, vha, 0x3077, 1008 "qpair not online. eeh_busy=%d.\n", ha->flags.eeh_busy); 1009 cmd->result = DID_NO_CONNECT << 16; 1010 goto qc24_fail_command; 1011 } 1012 1013 if (!fcport || fcport->deleted) { 1014 cmd->result = DID_IMM_RETRY << 16; 1015 goto qc24_fail_command; 1016 } 1017 1018 if (atomic_read(&fcport->state) != FCS_ONLINE || fcport->deleted) { 1019 if (atomic_read(&fcport->state) == FCS_DEVICE_DEAD || 1020 atomic_read(&base_vha->loop_state) == LOOP_DEAD) { 1021 ql_dbg(ql_dbg_io, vha, 0x3077, 1022 "Returning DNC, fcport_state=%d loop_state=%d.\n", 1023 atomic_read(&fcport->state), 1024 atomic_read(&base_vha->loop_state)); 1025 cmd->result = DID_NO_CONNECT << 16; 1026 goto qc24_fail_command; 1027 } 1028 goto qc24_target_busy; 1029 } 1030 1031 /* 1032 * Return target busy if we've received a non-zero retry_delay_timer 1033 * in a FCP_RSP. 1034 */ 1035 if (fcport->retry_delay_timestamp == 0) { 1036 /* retry delay not set */ 1037 } else if (time_after(jiffies, fcport->retry_delay_timestamp)) 1038 fcport->retry_delay_timestamp = 0; 1039 else 1040 goto qc24_target_busy; 1041 1042 sp = scsi_cmd_priv(cmd); 1043 /* ref: INIT */ 1044 qla2xxx_init_sp(sp, vha, qpair, fcport); 1045 1046 sp->u.scmd.cmd = cmd; 1047 sp->type = SRB_SCSI_CMD; 1048 sp->free = qla2xxx_qpair_sp_free_dma; 1049 sp->done = qla2xxx_qpair_sp_compl; 1050 1051 rval = ha->isp_ops->start_scsi_mq(sp); 1052 if (rval != QLA_SUCCESS) { 1053 ql_dbg(ql_dbg_io + ql_dbg_verbose, vha, 0x3078, 1054 "Start scsi failed rval=%d for cmd=%p.\n", rval, cmd); 1055 goto qc24_host_busy_free_sp; 1056 } 1057 1058 return 0; 1059 1060 qc24_host_busy_free_sp: 1061 /* ref: INIT */ 1062 kref_put(&sp->cmd_kref, qla2x00_sp_release); 1063 1064 qc24_target_busy: 1065 return SCSI_MLQUEUE_TARGET_BUSY; 1066 1067 qc24_fail_command: 1068 scsi_done(cmd); 1069 1070 return 0; 1071 } 1072 1073 /* 1074 * qla2x00_wait_for_hba_online 1075 * Wait till the HBA is online after going through 1076 * <= MAX_RETRIES_OF_ISP_ABORT or 1077 * finally HBA is disabled ie marked offline 1078 * 1079 * Input: 1080 * ha - pointer to host adapter structure 1081 * 1082 * Note: 1083 * Does context switching-Release SPIN_LOCK 1084 * (if any) before calling this routine. 1085 * 1086 * Return: 1087 * Success (Adapter is online) : 0 1088 * Failed (Adapter is offline/disabled) : 1 1089 */ 1090 int 1091 qla2x00_wait_for_hba_online(scsi_qla_host_t *vha) 1092 { 1093 int return_status; 1094 unsigned long wait_online; 1095 struct qla_hw_data *ha = vha->hw; 1096 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1097 1098 wait_online = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1099 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1100 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1101 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1102 ha->dpc_active) && time_before(jiffies, wait_online)) { 1103 1104 msleep(1000); 1105 } 1106 if (base_vha->flags.online) 1107 return_status = QLA_SUCCESS; 1108 else 1109 return_status = QLA_FUNCTION_FAILED; 1110 1111 return (return_status); 1112 } 1113 1114 static inline int test_fcport_count(scsi_qla_host_t *vha) 1115 { 1116 struct qla_hw_data *ha = vha->hw; 1117 unsigned long flags; 1118 int res; 1119 /* Return 0 = sleep, x=wake */ 1120 1121 spin_lock_irqsave(&ha->tgt.sess_lock, flags); 1122 ql_dbg(ql_dbg_init, vha, 0x00ec, 1123 "tgt %p, fcport_count=%d\n", 1124 vha, vha->fcport_count); 1125 res = (vha->fcport_count == 0); 1126 if (res) { 1127 struct fc_port *fcport; 1128 1129 list_for_each_entry(fcport, &vha->vp_fcports, list) { 1130 if (fcport->deleted != QLA_SESS_DELETED) { 1131 /* session(s) may not be fully logged in 1132 * (ie fcport_count=0), but session 1133 * deletion thread(s) may be inflight. 1134 */ 1135 1136 res = 0; 1137 break; 1138 } 1139 } 1140 } 1141 spin_unlock_irqrestore(&ha->tgt.sess_lock, flags); 1142 1143 return res; 1144 } 1145 1146 /* 1147 * qla2x00_wait_for_sess_deletion can only be called from remove_one. 1148 * it has dependency on UNLOADING flag to stop device discovery 1149 */ 1150 void 1151 qla2x00_wait_for_sess_deletion(scsi_qla_host_t *vha) 1152 { 1153 u8 i; 1154 1155 qla2x00_mark_all_devices_lost(vha); 1156 1157 for (i = 0; i < 10; i++) { 1158 if (wait_event_timeout(vha->fcport_waitQ, 1159 test_fcport_count(vha), HZ) > 0) 1160 break; 1161 } 1162 1163 flush_workqueue(vha->hw->wq); 1164 } 1165 1166 /* 1167 * qla2x00_wait_for_hba_ready 1168 * Wait till the HBA is ready before doing driver unload 1169 * 1170 * Input: 1171 * ha - pointer to host adapter structure 1172 * 1173 * Note: 1174 * Does context switching-Release SPIN_LOCK 1175 * (if any) before calling this routine. 1176 * 1177 */ 1178 static void 1179 qla2x00_wait_for_hba_ready(scsi_qla_host_t *vha) 1180 { 1181 struct qla_hw_data *ha = vha->hw; 1182 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1183 1184 while ((qla2x00_reset_active(vha) || ha->dpc_active || 1185 ha->flags.mbox_busy) || 1186 test_bit(FX00_RESET_RECOVERY, &vha->dpc_flags) || 1187 test_bit(FX00_TARGET_SCAN, &vha->dpc_flags) || 1188 (vha->scan.scan_flags & SF_SCANNING)) { 1189 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 1190 break; 1191 msleep(1000); 1192 } 1193 } 1194 1195 int 1196 qla2x00_wait_for_chip_reset(scsi_qla_host_t *vha) 1197 { 1198 int return_status; 1199 unsigned long wait_reset; 1200 struct qla_hw_data *ha = vha->hw; 1201 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1202 1203 wait_reset = jiffies + (MAX_LOOP_TIMEOUT * HZ); 1204 while (((test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags)) || 1205 test_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags) || 1206 test_bit(ISP_ABORT_RETRY, &base_vha->dpc_flags) || 1207 ha->dpc_active) && time_before(jiffies, wait_reset)) { 1208 1209 msleep(1000); 1210 1211 if (!test_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 1212 ha->flags.chip_reset_done) 1213 break; 1214 } 1215 if (ha->flags.chip_reset_done) 1216 return_status = QLA_SUCCESS; 1217 else 1218 return_status = QLA_FUNCTION_FAILED; 1219 1220 return return_status; 1221 } 1222 1223 /************************************************************************** 1224 * qla2xxx_eh_abort 1225 * 1226 * Description: 1227 * The abort function will abort the specified command. 1228 * 1229 * Input: 1230 * cmd = Linux SCSI command packet to be aborted. 1231 * 1232 * Returns: 1233 * Either SUCCESS or FAILED. 1234 * 1235 * Note: 1236 * Only return FAILED if command not returned by firmware. 1237 **************************************************************************/ 1238 static int 1239 qla2xxx_eh_abort(struct scsi_cmnd *cmd) 1240 { 1241 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1242 DECLARE_COMPLETION_ONSTACK(comp); 1243 srb_t *sp; 1244 int ret; 1245 unsigned int id; 1246 uint64_t lun; 1247 int rval; 1248 struct qla_hw_data *ha = vha->hw; 1249 uint32_t ratov_j; 1250 struct qla_qpair *qpair; 1251 unsigned long flags; 1252 int fast_fail_status = SUCCESS; 1253 1254 if (qla2x00_isp_reg_stat(ha)) { 1255 ql_log(ql_log_info, vha, 0x8042, 1256 "PCI/Register disconnect, exiting.\n"); 1257 qla_pci_set_eeh_busy(vha); 1258 return FAILED; 1259 } 1260 1261 /* Save any FAST_IO_FAIL value to return later if abort succeeds */ 1262 ret = fc_block_scsi_eh(cmd); 1263 if (ret != 0) 1264 fast_fail_status = ret; 1265 1266 sp = scsi_cmd_priv(cmd); 1267 qpair = sp->qpair; 1268 1269 vha->cmd_timeout_cnt++; 1270 1271 if ((sp->fcport && sp->fcport->deleted) || !qpair) 1272 return fast_fail_status != SUCCESS ? fast_fail_status : FAILED; 1273 1274 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1275 sp->comp = ∁ 1276 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1277 1278 1279 id = cmd->device->id; 1280 lun = cmd->device->lun; 1281 1282 ql_dbg(ql_dbg_taskm, vha, 0x8002, 1283 "Aborting from RISC nexus=%ld:%d:%llu sp=%p cmd=%p handle=%x\n", 1284 vha->host_no, id, lun, sp, cmd, sp->handle); 1285 1286 /* 1287 * Abort will release the original Command/sp from FW. Let the 1288 * original command call scsi_done. In return, he will wakeup 1289 * this sleeping thread. 1290 */ 1291 rval = ha->isp_ops->abort_command(sp); 1292 1293 ql_dbg(ql_dbg_taskm, vha, 0x8003, 1294 "Abort command mbx cmd=%p, rval=%x.\n", cmd, rval); 1295 1296 /* Wait for the command completion. */ 1297 ratov_j = ha->r_a_tov / 10 * 4; 1298 ratov_j = secs_to_jiffies(ratov_j); 1299 switch (rval) { 1300 case QLA_SUCCESS: 1301 if (!wait_for_completion_timeout(&comp, ratov_j)) { 1302 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1303 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1304 __func__, ha->r_a_tov/10); 1305 ret = FAILED; 1306 } else { 1307 ret = fast_fail_status; 1308 } 1309 break; 1310 default: 1311 ret = FAILED; 1312 break; 1313 } 1314 1315 sp->comp = NULL; 1316 1317 ql_log(ql_log_info, vha, 0x801c, 1318 "Abort command issued nexus=%ld:%d:%llu -- %x.\n", 1319 vha->host_no, id, lun, ret); 1320 1321 return ret; 1322 } 1323 1324 #define ABORT_POLLING_PERIOD 1000 1325 #define ABORT_WAIT_ITER ((2 * 1000) / (ABORT_POLLING_PERIOD)) 1326 1327 /* 1328 * Returns: QLA_SUCCESS or QLA_FUNCTION_FAILED. 1329 */ 1330 static int 1331 __qla2x00_eh_wait_for_pending_commands(struct qla_qpair *qpair, unsigned int t, 1332 uint64_t l, enum nexus_wait_type type) 1333 { 1334 int cnt, match, status; 1335 unsigned long flags; 1336 scsi_qla_host_t *vha = qpair->vha; 1337 struct req_que *req = qpair->req; 1338 srb_t *sp; 1339 struct scsi_cmnd *cmd; 1340 unsigned long wait_iter = ABORT_WAIT_ITER; 1341 bool found; 1342 struct qla_hw_data *ha = vha->hw; 1343 1344 status = QLA_SUCCESS; 1345 1346 while (wait_iter--) { 1347 found = false; 1348 1349 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1350 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1351 sp = req->outstanding_cmds[cnt]; 1352 if (!sp) 1353 continue; 1354 if (sp->type != SRB_SCSI_CMD) 1355 continue; 1356 if (vha->vp_idx != sp->vha->vp_idx) 1357 continue; 1358 match = 0; 1359 cmd = GET_CMD_SP(sp); 1360 switch (type) { 1361 case WAIT_HOST: 1362 match = 1; 1363 break; 1364 case WAIT_TARGET: 1365 if (sp->fcport) 1366 match = sp->fcport->d_id.b24 == t; 1367 else 1368 match = 0; 1369 break; 1370 case WAIT_LUN: 1371 if (sp->fcport) 1372 match = (sp->fcport->d_id.b24 == t && 1373 cmd->device->lun == l); 1374 else 1375 match = 0; 1376 break; 1377 } 1378 if (!match) 1379 continue; 1380 1381 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1382 1383 if (unlikely(pci_channel_offline(ha->pdev)) || 1384 ha->flags.eeh_busy) { 1385 ql_dbg(ql_dbg_taskm, vha, 0x8005, 1386 "Return:eh_wait.\n"); 1387 return status; 1388 } 1389 1390 /* 1391 * SRB_SCSI_CMD is still in the outstanding_cmds array. 1392 * it means scsi_done has not called. Wait for it to 1393 * clear from outstanding_cmds. 1394 */ 1395 msleep(ABORT_POLLING_PERIOD); 1396 spin_lock_irqsave(qpair->qp_lock_ptr, flags); 1397 found = true; 1398 } 1399 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags); 1400 1401 if (!found) 1402 break; 1403 } 1404 1405 if (wait_iter == -1) 1406 status = QLA_FUNCTION_FAILED; 1407 1408 return status; 1409 } 1410 1411 int 1412 qla2x00_eh_wait_for_pending_commands(scsi_qla_host_t *vha, unsigned int t, 1413 uint64_t l, enum nexus_wait_type type) 1414 { 1415 struct qla_qpair *qpair; 1416 struct qla_hw_data *ha = vha->hw; 1417 int i, status = QLA_SUCCESS; 1418 1419 status = __qla2x00_eh_wait_for_pending_commands(ha->base_qpair, t, l, 1420 type); 1421 for (i = 0; status == QLA_SUCCESS && i < ha->max_qpairs; i++) { 1422 qpair = ha->queue_pair_map[i]; 1423 if (!qpair) 1424 continue; 1425 status = __qla2x00_eh_wait_for_pending_commands(qpair, t, l, 1426 type); 1427 } 1428 return status; 1429 } 1430 1431 static char *reset_errors[] = { 1432 "HBA not online", 1433 "HBA not ready", 1434 "Task management failed", 1435 "Waiting for command completions", 1436 }; 1437 1438 static int 1439 qla2xxx_eh_device_reset(struct scsi_cmnd *cmd) 1440 { 1441 struct scsi_device *sdev = cmd->device; 1442 scsi_qla_host_t *vha = shost_priv(sdev->host); 1443 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1444 fc_port_t *fcport = (struct fc_port *) sdev->hostdata; 1445 struct qla_hw_data *ha = vha->hw; 1446 int err; 1447 1448 if (qla2x00_isp_reg_stat(ha)) { 1449 ql_log(ql_log_info, vha, 0x803e, 1450 "PCI/Register disconnect, exiting.\n"); 1451 qla_pci_set_eeh_busy(vha); 1452 return FAILED; 1453 } 1454 1455 if (!fcport) { 1456 return FAILED; 1457 } 1458 1459 err = fc_block_rport(rport); 1460 if (err != 0) 1461 return err; 1462 1463 if (fcport->deleted) 1464 return FAILED; 1465 1466 ql_log(ql_log_info, vha, 0x8009, 1467 "DEVICE RESET ISSUED nexus=%ld:%d:%llu cmd=%p.\n", vha->host_no, 1468 sdev->id, sdev->lun, cmd); 1469 1470 err = 0; 1471 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1472 ql_log(ql_log_warn, vha, 0x800a, 1473 "Wait for hba online failed for cmd=%p.\n", cmd); 1474 goto eh_reset_failed; 1475 } 1476 err = 2; 1477 if (ha->isp_ops->lun_reset(fcport, sdev->lun, 1) 1478 != QLA_SUCCESS) { 1479 ql_log(ql_log_warn, vha, 0x800c, 1480 "do_reset failed for cmd=%p.\n", cmd); 1481 goto eh_reset_failed; 1482 } 1483 err = 3; 1484 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 1485 cmd->device->lun, 1486 WAIT_LUN) != QLA_SUCCESS) { 1487 ql_log(ql_log_warn, vha, 0x800d, 1488 "wait for pending cmds failed for cmd=%p.\n", cmd); 1489 goto eh_reset_failed; 1490 } 1491 1492 ql_log(ql_log_info, vha, 0x800e, 1493 "DEVICE RESET SUCCEEDED nexus:%ld:%d:%llu cmd=%p.\n", 1494 vha->host_no, sdev->id, sdev->lun, cmd); 1495 1496 return SUCCESS; 1497 1498 eh_reset_failed: 1499 ql_log(ql_log_info, vha, 0x800f, 1500 "DEVICE RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1501 reset_errors[err], vha->host_no, sdev->id, sdev->lun, 1502 cmd); 1503 vha->reset_cmd_err_cnt++; 1504 return FAILED; 1505 } 1506 1507 static int 1508 qla2xxx_eh_target_reset(struct scsi_cmnd *cmd) 1509 { 1510 struct scsi_device *sdev = cmd->device; 1511 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1512 scsi_qla_host_t *vha = shost_priv(rport_to_shost(rport)); 1513 struct qla_hw_data *ha = vha->hw; 1514 fc_port_t *fcport = *(fc_port_t **)rport->dd_data; 1515 int err; 1516 1517 if (qla2x00_isp_reg_stat(ha)) { 1518 ql_log(ql_log_info, vha, 0x803f, 1519 "PCI/Register disconnect, exiting.\n"); 1520 qla_pci_set_eeh_busy(vha); 1521 return FAILED; 1522 } 1523 1524 if (!fcport) { 1525 return FAILED; 1526 } 1527 1528 err = fc_block_rport(rport); 1529 if (err != 0) 1530 return err; 1531 1532 if (fcport->deleted) 1533 return FAILED; 1534 1535 ql_log(ql_log_info, vha, 0x8009, 1536 "TARGET RESET ISSUED nexus=%ld:%d cmd=%p.\n", vha->host_no, 1537 sdev->id, cmd); 1538 1539 err = 0; 1540 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1541 ql_log(ql_log_warn, vha, 0x800a, 1542 "Wait for hba online failed for cmd=%p.\n", cmd); 1543 goto eh_reset_failed; 1544 } 1545 err = 2; 1546 if (ha->isp_ops->target_reset(fcport, 0, 0) != QLA_SUCCESS) { 1547 ql_log(ql_log_warn, vha, 0x800c, 1548 "target_reset failed for cmd=%p.\n", cmd); 1549 goto eh_reset_failed; 1550 } 1551 err = 3; 1552 if (qla2x00_eh_wait_for_pending_commands(vha, fcport->d_id.b24, 0, 1553 WAIT_TARGET) != QLA_SUCCESS) { 1554 ql_log(ql_log_warn, vha, 0x800d, 1555 "wait for pending cmds failed for cmd=%p.\n", cmd); 1556 goto eh_reset_failed; 1557 } 1558 1559 ql_log(ql_log_info, vha, 0x800e, 1560 "TARGET RESET SUCCEEDED nexus:%ld:%d cmd=%p.\n", 1561 vha->host_no, sdev->id, cmd); 1562 1563 return SUCCESS; 1564 1565 eh_reset_failed: 1566 ql_log(ql_log_info, vha, 0x800f, 1567 "TARGET RESET FAILED: %s nexus=%ld:%d:%llu cmd=%p.\n", 1568 reset_errors[err], vha->host_no, cmd->device->id, cmd->device->lun, 1569 cmd); 1570 vha->reset_cmd_err_cnt++; 1571 return FAILED; 1572 } 1573 1574 /************************************************************************** 1575 * qla2xxx_eh_bus_reset 1576 * 1577 * Description: 1578 * The bus reset function will reset the bus and abort any executing 1579 * commands. 1580 * 1581 * Input: 1582 * cmd = Linux SCSI command packet of the command that cause the 1583 * bus reset. 1584 * 1585 * Returns: 1586 * SUCCESS/FAILURE (defined as macro in scsi.h). 1587 * 1588 **************************************************************************/ 1589 static int 1590 qla2xxx_eh_bus_reset(struct scsi_cmnd *cmd) 1591 { 1592 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1593 int ret = FAILED; 1594 unsigned int id; 1595 uint64_t lun; 1596 struct qla_hw_data *ha = vha->hw; 1597 1598 if (qla2x00_isp_reg_stat(ha)) { 1599 ql_log(ql_log_info, vha, 0x8040, 1600 "PCI/Register disconnect, exiting.\n"); 1601 qla_pci_set_eeh_busy(vha); 1602 return FAILED; 1603 } 1604 1605 id = cmd->device->id; 1606 lun = cmd->device->lun; 1607 1608 if (qla2x00_chip_is_down(vha)) 1609 return ret; 1610 1611 ql_log(ql_log_info, vha, 0x8012, 1612 "BUS RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1613 1614 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1615 ql_log(ql_log_fatal, vha, 0x8013, 1616 "Wait for hba online failed board disabled.\n"); 1617 goto eh_bus_reset_done; 1618 } 1619 1620 if (qla2x00_loop_reset(vha) == QLA_SUCCESS) 1621 ret = SUCCESS; 1622 1623 if (ret == FAILED) 1624 goto eh_bus_reset_done; 1625 1626 /* Flush outstanding commands. */ 1627 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) != 1628 QLA_SUCCESS) { 1629 ql_log(ql_log_warn, vha, 0x8014, 1630 "Wait for pending commands failed.\n"); 1631 ret = FAILED; 1632 } 1633 1634 eh_bus_reset_done: 1635 ql_log(ql_log_warn, vha, 0x802b, 1636 "BUS RESET %s nexus=%ld:%d:%llu.\n", 1637 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1638 1639 return ret; 1640 } 1641 1642 /************************************************************************** 1643 * qla2xxx_eh_host_reset 1644 * 1645 * Description: 1646 * The reset function will reset the Adapter. 1647 * 1648 * Input: 1649 * cmd = Linux SCSI command packet of the command that cause the 1650 * adapter reset. 1651 * 1652 * Returns: 1653 * Either SUCCESS or FAILED. 1654 * 1655 * Note: 1656 **************************************************************************/ 1657 static int 1658 qla2xxx_eh_host_reset(struct scsi_cmnd *cmd) 1659 { 1660 scsi_qla_host_t *vha = shost_priv(cmd->device->host); 1661 struct qla_hw_data *ha = vha->hw; 1662 int ret = FAILED; 1663 unsigned int id; 1664 uint64_t lun; 1665 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 1666 1667 if (qla2x00_isp_reg_stat(ha)) { 1668 ql_log(ql_log_info, vha, 0x8041, 1669 "PCI/Register disconnect, exiting.\n"); 1670 qla_pci_set_eeh_busy(vha); 1671 return SUCCESS; 1672 } 1673 1674 id = cmd->device->id; 1675 lun = cmd->device->lun; 1676 1677 ql_log(ql_log_info, vha, 0x8018, 1678 "ADAPTER RESET ISSUED nexus=%ld:%d:%llu.\n", vha->host_no, id, lun); 1679 1680 /* 1681 * No point in issuing another reset if one is active. Also do not 1682 * attempt a reset if we are updating flash. 1683 */ 1684 if (qla2x00_reset_active(vha) || ha->optrom_state != QLA_SWAITING) 1685 goto eh_host_reset_lock; 1686 1687 if (vha != base_vha) { 1688 if (qla2x00_vp_abort_isp(vha)) 1689 goto eh_host_reset_lock; 1690 } else { 1691 if (IS_P3P_TYPE(vha->hw)) { 1692 if (!qla82xx_fcoe_ctx_reset(vha)) { 1693 /* Ctx reset success */ 1694 ret = SUCCESS; 1695 goto eh_host_reset_lock; 1696 } 1697 /* fall thru if ctx reset failed */ 1698 } 1699 if (ha->wq) 1700 flush_workqueue(ha->wq); 1701 1702 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1703 if (ha->isp_ops->abort_isp(base_vha)) { 1704 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1705 /* failed. schedule dpc to try */ 1706 set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); 1707 1708 if (qla2x00_wait_for_hba_online(vha) != QLA_SUCCESS) { 1709 ql_log(ql_log_warn, vha, 0x802a, 1710 "wait for hba online failed.\n"); 1711 goto eh_host_reset_lock; 1712 } 1713 } 1714 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 1715 } 1716 1717 /* Waiting for command to be returned to OS.*/ 1718 if (qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST) == 1719 QLA_SUCCESS) 1720 ret = SUCCESS; 1721 1722 eh_host_reset_lock: 1723 ql_log(ql_log_info, vha, 0x8017, 1724 "ADAPTER RESET %s nexus=%ld:%d:%llu.\n", 1725 (ret == FAILED) ? "FAILED" : "SUCCEEDED", vha->host_no, id, lun); 1726 1727 return ret; 1728 } 1729 1730 /* 1731 * qla2x00_loop_reset 1732 * Issue loop reset. 1733 * 1734 * Input: 1735 * ha = adapter block pointer. 1736 * 1737 * Returns: 1738 * 0 = success 1739 */ 1740 int 1741 qla2x00_loop_reset(scsi_qla_host_t *vha) 1742 { 1743 int ret; 1744 struct qla_hw_data *ha = vha->hw; 1745 1746 if (IS_QLAFX00(ha)) 1747 return QLA_SUCCESS; 1748 1749 if (ha->flags.enable_lip_full_login && !IS_CNA_CAPABLE(ha)) { 1750 atomic_set(&vha->loop_state, LOOP_DOWN); 1751 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME); 1752 qla2x00_mark_all_devices_lost(vha); 1753 ret = qla2x00_full_login_lip(vha); 1754 if (ret != QLA_SUCCESS) { 1755 ql_dbg(ql_dbg_taskm, vha, 0x802d, 1756 "full_login_lip=%d.\n", ret); 1757 } 1758 } 1759 1760 if (ha->flags.enable_lip_reset) { 1761 ret = qla2x00_lip_reset(vha); 1762 if (ret != QLA_SUCCESS) 1763 ql_dbg(ql_dbg_taskm, vha, 0x802e, 1764 "lip_reset failed (%d).\n", ret); 1765 } 1766 1767 /* Issue marker command only when we are going to start the I/O */ 1768 vha->marker_needed = 1; 1769 1770 return QLA_SUCCESS; 1771 } 1772 1773 /* 1774 * The caller must ensure that no completion interrupts will happen 1775 * while this function is in progress. 1776 */ 1777 static void qla2x00_abort_srb(struct qla_qpair *qp, srb_t *sp, const int res, 1778 unsigned long *flags) 1779 __releases(qp->qp_lock_ptr) 1780 __acquires(qp->qp_lock_ptr) 1781 { 1782 DECLARE_COMPLETION_ONSTACK(comp); 1783 scsi_qla_host_t *vha = qp->vha; 1784 struct qla_hw_data *ha = vha->hw; 1785 struct scsi_cmnd *cmd = GET_CMD_SP(sp); 1786 int rval; 1787 bool ret_cmd; 1788 uint32_t ratov_j; 1789 1790 lockdep_assert_held(qp->qp_lock_ptr); 1791 1792 if (qla2x00_chip_is_down(vha)) { 1793 sp->done(sp, res); 1794 return; 1795 } 1796 1797 if (sp->type == SRB_NVME_CMD || sp->type == SRB_NVME_LS || 1798 (sp->type == SRB_SCSI_CMD && !ha->flags.eeh_busy && 1799 !test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags) && 1800 !qla2x00_isp_reg_stat(ha))) { 1801 if (sp->comp) { 1802 sp->done(sp, res); 1803 return; 1804 } 1805 1806 sp->comp = ∁ 1807 spin_unlock_irqrestore(qp->qp_lock_ptr, *flags); 1808 1809 rval = ha->isp_ops->abort_command(sp); 1810 /* Wait for command completion. */ 1811 ret_cmd = false; 1812 ratov_j = ha->r_a_tov / 10 * 4; 1813 ratov_j = secs_to_jiffies(ratov_j); 1814 switch (rval) { 1815 case QLA_SUCCESS: 1816 if (wait_for_completion_timeout(&comp, ratov_j)) { 1817 ql_dbg(ql_dbg_taskm, vha, 0xffff, 1818 "%s: Abort wait timer (4 * R_A_TOV[%d]) expired\n", 1819 __func__, ha->r_a_tov/10); 1820 ret_cmd = true; 1821 } 1822 /* else FW return SP to driver */ 1823 break; 1824 default: 1825 ret_cmd = true; 1826 break; 1827 } 1828 1829 spin_lock_irqsave(qp->qp_lock_ptr, *flags); 1830 switch (sp->type) { 1831 case SRB_SCSI_CMD: 1832 if (ret_cmd && blk_mq_request_started(scsi_cmd_to_rq(cmd))) 1833 sp->done(sp, res); 1834 break; 1835 default: 1836 if (ret_cmd) 1837 sp->done(sp, res); 1838 break; 1839 } 1840 } else { 1841 sp->done(sp, res); 1842 } 1843 } 1844 1845 /* 1846 * The caller must ensure that no completion interrupts will happen 1847 * while this function is in progress. 1848 */ 1849 static void 1850 __qla2x00_abort_all_cmds(struct qla_qpair *qp, int res) 1851 { 1852 int cnt; 1853 unsigned long flags; 1854 srb_t *sp; 1855 scsi_qla_host_t *vha = qp->vha; 1856 struct qla_hw_data *ha = vha->hw; 1857 struct req_que *req; 1858 struct qla_tgt *tgt = vha->vha_tgt.qla_tgt; 1859 struct qla_tgt_cmd *cmd; 1860 1861 if (!ha->req_q_map) 1862 return; 1863 spin_lock_irqsave(qp->qp_lock_ptr, flags); 1864 req = qp->req; 1865 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++) { 1866 sp = req->outstanding_cmds[cnt]; 1867 if (sp) { 1868 switch (sp->cmd_type) { 1869 case TYPE_SRB: 1870 qla2x00_abort_srb(qp, sp, res, &flags); 1871 break; 1872 case TYPE_TGT_CMD: 1873 if (!vha->hw->tgt.tgt_ops || !tgt || 1874 qla_ini_mode_enabled(vha)) { 1875 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf003, 1876 "HOST-ABORT-HNDLR: dpc_flags=%lx. Target mode disabled\n", 1877 vha->dpc_flags); 1878 continue; 1879 } 1880 cmd = (struct qla_tgt_cmd *)sp; 1881 1882 if (cmd->sg_mapped) 1883 qlt_unmap_sg(vha, cmd); 1884 1885 if (cmd->state == QLA_TGT_STATE_NEED_DATA) { 1886 cmd->aborted = 1; 1887 cmd->write_data_transferred = 0; 1888 cmd->state = QLA_TGT_STATE_DATA_IN; 1889 ha->tgt.tgt_ops->handle_data(cmd); 1890 } else { 1891 ha->tgt.tgt_ops->free_cmd(cmd); 1892 } 1893 break; 1894 case TYPE_TGT_TMCMD: 1895 /* 1896 * Currently, only ABTS response gets on the 1897 * outstanding_cmds[] 1898 */ 1899 qlt_free_ul_mcmd(ha, 1900 (struct qla_tgt_mgmt_cmd *) sp); 1901 break; 1902 default: 1903 break; 1904 } 1905 req->outstanding_cmds[cnt] = NULL; 1906 } 1907 } 1908 spin_unlock_irqrestore(qp->qp_lock_ptr, flags); 1909 } 1910 1911 /* 1912 * The caller must ensure that no completion interrupts will happen 1913 * while this function is in progress. 1914 */ 1915 void 1916 qla2x00_abort_all_cmds(scsi_qla_host_t *vha, int res) 1917 { 1918 int que; 1919 struct qla_hw_data *ha = vha->hw; 1920 1921 /* Continue only if initialization complete. */ 1922 if (!ha->base_qpair) 1923 return; 1924 __qla2x00_abort_all_cmds(ha->base_qpair, res); 1925 1926 if (!ha->queue_pair_map) 1927 return; 1928 for (que = 0; que < ha->max_qpairs; que++) { 1929 if (!ha->queue_pair_map[que]) 1930 continue; 1931 1932 __qla2x00_abort_all_cmds(ha->queue_pair_map[que], res); 1933 } 1934 } 1935 1936 static int 1937 qla2xxx_sdev_init(struct scsi_device *sdev) 1938 { 1939 struct fc_rport *rport = starget_to_rport(scsi_target(sdev)); 1940 1941 if (!rport || fc_remote_port_chkready(rport)) 1942 return -ENXIO; 1943 1944 sdev->hostdata = *(fc_port_t **)rport->dd_data; 1945 1946 return 0; 1947 } 1948 1949 static int 1950 qla2xxx_sdev_configure(struct scsi_device *sdev, struct queue_limits *lim) 1951 { 1952 scsi_qla_host_t *vha = shost_priv(sdev->host); 1953 struct req_que *req = vha->req; 1954 1955 scsi_change_queue_depth(sdev, req->max_q_depth); 1956 return 0; 1957 } 1958 1959 static void 1960 qla2xxx_sdev_destroy(struct scsi_device *sdev) 1961 { 1962 sdev->hostdata = NULL; 1963 } 1964 1965 /** 1966 * qla2x00_config_dma_addressing() - Configure OS DMA addressing method. 1967 * @ha: HA context 1968 * 1969 * At exit, the @ha's flags.enable_64bit_addressing set to indicated 1970 * supported addressing method. 1971 */ 1972 static void 1973 qla2x00_config_dma_addressing(struct qla_hw_data *ha) 1974 { 1975 /* Assume a 32bit DMA mask. */ 1976 ha->flags.enable_64bit_addressing = 0; 1977 1978 if (!dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1979 /* Any upper-dword bits set? */ 1980 if (MSD(dma_get_required_mask(&ha->pdev->dev)) && 1981 !dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(64))) { 1982 /* Ok, a 64bit DMA mask is applicable. */ 1983 ha->flags.enable_64bit_addressing = 1; 1984 ha->isp_ops->calc_req_entries = qla2x00_calc_iocbs_64; 1985 ha->isp_ops->build_iocbs = qla2x00_build_scsi_iocbs_64; 1986 return; 1987 } 1988 } 1989 1990 dma_set_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1991 dma_set_coherent_mask(&ha->pdev->dev, DMA_BIT_MASK(32)); 1992 } 1993 1994 static void 1995 qla2x00_enable_intrs(struct qla_hw_data *ha) 1996 { 1997 unsigned long flags = 0; 1998 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1999 2000 spin_lock_irqsave(&ha->hardware_lock, flags); 2001 ha->interrupts_on = 1; 2002 /* enable risc and host interrupts */ 2003 wrt_reg_word(®->ictrl, ICR_EN_INT | ICR_EN_RISC); 2004 rd_reg_word(®->ictrl); 2005 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2006 2007 } 2008 2009 static void 2010 qla2x00_disable_intrs(struct qla_hw_data *ha) 2011 { 2012 unsigned long flags = 0; 2013 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2014 2015 spin_lock_irqsave(&ha->hardware_lock, flags); 2016 ha->interrupts_on = 0; 2017 /* disable risc and host interrupts */ 2018 wrt_reg_word(®->ictrl, 0); 2019 rd_reg_word(®->ictrl); 2020 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2021 } 2022 2023 static void 2024 qla24xx_enable_intrs(struct qla_hw_data *ha) 2025 { 2026 unsigned long flags = 0; 2027 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2028 2029 spin_lock_irqsave(&ha->hardware_lock, flags); 2030 ha->interrupts_on = 1; 2031 wrt_reg_dword(®->ictrl, ICRX_EN_RISC_INT); 2032 rd_reg_dword(®->ictrl); 2033 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2034 } 2035 2036 static void 2037 qla24xx_disable_intrs(struct qla_hw_data *ha) 2038 { 2039 unsigned long flags = 0; 2040 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 2041 2042 if (IS_NOPOLLING_TYPE(ha)) 2043 return; 2044 spin_lock_irqsave(&ha->hardware_lock, flags); 2045 ha->interrupts_on = 0; 2046 wrt_reg_dword(®->ictrl, 0); 2047 rd_reg_dword(®->ictrl); 2048 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2049 } 2050 2051 static int 2052 qla2x00_iospace_config(struct qla_hw_data *ha) 2053 { 2054 resource_size_t pio; 2055 uint16_t msix; 2056 2057 if (pci_request_selected_regions(ha->pdev, ha->bars, 2058 QLA2XXX_DRIVER_NAME)) { 2059 ql_log_pci(ql_log_fatal, ha->pdev, 0x0011, 2060 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2061 pci_name(ha->pdev)); 2062 goto iospace_error_exit; 2063 } 2064 if (!(ha->bars & 1)) 2065 goto skip_pio; 2066 2067 /* We only need PIO for Flash operations on ISP2312 v2 chips. */ 2068 pio = pci_resource_start(ha->pdev, 0); 2069 if (pci_resource_flags(ha->pdev, 0) & IORESOURCE_IO) { 2070 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2071 ql_log_pci(ql_log_warn, ha->pdev, 0x0012, 2072 "Invalid pci I/O region size (%s).\n", 2073 pci_name(ha->pdev)); 2074 pio = 0; 2075 } 2076 } else { 2077 ql_log_pci(ql_log_warn, ha->pdev, 0x0013, 2078 "Region #0 no a PIO resource (%s).\n", 2079 pci_name(ha->pdev)); 2080 pio = 0; 2081 } 2082 ha->pio_address = pio; 2083 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0014, 2084 "PIO address=%llu.\n", 2085 (unsigned long long)ha->pio_address); 2086 2087 skip_pio: 2088 /* Use MMIO operations for all accesses. */ 2089 if (!(pci_resource_flags(ha->pdev, 1) & IORESOURCE_MEM)) { 2090 ql_log_pci(ql_log_fatal, ha->pdev, 0x0015, 2091 "Region #1 not an MMIO resource (%s), aborting.\n", 2092 pci_name(ha->pdev)); 2093 goto iospace_error_exit; 2094 } 2095 if (pci_resource_len(ha->pdev, 1) < MIN_IOBASE_LEN) { 2096 ql_log_pci(ql_log_fatal, ha->pdev, 0x0016, 2097 "Invalid PCI mem region size (%s), aborting.\n", 2098 pci_name(ha->pdev)); 2099 goto iospace_error_exit; 2100 } 2101 2102 ha->iobase = ioremap(pci_resource_start(ha->pdev, 1), MIN_IOBASE_LEN); 2103 if (!ha->iobase) { 2104 ql_log_pci(ql_log_fatal, ha->pdev, 0x0017, 2105 "Cannot remap MMIO (%s), aborting.\n", 2106 pci_name(ha->pdev)); 2107 goto iospace_error_exit; 2108 } 2109 2110 /* Determine queue resources */ 2111 ha->max_req_queues = ha->max_rsp_queues = 1; 2112 ha->msix_count = QLA_BASE_VECTORS; 2113 2114 /* Check if FW supports MQ or not */ 2115 if (!(ha->fw_attributes & BIT_6)) 2116 goto mqiobase_exit; 2117 2118 if (!ql2xmqsupport || !ql2xnvmeenable || 2119 (!IS_QLA25XX(ha) && !IS_QLA81XX(ha))) 2120 goto mqiobase_exit; 2121 2122 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 3), 2123 pci_resource_len(ha->pdev, 3)); 2124 if (ha->mqiobase) { 2125 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0018, 2126 "MQIO Base=%p.\n", ha->mqiobase); 2127 /* Read MSIX vector size of the board */ 2128 pci_read_config_word(ha->pdev, QLA_PCI_MSIX_CONTROL, &msix); 2129 ha->msix_count = msix + 1; 2130 /* Max queues are bounded by available msix vectors */ 2131 /* MB interrupt uses 1 vector */ 2132 ha->max_req_queues = ha->msix_count - 1; 2133 ha->max_rsp_queues = ha->max_req_queues; 2134 /* Queue pairs is the max value minus the base queue pair */ 2135 ha->max_qpairs = ha->max_rsp_queues - 1; 2136 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0188, 2137 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2138 2139 ql_log_pci(ql_log_info, ha->pdev, 0x001a, 2140 "MSI-X vector count: %d.\n", ha->msix_count); 2141 } else 2142 ql_log_pci(ql_log_info, ha->pdev, 0x001b, 2143 "BAR 3 not enabled.\n"); 2144 2145 mqiobase_exit: 2146 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x001c, 2147 "MSIX Count: %d.\n", ha->msix_count); 2148 return (0); 2149 2150 iospace_error_exit: 2151 return (-ENOMEM); 2152 } 2153 2154 2155 static int 2156 qla83xx_iospace_config(struct qla_hw_data *ha) 2157 { 2158 uint16_t msix; 2159 2160 if (pci_request_selected_regions(ha->pdev, ha->bars, 2161 QLA2XXX_DRIVER_NAME)) { 2162 ql_log_pci(ql_log_fatal, ha->pdev, 0x0117, 2163 "Failed to reserve PIO/MMIO regions (%s), aborting.\n", 2164 pci_name(ha->pdev)); 2165 2166 goto iospace_error_exit; 2167 } 2168 2169 /* Use MMIO operations for all accesses. */ 2170 if (!(pci_resource_flags(ha->pdev, 0) & IORESOURCE_MEM)) { 2171 ql_log_pci(ql_log_warn, ha->pdev, 0x0118, 2172 "Invalid pci I/O region size (%s).\n", 2173 pci_name(ha->pdev)); 2174 goto iospace_error_exit; 2175 } 2176 if (pci_resource_len(ha->pdev, 0) < MIN_IOBASE_LEN) { 2177 ql_log_pci(ql_log_warn, ha->pdev, 0x0119, 2178 "Invalid PCI mem region size (%s), aborting\n", 2179 pci_name(ha->pdev)); 2180 goto iospace_error_exit; 2181 } 2182 2183 ha->iobase = ioremap(pci_resource_start(ha->pdev, 0), MIN_IOBASE_LEN); 2184 if (!ha->iobase) { 2185 ql_log_pci(ql_log_fatal, ha->pdev, 0x011a, 2186 "Cannot remap MMIO (%s), aborting.\n", 2187 pci_name(ha->pdev)); 2188 goto iospace_error_exit; 2189 } 2190 2191 /* 64bit PCI BAR - BAR2 will correspoond to region 4 */ 2192 /* 83XX 26XX always use MQ type access for queues 2193 * - mbar 2, a.k.a region 4 */ 2194 ha->max_req_queues = ha->max_rsp_queues = 1; 2195 ha->msix_count = QLA_BASE_VECTORS; 2196 ha->mqiobase = ioremap(pci_resource_start(ha->pdev, 4), 2197 pci_resource_len(ha->pdev, 4)); 2198 2199 if (!ha->mqiobase) { 2200 ql_log_pci(ql_log_fatal, ha->pdev, 0x011d, 2201 "BAR2/region4 not enabled\n"); 2202 goto mqiobase_exit; 2203 } 2204 2205 ha->msixbase = ioremap(pci_resource_start(ha->pdev, 2), 2206 pci_resource_len(ha->pdev, 2)); 2207 if (ha->msixbase) { 2208 /* Read MSIX vector size of the board */ 2209 pci_read_config_word(ha->pdev, 2210 QLA_83XX_PCI_MSIX_CONTROL, &msix); 2211 ha->msix_count = (msix & PCI_MSIX_FLAGS_QSIZE) + 1; 2212 /* 2213 * By default, driver uses at least two msix vectors 2214 * (default & rspq) 2215 */ 2216 if (ql2xmqsupport || ql2xnvmeenable) { 2217 /* MB interrupt uses 1 vector */ 2218 ha->max_req_queues = ha->msix_count - 1; 2219 2220 /* ATIOQ needs 1 vector. That's 1 less QPair */ 2221 if (QLA_TGT_MODE_ENABLED()) 2222 ha->max_req_queues--; 2223 2224 ha->max_rsp_queues = ha->max_req_queues; 2225 2226 /* Queue pairs is the max value minus 2227 * the base queue pair */ 2228 ha->max_qpairs = ha->max_req_queues - 1; 2229 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x00e3, 2230 "Max no of queues pairs: %d.\n", ha->max_qpairs); 2231 } 2232 ql_log_pci(ql_log_info, ha->pdev, 0x011c, 2233 "MSI-X vector count: %d.\n", ha->msix_count); 2234 } else 2235 ql_log_pci(ql_log_info, ha->pdev, 0x011e, 2236 "BAR 1 not enabled.\n"); 2237 2238 mqiobase_exit: 2239 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011f, 2240 "MSIX Count: %d.\n", ha->msix_count); 2241 return 0; 2242 2243 iospace_error_exit: 2244 return -ENOMEM; 2245 } 2246 2247 static struct isp_operations qla2100_isp_ops = { 2248 .pci_config = qla2100_pci_config, 2249 .reset_chip = qla2x00_reset_chip, 2250 .chip_diag = qla2x00_chip_diag, 2251 .config_rings = qla2x00_config_rings, 2252 .reset_adapter = qla2x00_reset_adapter, 2253 .nvram_config = qla2x00_nvram_config, 2254 .update_fw_options = qla2x00_update_fw_options, 2255 .load_risc = qla2x00_load_risc, 2256 .pci_info_str = qla2x00_pci_info_str, 2257 .fw_version_str = qla2x00_fw_version_str, 2258 .intr_handler = qla2100_intr_handler, 2259 .enable_intrs = qla2x00_enable_intrs, 2260 .disable_intrs = qla2x00_disable_intrs, 2261 .abort_command = qla2x00_abort_command, 2262 .target_reset = qla2x00_abort_target, 2263 .lun_reset = qla2x00_lun_reset, 2264 .fabric_login = qla2x00_login_fabric, 2265 .fabric_logout = qla2x00_fabric_logout, 2266 .calc_req_entries = qla2x00_calc_iocbs_32, 2267 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2268 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2269 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2270 .read_nvram = qla2x00_read_nvram_data, 2271 .write_nvram = qla2x00_write_nvram_data, 2272 .fw_dump = qla2100_fw_dump, 2273 .beacon_on = NULL, 2274 .beacon_off = NULL, 2275 .beacon_blink = NULL, 2276 .read_optrom = qla2x00_read_optrom_data, 2277 .write_optrom = qla2x00_write_optrom_data, 2278 .get_flash_version = qla2x00_get_flash_version, 2279 .start_scsi = qla2x00_start_scsi, 2280 .start_scsi_mq = NULL, 2281 .abort_isp = qla2x00_abort_isp, 2282 .iospace_config = qla2x00_iospace_config, 2283 .initialize_adapter = qla2x00_initialize_adapter, 2284 }; 2285 2286 static struct isp_operations qla2300_isp_ops = { 2287 .pci_config = qla2300_pci_config, 2288 .reset_chip = qla2x00_reset_chip, 2289 .chip_diag = qla2x00_chip_diag, 2290 .config_rings = qla2x00_config_rings, 2291 .reset_adapter = qla2x00_reset_adapter, 2292 .nvram_config = qla2x00_nvram_config, 2293 .update_fw_options = qla2x00_update_fw_options, 2294 .load_risc = qla2x00_load_risc, 2295 .pci_info_str = qla2x00_pci_info_str, 2296 .fw_version_str = qla2x00_fw_version_str, 2297 .intr_handler = qla2300_intr_handler, 2298 .enable_intrs = qla2x00_enable_intrs, 2299 .disable_intrs = qla2x00_disable_intrs, 2300 .abort_command = qla2x00_abort_command, 2301 .target_reset = qla2x00_abort_target, 2302 .lun_reset = qla2x00_lun_reset, 2303 .fabric_login = qla2x00_login_fabric, 2304 .fabric_logout = qla2x00_fabric_logout, 2305 .calc_req_entries = qla2x00_calc_iocbs_32, 2306 .build_iocbs = qla2x00_build_scsi_iocbs_32, 2307 .prep_ms_iocb = qla2x00_prep_ms_iocb, 2308 .prep_ms_fdmi_iocb = qla2x00_prep_ms_fdmi_iocb, 2309 .read_nvram = qla2x00_read_nvram_data, 2310 .write_nvram = qla2x00_write_nvram_data, 2311 .fw_dump = qla2300_fw_dump, 2312 .beacon_on = qla2x00_beacon_on, 2313 .beacon_off = qla2x00_beacon_off, 2314 .beacon_blink = qla2x00_beacon_blink, 2315 .read_optrom = qla2x00_read_optrom_data, 2316 .write_optrom = qla2x00_write_optrom_data, 2317 .get_flash_version = qla2x00_get_flash_version, 2318 .start_scsi = qla2x00_start_scsi, 2319 .start_scsi_mq = NULL, 2320 .abort_isp = qla2x00_abort_isp, 2321 .iospace_config = qla2x00_iospace_config, 2322 .initialize_adapter = qla2x00_initialize_adapter, 2323 }; 2324 2325 static struct isp_operations qla24xx_isp_ops = { 2326 .pci_config = qla24xx_pci_config, 2327 .reset_chip = qla24xx_reset_chip, 2328 .chip_diag = qla24xx_chip_diag, 2329 .config_rings = qla24xx_config_rings, 2330 .reset_adapter = qla24xx_reset_adapter, 2331 .nvram_config = qla24xx_nvram_config, 2332 .update_fw_options = qla24xx_update_fw_options, 2333 .load_risc = qla24xx_load_risc, 2334 .pci_info_str = qla24xx_pci_info_str, 2335 .fw_version_str = qla24xx_fw_version_str, 2336 .intr_handler = qla24xx_intr_handler, 2337 .enable_intrs = qla24xx_enable_intrs, 2338 .disable_intrs = qla24xx_disable_intrs, 2339 .abort_command = qla24xx_abort_command, 2340 .target_reset = qla24xx_abort_target, 2341 .lun_reset = qla24xx_lun_reset, 2342 .fabric_login = qla24xx_login_fabric, 2343 .fabric_logout = qla24xx_fabric_logout, 2344 .calc_req_entries = NULL, 2345 .build_iocbs = NULL, 2346 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2347 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2348 .read_nvram = qla24xx_read_nvram_data, 2349 .write_nvram = qla24xx_write_nvram_data, 2350 .fw_dump = qla24xx_fw_dump, 2351 .beacon_on = qla24xx_beacon_on, 2352 .beacon_off = qla24xx_beacon_off, 2353 .beacon_blink = qla24xx_beacon_blink, 2354 .read_optrom = qla24xx_read_optrom_data, 2355 .write_optrom = qla24xx_write_optrom_data, 2356 .get_flash_version = qla24xx_get_flash_version, 2357 .start_scsi = qla24xx_start_scsi, 2358 .start_scsi_mq = NULL, 2359 .abort_isp = qla2x00_abort_isp, 2360 .iospace_config = qla2x00_iospace_config, 2361 .initialize_adapter = qla2x00_initialize_adapter, 2362 }; 2363 2364 static struct isp_operations qla25xx_isp_ops = { 2365 .pci_config = qla25xx_pci_config, 2366 .reset_chip = qla24xx_reset_chip, 2367 .chip_diag = qla24xx_chip_diag, 2368 .config_rings = qla24xx_config_rings, 2369 .reset_adapter = qla24xx_reset_adapter, 2370 .nvram_config = qla24xx_nvram_config, 2371 .update_fw_options = qla24xx_update_fw_options, 2372 .load_risc = qla24xx_load_risc, 2373 .pci_info_str = qla24xx_pci_info_str, 2374 .fw_version_str = qla24xx_fw_version_str, 2375 .intr_handler = qla24xx_intr_handler, 2376 .enable_intrs = qla24xx_enable_intrs, 2377 .disable_intrs = qla24xx_disable_intrs, 2378 .abort_command = qla24xx_abort_command, 2379 .target_reset = qla24xx_abort_target, 2380 .lun_reset = qla24xx_lun_reset, 2381 .fabric_login = qla24xx_login_fabric, 2382 .fabric_logout = qla24xx_fabric_logout, 2383 .calc_req_entries = NULL, 2384 .build_iocbs = NULL, 2385 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2386 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2387 .read_nvram = qla25xx_read_nvram_data, 2388 .write_nvram = qla25xx_write_nvram_data, 2389 .fw_dump = qla25xx_fw_dump, 2390 .beacon_on = qla24xx_beacon_on, 2391 .beacon_off = qla24xx_beacon_off, 2392 .beacon_blink = qla24xx_beacon_blink, 2393 .read_optrom = qla25xx_read_optrom_data, 2394 .write_optrom = qla24xx_write_optrom_data, 2395 .get_flash_version = qla24xx_get_flash_version, 2396 .start_scsi = qla24xx_dif_start_scsi, 2397 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2398 .abort_isp = qla2x00_abort_isp, 2399 .iospace_config = qla2x00_iospace_config, 2400 .initialize_adapter = qla2x00_initialize_adapter, 2401 }; 2402 2403 static struct isp_operations qla81xx_isp_ops = { 2404 .pci_config = qla25xx_pci_config, 2405 .reset_chip = qla24xx_reset_chip, 2406 .chip_diag = qla24xx_chip_diag, 2407 .config_rings = qla24xx_config_rings, 2408 .reset_adapter = qla24xx_reset_adapter, 2409 .nvram_config = qla81xx_nvram_config, 2410 .update_fw_options = qla24xx_update_fw_options, 2411 .load_risc = qla81xx_load_risc, 2412 .pci_info_str = qla24xx_pci_info_str, 2413 .fw_version_str = qla24xx_fw_version_str, 2414 .intr_handler = qla24xx_intr_handler, 2415 .enable_intrs = qla24xx_enable_intrs, 2416 .disable_intrs = qla24xx_disable_intrs, 2417 .abort_command = qla24xx_abort_command, 2418 .target_reset = qla24xx_abort_target, 2419 .lun_reset = qla24xx_lun_reset, 2420 .fabric_login = qla24xx_login_fabric, 2421 .fabric_logout = qla24xx_fabric_logout, 2422 .calc_req_entries = NULL, 2423 .build_iocbs = NULL, 2424 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2425 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2426 .read_nvram = NULL, 2427 .write_nvram = NULL, 2428 .fw_dump = qla81xx_fw_dump, 2429 .beacon_on = qla24xx_beacon_on, 2430 .beacon_off = qla24xx_beacon_off, 2431 .beacon_blink = qla83xx_beacon_blink, 2432 .read_optrom = qla25xx_read_optrom_data, 2433 .write_optrom = qla24xx_write_optrom_data, 2434 .get_flash_version = qla24xx_get_flash_version, 2435 .start_scsi = qla24xx_dif_start_scsi, 2436 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2437 .abort_isp = qla2x00_abort_isp, 2438 .iospace_config = qla2x00_iospace_config, 2439 .initialize_adapter = qla2x00_initialize_adapter, 2440 }; 2441 2442 static struct isp_operations qla82xx_isp_ops = { 2443 .pci_config = qla82xx_pci_config, 2444 .reset_chip = qla82xx_reset_chip, 2445 .chip_diag = qla24xx_chip_diag, 2446 .config_rings = qla82xx_config_rings, 2447 .reset_adapter = qla24xx_reset_adapter, 2448 .nvram_config = qla81xx_nvram_config, 2449 .update_fw_options = qla24xx_update_fw_options, 2450 .load_risc = qla82xx_load_risc, 2451 .pci_info_str = qla24xx_pci_info_str, 2452 .fw_version_str = qla24xx_fw_version_str, 2453 .intr_handler = qla82xx_intr_handler, 2454 .enable_intrs = qla82xx_enable_intrs, 2455 .disable_intrs = qla82xx_disable_intrs, 2456 .abort_command = qla24xx_abort_command, 2457 .target_reset = qla24xx_abort_target, 2458 .lun_reset = qla24xx_lun_reset, 2459 .fabric_login = qla24xx_login_fabric, 2460 .fabric_logout = qla24xx_fabric_logout, 2461 .calc_req_entries = NULL, 2462 .build_iocbs = NULL, 2463 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2464 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2465 .read_nvram = qla24xx_read_nvram_data, 2466 .write_nvram = qla24xx_write_nvram_data, 2467 .fw_dump = qla82xx_fw_dump, 2468 .beacon_on = qla82xx_beacon_on, 2469 .beacon_off = qla82xx_beacon_off, 2470 .beacon_blink = NULL, 2471 .read_optrom = qla82xx_read_optrom_data, 2472 .write_optrom = qla82xx_write_optrom_data, 2473 .get_flash_version = qla82xx_get_flash_version, 2474 .start_scsi = qla82xx_start_scsi, 2475 .start_scsi_mq = NULL, 2476 .abort_isp = qla82xx_abort_isp, 2477 .iospace_config = qla82xx_iospace_config, 2478 .initialize_adapter = qla2x00_initialize_adapter, 2479 }; 2480 2481 static struct isp_operations qla8044_isp_ops = { 2482 .pci_config = qla82xx_pci_config, 2483 .reset_chip = qla82xx_reset_chip, 2484 .chip_diag = qla24xx_chip_diag, 2485 .config_rings = qla82xx_config_rings, 2486 .reset_adapter = qla24xx_reset_adapter, 2487 .nvram_config = qla81xx_nvram_config, 2488 .update_fw_options = qla24xx_update_fw_options, 2489 .load_risc = qla82xx_load_risc, 2490 .pci_info_str = qla24xx_pci_info_str, 2491 .fw_version_str = qla24xx_fw_version_str, 2492 .intr_handler = qla8044_intr_handler, 2493 .enable_intrs = qla82xx_enable_intrs, 2494 .disable_intrs = qla82xx_disable_intrs, 2495 .abort_command = qla24xx_abort_command, 2496 .target_reset = qla24xx_abort_target, 2497 .lun_reset = qla24xx_lun_reset, 2498 .fabric_login = qla24xx_login_fabric, 2499 .fabric_logout = qla24xx_fabric_logout, 2500 .calc_req_entries = NULL, 2501 .build_iocbs = NULL, 2502 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2503 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2504 .read_nvram = NULL, 2505 .write_nvram = NULL, 2506 .fw_dump = qla8044_fw_dump, 2507 .beacon_on = qla82xx_beacon_on, 2508 .beacon_off = qla82xx_beacon_off, 2509 .beacon_blink = NULL, 2510 .read_optrom = qla8044_read_optrom_data, 2511 .write_optrom = qla8044_write_optrom_data, 2512 .get_flash_version = qla82xx_get_flash_version, 2513 .start_scsi = qla82xx_start_scsi, 2514 .start_scsi_mq = NULL, 2515 .abort_isp = qla8044_abort_isp, 2516 .iospace_config = qla82xx_iospace_config, 2517 .initialize_adapter = qla2x00_initialize_adapter, 2518 }; 2519 2520 static struct isp_operations qla83xx_isp_ops = { 2521 .pci_config = qla25xx_pci_config, 2522 .reset_chip = qla24xx_reset_chip, 2523 .chip_diag = qla24xx_chip_diag, 2524 .config_rings = qla24xx_config_rings, 2525 .reset_adapter = qla24xx_reset_adapter, 2526 .nvram_config = qla81xx_nvram_config, 2527 .update_fw_options = qla24xx_update_fw_options, 2528 .load_risc = qla81xx_load_risc, 2529 .pci_info_str = qla24xx_pci_info_str, 2530 .fw_version_str = qla24xx_fw_version_str, 2531 .intr_handler = qla24xx_intr_handler, 2532 .enable_intrs = qla24xx_enable_intrs, 2533 .disable_intrs = qla24xx_disable_intrs, 2534 .abort_command = qla24xx_abort_command, 2535 .target_reset = qla24xx_abort_target, 2536 .lun_reset = qla24xx_lun_reset, 2537 .fabric_login = qla24xx_login_fabric, 2538 .fabric_logout = qla24xx_fabric_logout, 2539 .calc_req_entries = NULL, 2540 .build_iocbs = NULL, 2541 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2542 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2543 .read_nvram = NULL, 2544 .write_nvram = NULL, 2545 .fw_dump = qla83xx_fw_dump, 2546 .beacon_on = qla24xx_beacon_on, 2547 .beacon_off = qla24xx_beacon_off, 2548 .beacon_blink = qla83xx_beacon_blink, 2549 .read_optrom = qla25xx_read_optrom_data, 2550 .write_optrom = qla24xx_write_optrom_data, 2551 .get_flash_version = qla24xx_get_flash_version, 2552 .start_scsi = qla24xx_dif_start_scsi, 2553 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2554 .abort_isp = qla2x00_abort_isp, 2555 .iospace_config = qla83xx_iospace_config, 2556 .initialize_adapter = qla2x00_initialize_adapter, 2557 }; 2558 2559 static struct isp_operations qlafx00_isp_ops = { 2560 .pci_config = qlafx00_pci_config, 2561 .reset_chip = qlafx00_soft_reset, 2562 .chip_diag = qlafx00_chip_diag, 2563 .config_rings = qlafx00_config_rings, 2564 .reset_adapter = qlafx00_soft_reset, 2565 .nvram_config = NULL, 2566 .update_fw_options = NULL, 2567 .load_risc = NULL, 2568 .pci_info_str = qlafx00_pci_info_str, 2569 .fw_version_str = qlafx00_fw_version_str, 2570 .intr_handler = qlafx00_intr_handler, 2571 .enable_intrs = qlafx00_enable_intrs, 2572 .disable_intrs = qlafx00_disable_intrs, 2573 .abort_command = qla24xx_async_abort_command, 2574 .target_reset = qlafx00_abort_target, 2575 .lun_reset = qlafx00_lun_reset, 2576 .fabric_login = NULL, 2577 .fabric_logout = NULL, 2578 .calc_req_entries = NULL, 2579 .build_iocbs = NULL, 2580 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2581 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2582 .read_nvram = qla24xx_read_nvram_data, 2583 .write_nvram = qla24xx_write_nvram_data, 2584 .fw_dump = NULL, 2585 .beacon_on = qla24xx_beacon_on, 2586 .beacon_off = qla24xx_beacon_off, 2587 .beacon_blink = NULL, 2588 .read_optrom = qla24xx_read_optrom_data, 2589 .write_optrom = qla24xx_write_optrom_data, 2590 .get_flash_version = qla24xx_get_flash_version, 2591 .start_scsi = qlafx00_start_scsi, 2592 .start_scsi_mq = NULL, 2593 .abort_isp = qlafx00_abort_isp, 2594 .iospace_config = qlafx00_iospace_config, 2595 .initialize_adapter = qlafx00_initialize_adapter, 2596 }; 2597 2598 static struct isp_operations qla27xx_isp_ops = { 2599 .pci_config = qla25xx_pci_config, 2600 .reset_chip = qla24xx_reset_chip, 2601 .chip_diag = qla24xx_chip_diag, 2602 .config_rings = qla24xx_config_rings, 2603 .reset_adapter = qla24xx_reset_adapter, 2604 .nvram_config = qla81xx_nvram_config, 2605 .update_fw_options = qla24xx_update_fw_options, 2606 .load_risc = qla81xx_load_risc, 2607 .pci_info_str = qla24xx_pci_info_str, 2608 .fw_version_str = qla24xx_fw_version_str, 2609 .intr_handler = qla24xx_intr_handler, 2610 .enable_intrs = qla24xx_enable_intrs, 2611 .disable_intrs = qla24xx_disable_intrs, 2612 .abort_command = qla24xx_abort_command, 2613 .target_reset = qla24xx_abort_target, 2614 .lun_reset = qla24xx_lun_reset, 2615 .fabric_login = qla24xx_login_fabric, 2616 .fabric_logout = qla24xx_fabric_logout, 2617 .calc_req_entries = NULL, 2618 .build_iocbs = NULL, 2619 .prep_ms_iocb = qla24xx_prep_ms_iocb, 2620 .prep_ms_fdmi_iocb = qla24xx_prep_ms_fdmi_iocb, 2621 .read_nvram = NULL, 2622 .write_nvram = NULL, 2623 .fw_dump = qla27xx_fwdump, 2624 .mpi_fw_dump = qla27xx_mpi_fwdump, 2625 .beacon_on = qla24xx_beacon_on, 2626 .beacon_off = qla24xx_beacon_off, 2627 .beacon_blink = qla83xx_beacon_blink, 2628 .read_optrom = qla25xx_read_optrom_data, 2629 .write_optrom = qla24xx_write_optrom_data, 2630 .get_flash_version = qla24xx_get_flash_version, 2631 .start_scsi = qla24xx_dif_start_scsi, 2632 .start_scsi_mq = qla2xxx_dif_start_scsi_mq, 2633 .abort_isp = qla2x00_abort_isp, 2634 .iospace_config = qla83xx_iospace_config, 2635 .initialize_adapter = qla2x00_initialize_adapter, 2636 }; 2637 2638 static inline void 2639 qla2x00_set_isp_flags(struct qla_hw_data *ha) 2640 { 2641 ha->device_type = DT_EXTENDED_IDS; 2642 switch (ha->pdev->device) { 2643 case PCI_DEVICE_ID_QLOGIC_ISP2100: 2644 ha->isp_type |= DT_ISP2100; 2645 ha->device_type &= ~DT_EXTENDED_IDS; 2646 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2647 break; 2648 case PCI_DEVICE_ID_QLOGIC_ISP2200: 2649 ha->isp_type |= DT_ISP2200; 2650 ha->device_type &= ~DT_EXTENDED_IDS; 2651 ha->fw_srisc_address = RISC_START_ADDRESS_2100; 2652 break; 2653 case PCI_DEVICE_ID_QLOGIC_ISP2300: 2654 ha->isp_type |= DT_ISP2300; 2655 ha->device_type |= DT_ZIO_SUPPORTED; 2656 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2657 break; 2658 case PCI_DEVICE_ID_QLOGIC_ISP2312: 2659 ha->isp_type |= DT_ISP2312; 2660 ha->device_type |= DT_ZIO_SUPPORTED; 2661 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2662 break; 2663 case PCI_DEVICE_ID_QLOGIC_ISP2322: 2664 ha->isp_type |= DT_ISP2322; 2665 ha->device_type |= DT_ZIO_SUPPORTED; 2666 if (ha->pdev->subsystem_vendor == 0x1028 && 2667 ha->pdev->subsystem_device == 0x0170) 2668 ha->device_type |= DT_OEM_001; 2669 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2670 break; 2671 case PCI_DEVICE_ID_QLOGIC_ISP6312: 2672 ha->isp_type |= DT_ISP6312; 2673 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2674 break; 2675 case PCI_DEVICE_ID_QLOGIC_ISP6322: 2676 ha->isp_type |= DT_ISP6322; 2677 ha->fw_srisc_address = RISC_START_ADDRESS_2300; 2678 break; 2679 case PCI_DEVICE_ID_QLOGIC_ISP2422: 2680 ha->isp_type |= DT_ISP2422; 2681 ha->device_type |= DT_ZIO_SUPPORTED; 2682 ha->device_type |= DT_FWI2; 2683 ha->device_type |= DT_IIDMA; 2684 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2685 break; 2686 case PCI_DEVICE_ID_QLOGIC_ISP2432: 2687 ha->isp_type |= DT_ISP2432; 2688 ha->device_type |= DT_ZIO_SUPPORTED; 2689 ha->device_type |= DT_FWI2; 2690 ha->device_type |= DT_IIDMA; 2691 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2692 break; 2693 case PCI_DEVICE_ID_QLOGIC_ISP8432: 2694 ha->isp_type |= DT_ISP8432; 2695 ha->device_type |= DT_ZIO_SUPPORTED; 2696 ha->device_type |= DT_FWI2; 2697 ha->device_type |= DT_IIDMA; 2698 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2699 break; 2700 case PCI_DEVICE_ID_QLOGIC_ISP5422: 2701 ha->isp_type |= DT_ISP5422; 2702 ha->device_type |= DT_FWI2; 2703 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2704 break; 2705 case PCI_DEVICE_ID_QLOGIC_ISP5432: 2706 ha->isp_type |= DT_ISP5432; 2707 ha->device_type |= DT_FWI2; 2708 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2709 break; 2710 case PCI_DEVICE_ID_QLOGIC_ISP2532: 2711 ha->isp_type |= DT_ISP2532; 2712 ha->device_type |= DT_ZIO_SUPPORTED; 2713 ha->device_type |= DT_FWI2; 2714 ha->device_type |= DT_IIDMA; 2715 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2716 break; 2717 case PCI_DEVICE_ID_QLOGIC_ISP8001: 2718 ha->isp_type |= DT_ISP8001; 2719 ha->device_type |= DT_ZIO_SUPPORTED; 2720 ha->device_type |= DT_FWI2; 2721 ha->device_type |= DT_IIDMA; 2722 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2723 break; 2724 case PCI_DEVICE_ID_QLOGIC_ISP8021: 2725 ha->isp_type |= DT_ISP8021; 2726 ha->device_type |= DT_ZIO_SUPPORTED; 2727 ha->device_type |= DT_FWI2; 2728 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2729 /* Initialize 82XX ISP flags */ 2730 qla82xx_init_flags(ha); 2731 break; 2732 case PCI_DEVICE_ID_QLOGIC_ISP8044: 2733 ha->isp_type |= DT_ISP8044; 2734 ha->device_type |= DT_ZIO_SUPPORTED; 2735 ha->device_type |= DT_FWI2; 2736 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2737 /* Initialize 82XX ISP flags */ 2738 qla82xx_init_flags(ha); 2739 break; 2740 case PCI_DEVICE_ID_QLOGIC_ISP2031: 2741 ha->isp_type |= DT_ISP2031; 2742 ha->device_type |= DT_ZIO_SUPPORTED; 2743 ha->device_type |= DT_FWI2; 2744 ha->device_type |= DT_IIDMA; 2745 ha->device_type |= DT_T10_PI; 2746 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2747 break; 2748 case PCI_DEVICE_ID_QLOGIC_ISP8031: 2749 ha->isp_type |= DT_ISP8031; 2750 ha->device_type |= DT_ZIO_SUPPORTED; 2751 ha->device_type |= DT_FWI2; 2752 ha->device_type |= DT_IIDMA; 2753 ha->device_type |= DT_T10_PI; 2754 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2755 break; 2756 case PCI_DEVICE_ID_QLOGIC_ISPF001: 2757 ha->isp_type |= DT_ISPFX00; 2758 break; 2759 case PCI_DEVICE_ID_QLOGIC_ISP2071: 2760 ha->isp_type |= DT_ISP2071; 2761 ha->device_type |= DT_ZIO_SUPPORTED; 2762 ha->device_type |= DT_FWI2; 2763 ha->device_type |= DT_IIDMA; 2764 ha->device_type |= DT_T10_PI; 2765 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2766 break; 2767 case PCI_DEVICE_ID_QLOGIC_ISP2271: 2768 ha->isp_type |= DT_ISP2271; 2769 ha->device_type |= DT_ZIO_SUPPORTED; 2770 ha->device_type |= DT_FWI2; 2771 ha->device_type |= DT_IIDMA; 2772 ha->device_type |= DT_T10_PI; 2773 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2774 break; 2775 case PCI_DEVICE_ID_QLOGIC_ISP2261: 2776 ha->isp_type |= DT_ISP2261; 2777 ha->device_type |= DT_ZIO_SUPPORTED; 2778 ha->device_type |= DT_FWI2; 2779 ha->device_type |= DT_IIDMA; 2780 ha->device_type |= DT_T10_PI; 2781 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2782 break; 2783 case PCI_DEVICE_ID_QLOGIC_ISP2081: 2784 case PCI_DEVICE_ID_QLOGIC_ISP2089: 2785 ha->isp_type |= DT_ISP2081; 2786 ha->device_type |= DT_ZIO_SUPPORTED; 2787 ha->device_type |= DT_FWI2; 2788 ha->device_type |= DT_IIDMA; 2789 ha->device_type |= DT_T10_PI; 2790 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2791 break; 2792 case PCI_DEVICE_ID_QLOGIC_ISP2281: 2793 case PCI_DEVICE_ID_QLOGIC_ISP2289: 2794 ha->isp_type |= DT_ISP2281; 2795 ha->device_type |= DT_ZIO_SUPPORTED; 2796 ha->device_type |= DT_FWI2; 2797 ha->device_type |= DT_IIDMA; 2798 ha->device_type |= DT_T10_PI; 2799 ha->fw_srisc_address = RISC_START_ADDRESS_2400; 2800 break; 2801 } 2802 2803 if (IS_QLA82XX(ha)) 2804 ha->port_no = ha->portnum & 1; 2805 else { 2806 /* Get adapter physical port no from interrupt pin register. */ 2807 pci_read_config_byte(ha->pdev, PCI_INTERRUPT_PIN, &ha->port_no); 2808 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || 2809 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 2810 ha->port_no--; 2811 else 2812 ha->port_no = !(ha->port_no & 1); 2813 } 2814 2815 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x000b, 2816 "device_type=0x%x port=%d fw_srisc_address=0x%x.\n", 2817 ha->device_type, ha->port_no, ha->fw_srisc_address); 2818 } 2819 2820 static void 2821 qla2xxx_scan_start(struct Scsi_Host *shost) 2822 { 2823 scsi_qla_host_t *vha = shost_priv(shost); 2824 2825 if (vha->hw->flags.running_gold_fw) 2826 return; 2827 2828 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags); 2829 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags); 2830 set_bit(RSCN_UPDATE, &vha->dpc_flags); 2831 set_bit(NPIV_CONFIG_NEEDED, &vha->dpc_flags); 2832 } 2833 2834 static int 2835 qla2xxx_scan_finished(struct Scsi_Host *shost, unsigned long time) 2836 { 2837 scsi_qla_host_t *vha = shost_priv(shost); 2838 2839 if (test_bit(UNLOADING, &vha->dpc_flags)) 2840 return 1; 2841 if (!vha->host) 2842 return 1; 2843 if (time > vha->hw->loop_reset_delay * HZ) 2844 return 1; 2845 2846 return atomic_read(&vha->loop_state) == LOOP_READY; 2847 } 2848 2849 static void qla_heartbeat_work_fn(struct work_struct *work) 2850 { 2851 struct qla_hw_data *ha = container_of(work, 2852 struct qla_hw_data, heartbeat_work); 2853 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2854 2855 if (!ha->flags.mbox_busy && base_vha->flags.init_done) 2856 qla_no_op_mb(base_vha); 2857 } 2858 2859 static void qla2x00_iocb_work_fn(struct work_struct *work) 2860 { 2861 struct scsi_qla_host *vha = container_of(work, 2862 struct scsi_qla_host, iocb_work); 2863 struct qla_hw_data *ha = vha->hw; 2864 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 2865 int i = 2; 2866 unsigned long flags; 2867 2868 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 2869 return; 2870 2871 while (!list_empty(&vha->work_list) && i > 0) { 2872 qla2x00_do_work(vha); 2873 i--; 2874 } 2875 2876 spin_lock_irqsave(&vha->work_lock, flags); 2877 clear_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags); 2878 spin_unlock_irqrestore(&vha->work_lock, flags); 2879 } 2880 2881 static void 2882 qla_trace_init(void) 2883 { 2884 qla_trc_array = trace_array_get_by_name("qla2xxx", NULL); 2885 if (!qla_trc_array) { 2886 ql_log(ql_log_fatal, NULL, 0x0001, 2887 "Unable to create qla2xxx trace instance, instance logging will be disabled.\n"); 2888 return; 2889 } 2890 2891 QLA_TRACE_ENABLE(qla_trc_array); 2892 } 2893 2894 static void 2895 qla_trace_uninit(void) 2896 { 2897 if (!qla_trc_array) 2898 return; 2899 trace_array_put(qla_trc_array); 2900 } 2901 2902 /* 2903 * PCI driver interface 2904 */ 2905 static int 2906 qla2x00_probe_one(struct pci_dev *pdev, const struct pci_device_id *id) 2907 { 2908 int ret = -ENODEV; 2909 struct Scsi_Host *host; 2910 scsi_qla_host_t *base_vha = NULL; 2911 struct qla_hw_data *ha; 2912 char pci_info[30]; 2913 char fw_str[30], wq_name[30]; 2914 struct scsi_host_template *sht; 2915 int bars, mem_only = 0; 2916 uint16_t req_length = 0, rsp_length = 0; 2917 struct req_que *req = NULL; 2918 struct rsp_que *rsp = NULL; 2919 int i; 2920 2921 bars = pci_select_bars(pdev, IORESOURCE_MEM | IORESOURCE_IO); 2922 sht = &qla2xxx_driver_template; 2923 if (pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422 || 2924 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432 || 2925 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8432 || 2926 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5422 || 2927 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP5432 || 2928 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2532 || 2929 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8001 || 2930 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8021 || 2931 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2031 || 2932 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8031 || 2933 pdev->device == PCI_DEVICE_ID_QLOGIC_ISPF001 || 2934 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP8044 || 2935 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2071 || 2936 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2271 || 2937 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2261 || 2938 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2081 || 2939 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2281 || 2940 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2089 || 2941 pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2289) { 2942 bars = pci_select_bars(pdev, IORESOURCE_MEM); 2943 mem_only = 1; 2944 ql_dbg_pci(ql_dbg_init, pdev, 0x0007, 2945 "Mem only adapter.\n"); 2946 } 2947 ql_dbg_pci(ql_dbg_init, pdev, 0x0008, 2948 "Bars=%d.\n", bars); 2949 2950 if (mem_only) { 2951 if (pci_enable_device_mem(pdev)) 2952 return ret; 2953 } else { 2954 if (pci_enable_device(pdev)) 2955 return ret; 2956 } 2957 2958 if (is_kdump_kernel()) { 2959 ql2xmqsupport = 0; 2960 ql2xallocfwdump = 0; 2961 } 2962 2963 ha = kzalloc(sizeof(struct qla_hw_data), GFP_KERNEL); 2964 if (!ha) { 2965 ql_log_pci(ql_log_fatal, pdev, 0x0009, 2966 "Unable to allocate memory for ha.\n"); 2967 goto disable_device; 2968 } 2969 ql_dbg_pci(ql_dbg_init, pdev, 0x000a, 2970 "Memory allocated for ha=%p.\n", ha); 2971 ha->pdev = pdev; 2972 INIT_LIST_HEAD(&ha->tgt.q_full_list); 2973 spin_lock_init(&ha->tgt.q_full_lock); 2974 spin_lock_init(&ha->tgt.sess_lock); 2975 spin_lock_init(&ha->tgt.atio_lock); 2976 2977 spin_lock_init(&ha->sadb_lock); 2978 INIT_LIST_HEAD(&ha->sadb_tx_index_list); 2979 INIT_LIST_HEAD(&ha->sadb_rx_index_list); 2980 2981 spin_lock_init(&ha->sadb_fp_lock); 2982 2983 if (qla_edif_sadb_build_free_pool(ha)) { 2984 kfree(ha); 2985 goto disable_device; 2986 } 2987 2988 atomic_set(&ha->nvme_active_aen_cnt, 0); 2989 2990 /* Clear our data area */ 2991 ha->bars = bars; 2992 ha->mem_only = mem_only; 2993 spin_lock_init(&ha->hardware_lock); 2994 spin_lock_init(&ha->vport_slock); 2995 mutex_init(&ha->selflogin_lock); 2996 mutex_init(&ha->optrom_mutex); 2997 2998 /* Set ISP-type information. */ 2999 qla2x00_set_isp_flags(ha); 3000 3001 /* Set EEH reset type to fundamental if required by hba */ 3002 if (IS_QLA24XX(ha) || IS_QLA25XX(ha) || IS_QLA81XX(ha) || 3003 IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3004 pdev->needs_freset = 1; 3005 3006 ha->prev_topology = 0; 3007 ha->init_cb_size = sizeof(init_cb_t); 3008 ha->link_data_rate = PORT_SPEED_UNKNOWN; 3009 ha->optrom_size = OPTROM_SIZE_2300; 3010 ha->max_exchg = FW_MAX_EXCHANGES_CNT; 3011 atomic_set(&ha->num_pend_mbx_stage1, 0); 3012 atomic_set(&ha->num_pend_mbx_stage2, 0); 3013 atomic_set(&ha->zio_threshold, DEFAULT_ZIO_THRESHOLD); 3014 ha->last_zio_threshold = DEFAULT_ZIO_THRESHOLD; 3015 INIT_LIST_HEAD(&ha->tmf_pending); 3016 INIT_LIST_HEAD(&ha->tmf_active); 3017 3018 /* Assign ISP specific operations. */ 3019 if (IS_QLA2100(ha)) { 3020 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3021 ha->mbx_count = MAILBOX_REGISTER_COUNT_2100; 3022 req_length = REQUEST_ENTRY_CNT_2100; 3023 rsp_length = RESPONSE_ENTRY_CNT_2100; 3024 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3025 ha->gid_list_info_size = 4; 3026 ha->flash_conf_off = ~0; 3027 ha->flash_data_off = ~0; 3028 ha->nvram_conf_off = ~0; 3029 ha->nvram_data_off = ~0; 3030 ha->isp_ops = &qla2100_isp_ops; 3031 } else if (IS_QLA2200(ha)) { 3032 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3033 ha->mbx_count = MAILBOX_REGISTER_COUNT_2200; 3034 req_length = REQUEST_ENTRY_CNT_2200; 3035 rsp_length = RESPONSE_ENTRY_CNT_2100; 3036 ha->max_loop_id = SNS_LAST_LOOP_ID_2100; 3037 ha->gid_list_info_size = 4; 3038 ha->flash_conf_off = ~0; 3039 ha->flash_data_off = ~0; 3040 ha->nvram_conf_off = ~0; 3041 ha->nvram_data_off = ~0; 3042 ha->isp_ops = &qla2100_isp_ops; 3043 } else if (IS_QLA23XX(ha)) { 3044 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2100; 3045 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3046 req_length = REQUEST_ENTRY_CNT_2200; 3047 rsp_length = RESPONSE_ENTRY_CNT_2300; 3048 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3049 ha->gid_list_info_size = 6; 3050 if (IS_QLA2322(ha) || IS_QLA6322(ha)) 3051 ha->optrom_size = OPTROM_SIZE_2322; 3052 ha->flash_conf_off = ~0; 3053 ha->flash_data_off = ~0; 3054 ha->nvram_conf_off = ~0; 3055 ha->nvram_data_off = ~0; 3056 ha->isp_ops = &qla2300_isp_ops; 3057 } else if (IS_QLA24XX_TYPE(ha)) { 3058 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3059 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3060 req_length = REQUEST_ENTRY_CNT_24XX; 3061 rsp_length = RESPONSE_ENTRY_CNT_2300; 3062 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3063 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3064 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3065 ha->gid_list_info_size = 8; 3066 ha->optrom_size = OPTROM_SIZE_24XX; 3067 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA24XX; 3068 ha->isp_ops = &qla24xx_isp_ops; 3069 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3070 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3071 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3072 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3073 } else if (IS_QLA25XX(ha)) { 3074 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3075 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3076 req_length = REQUEST_ENTRY_CNT_24XX; 3077 rsp_length = RESPONSE_ENTRY_CNT_2300; 3078 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3079 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3080 ha->init_cb_size = sizeof(struct mid_init_cb_24xx); 3081 ha->gid_list_info_size = 8; 3082 ha->optrom_size = OPTROM_SIZE_25XX; 3083 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3084 ha->isp_ops = &qla25xx_isp_ops; 3085 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3086 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3087 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3088 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3089 } else if (IS_QLA81XX(ha)) { 3090 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3091 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3092 req_length = REQUEST_ENTRY_CNT_24XX; 3093 rsp_length = RESPONSE_ENTRY_CNT_2300; 3094 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3095 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3096 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3097 ha->gid_list_info_size = 8; 3098 ha->optrom_size = OPTROM_SIZE_81XX; 3099 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3100 ha->isp_ops = &qla81xx_isp_ops; 3101 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3102 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3103 ha->nvram_conf_off = ~0; 3104 ha->nvram_data_off = ~0; 3105 } else if (IS_QLA82XX(ha)) { 3106 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3107 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3108 req_length = REQUEST_ENTRY_CNT_82XX; 3109 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3110 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3111 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3112 ha->gid_list_info_size = 8; 3113 ha->optrom_size = OPTROM_SIZE_82XX; 3114 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3115 ha->isp_ops = &qla82xx_isp_ops; 3116 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3117 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3118 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3119 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3120 } else if (IS_QLA8044(ha)) { 3121 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3122 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3123 req_length = REQUEST_ENTRY_CNT_82XX; 3124 rsp_length = RESPONSE_ENTRY_CNT_82XX; 3125 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3126 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3127 ha->gid_list_info_size = 8; 3128 ha->optrom_size = OPTROM_SIZE_83XX; 3129 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3130 ha->isp_ops = &qla8044_isp_ops; 3131 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF; 3132 ha->flash_data_off = FARX_ACCESS_FLASH_DATA; 3133 ha->nvram_conf_off = FARX_ACCESS_NVRAM_CONF; 3134 ha->nvram_data_off = FARX_ACCESS_NVRAM_DATA; 3135 } else if (IS_QLA83XX(ha)) { 3136 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3137 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3138 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3139 req_length = REQUEST_ENTRY_CNT_83XX; 3140 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3141 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3142 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3143 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3144 ha->gid_list_info_size = 8; 3145 ha->optrom_size = OPTROM_SIZE_83XX; 3146 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3147 ha->isp_ops = &qla83xx_isp_ops; 3148 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3149 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3150 ha->nvram_conf_off = ~0; 3151 ha->nvram_data_off = ~0; 3152 } else if (IS_QLAFX00(ha)) { 3153 ha->max_fibre_devices = MAX_FIBRE_DEVICES_FX00; 3154 ha->mbx_count = MAILBOX_REGISTER_COUNT_FX00; 3155 ha->aen_mbx_count = AEN_MAILBOX_REGISTER_COUNT_FX00; 3156 req_length = REQUEST_ENTRY_CNT_FX00; 3157 rsp_length = RESPONSE_ENTRY_CNT_FX00; 3158 ha->isp_ops = &qlafx00_isp_ops; 3159 ha->port_down_retry_count = 30; /* default value */ 3160 ha->mr.fw_hbt_cnt = QLAFX00_HEARTBEAT_INTERVAL; 3161 ha->mr.fw_reset_timer_tick = QLAFX00_RESET_INTERVAL; 3162 ha->mr.fw_critemp_timer_tick = QLAFX00_CRITEMP_INTERVAL; 3163 ha->mr.fw_hbt_en = 1; 3164 ha->mr.host_info_resend = false; 3165 ha->mr.hinfo_resend_timer_tick = QLAFX00_HINFO_RESEND_INTERVAL; 3166 } else if (IS_QLA27XX(ha)) { 3167 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3168 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3169 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3170 req_length = REQUEST_ENTRY_CNT_83XX; 3171 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3172 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3173 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3174 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3175 ha->gid_list_info_size = 8; 3176 ha->optrom_size = OPTROM_SIZE_83XX; 3177 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3178 ha->isp_ops = &qla27xx_isp_ops; 3179 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_81XX; 3180 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_81XX; 3181 ha->nvram_conf_off = ~0; 3182 ha->nvram_data_off = ~0; 3183 } else if (IS_QLA28XX(ha)) { 3184 ha->portnum = PCI_FUNC(ha->pdev->devfn); 3185 ha->max_fibre_devices = MAX_FIBRE_DEVICES_2400; 3186 ha->mbx_count = MAILBOX_REGISTER_COUNT; 3187 req_length = REQUEST_ENTRY_CNT_83XX; 3188 rsp_length = RESPONSE_ENTRY_CNT_83XX; 3189 ha->tgt.atio_q_length = ATIO_ENTRY_CNT_24XX; 3190 ha->max_loop_id = SNS_LAST_LOOP_ID_2300; 3191 ha->init_cb_size = sizeof(struct mid_init_cb_81xx); 3192 ha->gid_list_info_size = 8; 3193 ha->optrom_size = OPTROM_SIZE_28XX; 3194 ha->nvram_npiv_size = QLA_MAX_VPORTS_QLA25XX; 3195 ha->isp_ops = &qla27xx_isp_ops; 3196 ha->flash_conf_off = FARX_ACCESS_FLASH_CONF_28XX; 3197 ha->flash_data_off = FARX_ACCESS_FLASH_DATA_28XX; 3198 ha->nvram_conf_off = ~0; 3199 ha->nvram_data_off = ~0; 3200 } 3201 3202 ql_dbg_pci(ql_dbg_init, pdev, 0x001e, 3203 "mbx_count=%d, req_length=%d, " 3204 "rsp_length=%d, max_loop_id=%d, init_cb_size=%d, " 3205 "gid_list_info_size=%d, optrom_size=%d, nvram_npiv_size=%d, " 3206 "max_fibre_devices=%d.\n", 3207 ha->mbx_count, req_length, rsp_length, ha->max_loop_id, 3208 ha->init_cb_size, ha->gid_list_info_size, ha->optrom_size, 3209 ha->nvram_npiv_size, ha->max_fibre_devices); 3210 ql_dbg_pci(ql_dbg_init, pdev, 0x001f, 3211 "isp_ops=%p, flash_conf_off=%d, " 3212 "flash_data_off=%d, nvram_conf_off=%d, nvram_data_off=%d.\n", 3213 ha->isp_ops, ha->flash_conf_off, ha->flash_data_off, 3214 ha->nvram_conf_off, ha->nvram_data_off); 3215 3216 /* Configure PCI I/O space */ 3217 ret = ha->isp_ops->iospace_config(ha); 3218 if (ret) 3219 goto iospace_config_failed; 3220 3221 ql_log_pci(ql_log_info, pdev, 0x001d, 3222 "Found an ISP%04X irq %d iobase 0x%p.\n", 3223 pdev->device, pdev->irq, ha->iobase); 3224 mutex_init(&ha->vport_lock); 3225 mutex_init(&ha->mq_lock); 3226 init_completion(&ha->mbx_cmd_comp); 3227 complete(&ha->mbx_cmd_comp); 3228 init_completion(&ha->mbx_intr_comp); 3229 init_completion(&ha->dcbx_comp); 3230 init_completion(&ha->lb_portup_comp); 3231 3232 set_bit(0, (unsigned long *) ha->vp_idx_map); 3233 3234 qla2x00_config_dma_addressing(ha); 3235 ql_dbg_pci(ql_dbg_init, pdev, 0x0020, 3236 "64 Bit addressing is %s.\n", 3237 ha->flags.enable_64bit_addressing ? "enable" : 3238 "disable"); 3239 ret = qla2x00_mem_alloc(ha, req_length, rsp_length, &req, &rsp); 3240 if (ret) { 3241 ql_log_pci(ql_log_fatal, pdev, 0x0031, 3242 "Failed to allocate memory for adapter, aborting.\n"); 3243 3244 goto probe_hw_failed; 3245 } 3246 3247 req->max_q_depth = MAX_Q_DEPTH; 3248 if (ql2xmaxqdepth != 0 && ql2xmaxqdepth <= 0xffffU) 3249 req->max_q_depth = ql2xmaxqdepth; 3250 3251 3252 base_vha = qla2x00_create_host(sht, ha); 3253 if (!base_vha) { 3254 ret = -ENOMEM; 3255 goto probe_hw_failed; 3256 } 3257 3258 pci_set_drvdata(pdev, base_vha); 3259 set_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3260 3261 host = base_vha->host; 3262 base_vha->req = req; 3263 if (IS_QLA2XXX_MIDTYPE(ha)) 3264 base_vha->mgmt_svr_loop_id = 3265 qla2x00_reserve_mgmt_server_loop_id(base_vha); 3266 else 3267 base_vha->mgmt_svr_loop_id = MANAGEMENT_SERVER + 3268 base_vha->vp_idx; 3269 3270 /* Setup fcport template structure. */ 3271 ha->mr.fcport.vha = base_vha; 3272 ha->mr.fcport.port_type = FCT_UNKNOWN; 3273 ha->mr.fcport.loop_id = FC_NO_LOOP_ID; 3274 qla2x00_set_fcport_state(&ha->mr.fcport, FCS_UNCONFIGURED); 3275 ha->mr.fcport.supported_classes = FC_COS_UNSPECIFIED; 3276 ha->mr.fcport.scan_state = 1; 3277 3278 qla2xxx_reset_stats(host, QLA2XX_HW_ERROR | QLA2XX_SHT_LNK_DWN | 3279 QLA2XX_INT_ERR | QLA2XX_CMD_TIMEOUT | 3280 QLA2XX_RESET_CMD_ERR | QLA2XX_TGT_SHT_LNK_DOWN); 3281 3282 /* Set the SG table size based on ISP type */ 3283 if (!IS_FWI2_CAPABLE(ha)) { 3284 if (IS_QLA2100(ha)) 3285 host->sg_tablesize = 32; 3286 } else { 3287 if (!IS_QLA82XX(ha)) 3288 host->sg_tablesize = QLA_SG_ALL; 3289 } 3290 host->max_id = ha->max_fibre_devices; 3291 host->cmd_per_lun = 3; 3292 host->unique_id = host->host_no; 3293 3294 if (ql2xenabledif && ql2xenabledif != 2) { 3295 ql_log(ql_log_warn, base_vha, 0x302d, 3296 "Invalid value for ql2xenabledif, resetting it to default (2)\n"); 3297 ql2xenabledif = 2; 3298 } 3299 3300 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) 3301 host->max_cmd_len = 32; 3302 else 3303 host->max_cmd_len = MAX_CMDSZ; 3304 host->max_channel = MAX_BUSES - 1; 3305 /* Older HBAs support only 16-bit LUNs */ 3306 if (!IS_QLAFX00(ha) && !IS_FWI2_CAPABLE(ha) && 3307 ql2xmaxlun > 0xffff) 3308 host->max_lun = 0xffff; 3309 else 3310 host->max_lun = ql2xmaxlun; 3311 host->transportt = qla2xxx_transport_template; 3312 sht->vendor_id = (SCSI_NL_VID_TYPE_PCI | PCI_VENDOR_ID_QLOGIC); 3313 3314 ql_dbg(ql_dbg_init, base_vha, 0x0033, 3315 "max_id=%d this_id=%d " 3316 "cmd_per_len=%d unique_id=%d max_cmd_len=%d max_channel=%d " 3317 "max_lun=%llu transportt=%p, vendor_id=%llu.\n", host->max_id, 3318 host->this_id, host->cmd_per_lun, host->unique_id, 3319 host->max_cmd_len, host->max_channel, host->max_lun, 3320 host->transportt, sht->vendor_id); 3321 3322 INIT_WORK(&ha->heartbeat_work, qla_heartbeat_work_fn); 3323 3324 /* Set up the irqs */ 3325 ret = qla2x00_request_irqs(ha, rsp); 3326 if (ret) 3327 goto probe_failed; 3328 3329 /* Alloc arrays of request and response ring ptrs */ 3330 ret = qla2x00_alloc_queues(ha, req, rsp); 3331 if (ret) { 3332 ql_log(ql_log_fatal, base_vha, 0x003d, 3333 "Failed to allocate memory for queue pointers..." 3334 "aborting.\n"); 3335 ret = -ENODEV; 3336 goto probe_failed; 3337 } 3338 3339 if (ha->mqenable) { 3340 /* number of hardware queues supported by blk/scsi-mq*/ 3341 host->nr_hw_queues = ha->max_qpairs; 3342 3343 ql_dbg(ql_dbg_init, base_vha, 0x0192, 3344 "blk/scsi-mq enabled, HW queues = %d.\n", host->nr_hw_queues); 3345 } else { 3346 if (ql2xnvmeenable) { 3347 host->nr_hw_queues = ha->max_qpairs; 3348 ql_dbg(ql_dbg_init, base_vha, 0x0194, 3349 "FC-NVMe support is enabled, HW queues=%d\n", 3350 host->nr_hw_queues); 3351 } else { 3352 ql_dbg(ql_dbg_init, base_vha, 0x0193, 3353 "blk/scsi-mq disabled.\n"); 3354 } 3355 } 3356 3357 qlt_probe_one_stage1(base_vha, ha); 3358 3359 pci_save_state(pdev); 3360 3361 /* Assign back pointers */ 3362 rsp->req = req; 3363 req->rsp = rsp; 3364 3365 if (IS_QLAFX00(ha)) { 3366 ha->rsp_q_map[0] = rsp; 3367 ha->req_q_map[0] = req; 3368 set_bit(0, ha->req_qid_map); 3369 set_bit(0, ha->rsp_qid_map); 3370 } 3371 3372 /* FWI2-capable only. */ 3373 req->req_q_in = &ha->iobase->isp24.req_q_in; 3374 req->req_q_out = &ha->iobase->isp24.req_q_out; 3375 rsp->rsp_q_in = &ha->iobase->isp24.rsp_q_in; 3376 rsp->rsp_q_out = &ha->iobase->isp24.rsp_q_out; 3377 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) || 3378 IS_QLA28XX(ha)) { 3379 req->req_q_in = &ha->mqiobase->isp25mq.req_q_in; 3380 req->req_q_out = &ha->mqiobase->isp25mq.req_q_out; 3381 rsp->rsp_q_in = &ha->mqiobase->isp25mq.rsp_q_in; 3382 rsp->rsp_q_out = &ha->mqiobase->isp25mq.rsp_q_out; 3383 } 3384 3385 if (IS_QLAFX00(ha)) { 3386 req->req_q_in = &ha->iobase->ispfx00.req_q_in; 3387 req->req_q_out = &ha->iobase->ispfx00.req_q_out; 3388 rsp->rsp_q_in = &ha->iobase->ispfx00.rsp_q_in; 3389 rsp->rsp_q_out = &ha->iobase->ispfx00.rsp_q_out; 3390 } 3391 3392 if (IS_P3P_TYPE(ha)) { 3393 req->req_q_out = &ha->iobase->isp82.req_q_out[0]; 3394 rsp->rsp_q_in = &ha->iobase->isp82.rsp_q_in[0]; 3395 rsp->rsp_q_out = &ha->iobase->isp82.rsp_q_out[0]; 3396 } 3397 3398 ql_dbg(ql_dbg_multiq, base_vha, 0xc009, 3399 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3400 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3401 ql_dbg(ql_dbg_multiq, base_vha, 0xc00a, 3402 "req->req_q_in=%p req->req_q_out=%p " 3403 "rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3404 req->req_q_in, req->req_q_out, 3405 rsp->rsp_q_in, rsp->rsp_q_out); 3406 ql_dbg(ql_dbg_init, base_vha, 0x003e, 3407 "rsp_q_map=%p req_q_map=%p rsp->req=%p req->rsp=%p.\n", 3408 ha->rsp_q_map, ha->req_q_map, rsp->req, req->rsp); 3409 ql_dbg(ql_dbg_init, base_vha, 0x003f, 3410 "req->req_q_in=%p req->req_q_out=%p rsp->rsp_q_in=%p rsp->rsp_q_out=%p.\n", 3411 req->req_q_in, req->req_q_out, rsp->rsp_q_in, rsp->rsp_q_out); 3412 3413 ha->wq = alloc_workqueue("qla2xxx_wq", WQ_MEM_RECLAIM | WQ_PERCPU, 0); 3414 if (unlikely(!ha->wq)) { 3415 ret = -ENOMEM; 3416 goto probe_failed; 3417 } 3418 3419 if (ha->isp_ops->initialize_adapter(base_vha)) { 3420 ql_log(ql_log_fatal, base_vha, 0x00d6, 3421 "Failed to initialize adapter - Adapter flags %x.\n", 3422 base_vha->device_flags); 3423 3424 if (IS_QLA82XX(ha)) { 3425 qla82xx_idc_lock(ha); 3426 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 3427 QLA8XXX_DEV_FAILED); 3428 qla82xx_idc_unlock(ha); 3429 ql_log(ql_log_fatal, base_vha, 0x00d7, 3430 "HW State: FAILED.\n"); 3431 } else if (IS_QLA8044(ha)) { 3432 qla8044_idc_lock(ha); 3433 qla8044_wr_direct(base_vha, 3434 QLA8044_CRB_DEV_STATE_INDEX, 3435 QLA8XXX_DEV_FAILED); 3436 qla8044_idc_unlock(ha); 3437 ql_log(ql_log_fatal, base_vha, 0x0150, 3438 "HW State: FAILED.\n"); 3439 } 3440 3441 ret = -ENODEV; 3442 goto probe_failed; 3443 } 3444 3445 if (IS_QLAFX00(ha)) 3446 host->can_queue = QLAFX00_MAX_CANQUEUE; 3447 else 3448 host->can_queue = req->num_outstanding_cmds - 10; 3449 3450 ql_dbg(ql_dbg_init, base_vha, 0x0032, 3451 "can_queue=%d, req=%p, mgmt_svr_loop_id=%d, sg_tablesize=%d.\n", 3452 host->can_queue, base_vha->req, 3453 base_vha->mgmt_svr_loop_id, host->sg_tablesize); 3454 3455 /* Check if FW supports MQ or not for ISP25xx */ 3456 if (IS_QLA25XX(ha) && !(ha->fw_attributes & BIT_6)) 3457 ha->mqenable = 0; 3458 3459 if (ha->mqenable) { 3460 bool startit = !!(host->active_mode & MODE_INITIATOR); 3461 3462 /* Create start of day qpairs for Block MQ */ 3463 for (i = 0; i < ha->max_qpairs; i++) 3464 qla2xxx_create_qpair(base_vha, 5, 0, startit); 3465 } 3466 qla_init_iocb_limit(base_vha); 3467 3468 if (ha->flags.running_gold_fw) 3469 goto skip_dpc; 3470 3471 /* 3472 * Startup the kernel thread for this host adapter 3473 */ 3474 ha->dpc_thread = kthread_create(qla2x00_do_dpc, ha, 3475 "%s_dpc", base_vha->host_str); 3476 if (IS_ERR(ha->dpc_thread)) { 3477 ql_log(ql_log_fatal, base_vha, 0x00ed, 3478 "Failed to start DPC thread.\n"); 3479 ret = PTR_ERR(ha->dpc_thread); 3480 ha->dpc_thread = NULL; 3481 goto probe_failed; 3482 } 3483 ql_dbg(ql_dbg_init, base_vha, 0x00ee, 3484 "DPC thread started successfully.\n"); 3485 3486 /* 3487 * If we're not coming up in initiator mode, we might sit for 3488 * a while without waking up the dpc thread, which leads to a 3489 * stuck process warning. So just kick the dpc once here and 3490 * let the kthread start (and go back to sleep in qla2x00_do_dpc). 3491 */ 3492 qla2xxx_wake_dpc(base_vha); 3493 3494 INIT_WORK(&ha->board_disable, qla2x00_disable_board_on_pci_error); 3495 3496 if (IS_QLA8031(ha) || IS_MCTP_CAPABLE(ha)) { 3497 sprintf(wq_name, "qla2xxx_%lu_dpc_lp_wq", base_vha->host_no); 3498 ha->dpc_lp_wq = 3499 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name); 3500 INIT_WORK(&ha->idc_aen, qla83xx_service_idc_aen); 3501 3502 sprintf(wq_name, "qla2xxx_%lu_dpc_hp_wq", base_vha->host_no); 3503 ha->dpc_hp_wq = 3504 alloc_ordered_workqueue("%s", WQ_MEM_RECLAIM, wq_name); 3505 INIT_WORK(&ha->nic_core_reset, qla83xx_nic_core_reset_work); 3506 INIT_WORK(&ha->idc_state_handler, 3507 qla83xx_idc_state_handler_work); 3508 INIT_WORK(&ha->nic_core_unrecoverable, 3509 qla83xx_nic_core_unrecoverable_work); 3510 } 3511 3512 skip_dpc: 3513 list_add_tail(&base_vha->list, &ha->vp_list); 3514 base_vha->host->irq = ha->pdev->irq; 3515 3516 /* Initialized the timer */ 3517 qla2x00_start_timer(base_vha, WATCH_INTERVAL); 3518 ql_dbg(ql_dbg_init, base_vha, 0x00ef, 3519 "Started qla2x00_timer with " 3520 "interval=%d.\n", WATCH_INTERVAL); 3521 ql_dbg(ql_dbg_init, base_vha, 0x00f0, 3522 "Detected hba at address=%p.\n", 3523 ha); 3524 3525 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) { 3526 if (ha->fw_attributes & BIT_4) { 3527 int prot = 0, guard; 3528 3529 base_vha->flags.difdix_supported = 1; 3530 ql_dbg(ql_dbg_init, base_vha, 0x00f1, 3531 "Registering for DIF/DIX type 1 and 3 protection.\n"); 3532 if (ql2xprotmask) 3533 scsi_host_set_prot(host, ql2xprotmask); 3534 else 3535 scsi_host_set_prot(host, 3536 prot | SHOST_DIF_TYPE1_PROTECTION 3537 | SHOST_DIF_TYPE2_PROTECTION 3538 | SHOST_DIF_TYPE3_PROTECTION 3539 | SHOST_DIX_TYPE1_PROTECTION 3540 | SHOST_DIX_TYPE2_PROTECTION 3541 | SHOST_DIX_TYPE3_PROTECTION); 3542 3543 guard = SHOST_DIX_GUARD_CRC; 3544 3545 if (IS_PI_IPGUARD_CAPABLE(ha) && 3546 (ql2xenabledif > 1 || IS_PI_DIFB_DIX0_CAPABLE(ha))) 3547 guard |= SHOST_DIX_GUARD_IP; 3548 3549 if (ql2xprotguard) 3550 scsi_host_set_guard(host, ql2xprotguard); 3551 else 3552 scsi_host_set_guard(host, guard); 3553 } else 3554 base_vha->flags.difdix_supported = 0; 3555 } 3556 3557 ha->isp_ops->enable_intrs(ha); 3558 3559 if (IS_QLAFX00(ha)) { 3560 ret = qlafx00_fx_disc(base_vha, 3561 &base_vha->hw->mr.fcport, FXDISC_GET_CONFIG_INFO); 3562 host->sg_tablesize = (ha->mr.extended_io_enabled) ? 3563 QLA_SG_ALL : 128; 3564 } 3565 3566 if (IS_T10_PI_CAPABLE(base_vha->hw)) 3567 host->dma_alignment = 0x7; 3568 3569 ret = scsi_add_host(host, &pdev->dev); 3570 if (ret) 3571 goto probe_failed; 3572 3573 base_vha->flags.init_done = 1; 3574 base_vha->flags.online = 1; 3575 ha->prev_minidump_failed = 0; 3576 3577 ql_dbg(ql_dbg_init, base_vha, 0x00f2, 3578 "Init done and hba is online.\n"); 3579 3580 if (qla_ini_mode_enabled(base_vha) || 3581 qla_dual_mode_enabled(base_vha)) 3582 scsi_scan_host(host); 3583 else 3584 ql_log(ql_log_info, base_vha, 0x0122, 3585 "skipping scsi_scan_host() for non-initiator port\n"); 3586 3587 qla2x00_alloc_sysfs_attr(base_vha); 3588 3589 if (IS_QLAFX00(ha)) { 3590 ret = qlafx00_fx_disc(base_vha, 3591 &base_vha->hw->mr.fcport, FXDISC_GET_PORT_INFO); 3592 3593 /* Register system information */ 3594 ret = qlafx00_fx_disc(base_vha, 3595 &base_vha->hw->mr.fcport, FXDISC_REG_HOST_INFO); 3596 } 3597 3598 qla2x00_init_host_attr(base_vha); 3599 3600 qla2x00_dfs_setup(base_vha); 3601 3602 ql_log(ql_log_info, base_vha, 0x00fb, 3603 "QLogic %s - %s.\n", ha->model_number, ha->model_desc); 3604 ql_log(ql_log_info, base_vha, 0x00fc, 3605 "ISP%04X: %s @ %s hdma%c host#=%ld fw=%s.\n", 3606 pdev->device, ha->isp_ops->pci_info_str(base_vha, pci_info, 3607 sizeof(pci_info)), 3608 pci_name(pdev), ha->flags.enable_64bit_addressing ? '+' : '-', 3609 base_vha->host_no, 3610 ha->isp_ops->fw_version_str(base_vha, fw_str, sizeof(fw_str))); 3611 3612 qlt_add_target(ha, base_vha); 3613 3614 clear_bit(PFLG_DRIVER_PROBING, &base_vha->pci_flags); 3615 3616 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 3617 return -ENODEV; 3618 3619 return 0; 3620 3621 probe_failed: 3622 qla_enode_stop(base_vha); 3623 qla_edb_stop(base_vha); 3624 vfree(base_vha->scan.l); 3625 if (base_vha->gnl.l) { 3626 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3627 base_vha->gnl.l, base_vha->gnl.ldma); 3628 base_vha->gnl.l = NULL; 3629 } 3630 3631 if (base_vha->timer_active) 3632 qla2x00_stop_timer(base_vha); 3633 base_vha->flags.online = 0; 3634 if (ha->dpc_thread) { 3635 struct task_struct *t = ha->dpc_thread; 3636 3637 ha->dpc_thread = NULL; 3638 kthread_stop(t); 3639 } 3640 3641 qla2x00_free_device(base_vha); 3642 scsi_host_put(base_vha->host); 3643 /* 3644 * Need to NULL out local req/rsp after 3645 * qla2x00_free_device => qla2x00_free_queues frees 3646 * what these are pointing to. Or else we'll 3647 * fall over below in qla2x00_free_req/rsp_que. 3648 */ 3649 req = NULL; 3650 rsp = NULL; 3651 3652 probe_hw_failed: 3653 qla2x00_mem_free(ha); 3654 qla2x00_free_req_que(ha, req); 3655 qla2x00_free_rsp_que(ha, rsp); 3656 qla2x00_clear_drv_active(ha); 3657 3658 iospace_config_failed: 3659 if (IS_P3P_TYPE(ha)) { 3660 if (!ha->nx_pcibase) 3661 iounmap((device_reg_t *)ha->nx_pcibase); 3662 if (!ql2xdbwr) 3663 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3664 } else { 3665 if (ha->iobase) 3666 iounmap(ha->iobase); 3667 if (ha->cregbase) 3668 iounmap(ha->cregbase); 3669 } 3670 pci_release_selected_regions(ha->pdev, ha->bars); 3671 kfree(ha); 3672 3673 disable_device: 3674 pci_disable_device(pdev); 3675 return ret; 3676 } 3677 3678 static void __qla_set_remove_flag(scsi_qla_host_t *base_vha) 3679 { 3680 scsi_qla_host_t *vp; 3681 unsigned long flags; 3682 struct qla_hw_data *ha; 3683 3684 if (!base_vha) 3685 return; 3686 3687 ha = base_vha->hw; 3688 3689 spin_lock_irqsave(&ha->vport_slock, flags); 3690 list_for_each_entry(vp, &ha->vp_list, list) 3691 set_bit(PFLG_DRIVER_REMOVING, &vp->pci_flags); 3692 3693 /* 3694 * Indicate device removal to prevent future board_disable 3695 * and wait until any pending board_disable has completed. 3696 */ 3697 set_bit(PFLG_DRIVER_REMOVING, &base_vha->pci_flags); 3698 spin_unlock_irqrestore(&ha->vport_slock, flags); 3699 } 3700 3701 static void 3702 qla2x00_shutdown(struct pci_dev *pdev) 3703 { 3704 scsi_qla_host_t *vha; 3705 struct qla_hw_data *ha; 3706 3707 vha = pci_get_drvdata(pdev); 3708 ha = vha->hw; 3709 3710 ql_log(ql_log_info, vha, 0xfffa, 3711 "Adapter shutdown\n"); 3712 3713 /* 3714 * Prevent future board_disable and wait 3715 * until any pending board_disable has completed. 3716 */ 3717 __qla_set_remove_flag(vha); 3718 cancel_work_sync(&ha->board_disable); 3719 3720 if (!atomic_read(&pdev->enable_cnt)) 3721 return; 3722 3723 /* Notify ISPFX00 firmware */ 3724 if (IS_QLAFX00(ha)) 3725 qlafx00_driver_shutdown(vha, 20); 3726 3727 /* Turn-off FCE trace */ 3728 if (ha->flags.fce_enabled) { 3729 qla2x00_disable_fce_trace(vha, NULL, NULL); 3730 ha->flags.fce_enabled = 0; 3731 } 3732 3733 /* Turn-off EFT trace */ 3734 if (ha->eft) 3735 qla2x00_disable_eft_trace(vha); 3736 3737 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3738 IS_QLA28XX(ha)) { 3739 if (ha->flags.fw_started) 3740 qla2x00_abort_isp_cleanup(vha); 3741 } else { 3742 /* Stop currently executing firmware. */ 3743 qla2x00_try_to_stop_firmware(vha); 3744 } 3745 3746 /* Disable timer */ 3747 if (vha->timer_active) 3748 qla2x00_stop_timer(vha); 3749 3750 /* Turn adapter off line */ 3751 vha->flags.online = 0; 3752 3753 /* turn-off interrupts on the card */ 3754 if (ha->interrupts_on) { 3755 vha->flags.init_done = 0; 3756 ha->isp_ops->disable_intrs(ha); 3757 } 3758 3759 qla2x00_free_irqs(vha); 3760 3761 qla2x00_free_fw_dump(ha); 3762 3763 pci_disable_device(pdev); 3764 ql_log(ql_log_info, vha, 0xfffe, 3765 "Adapter shutdown successfully.\n"); 3766 } 3767 3768 /* Deletes all the virtual ports for a given ha */ 3769 static void 3770 qla2x00_delete_all_vps(struct qla_hw_data *ha, scsi_qla_host_t *base_vha) 3771 { 3772 scsi_qla_host_t *vha; 3773 unsigned long flags; 3774 3775 mutex_lock(&ha->vport_lock); 3776 while (ha->cur_vport_count) { 3777 spin_lock_irqsave(&ha->vport_slock, flags); 3778 3779 BUG_ON(base_vha->list.next == &ha->vp_list); 3780 /* This assumes first entry in ha->vp_list is always base vha */ 3781 vha = list_first_entry(&base_vha->list, scsi_qla_host_t, list); 3782 scsi_host_get(vha->host); 3783 3784 spin_unlock_irqrestore(&ha->vport_slock, flags); 3785 mutex_unlock(&ha->vport_lock); 3786 3787 qla_nvme_delete(vha); 3788 3789 fc_vport_terminate(vha->fc_vport); 3790 scsi_host_put(vha->host); 3791 3792 mutex_lock(&ha->vport_lock); 3793 } 3794 mutex_unlock(&ha->vport_lock); 3795 } 3796 3797 /* Stops all deferred work threads */ 3798 static void 3799 qla2x00_destroy_deferred_work(struct qla_hw_data *ha) 3800 { 3801 /* Cancel all work and destroy DPC workqueues */ 3802 if (ha->dpc_lp_wq) { 3803 cancel_work_sync(&ha->idc_aen); 3804 destroy_workqueue(ha->dpc_lp_wq); 3805 ha->dpc_lp_wq = NULL; 3806 } 3807 3808 if (ha->dpc_hp_wq) { 3809 cancel_work_sync(&ha->nic_core_reset); 3810 cancel_work_sync(&ha->idc_state_handler); 3811 cancel_work_sync(&ha->nic_core_unrecoverable); 3812 destroy_workqueue(ha->dpc_hp_wq); 3813 ha->dpc_hp_wq = NULL; 3814 } 3815 3816 /* Kill the kernel thread for this host */ 3817 if (ha->dpc_thread) { 3818 struct task_struct *t = ha->dpc_thread; 3819 3820 /* 3821 * qla2xxx_wake_dpc checks for ->dpc_thread 3822 * so we need to zero it out. 3823 */ 3824 ha->dpc_thread = NULL; 3825 kthread_stop(t); 3826 } 3827 } 3828 3829 static void 3830 qla2x00_unmap_iobases(struct qla_hw_data *ha) 3831 { 3832 if (IS_QLA82XX(ha)) { 3833 3834 iounmap((device_reg_t *)ha->nx_pcibase); 3835 if (!ql2xdbwr) 3836 iounmap((device_reg_t *)ha->nxdb_wr_ptr); 3837 } else { 3838 if (ha->iobase) 3839 iounmap(ha->iobase); 3840 3841 if (ha->cregbase) 3842 iounmap(ha->cregbase); 3843 3844 if (ha->mqiobase) 3845 iounmap(ha->mqiobase); 3846 3847 if (ha->msixbase) 3848 iounmap(ha->msixbase); 3849 } 3850 } 3851 3852 static void 3853 qla2x00_clear_drv_active(struct qla_hw_data *ha) 3854 { 3855 if (IS_QLA8044(ha)) { 3856 qla8044_idc_lock(ha); 3857 qla8044_clear_drv_active(ha); 3858 qla8044_idc_unlock(ha); 3859 } else if (IS_QLA82XX(ha)) { 3860 qla82xx_idc_lock(ha); 3861 qla82xx_clear_drv_active(ha); 3862 qla82xx_idc_unlock(ha); 3863 } 3864 } 3865 3866 static void 3867 qla2x00_remove_one(struct pci_dev *pdev) 3868 { 3869 scsi_qla_host_t *base_vha; 3870 struct qla_hw_data *ha; 3871 3872 base_vha = pci_get_drvdata(pdev); 3873 ha = base_vha->hw; 3874 ql_log(ql_log_info, base_vha, 0xb079, 3875 "Removing driver\n"); 3876 __qla_set_remove_flag(base_vha); 3877 cancel_work_sync(&ha->board_disable); 3878 3879 /* 3880 * If the PCI device is disabled then there was a PCI-disconnect and 3881 * qla2x00_disable_board_on_pci_error has taken care of most of the 3882 * resources. 3883 */ 3884 if (!atomic_read(&pdev->enable_cnt)) { 3885 dma_free_coherent(&ha->pdev->dev, base_vha->gnl.size, 3886 base_vha->gnl.l, base_vha->gnl.ldma); 3887 base_vha->gnl.l = NULL; 3888 scsi_host_put(base_vha->host); 3889 kfree(ha); 3890 pci_set_drvdata(pdev, NULL); 3891 return; 3892 } 3893 qla2x00_wait_for_hba_ready(base_vha); 3894 3895 /* 3896 * if UNLOADING flag is already set, then continue unload, 3897 * where it was set first. 3898 */ 3899 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 3900 return; 3901 3902 if (IS_QLA25XX(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 3903 IS_QLA28XX(ha)) { 3904 if (ha->flags.fw_started) 3905 qla2x00_abort_isp_cleanup(base_vha); 3906 } else if (!IS_QLAFX00(ha)) { 3907 if (IS_QLA8031(ha)) { 3908 ql_dbg(ql_dbg_p3p, base_vha, 0xb07e, 3909 "Clearing fcoe driver presence.\n"); 3910 if (qla83xx_clear_drv_presence(base_vha) != QLA_SUCCESS) 3911 ql_dbg(ql_dbg_p3p, base_vha, 0xb079, 3912 "Error while clearing DRV-Presence.\n"); 3913 } 3914 3915 qla2x00_try_to_stop_firmware(base_vha); 3916 } 3917 3918 qla2x00_wait_for_sess_deletion(base_vha); 3919 3920 qla_nvme_delete(base_vha); 3921 3922 dma_free_coherent(&ha->pdev->dev, 3923 base_vha->gnl.size, base_vha->gnl.l, base_vha->gnl.ldma); 3924 3925 base_vha->gnl.l = NULL; 3926 qla_enode_stop(base_vha); 3927 qla_edb_stop(base_vha); 3928 3929 vfree(base_vha->scan.l); 3930 3931 if (IS_QLAFX00(ha)) 3932 qlafx00_driver_shutdown(base_vha, 20); 3933 3934 qla2x00_delete_all_vps(ha, base_vha); 3935 3936 qla2x00_dfs_remove(base_vha); 3937 3938 qla84xx_put_chip(base_vha); 3939 3940 /* Disable timer */ 3941 if (base_vha->timer_active) 3942 qla2x00_stop_timer(base_vha); 3943 3944 base_vha->flags.online = 0; 3945 3946 /* free DMA memory */ 3947 if (ha->exlogin_buf) 3948 qla2x00_free_exlogin_buffer(ha); 3949 3950 /* free DMA memory */ 3951 if (ha->exchoffld_buf) 3952 qla2x00_free_exchoffld_buffer(ha); 3953 3954 qla2x00_destroy_deferred_work(ha); 3955 3956 qlt_remove_target(ha, base_vha); 3957 3958 qla2x00_free_sysfs_attr(base_vha, true); 3959 3960 fc_remove_host(base_vha->host); 3961 3962 scsi_remove_host(base_vha->host); 3963 3964 qla2x00_free_device(base_vha); 3965 3966 qla2x00_clear_drv_active(ha); 3967 3968 scsi_host_put(base_vha->host); 3969 3970 qla2x00_unmap_iobases(ha); 3971 3972 pci_release_selected_regions(ha->pdev, ha->bars); 3973 kfree(ha); 3974 3975 pci_disable_device(pdev); 3976 } 3977 3978 static inline void 3979 qla24xx_free_purex_list(struct purex_list *list) 3980 { 3981 struct purex_item *item, *next; 3982 ulong flags; 3983 3984 spin_lock_irqsave(&list->lock, flags); 3985 list_for_each_entry_safe(item, next, &list->head, list) { 3986 list_del(&item->list); 3987 if (item == &item->vha->default_item) 3988 continue; 3989 kfree(item); 3990 } 3991 spin_unlock_irqrestore(&list->lock, flags); 3992 } 3993 3994 static void 3995 qla2x00_free_device(scsi_qla_host_t *vha) 3996 { 3997 struct qla_hw_data *ha = vha->hw; 3998 3999 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 4000 4001 /* Disable timer */ 4002 if (vha->timer_active) 4003 qla2x00_stop_timer(vha); 4004 4005 qla25xx_delete_queues(vha); 4006 vha->flags.online = 0; 4007 4008 /* turn-off interrupts on the card */ 4009 if (ha->interrupts_on) { 4010 vha->flags.init_done = 0; 4011 ha->isp_ops->disable_intrs(ha); 4012 } 4013 4014 qla2x00_free_fcports(vha); 4015 4016 qla2x00_free_irqs(vha); 4017 4018 /* Flush the work queue and remove it */ 4019 if (ha->wq) { 4020 destroy_workqueue(ha->wq); 4021 ha->wq = NULL; 4022 } 4023 4024 4025 qla24xx_free_purex_list(&vha->purex_list); 4026 4027 qla2x00_mem_free(ha); 4028 4029 qla82xx_md_free(vha); 4030 4031 qla_edif_sadb_release_free_pool(ha); 4032 qla_edif_sadb_release(ha); 4033 4034 qla2x00_free_queues(ha); 4035 } 4036 4037 void qla2x00_free_fcports(struct scsi_qla_host *vha) 4038 { 4039 fc_port_t *fcport, *tfcport; 4040 4041 list_for_each_entry_safe(fcport, tfcport, &vha->vp_fcports, list) 4042 qla2x00_free_fcport(fcport); 4043 } 4044 4045 static inline void 4046 qla2x00_schedule_rport_del(struct scsi_qla_host *vha, fc_port_t *fcport) 4047 { 4048 int now; 4049 4050 if (!fcport->rport) 4051 return; 4052 4053 if (fcport->rport) { 4054 ql_dbg(ql_dbg_disc, fcport->vha, 0x2109, 4055 "%s %8phN. rport %p roles %x\n", 4056 __func__, fcport->port_name, fcport->rport, 4057 fcport->rport->roles); 4058 fc_remote_port_delete(fcport->rport); 4059 } 4060 qlt_do_generation_tick(vha, &now); 4061 } 4062 4063 /* 4064 * qla2x00_mark_device_lost Updates fcport state when device goes offline. 4065 * 4066 * Input: ha = adapter block pointer. fcport = port structure pointer. 4067 * 4068 * Return: None. 4069 * 4070 * Context: 4071 */ 4072 void qla2x00_mark_device_lost(scsi_qla_host_t *vha, fc_port_t *fcport, 4073 int do_login) 4074 { 4075 if (IS_QLAFX00(vha->hw)) { 4076 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4077 qla2x00_schedule_rport_del(vha, fcport); 4078 return; 4079 } 4080 4081 if (atomic_read(&fcport->state) == FCS_ONLINE && 4082 vha->vp_idx == fcport->vha->vp_idx) { 4083 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4084 qla2x00_schedule_rport_del(vha, fcport); 4085 } 4086 4087 /* 4088 * We may need to retry the login, so don't change the state of the 4089 * port but do the retries. 4090 */ 4091 if (atomic_read(&fcport->state) != FCS_DEVICE_DEAD) 4092 qla2x00_set_fcport_state(fcport, FCS_DEVICE_LOST); 4093 4094 if (!do_login) 4095 return; 4096 4097 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 4098 } 4099 4100 void 4101 qla2x00_mark_all_devices_lost(scsi_qla_host_t *vha) 4102 { 4103 fc_port_t *fcport; 4104 4105 ql_dbg(ql_dbg_disc, vha, 0x20f1, 4106 "Mark all dev lost\n"); 4107 4108 list_for_each_entry(fcport, &vha->vp_fcports, list) { 4109 if (ql2xfc2target && 4110 fcport->loop_id != FC_NO_LOOP_ID && 4111 (fcport->flags & FCF_FCP2_DEVICE) && 4112 fcport->port_type == FCT_TARGET && 4113 !qla2x00_reset_active(vha)) { 4114 ql_dbg(ql_dbg_disc, vha, 0x211a, 4115 "Delaying session delete for FCP2 flags 0x%x port_type = 0x%x port_id=%06x %phC", 4116 fcport->flags, fcport->port_type, 4117 fcport->d_id.b24, fcport->port_name); 4118 continue; 4119 } 4120 fcport->scan_state = 0; 4121 qlt_schedule_sess_for_deletion(fcport); 4122 } 4123 } 4124 4125 static void qla2x00_set_reserved_loop_ids(struct qla_hw_data *ha) 4126 { 4127 int i; 4128 4129 if (IS_FWI2_CAPABLE(ha)) 4130 return; 4131 4132 for (i = 0; i < SNS_FIRST_LOOP_ID; i++) 4133 set_bit(i, ha->loop_id_map); 4134 set_bit(MANAGEMENT_SERVER, ha->loop_id_map); 4135 set_bit(BROADCAST, ha->loop_id_map); 4136 } 4137 4138 /* 4139 * qla2x00_mem_alloc 4140 * Allocates adapter memory. 4141 * 4142 * Returns: 4143 * 0 = success. 4144 * !0 = failure. 4145 */ 4146 static int 4147 qla2x00_mem_alloc(struct qla_hw_data *ha, uint16_t req_len, uint16_t rsp_len, 4148 struct req_que **req, struct rsp_que **rsp) 4149 { 4150 char name[16]; 4151 int rc; 4152 4153 if (QLA_TGT_MODE_ENABLED() || EDIF_CAP(ha)) { 4154 ha->vp_map = kcalloc(MAX_MULTI_ID_FABRIC, sizeof(struct qla_vp_map), GFP_KERNEL); 4155 if (!ha->vp_map) 4156 goto fail; 4157 } 4158 4159 ha->init_cb = dma_alloc_coherent(&ha->pdev->dev, ha->init_cb_size, 4160 &ha->init_cb_dma, GFP_KERNEL); 4161 if (!ha->init_cb) 4162 goto fail_free_vp_map; 4163 4164 rc = btree_init32(&ha->host_map); 4165 if (rc) 4166 goto fail_free_init_cb; 4167 4168 if (qlt_mem_alloc(ha) < 0) 4169 goto fail_free_btree; 4170 4171 ha->gid_list = dma_alloc_coherent(&ha->pdev->dev, 4172 qla2x00_gid_list_size(ha), &ha->gid_list_dma, GFP_KERNEL); 4173 if (!ha->gid_list) 4174 goto fail_free_tgt_mem; 4175 4176 ha->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep); 4177 if (!ha->srb_mempool) 4178 goto fail_free_gid_list; 4179 4180 if (IS_P3P_TYPE(ha) || IS_QLA27XX(ha) || (ql2xsecenable && IS_QLA28XX(ha))) { 4181 /* Allocate cache for CT6 Ctx. */ 4182 if (!ctx_cachep) { 4183 ctx_cachep = kmem_cache_create("qla2xxx_ctx", 4184 sizeof(struct ct6_dsd), 0, 4185 SLAB_HWCACHE_ALIGN, NULL); 4186 if (!ctx_cachep) 4187 goto fail_free_srb_mempool; 4188 } 4189 ha->ctx_mempool = mempool_create_slab_pool(SRB_MIN_REQ, 4190 ctx_cachep); 4191 if (!ha->ctx_mempool) 4192 goto fail_free_srb_mempool; 4193 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0021, 4194 "ctx_cachep=%p ctx_mempool=%p.\n", 4195 ctx_cachep, ha->ctx_mempool); 4196 } 4197 4198 /* Get memory for cached NVRAM */ 4199 ha->nvram = kzalloc(MAX_NVRAM_SIZE, GFP_KERNEL); 4200 if (!ha->nvram) 4201 goto fail_free_ctx_mempool; 4202 4203 snprintf(name, sizeof(name), "%s_%d", QLA2XXX_DRIVER_NAME, 4204 ha->pdev->device); 4205 ha->s_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4206 DMA_POOL_SIZE, 8, 0); 4207 if (!ha->s_dma_pool) 4208 goto fail_free_nvram; 4209 4210 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0022, 4211 "init_cb=%p gid_list=%p, srb_mempool=%p s_dma_pool=%p.\n", 4212 ha->init_cb, ha->gid_list, ha->srb_mempool, ha->s_dma_pool); 4213 4214 if (IS_P3P_TYPE(ha) || ql2xenabledif || (IS_QLA28XX(ha) && ql2xsecenable)) { 4215 ha->dl_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4216 DSD_LIST_DMA_POOL_SIZE, 8, 0); 4217 if (!ha->dl_dma_pool) { 4218 ql_log_pci(ql_log_fatal, ha->pdev, 0x0023, 4219 "Failed to allocate memory for dl_dma_pool.\n"); 4220 goto fail_s_dma_pool; 4221 } 4222 4223 ha->fcp_cmnd_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4224 FCP_CMND_DMA_POOL_SIZE, 8, 0); 4225 if (!ha->fcp_cmnd_dma_pool) { 4226 ql_log_pci(ql_log_fatal, ha->pdev, 0x0024, 4227 "Failed to allocate memory for fcp_cmnd_dma_pool.\n"); 4228 goto fail_dl_dma_pool; 4229 } 4230 4231 if (ql2xenabledif) { 4232 u64 bufsize = DIF_BUNDLING_DMA_POOL_SIZE; 4233 struct dsd_dma *dsd, *nxt; 4234 uint i; 4235 /* Creata a DMA pool of buffers for DIF bundling */ 4236 ha->dif_bundl_pool = dma_pool_create(name, 4237 &ha->pdev->dev, DIF_BUNDLING_DMA_POOL_SIZE, 8, 0); 4238 if (!ha->dif_bundl_pool) { 4239 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4240 "%s: failed create dif_bundl_pool\n", 4241 __func__); 4242 goto fail_dif_bundl_dma_pool; 4243 } 4244 4245 INIT_LIST_HEAD(&ha->pool.good.head); 4246 INIT_LIST_HEAD(&ha->pool.unusable.head); 4247 ha->pool.good.count = 0; 4248 ha->pool.unusable.count = 0; 4249 for (i = 0; i < 128; i++) { 4250 dsd = kzalloc(sizeof(*dsd), GFP_ATOMIC); 4251 if (!dsd) { 4252 ql_dbg_pci(ql_dbg_init, ha->pdev, 4253 0xe0ee, "%s: failed alloc dsd\n", 4254 __func__); 4255 return -ENOMEM; 4256 } 4257 ha->dif_bundle_kallocs++; 4258 4259 dsd->dsd_addr = dma_pool_alloc( 4260 ha->dif_bundl_pool, GFP_ATOMIC, 4261 &dsd->dsd_list_dma); 4262 if (!dsd->dsd_addr) { 4263 ql_dbg_pci(ql_dbg_init, ha->pdev, 4264 0xe0ee, 4265 "%s: failed alloc ->dsd_addr\n", 4266 __func__); 4267 kfree(dsd); 4268 ha->dif_bundle_kallocs--; 4269 continue; 4270 } 4271 ha->dif_bundle_dma_allocs++; 4272 4273 /* 4274 * if DMA buffer crosses 4G boundary, 4275 * put it on bad list 4276 */ 4277 if (MSD(dsd->dsd_list_dma) ^ 4278 MSD(dsd->dsd_list_dma + bufsize)) { 4279 list_add_tail(&dsd->list, 4280 &ha->pool.unusable.head); 4281 ha->pool.unusable.count++; 4282 } else { 4283 list_add_tail(&dsd->list, 4284 &ha->pool.good.head); 4285 ha->pool.good.count++; 4286 } 4287 } 4288 4289 /* return the good ones back to the pool */ 4290 list_for_each_entry_safe(dsd, nxt, 4291 &ha->pool.good.head, list) { 4292 list_del(&dsd->list); 4293 dma_pool_free(ha->dif_bundl_pool, 4294 dsd->dsd_addr, dsd->dsd_list_dma); 4295 ha->dif_bundle_dma_allocs--; 4296 kfree(dsd); 4297 ha->dif_bundle_kallocs--; 4298 } 4299 4300 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0024, 4301 "%s: dif dma pool (good=%u unusable=%u)\n", 4302 __func__, ha->pool.good.count, 4303 ha->pool.unusable.count); 4304 } 4305 4306 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0025, 4307 "dl_dma_pool=%p fcp_cmnd_dma_pool=%p dif_bundl_pool=%p.\n", 4308 ha->dl_dma_pool, ha->fcp_cmnd_dma_pool, 4309 ha->dif_bundl_pool); 4310 } 4311 4312 /* Allocate memory for SNS commands */ 4313 if (IS_QLA2100(ha) || IS_QLA2200(ha)) { 4314 /* Get consistent memory allocated for SNS commands */ 4315 ha->sns_cmd = dma_alloc_coherent(&ha->pdev->dev, 4316 sizeof(struct sns_cmd_pkt), &ha->sns_cmd_dma, GFP_KERNEL); 4317 if (!ha->sns_cmd) 4318 goto fail_dma_pool; 4319 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0026, 4320 "sns_cmd: %p.\n", ha->sns_cmd); 4321 } else { 4322 /* Get consistent memory allocated for MS IOCB */ 4323 ha->ms_iocb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4324 &ha->ms_iocb_dma); 4325 if (!ha->ms_iocb) 4326 goto fail_dma_pool; 4327 /* Get consistent memory allocated for CT SNS commands */ 4328 ha->ct_sns = dma_alloc_coherent(&ha->pdev->dev, 4329 sizeof(struct ct_sns_pkt), &ha->ct_sns_dma, GFP_KERNEL); 4330 if (!ha->ct_sns) 4331 goto fail_free_ms_iocb; 4332 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0027, 4333 "ms_iocb=%p ct_sns=%p.\n", 4334 ha->ms_iocb, ha->ct_sns); 4335 } 4336 4337 /* Allocate memory for request ring */ 4338 *req = kzalloc(sizeof(struct req_que), GFP_KERNEL); 4339 if (!*req) { 4340 ql_log_pci(ql_log_fatal, ha->pdev, 0x0028, 4341 "Failed to allocate memory for req.\n"); 4342 goto fail_req; 4343 } 4344 (*req)->length = req_len; 4345 (*req)->ring = dma_alloc_coherent(&ha->pdev->dev, 4346 ((*req)->length + 1) * sizeof(request_t), 4347 &(*req)->dma, GFP_KERNEL); 4348 if (!(*req)->ring) { 4349 ql_log_pci(ql_log_fatal, ha->pdev, 0x0029, 4350 "Failed to allocate memory for req_ring.\n"); 4351 goto fail_req_ring; 4352 } 4353 /* Allocate memory for response ring */ 4354 *rsp = kzalloc(sizeof(struct rsp_que), GFP_KERNEL); 4355 if (!*rsp) { 4356 ql_log_pci(ql_log_fatal, ha->pdev, 0x002a, 4357 "Failed to allocate memory for rsp.\n"); 4358 goto fail_rsp; 4359 } 4360 (*rsp)->hw = ha; 4361 (*rsp)->length = rsp_len; 4362 (*rsp)->ring = dma_alloc_coherent(&ha->pdev->dev, 4363 ((*rsp)->length + 1) * sizeof(response_t), 4364 &(*rsp)->dma, GFP_KERNEL); 4365 if (!(*rsp)->ring) { 4366 ql_log_pci(ql_log_fatal, ha->pdev, 0x002b, 4367 "Failed to allocate memory for rsp_ring.\n"); 4368 goto fail_rsp_ring; 4369 } 4370 (*req)->rsp = *rsp; 4371 (*rsp)->req = *req; 4372 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002c, 4373 "req=%p req->length=%d req->ring=%p rsp=%p " 4374 "rsp->length=%d rsp->ring=%p.\n", 4375 *req, (*req)->length, (*req)->ring, *rsp, (*rsp)->length, 4376 (*rsp)->ring); 4377 /* Allocate memory for NVRAM data for vports */ 4378 if (ha->nvram_npiv_size) { 4379 ha->npiv_info = kcalloc(ha->nvram_npiv_size, 4380 sizeof(struct qla_npiv_entry), 4381 GFP_KERNEL); 4382 if (!ha->npiv_info) { 4383 ql_log_pci(ql_log_fatal, ha->pdev, 0x002d, 4384 "Failed to allocate memory for npiv_info.\n"); 4385 goto fail_npiv_info; 4386 } 4387 } else 4388 ha->npiv_info = NULL; 4389 4390 /* Get consistent memory allocated for EX-INIT-CB. */ 4391 if (IS_CNA_CAPABLE(ha) || IS_QLA2031(ha) || IS_QLA27XX(ha) || 4392 IS_QLA28XX(ha)) { 4393 ha->ex_init_cb = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4394 &ha->ex_init_cb_dma); 4395 if (!ha->ex_init_cb) 4396 goto fail_ex_init_cb; 4397 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002e, 4398 "ex_init_cb=%p.\n", ha->ex_init_cb); 4399 } 4400 4401 /* Get consistent memory allocated for Special Features-CB. */ 4402 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 4403 ha->sf_init_cb = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, 4404 &ha->sf_init_cb_dma); 4405 if (!ha->sf_init_cb) 4406 goto fail_sf_init_cb; 4407 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0199, 4408 "sf_init_cb=%p.\n", ha->sf_init_cb); 4409 } 4410 4411 4412 /* Get consistent memory allocated for Async Port-Database. */ 4413 if (!IS_FWI2_CAPABLE(ha)) { 4414 ha->async_pd = dma_pool_alloc(ha->s_dma_pool, GFP_KERNEL, 4415 &ha->async_pd_dma); 4416 if (!ha->async_pd) 4417 goto fail_async_pd; 4418 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x002f, 4419 "async_pd=%p.\n", ha->async_pd); 4420 } 4421 4422 INIT_LIST_HEAD(&ha->vp_list); 4423 4424 /* Allocate memory for our loop_id bitmap */ 4425 ha->loop_id_map = kcalloc(BITS_TO_LONGS(LOOPID_MAP_SIZE), 4426 sizeof(long), 4427 GFP_KERNEL); 4428 if (!ha->loop_id_map) 4429 goto fail_loop_id_map; 4430 else { 4431 qla2x00_set_reserved_loop_ids(ha); 4432 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x0123, 4433 "loop_id_map=%p.\n", ha->loop_id_map); 4434 } 4435 4436 ha->sfp_data = dma_alloc_coherent(&ha->pdev->dev, 4437 SFP_DEV_SIZE, &ha->sfp_data_dma, GFP_KERNEL); 4438 if (!ha->sfp_data) { 4439 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4440 "Unable to allocate memory for SFP read-data.\n"); 4441 goto fail_sfp_data; 4442 } 4443 4444 ha->flt = dma_alloc_coherent(&ha->pdev->dev, 4445 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, &ha->flt_dma, 4446 GFP_KERNEL); 4447 if (!ha->flt) { 4448 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4449 "Unable to allocate memory for FLT.\n"); 4450 goto fail_flt_buffer; 4451 } 4452 4453 /* allocate the purex dma pool */ 4454 ha->purex_dma_pool = dma_pool_create(name, &ha->pdev->dev, 4455 ELS_MAX_PAYLOAD, 8, 0); 4456 4457 if (!ha->purex_dma_pool) { 4458 ql_dbg_pci(ql_dbg_init, ha->pdev, 0x011b, 4459 "Unable to allocate purex_dma_pool.\n"); 4460 goto fail_flt; 4461 } 4462 4463 ha->elsrej.size = sizeof(struct fc_els_ls_rjt) + 16; 4464 ha->elsrej.c = dma_alloc_coherent(&ha->pdev->dev, 4465 ha->elsrej.size, 4466 &ha->elsrej.cdma, 4467 GFP_KERNEL); 4468 if (!ha->elsrej.c) { 4469 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4470 "Alloc failed for els reject cmd.\n"); 4471 goto fail_elsrej; 4472 } 4473 ha->elsrej.c->er_cmd = ELS_LS_RJT; 4474 ha->elsrej.c->er_reason = ELS_RJT_LOGIC; 4475 ha->elsrej.c->er_explan = ELS_EXPL_UNAB_DATA; 4476 4477 ha->lsrjt.size = sizeof(struct fcnvme_ls_rjt); 4478 ha->lsrjt.c = dma_alloc_coherent(&ha->pdev->dev, ha->lsrjt.size, 4479 &ha->lsrjt.cdma, GFP_KERNEL); 4480 if (!ha->lsrjt.c) { 4481 ql_dbg_pci(ql_dbg_init, ha->pdev, 0xffff, 4482 "Alloc failed for nvme fc reject cmd.\n"); 4483 goto fail_lsrjt; 4484 } 4485 4486 return 0; 4487 4488 fail_lsrjt: 4489 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 4490 ha->elsrej.c, ha->elsrej.cdma); 4491 fail_elsrej: 4492 dma_pool_destroy(ha->purex_dma_pool); 4493 fail_flt: 4494 dma_free_coherent(&ha->pdev->dev, sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4495 ha->flt, ha->flt_dma); 4496 4497 fail_flt_buffer: 4498 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, 4499 ha->sfp_data, ha->sfp_data_dma); 4500 fail_sfp_data: 4501 kfree(ha->loop_id_map); 4502 fail_loop_id_map: 4503 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4504 fail_async_pd: 4505 dma_pool_free(ha->s_dma_pool, ha->sf_init_cb, ha->sf_init_cb_dma); 4506 fail_sf_init_cb: 4507 dma_pool_free(ha->s_dma_pool, ha->ex_init_cb, ha->ex_init_cb_dma); 4508 fail_ex_init_cb: 4509 kfree(ha->npiv_info); 4510 fail_npiv_info: 4511 dma_free_coherent(&ha->pdev->dev, ((*rsp)->length + 1) * 4512 sizeof(response_t), (*rsp)->ring, (*rsp)->dma); 4513 (*rsp)->ring = NULL; 4514 (*rsp)->dma = 0; 4515 fail_rsp_ring: 4516 kfree(*rsp); 4517 *rsp = NULL; 4518 fail_rsp: 4519 dma_free_coherent(&ha->pdev->dev, ((*req)->length + 1) * 4520 sizeof(request_t), (*req)->ring, (*req)->dma); 4521 (*req)->ring = NULL; 4522 (*req)->dma = 0; 4523 fail_req_ring: 4524 kfree(*req); 4525 *req = NULL; 4526 fail_req: 4527 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4528 ha->ct_sns, ha->ct_sns_dma); 4529 ha->ct_sns = NULL; 4530 ha->ct_sns_dma = 0; 4531 fail_free_ms_iocb: 4532 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4533 ha->ms_iocb = NULL; 4534 ha->ms_iocb_dma = 0; 4535 4536 if (ha->sns_cmd) 4537 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4538 ha->sns_cmd, ha->sns_cmd_dma); 4539 fail_dma_pool: 4540 if (ql2xenabledif) { 4541 struct dsd_dma *dsd, *nxt; 4542 4543 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4544 list) { 4545 list_del(&dsd->list); 4546 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4547 dsd->dsd_list_dma); 4548 ha->dif_bundle_dma_allocs--; 4549 kfree(dsd); 4550 ha->dif_bundle_kallocs--; 4551 ha->pool.unusable.count--; 4552 } 4553 dma_pool_destroy(ha->dif_bundl_pool); 4554 ha->dif_bundl_pool = NULL; 4555 } 4556 4557 fail_dif_bundl_dma_pool: 4558 if (IS_QLA82XX(ha) || ql2xenabledif) { 4559 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4560 ha->fcp_cmnd_dma_pool = NULL; 4561 } 4562 fail_dl_dma_pool: 4563 if (IS_QLA82XX(ha) || ql2xenabledif) { 4564 dma_pool_destroy(ha->dl_dma_pool); 4565 ha->dl_dma_pool = NULL; 4566 } 4567 fail_s_dma_pool: 4568 dma_pool_destroy(ha->s_dma_pool); 4569 ha->s_dma_pool = NULL; 4570 fail_free_nvram: 4571 kfree(ha->nvram); 4572 ha->nvram = NULL; 4573 fail_free_ctx_mempool: 4574 mempool_destroy(ha->ctx_mempool); 4575 ha->ctx_mempool = NULL; 4576 fail_free_srb_mempool: 4577 mempool_destroy(ha->srb_mempool); 4578 ha->srb_mempool = NULL; 4579 fail_free_gid_list: 4580 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4581 ha->gid_list, 4582 ha->gid_list_dma); 4583 ha->gid_list = NULL; 4584 ha->gid_list_dma = 0; 4585 fail_free_tgt_mem: 4586 qlt_mem_free(ha); 4587 fail_free_btree: 4588 btree_destroy32(&ha->host_map); 4589 fail_free_init_cb: 4590 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, ha->init_cb, 4591 ha->init_cb_dma); 4592 ha->init_cb = NULL; 4593 ha->init_cb_dma = 0; 4594 fail_free_vp_map: 4595 kfree(ha->vp_map); 4596 ha->vp_map = NULL; 4597 fail: 4598 ql_log(ql_log_fatal, NULL, 0x0030, 4599 "Memory allocation failure.\n"); 4600 return -ENOMEM; 4601 } 4602 4603 int 4604 qla2x00_set_exlogins_buffer(scsi_qla_host_t *vha) 4605 { 4606 int rval; 4607 uint16_t size, max_cnt; 4608 uint32_t temp; 4609 struct qla_hw_data *ha = vha->hw; 4610 4611 /* Return if we don't need to alloacate any extended logins */ 4612 if (ql2xexlogins <= MAX_FIBRE_DEVICES_2400) 4613 return QLA_SUCCESS; 4614 4615 if (!IS_EXLOGIN_OFFLD_CAPABLE(ha)) 4616 return QLA_SUCCESS; 4617 4618 ql_log(ql_log_info, vha, 0xd021, "EXLOGIN count: %d.\n", ql2xexlogins); 4619 max_cnt = 0; 4620 rval = qla_get_exlogin_status(vha, &size, &max_cnt); 4621 if (rval != QLA_SUCCESS) { 4622 ql_log_pci(ql_log_fatal, ha->pdev, 0xd029, 4623 "Failed to get exlogin status.\n"); 4624 return rval; 4625 } 4626 4627 temp = (ql2xexlogins > max_cnt) ? max_cnt : ql2xexlogins; 4628 temp *= size; 4629 4630 if (temp != ha->exlogin_size) { 4631 qla2x00_free_exlogin_buffer(ha); 4632 ha->exlogin_size = temp; 4633 4634 ql_log(ql_log_info, vha, 0xd024, 4635 "EXLOGIN: max_logins=%d, portdb=0x%x, total=%d.\n", 4636 max_cnt, size, temp); 4637 4638 ql_log(ql_log_info, vha, 0xd025, 4639 "EXLOGIN: requested size=0x%x\n", ha->exlogin_size); 4640 4641 /* Get consistent memory for extended logins */ 4642 ha->exlogin_buf = dma_alloc_coherent(&ha->pdev->dev, 4643 ha->exlogin_size, &ha->exlogin_buf_dma, GFP_KERNEL); 4644 if (!ha->exlogin_buf) { 4645 ql_log_pci(ql_log_fatal, ha->pdev, 0xd02a, 4646 "Failed to allocate memory for exlogin_buf_dma.\n"); 4647 return -ENOMEM; 4648 } 4649 } 4650 4651 /* Now configure the dma buffer */ 4652 rval = qla_set_exlogin_mem_cfg(vha, ha->exlogin_buf_dma); 4653 if (rval) { 4654 ql_log(ql_log_fatal, vha, 0xd033, 4655 "Setup extended login buffer ****FAILED****.\n"); 4656 qla2x00_free_exlogin_buffer(ha); 4657 } 4658 4659 return rval; 4660 } 4661 4662 /* 4663 * qla2x00_free_exlogin_buffer 4664 * 4665 * Input: 4666 * ha = adapter block pointer 4667 */ 4668 void 4669 qla2x00_free_exlogin_buffer(struct qla_hw_data *ha) 4670 { 4671 if (ha->exlogin_buf) { 4672 dma_free_coherent(&ha->pdev->dev, ha->exlogin_size, 4673 ha->exlogin_buf, ha->exlogin_buf_dma); 4674 ha->exlogin_buf = NULL; 4675 ha->exlogin_size = 0; 4676 } 4677 } 4678 4679 static void 4680 qla2x00_number_of_exch(scsi_qla_host_t *vha, u32 *ret_cnt, u16 max_cnt) 4681 { 4682 u32 temp; 4683 struct init_cb_81xx *icb = (struct init_cb_81xx *)vha->hw->init_cb; 4684 *ret_cnt = FW_DEF_EXCHANGES_CNT; 4685 4686 if (max_cnt > vha->hw->max_exchg) 4687 max_cnt = vha->hw->max_exchg; 4688 4689 if (qla_ini_mode_enabled(vha)) { 4690 if (vha->ql2xiniexchg > max_cnt) 4691 vha->ql2xiniexchg = max_cnt; 4692 4693 if (vha->ql2xiniexchg > FW_DEF_EXCHANGES_CNT) 4694 *ret_cnt = vha->ql2xiniexchg; 4695 4696 } else if (qla_tgt_mode_enabled(vha)) { 4697 if (vha->ql2xexchoffld > max_cnt) { 4698 vha->ql2xexchoffld = max_cnt; 4699 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4700 } 4701 4702 if (vha->ql2xexchoffld > FW_DEF_EXCHANGES_CNT) 4703 *ret_cnt = vha->ql2xexchoffld; 4704 } else if (qla_dual_mode_enabled(vha)) { 4705 temp = vha->ql2xiniexchg + vha->ql2xexchoffld; 4706 if (temp > max_cnt) { 4707 vha->ql2xiniexchg -= (temp - max_cnt)/2; 4708 vha->ql2xexchoffld -= (((temp - max_cnt)/2) + 1); 4709 temp = max_cnt; 4710 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4711 } 4712 4713 if (temp > FW_DEF_EXCHANGES_CNT) 4714 *ret_cnt = temp; 4715 } 4716 } 4717 4718 int 4719 qla2x00_set_exchoffld_buffer(scsi_qla_host_t *vha) 4720 { 4721 int rval; 4722 u16 size, max_cnt; 4723 u32 actual_cnt, totsz; 4724 struct qla_hw_data *ha = vha->hw; 4725 4726 if (!ha->flags.exchoffld_enabled) 4727 return QLA_SUCCESS; 4728 4729 if (!IS_EXCHG_OFFLD_CAPABLE(ha)) 4730 return QLA_SUCCESS; 4731 4732 max_cnt = 0; 4733 rval = qla_get_exchoffld_status(vha, &size, &max_cnt); 4734 if (rval != QLA_SUCCESS) { 4735 ql_log_pci(ql_log_fatal, ha->pdev, 0xd012, 4736 "Failed to get exlogin status.\n"); 4737 return rval; 4738 } 4739 4740 qla2x00_number_of_exch(vha, &actual_cnt, max_cnt); 4741 ql_log(ql_log_info, vha, 0xd014, 4742 "Actual exchange offload count: %d.\n", actual_cnt); 4743 4744 totsz = actual_cnt * size; 4745 4746 if (totsz != ha->exchoffld_size) { 4747 qla2x00_free_exchoffld_buffer(ha); 4748 if (actual_cnt <= FW_DEF_EXCHANGES_CNT) { 4749 ha->exchoffld_size = 0; 4750 ha->flags.exchoffld_enabled = 0; 4751 return QLA_SUCCESS; 4752 } 4753 4754 ha->exchoffld_size = totsz; 4755 4756 ql_log(ql_log_info, vha, 0xd016, 4757 "Exchange offload: max_count=%d, actual count=%d entry sz=0x%x, total sz=0x%x\n", 4758 max_cnt, actual_cnt, size, totsz); 4759 4760 ql_log(ql_log_info, vha, 0xd017, 4761 "Exchange Buffers requested size = 0x%x\n", 4762 ha->exchoffld_size); 4763 4764 /* Get consistent memory for extended logins */ 4765 ha->exchoffld_buf = dma_alloc_coherent(&ha->pdev->dev, 4766 ha->exchoffld_size, &ha->exchoffld_buf_dma, GFP_KERNEL); 4767 if (!ha->exchoffld_buf) { 4768 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4769 "Failed to allocate memory for Exchange Offload.\n"); 4770 4771 if (ha->max_exchg > 4772 (FW_DEF_EXCHANGES_CNT + REDUCE_EXCHANGES_CNT)) { 4773 ha->max_exchg -= REDUCE_EXCHANGES_CNT; 4774 } else if (ha->max_exchg > 4775 (FW_DEF_EXCHANGES_CNT + 512)) { 4776 ha->max_exchg -= 512; 4777 } else { 4778 ha->flags.exchoffld_enabled = 0; 4779 ql_log_pci(ql_log_fatal, ha->pdev, 0xd013, 4780 "Disabling Exchange offload due to lack of memory\n"); 4781 } 4782 ha->exchoffld_size = 0; 4783 4784 return -ENOMEM; 4785 } 4786 } else if (!ha->exchoffld_buf || (actual_cnt <= FW_DEF_EXCHANGES_CNT)) { 4787 /* pathological case */ 4788 qla2x00_free_exchoffld_buffer(ha); 4789 ha->exchoffld_size = 0; 4790 ha->flags.exchoffld_enabled = 0; 4791 ql_log(ql_log_info, vha, 0xd016, 4792 "Exchange offload not enable: offld size=%d, actual count=%d entry sz=0x%x, total sz=0x%x.\n", 4793 ha->exchoffld_size, actual_cnt, size, totsz); 4794 return 0; 4795 } 4796 4797 /* Now configure the dma buffer */ 4798 rval = qla_set_exchoffld_mem_cfg(vha); 4799 if (rval) { 4800 ql_log(ql_log_fatal, vha, 0xd02e, 4801 "Setup exchange offload buffer ****FAILED****.\n"); 4802 qla2x00_free_exchoffld_buffer(ha); 4803 } else { 4804 /* re-adjust number of target exchange */ 4805 struct init_cb_81xx *icb = (struct init_cb_81xx *)ha->init_cb; 4806 4807 if (qla_ini_mode_enabled(vha)) 4808 icb->exchange_count = 0; 4809 else 4810 icb->exchange_count = cpu_to_le16(vha->ql2xexchoffld); 4811 } 4812 4813 return rval; 4814 } 4815 4816 /* 4817 * qla2x00_free_exchoffld_buffer 4818 * 4819 * Input: 4820 * ha = adapter block pointer 4821 */ 4822 void 4823 qla2x00_free_exchoffld_buffer(struct qla_hw_data *ha) 4824 { 4825 if (ha->exchoffld_buf) { 4826 dma_free_coherent(&ha->pdev->dev, ha->exchoffld_size, 4827 ha->exchoffld_buf, ha->exchoffld_buf_dma); 4828 ha->exchoffld_buf = NULL; 4829 ha->exchoffld_size = 0; 4830 } 4831 } 4832 4833 /* 4834 * qla2x00_free_fw_dump 4835 * Frees fw dump stuff. 4836 * 4837 * Input: 4838 * ha = adapter block pointer 4839 */ 4840 static void 4841 qla2x00_free_fw_dump(struct qla_hw_data *ha) 4842 { 4843 struct fwdt *fwdt = ha->fwdt; 4844 uint j; 4845 4846 if (ha->fce) 4847 dma_free_coherent(&ha->pdev->dev, 4848 FCE_SIZE, ha->fce, ha->fce_dma); 4849 4850 if (ha->eft) 4851 dma_free_coherent(&ha->pdev->dev, 4852 EFT_SIZE, ha->eft, ha->eft_dma); 4853 4854 vfree(ha->fw_dump); 4855 4856 ha->fce = NULL; 4857 ha->fce_dma = 0; 4858 ha->flags.fce_enabled = 0; 4859 ha->eft = NULL; 4860 ha->eft_dma = 0; 4861 ha->fw_dumped = false; 4862 ha->fw_dump_cap_flags = 0; 4863 ha->fw_dump_reading = 0; 4864 ha->fw_dump = NULL; 4865 ha->fw_dump_len = 0; 4866 4867 for (j = 0; j < 2; j++, fwdt++) { 4868 vfree(fwdt->template); 4869 fwdt->template = NULL; 4870 fwdt->length = 0; 4871 } 4872 } 4873 4874 /* 4875 * qla2x00_mem_free 4876 * Frees all adapter allocated memory. 4877 * 4878 * Input: 4879 * ha = adapter block pointer. 4880 */ 4881 static void 4882 qla2x00_mem_free(struct qla_hw_data *ha) 4883 { 4884 qla2x00_free_fw_dump(ha); 4885 4886 if (ha->mctp_dump) 4887 dma_free_coherent(&ha->pdev->dev, MCTP_DUMP_SIZE, ha->mctp_dump, 4888 ha->mctp_dump_dma); 4889 ha->mctp_dump = NULL; 4890 4891 mempool_destroy(ha->srb_mempool); 4892 ha->srb_mempool = NULL; 4893 4894 if (ha->dcbx_tlv) 4895 dma_free_coherent(&ha->pdev->dev, DCBX_TLV_DATA_SIZE, 4896 ha->dcbx_tlv, ha->dcbx_tlv_dma); 4897 ha->dcbx_tlv = NULL; 4898 4899 if (ha->xgmac_data) 4900 dma_free_coherent(&ha->pdev->dev, XGMAC_DATA_SIZE, 4901 ha->xgmac_data, ha->xgmac_data_dma); 4902 ha->xgmac_data = NULL; 4903 4904 if (ha->sns_cmd) 4905 dma_free_coherent(&ha->pdev->dev, sizeof(struct sns_cmd_pkt), 4906 ha->sns_cmd, ha->sns_cmd_dma); 4907 ha->sns_cmd = NULL; 4908 ha->sns_cmd_dma = 0; 4909 4910 if (ha->ct_sns) 4911 dma_free_coherent(&ha->pdev->dev, sizeof(struct ct_sns_pkt), 4912 ha->ct_sns, ha->ct_sns_dma); 4913 ha->ct_sns = NULL; 4914 ha->ct_sns_dma = 0; 4915 4916 if (ha->sfp_data) 4917 dma_free_coherent(&ha->pdev->dev, SFP_DEV_SIZE, ha->sfp_data, 4918 ha->sfp_data_dma); 4919 ha->sfp_data = NULL; 4920 4921 if (ha->flt) 4922 dma_free_coherent(&ha->pdev->dev, 4923 sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE, 4924 ha->flt, ha->flt_dma); 4925 ha->flt = NULL; 4926 ha->flt_dma = 0; 4927 4928 if (ha->ms_iocb) 4929 dma_pool_free(ha->s_dma_pool, ha->ms_iocb, ha->ms_iocb_dma); 4930 ha->ms_iocb = NULL; 4931 ha->ms_iocb_dma = 0; 4932 4933 if (ha->sf_init_cb) 4934 dma_pool_free(ha->s_dma_pool, 4935 ha->sf_init_cb, ha->sf_init_cb_dma); 4936 4937 if (ha->ex_init_cb) 4938 dma_pool_free(ha->s_dma_pool, 4939 ha->ex_init_cb, ha->ex_init_cb_dma); 4940 ha->ex_init_cb = NULL; 4941 ha->ex_init_cb_dma = 0; 4942 4943 if (ha->async_pd) 4944 dma_pool_free(ha->s_dma_pool, ha->async_pd, ha->async_pd_dma); 4945 ha->async_pd = NULL; 4946 ha->async_pd_dma = 0; 4947 4948 dma_pool_destroy(ha->s_dma_pool); 4949 ha->s_dma_pool = NULL; 4950 4951 if (ha->gid_list) 4952 dma_free_coherent(&ha->pdev->dev, qla2x00_gid_list_size(ha), 4953 ha->gid_list, ha->gid_list_dma); 4954 ha->gid_list = NULL; 4955 ha->gid_list_dma = 0; 4956 4957 if (ha->base_qpair && !list_empty(&ha->base_qpair->dsd_list)) { 4958 struct dsd_dma *dsd_ptr, *tdsd_ptr; 4959 4960 /* clean up allocated prev pool */ 4961 list_for_each_entry_safe(dsd_ptr, tdsd_ptr, 4962 &ha->base_qpair->dsd_list, list) { 4963 dma_pool_free(ha->dl_dma_pool, dsd_ptr->dsd_addr, 4964 dsd_ptr->dsd_list_dma); 4965 list_del(&dsd_ptr->list); 4966 kfree(dsd_ptr); 4967 } 4968 } 4969 4970 dma_pool_destroy(ha->dl_dma_pool); 4971 ha->dl_dma_pool = NULL; 4972 4973 dma_pool_destroy(ha->fcp_cmnd_dma_pool); 4974 ha->fcp_cmnd_dma_pool = NULL; 4975 4976 mempool_destroy(ha->ctx_mempool); 4977 ha->ctx_mempool = NULL; 4978 4979 if (ql2xenabledif && ha->dif_bundl_pool) { 4980 struct dsd_dma *dsd, *nxt; 4981 4982 list_for_each_entry_safe(dsd, nxt, &ha->pool.unusable.head, 4983 list) { 4984 list_del(&dsd->list); 4985 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4986 dsd->dsd_list_dma); 4987 ha->dif_bundle_dma_allocs--; 4988 kfree(dsd); 4989 ha->dif_bundle_kallocs--; 4990 ha->pool.unusable.count--; 4991 } 4992 list_for_each_entry_safe(dsd, nxt, &ha->pool.good.head, list) { 4993 list_del(&dsd->list); 4994 dma_pool_free(ha->dif_bundl_pool, dsd->dsd_addr, 4995 dsd->dsd_list_dma); 4996 ha->dif_bundle_dma_allocs--; 4997 kfree(dsd); 4998 ha->dif_bundle_kallocs--; 4999 } 5000 } 5001 5002 dma_pool_destroy(ha->dif_bundl_pool); 5003 ha->dif_bundl_pool = NULL; 5004 5005 qlt_mem_free(ha); 5006 qla_remove_hostmap(ha); 5007 5008 if (ha->init_cb) 5009 dma_free_coherent(&ha->pdev->dev, ha->init_cb_size, 5010 ha->init_cb, ha->init_cb_dma); 5011 5012 dma_pool_destroy(ha->purex_dma_pool); 5013 ha->purex_dma_pool = NULL; 5014 5015 if (ha->elsrej.c) { 5016 dma_free_coherent(&ha->pdev->dev, ha->elsrej.size, 5017 ha->elsrej.c, ha->elsrej.cdma); 5018 ha->elsrej.c = NULL; 5019 } 5020 5021 if (ha->lsrjt.c) { 5022 dma_free_coherent(&ha->pdev->dev, ha->lsrjt.size, ha->lsrjt.c, 5023 ha->lsrjt.cdma); 5024 ha->lsrjt.c = NULL; 5025 } 5026 5027 ha->init_cb = NULL; 5028 ha->init_cb_dma = 0; 5029 5030 vfree(ha->optrom_buffer); 5031 ha->optrom_buffer = NULL; 5032 kfree(ha->nvram); 5033 ha->nvram = NULL; 5034 kfree(ha->npiv_info); 5035 ha->npiv_info = NULL; 5036 kfree(ha->swl); 5037 ha->swl = NULL; 5038 kfree(ha->loop_id_map); 5039 ha->sf_init_cb = NULL; 5040 ha->sf_init_cb_dma = 0; 5041 ha->loop_id_map = NULL; 5042 5043 kfree(ha->vp_map); 5044 ha->vp_map = NULL; 5045 } 5046 5047 struct scsi_qla_host *qla2x00_create_host(const struct scsi_host_template *sht, 5048 struct qla_hw_data *ha) 5049 { 5050 struct Scsi_Host *host; 5051 struct scsi_qla_host *vha = NULL; 5052 5053 host = scsi_host_alloc(sht, sizeof(scsi_qla_host_t)); 5054 if (!host) { 5055 ql_log_pci(ql_log_fatal, ha->pdev, 0x0107, 5056 "Failed to allocate host from the scsi layer, aborting.\n"); 5057 return NULL; 5058 } 5059 5060 /* Clear our data area */ 5061 vha = shost_priv(host); 5062 memset(vha, 0, sizeof(scsi_qla_host_t)); 5063 5064 vha->host = host; 5065 vha->host_no = host->host_no; 5066 vha->hw = ha; 5067 5068 vha->qlini_mode = ql2x_ini_mode; 5069 vha->ql2xexchoffld = ql2xexchoffld; 5070 vha->ql2xiniexchg = ql2xiniexchg; 5071 5072 INIT_LIST_HEAD(&vha->vp_fcports); 5073 INIT_LIST_HEAD(&vha->work_list); 5074 INIT_LIST_HEAD(&vha->list); 5075 INIT_LIST_HEAD(&vha->qla_cmd_list); 5076 INIT_LIST_HEAD(&vha->logo_list); 5077 INIT_LIST_HEAD(&vha->plogi_ack_list); 5078 INIT_LIST_HEAD(&vha->qp_list); 5079 INIT_LIST_HEAD(&vha->gnl.fcports); 5080 INIT_WORK(&vha->iocb_work, qla2x00_iocb_work_fn); 5081 5082 INIT_LIST_HEAD(&vha->purex_list.head); 5083 spin_lock_init(&vha->purex_list.lock); 5084 5085 spin_lock_init(&vha->work_lock); 5086 spin_lock_init(&vha->cmd_list_lock); 5087 init_waitqueue_head(&vha->fcport_waitQ); 5088 init_waitqueue_head(&vha->vref_waitq); 5089 qla_enode_init(vha); 5090 qla_edb_init(vha); 5091 5092 5093 vha->gnl.size = sizeof(struct get_name_list_extended) * 5094 (ha->max_loop_id + 1); 5095 vha->gnl.l = dma_alloc_coherent(&ha->pdev->dev, 5096 vha->gnl.size, &vha->gnl.ldma, GFP_KERNEL); 5097 if (!vha->gnl.l) { 5098 ql_log(ql_log_fatal, vha, 0xd04a, 5099 "Alloc failed for name list.\n"); 5100 scsi_host_put(vha->host); 5101 return NULL; 5102 } 5103 5104 /* todo: what about ext login? */ 5105 vha->scan.size = ha->max_fibre_devices * sizeof(struct fab_scan_rp); 5106 vha->scan.l = vmalloc(vha->scan.size); 5107 if (!vha->scan.l) { 5108 ql_log(ql_log_fatal, vha, 0xd04a, 5109 "Alloc failed for scan database.\n"); 5110 dma_free_coherent(&ha->pdev->dev, vha->gnl.size, 5111 vha->gnl.l, vha->gnl.ldma); 5112 vha->gnl.l = NULL; 5113 scsi_host_put(vha->host); 5114 return NULL; 5115 } 5116 INIT_DELAYED_WORK(&vha->scan.scan_work, qla_scan_work_fn); 5117 5118 snprintf(vha->host_str, sizeof(vha->host_str), "%s_%lu", 5119 QLA2XXX_DRIVER_NAME, vha->host_no); 5120 ql_dbg(ql_dbg_init, vha, 0x0041, 5121 "Allocated the host=%p hw=%p vha=%p dev_name=%s", 5122 vha->host, vha->hw, vha, 5123 dev_name(&(ha->pdev->dev))); 5124 5125 return vha; 5126 } 5127 5128 struct qla_work_evt * 5129 qla2x00_alloc_work(struct scsi_qla_host *vha, enum qla_work_type type) 5130 { 5131 struct qla_work_evt *e; 5132 5133 if (test_bit(UNLOADING, &vha->dpc_flags)) 5134 return NULL; 5135 5136 if (qla_vha_mark_busy(vha)) 5137 return NULL; 5138 5139 e = kzalloc(sizeof(struct qla_work_evt), GFP_ATOMIC); 5140 if (!e) { 5141 QLA_VHA_MARK_NOT_BUSY(vha); 5142 return NULL; 5143 } 5144 5145 INIT_LIST_HEAD(&e->list); 5146 e->type = type; 5147 e->flags = QLA_EVT_FLAG_FREE; 5148 return e; 5149 } 5150 5151 int 5152 qla2x00_post_work(struct scsi_qla_host *vha, struct qla_work_evt *e) 5153 { 5154 unsigned long flags; 5155 bool q = false; 5156 5157 spin_lock_irqsave(&vha->work_lock, flags); 5158 list_add_tail(&e->list, &vha->work_list); 5159 5160 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 5161 q = true; 5162 5163 spin_unlock_irqrestore(&vha->work_lock, flags); 5164 5165 if (q) 5166 queue_work(vha->hw->wq, &vha->iocb_work); 5167 5168 return QLA_SUCCESS; 5169 } 5170 5171 int 5172 qla2x00_post_aen_work(struct scsi_qla_host *vha, enum fc_host_event_code code, 5173 u32 data) 5174 { 5175 struct qla_work_evt *e; 5176 5177 e = qla2x00_alloc_work(vha, QLA_EVT_AEN); 5178 if (!e) 5179 return QLA_FUNCTION_FAILED; 5180 5181 e->u.aen.code = code; 5182 e->u.aen.data = data; 5183 return qla2x00_post_work(vha, e); 5184 } 5185 5186 int 5187 qla2x00_post_idc_ack_work(struct scsi_qla_host *vha, uint16_t *mb) 5188 { 5189 struct qla_work_evt *e; 5190 5191 e = qla2x00_alloc_work(vha, QLA_EVT_IDC_ACK); 5192 if (!e) 5193 return QLA_FUNCTION_FAILED; 5194 5195 memcpy(e->u.idc_ack.mb, mb, QLA_IDC_ACK_REGS * sizeof(uint16_t)); 5196 return qla2x00_post_work(vha, e); 5197 } 5198 5199 #define qla2x00_post_async_work(name, type) \ 5200 int qla2x00_post_async_##name##_work( \ 5201 struct scsi_qla_host *vha, \ 5202 fc_port_t *fcport, uint16_t *data) \ 5203 { \ 5204 struct qla_work_evt *e; \ 5205 \ 5206 e = qla2x00_alloc_work(vha, type); \ 5207 if (!e) \ 5208 return QLA_FUNCTION_FAILED; \ 5209 \ 5210 e->u.logio.fcport = fcport; \ 5211 if (data) { \ 5212 e->u.logio.data[0] = data[0]; \ 5213 e->u.logio.data[1] = data[1]; \ 5214 } \ 5215 fcport->flags |= FCF_ASYNC_ACTIVE; \ 5216 return qla2x00_post_work(vha, e); \ 5217 } 5218 5219 qla2x00_post_async_work(login, QLA_EVT_ASYNC_LOGIN); 5220 qla2x00_post_async_work(logout, QLA_EVT_ASYNC_LOGOUT); 5221 qla2x00_post_async_work(adisc, QLA_EVT_ASYNC_ADISC); 5222 qla2x00_post_async_work(prlo, QLA_EVT_ASYNC_PRLO); 5223 qla2x00_post_async_work(prlo_done, QLA_EVT_ASYNC_PRLO_DONE); 5224 5225 int 5226 qla2x00_post_uevent_work(struct scsi_qla_host *vha, u32 code) 5227 { 5228 struct qla_work_evt *e; 5229 5230 e = qla2x00_alloc_work(vha, QLA_EVT_UEVENT); 5231 if (!e) 5232 return QLA_FUNCTION_FAILED; 5233 5234 e->u.uevent.code = code; 5235 return qla2x00_post_work(vha, e); 5236 } 5237 5238 static void 5239 qla2x00_uevent_emit(struct scsi_qla_host *vha, u32 code) 5240 { 5241 char event_string[40]; 5242 char *envp[] = { event_string, NULL }; 5243 5244 switch (code) { 5245 case QLA_UEVENT_CODE_FW_DUMP: 5246 snprintf(event_string, sizeof(event_string), "FW_DUMP=%lu", 5247 vha->host_no); 5248 break; 5249 default: 5250 /* do nothing */ 5251 break; 5252 } 5253 kobject_uevent_env(&vha->hw->pdev->dev.kobj, KOBJ_CHANGE, envp); 5254 } 5255 5256 int 5257 qlafx00_post_aenfx_work(struct scsi_qla_host *vha, uint32_t evtcode, 5258 uint32_t *data, int cnt) 5259 { 5260 struct qla_work_evt *e; 5261 5262 e = qla2x00_alloc_work(vha, QLA_EVT_AENFX); 5263 if (!e) 5264 return QLA_FUNCTION_FAILED; 5265 5266 e->u.aenfx.evtcode = evtcode; 5267 e->u.aenfx.count = cnt; 5268 memcpy(e->u.aenfx.mbx, data, sizeof(*data) * cnt); 5269 return qla2x00_post_work(vha, e); 5270 } 5271 5272 void qla24xx_sched_upd_fcport(fc_port_t *fcport) 5273 { 5274 unsigned long flags; 5275 5276 if (IS_SW_RESV_ADDR(fcport->d_id)) 5277 return; 5278 5279 spin_lock_irqsave(&fcport->vha->work_lock, flags); 5280 if (fcport->disc_state == DSC_UPD_FCPORT) { 5281 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5282 return; 5283 } 5284 fcport->jiffies_at_registration = jiffies; 5285 fcport->sec_since_registration = 0; 5286 fcport->next_disc_state = DSC_DELETED; 5287 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT); 5288 spin_unlock_irqrestore(&fcport->vha->work_lock, flags); 5289 5290 queue_work(system_dfl_wq, &fcport->reg_work); 5291 } 5292 5293 static 5294 void qla24xx_create_new_sess(struct scsi_qla_host *vha, struct qla_work_evt *e) 5295 { 5296 unsigned long flags; 5297 fc_port_t *fcport = NULL, *tfcp; 5298 struct qlt_plogi_ack_t *pla = 5299 (struct qlt_plogi_ack_t *)e->u.new_sess.pla; 5300 uint8_t free_fcport = 0; 5301 5302 ql_dbg(ql_dbg_disc, vha, 0xffff, 5303 "%s %d %8phC enter\n", 5304 __func__, __LINE__, e->u.new_sess.port_name); 5305 5306 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5307 fcport = qla2x00_find_fcport_by_wwpn(vha, e->u.new_sess.port_name, 1); 5308 if (fcport) { 5309 fcport->d_id = e->u.new_sess.id; 5310 if (pla) { 5311 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5312 memcpy(fcport->node_name, 5313 pla->iocb.u.isp24.u.plogi.node_name, 5314 WWN_SIZE); 5315 qlt_plogi_ack_link(vha, pla, fcport, QLT_PLOGI_LINK_SAME_WWN); 5316 /* we took an extra ref_count to prevent PLOGI ACK when 5317 * fcport/sess has not been created. 5318 */ 5319 pla->ref_count--; 5320 } 5321 } else { 5322 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5323 fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL); 5324 if (fcport) { 5325 fcport->d_id = e->u.new_sess.id; 5326 fcport->flags |= FCF_FABRIC_DEVICE; 5327 fcport->fw_login_state = DSC_LS_PLOGI_PEND; 5328 fcport->tgt_short_link_down_cnt = 0; 5329 5330 memcpy(fcport->port_name, e->u.new_sess.port_name, 5331 WWN_SIZE); 5332 5333 fcport->fc4_type = e->u.new_sess.fc4_type; 5334 if (NVME_PRIORITY(vha->hw, fcport)) 5335 fcport->do_prli_nvme = 1; 5336 else 5337 fcport->do_prli_nvme = 0; 5338 5339 if (e->u.new_sess.fc4_type & FS_FCP_IS_N2N) { 5340 fcport->dm_login_expire = jiffies + 5341 QLA_N2N_WAIT_TIME * HZ; 5342 fcport->fc4_type = FS_FC4TYPE_FCP; 5343 fcport->n2n_flag = 1; 5344 if (vha->flags.nvme_enabled) 5345 fcport->fc4_type |= FS_FC4TYPE_NVME; 5346 } 5347 5348 } else { 5349 ql_dbg(ql_dbg_disc, vha, 0xffff, 5350 "%s %8phC mem alloc fail.\n", 5351 __func__, e->u.new_sess.port_name); 5352 5353 if (pla) { 5354 list_del(&pla->list); 5355 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5356 } 5357 return; 5358 } 5359 5360 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5361 /* search again to make sure no one else got ahead */ 5362 tfcp = qla2x00_find_fcport_by_wwpn(vha, 5363 e->u.new_sess.port_name, 1); 5364 if (tfcp) { 5365 /* should rarily happen */ 5366 ql_dbg(ql_dbg_disc, vha, 0xffff, 5367 "%s %8phC found existing fcport b4 add. DS %d LS %d\n", 5368 __func__, tfcp->port_name, tfcp->disc_state, 5369 tfcp->fw_login_state); 5370 5371 free_fcport = 1; 5372 } else { 5373 list_add_tail(&fcport->list, &vha->vp_fcports); 5374 5375 } 5376 if (pla) { 5377 qlt_plogi_ack_link(vha, pla, fcport, 5378 QLT_PLOGI_LINK_SAME_WWN); 5379 pla->ref_count--; 5380 } 5381 } 5382 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5383 5384 if (fcport) { 5385 fcport->id_changed = 1; 5386 fcport->scan_state = QLA_FCPORT_FOUND; 5387 fcport->chip_reset = vha->hw->base_qpair->chip_reset; 5388 memcpy(fcport->node_name, e->u.new_sess.node_name, WWN_SIZE); 5389 5390 if (pla) { 5391 if (pla->iocb.u.isp24.status_subcode == ELS_PRLI) { 5392 u16 wd3_lo; 5393 5394 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5395 fcport->local = 0; 5396 fcport->loop_id = 5397 le16_to_cpu( 5398 pla->iocb.u.isp24.nport_handle); 5399 fcport->fw_login_state = DSC_LS_PRLI_PEND; 5400 wd3_lo = 5401 le16_to_cpu( 5402 pla->iocb.u.isp24.u.prli.wd3_lo); 5403 5404 if (wd3_lo & BIT_7) 5405 fcport->conf_compl_supported = 1; 5406 5407 if ((wd3_lo & BIT_4) == 0) 5408 fcport->port_type = FCT_INITIATOR; 5409 else 5410 fcport->port_type = FCT_TARGET; 5411 } 5412 qlt_plogi_ack_unref(vha, pla); 5413 } else { 5414 fc_port_t *dfcp = NULL; 5415 5416 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 5417 tfcp = qla2x00_find_fcport_by_nportid(vha, 5418 &e->u.new_sess.id, 1); 5419 if (tfcp && (tfcp != fcport)) { 5420 /* 5421 * We have a conflict fcport with same NportID. 5422 */ 5423 ql_dbg(ql_dbg_disc, vha, 0xffff, 5424 "%s %8phC found conflict b4 add. DS %d LS %d\n", 5425 __func__, tfcp->port_name, tfcp->disc_state, 5426 tfcp->fw_login_state); 5427 5428 switch (tfcp->disc_state) { 5429 case DSC_DELETED: 5430 break; 5431 case DSC_DELETE_PEND: 5432 fcport->login_pause = 1; 5433 tfcp->conflict = fcport; 5434 break; 5435 default: 5436 fcport->login_pause = 1; 5437 tfcp->conflict = fcport; 5438 dfcp = tfcp; 5439 break; 5440 } 5441 } 5442 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 5443 if (dfcp) 5444 qlt_schedule_sess_for_deletion(tfcp); 5445 5446 if (N2N_TOPO(vha->hw)) { 5447 fcport->flags &= ~FCF_FABRIC_DEVICE; 5448 fcport->keep_nport_handle = 1; 5449 if (vha->flags.nvme_enabled) { 5450 fcport->fc4_type = 5451 (FS_FC4TYPE_NVME | FS_FC4TYPE_FCP); 5452 fcport->n2n_flag = 1; 5453 } 5454 fcport->fw_login_state = 0; 5455 5456 schedule_delayed_work(&vha->scan.scan_work, 5); 5457 } else { 5458 qla24xx_fcport_handle_login(vha, fcport); 5459 } 5460 } 5461 } 5462 5463 if (free_fcport) { 5464 qla2x00_free_fcport(fcport); 5465 if (pla) { 5466 list_del(&pla->list); 5467 kmem_cache_free(qla_tgt_plogi_cachep, pla); 5468 } 5469 } 5470 } 5471 5472 static void qla_sp_retry(struct scsi_qla_host *vha, struct qla_work_evt *e) 5473 { 5474 struct srb *sp = e->u.iosb.sp; 5475 int rval; 5476 5477 rval = qla2x00_start_sp(sp); 5478 if (rval != QLA_SUCCESS) { 5479 ql_dbg(ql_dbg_disc, vha, 0x2043, 5480 "%s: %s: Re-issue IOCB failed (%d).\n", 5481 __func__, sp->name, rval); 5482 qla24xx_sp_unmap(vha, sp); 5483 } 5484 } 5485 5486 void 5487 qla2x00_do_work(struct scsi_qla_host *vha) 5488 { 5489 struct qla_work_evt *e, *tmp; 5490 unsigned long flags; 5491 LIST_HEAD(work); 5492 int rc; 5493 5494 spin_lock_irqsave(&vha->work_lock, flags); 5495 list_splice_init(&vha->work_list, &work); 5496 spin_unlock_irqrestore(&vha->work_lock, flags); 5497 5498 list_for_each_entry_safe(e, tmp, &work, list) { 5499 rc = QLA_SUCCESS; 5500 switch (e->type) { 5501 case QLA_EVT_AEN: 5502 fc_host_post_event(vha->host, fc_get_event_number(), 5503 e->u.aen.code, e->u.aen.data); 5504 break; 5505 case QLA_EVT_IDC_ACK: 5506 qla81xx_idc_ack(vha, e->u.idc_ack.mb); 5507 break; 5508 case QLA_EVT_ASYNC_LOGIN: 5509 qla2x00_async_login(vha, e->u.logio.fcport, 5510 e->u.logio.data); 5511 break; 5512 case QLA_EVT_ASYNC_LOGOUT: 5513 rc = qla2x00_async_logout(vha, e->u.logio.fcport); 5514 break; 5515 case QLA_EVT_ASYNC_ADISC: 5516 qla2x00_async_adisc(vha, e->u.logio.fcport, 5517 e->u.logio.data); 5518 break; 5519 case QLA_EVT_UEVENT: 5520 qla2x00_uevent_emit(vha, e->u.uevent.code); 5521 break; 5522 case QLA_EVT_AENFX: 5523 qlafx00_process_aen(vha, e); 5524 break; 5525 case QLA_EVT_UNMAP: 5526 qla24xx_sp_unmap(vha, e->u.iosb.sp); 5527 break; 5528 case QLA_EVT_RELOGIN: 5529 qla2x00_relogin(vha); 5530 break; 5531 case QLA_EVT_NEW_SESS: 5532 qla24xx_create_new_sess(vha, e); 5533 break; 5534 case QLA_EVT_GPDB: 5535 qla24xx_async_gpdb(vha, e->u.fcport.fcport, 5536 e->u.fcport.opt); 5537 break; 5538 case QLA_EVT_PRLI: 5539 qla24xx_async_prli(vha, e->u.fcport.fcport); 5540 break; 5541 case QLA_EVT_GPSC: 5542 qla24xx_async_gpsc(vha, e->u.fcport.fcport); 5543 break; 5544 case QLA_EVT_GNL: 5545 qla24xx_async_gnl(vha, e->u.fcport.fcport); 5546 break; 5547 case QLA_EVT_NACK: 5548 qla24xx_do_nack_work(vha, e); 5549 break; 5550 case QLA_EVT_ASYNC_PRLO: 5551 rc = qla2x00_async_prlo(vha, e->u.logio.fcport); 5552 break; 5553 case QLA_EVT_ASYNC_PRLO_DONE: 5554 qla2x00_async_prlo_done(vha, e->u.logio.fcport, 5555 e->u.logio.data); 5556 break; 5557 case QLA_EVT_SCAN_CMD: 5558 qla_fab_async_scan(vha, e->u.iosb.sp); 5559 break; 5560 case QLA_EVT_SCAN_FINISH: 5561 qla_fab_scan_finish(vha, e->u.iosb.sp); 5562 break; 5563 case QLA_EVT_GFPNID: 5564 qla24xx_async_gfpnid(vha, e->u.fcport.fcport); 5565 break; 5566 case QLA_EVT_SP_RETRY: 5567 qla_sp_retry(vha, e); 5568 break; 5569 case QLA_EVT_IIDMA: 5570 qla_do_iidma_work(vha, e->u.fcport.fcport); 5571 break; 5572 case QLA_EVT_ELS_PLOGI: 5573 qla24xx_els_dcmd2_iocb(vha, ELS_DCMD_PLOGI, 5574 e->u.fcport.fcport); 5575 break; 5576 case QLA_EVT_SA_REPLACE: 5577 rc = qla24xx_issue_sa_replace_iocb(vha, e); 5578 break; 5579 } 5580 5581 if (rc == EAGAIN) { 5582 /* put 'work' at head of 'vha->work_list' */ 5583 spin_lock_irqsave(&vha->work_lock, flags); 5584 list_splice(&work, &vha->work_list); 5585 spin_unlock_irqrestore(&vha->work_lock, flags); 5586 break; 5587 } 5588 list_del_init(&e->list); 5589 if (e->flags & QLA_EVT_FLAG_FREE) 5590 kfree(e); 5591 5592 /* For each work completed decrement vha ref count */ 5593 QLA_VHA_MARK_NOT_BUSY(vha); 5594 } 5595 } 5596 5597 int qla24xx_post_relogin_work(struct scsi_qla_host *vha) 5598 { 5599 struct qla_work_evt *e; 5600 5601 e = qla2x00_alloc_work(vha, QLA_EVT_RELOGIN); 5602 5603 if (!e) { 5604 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5605 return QLA_FUNCTION_FAILED; 5606 } 5607 5608 return qla2x00_post_work(vha, e); 5609 } 5610 5611 /* Relogins all the fcports of a vport 5612 * Context: dpc thread 5613 */ 5614 void qla2x00_relogin(struct scsi_qla_host *vha) 5615 { 5616 fc_port_t *fcport; 5617 int status, relogin_needed = 0; 5618 struct event_arg ea; 5619 5620 list_for_each_entry(fcport, &vha->vp_fcports, list) { 5621 /* 5622 * If the port is not ONLINE then try to login 5623 * to it if we haven't run out of retries. 5624 */ 5625 if (atomic_read(&fcport->state) != FCS_ONLINE && 5626 fcport->login_retry) { 5627 if (fcport->scan_state != QLA_FCPORT_FOUND || 5628 fcport->disc_state == DSC_LOGIN_AUTH_PEND || 5629 fcport->disc_state == DSC_LOGIN_COMPLETE) 5630 continue; 5631 5632 if (fcport->flags & (FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE) || 5633 fcport->disc_state == DSC_DELETE_PEND) { 5634 relogin_needed = 1; 5635 } else { 5636 if (vha->hw->current_topology != ISP_CFG_NL) { 5637 memset(&ea, 0, sizeof(ea)); 5638 ea.fcport = fcport; 5639 qla24xx_handle_relogin_event(vha, &ea); 5640 } else if (vha->hw->current_topology == 5641 ISP_CFG_NL && 5642 IS_QLA2XXX_MIDTYPE(vha->hw)) { 5643 (void)qla24xx_fcport_handle_login(vha, 5644 fcport); 5645 } else if (vha->hw->current_topology == 5646 ISP_CFG_NL) { 5647 fcport->login_retry--; 5648 status = 5649 qla2x00_local_device_login(vha, 5650 fcport); 5651 if (status == QLA_SUCCESS) { 5652 fcport->old_loop_id = 5653 fcport->loop_id; 5654 ql_dbg(ql_dbg_disc, vha, 0x2003, 5655 "Port login OK: logged in ID 0x%x.\n", 5656 fcport->loop_id); 5657 qla2x00_update_fcport 5658 (vha, fcport); 5659 } else if (status == 1) { 5660 set_bit(RELOGIN_NEEDED, 5661 &vha->dpc_flags); 5662 /* retry the login again */ 5663 ql_dbg(ql_dbg_disc, vha, 0x2007, 5664 "Retrying %d login again loop_id 0x%x.\n", 5665 fcport->login_retry, 5666 fcport->loop_id); 5667 } else { 5668 fcport->login_retry = 0; 5669 } 5670 5671 if (fcport->login_retry == 0 && 5672 status != QLA_SUCCESS) 5673 qla2x00_clear_loop_id(fcport); 5674 } 5675 } 5676 } 5677 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) 5678 break; 5679 } 5680 5681 if (relogin_needed) 5682 set_bit(RELOGIN_NEEDED, &vha->dpc_flags); 5683 5684 ql_dbg(ql_dbg_disc, vha, 0x400e, 5685 "Relogin end.\n"); 5686 } 5687 5688 /* Schedule work on any of the dpc-workqueues */ 5689 void 5690 qla83xx_schedule_work(scsi_qla_host_t *base_vha, int work_code) 5691 { 5692 struct qla_hw_data *ha = base_vha->hw; 5693 5694 switch (work_code) { 5695 case MBA_IDC_AEN: /* 0x8200 */ 5696 if (ha->dpc_lp_wq) 5697 queue_work(ha->dpc_lp_wq, &ha->idc_aen); 5698 break; 5699 5700 case QLA83XX_NIC_CORE_RESET: /* 0x1 */ 5701 if (!ha->flags.nic_core_reset_hdlr_active) { 5702 if (ha->dpc_hp_wq) 5703 queue_work(ha->dpc_hp_wq, &ha->nic_core_reset); 5704 } else 5705 ql_dbg(ql_dbg_p3p, base_vha, 0xb05e, 5706 "NIC Core reset is already active. Skip " 5707 "scheduling it again.\n"); 5708 break; 5709 case QLA83XX_IDC_STATE_HANDLER: /* 0x2 */ 5710 if (ha->dpc_hp_wq) 5711 queue_work(ha->dpc_hp_wq, &ha->idc_state_handler); 5712 break; 5713 case QLA83XX_NIC_CORE_UNRECOVERABLE: /* 0x3 */ 5714 if (ha->dpc_hp_wq) 5715 queue_work(ha->dpc_hp_wq, &ha->nic_core_unrecoverable); 5716 break; 5717 default: 5718 ql_log(ql_log_warn, base_vha, 0xb05f, 5719 "Unknown work-code=0x%x.\n", work_code); 5720 } 5721 5722 return; 5723 } 5724 5725 /* Work: Perform NIC Core Unrecoverable state handling */ 5726 void 5727 qla83xx_nic_core_unrecoverable_work(struct work_struct *work) 5728 { 5729 struct qla_hw_data *ha = 5730 container_of(work, struct qla_hw_data, nic_core_unrecoverable); 5731 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5732 uint32_t dev_state = 0; 5733 5734 qla83xx_idc_lock(base_vha, 0); 5735 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5736 qla83xx_reset_ownership(base_vha); 5737 if (ha->flags.nic_core_reset_owner) { 5738 ha->flags.nic_core_reset_owner = 0; 5739 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5740 QLA8XXX_DEV_FAILED); 5741 ql_log(ql_log_info, base_vha, 0xb060, "HW State: FAILED.\n"); 5742 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5743 } 5744 qla83xx_idc_unlock(base_vha, 0); 5745 } 5746 5747 /* Work: Execute IDC state handler */ 5748 void 5749 qla83xx_idc_state_handler_work(struct work_struct *work) 5750 { 5751 struct qla_hw_data *ha = 5752 container_of(work, struct qla_hw_data, idc_state_handler); 5753 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5754 uint32_t dev_state = 0; 5755 5756 qla83xx_idc_lock(base_vha, 0); 5757 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5758 if (dev_state == QLA8XXX_DEV_FAILED || 5759 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) 5760 qla83xx_idc_state_handler(base_vha); 5761 qla83xx_idc_unlock(base_vha, 0); 5762 } 5763 5764 static int 5765 qla83xx_check_nic_core_fw_alive(scsi_qla_host_t *base_vha) 5766 { 5767 int rval = QLA_SUCCESS; 5768 unsigned long heart_beat_wait = jiffies + (1 * HZ); 5769 uint32_t heart_beat_counter1, heart_beat_counter2; 5770 5771 do { 5772 if (time_after(jiffies, heart_beat_wait)) { 5773 ql_dbg(ql_dbg_p3p, base_vha, 0xb07c, 5774 "Nic Core f/w is not alive.\n"); 5775 rval = QLA_FUNCTION_FAILED; 5776 break; 5777 } 5778 5779 qla83xx_idc_lock(base_vha, 0); 5780 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5781 &heart_beat_counter1); 5782 qla83xx_idc_unlock(base_vha, 0); 5783 msleep(100); 5784 qla83xx_idc_lock(base_vha, 0); 5785 qla83xx_rd_reg(base_vha, QLA83XX_FW_HEARTBEAT, 5786 &heart_beat_counter2); 5787 qla83xx_idc_unlock(base_vha, 0); 5788 } while (heart_beat_counter1 == heart_beat_counter2); 5789 5790 return rval; 5791 } 5792 5793 /* Work: Perform NIC Core Reset handling */ 5794 void 5795 qla83xx_nic_core_reset_work(struct work_struct *work) 5796 { 5797 struct qla_hw_data *ha = 5798 container_of(work, struct qla_hw_data, nic_core_reset); 5799 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5800 uint32_t dev_state = 0; 5801 5802 if (IS_QLA2031(ha)) { 5803 if (qla2xxx_mctp_dump(base_vha) != QLA_SUCCESS) 5804 ql_log(ql_log_warn, base_vha, 0xb081, 5805 "Failed to dump mctp\n"); 5806 return; 5807 } 5808 5809 if (!ha->flags.nic_core_reset_hdlr_active) { 5810 if (qla83xx_check_nic_core_fw_alive(base_vha) == QLA_SUCCESS) { 5811 qla83xx_idc_lock(base_vha, 0); 5812 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, 5813 &dev_state); 5814 qla83xx_idc_unlock(base_vha, 0); 5815 if (dev_state != QLA8XXX_DEV_NEED_RESET) { 5816 ql_dbg(ql_dbg_p3p, base_vha, 0xb07a, 5817 "Nic Core f/w is alive.\n"); 5818 return; 5819 } 5820 } 5821 5822 ha->flags.nic_core_reset_hdlr_active = 1; 5823 if (qla83xx_nic_core_reset(base_vha)) { 5824 /* NIC Core reset failed. */ 5825 ql_dbg(ql_dbg_p3p, base_vha, 0xb061, 5826 "NIC Core reset failed.\n"); 5827 } 5828 ha->flags.nic_core_reset_hdlr_active = 0; 5829 } 5830 } 5831 5832 /* Work: Handle 8200 IDC aens */ 5833 void 5834 qla83xx_service_idc_aen(struct work_struct *work) 5835 { 5836 struct qla_hw_data *ha = 5837 container_of(work, struct qla_hw_data, idc_aen); 5838 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 5839 uint32_t dev_state, idc_control; 5840 5841 qla83xx_idc_lock(base_vha, 0); 5842 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 5843 qla83xx_rd_reg(base_vha, QLA83XX_IDC_CONTROL, &idc_control); 5844 qla83xx_idc_unlock(base_vha, 0); 5845 if (dev_state == QLA8XXX_DEV_NEED_RESET) { 5846 if (idc_control & QLA83XX_IDC_GRACEFUL_RESET) { 5847 ql_dbg(ql_dbg_p3p, base_vha, 0xb062, 5848 "Application requested NIC Core Reset.\n"); 5849 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5850 } else if (qla83xx_check_nic_core_fw_alive(base_vha) == 5851 QLA_SUCCESS) { 5852 ql_dbg(ql_dbg_p3p, base_vha, 0xb07b, 5853 "Other protocol driver requested NIC Core Reset.\n"); 5854 qla83xx_schedule_work(base_vha, QLA83XX_NIC_CORE_RESET); 5855 } 5856 } else if (dev_state == QLA8XXX_DEV_FAILED || 5857 dev_state == QLA8XXX_DEV_NEED_QUIESCENT) { 5858 qla83xx_schedule_work(base_vha, QLA83XX_IDC_STATE_HANDLER); 5859 } 5860 } 5861 5862 /* 5863 * Control the frequency of IDC lock retries 5864 */ 5865 #define QLA83XX_WAIT_LOGIC_MS 100 5866 5867 static int 5868 qla83xx_force_lock_recovery(scsi_qla_host_t *base_vha) 5869 { 5870 int rval; 5871 uint32_t data; 5872 uint32_t idc_lck_rcvry_stage_mask = 0x3; 5873 uint32_t idc_lck_rcvry_owner_mask = 0x3c; 5874 struct qla_hw_data *ha = base_vha->hw; 5875 5876 ql_dbg(ql_dbg_p3p, base_vha, 0xb086, 5877 "Trying force recovery of the IDC lock.\n"); 5878 5879 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, &data); 5880 if (rval) 5881 return rval; 5882 5883 if ((data & idc_lck_rcvry_stage_mask) > 0) { 5884 return QLA_SUCCESS; 5885 } else { 5886 data = (IDC_LOCK_RECOVERY_STAGE1) | (ha->portnum << 2); 5887 rval = qla83xx_wr_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5888 data); 5889 if (rval) 5890 return rval; 5891 5892 msleep(200); 5893 5894 rval = qla83xx_rd_reg(base_vha, QLA83XX_IDC_LOCK_RECOVERY, 5895 &data); 5896 if (rval) 5897 return rval; 5898 5899 if (((data & idc_lck_rcvry_owner_mask) >> 2) == ha->portnum) { 5900 data &= (IDC_LOCK_RECOVERY_STAGE2 | 5901 ~(idc_lck_rcvry_stage_mask)); 5902 rval = qla83xx_wr_reg(base_vha, 5903 QLA83XX_IDC_LOCK_RECOVERY, data); 5904 if (rval) 5905 return rval; 5906 5907 /* Forcefully perform IDC UnLock */ 5908 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, 5909 &data); 5910 if (rval) 5911 return rval; 5912 /* Clear lock-id by setting 0xff */ 5913 rval = qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5914 0xff); 5915 if (rval) 5916 return rval; 5917 /* Clear lock-recovery by setting 0x0 */ 5918 rval = qla83xx_wr_reg(base_vha, 5919 QLA83XX_IDC_LOCK_RECOVERY, 0x0); 5920 if (rval) 5921 return rval; 5922 } else 5923 return QLA_SUCCESS; 5924 } 5925 5926 return rval; 5927 } 5928 5929 static int 5930 qla83xx_idc_lock_recovery(scsi_qla_host_t *base_vha) 5931 { 5932 int rval = QLA_SUCCESS; 5933 uint32_t o_drv_lockid, n_drv_lockid; 5934 unsigned long lock_recovery_timeout; 5935 5936 lock_recovery_timeout = jiffies + QLA83XX_MAX_LOCK_RECOVERY_WAIT; 5937 retry_lockid: 5938 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &o_drv_lockid); 5939 if (rval) 5940 goto exit; 5941 5942 /* MAX wait time before forcing IDC Lock recovery = 2 secs */ 5943 if (time_after_eq(jiffies, lock_recovery_timeout)) { 5944 if (qla83xx_force_lock_recovery(base_vha) == QLA_SUCCESS) 5945 return QLA_SUCCESS; 5946 else 5947 return QLA_FUNCTION_FAILED; 5948 } 5949 5950 rval = qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &n_drv_lockid); 5951 if (rval) 5952 goto exit; 5953 5954 if (o_drv_lockid == n_drv_lockid) { 5955 msleep(QLA83XX_WAIT_LOGIC_MS); 5956 goto retry_lockid; 5957 } else 5958 return QLA_SUCCESS; 5959 5960 exit: 5961 return rval; 5962 } 5963 5964 /* 5965 * Context: task, can sleep 5966 */ 5967 void 5968 qla83xx_idc_lock(scsi_qla_host_t *base_vha, uint16_t requester_id) 5969 { 5970 uint32_t data; 5971 uint32_t lock_owner; 5972 struct qla_hw_data *ha = base_vha->hw; 5973 5974 might_sleep(); 5975 5976 /* IDC-lock implementation using driver-lock/lock-id remote registers */ 5977 retry_lock: 5978 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCK, &data) 5979 == QLA_SUCCESS) { 5980 if (data) { 5981 /* Setting lock-id to our function-number */ 5982 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5983 ha->portnum); 5984 } else { 5985 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, 5986 &lock_owner); 5987 ql_dbg(ql_dbg_p3p, base_vha, 0xb063, 5988 "Failed to acquire IDC lock, acquired by %d, " 5989 "retrying...\n", lock_owner); 5990 5991 /* Retry/Perform IDC-Lock recovery */ 5992 if (qla83xx_idc_lock_recovery(base_vha) 5993 == QLA_SUCCESS) { 5994 msleep(QLA83XX_WAIT_LOGIC_MS); 5995 goto retry_lock; 5996 } else 5997 ql_log(ql_log_warn, base_vha, 0xb075, 5998 "IDC Lock recovery FAILED.\n"); 5999 } 6000 6001 } 6002 6003 return; 6004 } 6005 6006 static bool 6007 qla25xx_rdp_rsp_reduce_size(struct scsi_qla_host *vha, 6008 struct purex_entry_24xx *purex) 6009 { 6010 char fwstr[16]; 6011 u32 sid = purex->s_id[2] << 16 | purex->s_id[1] << 8 | purex->s_id[0]; 6012 struct port_database_24xx *pdb; 6013 6014 /* Domain Controller is always logged-out. */ 6015 /* if RDP request is not from Domain Controller: */ 6016 if (sid != 0xfffc01) 6017 return false; 6018 6019 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: s_id=%#x\n", __func__, sid); 6020 6021 pdb = kzalloc(sizeof(*pdb), GFP_KERNEL); 6022 if (!pdb) { 6023 ql_dbg(ql_dbg_init, vha, 0x0181, 6024 "%s: Failed allocate pdb\n", __func__); 6025 } else if (qla24xx_get_port_database(vha, 6026 le16_to_cpu(purex->nport_handle), pdb)) { 6027 ql_dbg(ql_dbg_init, vha, 0x0181, 6028 "%s: Failed get pdb sid=%x\n", __func__, sid); 6029 } else if (pdb->current_login_state != PDS_PLOGI_COMPLETE && 6030 pdb->current_login_state != PDS_PRLI_COMPLETE) { 6031 ql_dbg(ql_dbg_init, vha, 0x0181, 6032 "%s: Port not logged in sid=%#x\n", __func__, sid); 6033 } else { 6034 /* RDP request is from logged in port */ 6035 kfree(pdb); 6036 return false; 6037 } 6038 kfree(pdb); 6039 6040 vha->hw->isp_ops->fw_version_str(vha, fwstr, sizeof(fwstr)); 6041 fwstr[strcspn(fwstr, " ")] = 0; 6042 /* if FW version allows RDP response length upto 2048 bytes: */ 6043 if (strcmp(fwstr, "8.09.00") > 0 || strcmp(fwstr, "8.05.65") == 0) 6044 return false; 6045 6046 ql_dbg(ql_dbg_init, vha, 0x0181, "%s: fw=%s\n", __func__, fwstr); 6047 6048 /* RDP response length is to be reduced to maximum 256 bytes */ 6049 return true; 6050 } 6051 6052 /* 6053 * Function Name: qla24xx_process_purex_iocb 6054 * 6055 * Description: 6056 * Prepare a RDP response and send to Fabric switch 6057 * 6058 * PARAMETERS: 6059 * vha: SCSI qla host 6060 * purex: RDP request received by HBA 6061 */ 6062 void qla24xx_process_purex_rdp(struct scsi_qla_host *vha, 6063 struct purex_item *item) 6064 { 6065 struct qla_hw_data *ha = vha->hw; 6066 struct purex_entry_24xx *purex = 6067 (struct purex_entry_24xx *)&item->iocb; 6068 dma_addr_t rsp_els_dma; 6069 dma_addr_t rsp_payload_dma; 6070 dma_addr_t stat_dma; 6071 dma_addr_t sfp_dma; 6072 struct els_entry_24xx *rsp_els = NULL; 6073 struct rdp_rsp_payload *rsp_payload = NULL; 6074 struct link_statistics *stat = NULL; 6075 uint8_t *sfp = NULL; 6076 uint16_t sfp_flags = 0; 6077 uint rsp_payload_length = sizeof(*rsp_payload); 6078 int rval; 6079 6080 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0180, 6081 "%s: Enter\n", __func__); 6082 6083 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0181, 6084 "-------- ELS REQ -------\n"); 6085 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0182, 6086 purex, sizeof(*purex)); 6087 6088 if (qla25xx_rdp_rsp_reduce_size(vha, purex)) { 6089 rsp_payload_length = 6090 offsetof(typeof(*rsp_payload), optical_elmt_desc); 6091 ql_dbg(ql_dbg_init, vha, 0x0181, 6092 "Reducing RSP payload length to %u bytes...\n", 6093 rsp_payload_length); 6094 } 6095 6096 rsp_els = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6097 &rsp_els_dma, GFP_KERNEL); 6098 if (!rsp_els) { 6099 ql_log(ql_log_warn, vha, 0x0183, 6100 "Failed allocate dma buffer ELS RSP.\n"); 6101 goto dealloc; 6102 } 6103 6104 rsp_payload = dma_alloc_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6105 &rsp_payload_dma, GFP_KERNEL); 6106 if (!rsp_payload) { 6107 ql_log(ql_log_warn, vha, 0x0184, 6108 "Failed allocate dma buffer ELS RSP payload.\n"); 6109 goto dealloc; 6110 } 6111 6112 sfp = dma_alloc_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6113 &sfp_dma, GFP_KERNEL); 6114 6115 stat = dma_alloc_coherent(&ha->pdev->dev, sizeof(*stat), 6116 &stat_dma, GFP_KERNEL); 6117 6118 /* Prepare Response IOCB */ 6119 rsp_els->entry_type = ELS_IOCB_TYPE; 6120 rsp_els->entry_count = 1; 6121 rsp_els->sys_define = 0; 6122 rsp_els->entry_status = 0; 6123 rsp_els->handle = 0; 6124 rsp_els->nport_handle = purex->nport_handle; 6125 rsp_els->tx_dsd_count = cpu_to_le16(1); 6126 rsp_els->vp_index = purex->vp_idx; 6127 rsp_els->sof_type = EST_SOFI3; 6128 rsp_els->rx_xchg_address = purex->rx_xchg_addr; 6129 rsp_els->rx_dsd_count = 0; 6130 rsp_els->opcode = purex->els_frame_payload[0]; 6131 6132 rsp_els->d_id[0] = purex->s_id[0]; 6133 rsp_els->d_id[1] = purex->s_id[1]; 6134 rsp_els->d_id[2] = purex->s_id[2]; 6135 6136 rsp_els->control_flags = cpu_to_le16(EPD_ELS_ACC); 6137 rsp_els->rx_byte_count = 0; 6138 rsp_els->tx_byte_count = cpu_to_le32(rsp_payload_length); 6139 6140 put_unaligned_le64(rsp_payload_dma, &rsp_els->tx_address); 6141 rsp_els->tx_len = rsp_els->tx_byte_count; 6142 6143 rsp_els->rx_address = 0; 6144 rsp_els->rx_len = 0; 6145 6146 /* Prepare Response Payload */ 6147 rsp_payload->hdr.cmd = cpu_to_be32(0x2 << 24); /* LS_ACC */ 6148 rsp_payload->hdr.len = cpu_to_be32(le32_to_cpu(rsp_els->tx_byte_count) - 6149 sizeof(rsp_payload->hdr)); 6150 6151 /* Link service Request Info Descriptor */ 6152 rsp_payload->ls_req_info_desc.desc_tag = cpu_to_be32(0x1); 6153 rsp_payload->ls_req_info_desc.desc_len = 6154 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc)); 6155 rsp_payload->ls_req_info_desc.req_payload_word_0 = 6156 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6157 6158 /* Link service Request Info Descriptor 2 */ 6159 rsp_payload->ls_req_info_desc2.desc_tag = cpu_to_be32(0x1); 6160 rsp_payload->ls_req_info_desc2.desc_len = 6161 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_req_info_desc2)); 6162 rsp_payload->ls_req_info_desc2.req_payload_word_0 = 6163 cpu_to_be32p((uint32_t *)purex->els_frame_payload); 6164 6165 6166 rsp_payload->sfp_diag_desc.desc_tag = cpu_to_be32(0x10000); 6167 rsp_payload->sfp_diag_desc.desc_len = 6168 cpu_to_be32(RDP_DESC_LEN(rsp_payload->sfp_diag_desc)); 6169 6170 if (sfp) { 6171 /* SFP Flags */ 6172 memset(sfp, 0, SFP_RTDI_LEN); 6173 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x7, 2, 0); 6174 if (!rval) { 6175 /* SFP Flags bits 3-0: Port Tx Laser Type */ 6176 if (sfp[0] & BIT_2 || sfp[1] & (BIT_6|BIT_5)) 6177 sfp_flags |= BIT_0; /* short wave */ 6178 else if (sfp[0] & BIT_1) 6179 sfp_flags |= BIT_1; /* long wave 1310nm */ 6180 else if (sfp[1] & BIT_4) 6181 sfp_flags |= BIT_1|BIT_0; /* long wave 1550nm */ 6182 } 6183 6184 /* SFP Type */ 6185 memset(sfp, 0, SFP_RTDI_LEN); 6186 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 0x0, 1, 0); 6187 if (!rval) { 6188 sfp_flags |= BIT_4; /* optical */ 6189 if (sfp[0] == 0x3) 6190 sfp_flags |= BIT_6; /* sfp+ */ 6191 } 6192 6193 rsp_payload->sfp_diag_desc.sfp_flags = cpu_to_be16(sfp_flags); 6194 6195 /* SFP Diagnostics */ 6196 memset(sfp, 0, SFP_RTDI_LEN); 6197 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0x60, 10, 0); 6198 if (!rval) { 6199 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6200 rsp_payload->sfp_diag_desc.temperature = trx[0]; 6201 rsp_payload->sfp_diag_desc.vcc = trx[1]; 6202 rsp_payload->sfp_diag_desc.tx_bias = trx[2]; 6203 rsp_payload->sfp_diag_desc.tx_power = trx[3]; 6204 rsp_payload->sfp_diag_desc.rx_power = trx[4]; 6205 } 6206 } 6207 6208 /* Port Speed Descriptor */ 6209 rsp_payload->port_speed_desc.desc_tag = cpu_to_be32(0x10001); 6210 rsp_payload->port_speed_desc.desc_len = 6211 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_speed_desc)); 6212 rsp_payload->port_speed_desc.speed_capab = cpu_to_be16( 6213 qla25xx_fdmi_port_speed_capability(ha)); 6214 rsp_payload->port_speed_desc.operating_speed = cpu_to_be16( 6215 qla25xx_fdmi_port_speed_currently(ha)); 6216 6217 /* Link Error Status Descriptor */ 6218 rsp_payload->ls_err_desc.desc_tag = cpu_to_be32(0x10002); 6219 rsp_payload->ls_err_desc.desc_len = 6220 cpu_to_be32(RDP_DESC_LEN(rsp_payload->ls_err_desc)); 6221 6222 if (stat) { 6223 rval = qla24xx_get_isp_stats(vha, stat, stat_dma, 0); 6224 if (!rval) { 6225 rsp_payload->ls_err_desc.link_fail_cnt = 6226 cpu_to_be32(le32_to_cpu(stat->link_fail_cnt)); 6227 rsp_payload->ls_err_desc.loss_sync_cnt = 6228 cpu_to_be32(le32_to_cpu(stat->loss_sync_cnt)); 6229 rsp_payload->ls_err_desc.loss_sig_cnt = 6230 cpu_to_be32(le32_to_cpu(stat->loss_sig_cnt)); 6231 rsp_payload->ls_err_desc.prim_seq_err_cnt = 6232 cpu_to_be32(le32_to_cpu(stat->prim_seq_err_cnt)); 6233 rsp_payload->ls_err_desc.inval_xmit_word_cnt = 6234 cpu_to_be32(le32_to_cpu(stat->inval_xmit_word_cnt)); 6235 rsp_payload->ls_err_desc.inval_crc_cnt = 6236 cpu_to_be32(le32_to_cpu(stat->inval_crc_cnt)); 6237 rsp_payload->ls_err_desc.pn_port_phy_type |= BIT_6; 6238 } 6239 } 6240 6241 /* Portname Descriptor */ 6242 rsp_payload->port_name_diag_desc.desc_tag = cpu_to_be32(0x10003); 6243 rsp_payload->port_name_diag_desc.desc_len = 6244 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_diag_desc)); 6245 memcpy(rsp_payload->port_name_diag_desc.WWNN, 6246 vha->node_name, 6247 sizeof(rsp_payload->port_name_diag_desc.WWNN)); 6248 memcpy(rsp_payload->port_name_diag_desc.WWPN, 6249 vha->port_name, 6250 sizeof(rsp_payload->port_name_diag_desc.WWPN)); 6251 6252 /* F-Port Portname Descriptor */ 6253 rsp_payload->port_name_direct_desc.desc_tag = cpu_to_be32(0x10003); 6254 rsp_payload->port_name_direct_desc.desc_len = 6255 cpu_to_be32(RDP_DESC_LEN(rsp_payload->port_name_direct_desc)); 6256 memcpy(rsp_payload->port_name_direct_desc.WWNN, 6257 vha->fabric_node_name, 6258 sizeof(rsp_payload->port_name_direct_desc.WWNN)); 6259 memcpy(rsp_payload->port_name_direct_desc.WWPN, 6260 vha->fabric_port_name, 6261 sizeof(rsp_payload->port_name_direct_desc.WWPN)); 6262 6263 /* Bufer Credit Descriptor */ 6264 rsp_payload->buffer_credit_desc.desc_tag = cpu_to_be32(0x10006); 6265 rsp_payload->buffer_credit_desc.desc_len = 6266 cpu_to_be32(RDP_DESC_LEN(rsp_payload->buffer_credit_desc)); 6267 rsp_payload->buffer_credit_desc.fcport_b2b = 0; 6268 rsp_payload->buffer_credit_desc.attached_fcport_b2b = cpu_to_be32(0); 6269 rsp_payload->buffer_credit_desc.fcport_rtt = cpu_to_be32(0); 6270 6271 if (ha->flags.plogi_template_valid) { 6272 uint32_t tmp = 6273 be16_to_cpu(ha->plogi_els_payld.fl_csp.sp_bb_cred); 6274 rsp_payload->buffer_credit_desc.fcport_b2b = cpu_to_be32(tmp); 6275 } 6276 6277 if (rsp_payload_length < sizeof(*rsp_payload)) 6278 goto send; 6279 6280 /* Optical Element Descriptor, Temperature */ 6281 rsp_payload->optical_elmt_desc[0].desc_tag = cpu_to_be32(0x10007); 6282 rsp_payload->optical_elmt_desc[0].desc_len = 6283 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6284 /* Optical Element Descriptor, Voltage */ 6285 rsp_payload->optical_elmt_desc[1].desc_tag = cpu_to_be32(0x10007); 6286 rsp_payload->optical_elmt_desc[1].desc_len = 6287 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6288 /* Optical Element Descriptor, Tx Bias Current */ 6289 rsp_payload->optical_elmt_desc[2].desc_tag = cpu_to_be32(0x10007); 6290 rsp_payload->optical_elmt_desc[2].desc_len = 6291 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6292 /* Optical Element Descriptor, Tx Power */ 6293 rsp_payload->optical_elmt_desc[3].desc_tag = cpu_to_be32(0x10007); 6294 rsp_payload->optical_elmt_desc[3].desc_len = 6295 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6296 /* Optical Element Descriptor, Rx Power */ 6297 rsp_payload->optical_elmt_desc[4].desc_tag = cpu_to_be32(0x10007); 6298 rsp_payload->optical_elmt_desc[4].desc_len = 6299 cpu_to_be32(RDP_DESC_LEN(*rsp_payload->optical_elmt_desc)); 6300 6301 if (sfp) { 6302 memset(sfp, 0, SFP_RTDI_LEN); 6303 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 0, 64, 0); 6304 if (!rval) { 6305 __be16 *trx = (__force __be16 *)sfp; /* already be16 */ 6306 6307 /* Optical Element Descriptor, Temperature */ 6308 rsp_payload->optical_elmt_desc[0].high_alarm = trx[0]; 6309 rsp_payload->optical_elmt_desc[0].low_alarm = trx[1]; 6310 rsp_payload->optical_elmt_desc[0].high_warn = trx[2]; 6311 rsp_payload->optical_elmt_desc[0].low_warn = trx[3]; 6312 rsp_payload->optical_elmt_desc[0].element_flags = 6313 cpu_to_be32(1 << 28); 6314 6315 /* Optical Element Descriptor, Voltage */ 6316 rsp_payload->optical_elmt_desc[1].high_alarm = trx[4]; 6317 rsp_payload->optical_elmt_desc[1].low_alarm = trx[5]; 6318 rsp_payload->optical_elmt_desc[1].high_warn = trx[6]; 6319 rsp_payload->optical_elmt_desc[1].low_warn = trx[7]; 6320 rsp_payload->optical_elmt_desc[1].element_flags = 6321 cpu_to_be32(2 << 28); 6322 6323 /* Optical Element Descriptor, Tx Bias Current */ 6324 rsp_payload->optical_elmt_desc[2].high_alarm = trx[8]; 6325 rsp_payload->optical_elmt_desc[2].low_alarm = trx[9]; 6326 rsp_payload->optical_elmt_desc[2].high_warn = trx[10]; 6327 rsp_payload->optical_elmt_desc[2].low_warn = trx[11]; 6328 rsp_payload->optical_elmt_desc[2].element_flags = 6329 cpu_to_be32(3 << 28); 6330 6331 /* Optical Element Descriptor, Tx Power */ 6332 rsp_payload->optical_elmt_desc[3].high_alarm = trx[12]; 6333 rsp_payload->optical_elmt_desc[3].low_alarm = trx[13]; 6334 rsp_payload->optical_elmt_desc[3].high_warn = trx[14]; 6335 rsp_payload->optical_elmt_desc[3].low_warn = trx[15]; 6336 rsp_payload->optical_elmt_desc[3].element_flags = 6337 cpu_to_be32(4 << 28); 6338 6339 /* Optical Element Descriptor, Rx Power */ 6340 rsp_payload->optical_elmt_desc[4].high_alarm = trx[16]; 6341 rsp_payload->optical_elmt_desc[4].low_alarm = trx[17]; 6342 rsp_payload->optical_elmt_desc[4].high_warn = trx[18]; 6343 rsp_payload->optical_elmt_desc[4].low_warn = trx[19]; 6344 rsp_payload->optical_elmt_desc[4].element_flags = 6345 cpu_to_be32(5 << 28); 6346 } 6347 6348 memset(sfp, 0, SFP_RTDI_LEN); 6349 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa2, 112, 64, 0); 6350 if (!rval) { 6351 /* Temperature high/low alarm/warning */ 6352 rsp_payload->optical_elmt_desc[0].element_flags |= 6353 cpu_to_be32( 6354 (sfp[0] >> 7 & 1) << 3 | 6355 (sfp[0] >> 6 & 1) << 2 | 6356 (sfp[4] >> 7 & 1) << 1 | 6357 (sfp[4] >> 6 & 1) << 0); 6358 6359 /* Voltage high/low alarm/warning */ 6360 rsp_payload->optical_elmt_desc[1].element_flags |= 6361 cpu_to_be32( 6362 (sfp[0] >> 5 & 1) << 3 | 6363 (sfp[0] >> 4 & 1) << 2 | 6364 (sfp[4] >> 5 & 1) << 1 | 6365 (sfp[4] >> 4 & 1) << 0); 6366 6367 /* Tx Bias Current high/low alarm/warning */ 6368 rsp_payload->optical_elmt_desc[2].element_flags |= 6369 cpu_to_be32( 6370 (sfp[0] >> 3 & 1) << 3 | 6371 (sfp[0] >> 2 & 1) << 2 | 6372 (sfp[4] >> 3 & 1) << 1 | 6373 (sfp[4] >> 2 & 1) << 0); 6374 6375 /* Tx Power high/low alarm/warning */ 6376 rsp_payload->optical_elmt_desc[3].element_flags |= 6377 cpu_to_be32( 6378 (sfp[0] >> 1 & 1) << 3 | 6379 (sfp[0] >> 0 & 1) << 2 | 6380 (sfp[4] >> 1 & 1) << 1 | 6381 (sfp[4] >> 0 & 1) << 0); 6382 6383 /* Rx Power high/low alarm/warning */ 6384 rsp_payload->optical_elmt_desc[4].element_flags |= 6385 cpu_to_be32( 6386 (sfp[1] >> 7 & 1) << 3 | 6387 (sfp[1] >> 6 & 1) << 2 | 6388 (sfp[5] >> 7 & 1) << 1 | 6389 (sfp[5] >> 6 & 1) << 0); 6390 } 6391 } 6392 6393 /* Optical Product Data Descriptor */ 6394 rsp_payload->optical_prod_desc.desc_tag = cpu_to_be32(0x10008); 6395 rsp_payload->optical_prod_desc.desc_len = 6396 cpu_to_be32(RDP_DESC_LEN(rsp_payload->optical_prod_desc)); 6397 6398 if (sfp) { 6399 memset(sfp, 0, SFP_RTDI_LEN); 6400 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 20, 64, 0); 6401 if (!rval) { 6402 memcpy(rsp_payload->optical_prod_desc.vendor_name, 6403 sfp + 0, 6404 sizeof(rsp_payload->optical_prod_desc.vendor_name)); 6405 memcpy(rsp_payload->optical_prod_desc.part_number, 6406 sfp + 20, 6407 sizeof(rsp_payload->optical_prod_desc.part_number)); 6408 memcpy(rsp_payload->optical_prod_desc.revision, 6409 sfp + 36, 6410 sizeof(rsp_payload->optical_prod_desc.revision)); 6411 memcpy(rsp_payload->optical_prod_desc.serial_number, 6412 sfp + 48, 6413 sizeof(rsp_payload->optical_prod_desc.serial_number)); 6414 } 6415 6416 memset(sfp, 0, SFP_RTDI_LEN); 6417 rval = qla2x00_read_sfp(vha, sfp_dma, sfp, 0xa0, 84, 8, 0); 6418 if (!rval) { 6419 memcpy(rsp_payload->optical_prod_desc.date, 6420 sfp + 0, 6421 sizeof(rsp_payload->optical_prod_desc.date)); 6422 } 6423 } 6424 6425 send: 6426 ql_dbg(ql_dbg_init, vha, 0x0183, 6427 "Sending ELS Response to RDP Request...\n"); 6428 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0184, 6429 "-------- ELS RSP -------\n"); 6430 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0185, 6431 rsp_els, sizeof(*rsp_els)); 6432 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x0186, 6433 "-------- ELS RSP PAYLOAD -------\n"); 6434 ql_dump_buffer(ql_dbg_init + ql_dbg_verbose, vha, 0x0187, 6435 rsp_payload, rsp_payload_length); 6436 6437 rval = qla2x00_issue_iocb(vha, rsp_els, rsp_els_dma, 0); 6438 6439 if (rval) { 6440 ql_log(ql_log_warn, vha, 0x0188, 6441 "%s: iocb failed to execute -> %x\n", __func__, rval); 6442 } else if (rsp_els->comp_status) { 6443 ql_log(ql_log_warn, vha, 0x0189, 6444 "%s: iocb failed to complete -> completion=%#x subcode=(%#x,%#x)\n", 6445 __func__, rsp_els->comp_status, 6446 rsp_els->error_subcode_1, rsp_els->error_subcode_2); 6447 } else { 6448 ql_dbg(ql_dbg_init, vha, 0x018a, "%s: done.\n", __func__); 6449 } 6450 6451 dealloc: 6452 if (stat) 6453 dma_free_coherent(&ha->pdev->dev, sizeof(*stat), 6454 stat, stat_dma); 6455 if (sfp) 6456 dma_free_coherent(&ha->pdev->dev, SFP_RTDI_LEN, 6457 sfp, sfp_dma); 6458 if (rsp_payload) 6459 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_payload), 6460 rsp_payload, rsp_payload_dma); 6461 if (rsp_els) 6462 dma_free_coherent(&ha->pdev->dev, sizeof(*rsp_els), 6463 rsp_els, rsp_els_dma); 6464 } 6465 6466 void 6467 qla24xx_free_purex_item(struct purex_item *item) 6468 { 6469 if (item == &item->vha->default_item) 6470 memset(&item->vha->default_item, 0, sizeof(struct purex_item)); 6471 else 6472 kfree(item); 6473 } 6474 6475 void qla24xx_process_purex_list(struct purex_list *list) 6476 { 6477 struct list_head head = LIST_HEAD_INIT(head); 6478 struct purex_item *item, *next; 6479 ulong flags; 6480 6481 spin_lock_irqsave(&list->lock, flags); 6482 list_splice_init(&list->head, &head); 6483 spin_unlock_irqrestore(&list->lock, flags); 6484 6485 list_for_each_entry_safe(item, next, &head, list) { 6486 list_del(&item->list); 6487 item->process_item(item->vha, item); 6488 qla24xx_free_purex_item(item); 6489 } 6490 } 6491 6492 /* 6493 * Context: task, can sleep 6494 */ 6495 void 6496 qla83xx_idc_unlock(scsi_qla_host_t *base_vha, uint16_t requester_id) 6497 { 6498 #if 0 6499 uint16_t options = (requester_id << 15) | BIT_7; 6500 #endif 6501 uint16_t retry; 6502 uint32_t data; 6503 struct qla_hw_data *ha = base_vha->hw; 6504 6505 might_sleep(); 6506 6507 /* IDC-unlock implementation using driver-unlock/lock-id 6508 * remote registers 6509 */ 6510 retry = 0; 6511 retry_unlock: 6512 if (qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_LOCKID, &data) 6513 == QLA_SUCCESS) { 6514 if (data == ha->portnum) { 6515 qla83xx_rd_reg(base_vha, QLA83XX_DRIVER_UNLOCK, &data); 6516 /* Clearing lock-id by setting 0xff */ 6517 qla83xx_wr_reg(base_vha, QLA83XX_DRIVER_LOCKID, 0xff); 6518 } else if (retry < 10) { 6519 /* SV: XXX: IDC unlock retrying needed here? */ 6520 6521 /* Retry for IDC-unlock */ 6522 msleep(QLA83XX_WAIT_LOGIC_MS); 6523 retry++; 6524 ql_dbg(ql_dbg_p3p, base_vha, 0xb064, 6525 "Failed to release IDC lock, retrying=%d\n", retry); 6526 goto retry_unlock; 6527 } 6528 } else if (retry < 10) { 6529 /* Retry for IDC-unlock */ 6530 msleep(QLA83XX_WAIT_LOGIC_MS); 6531 retry++; 6532 ql_dbg(ql_dbg_p3p, base_vha, 0xb065, 6533 "Failed to read drv-lockid, retrying=%d\n", retry); 6534 goto retry_unlock; 6535 } 6536 6537 return; 6538 6539 #if 0 6540 /* XXX: IDC-unlock implementation using access-control mbx */ 6541 retry = 0; 6542 retry_unlock2: 6543 if (qla83xx_access_control(base_vha, options, 0, 0, NULL)) { 6544 if (retry < 10) { 6545 /* Retry for IDC-unlock */ 6546 msleep(QLA83XX_WAIT_LOGIC_MS); 6547 retry++; 6548 ql_dbg(ql_dbg_p3p, base_vha, 0xb066, 6549 "Failed to release IDC lock, retrying=%d\n", retry); 6550 goto retry_unlock2; 6551 } 6552 } 6553 6554 return; 6555 #endif 6556 } 6557 6558 int 6559 __qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6560 { 6561 int rval = QLA_SUCCESS; 6562 struct qla_hw_data *ha = vha->hw; 6563 uint32_t drv_presence; 6564 6565 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6566 if (rval == QLA_SUCCESS) { 6567 drv_presence |= (1 << ha->portnum); 6568 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6569 drv_presence); 6570 } 6571 6572 return rval; 6573 } 6574 6575 int 6576 qla83xx_set_drv_presence(scsi_qla_host_t *vha) 6577 { 6578 int rval = QLA_SUCCESS; 6579 6580 qla83xx_idc_lock(vha, 0); 6581 rval = __qla83xx_set_drv_presence(vha); 6582 qla83xx_idc_unlock(vha, 0); 6583 6584 return rval; 6585 } 6586 6587 int 6588 __qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6589 { 6590 int rval = QLA_SUCCESS; 6591 struct qla_hw_data *ha = vha->hw; 6592 uint32_t drv_presence; 6593 6594 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6595 if (rval == QLA_SUCCESS) { 6596 drv_presence &= ~(1 << ha->portnum); 6597 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6598 drv_presence); 6599 } 6600 6601 return rval; 6602 } 6603 6604 int 6605 qla83xx_clear_drv_presence(scsi_qla_host_t *vha) 6606 { 6607 int rval = QLA_SUCCESS; 6608 6609 qla83xx_idc_lock(vha, 0); 6610 rval = __qla83xx_clear_drv_presence(vha); 6611 qla83xx_idc_unlock(vha, 0); 6612 6613 return rval; 6614 } 6615 6616 static void 6617 qla83xx_need_reset_handler(scsi_qla_host_t *vha) 6618 { 6619 struct qla_hw_data *ha = vha->hw; 6620 uint32_t drv_ack, drv_presence; 6621 unsigned long ack_timeout; 6622 6623 /* Wait for IDC ACK from all functions (DRV-ACK == DRV-PRESENCE) */ 6624 ack_timeout = jiffies + (ha->fcoe_reset_timeout * HZ); 6625 while (1) { 6626 qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack); 6627 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence); 6628 if ((drv_ack & drv_presence) == drv_presence) 6629 break; 6630 6631 if (time_after_eq(jiffies, ack_timeout)) { 6632 ql_log(ql_log_warn, vha, 0xb067, 6633 "RESET ACK TIMEOUT! drv_presence=0x%x " 6634 "drv_ack=0x%x\n", drv_presence, drv_ack); 6635 /* 6636 * The function(s) which did not ack in time are forced 6637 * to withdraw any further participation in the IDC 6638 * reset. 6639 */ 6640 if (drv_ack != drv_presence) 6641 qla83xx_wr_reg(vha, QLA83XX_IDC_DRV_PRESENCE, 6642 drv_ack); 6643 break; 6644 } 6645 6646 qla83xx_idc_unlock(vha, 0); 6647 msleep(1000); 6648 qla83xx_idc_lock(vha, 0); 6649 } 6650 6651 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_COLD); 6652 ql_log(ql_log_info, vha, 0xb068, "HW State: COLD/RE-INIT.\n"); 6653 } 6654 6655 static int 6656 qla83xx_device_bootstrap(scsi_qla_host_t *vha) 6657 { 6658 int rval = QLA_SUCCESS; 6659 uint32_t idc_control; 6660 6661 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_INITIALIZING); 6662 ql_log(ql_log_info, vha, 0xb069, "HW State: INITIALIZING.\n"); 6663 6664 /* Clearing IDC-Control Graceful-Reset Bit before resetting f/w */ 6665 __qla83xx_get_idc_control(vha, &idc_control); 6666 idc_control &= ~QLA83XX_IDC_GRACEFUL_RESET; 6667 __qla83xx_set_idc_control(vha, 0); 6668 6669 qla83xx_idc_unlock(vha, 0); 6670 rval = qla83xx_restart_nic_firmware(vha); 6671 qla83xx_idc_lock(vha, 0); 6672 6673 if (rval != QLA_SUCCESS) { 6674 ql_log(ql_log_fatal, vha, 0xb06a, 6675 "Failed to restart NIC f/w.\n"); 6676 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_FAILED); 6677 ql_log(ql_log_info, vha, 0xb06b, "HW State: FAILED.\n"); 6678 } else { 6679 ql_dbg(ql_dbg_p3p, vha, 0xb06c, 6680 "Success in restarting nic f/w.\n"); 6681 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE, QLA8XXX_DEV_READY); 6682 ql_log(ql_log_info, vha, 0xb06d, "HW State: READY.\n"); 6683 } 6684 6685 return rval; 6686 } 6687 6688 /* Assumes idc_lock always held on entry */ 6689 int 6690 qla83xx_idc_state_handler(scsi_qla_host_t *base_vha) 6691 { 6692 struct qla_hw_data *ha = base_vha->hw; 6693 int rval = QLA_SUCCESS; 6694 unsigned long dev_init_timeout; 6695 uint32_t dev_state; 6696 6697 /* Wait for MAX-INIT-TIMEOUT for the device to go ready */ 6698 dev_init_timeout = jiffies + (ha->fcoe_dev_init_timeout * HZ); 6699 6700 while (1) { 6701 6702 if (time_after_eq(jiffies, dev_init_timeout)) { 6703 ql_log(ql_log_warn, base_vha, 0xb06e, 6704 "Initialization TIMEOUT!\n"); 6705 /* Init timeout. Disable further NIC Core 6706 * communication. 6707 */ 6708 qla83xx_wr_reg(base_vha, QLA83XX_IDC_DEV_STATE, 6709 QLA8XXX_DEV_FAILED); 6710 ql_log(ql_log_info, base_vha, 0xb06f, 6711 "HW State: FAILED.\n"); 6712 } 6713 6714 qla83xx_rd_reg(base_vha, QLA83XX_IDC_DEV_STATE, &dev_state); 6715 switch (dev_state) { 6716 case QLA8XXX_DEV_READY: 6717 if (ha->flags.nic_core_reset_owner) 6718 qla83xx_idc_audit(base_vha, 6719 IDC_AUDIT_COMPLETION); 6720 ha->flags.nic_core_reset_owner = 0; 6721 ql_dbg(ql_dbg_p3p, base_vha, 0xb070, 6722 "Reset_owner reset by 0x%x.\n", 6723 ha->portnum); 6724 goto exit; 6725 case QLA8XXX_DEV_COLD: 6726 if (ha->flags.nic_core_reset_owner) 6727 rval = qla83xx_device_bootstrap(base_vha); 6728 else { 6729 /* Wait for AEN to change device-state */ 6730 qla83xx_idc_unlock(base_vha, 0); 6731 msleep(1000); 6732 qla83xx_idc_lock(base_vha, 0); 6733 } 6734 break; 6735 case QLA8XXX_DEV_INITIALIZING: 6736 /* Wait for AEN to change device-state */ 6737 qla83xx_idc_unlock(base_vha, 0); 6738 msleep(1000); 6739 qla83xx_idc_lock(base_vha, 0); 6740 break; 6741 case QLA8XXX_DEV_NEED_RESET: 6742 if (!ql2xdontresethba && ha->flags.nic_core_reset_owner) 6743 qla83xx_need_reset_handler(base_vha); 6744 else { 6745 /* Wait for AEN to change device-state */ 6746 qla83xx_idc_unlock(base_vha, 0); 6747 msleep(1000); 6748 qla83xx_idc_lock(base_vha, 0); 6749 } 6750 /* reset timeout value after need reset handler */ 6751 dev_init_timeout = jiffies + 6752 (ha->fcoe_dev_init_timeout * HZ); 6753 break; 6754 case QLA8XXX_DEV_NEED_QUIESCENT: 6755 /* XXX: DEBUG for now */ 6756 qla83xx_idc_unlock(base_vha, 0); 6757 msleep(1000); 6758 qla83xx_idc_lock(base_vha, 0); 6759 break; 6760 case QLA8XXX_DEV_QUIESCENT: 6761 /* XXX: DEBUG for now */ 6762 if (ha->flags.quiesce_owner) 6763 goto exit; 6764 6765 qla83xx_idc_unlock(base_vha, 0); 6766 msleep(1000); 6767 qla83xx_idc_lock(base_vha, 0); 6768 dev_init_timeout = jiffies + 6769 (ha->fcoe_dev_init_timeout * HZ); 6770 break; 6771 case QLA8XXX_DEV_FAILED: 6772 if (ha->flags.nic_core_reset_owner) 6773 qla83xx_idc_audit(base_vha, 6774 IDC_AUDIT_COMPLETION); 6775 ha->flags.nic_core_reset_owner = 0; 6776 __qla83xx_clear_drv_presence(base_vha); 6777 qla83xx_idc_unlock(base_vha, 0); 6778 qla8xxx_dev_failed_handler(base_vha); 6779 rval = QLA_FUNCTION_FAILED; 6780 qla83xx_idc_lock(base_vha, 0); 6781 goto exit; 6782 case QLA8XXX_BAD_VALUE: 6783 qla83xx_idc_unlock(base_vha, 0); 6784 msleep(1000); 6785 qla83xx_idc_lock(base_vha, 0); 6786 break; 6787 default: 6788 ql_log(ql_log_warn, base_vha, 0xb071, 6789 "Unknown Device State: %x.\n", dev_state); 6790 qla83xx_idc_unlock(base_vha, 0); 6791 qla8xxx_dev_failed_handler(base_vha); 6792 rval = QLA_FUNCTION_FAILED; 6793 qla83xx_idc_lock(base_vha, 0); 6794 goto exit; 6795 } 6796 } 6797 6798 exit: 6799 return rval; 6800 } 6801 6802 void 6803 qla2x00_disable_board_on_pci_error(struct work_struct *work) 6804 { 6805 struct qla_hw_data *ha = container_of(work, struct qla_hw_data, 6806 board_disable); 6807 struct pci_dev *pdev = ha->pdev; 6808 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 6809 6810 ql_log(ql_log_warn, base_vha, 0x015b, 6811 "Disabling adapter.\n"); 6812 6813 if (!atomic_read(&pdev->enable_cnt)) { 6814 ql_log(ql_log_info, base_vha, 0xfffc, 6815 "PCI device disabled, no action req for PCI error=%lx\n", 6816 base_vha->pci_flags); 6817 return; 6818 } 6819 6820 /* 6821 * if UNLOADING flag is already set, then continue unload, 6822 * where it was set first. 6823 */ 6824 if (test_and_set_bit(UNLOADING, &base_vha->dpc_flags)) 6825 return; 6826 6827 qla2x00_wait_for_sess_deletion(base_vha); 6828 6829 qla2x00_delete_all_vps(ha, base_vha); 6830 6831 qla2x00_abort_all_cmds(base_vha, DID_NO_CONNECT << 16); 6832 6833 qla2x00_dfs_remove(base_vha); 6834 6835 qla84xx_put_chip(base_vha); 6836 6837 if (base_vha->timer_active) 6838 qla2x00_stop_timer(base_vha); 6839 6840 base_vha->flags.online = 0; 6841 6842 qla2x00_destroy_deferred_work(ha); 6843 6844 /* 6845 * Do not try to stop beacon blink as it will issue a mailbox 6846 * command. 6847 */ 6848 qla2x00_free_sysfs_attr(base_vha, false); 6849 6850 fc_remove_host(base_vha->host); 6851 6852 scsi_remove_host(base_vha->host); 6853 6854 base_vha->flags.init_done = 0; 6855 qla25xx_delete_queues(base_vha); 6856 qla2x00_free_fcports(base_vha); 6857 qla2x00_free_irqs(base_vha); 6858 qla2x00_mem_free(ha); 6859 qla82xx_md_free(base_vha); 6860 qla2x00_free_queues(ha); 6861 6862 qla2x00_unmap_iobases(ha); 6863 6864 pci_release_selected_regions(ha->pdev, ha->bars); 6865 pci_disable_device(pdev); 6866 6867 /* 6868 * Let qla2x00_remove_one cleanup qla_hw_data on device removal. 6869 */ 6870 } 6871 6872 /************************************************************************** 6873 * qla2x00_do_dpc 6874 * This kernel thread is a task that is schedule by the interrupt handler 6875 * to perform the background processing for interrupts. 6876 * 6877 * Notes: 6878 * This task always run in the context of a kernel thread. It 6879 * is kick-off by the driver's detect code and starts up 6880 * up one per adapter. It immediately goes to sleep and waits for 6881 * some fibre event. When either the interrupt handler or 6882 * the timer routine detects a event it will one of the task 6883 * bits then wake us up. 6884 **************************************************************************/ 6885 static int 6886 qla2x00_do_dpc(void *data) 6887 { 6888 scsi_qla_host_t *base_vha; 6889 struct qla_hw_data *ha; 6890 uint32_t online; 6891 struct qla_qpair *qpair; 6892 6893 ha = (struct qla_hw_data *)data; 6894 base_vha = pci_get_drvdata(ha->pdev); 6895 6896 set_user_nice(current, MIN_NICE); 6897 6898 set_current_state(TASK_INTERRUPTIBLE); 6899 while (1) { 6900 ql_dbg(ql_dbg_dpc, base_vha, 0x4000, 6901 "DPC handler sleeping.\n"); 6902 6903 schedule(); 6904 6905 if (kthread_should_stop()) 6906 break; 6907 6908 if (test_and_clear_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags)) 6909 qla_pci_set_eeh_busy(base_vha); 6910 6911 if (!base_vha->flags.init_done || ha->flags.mbox_busy) 6912 goto end_loop; 6913 6914 if (ha->flags.eeh_busy) { 6915 ql_dbg(ql_dbg_dpc, base_vha, 0x4003, 6916 "eeh_busy=%d.\n", ha->flags.eeh_busy); 6917 goto end_loop; 6918 } 6919 6920 if (test_bit(UNLOADING, &base_vha->dpc_flags)) 6921 /* don't do any work. Wait to be terminated by kthread_stop */ 6922 goto end_loop; 6923 6924 ha->dpc_active = 1; 6925 6926 ql_dbg(ql_dbg_dpc + ql_dbg_verbose, base_vha, 0x4001, 6927 "DPC handler waking up, dpc_flags=0x%lx.\n", 6928 base_vha->dpc_flags); 6929 6930 if (IS_P3P_TYPE(ha)) { 6931 if (IS_QLA8044(ha)) { 6932 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6933 &base_vha->dpc_flags)) { 6934 qla8044_idc_lock(ha); 6935 qla8044_wr_direct(base_vha, 6936 QLA8044_CRB_DEV_STATE_INDEX, 6937 QLA8XXX_DEV_FAILED); 6938 qla8044_idc_unlock(ha); 6939 ql_log(ql_log_info, base_vha, 0x4004, 6940 "HW State: FAILED.\n"); 6941 qla8044_device_state_handler(base_vha); 6942 continue; 6943 } 6944 6945 } else { 6946 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6947 &base_vha->dpc_flags)) { 6948 qla82xx_idc_lock(ha); 6949 qla82xx_wr_32(ha, QLA82XX_CRB_DEV_STATE, 6950 QLA8XXX_DEV_FAILED); 6951 qla82xx_idc_unlock(ha); 6952 ql_log(ql_log_info, base_vha, 0x0151, 6953 "HW State: FAILED.\n"); 6954 qla82xx_device_state_handler(base_vha); 6955 continue; 6956 } 6957 } 6958 6959 if (test_and_clear_bit(FCOE_CTX_RESET_NEEDED, 6960 &base_vha->dpc_flags)) { 6961 6962 ql_dbg(ql_dbg_dpc, base_vha, 0x4005, 6963 "FCoE context reset scheduled.\n"); 6964 if (!(test_and_set_bit(ABORT_ISP_ACTIVE, 6965 &base_vha->dpc_flags))) { 6966 if (qla82xx_fcoe_ctx_reset(base_vha)) { 6967 /* FCoE-ctx reset failed. 6968 * Escalate to chip-reset 6969 */ 6970 set_bit(ISP_ABORT_NEEDED, 6971 &base_vha->dpc_flags); 6972 } 6973 clear_bit(ABORT_ISP_ACTIVE, 6974 &base_vha->dpc_flags); 6975 } 6976 6977 ql_dbg(ql_dbg_dpc, base_vha, 0x4006, 6978 "FCoE context reset end.\n"); 6979 } 6980 } else if (IS_QLAFX00(ha)) { 6981 if (test_and_clear_bit(ISP_UNRECOVERABLE, 6982 &base_vha->dpc_flags)) { 6983 ql_dbg(ql_dbg_dpc, base_vha, 0x4020, 6984 "Firmware Reset Recovery\n"); 6985 if (qlafx00_reset_initialize(base_vha)) { 6986 /* Failed. Abort isp later. */ 6987 if (!test_bit(UNLOADING, 6988 &base_vha->dpc_flags)) { 6989 set_bit(ISP_UNRECOVERABLE, 6990 &base_vha->dpc_flags); 6991 ql_dbg(ql_dbg_dpc, base_vha, 6992 0x4021, 6993 "Reset Recovery Failed\n"); 6994 } 6995 } 6996 } 6997 6998 if (test_and_clear_bit(FX00_TARGET_SCAN, 6999 &base_vha->dpc_flags)) { 7000 ql_dbg(ql_dbg_dpc, base_vha, 0x4022, 7001 "ISPFx00 Target Scan scheduled\n"); 7002 if (qlafx00_rescan_isp(base_vha)) { 7003 if (!test_bit(UNLOADING, 7004 &base_vha->dpc_flags)) 7005 set_bit(ISP_UNRECOVERABLE, 7006 &base_vha->dpc_flags); 7007 ql_dbg(ql_dbg_dpc, base_vha, 0x401e, 7008 "ISPFx00 Target Scan Failed\n"); 7009 } 7010 ql_dbg(ql_dbg_dpc, base_vha, 0x401f, 7011 "ISPFx00 Target Scan End\n"); 7012 } 7013 if (test_and_clear_bit(FX00_HOST_INFO_RESEND, 7014 &base_vha->dpc_flags)) { 7015 ql_dbg(ql_dbg_dpc, base_vha, 0x4023, 7016 "ISPFx00 Host Info resend scheduled\n"); 7017 qlafx00_fx_disc(base_vha, 7018 &base_vha->hw->mr.fcport, 7019 FXDISC_REG_HOST_INFO); 7020 } 7021 } 7022 7023 if (test_and_clear_bit(DETECT_SFP_CHANGE, 7024 &base_vha->dpc_flags)) { 7025 /* Semantic: 7026 * - NO-OP -- await next ISP-ABORT. Preferred method 7027 * to minimize disruptions that will occur 7028 * when a forced chip-reset occurs. 7029 * - Force -- ISP-ABORT scheduled. 7030 */ 7031 /* set_bit(ISP_ABORT_NEEDED, &base_vha->dpc_flags); */ 7032 } 7033 7034 if (test_and_clear_bit 7035 (ISP_ABORT_NEEDED, &base_vha->dpc_flags) && 7036 !test_bit(UNLOADING, &base_vha->dpc_flags)) { 7037 bool do_reset = true; 7038 7039 switch (base_vha->qlini_mode) { 7040 case QLA2XXX_INI_MODE_ENABLED: 7041 break; 7042 case QLA2XXX_INI_MODE_DISABLED: 7043 if (!qla_tgt_mode_enabled(base_vha) && 7044 !ha->flags.fw_started) 7045 do_reset = false; 7046 break; 7047 case QLA2XXX_INI_MODE_DUAL: 7048 if (!qla_dual_mode_enabled(base_vha) && 7049 !ha->flags.fw_started) 7050 do_reset = false; 7051 break; 7052 default: 7053 break; 7054 } 7055 7056 if (do_reset && !(test_and_set_bit(ABORT_ISP_ACTIVE, 7057 &base_vha->dpc_flags))) { 7058 base_vha->flags.online = 1; 7059 ql_dbg(ql_dbg_dpc, base_vha, 0x4007, 7060 "ISP abort scheduled.\n"); 7061 if (ha->isp_ops->abort_isp(base_vha)) { 7062 /* failed. retry later */ 7063 set_bit(ISP_ABORT_NEEDED, 7064 &base_vha->dpc_flags); 7065 } 7066 clear_bit(ABORT_ISP_ACTIVE, 7067 &base_vha->dpc_flags); 7068 ql_dbg(ql_dbg_dpc, base_vha, 0x4008, 7069 "ISP abort end.\n"); 7070 } 7071 } 7072 7073 if (test_bit(PROCESS_PUREX_IOCB, &base_vha->dpc_flags)) { 7074 if (atomic_read(&base_vha->loop_state) == LOOP_READY) { 7075 qla24xx_process_purex_list 7076 (&base_vha->purex_list); 7077 clear_bit(PROCESS_PUREX_IOCB, 7078 &base_vha->dpc_flags); 7079 } 7080 } 7081 7082 if (IS_QLAFX00(ha)) 7083 goto loop_resync_check; 7084 7085 if (test_bit(ISP_QUIESCE_NEEDED, &base_vha->dpc_flags)) { 7086 ql_dbg(ql_dbg_dpc, base_vha, 0x4009, 7087 "Quiescence mode scheduled.\n"); 7088 if (IS_P3P_TYPE(ha)) { 7089 if (IS_QLA82XX(ha)) 7090 qla82xx_device_state_handler(base_vha); 7091 if (IS_QLA8044(ha)) 7092 qla8044_device_state_handler(base_vha); 7093 clear_bit(ISP_QUIESCE_NEEDED, 7094 &base_vha->dpc_flags); 7095 if (!ha->flags.quiesce_owner) { 7096 qla2x00_perform_loop_resync(base_vha); 7097 if (IS_QLA82XX(ha)) { 7098 qla82xx_idc_lock(ha); 7099 qla82xx_clear_qsnt_ready( 7100 base_vha); 7101 qla82xx_idc_unlock(ha); 7102 } else if (IS_QLA8044(ha)) { 7103 qla8044_idc_lock(ha); 7104 qla8044_clear_qsnt_ready( 7105 base_vha); 7106 qla8044_idc_unlock(ha); 7107 } 7108 } 7109 } else { 7110 clear_bit(ISP_QUIESCE_NEEDED, 7111 &base_vha->dpc_flags); 7112 qla2x00_quiesce_io(base_vha); 7113 } 7114 ql_dbg(ql_dbg_dpc, base_vha, 0x400a, 7115 "Quiescence mode end.\n"); 7116 } 7117 7118 if (test_and_clear_bit(RESET_MARKER_NEEDED, 7119 &base_vha->dpc_flags) && 7120 (!(test_and_set_bit(RESET_ACTIVE, &base_vha->dpc_flags)))) { 7121 7122 ql_dbg(ql_dbg_dpc, base_vha, 0x400b, 7123 "Reset marker scheduled.\n"); 7124 qla2x00_rst_aen(base_vha); 7125 clear_bit(RESET_ACTIVE, &base_vha->dpc_flags); 7126 ql_dbg(ql_dbg_dpc, base_vha, 0x400c, 7127 "Reset marker end.\n"); 7128 } 7129 7130 /* Retry each device up to login retry count */ 7131 if (test_bit(RELOGIN_NEEDED, &base_vha->dpc_flags) && 7132 !test_bit(LOOP_RESYNC_NEEDED, &base_vha->dpc_flags) && 7133 atomic_read(&base_vha->loop_state) != LOOP_DOWN) { 7134 7135 if (!base_vha->relogin_jif || 7136 time_after_eq(jiffies, base_vha->relogin_jif)) { 7137 base_vha->relogin_jif = jiffies + HZ; 7138 clear_bit(RELOGIN_NEEDED, &base_vha->dpc_flags); 7139 7140 ql_dbg(ql_dbg_disc, base_vha, 0x400d, 7141 "Relogin scheduled.\n"); 7142 qla24xx_post_relogin_work(base_vha); 7143 } 7144 } 7145 loop_resync_check: 7146 if (!qla2x00_reset_active(base_vha) && 7147 test_and_clear_bit(LOOP_RESYNC_NEEDED, 7148 &base_vha->dpc_flags)) { 7149 /* 7150 * Allow abort_isp to complete before moving on to scanning. 7151 */ 7152 ql_dbg(ql_dbg_dpc, base_vha, 0x400f, 7153 "Loop resync scheduled.\n"); 7154 7155 if (!(test_and_set_bit(LOOP_RESYNC_ACTIVE, 7156 &base_vha->dpc_flags))) { 7157 7158 qla2x00_loop_resync(base_vha); 7159 7160 clear_bit(LOOP_RESYNC_ACTIVE, 7161 &base_vha->dpc_flags); 7162 } 7163 7164 ql_dbg(ql_dbg_dpc, base_vha, 0x4010, 7165 "Loop resync end.\n"); 7166 } 7167 7168 if (IS_QLAFX00(ha)) 7169 goto intr_on_check; 7170 7171 if (test_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags) && 7172 atomic_read(&base_vha->loop_state) == LOOP_READY) { 7173 clear_bit(NPIV_CONFIG_NEEDED, &base_vha->dpc_flags); 7174 qla2xxx_flash_npiv_conf(base_vha); 7175 } 7176 7177 intr_on_check: 7178 if (!ha->interrupts_on) 7179 ha->isp_ops->enable_intrs(ha); 7180 7181 if (test_and_clear_bit(BEACON_BLINK_NEEDED, 7182 &base_vha->dpc_flags)) { 7183 if (ha->beacon_blink_led == 1) 7184 ha->isp_ops->beacon_blink(base_vha); 7185 } 7186 7187 /* qpair online check */ 7188 if (test_and_clear_bit(QPAIR_ONLINE_CHECK_NEEDED, 7189 &base_vha->dpc_flags)) { 7190 if (ha->flags.eeh_busy || 7191 ha->flags.pci_channel_io_perm_failure) 7192 online = 0; 7193 else 7194 online = 1; 7195 7196 mutex_lock(&ha->mq_lock); 7197 list_for_each_entry(qpair, &base_vha->qp_list, 7198 qp_list_elem) 7199 qpair->online = online; 7200 mutex_unlock(&ha->mq_lock); 7201 } 7202 7203 if (test_and_clear_bit(SET_ZIO_THRESHOLD_NEEDED, 7204 &base_vha->dpc_flags)) { 7205 u16 threshold = ha->nvme_last_rptd_aen + ha->last_zio_threshold; 7206 7207 if (threshold > ha->orig_fw_xcb_count) 7208 threshold = ha->orig_fw_xcb_count; 7209 7210 ql_log(ql_log_info, base_vha, 0xffffff, 7211 "SET ZIO Activity exchange threshold to %d.\n", 7212 threshold); 7213 if (qla27xx_set_zio_threshold(base_vha, threshold)) { 7214 ql_log(ql_log_info, base_vha, 0xffffff, 7215 "Unable to SET ZIO Activity exchange threshold to %d.\n", 7216 threshold); 7217 } 7218 } 7219 7220 if (!IS_QLAFX00(ha)) 7221 qla2x00_do_dpc_all_vps(base_vha); 7222 7223 if (test_and_clear_bit(N2N_LINK_RESET, 7224 &base_vha->dpc_flags)) { 7225 qla2x00_lip_reset(base_vha); 7226 } 7227 7228 ha->dpc_active = 0; 7229 end_loop: 7230 set_current_state(TASK_INTERRUPTIBLE); 7231 } /* End of while(1) */ 7232 __set_current_state(TASK_RUNNING); 7233 7234 ql_dbg(ql_dbg_dpc, base_vha, 0x4011, 7235 "DPC handler exiting.\n"); 7236 7237 /* 7238 * Make sure that nobody tries to wake us up again. 7239 */ 7240 ha->dpc_active = 0; 7241 7242 return 0; 7243 } 7244 7245 void 7246 qla2xxx_wake_dpc(struct scsi_qla_host *vha) 7247 { 7248 struct qla_hw_data *ha = vha->hw; 7249 struct task_struct *t = ha->dpc_thread; 7250 7251 if (!test_bit(UNLOADING, &vha->dpc_flags) && t) 7252 wake_up_process(t); 7253 } 7254 EXPORT_SYMBOL(qla2xxx_wake_dpc); 7255 7256 /* 7257 * qla2x00_rst_aen 7258 * Processes asynchronous reset. 7259 * 7260 * Input: 7261 * ha = adapter block pointer. 7262 */ 7263 static void 7264 qla2x00_rst_aen(scsi_qla_host_t *vha) 7265 { 7266 if (vha->flags.online && !vha->flags.reset_active && 7267 !atomic_read(&vha->loop_down_timer) && 7268 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags))) { 7269 do { 7270 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags); 7271 7272 /* 7273 * Issue marker command only when we are going to start 7274 * the I/O. 7275 */ 7276 vha->marker_needed = 1; 7277 } while (!atomic_read(&vha->loop_down_timer) && 7278 (test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags))); 7279 } 7280 } 7281 7282 static bool qla_do_heartbeat(struct scsi_qla_host *vha) 7283 { 7284 struct qla_hw_data *ha = vha->hw; 7285 u32 cmpl_cnt; 7286 u16 i; 7287 bool do_heartbeat = false; 7288 7289 /* 7290 * Allow do_heartbeat only if we don’t have any active interrupts, 7291 * but there are still IOs outstanding with firmware. 7292 */ 7293 cmpl_cnt = ha->base_qpair->cmd_completion_cnt; 7294 if (cmpl_cnt == ha->base_qpair->prev_completion_cnt && 7295 cmpl_cnt != ha->base_qpair->cmd_cnt) { 7296 do_heartbeat = true; 7297 goto skip; 7298 } 7299 ha->base_qpair->prev_completion_cnt = cmpl_cnt; 7300 7301 for (i = 0; i < ha->max_qpairs; i++) { 7302 if (ha->queue_pair_map[i]) { 7303 cmpl_cnt = ha->queue_pair_map[i]->cmd_completion_cnt; 7304 if (cmpl_cnt == ha->queue_pair_map[i]->prev_completion_cnt && 7305 cmpl_cnt != ha->queue_pair_map[i]->cmd_cnt) { 7306 do_heartbeat = true; 7307 break; 7308 } 7309 ha->queue_pair_map[i]->prev_completion_cnt = cmpl_cnt; 7310 } 7311 } 7312 7313 skip: 7314 return do_heartbeat; 7315 } 7316 7317 static void qla_heart_beat(struct scsi_qla_host *vha, u16 dpc_started) 7318 { 7319 struct qla_hw_data *ha = vha->hw; 7320 7321 if (vha->vp_idx) 7322 return; 7323 7324 if (vha->hw->flags.eeh_busy || qla2x00_chip_is_down(vha)) 7325 return; 7326 7327 /* 7328 * dpc thread cannot run if heartbeat is running at the same time. 7329 * We also do not want to starve heartbeat task. Therefore, do 7330 * heartbeat task at least once every 5 seconds. 7331 */ 7332 if (dpc_started && 7333 time_before(jiffies, ha->last_heartbeat_run_jiffies + 5 * HZ)) 7334 return; 7335 7336 if (qla_do_heartbeat(vha)) { 7337 ha->last_heartbeat_run_jiffies = jiffies; 7338 queue_work(ha->wq, &ha->heartbeat_work); 7339 } 7340 } 7341 7342 static void qla_wind_down_chip(scsi_qla_host_t *vha) 7343 { 7344 struct qla_hw_data *ha = vha->hw; 7345 7346 if (!ha->flags.eeh_busy) 7347 return; 7348 if (ha->pci_error_state) 7349 /* system is trying to recover */ 7350 return; 7351 7352 /* 7353 * Current system is not handling PCIE error. At this point, this is 7354 * best effort to wind down the adapter. 7355 */ 7356 if (time_after_eq(jiffies, ha->eeh_jif + ql2xdelay_before_pci_error_handling * HZ) && 7357 !ha->flags.eeh_flush) { 7358 ql_log(ql_log_info, vha, 0x9009, 7359 "PCI Error detected, attempting to reset hardware.\n"); 7360 7361 ha->isp_ops->reset_chip(vha); 7362 ha->isp_ops->disable_intrs(ha); 7363 7364 ha->flags.eeh_flush = EEH_FLUSH_RDY; 7365 ha->eeh_jif = jiffies; 7366 7367 } else if (ha->flags.eeh_flush == EEH_FLUSH_RDY && 7368 time_after_eq(jiffies, ha->eeh_jif + 5 * HZ)) { 7369 pci_clear_master(ha->pdev); 7370 7371 /* flush all command */ 7372 qla2x00_abort_isp_cleanup(vha); 7373 ha->flags.eeh_flush = EEH_FLUSH_DONE; 7374 7375 ql_log(ql_log_info, vha, 0x900a, 7376 "PCI Error handling complete, all IOs aborted.\n"); 7377 } 7378 } 7379 7380 /************************************************************************** 7381 * qla2x00_timer 7382 * 7383 * Description: 7384 * One second timer 7385 * 7386 * Context: Interrupt 7387 ***************************************************************************/ 7388 void 7389 qla2x00_timer(struct timer_list *t) 7390 { 7391 scsi_qla_host_t *vha = timer_container_of(vha, t, timer); 7392 unsigned long cpu_flags = 0; 7393 int start_dpc = 0; 7394 int index; 7395 srb_t *sp; 7396 uint16_t w; 7397 struct qla_hw_data *ha = vha->hw; 7398 struct req_que *req; 7399 unsigned long flags; 7400 fc_port_t *fcport = NULL; 7401 7402 if (ha->flags.eeh_busy) { 7403 qla_wind_down_chip(vha); 7404 7405 ql_dbg(ql_dbg_timer, vha, 0x6000, 7406 "EEH = %d, restarting timer.\n", 7407 ha->flags.eeh_busy); 7408 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7409 return; 7410 } 7411 7412 /* 7413 * Hardware read to raise pending EEH errors during mailbox waits. If 7414 * the read returns -1 then disable the board. 7415 */ 7416 if (!pci_channel_offline(ha->pdev)) { 7417 pci_read_config_word(ha->pdev, PCI_VENDOR_ID, &w); 7418 qla2x00_check_reg16_for_disconnect(vha, w); 7419 } 7420 7421 /* Make sure qla82xx_watchdog is run only for physical port */ 7422 if (!vha->vp_idx && IS_P3P_TYPE(ha)) { 7423 if (test_bit(ISP_QUIESCE_NEEDED, &vha->dpc_flags)) 7424 start_dpc++; 7425 if (IS_QLA82XX(ha)) 7426 qla82xx_watchdog(vha); 7427 else if (IS_QLA8044(ha)) 7428 qla8044_watchdog(vha); 7429 } 7430 7431 if (!vha->vp_idx && IS_QLAFX00(ha)) 7432 qlafx00_timer_routine(vha); 7433 7434 if (vha->link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7435 vha->link_down_time++; 7436 7437 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags); 7438 list_for_each_entry(fcport, &vha->vp_fcports, list) { 7439 if (fcport->tgt_link_down_time < QLA2XX_MAX_LINK_DOWN_TIME) 7440 fcport->tgt_link_down_time++; 7441 } 7442 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags); 7443 7444 /* Loop down handler. */ 7445 if (atomic_read(&vha->loop_down_timer) > 0 && 7446 !(test_bit(ABORT_ISP_ACTIVE, &vha->dpc_flags)) && 7447 !(test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags)) 7448 && vha->flags.online) { 7449 7450 if (atomic_read(&vha->loop_down_timer) == 7451 vha->loop_down_abort_time) { 7452 7453 ql_log(ql_log_info, vha, 0x6008, 7454 "Loop down - aborting the queues before time expires.\n"); 7455 7456 if (!IS_QLA2100(ha) && vha->link_down_timeout) 7457 atomic_set(&vha->loop_state, LOOP_DEAD); 7458 7459 /* 7460 * Schedule an ISP abort to return any FCP2-device 7461 * commands. 7462 */ 7463 /* NPIV - scan physical port only */ 7464 if (!vha->vp_idx) { 7465 spin_lock_irqsave(&ha->hardware_lock, 7466 cpu_flags); 7467 req = ha->req_q_map[0]; 7468 for (index = 1; 7469 index < req->num_outstanding_cmds; 7470 index++) { 7471 fc_port_t *sfcp; 7472 7473 sp = req->outstanding_cmds[index]; 7474 if (!sp) 7475 continue; 7476 if (sp->cmd_type != TYPE_SRB) 7477 continue; 7478 if (sp->type != SRB_SCSI_CMD) 7479 continue; 7480 sfcp = sp->fcport; 7481 if (!(sfcp->flags & FCF_FCP2_DEVICE)) 7482 continue; 7483 7484 if (IS_QLA82XX(ha)) 7485 set_bit(FCOE_CTX_RESET_NEEDED, 7486 &vha->dpc_flags); 7487 else 7488 set_bit(ISP_ABORT_NEEDED, 7489 &vha->dpc_flags); 7490 break; 7491 } 7492 spin_unlock_irqrestore(&ha->hardware_lock, 7493 cpu_flags); 7494 } 7495 start_dpc++; 7496 } 7497 7498 /* if the loop has been down for 4 minutes, reinit adapter */ 7499 if (atomic_dec_and_test(&vha->loop_down_timer) != 0) { 7500 if (!(vha->device_flags & DFLG_NO_CABLE) && !vha->vp_idx) { 7501 ql_log(ql_log_warn, vha, 0x6009, 7502 "Loop down - aborting ISP.\n"); 7503 7504 if (IS_QLA82XX(ha)) 7505 set_bit(FCOE_CTX_RESET_NEEDED, 7506 &vha->dpc_flags); 7507 else 7508 set_bit(ISP_ABORT_NEEDED, 7509 &vha->dpc_flags); 7510 } 7511 } 7512 ql_dbg(ql_dbg_timer, vha, 0x600a, 7513 "Loop down - seconds remaining %d.\n", 7514 atomic_read(&vha->loop_down_timer)); 7515 } 7516 /* Check if beacon LED needs to be blinked for physical host only */ 7517 if (!vha->vp_idx && (ha->beacon_blink_led == 1)) { 7518 /* There is no beacon_blink function for ISP82xx */ 7519 if (!IS_P3P_TYPE(ha)) { 7520 set_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags); 7521 start_dpc++; 7522 } 7523 } 7524 7525 /* check if edif running */ 7526 if (vha->hw->flags.edif_enabled) 7527 qla_edif_timer(vha); 7528 7529 /* Process any deferred work. */ 7530 if (!list_empty(&vha->work_list)) { 7531 unsigned long flags; 7532 bool q = false; 7533 7534 spin_lock_irqsave(&vha->work_lock, flags); 7535 if (!test_and_set_bit(IOCB_WORK_ACTIVE, &vha->dpc_flags)) 7536 q = true; 7537 spin_unlock_irqrestore(&vha->work_lock, flags); 7538 if (q) 7539 queue_work(vha->hw->wq, &vha->iocb_work); 7540 } 7541 7542 /* 7543 * FC-NVME 7544 * see if the active AEN count has changed from what was last reported. 7545 */ 7546 index = atomic_read(&ha->nvme_active_aen_cnt); 7547 if (!vha->vp_idx && 7548 (index != ha->nvme_last_rptd_aen) && 7549 ha->zio_mode == QLA_ZIO_MODE_6 && 7550 !ha->flags.host_shutting_down) { 7551 ha->nvme_last_rptd_aen = atomic_read(&ha->nvme_active_aen_cnt); 7552 ql_log(ql_log_info, vha, 0x3002, 7553 "nvme: Sched: Set ZIO exchange threshold to %d.\n", 7554 ha->nvme_last_rptd_aen); 7555 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7556 start_dpc++; 7557 } 7558 7559 if (!vha->vp_idx && 7560 atomic_read(&ha->zio_threshold) != ha->last_zio_threshold && 7561 IS_ZIO_THRESHOLD_CAPABLE(ha)) { 7562 ql_log(ql_log_info, vha, 0x3002, 7563 "Sched: Set ZIO exchange threshold to %d.\n", 7564 ha->last_zio_threshold); 7565 ha->last_zio_threshold = atomic_read(&ha->zio_threshold); 7566 set_bit(SET_ZIO_THRESHOLD_NEEDED, &vha->dpc_flags); 7567 start_dpc++; 7568 } 7569 qla_adjust_buf(vha); 7570 7571 /* borrowing w to signify dpc will run */ 7572 w = 0; 7573 /* Schedule the DPC routine if needed */ 7574 if ((test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags) || 7575 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags) || 7576 start_dpc || 7577 test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags) || 7578 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags) || 7579 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags) || 7580 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags) || 7581 test_bit(VP_DPC_NEEDED, &vha->dpc_flags) || 7582 test_bit(RELOGIN_NEEDED, &vha->dpc_flags) || 7583 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags))) { 7584 ql_dbg(ql_dbg_timer, vha, 0x600b, 7585 "isp_abort_needed=%d loop_resync_needed=%d " 7586 "start_dpc=%d reset_marker_needed=%d", 7587 test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags), 7588 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags), 7589 start_dpc, test_bit(RESET_MARKER_NEEDED, &vha->dpc_flags)); 7590 ql_dbg(ql_dbg_timer, vha, 0x600c, 7591 "beacon_blink_needed=%d isp_unrecoverable=%d " 7592 "fcoe_ctx_reset_needed=%d vp_dpc_needed=%d " 7593 "relogin_needed=%d, Process_purex_iocb=%d.\n", 7594 test_bit(BEACON_BLINK_NEEDED, &vha->dpc_flags), 7595 test_bit(ISP_UNRECOVERABLE, &vha->dpc_flags), 7596 test_bit(FCOE_CTX_RESET_NEEDED, &vha->dpc_flags), 7597 test_bit(VP_DPC_NEEDED, &vha->dpc_flags), 7598 test_bit(RELOGIN_NEEDED, &vha->dpc_flags), 7599 test_bit(PROCESS_PUREX_IOCB, &vha->dpc_flags)); 7600 qla2xxx_wake_dpc(vha); 7601 w = 1; 7602 } 7603 7604 qla_heart_beat(vha, w); 7605 7606 qla2x00_restart_timer(vha, WATCH_INTERVAL); 7607 } 7608 7609 /* Firmware interface routines. */ 7610 7611 #define FW_ISP21XX 0 7612 #define FW_ISP22XX 1 7613 #define FW_ISP2300 2 7614 #define FW_ISP2322 3 7615 #define FW_ISP24XX 4 7616 #define FW_ISP25XX 5 7617 #define FW_ISP81XX 6 7618 #define FW_ISP82XX 7 7619 #define FW_ISP2031 8 7620 #define FW_ISP8031 9 7621 #define FW_ISP27XX 10 7622 #define FW_ISP28XX 11 7623 7624 #define FW_FILE_ISP21XX "ql2100_fw.bin" 7625 #define FW_FILE_ISP22XX "ql2200_fw.bin" 7626 #define FW_FILE_ISP2300 "ql2300_fw.bin" 7627 #define FW_FILE_ISP2322 "ql2322_fw.bin" 7628 #define FW_FILE_ISP24XX "ql2400_fw.bin" 7629 #define FW_FILE_ISP25XX "ql2500_fw.bin" 7630 #define FW_FILE_ISP81XX "ql8100_fw.bin" 7631 #define FW_FILE_ISP82XX "ql8200_fw.bin" 7632 #define FW_FILE_ISP2031 "ql2600_fw.bin" 7633 #define FW_FILE_ISP8031 "ql8300_fw.bin" 7634 #define FW_FILE_ISP27XX "ql2700_fw.bin" 7635 #define FW_FILE_ISP28XX "ql2800_fw.bin" 7636 7637 7638 static DEFINE_MUTEX(qla_fw_lock); 7639 7640 static struct fw_blob qla_fw_blobs[] = { 7641 { .name = FW_FILE_ISP21XX, .segs = { 0x1000, 0 }, }, 7642 { .name = FW_FILE_ISP22XX, .segs = { 0x1000, 0 }, }, 7643 { .name = FW_FILE_ISP2300, .segs = { 0x800, 0 }, }, 7644 { .name = FW_FILE_ISP2322, .segs = { 0x800, 0x1c000, 0x1e000, 0 }, }, 7645 { .name = FW_FILE_ISP24XX, }, 7646 { .name = FW_FILE_ISP25XX, }, 7647 { .name = FW_FILE_ISP81XX, }, 7648 { .name = FW_FILE_ISP82XX, }, 7649 { .name = FW_FILE_ISP2031, }, 7650 { .name = FW_FILE_ISP8031, }, 7651 { .name = FW_FILE_ISP27XX, }, 7652 { .name = FW_FILE_ISP28XX, }, 7653 { .name = NULL, }, 7654 }; 7655 7656 struct fw_blob * 7657 qla2x00_request_firmware(scsi_qla_host_t *vha) 7658 { 7659 struct qla_hw_data *ha = vha->hw; 7660 struct fw_blob *blob; 7661 7662 if (IS_QLA2100(ha)) { 7663 blob = &qla_fw_blobs[FW_ISP21XX]; 7664 } else if (IS_QLA2200(ha)) { 7665 blob = &qla_fw_blobs[FW_ISP22XX]; 7666 } else if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) { 7667 blob = &qla_fw_blobs[FW_ISP2300]; 7668 } else if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 7669 blob = &qla_fw_blobs[FW_ISP2322]; 7670 } else if (IS_QLA24XX_TYPE(ha)) { 7671 blob = &qla_fw_blobs[FW_ISP24XX]; 7672 } else if (IS_QLA25XX(ha)) { 7673 blob = &qla_fw_blobs[FW_ISP25XX]; 7674 } else if (IS_QLA81XX(ha)) { 7675 blob = &qla_fw_blobs[FW_ISP81XX]; 7676 } else if (IS_QLA82XX(ha)) { 7677 blob = &qla_fw_blobs[FW_ISP82XX]; 7678 } else if (IS_QLA2031(ha)) { 7679 blob = &qla_fw_blobs[FW_ISP2031]; 7680 } else if (IS_QLA8031(ha)) { 7681 blob = &qla_fw_blobs[FW_ISP8031]; 7682 } else if (IS_QLA27XX(ha)) { 7683 blob = &qla_fw_blobs[FW_ISP27XX]; 7684 } else if (IS_QLA28XX(ha)) { 7685 blob = &qla_fw_blobs[FW_ISP28XX]; 7686 } else { 7687 return NULL; 7688 } 7689 7690 if (!blob->name) 7691 return NULL; 7692 7693 mutex_lock(&qla_fw_lock); 7694 if (blob->fw) 7695 goto out; 7696 7697 if (request_firmware(&blob->fw, blob->name, &ha->pdev->dev)) { 7698 ql_log(ql_log_warn, vha, 0x0063, 7699 "Failed to load firmware image (%s).\n", blob->name); 7700 blob->fw = NULL; 7701 blob = NULL; 7702 } 7703 7704 out: 7705 mutex_unlock(&qla_fw_lock); 7706 return blob; 7707 } 7708 7709 static void 7710 qla2x00_release_firmware(void) 7711 { 7712 struct fw_blob *blob; 7713 7714 mutex_lock(&qla_fw_lock); 7715 for (blob = qla_fw_blobs; blob->name; blob++) 7716 release_firmware(blob->fw); 7717 mutex_unlock(&qla_fw_lock); 7718 } 7719 7720 static void qla_pci_error_cleanup(scsi_qla_host_t *vha) 7721 { 7722 struct qla_hw_data *ha = vha->hw; 7723 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev); 7724 struct qla_qpair *qpair = NULL; 7725 struct scsi_qla_host *vp, *tvp; 7726 fc_port_t *fcport; 7727 int i; 7728 unsigned long flags; 7729 7730 ql_dbg(ql_dbg_aer, vha, 0x9000, 7731 "%s\n", __func__); 7732 ha->chip_reset++; 7733 7734 ha->base_qpair->chip_reset = ha->chip_reset; 7735 for (i = 0; i < ha->max_qpairs; i++) { 7736 if (ha->queue_pair_map[i]) 7737 ha->queue_pair_map[i]->chip_reset = 7738 ha->base_qpair->chip_reset; 7739 } 7740 7741 /* 7742 * purge mailbox might take a while. Slot Reset/chip reset 7743 * will take care of the purge 7744 */ 7745 7746 mutex_lock(&ha->mq_lock); 7747 ha->base_qpair->online = 0; 7748 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7749 qpair->online = 0; 7750 wmb(); 7751 mutex_unlock(&ha->mq_lock); 7752 7753 qla2x00_mark_all_devices_lost(vha); 7754 7755 spin_lock_irqsave(&ha->vport_slock, flags); 7756 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7757 atomic_inc(&vp->vref_count); 7758 spin_unlock_irqrestore(&ha->vport_slock, flags); 7759 qla2x00_mark_all_devices_lost(vp); 7760 spin_lock_irqsave(&ha->vport_slock, flags); 7761 atomic_dec(&vp->vref_count); 7762 } 7763 spin_unlock_irqrestore(&ha->vport_slock, flags); 7764 7765 /* Clear all async request states across all VPs. */ 7766 list_for_each_entry(fcport, &vha->vp_fcports, list) 7767 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7768 7769 spin_lock_irqsave(&ha->vport_slock, flags); 7770 list_for_each_entry_safe(vp, tvp, &ha->vp_list, list) { 7771 atomic_inc(&vp->vref_count); 7772 spin_unlock_irqrestore(&ha->vport_slock, flags); 7773 list_for_each_entry(fcport, &vp->vp_fcports, list) 7774 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT); 7775 spin_lock_irqsave(&ha->vport_slock, flags); 7776 atomic_dec(&vp->vref_count); 7777 } 7778 spin_unlock_irqrestore(&ha->vport_slock, flags); 7779 } 7780 7781 7782 /** 7783 * qla2xxx_set_affinity_nobalance 7784 * @pdev: pci_dev struct for a qla2xxx device 7785 * @flag: bool 7786 * true: enable "IRQ_NO_BALANCING" bit for msix interrupt 7787 * false: disable "IRQ_NO_BALANCING" bit for msix interrupt 7788 * Description: This function will be called to disable/enable 7789 * "IRQ_NO_BALANCING" to avoid irqbalance daemon 7790 * kicking in during adapter reset. 7791 **/ 7792 7793 static void qla2xxx_set_affinity_nobalance(struct pci_dev *pdev, bool flag) 7794 { 7795 int irq, i; 7796 7797 for (i = 0; i < QLA_BASE_VECTORS; i++) { 7798 irq = pci_irq_vector(pdev, i); 7799 7800 if (flag) 7801 irq_set_status_flags(irq, IRQ_NO_BALANCING); 7802 else 7803 irq_clear_status_flags(irq, IRQ_NO_BALANCING); 7804 } 7805 } 7806 7807 static pci_ers_result_t 7808 qla2xxx_pci_error_detected(struct pci_dev *pdev, pci_channel_state_t state) 7809 { 7810 scsi_qla_host_t *vha = pci_get_drvdata(pdev); 7811 struct qla_hw_data *ha = vha->hw; 7812 pci_ers_result_t ret = PCI_ERS_RESULT_NEED_RESET; 7813 7814 ql_log(ql_log_warn, vha, 0x9000, 7815 "PCI error detected, state %x.\n", state); 7816 ha->pci_error_state = QLA_PCI_ERR_DETECTED; 7817 7818 if (!atomic_read(&pdev->enable_cnt)) { 7819 ql_log(ql_log_info, vha, 0xffff, 7820 "PCI device is disabled,state %x\n", state); 7821 ret = PCI_ERS_RESULT_NEED_RESET; 7822 goto out; 7823 } 7824 7825 qla2xxx_set_affinity_nobalance(pdev, false); 7826 7827 switch (state) { 7828 case pci_channel_io_normal: 7829 qla_pci_set_eeh_busy(vha); 7830 if (ql2xmqsupport || ql2xnvmeenable) { 7831 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7832 qla2xxx_wake_dpc(vha); 7833 } 7834 ret = PCI_ERS_RESULT_CAN_RECOVER; 7835 break; 7836 case pci_channel_io_frozen: 7837 qla_pci_set_eeh_busy(vha); 7838 ret = PCI_ERS_RESULT_NEED_RESET; 7839 break; 7840 case pci_channel_io_perm_failure: 7841 ha->flags.pci_channel_io_perm_failure = 1; 7842 qla2x00_abort_all_cmds(vha, DID_NO_CONNECT << 16); 7843 if (ql2xmqsupport || ql2xnvmeenable) { 7844 set_bit(QPAIR_ONLINE_CHECK_NEEDED, &vha->dpc_flags); 7845 qla2xxx_wake_dpc(vha); 7846 } 7847 ret = PCI_ERS_RESULT_DISCONNECT; 7848 } 7849 out: 7850 ql_dbg(ql_dbg_aer, vha, 0x600d, 7851 "PCI error detected returning [%x].\n", ret); 7852 return ret; 7853 } 7854 7855 static pci_ers_result_t 7856 qla2xxx_pci_mmio_enabled(struct pci_dev *pdev) 7857 { 7858 int risc_paused = 0; 7859 uint32_t stat; 7860 unsigned long flags; 7861 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7862 struct qla_hw_data *ha = base_vha->hw; 7863 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 7864 struct device_reg_24xx __iomem *reg24 = &ha->iobase->isp24; 7865 7866 ql_log(ql_log_warn, base_vha, 0x9000, 7867 "mmio enabled\n"); 7868 7869 ha->pci_error_state = QLA_PCI_MMIO_ENABLED; 7870 7871 if (IS_QLA82XX(ha)) 7872 return PCI_ERS_RESULT_RECOVERED; 7873 7874 if (qla2x00_isp_reg_stat(ha)) { 7875 ql_log(ql_log_info, base_vha, 0x803f, 7876 "During mmio enabled, PCI/Register disconnect still detected.\n"); 7877 goto out; 7878 } 7879 7880 spin_lock_irqsave(&ha->hardware_lock, flags); 7881 if (IS_QLA2100(ha) || IS_QLA2200(ha)){ 7882 stat = rd_reg_word(®->hccr); 7883 if (stat & HCCR_RISC_PAUSE) 7884 risc_paused = 1; 7885 } else if (IS_QLA23XX(ha)) { 7886 stat = rd_reg_dword(®->u.isp2300.host_status); 7887 if (stat & HSR_RISC_PAUSED) 7888 risc_paused = 1; 7889 } else if (IS_FWI2_CAPABLE(ha)) { 7890 stat = rd_reg_dword(®24->host_status); 7891 if (stat & HSRX_RISC_PAUSED) 7892 risc_paused = 1; 7893 } 7894 spin_unlock_irqrestore(&ha->hardware_lock, flags); 7895 7896 if (risc_paused) { 7897 ql_log(ql_log_info, base_vha, 0x9003, 7898 "RISC paused -- mmio_enabled, Dumping firmware.\n"); 7899 qla2xxx_dump_fw(base_vha); 7900 } 7901 out: 7902 /* set PCI_ERS_RESULT_NEED_RESET to trigger call to qla2xxx_pci_slot_reset */ 7903 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7904 "mmio enabled returning.\n"); 7905 return PCI_ERS_RESULT_NEED_RESET; 7906 } 7907 7908 static pci_ers_result_t 7909 qla2xxx_pci_slot_reset(struct pci_dev *pdev) 7910 { 7911 pci_ers_result_t ret = PCI_ERS_RESULT_DISCONNECT; 7912 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7913 struct qla_hw_data *ha = base_vha->hw; 7914 int rc; 7915 struct qla_qpair *qpair = NULL; 7916 7917 ql_log(ql_log_warn, base_vha, 0x9004, 7918 "Slot Reset.\n"); 7919 7920 ha->pci_error_state = QLA_PCI_SLOT_RESET; 7921 7922 pci_restore_state(pdev); 7923 7924 if (ha->mem_only) 7925 rc = pci_enable_device_mem(pdev); 7926 else 7927 rc = pci_enable_device(pdev); 7928 7929 if (rc) { 7930 ql_log(ql_log_warn, base_vha, 0x9005, 7931 "Can't re-enable PCI device after reset.\n"); 7932 goto exit_slot_reset; 7933 } 7934 7935 7936 if (ha->isp_ops->pci_config(base_vha)) 7937 goto exit_slot_reset; 7938 7939 mutex_lock(&ha->mq_lock); 7940 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 7941 qpair->online = 1; 7942 mutex_unlock(&ha->mq_lock); 7943 7944 ha->flags.eeh_busy = 0; 7945 base_vha->flags.online = 1; 7946 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7947 ha->isp_ops->abort_isp(base_vha); 7948 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 7949 7950 if (qla2x00_isp_reg_stat(ha)) { 7951 ha->flags.eeh_busy = 1; 7952 qla_pci_error_cleanup(base_vha); 7953 ql_log(ql_log_warn, base_vha, 0x9005, 7954 "Device unable to recover from PCI error.\n"); 7955 } else { 7956 ret = PCI_ERS_RESULT_RECOVERED; 7957 } 7958 7959 exit_slot_reset: 7960 ql_dbg(ql_dbg_aer, base_vha, 0x900e, 7961 "Slot Reset returning %x.\n", ret); 7962 7963 qla2xxx_set_affinity_nobalance(pdev, true); 7964 7965 return ret; 7966 } 7967 7968 static void 7969 qla2xxx_pci_resume(struct pci_dev *pdev) 7970 { 7971 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 7972 struct qla_hw_data *ha = base_vha->hw; 7973 int ret; 7974 7975 ql_log(ql_log_warn, base_vha, 0x900f, 7976 "Pci Resume.\n"); 7977 7978 7979 ret = qla2x00_wait_for_hba_online(base_vha); 7980 if (ret != QLA_SUCCESS) { 7981 ql_log(ql_log_fatal, base_vha, 0x9002, 7982 "The device failed to resume I/O from slot/link_reset.\n"); 7983 } 7984 ha->pci_error_state = QLA_PCI_RESUME; 7985 ql_dbg(ql_dbg_aer, base_vha, 0x600d, 7986 "Pci Resume returning.\n"); 7987 } 7988 7989 void qla_pci_set_eeh_busy(struct scsi_qla_host *vha) 7990 { 7991 struct qla_hw_data *ha = vha->hw; 7992 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 7993 bool do_cleanup = false; 7994 unsigned long flags; 7995 7996 if (ha->flags.eeh_busy) 7997 return; 7998 7999 spin_lock_irqsave(&base_vha->work_lock, flags); 8000 if (!ha->flags.eeh_busy) { 8001 ha->eeh_jif = jiffies; 8002 ha->flags.eeh_flush = 0; 8003 8004 ha->flags.eeh_busy = 1; 8005 do_cleanup = true; 8006 } 8007 spin_unlock_irqrestore(&base_vha->work_lock, flags); 8008 8009 if (do_cleanup) 8010 qla_pci_error_cleanup(base_vha); 8011 } 8012 8013 /* 8014 * this routine will schedule a task to pause IO from interrupt context 8015 * if caller sees a PCIE error event (register read = 0xf's) 8016 */ 8017 void qla_schedule_eeh_work(struct scsi_qla_host *vha) 8018 { 8019 struct qla_hw_data *ha = vha->hw; 8020 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev); 8021 8022 if (ha->flags.eeh_busy) 8023 return; 8024 8025 set_bit(DO_EEH_RECOVERY, &base_vha->dpc_flags); 8026 qla2xxx_wake_dpc(base_vha); 8027 } 8028 8029 static void 8030 qla_pci_reset_prepare(struct pci_dev *pdev) 8031 { 8032 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 8033 struct qla_hw_data *ha = base_vha->hw; 8034 struct qla_qpair *qpair; 8035 8036 ql_log(ql_log_warn, base_vha, 0xffff, 8037 "%s.\n", __func__); 8038 8039 /* 8040 * PCI FLR/function reset is about to reset the 8041 * slot. Stop the chip to stop all DMA access. 8042 * It is assumed that pci_reset_done will be called 8043 * after FLR to resume Chip operation. 8044 */ 8045 ha->flags.eeh_busy = 1; 8046 mutex_lock(&ha->mq_lock); 8047 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8048 qpair->online = 0; 8049 mutex_unlock(&ha->mq_lock); 8050 8051 set_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8052 qla2x00_abort_isp_cleanup(base_vha); 8053 qla2x00_abort_all_cmds(base_vha, DID_RESET << 16); 8054 } 8055 8056 static void 8057 qla_pci_reset_done(struct pci_dev *pdev) 8058 { 8059 scsi_qla_host_t *base_vha = pci_get_drvdata(pdev); 8060 struct qla_hw_data *ha = base_vha->hw; 8061 struct qla_qpair *qpair; 8062 8063 ql_log(ql_log_warn, base_vha, 0xffff, 8064 "%s.\n", __func__); 8065 8066 /* 8067 * FLR just completed by PCI layer. Resume adapter 8068 */ 8069 ha->flags.eeh_busy = 0; 8070 mutex_lock(&ha->mq_lock); 8071 list_for_each_entry(qpair, &base_vha->qp_list, qp_list_elem) 8072 qpair->online = 1; 8073 mutex_unlock(&ha->mq_lock); 8074 8075 base_vha->flags.online = 1; 8076 ha->isp_ops->abort_isp(base_vha); 8077 clear_bit(ABORT_ISP_ACTIVE, &base_vha->dpc_flags); 8078 } 8079 8080 static void qla2xxx_map_queues(struct Scsi_Host *shost) 8081 { 8082 scsi_qla_host_t *vha = (scsi_qla_host_t *)shost->hostdata; 8083 struct blk_mq_queue_map *qmap = &shost->tag_set.map[HCTX_TYPE_DEFAULT]; 8084 8085 if (USER_CTRL_IRQ(vha->hw) || !vha->hw->mqiobase) 8086 blk_mq_map_queues(qmap); 8087 else 8088 blk_mq_map_hw_queues(qmap, &vha->hw->pdev->dev, 8089 vha->irq_offset); 8090 } 8091 8092 struct scsi_host_template qla2xxx_driver_template = { 8093 .module = THIS_MODULE, 8094 .name = QLA2XXX_DRIVER_NAME, 8095 .queuecommand = qla2xxx_queuecommand, 8096 8097 .eh_timed_out = fc_eh_timed_out, 8098 .eh_abort_handler = qla2xxx_eh_abort, 8099 .eh_should_retry_cmd = fc_eh_should_retry_cmd, 8100 .eh_device_reset_handler = qla2xxx_eh_device_reset, 8101 .eh_target_reset_handler = qla2xxx_eh_target_reset, 8102 .eh_bus_reset_handler = qla2xxx_eh_bus_reset, 8103 .eh_host_reset_handler = qla2xxx_eh_host_reset, 8104 8105 .sdev_configure = qla2xxx_sdev_configure, 8106 8107 .sdev_init = qla2xxx_sdev_init, 8108 .sdev_destroy = qla2xxx_sdev_destroy, 8109 .scan_finished = qla2xxx_scan_finished, 8110 .scan_start = qla2xxx_scan_start, 8111 .change_queue_depth = scsi_change_queue_depth, 8112 .map_queues = qla2xxx_map_queues, 8113 .this_id = -1, 8114 .cmd_per_lun = 3, 8115 .sg_tablesize = SG_ALL, 8116 8117 .max_sectors = 0xFFFF, 8118 .shost_groups = qla2x00_host_groups, 8119 8120 .supported_mode = MODE_INITIATOR, 8121 .track_queue_depth = 1, 8122 .cmd_size = sizeof(srb_t), 8123 }; 8124 8125 static const struct pci_error_handlers qla2xxx_err_handler = { 8126 .error_detected = qla2xxx_pci_error_detected, 8127 .mmio_enabled = qla2xxx_pci_mmio_enabled, 8128 .slot_reset = qla2xxx_pci_slot_reset, 8129 .resume = qla2xxx_pci_resume, 8130 .reset_prepare = qla_pci_reset_prepare, 8131 .reset_done = qla_pci_reset_done, 8132 }; 8133 8134 static const struct pci_device_id qla2xxx_pci_tbl[] = { 8135 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2100) }, 8136 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2200) }, 8137 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2300) }, 8138 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2312) }, 8139 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2322) }, 8140 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6312) }, 8141 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP6322) }, 8142 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2422) }, 8143 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2432) }, 8144 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8432) }, 8145 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5422) }, 8146 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP5432) }, 8147 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2532) }, 8148 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2031) }, 8149 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8001) }, 8150 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8021) }, 8151 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8031) }, 8152 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISPF001) }, 8153 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP8044) }, 8154 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2071) }, 8155 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2271) }, 8156 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2261) }, 8157 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2061) }, 8158 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2081) }, 8159 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2281) }, 8160 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2089) }, 8161 { PCI_DEVICE(PCI_VENDOR_ID_QLOGIC, PCI_DEVICE_ID_QLOGIC_ISP2289) }, 8162 { 0 }, 8163 }; 8164 MODULE_DEVICE_TABLE(pci, qla2xxx_pci_tbl); 8165 8166 static struct pci_driver qla2xxx_pci_driver = { 8167 .name = QLA2XXX_DRIVER_NAME, 8168 .id_table = qla2xxx_pci_tbl, 8169 .probe = qla2x00_probe_one, 8170 .remove = qla2x00_remove_one, 8171 .shutdown = qla2x00_shutdown, 8172 .err_handler = &qla2xxx_err_handler, 8173 }; 8174 8175 static const struct file_operations apidev_fops = { 8176 .owner = THIS_MODULE, 8177 .llseek = noop_llseek, 8178 }; 8179 8180 /** 8181 * qla2x00_module_init - Module initialization. 8182 **/ 8183 static int __init 8184 qla2x00_module_init(void) 8185 { 8186 int ret = 0; 8187 8188 BUILD_BUG_ON(sizeof(cmd_a64_entry_t) != 64); 8189 BUILD_BUG_ON(sizeof(cmd_entry_t) != 64); 8190 BUILD_BUG_ON(sizeof(cont_a64_entry_t) != 64); 8191 BUILD_BUG_ON(sizeof(cont_entry_t) != 64); 8192 BUILD_BUG_ON(sizeof(init_cb_t) != 96); 8193 BUILD_BUG_ON(sizeof(mrk_entry_t) != 64); 8194 BUILD_BUG_ON(sizeof(ms_iocb_entry_t) != 64); 8195 BUILD_BUG_ON(sizeof(request_t) != 64); 8196 BUILD_BUG_ON(sizeof(struct abort_entry_24xx) != 64); 8197 BUILD_BUG_ON(sizeof(struct abort_iocb_entry_fx00) != 64); 8198 BUILD_BUG_ON(sizeof(struct abts_entry_24xx) != 64); 8199 BUILD_BUG_ON(sizeof(struct access_chip_84xx) != 64); 8200 BUILD_BUG_ON(sizeof(struct access_chip_rsp_84xx) != 64); 8201 BUILD_BUG_ON(sizeof(struct cmd_bidir) != 64); 8202 BUILD_BUG_ON(sizeof(struct cmd_nvme) != 64); 8203 BUILD_BUG_ON(sizeof(struct cmd_type_6) != 64); 8204 BUILD_BUG_ON(sizeof(struct cmd_type_7) != 64); 8205 BUILD_BUG_ON(sizeof(struct cmd_type_7_fx00) != 64); 8206 BUILD_BUG_ON(sizeof(struct cmd_type_crc_2) != 64); 8207 BUILD_BUG_ON(sizeof(struct ct_entry_24xx) != 64); 8208 BUILD_BUG_ON(sizeof(struct ct_fdmi1_hba_attributes) != 2604); 8209 BUILD_BUG_ON(sizeof(struct ct_fdmi2_hba_attributes) != 4424); 8210 BUILD_BUG_ON(sizeof(struct ct_fdmi2_port_attributes) != 4164); 8211 BUILD_BUG_ON(sizeof(struct ct_fdmi_hba_attr) != 260); 8212 BUILD_BUG_ON(sizeof(struct ct_fdmi_port_attr) != 260); 8213 BUILD_BUG_ON(sizeof(struct ct_rsp_hdr) != 16); 8214 BUILD_BUG_ON(sizeof(struct ctio_crc2_to_fw) != 64); 8215 BUILD_BUG_ON(sizeof(struct device_reg_24xx) != 256); 8216 BUILD_BUG_ON(sizeof(struct device_reg_25xxmq) != 24); 8217 BUILD_BUG_ON(sizeof(struct device_reg_2xxx) != 256); 8218 BUILD_BUG_ON(sizeof(struct device_reg_82xx) != 1288); 8219 BUILD_BUG_ON(sizeof(struct device_reg_fx00) != 216); 8220 BUILD_BUG_ON(sizeof(struct els_entry_24xx) != 64); 8221 BUILD_BUG_ON(sizeof(struct els_sts_entry_24xx) != 64); 8222 BUILD_BUG_ON(sizeof(struct fxdisc_entry_fx00) != 64); 8223 BUILD_BUG_ON(sizeof(struct imm_ntfy_from_isp) != 64); 8224 BUILD_BUG_ON(sizeof(struct init_cb_24xx) != 128); 8225 BUILD_BUG_ON(sizeof(struct init_cb_81xx) != 128); 8226 BUILD_BUG_ON(sizeof(struct logio_entry_24xx) != 64); 8227 BUILD_BUG_ON(sizeof(struct mbx_entry) != 64); 8228 BUILD_BUG_ON(sizeof(struct mid_init_cb_24xx) != 5252); 8229 BUILD_BUG_ON(sizeof(struct mrk_entry_24xx) != 64); 8230 BUILD_BUG_ON(sizeof(struct nvram_24xx) != 512); 8231 BUILD_BUG_ON(sizeof(struct nvram_81xx) != 512); 8232 BUILD_BUG_ON(sizeof(struct pt_ls4_request) != 64); 8233 BUILD_BUG_ON(sizeof(struct pt_ls4_rx_unsol) != 64); 8234 BUILD_BUG_ON(sizeof(struct purex_entry_24xx) != 64); 8235 BUILD_BUG_ON(sizeof(struct qla2100_fw_dump) != 123634); 8236 BUILD_BUG_ON(sizeof(struct qla2300_fw_dump) != 136100); 8237 BUILD_BUG_ON(sizeof(struct qla24xx_fw_dump) != 37976); 8238 BUILD_BUG_ON(sizeof(struct qla25xx_fw_dump) != 39228); 8239 BUILD_BUG_ON(sizeof(struct qla2xxx_fce_chain) != 52); 8240 BUILD_BUG_ON(sizeof(struct qla2xxx_fw_dump) != 136172); 8241 BUILD_BUG_ON(sizeof(struct qla2xxx_mq_chain) != 524); 8242 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_chain) != 8); 8243 BUILD_BUG_ON(sizeof(struct qla2xxx_mqueue_header) != 12); 8244 BUILD_BUG_ON(sizeof(struct qla2xxx_offld_chain) != 24); 8245 BUILD_BUG_ON(sizeof(struct qla81xx_fw_dump) != 39420); 8246 BUILD_BUG_ON(sizeof(struct qla82xx_uri_data_desc) != 28); 8247 BUILD_BUG_ON(sizeof(struct qla82xx_uri_table_desc) != 32); 8248 BUILD_BUG_ON(sizeof(struct qla83xx_fw_dump) != 51196); 8249 BUILD_BUG_ON(sizeof(struct qla_fcp_prio_cfg) != FCP_PRIO_CFG_SIZE); 8250 BUILD_BUG_ON(sizeof(struct qla_fdt_layout) != 128); 8251 BUILD_BUG_ON(sizeof(struct qla_flt_header) != 8); 8252 BUILD_BUG_ON(sizeof(struct qla_flt_region) != 16); 8253 BUILD_BUG_ON(sizeof(struct qla_npiv_entry) != 24); 8254 BUILD_BUG_ON(sizeof(struct qla_npiv_header) != 16); 8255 BUILD_BUG_ON(sizeof(struct rdp_rsp_payload) != 336); 8256 BUILD_BUG_ON(sizeof(struct sns_cmd_pkt) != 2064); 8257 BUILD_BUG_ON(sizeof(struct sts_entry_24xx) != 64); 8258 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry) != 64); 8259 BUILD_BUG_ON(sizeof(struct tsk_mgmt_entry_fx00) != 64); 8260 BUILD_BUG_ON(sizeof(struct verify_chip_entry_84xx) != 64); 8261 BUILD_BUG_ON(sizeof(struct verify_chip_rsp_84xx) != 52); 8262 BUILD_BUG_ON(sizeof(struct vf_evfp_entry_24xx) != 56); 8263 BUILD_BUG_ON(sizeof(struct vp_config_entry_24xx) != 64); 8264 BUILD_BUG_ON(sizeof(struct vp_ctrl_entry_24xx) != 64); 8265 BUILD_BUG_ON(sizeof(struct vp_rpt_id_entry_24xx) != 64); 8266 BUILD_BUG_ON(sizeof(sts21_entry_t) != 64); 8267 BUILD_BUG_ON(sizeof(sts22_entry_t) != 64); 8268 BUILD_BUG_ON(sizeof(sts_cont_entry_t) != 64); 8269 BUILD_BUG_ON(sizeof(sts_entry_t) != 64); 8270 BUILD_BUG_ON(sizeof(sw_info_t) != 32); 8271 BUILD_BUG_ON(sizeof(target_id_t) != 2); 8272 8273 qla_trace_init(); 8274 8275 /* Allocate cache for SRBs. */ 8276 srb_cachep = kmem_cache_create("qla2xxx_srbs", sizeof(srb_t), 0, 8277 SLAB_HWCACHE_ALIGN, NULL); 8278 if (srb_cachep == NULL) { 8279 ql_log(ql_log_fatal, NULL, 0x0001, 8280 "Unable to allocate SRB cache...Failing load!.\n"); 8281 return -ENOMEM; 8282 } 8283 8284 /* Initialize target kmem_cache and mem_pools */ 8285 ret = qlt_init(); 8286 if (ret < 0) { 8287 goto destroy_cache; 8288 } else if (ret > 0) { 8289 /* 8290 * If initiator mode is explictly disabled by qlt_init(), 8291 * prevent scsi_transport_fc.c:fc_scsi_scan_rport() from 8292 * performing scsi_scan_target() during LOOP UP event. 8293 */ 8294 qla2xxx_transport_functions.disable_target_scan = 1; 8295 qla2xxx_transport_vport_functions.disable_target_scan = 1; 8296 } 8297 8298 /* Derive version string. */ 8299 strcpy(qla2x00_version_str, QLA2XXX_VERSION); 8300 if (ql2xextended_error_logging) 8301 strcat(qla2x00_version_str, "-debug"); 8302 if (ql2xextended_error_logging == 1) 8303 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK; 8304 8305 qla2xxx_transport_template = 8306 fc_attach_transport(&qla2xxx_transport_functions); 8307 if (!qla2xxx_transport_template) { 8308 ql_log(ql_log_fatal, NULL, 0x0002, 8309 "fc_attach_transport failed...Failing load!.\n"); 8310 ret = -ENODEV; 8311 goto qlt_exit; 8312 } 8313 8314 apidev_major = register_chrdev(0, QLA2XXX_APIDEV, &apidev_fops); 8315 if (apidev_major < 0) { 8316 ql_log(ql_log_fatal, NULL, 0x0003, 8317 "Unable to register char device %s.\n", QLA2XXX_APIDEV); 8318 } 8319 8320 qla2xxx_transport_vport_template = 8321 fc_attach_transport(&qla2xxx_transport_vport_functions); 8322 if (!qla2xxx_transport_vport_template) { 8323 ql_log(ql_log_fatal, NULL, 0x0004, 8324 "fc_attach_transport vport failed...Failing load!.\n"); 8325 ret = -ENODEV; 8326 goto unreg_chrdev; 8327 } 8328 ql_log(ql_log_info, NULL, 0x0005, 8329 "QLogic Fibre Channel HBA Driver: %s.\n", 8330 qla2x00_version_str); 8331 ret = pci_register_driver(&qla2xxx_pci_driver); 8332 if (ret) { 8333 ql_log(ql_log_fatal, NULL, 0x0006, 8334 "pci_register_driver failed...ret=%d Failing load!.\n", 8335 ret); 8336 goto release_vport_transport; 8337 } 8338 return ret; 8339 8340 release_vport_transport: 8341 fc_release_transport(qla2xxx_transport_vport_template); 8342 8343 unreg_chrdev: 8344 if (apidev_major >= 0) 8345 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8346 fc_release_transport(qla2xxx_transport_template); 8347 8348 qlt_exit: 8349 qlt_exit(); 8350 8351 destroy_cache: 8352 kmem_cache_destroy(srb_cachep); 8353 8354 qla_trace_uninit(); 8355 return ret; 8356 } 8357 8358 /** 8359 * qla2x00_module_exit - Module cleanup. 8360 **/ 8361 static void __exit 8362 qla2x00_module_exit(void) 8363 { 8364 pci_unregister_driver(&qla2xxx_pci_driver); 8365 qla2x00_release_firmware(); 8366 kmem_cache_destroy(ctx_cachep); 8367 fc_release_transport(qla2xxx_transport_vport_template); 8368 if (apidev_major >= 0) 8369 unregister_chrdev(apidev_major, QLA2XXX_APIDEV); 8370 fc_release_transport(qla2xxx_transport_template); 8371 qlt_exit(); 8372 kmem_cache_destroy(srb_cachep); 8373 qla_trace_uninit(); 8374 } 8375 8376 module_init(qla2x00_module_init); 8377 module_exit(qla2x00_module_exit); 8378 8379 MODULE_AUTHOR("QLogic Corporation"); 8380 MODULE_DESCRIPTION("QLogic Fibre Channel HBA Driver"); 8381 MODULE_LICENSE("GPL"); 8382 MODULE_FIRMWARE(FW_FILE_ISP21XX); 8383 MODULE_FIRMWARE(FW_FILE_ISP22XX); 8384 MODULE_FIRMWARE(FW_FILE_ISP2300); 8385 MODULE_FIRMWARE(FW_FILE_ISP2322); 8386 MODULE_FIRMWARE(FW_FILE_ISP24XX); 8387 MODULE_FIRMWARE(FW_FILE_ISP25XX); 8388