1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * QLogic Fibre Channel HBA Driver 4 * Copyright (c) 2003-2014 QLogic Corporation 5 */ 6 #include "qla_def.h" 7 8 #include <linux/delay.h> 9 #include <linux/slab.h> 10 #include <linux/vmalloc.h> 11 #include <linux/uaccess.h> 12 13 /* 14 * NVRAM support routines 15 */ 16 17 /** 18 * qla2x00_lock_nvram_access() - 19 * @ha: HA context 20 */ 21 static void 22 qla2x00_lock_nvram_access(struct qla_hw_data *ha) 23 { 24 uint16_t data; 25 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 26 27 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 28 data = rd_reg_word(®->nvram); 29 while (data & NVR_BUSY) { 30 udelay(100); 31 data = rd_reg_word(®->nvram); 32 } 33 34 /* Lock resource */ 35 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); 36 rd_reg_word(®->u.isp2300.host_semaphore); 37 udelay(5); 38 data = rd_reg_word(®->u.isp2300.host_semaphore); 39 while ((data & BIT_0) == 0) { 40 /* Lock failed */ 41 udelay(100); 42 wrt_reg_word(®->u.isp2300.host_semaphore, 0x1); 43 rd_reg_word(®->u.isp2300.host_semaphore); 44 udelay(5); 45 data = rd_reg_word(®->u.isp2300.host_semaphore); 46 } 47 } 48 } 49 50 /** 51 * qla2x00_unlock_nvram_access() - 52 * @ha: HA context 53 */ 54 static void 55 qla2x00_unlock_nvram_access(struct qla_hw_data *ha) 56 { 57 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 58 59 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha)) { 60 wrt_reg_word(®->u.isp2300.host_semaphore, 0); 61 rd_reg_word(®->u.isp2300.host_semaphore); 62 } 63 } 64 65 /** 66 * qla2x00_nv_write() - Prepare for NVRAM read/write operation. 67 * @ha: HA context 68 * @data: Serial interface selector 69 */ 70 static void 71 qla2x00_nv_write(struct qla_hw_data *ha, uint16_t data) 72 { 73 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 74 75 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 76 rd_reg_word(®->nvram); /* PCI Posting. */ 77 NVRAM_DELAY(); 78 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_CLOCK | 79 NVR_WRT_ENABLE); 80 rd_reg_word(®->nvram); /* PCI Posting. */ 81 NVRAM_DELAY(); 82 wrt_reg_word(®->nvram, data | NVR_SELECT | NVR_WRT_ENABLE); 83 rd_reg_word(®->nvram); /* PCI Posting. */ 84 NVRAM_DELAY(); 85 } 86 87 /** 88 * qla2x00_nvram_request() - Sends read command to NVRAM and gets data from 89 * NVRAM. 90 * @ha: HA context 91 * @nv_cmd: NVRAM command 92 * 93 * Bit definitions for NVRAM command: 94 * 95 * Bit 26 = start bit 96 * Bit 25, 24 = opcode 97 * Bit 23-16 = address 98 * Bit 15-0 = write data 99 * 100 * Returns the word read from nvram @addr. 101 */ 102 static uint16_t 103 qla2x00_nvram_request(struct qla_hw_data *ha, uint32_t nv_cmd) 104 { 105 uint8_t cnt; 106 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 107 uint16_t data = 0; 108 uint16_t reg_data; 109 110 /* Send command to NVRAM. */ 111 nv_cmd <<= 5; 112 for (cnt = 0; cnt < 11; cnt++) { 113 if (nv_cmd & BIT_31) 114 qla2x00_nv_write(ha, NVR_DATA_OUT); 115 else 116 qla2x00_nv_write(ha, 0); 117 nv_cmd <<= 1; 118 } 119 120 /* Read data from NVRAM. */ 121 for (cnt = 0; cnt < 16; cnt++) { 122 wrt_reg_word(®->nvram, NVR_SELECT | NVR_CLOCK); 123 rd_reg_word(®->nvram); /* PCI Posting. */ 124 NVRAM_DELAY(); 125 data <<= 1; 126 reg_data = rd_reg_word(®->nvram); 127 if (reg_data & NVR_DATA_IN) 128 data |= BIT_0; 129 wrt_reg_word(®->nvram, NVR_SELECT); 130 rd_reg_word(®->nvram); /* PCI Posting. */ 131 NVRAM_DELAY(); 132 } 133 134 /* Deselect chip. */ 135 wrt_reg_word(®->nvram, NVR_DESELECT); 136 rd_reg_word(®->nvram); /* PCI Posting. */ 137 NVRAM_DELAY(); 138 139 return data; 140 } 141 142 143 /** 144 * qla2x00_get_nvram_word() - Calculates word position in NVRAM and calls the 145 * request routine to get the word from NVRAM. 146 * @ha: HA context 147 * @addr: Address in NVRAM to read 148 * 149 * Returns the word read from nvram @addr. 150 */ 151 static uint16_t 152 qla2x00_get_nvram_word(struct qla_hw_data *ha, uint32_t addr) 153 { 154 uint16_t data; 155 uint32_t nv_cmd; 156 157 nv_cmd = addr << 16; 158 nv_cmd |= NV_READ_OP; 159 data = qla2x00_nvram_request(ha, nv_cmd); 160 161 return (data); 162 } 163 164 /** 165 * qla2x00_nv_deselect() - Deselect NVRAM operations. 166 * @ha: HA context 167 */ 168 static void 169 qla2x00_nv_deselect(struct qla_hw_data *ha) 170 { 171 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 172 173 wrt_reg_word(®->nvram, NVR_DESELECT); 174 rd_reg_word(®->nvram); /* PCI Posting. */ 175 NVRAM_DELAY(); 176 } 177 178 /** 179 * qla2x00_write_nvram_word() - Write NVRAM data. 180 * @ha: HA context 181 * @addr: Address in NVRAM to write 182 * @data: word to program 183 */ 184 static void 185 qla2x00_write_nvram_word(struct qla_hw_data *ha, uint32_t addr, __le16 data) 186 { 187 int count; 188 uint16_t word; 189 uint32_t nv_cmd, wait_cnt; 190 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 191 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 192 193 qla2x00_nv_write(ha, NVR_DATA_OUT); 194 qla2x00_nv_write(ha, 0); 195 qla2x00_nv_write(ha, 0); 196 197 for (word = 0; word < 8; word++) 198 qla2x00_nv_write(ha, NVR_DATA_OUT); 199 200 qla2x00_nv_deselect(ha); 201 202 /* Write data */ 203 nv_cmd = (addr << 16) | NV_WRITE_OP; 204 nv_cmd |= (__force u16)data; 205 nv_cmd <<= 5; 206 for (count = 0; count < 27; count++) { 207 if (nv_cmd & BIT_31) 208 qla2x00_nv_write(ha, NVR_DATA_OUT); 209 else 210 qla2x00_nv_write(ha, 0); 211 212 nv_cmd <<= 1; 213 } 214 215 qla2x00_nv_deselect(ha); 216 217 /* Wait for NVRAM to become ready */ 218 wrt_reg_word(®->nvram, NVR_SELECT); 219 rd_reg_word(®->nvram); /* PCI Posting. */ 220 wait_cnt = NVR_WAIT_CNT; 221 do { 222 if (!--wait_cnt) { 223 ql_dbg(ql_dbg_user, vha, 0x708d, 224 "NVRAM didn't go ready...\n"); 225 break; 226 } 227 NVRAM_DELAY(); 228 word = rd_reg_word(®->nvram); 229 } while ((word & NVR_DATA_IN) == 0); 230 231 qla2x00_nv_deselect(ha); 232 233 /* Disable writes */ 234 qla2x00_nv_write(ha, NVR_DATA_OUT); 235 for (count = 0; count < 10; count++) 236 qla2x00_nv_write(ha, 0); 237 238 qla2x00_nv_deselect(ha); 239 } 240 241 static int 242 qla2x00_write_nvram_word_tmo(struct qla_hw_data *ha, uint32_t addr, 243 __le16 data, uint32_t tmo) 244 { 245 int ret, count; 246 uint16_t word; 247 uint32_t nv_cmd; 248 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 249 250 ret = QLA_SUCCESS; 251 252 qla2x00_nv_write(ha, NVR_DATA_OUT); 253 qla2x00_nv_write(ha, 0); 254 qla2x00_nv_write(ha, 0); 255 256 for (word = 0; word < 8; word++) 257 qla2x00_nv_write(ha, NVR_DATA_OUT); 258 259 qla2x00_nv_deselect(ha); 260 261 /* Write data */ 262 nv_cmd = (addr << 16) | NV_WRITE_OP; 263 nv_cmd |= (__force u16)data; 264 nv_cmd <<= 5; 265 for (count = 0; count < 27; count++) { 266 if (nv_cmd & BIT_31) 267 qla2x00_nv_write(ha, NVR_DATA_OUT); 268 else 269 qla2x00_nv_write(ha, 0); 270 271 nv_cmd <<= 1; 272 } 273 274 qla2x00_nv_deselect(ha); 275 276 /* Wait for NVRAM to become ready */ 277 wrt_reg_word(®->nvram, NVR_SELECT); 278 rd_reg_word(®->nvram); /* PCI Posting. */ 279 do { 280 NVRAM_DELAY(); 281 word = rd_reg_word(®->nvram); 282 if (!--tmo) { 283 ret = QLA_FUNCTION_FAILED; 284 break; 285 } 286 } while ((word & NVR_DATA_IN) == 0); 287 288 qla2x00_nv_deselect(ha); 289 290 /* Disable writes */ 291 qla2x00_nv_write(ha, NVR_DATA_OUT); 292 for (count = 0; count < 10; count++) 293 qla2x00_nv_write(ha, 0); 294 295 qla2x00_nv_deselect(ha); 296 297 return ret; 298 } 299 300 /** 301 * qla2x00_clear_nvram_protection() - 302 * @ha: HA context 303 */ 304 static int 305 qla2x00_clear_nvram_protection(struct qla_hw_data *ha) 306 { 307 int ret, stat; 308 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 309 uint32_t word, wait_cnt; 310 __le16 wprot, wprot_old; 311 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 312 313 /* Clear NVRAM write protection. */ 314 ret = QLA_FUNCTION_FAILED; 315 316 wprot_old = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 317 stat = qla2x00_write_nvram_word_tmo(ha, ha->nvram_base, 318 cpu_to_le16(0x1234), 100000); 319 wprot = cpu_to_le16(qla2x00_get_nvram_word(ha, ha->nvram_base)); 320 if (stat != QLA_SUCCESS || wprot != cpu_to_le16(0x1234)) { 321 /* Write enable. */ 322 qla2x00_nv_write(ha, NVR_DATA_OUT); 323 qla2x00_nv_write(ha, 0); 324 qla2x00_nv_write(ha, 0); 325 for (word = 0; word < 8; word++) 326 qla2x00_nv_write(ha, NVR_DATA_OUT); 327 328 qla2x00_nv_deselect(ha); 329 330 /* Enable protection register. */ 331 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 332 qla2x00_nv_write(ha, NVR_PR_ENABLE); 333 qla2x00_nv_write(ha, NVR_PR_ENABLE); 334 for (word = 0; word < 8; word++) 335 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 336 337 qla2x00_nv_deselect(ha); 338 339 /* Clear protection register (ffff is cleared). */ 340 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 341 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 342 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 343 for (word = 0; word < 8; word++) 344 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 345 346 qla2x00_nv_deselect(ha); 347 348 /* Wait for NVRAM to become ready. */ 349 wrt_reg_word(®->nvram, NVR_SELECT); 350 rd_reg_word(®->nvram); /* PCI Posting. */ 351 wait_cnt = NVR_WAIT_CNT; 352 do { 353 if (!--wait_cnt) { 354 ql_dbg(ql_dbg_user, vha, 0x708e, 355 "NVRAM didn't go ready...\n"); 356 break; 357 } 358 NVRAM_DELAY(); 359 word = rd_reg_word(®->nvram); 360 } while ((word & NVR_DATA_IN) == 0); 361 362 if (wait_cnt) 363 ret = QLA_SUCCESS; 364 } else 365 qla2x00_write_nvram_word(ha, ha->nvram_base, wprot_old); 366 367 return ret; 368 } 369 370 static void 371 qla2x00_set_nvram_protection(struct qla_hw_data *ha, int stat) 372 { 373 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 374 uint32_t word, wait_cnt; 375 scsi_qla_host_t *vha = pci_get_drvdata(ha->pdev); 376 377 if (stat != QLA_SUCCESS) 378 return; 379 380 /* Set NVRAM write protection. */ 381 /* Write enable. */ 382 qla2x00_nv_write(ha, NVR_DATA_OUT); 383 qla2x00_nv_write(ha, 0); 384 qla2x00_nv_write(ha, 0); 385 for (word = 0; word < 8; word++) 386 qla2x00_nv_write(ha, NVR_DATA_OUT); 387 388 qla2x00_nv_deselect(ha); 389 390 /* Enable protection register. */ 391 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 392 qla2x00_nv_write(ha, NVR_PR_ENABLE); 393 qla2x00_nv_write(ha, NVR_PR_ENABLE); 394 for (word = 0; word < 8; word++) 395 qla2x00_nv_write(ha, NVR_DATA_OUT | NVR_PR_ENABLE); 396 397 qla2x00_nv_deselect(ha); 398 399 /* Enable protection register. */ 400 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 401 qla2x00_nv_write(ha, NVR_PR_ENABLE); 402 qla2x00_nv_write(ha, NVR_PR_ENABLE | NVR_DATA_OUT); 403 for (word = 0; word < 8; word++) 404 qla2x00_nv_write(ha, NVR_PR_ENABLE); 405 406 qla2x00_nv_deselect(ha); 407 408 /* Wait for NVRAM to become ready. */ 409 wrt_reg_word(®->nvram, NVR_SELECT); 410 rd_reg_word(®->nvram); /* PCI Posting. */ 411 wait_cnt = NVR_WAIT_CNT; 412 do { 413 if (!--wait_cnt) { 414 ql_dbg(ql_dbg_user, vha, 0x708f, 415 "NVRAM didn't go ready...\n"); 416 break; 417 } 418 NVRAM_DELAY(); 419 word = rd_reg_word(®->nvram); 420 } while ((word & NVR_DATA_IN) == 0); 421 } 422 423 424 /*****************************************************************************/ 425 /* Flash Manipulation Routines */ 426 /*****************************************************************************/ 427 428 static inline uint32_t 429 flash_conf_addr(struct qla_hw_data *ha, uint32_t faddr) 430 { 431 return ha->flash_conf_off + faddr; 432 } 433 434 static inline uint32_t 435 flash_data_addr(struct qla_hw_data *ha, uint32_t faddr) 436 { 437 return ha->flash_data_off + faddr; 438 } 439 440 static inline uint32_t 441 nvram_conf_addr(struct qla_hw_data *ha, uint32_t naddr) 442 { 443 return ha->nvram_conf_off + naddr; 444 } 445 446 static inline uint32_t 447 nvram_data_addr(struct qla_hw_data *ha, uint32_t naddr) 448 { 449 return ha->nvram_data_off + naddr; 450 } 451 452 static int 453 qla24xx_read_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t *data) 454 { 455 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 456 ulong cnt = 30000; 457 458 wrt_reg_dword(®->flash_addr, addr & ~FARX_DATA_FLAG); 459 460 while (cnt--) { 461 if (rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG) { 462 *data = rd_reg_dword(®->flash_data); 463 return QLA_SUCCESS; 464 } 465 udelay(10); 466 cond_resched(); 467 } 468 469 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090, 470 "Flash read dword at %x timeout.\n", addr); 471 *data = 0xDEADDEAD; 472 return QLA_FUNCTION_TIMEOUT; 473 } 474 475 int 476 qla24xx_read_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 477 uint32_t dwords) 478 { 479 ulong i; 480 int ret = QLA_SUCCESS; 481 struct qla_hw_data *ha = vha->hw; 482 483 /* Dword reads to flash. */ 484 faddr = flash_data_addr(ha, faddr); 485 for (i = 0; i < dwords; i++, faddr++, dwptr++) { 486 ret = qla24xx_read_flash_dword(ha, faddr, dwptr); 487 if (ret != QLA_SUCCESS) 488 break; 489 cpu_to_le32s(dwptr); 490 } 491 492 return ret; 493 } 494 495 static int 496 qla24xx_write_flash_dword(struct qla_hw_data *ha, uint32_t addr, uint32_t data) 497 { 498 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 499 ulong cnt = 500000; 500 501 wrt_reg_dword(®->flash_data, data); 502 wrt_reg_dword(®->flash_addr, addr | FARX_DATA_FLAG); 503 504 while (cnt--) { 505 if (!(rd_reg_dword(®->flash_addr) & FARX_DATA_FLAG)) 506 return QLA_SUCCESS; 507 udelay(10); 508 cond_resched(); 509 } 510 511 ql_log(ql_log_warn, pci_get_drvdata(ha->pdev), 0x7090, 512 "Flash write dword at %x timeout.\n", addr); 513 return QLA_FUNCTION_TIMEOUT; 514 } 515 516 static void 517 qla24xx_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 518 uint8_t *flash_id) 519 { 520 uint32_t faddr, ids = 0; 521 522 *man_id = *flash_id = 0; 523 524 faddr = flash_conf_addr(ha, 0x03ab); 525 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) { 526 *man_id = LSB(ids); 527 *flash_id = MSB(ids); 528 } 529 530 /* Check if man_id and flash_id are valid. */ 531 if (ids != 0xDEADDEAD && (*man_id == 0 || *flash_id == 0)) { 532 /* Read information using 0x9f opcode 533 * Device ID, Mfg ID would be read in the format: 534 * <Ext Dev Info><Device ID Part2><Device ID Part 1><Mfg ID> 535 * Example: ATMEL 0x00 01 45 1F 536 * Extract MFG and Dev ID from last two bytes. 537 */ 538 faddr = flash_conf_addr(ha, 0x009f); 539 if (!qla24xx_read_flash_dword(ha, faddr, &ids)) { 540 *man_id = LSB(ids); 541 *flash_id = MSB(ids); 542 } 543 } 544 } 545 546 static int 547 qla2xxx_find_flt_start(scsi_qla_host_t *vha, uint32_t *start) 548 { 549 const char *loc, *locations[] = { "DEF", "PCI" }; 550 uint32_t pcihdr, pcids; 551 uint16_t cnt, chksum; 552 __le16 *wptr; 553 struct qla_hw_data *ha = vha->hw; 554 struct req_que *req = ha->req_q_map[0]; 555 struct qla_flt_location *fltl = (void *)req->ring; 556 uint32_t *dcode = (uint32_t *)req->ring; 557 uint8_t *buf = (void *)req->ring, *bcode, last_image; 558 int rc; 559 560 /* 561 * FLT-location structure resides after the last PCI region. 562 */ 563 564 /* Begin with sane defaults. */ 565 loc = locations[0]; 566 *start = 0; 567 if (IS_QLA24XX_TYPE(ha)) 568 *start = FA_FLASH_LAYOUT_ADDR_24; 569 else if (IS_QLA25XX(ha)) 570 *start = FA_FLASH_LAYOUT_ADDR; 571 else if (IS_QLA81XX(ha)) 572 *start = FA_FLASH_LAYOUT_ADDR_81; 573 else if (IS_P3P_TYPE(ha)) { 574 *start = FA_FLASH_LAYOUT_ADDR_82; 575 goto end; 576 } else if (IS_QLA83XX(ha) || IS_QLA27XX(ha)) { 577 *start = FA_FLASH_LAYOUT_ADDR_83; 578 goto end; 579 } else if (IS_QLA28XX(ha)) { 580 *start = FA_FLASH_LAYOUT_ADDR_28; 581 goto end; 582 } 583 584 /* Begin with first PCI expansion ROM header. */ 585 pcihdr = 0; 586 do { 587 /* Verify PCI expansion ROM header. */ 588 rc = qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 589 if (rc) { 590 ql_log(ql_log_info, vha, 0x016d, 591 "Unable to read PCI Expansion Rom Header (%x).\n", rc); 592 return QLA_FUNCTION_FAILED; 593 } 594 bcode = buf + (pcihdr % 4); 595 if (bcode[0x0] != 0x55 || bcode[0x1] != 0xaa) 596 goto end; 597 598 /* Locate PCI data structure. */ 599 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 600 rc = qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 601 if (rc) { 602 ql_log(ql_log_info, vha, 0x0179, 603 "Unable to read PCI Data Structure (%x).\n", rc); 604 return QLA_FUNCTION_FAILED; 605 } 606 bcode = buf + (pcihdr % 4); 607 608 /* Validate signature of PCI data structure. */ 609 if (bcode[0x0] != 'P' || bcode[0x1] != 'C' || 610 bcode[0x2] != 'I' || bcode[0x3] != 'R') 611 goto end; 612 613 last_image = bcode[0x15] & BIT_7; 614 615 /* Locate next PCI expansion ROM. */ 616 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 617 } while (!last_image); 618 619 /* Now verify FLT-location structure. */ 620 rc = qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, sizeof(*fltl) >> 2); 621 if (rc) { 622 ql_log(ql_log_info, vha, 0x017a, 623 "Unable to read FLT (%x).\n", rc); 624 return QLA_FUNCTION_FAILED; 625 } 626 if (memcmp(fltl->sig, "QFLT", 4)) 627 goto end; 628 629 wptr = (__force __le16 *)req->ring; 630 cnt = sizeof(*fltl) / sizeof(*wptr); 631 for (chksum = 0; cnt--; wptr++) 632 chksum += le16_to_cpu(*wptr); 633 if (chksum) { 634 ql_log(ql_log_fatal, vha, 0x0045, 635 "Inconsistent FLTL detected: checksum=0x%x.\n", chksum); 636 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010e, 637 fltl, sizeof(*fltl)); 638 return QLA_FUNCTION_FAILED; 639 } 640 641 /* Good data. Use specified location. */ 642 loc = locations[1]; 643 *start = (le16_to_cpu(fltl->start_hi) << 16 | 644 le16_to_cpu(fltl->start_lo)) >> 2; 645 end: 646 ql_dbg(ql_dbg_init, vha, 0x0046, 647 "FLTL[%s] = 0x%x.\n", 648 loc, *start); 649 return QLA_SUCCESS; 650 } 651 652 static void 653 qla2xxx_get_flt_info(scsi_qla_host_t *vha, uint32_t flt_addr) 654 { 655 const char *locations[] = { "DEF", "FLT" }, *loc = locations[1]; 656 const uint32_t def_fw[] = 657 { FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR, FA_RISC_CODE_ADDR_81 }; 658 const uint32_t def_boot[] = 659 { FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR, FA_BOOT_CODE_ADDR_81 }; 660 const uint32_t def_vpd_nvram[] = 661 { FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR, FA_VPD_NVRAM_ADDR_81 }; 662 const uint32_t def_vpd0[] = 663 { 0, 0, FA_VPD0_ADDR_81 }; 664 const uint32_t def_vpd1[] = 665 { 0, 0, FA_VPD1_ADDR_81 }; 666 const uint32_t def_nvram0[] = 667 { 0, 0, FA_NVRAM0_ADDR_81 }; 668 const uint32_t def_nvram1[] = 669 { 0, 0, FA_NVRAM1_ADDR_81 }; 670 const uint32_t def_fdt[] = 671 { FA_FLASH_DESCR_ADDR_24, FA_FLASH_DESCR_ADDR, 672 FA_FLASH_DESCR_ADDR_81 }; 673 const uint32_t def_npiv_conf0[] = 674 { FA_NPIV_CONF0_ADDR_24, FA_NPIV_CONF0_ADDR, 675 FA_NPIV_CONF0_ADDR_81 }; 676 const uint32_t def_npiv_conf1[] = 677 { FA_NPIV_CONF1_ADDR_24, FA_NPIV_CONF1_ADDR, 678 FA_NPIV_CONF1_ADDR_81 }; 679 const uint32_t fcp_prio_cfg0[] = 680 { FA_FCP_PRIO0_ADDR, FA_FCP_PRIO0_ADDR_25, 681 0 }; 682 const uint32_t fcp_prio_cfg1[] = 683 { FA_FCP_PRIO1_ADDR, FA_FCP_PRIO1_ADDR_25, 684 0 }; 685 686 struct qla_hw_data *ha = vha->hw; 687 uint32_t def = IS_QLA81XX(ha) ? 2 : IS_QLA25XX(ha) ? 1 : 0; 688 struct qla_flt_header *flt = ha->flt; 689 struct qla_flt_region *region = &flt->region[0]; 690 __le16 *wptr; 691 uint16_t cnt, chksum; 692 uint32_t start; 693 694 /* Assign FCP prio region since older adapters may not have FLT, or 695 FCP prio region in it's FLT. 696 */ 697 ha->flt_region_fcp_prio = (ha->port_no == 0) ? 698 fcp_prio_cfg0[def] : fcp_prio_cfg1[def]; 699 700 ha->flt_region_flt = flt_addr; 701 wptr = (__force __le16 *)ha->flt; 702 ha->isp_ops->read_optrom(vha, flt, flt_addr << 2, 703 (sizeof(struct qla_flt_header) + FLT_REGIONS_SIZE)); 704 705 if (le16_to_cpu(*wptr) == 0xffff) 706 goto no_flash_data; 707 if (flt->version != cpu_to_le16(1)) { 708 ql_log(ql_log_warn, vha, 0x0047, 709 "Unsupported FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", 710 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 711 le16_to_cpu(flt->checksum)); 712 goto no_flash_data; 713 } 714 715 cnt = (sizeof(*flt) + le16_to_cpu(flt->length)) / sizeof(*wptr); 716 for (chksum = 0; cnt--; wptr++) 717 chksum += le16_to_cpu(*wptr); 718 if (chksum) { 719 ql_log(ql_log_fatal, vha, 0x0048, 720 "Inconsistent FLT detected: version=0x%x length=0x%x checksum=0x%x.\n", 721 le16_to_cpu(flt->version), le16_to_cpu(flt->length), 722 le16_to_cpu(flt->checksum)); 723 goto no_flash_data; 724 } 725 726 cnt = le16_to_cpu(flt->length) / sizeof(*region); 727 for ( ; cnt; cnt--, region++) { 728 /* Store addresses as DWORD offsets. */ 729 start = le32_to_cpu(region->start) >> 2; 730 ql_dbg(ql_dbg_init, vha, 0x0049, 731 "FLT[%#x]: start=%#x end=%#x size=%#x.\n", 732 le16_to_cpu(region->code), start, 733 le32_to_cpu(region->end) >> 2, 734 le32_to_cpu(region->size) >> 2); 735 if (region->attribute) 736 ql_log(ql_dbg_init, vha, 0xffff, 737 "Region %x is secure\n", region->code); 738 739 switch (le16_to_cpu(region->code)) { 740 case FLT_REG_FCOE_FW: 741 if (!IS_QLA8031(ha)) 742 break; 743 ha->flt_region_fw = start; 744 break; 745 case FLT_REG_FW: 746 if (IS_QLA8031(ha)) 747 break; 748 ha->flt_region_fw = start; 749 break; 750 case FLT_REG_BOOT_CODE: 751 ha->flt_region_boot = start; 752 break; 753 case FLT_REG_VPD_0: 754 if (IS_QLA8031(ha)) 755 break; 756 ha->flt_region_vpd_nvram = start; 757 if (IS_P3P_TYPE(ha)) 758 break; 759 if (ha->port_no == 0) 760 ha->flt_region_vpd = start; 761 break; 762 case FLT_REG_VPD_1: 763 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha)) 764 break; 765 if (ha->port_no == 1) 766 ha->flt_region_vpd = start; 767 break; 768 case FLT_REG_VPD_2: 769 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 770 break; 771 if (ha->port_no == 2) 772 ha->flt_region_vpd = start; 773 break; 774 case FLT_REG_VPD_3: 775 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 776 break; 777 if (ha->port_no == 3) 778 ha->flt_region_vpd = start; 779 break; 780 case FLT_REG_NVRAM_0: 781 if (IS_QLA8031(ha)) 782 break; 783 if (ha->port_no == 0) 784 ha->flt_region_nvram = start; 785 break; 786 case FLT_REG_NVRAM_1: 787 if (IS_QLA8031(ha)) 788 break; 789 if (ha->port_no == 1) 790 ha->flt_region_nvram = start; 791 break; 792 case FLT_REG_NVRAM_2: 793 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 794 break; 795 if (ha->port_no == 2) 796 ha->flt_region_nvram = start; 797 break; 798 case FLT_REG_NVRAM_3: 799 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 800 break; 801 if (ha->port_no == 3) 802 ha->flt_region_nvram = start; 803 break; 804 case FLT_REG_FDT: 805 ha->flt_region_fdt = start; 806 break; 807 case FLT_REG_NPIV_CONF_0: 808 if (ha->port_no == 0) 809 ha->flt_region_npiv_conf = start; 810 break; 811 case FLT_REG_NPIV_CONF_1: 812 if (ha->port_no == 1) 813 ha->flt_region_npiv_conf = start; 814 break; 815 case FLT_REG_GOLD_FW: 816 ha->flt_region_gold_fw = start; 817 break; 818 case FLT_REG_FCP_PRIO_0: 819 if (ha->port_no == 0) 820 ha->flt_region_fcp_prio = start; 821 break; 822 case FLT_REG_FCP_PRIO_1: 823 if (ha->port_no == 1) 824 ha->flt_region_fcp_prio = start; 825 break; 826 case FLT_REG_BOOT_CODE_82XX: 827 ha->flt_region_boot = start; 828 break; 829 case FLT_REG_BOOT_CODE_8044: 830 if (IS_QLA8044(ha)) 831 ha->flt_region_boot = start; 832 break; 833 case FLT_REG_FW_82XX: 834 ha->flt_region_fw = start; 835 break; 836 case FLT_REG_CNA_FW: 837 if (IS_CNA_CAPABLE(ha)) 838 ha->flt_region_fw = start; 839 break; 840 case FLT_REG_GOLD_FW_82XX: 841 ha->flt_region_gold_fw = start; 842 break; 843 case FLT_REG_BOOTLOAD_82XX: 844 ha->flt_region_bootload = start; 845 break; 846 case FLT_REG_VPD_8XXX: 847 if (IS_CNA_CAPABLE(ha)) 848 ha->flt_region_vpd = start; 849 break; 850 case FLT_REG_FCOE_NVRAM_0: 851 if (!(IS_QLA8031(ha) || IS_QLA8044(ha))) 852 break; 853 if (ha->port_no == 0) 854 ha->flt_region_nvram = start; 855 break; 856 case FLT_REG_FCOE_NVRAM_1: 857 if (!(IS_QLA8031(ha) || IS_QLA8044(ha))) 858 break; 859 if (ha->port_no == 1) 860 ha->flt_region_nvram = start; 861 break; 862 case FLT_REG_IMG_PRI_27XX: 863 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 864 ha->flt_region_img_status_pri = start; 865 break; 866 case FLT_REG_IMG_SEC_27XX: 867 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 868 ha->flt_region_img_status_sec = start; 869 break; 870 case FLT_REG_FW_SEC_27XX: 871 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 872 ha->flt_region_fw_sec = start; 873 break; 874 case FLT_REG_BOOTLOAD_SEC_27XX: 875 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 876 ha->flt_region_boot_sec = start; 877 break; 878 case FLT_REG_AUX_IMG_PRI_28XX: 879 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 880 ha->flt_region_aux_img_status_pri = start; 881 break; 882 case FLT_REG_AUX_IMG_SEC_28XX: 883 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 884 ha->flt_region_aux_img_status_sec = start; 885 break; 886 case FLT_REG_NVRAM_SEC_28XX_0: 887 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 888 if (ha->port_no == 0) 889 ha->flt_region_nvram_sec = start; 890 break; 891 case FLT_REG_NVRAM_SEC_28XX_1: 892 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 893 if (ha->port_no == 1) 894 ha->flt_region_nvram_sec = start; 895 break; 896 case FLT_REG_NVRAM_SEC_28XX_2: 897 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 898 if (ha->port_no == 2) 899 ha->flt_region_nvram_sec = start; 900 break; 901 case FLT_REG_NVRAM_SEC_28XX_3: 902 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 903 if (ha->port_no == 3) 904 ha->flt_region_nvram_sec = start; 905 break; 906 case FLT_REG_VPD_SEC_27XX_0: 907 case FLT_REG_VPD_SEC_28XX_0: 908 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 909 ha->flt_region_vpd_nvram_sec = start; 910 if (ha->port_no == 0) 911 ha->flt_region_vpd_sec = start; 912 } 913 break; 914 case FLT_REG_VPD_SEC_27XX_1: 915 case FLT_REG_VPD_SEC_28XX_1: 916 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 917 if (ha->port_no == 1) 918 ha->flt_region_vpd_sec = start; 919 break; 920 case FLT_REG_VPD_SEC_27XX_2: 921 case FLT_REG_VPD_SEC_28XX_2: 922 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 923 if (ha->port_no == 2) 924 ha->flt_region_vpd_sec = start; 925 break; 926 case FLT_REG_VPD_SEC_27XX_3: 927 case FLT_REG_VPD_SEC_28XX_3: 928 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 929 if (ha->port_no == 3) 930 ha->flt_region_vpd_sec = start; 931 break; 932 } 933 } 934 goto done; 935 936 no_flash_data: 937 /* Use hardcoded defaults. */ 938 loc = locations[0]; 939 ha->flt_region_fw = def_fw[def]; 940 ha->flt_region_boot = def_boot[def]; 941 ha->flt_region_vpd_nvram = def_vpd_nvram[def]; 942 ha->flt_region_vpd = (ha->port_no == 0) ? 943 def_vpd0[def] : def_vpd1[def]; 944 ha->flt_region_nvram = (ha->port_no == 0) ? 945 def_nvram0[def] : def_nvram1[def]; 946 ha->flt_region_fdt = def_fdt[def]; 947 ha->flt_region_npiv_conf = (ha->port_no == 0) ? 948 def_npiv_conf0[def] : def_npiv_conf1[def]; 949 done: 950 ql_dbg(ql_dbg_init, vha, 0x004a, 951 "FLT[%s]: boot=0x%x fw=0x%x vpd_nvram=0x%x vpd=0x%x nvram=0x%x " 952 "fdt=0x%x flt=0x%x npiv=0x%x fcp_prif_cfg=0x%x.\n", 953 loc, ha->flt_region_boot, ha->flt_region_fw, 954 ha->flt_region_vpd_nvram, ha->flt_region_vpd, ha->flt_region_nvram, 955 ha->flt_region_fdt, ha->flt_region_flt, ha->flt_region_npiv_conf, 956 ha->flt_region_fcp_prio); 957 } 958 959 static void 960 qla2xxx_get_fdt_info(scsi_qla_host_t *vha) 961 { 962 #define FLASH_BLK_SIZE_4K 0x1000 963 #define FLASH_BLK_SIZE_32K 0x8000 964 #define FLASH_BLK_SIZE_64K 0x10000 965 const char *loc, *locations[] = { "MID", "FDT" }; 966 struct qla_hw_data *ha = vha->hw; 967 struct req_que *req = ha->req_q_map[0]; 968 uint16_t cnt, chksum; 969 __le16 *wptr = (__force __le16 *)req->ring; 970 struct qla_fdt_layout *fdt = (struct qla_fdt_layout *)req->ring; 971 uint8_t man_id, flash_id; 972 uint16_t mid = 0, fid = 0; 973 974 ha->isp_ops->read_optrom(vha, fdt, ha->flt_region_fdt << 2, 975 OPTROM_BURST_DWORDS); 976 if (le16_to_cpu(*wptr) == 0xffff) 977 goto no_flash_data; 978 if (memcmp(fdt->sig, "QLID", 4)) 979 goto no_flash_data; 980 981 for (cnt = 0, chksum = 0; cnt < sizeof(*fdt) >> 1; cnt++, wptr++) 982 chksum += le16_to_cpu(*wptr); 983 if (chksum) { 984 ql_dbg(ql_dbg_init, vha, 0x004c, 985 "Inconsistent FDT detected:" 986 " checksum=0x%x id=%c version0x%x.\n", chksum, 987 fdt->sig[0], le16_to_cpu(fdt->version)); 988 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0113, 989 fdt, sizeof(*fdt)); 990 goto no_flash_data; 991 } 992 993 loc = locations[1]; 994 mid = le16_to_cpu(fdt->man_id); 995 fid = le16_to_cpu(fdt->id); 996 ha->fdt_wrt_disable = fdt->wrt_disable_bits; 997 ha->fdt_wrt_enable = fdt->wrt_enable_bits; 998 ha->fdt_wrt_sts_reg_cmd = fdt->wrt_sts_reg_cmd; 999 if (IS_QLA8044(ha)) 1000 ha->fdt_erase_cmd = fdt->erase_cmd; 1001 else 1002 ha->fdt_erase_cmd = 1003 flash_conf_addr(ha, 0x0300 | fdt->erase_cmd); 1004 ha->fdt_block_size = le32_to_cpu(fdt->block_size); 1005 if (fdt->unprotect_sec_cmd) { 1006 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0300 | 1007 fdt->unprotect_sec_cmd); 1008 ha->fdt_protect_sec_cmd = fdt->protect_sec_cmd ? 1009 flash_conf_addr(ha, 0x0300 | fdt->protect_sec_cmd) : 1010 flash_conf_addr(ha, 0x0336); 1011 } 1012 goto done; 1013 no_flash_data: 1014 loc = locations[0]; 1015 if (IS_P3P_TYPE(ha)) { 1016 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1017 goto done; 1018 } 1019 qla24xx_get_flash_manufacturer(ha, &man_id, &flash_id); 1020 mid = man_id; 1021 fid = flash_id; 1022 ha->fdt_wrt_disable = 0x9c; 1023 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x03d8); 1024 switch (man_id) { 1025 case 0xbf: /* STT flash. */ 1026 if (flash_id == 0x8e) 1027 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1028 else 1029 ha->fdt_block_size = FLASH_BLK_SIZE_32K; 1030 1031 if (flash_id == 0x80) 1032 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0352); 1033 break; 1034 case 0x13: /* ST M25P80. */ 1035 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1036 break; 1037 case 0x1f: /* Atmel 26DF081A. */ 1038 ha->fdt_block_size = FLASH_BLK_SIZE_4K; 1039 ha->fdt_erase_cmd = flash_conf_addr(ha, 0x0320); 1040 ha->fdt_unprotect_sec_cmd = flash_conf_addr(ha, 0x0339); 1041 ha->fdt_protect_sec_cmd = flash_conf_addr(ha, 0x0336); 1042 break; 1043 default: 1044 /* Default to 64 kb sector size. */ 1045 ha->fdt_block_size = FLASH_BLK_SIZE_64K; 1046 break; 1047 } 1048 done: 1049 ql_dbg(ql_dbg_init, vha, 0x004d, 1050 "FDT[%s]: (0x%x/0x%x) erase=0x%x " 1051 "pr=%x wrtd=0x%x blk=0x%x.\n", 1052 loc, mid, fid, 1053 ha->fdt_erase_cmd, ha->fdt_protect_sec_cmd, 1054 ha->fdt_wrt_disable, ha->fdt_block_size); 1055 1056 } 1057 1058 static void 1059 qla2xxx_get_idc_param(scsi_qla_host_t *vha) 1060 { 1061 #define QLA82XX_IDC_PARAM_ADDR 0x003e885c 1062 __le32 *wptr; 1063 struct qla_hw_data *ha = vha->hw; 1064 struct req_que *req = ha->req_q_map[0]; 1065 1066 if (!(IS_P3P_TYPE(ha))) 1067 return; 1068 1069 wptr = (__force __le32 *)req->ring; 1070 ha->isp_ops->read_optrom(vha, req->ring, QLA82XX_IDC_PARAM_ADDR, 8); 1071 1072 if (*wptr == cpu_to_le32(0xffffffff)) { 1073 ha->fcoe_dev_init_timeout = QLA82XX_ROM_DEV_INIT_TIMEOUT; 1074 ha->fcoe_reset_timeout = QLA82XX_ROM_DRV_RESET_ACK_TIMEOUT; 1075 } else { 1076 ha->fcoe_dev_init_timeout = le32_to_cpu(*wptr); 1077 wptr++; 1078 ha->fcoe_reset_timeout = le32_to_cpu(*wptr); 1079 } 1080 ql_dbg(ql_dbg_init, vha, 0x004e, 1081 "fcoe_dev_init_timeout=%d " 1082 "fcoe_reset_timeout=%d.\n", ha->fcoe_dev_init_timeout, 1083 ha->fcoe_reset_timeout); 1084 return; 1085 } 1086 1087 static int qla28xx_validate_mcu_signature(scsi_qla_host_t *vha) 1088 { 1089 struct qla_hw_data *ha = vha->hw; 1090 struct req_que *req = ha->req_q_map[0]; 1091 uint32_t *dcode = (uint32_t *)req->ring; 1092 uint32_t signature[2] = {0x000c0000, 0x00050000}; 1093 int ret = QLA_SUCCESS; 1094 1095 ret = qla24xx_read_flash_data(vha, dcode, FA_FLASH_MCU_OFF >> 2, 2); 1096 if (ret) { 1097 ql_log(ql_log_fatal, vha, 0x01ab, 1098 "-> Failed to read flash mcu signature.\n"); 1099 ret = QLA_FUNCTION_FAILED; 1100 goto done; 1101 } 1102 1103 ql_dbg(ql_dbg_init, vha, 0x01ac, 1104 "Flash data 0x%08x 0x%08x.\n", dcode[0], dcode[1]); 1105 1106 if (!(dcode[0] == signature[0] && dcode[1] == signature[1])) 1107 ret = QLA_FUNCTION_FAILED; 1108 1109 done: 1110 return ret; 1111 } 1112 1113 int 1114 qla2xxx_get_flash_info(scsi_qla_host_t *vha) 1115 { 1116 int ret; 1117 uint32_t flt_addr; 1118 struct qla_hw_data *ha = vha->hw; 1119 1120 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 1121 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha) && 1122 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1123 return QLA_SUCCESS; 1124 1125 if (IS_QLA28XX(ha) && !qla28xx_validate_mcu_signature(vha)) 1126 ha->flags.secure_mcu = 1; 1127 1128 ret = qla2xxx_find_flt_start(vha, &flt_addr); 1129 if (ret != QLA_SUCCESS) 1130 return ret; 1131 1132 qla2xxx_get_flt_info(vha, flt_addr); 1133 qla2xxx_get_fdt_info(vha); 1134 qla2xxx_get_idc_param(vha); 1135 1136 return QLA_SUCCESS; 1137 } 1138 1139 void 1140 qla2xxx_flash_npiv_conf(scsi_qla_host_t *vha) 1141 { 1142 #define NPIV_CONFIG_SIZE (16*1024) 1143 void *data; 1144 __le16 *wptr; 1145 uint16_t cnt, chksum; 1146 int i; 1147 struct qla_npiv_header hdr; 1148 struct qla_npiv_entry *entry; 1149 struct qla_hw_data *ha = vha->hw; 1150 1151 if (!IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) && 1152 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha)) 1153 return; 1154 1155 if (ha->flags.nic_core_reset_hdlr_active) 1156 return; 1157 1158 if (IS_QLA8044(ha)) 1159 return; 1160 1161 ha->isp_ops->read_optrom(vha, &hdr, ha->flt_region_npiv_conf << 2, 1162 sizeof(struct qla_npiv_header)); 1163 if (hdr.version == cpu_to_le16(0xffff)) 1164 return; 1165 if (hdr.version != cpu_to_le16(1)) { 1166 ql_dbg(ql_dbg_user, vha, 0x7090, 1167 "Unsupported NPIV-Config " 1168 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 1169 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 1170 le16_to_cpu(hdr.checksum)); 1171 return; 1172 } 1173 1174 data = kmalloc(NPIV_CONFIG_SIZE, GFP_KERNEL); 1175 if (!data) { 1176 ql_log(ql_log_warn, vha, 0x7091, 1177 "Unable to allocate memory for data.\n"); 1178 return; 1179 } 1180 1181 ha->isp_ops->read_optrom(vha, data, ha->flt_region_npiv_conf << 2, 1182 NPIV_CONFIG_SIZE); 1183 1184 cnt = (sizeof(hdr) + le16_to_cpu(hdr.entries) * sizeof(*entry)) >> 1; 1185 for (wptr = data, chksum = 0; cnt--; wptr++) 1186 chksum += le16_to_cpu(*wptr); 1187 if (chksum) { 1188 ql_dbg(ql_dbg_user, vha, 0x7092, 1189 "Inconsistent NPIV-Config " 1190 "detected: version=0x%x entries=0x%x checksum=0x%x.\n", 1191 le16_to_cpu(hdr.version), le16_to_cpu(hdr.entries), 1192 le16_to_cpu(hdr.checksum)); 1193 goto done; 1194 } 1195 1196 entry = data + sizeof(struct qla_npiv_header); 1197 cnt = le16_to_cpu(hdr.entries); 1198 for (i = 0; cnt; cnt--, entry++, i++) { 1199 uint16_t flags; 1200 struct fc_vport_identifiers vid; 1201 struct fc_vport *vport; 1202 1203 memcpy(&ha->npiv_info[i], entry, sizeof(struct qla_npiv_entry)); 1204 1205 flags = le16_to_cpu(entry->flags); 1206 if (flags == 0xffff) 1207 continue; 1208 if ((flags & BIT_0) == 0) 1209 continue; 1210 1211 memset(&vid, 0, sizeof(vid)); 1212 vid.roles = FC_PORT_ROLE_FCP_INITIATOR; 1213 vid.vport_type = FC_PORTTYPE_NPIV; 1214 vid.disable = false; 1215 vid.port_name = wwn_to_u64(entry->port_name); 1216 vid.node_name = wwn_to_u64(entry->node_name); 1217 1218 ql_dbg(ql_dbg_user, vha, 0x7093, 1219 "NPIV[%02x]: wwpn=%llx wwnn=%llx vf_id=%#x Q_qos=%#x F_qos=%#x.\n", 1220 cnt, vid.port_name, vid.node_name, 1221 le16_to_cpu(entry->vf_id), 1222 entry->q_qos, entry->f_qos); 1223 1224 if (i < QLA_PRECONFIG_VPORTS) { 1225 vport = fc_vport_create(vha->host, 0, &vid); 1226 if (!vport) 1227 ql_log(ql_log_warn, vha, 0x7094, 1228 "NPIV-Config Failed to create vport [%02x]: wwpn=%llx wwnn=%llx.\n", 1229 cnt, vid.port_name, vid.node_name); 1230 } 1231 } 1232 done: 1233 kfree(data); 1234 } 1235 1236 static int 1237 qla24xx_unprotect_flash(scsi_qla_host_t *vha) 1238 { 1239 struct qla_hw_data *ha = vha->hw; 1240 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1241 1242 if (ha->flags.fac_supported) 1243 return qla81xx_fac_do_write_enable(vha, 1); 1244 1245 /* Enable flash write. */ 1246 wrt_reg_dword(®->ctrl_status, 1247 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE); 1248 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ 1249 1250 if (!ha->fdt_wrt_disable) 1251 goto done; 1252 1253 /* Disable flash write-protection, first clear SR protection bit */ 1254 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1255 /* Then write zero again to clear remaining SR bits.*/ 1256 qla24xx_write_flash_dword(ha, flash_conf_addr(ha, 0x101), 0); 1257 done: 1258 return QLA_SUCCESS; 1259 } 1260 1261 static int 1262 qla24xx_protect_flash(scsi_qla_host_t *vha) 1263 { 1264 struct qla_hw_data *ha = vha->hw; 1265 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1266 ulong cnt = 300; 1267 uint32_t faddr, dword; 1268 1269 if (ha->flags.fac_supported) 1270 return qla81xx_fac_do_write_enable(vha, 0); 1271 1272 if (!ha->fdt_wrt_disable) 1273 goto skip_wrt_protect; 1274 1275 /* Enable flash write-protection and wait for completion. */ 1276 faddr = flash_conf_addr(ha, 0x101); 1277 qla24xx_write_flash_dword(ha, faddr, ha->fdt_wrt_disable); 1278 faddr = flash_conf_addr(ha, 0x5); 1279 while (cnt--) { 1280 if (!qla24xx_read_flash_dword(ha, faddr, &dword)) { 1281 if (!(dword & BIT_0)) 1282 break; 1283 } 1284 udelay(10); 1285 } 1286 1287 skip_wrt_protect: 1288 /* Disable flash write. */ 1289 wrt_reg_dword(®->ctrl_status, 1290 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1291 1292 return QLA_SUCCESS; 1293 } 1294 1295 static int 1296 qla24xx_erase_sector(scsi_qla_host_t *vha, uint32_t fdata) 1297 { 1298 struct qla_hw_data *ha = vha->hw; 1299 uint32_t start, finish; 1300 1301 if (ha->flags.fac_supported) { 1302 start = fdata >> 2; 1303 finish = start + (ha->fdt_block_size >> 2) - 1; 1304 return qla81xx_fac_erase_sector(vha, flash_data_addr(ha, 1305 start), flash_data_addr(ha, finish)); 1306 } 1307 1308 return qla24xx_write_flash_dword(ha, ha->fdt_erase_cmd, 1309 (fdata & 0xff00) | ((fdata << 16) & 0xff0000) | 1310 ((fdata >> 16) & 0xff)); 1311 } 1312 1313 static int 1314 qla24xx_write_flash_data(scsi_qla_host_t *vha, __le32 *dwptr, uint32_t faddr, 1315 uint32_t dwords) 1316 { 1317 int ret; 1318 ulong liter; 1319 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */ 1320 uint32_t sec_mask, rest_addr, fdata; 1321 dma_addr_t optrom_dma; 1322 void *optrom = NULL; 1323 struct qla_hw_data *ha = vha->hw; 1324 1325 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) && 1326 !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1327 goto next; 1328 1329 /* Allocate dma buffer for burst write */ 1330 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 1331 &optrom_dma, GFP_KERNEL); 1332 if (!optrom) { 1333 ql_log(ql_log_warn, vha, 0x7095, 1334 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE); 1335 } 1336 1337 next: 1338 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1339 "Unprotect flash...\n"); 1340 ret = qla24xx_unprotect_flash(vha); 1341 if (ret) { 1342 ql_log(ql_log_warn, vha, 0x7096, 1343 "Failed to unprotect flash.\n"); 1344 goto done; 1345 } 1346 1347 rest_addr = (ha->fdt_block_size >> 2) - 1; 1348 sec_mask = ~rest_addr; 1349 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 1350 fdata = (faddr & sec_mask) << 2; 1351 1352 /* Are we at the beginning of a sector? */ 1353 if (!(faddr & rest_addr)) { 1354 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1355 "Erase sector %#x...\n", faddr); 1356 1357 ret = qla24xx_erase_sector(vha, fdata); 1358 if (ret) { 1359 ql_dbg(ql_dbg_user, vha, 0x7007, 1360 "Failed to erase sector %x.\n", faddr); 1361 break; 1362 } 1363 } 1364 1365 if (optrom) { 1366 /* If smaller than a burst remaining */ 1367 if (dwords - liter < dburst) 1368 dburst = dwords - liter; 1369 1370 /* Copy to dma buffer */ 1371 memcpy(optrom, dwptr, dburst << 2); 1372 1373 /* Burst write */ 1374 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1375 "Write burst (%#lx dwords)...\n", dburst); 1376 ret = qla2x00_load_ram(vha, optrom_dma, 1377 flash_data_addr(ha, faddr), dburst); 1378 if (!ret) { 1379 liter += dburst - 1; 1380 faddr += dburst - 1; 1381 dwptr += dburst - 1; 1382 continue; 1383 } 1384 1385 ql_log(ql_log_warn, vha, 0x7097, 1386 "Failed burst-write at %x (%p/%#llx)....\n", 1387 flash_data_addr(ha, faddr), optrom, 1388 (u64)optrom_dma); 1389 1390 dma_free_coherent(&ha->pdev->dev, 1391 OPTROM_BURST_SIZE, optrom, optrom_dma); 1392 optrom = NULL; 1393 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1394 break; 1395 ql_log(ql_log_warn, vha, 0x7098, 1396 "Reverting to slow write...\n"); 1397 } 1398 1399 /* Slow write */ 1400 ret = qla24xx_write_flash_dword(ha, 1401 flash_data_addr(ha, faddr), le32_to_cpu(*dwptr)); 1402 if (ret) { 1403 ql_dbg(ql_dbg_user, vha, 0x7006, 1404 "Failed slow write %x (%x)\n", faddr, *dwptr); 1405 break; 1406 } 1407 } 1408 1409 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 1410 "Protect flash...\n"); 1411 ret = qla24xx_protect_flash(vha); 1412 if (ret) 1413 ql_log(ql_log_warn, vha, 0x7099, 1414 "Failed to protect flash\n"); 1415 done: 1416 if (optrom) 1417 dma_free_coherent(&ha->pdev->dev, 1418 OPTROM_BURST_SIZE, optrom, optrom_dma); 1419 1420 return ret; 1421 } 1422 1423 uint8_t * 1424 qla2x00_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1425 uint32_t bytes) 1426 { 1427 uint32_t i; 1428 __le16 *wptr; 1429 struct qla_hw_data *ha = vha->hw; 1430 1431 /* Word reads to NVRAM via registers. */ 1432 wptr = buf; 1433 qla2x00_lock_nvram_access(ha); 1434 for (i = 0; i < bytes >> 1; i++, naddr++) 1435 wptr[i] = cpu_to_le16(qla2x00_get_nvram_word(ha, 1436 naddr)); 1437 qla2x00_unlock_nvram_access(ha); 1438 1439 return buf; 1440 } 1441 1442 uint8_t * 1443 qla24xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1444 uint32_t bytes) 1445 { 1446 struct qla_hw_data *ha = vha->hw; 1447 uint32_t *dwptr = buf; 1448 uint32_t i; 1449 1450 if (IS_P3P_TYPE(ha)) 1451 return buf; 1452 1453 /* Dword reads to flash. */ 1454 naddr = nvram_data_addr(ha, naddr); 1455 bytes >>= 2; 1456 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1457 if (qla24xx_read_flash_dword(ha, naddr, dwptr)) 1458 break; 1459 cpu_to_le32s(dwptr); 1460 } 1461 1462 return buf; 1463 } 1464 1465 int 1466 qla2x00_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1467 uint32_t bytes) 1468 { 1469 int ret, stat; 1470 uint32_t i; 1471 uint16_t *wptr; 1472 unsigned long flags; 1473 struct qla_hw_data *ha = vha->hw; 1474 1475 ret = QLA_SUCCESS; 1476 1477 spin_lock_irqsave(&ha->hardware_lock, flags); 1478 qla2x00_lock_nvram_access(ha); 1479 1480 /* Disable NVRAM write-protection. */ 1481 stat = qla2x00_clear_nvram_protection(ha); 1482 1483 wptr = (uint16_t *)buf; 1484 for (i = 0; i < bytes >> 1; i++, naddr++) { 1485 qla2x00_write_nvram_word(ha, naddr, 1486 cpu_to_le16(*wptr)); 1487 wptr++; 1488 } 1489 1490 /* Enable NVRAM write-protection. */ 1491 qla2x00_set_nvram_protection(ha, stat); 1492 1493 qla2x00_unlock_nvram_access(ha); 1494 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1495 1496 return ret; 1497 } 1498 1499 int 1500 qla24xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1501 uint32_t bytes) 1502 { 1503 struct qla_hw_data *ha = vha->hw; 1504 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1505 __le32 *dwptr = buf; 1506 uint32_t i; 1507 int ret; 1508 1509 ret = QLA_SUCCESS; 1510 1511 if (IS_P3P_TYPE(ha)) 1512 return ret; 1513 1514 /* Enable flash write. */ 1515 wrt_reg_dword(®->ctrl_status, 1516 rd_reg_dword(®->ctrl_status) | CSRX_FLASH_ENABLE); 1517 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ 1518 1519 /* Disable NVRAM write-protection. */ 1520 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1521 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0); 1522 1523 /* Dword writes to flash. */ 1524 naddr = nvram_data_addr(ha, naddr); 1525 bytes >>= 2; 1526 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1527 if (qla24xx_write_flash_dword(ha, naddr, le32_to_cpu(*dwptr))) { 1528 ql_dbg(ql_dbg_user, vha, 0x709a, 1529 "Unable to program nvram address=%x data=%x.\n", 1530 naddr, *dwptr); 1531 break; 1532 } 1533 } 1534 1535 /* Enable NVRAM write-protection. */ 1536 qla24xx_write_flash_dword(ha, nvram_conf_addr(ha, 0x101), 0x8c); 1537 1538 /* Disable flash write. */ 1539 wrt_reg_dword(®->ctrl_status, 1540 rd_reg_dword(®->ctrl_status) & ~CSRX_FLASH_ENABLE); 1541 rd_reg_dword(®->ctrl_status); /* PCI Posting. */ 1542 1543 return ret; 1544 } 1545 1546 uint8_t * 1547 qla25xx_read_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1548 uint32_t bytes) 1549 { 1550 struct qla_hw_data *ha = vha->hw; 1551 uint32_t *dwptr = buf; 1552 uint32_t i; 1553 1554 /* Dword reads to flash. */ 1555 naddr = flash_data_addr(ha, ha->flt_region_vpd_nvram | naddr); 1556 bytes >>= 2; 1557 for (i = 0; i < bytes; i++, naddr++, dwptr++) { 1558 if (qla24xx_read_flash_dword(ha, naddr, dwptr)) 1559 break; 1560 1561 cpu_to_le32s(dwptr); 1562 } 1563 1564 return buf; 1565 } 1566 1567 #define RMW_BUFFER_SIZE (64 * 1024) 1568 int 1569 qla25xx_write_nvram_data(scsi_qla_host_t *vha, void *buf, uint32_t naddr, 1570 uint32_t bytes) 1571 { 1572 struct qla_hw_data *ha = vha->hw; 1573 uint8_t *dbuf = vmalloc(RMW_BUFFER_SIZE); 1574 1575 if (!dbuf) 1576 return QLA_MEMORY_ALLOC_FAILED; 1577 ha->isp_ops->read_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1578 RMW_BUFFER_SIZE); 1579 memcpy(dbuf + (naddr << 2), buf, bytes); 1580 ha->isp_ops->write_optrom(vha, dbuf, ha->flt_region_vpd_nvram << 2, 1581 RMW_BUFFER_SIZE); 1582 vfree(dbuf); 1583 1584 return QLA_SUCCESS; 1585 } 1586 1587 static inline void 1588 qla2x00_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1589 { 1590 if (IS_QLA2322(ha)) { 1591 /* Flip all colors. */ 1592 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1593 /* Turn off. */ 1594 ha->beacon_color_state = 0; 1595 *pflags = GPIO_LED_ALL_OFF; 1596 } else { 1597 /* Turn on. */ 1598 ha->beacon_color_state = QLA_LED_ALL_ON; 1599 *pflags = GPIO_LED_RGA_ON; 1600 } 1601 } else { 1602 /* Flip green led only. */ 1603 if (ha->beacon_color_state == QLA_LED_GRN_ON) { 1604 /* Turn off. */ 1605 ha->beacon_color_state = 0; 1606 *pflags = GPIO_LED_GREEN_OFF_AMBER_OFF; 1607 } else { 1608 /* Turn on. */ 1609 ha->beacon_color_state = QLA_LED_GRN_ON; 1610 *pflags = GPIO_LED_GREEN_ON_AMBER_OFF; 1611 } 1612 } 1613 } 1614 1615 #define PIO_REG(h, r) ((h)->pio_address + offsetof(struct device_reg_2xxx, r)) 1616 1617 void 1618 qla2x00_beacon_blink(struct scsi_qla_host *vha) 1619 { 1620 uint16_t gpio_enable; 1621 uint16_t gpio_data; 1622 uint16_t led_color = 0; 1623 unsigned long flags; 1624 struct qla_hw_data *ha = vha->hw; 1625 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1626 1627 if (IS_P3P_TYPE(ha)) 1628 return; 1629 1630 spin_lock_irqsave(&ha->hardware_lock, flags); 1631 1632 /* Save the Original GPIOE. */ 1633 if (ha->pio_address) { 1634 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1635 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1636 } else { 1637 gpio_enable = rd_reg_word(®->gpioe); 1638 gpio_data = rd_reg_word(®->gpiod); 1639 } 1640 1641 /* Set the modified gpio_enable values */ 1642 gpio_enable |= GPIO_LED_MASK; 1643 1644 if (ha->pio_address) { 1645 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1646 } else { 1647 wrt_reg_word(®->gpioe, gpio_enable); 1648 rd_reg_word(®->gpioe); 1649 } 1650 1651 qla2x00_flip_colors(ha, &led_color); 1652 1653 /* Clear out any previously set LED color. */ 1654 gpio_data &= ~GPIO_LED_MASK; 1655 1656 /* Set the new input LED color to GPIOD. */ 1657 gpio_data |= led_color; 1658 1659 /* Set the modified gpio_data values */ 1660 if (ha->pio_address) { 1661 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1662 } else { 1663 wrt_reg_word(®->gpiod, gpio_data); 1664 rd_reg_word(®->gpiod); 1665 } 1666 1667 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1668 } 1669 1670 int 1671 qla2x00_beacon_on(struct scsi_qla_host *vha) 1672 { 1673 uint16_t gpio_enable; 1674 uint16_t gpio_data; 1675 unsigned long flags; 1676 struct qla_hw_data *ha = vha->hw; 1677 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 1678 1679 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1680 ha->fw_options[1] |= FO1_DISABLE_GPIO6_7; 1681 1682 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1683 ql_log(ql_log_warn, vha, 0x709b, 1684 "Unable to update fw options (beacon on).\n"); 1685 return QLA_FUNCTION_FAILED; 1686 } 1687 1688 /* Turn off LEDs. */ 1689 spin_lock_irqsave(&ha->hardware_lock, flags); 1690 if (ha->pio_address) { 1691 gpio_enable = RD_REG_WORD_PIO(PIO_REG(ha, gpioe)); 1692 gpio_data = RD_REG_WORD_PIO(PIO_REG(ha, gpiod)); 1693 } else { 1694 gpio_enable = rd_reg_word(®->gpioe); 1695 gpio_data = rd_reg_word(®->gpiod); 1696 } 1697 gpio_enable |= GPIO_LED_MASK; 1698 1699 /* Set the modified gpio_enable values. */ 1700 if (ha->pio_address) { 1701 WRT_REG_WORD_PIO(PIO_REG(ha, gpioe), gpio_enable); 1702 } else { 1703 wrt_reg_word(®->gpioe, gpio_enable); 1704 rd_reg_word(®->gpioe); 1705 } 1706 1707 /* Clear out previously set LED colour. */ 1708 gpio_data &= ~GPIO_LED_MASK; 1709 if (ha->pio_address) { 1710 WRT_REG_WORD_PIO(PIO_REG(ha, gpiod), gpio_data); 1711 } else { 1712 wrt_reg_word(®->gpiod, gpio_data); 1713 rd_reg_word(®->gpiod); 1714 } 1715 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1716 1717 /* 1718 * Let the per HBA timer kick off the blinking process based on 1719 * the following flags. No need to do anything else now. 1720 */ 1721 ha->beacon_blink_led = 1; 1722 ha->beacon_color_state = 0; 1723 1724 return QLA_SUCCESS; 1725 } 1726 1727 int 1728 qla2x00_beacon_off(struct scsi_qla_host *vha) 1729 { 1730 int rval = QLA_SUCCESS; 1731 struct qla_hw_data *ha = vha->hw; 1732 1733 ha->beacon_blink_led = 0; 1734 1735 /* Set the on flag so when it gets flipped it will be off. */ 1736 if (IS_QLA2322(ha)) 1737 ha->beacon_color_state = QLA_LED_ALL_ON; 1738 else 1739 ha->beacon_color_state = QLA_LED_GRN_ON; 1740 1741 ha->isp_ops->beacon_blink(vha); /* This turns green LED off */ 1742 1743 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING; 1744 ha->fw_options[1] &= ~FO1_DISABLE_GPIO6_7; 1745 1746 rval = qla2x00_set_fw_options(vha, ha->fw_options); 1747 if (rval != QLA_SUCCESS) 1748 ql_log(ql_log_warn, vha, 0x709c, 1749 "Unable to update fw options (beacon off).\n"); 1750 return rval; 1751 } 1752 1753 1754 static inline void 1755 qla24xx_flip_colors(struct qla_hw_data *ha, uint16_t *pflags) 1756 { 1757 /* Flip all colors. */ 1758 if (ha->beacon_color_state == QLA_LED_ALL_ON) { 1759 /* Turn off. */ 1760 ha->beacon_color_state = 0; 1761 *pflags = 0; 1762 } else { 1763 /* Turn on. */ 1764 ha->beacon_color_state = QLA_LED_ALL_ON; 1765 *pflags = GPDX_LED_YELLOW_ON | GPDX_LED_AMBER_ON; 1766 } 1767 } 1768 1769 void 1770 qla24xx_beacon_blink(struct scsi_qla_host *vha) 1771 { 1772 uint16_t led_color = 0; 1773 uint32_t gpio_data; 1774 unsigned long flags; 1775 struct qla_hw_data *ha = vha->hw; 1776 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1777 1778 /* Save the Original GPIOD. */ 1779 spin_lock_irqsave(&ha->hardware_lock, flags); 1780 gpio_data = rd_reg_dword(®->gpiod); 1781 1782 /* Enable the gpio_data reg for update. */ 1783 gpio_data |= GPDX_LED_UPDATE_MASK; 1784 1785 wrt_reg_dword(®->gpiod, gpio_data); 1786 gpio_data = rd_reg_dword(®->gpiod); 1787 1788 /* Set the color bits. */ 1789 qla24xx_flip_colors(ha, &led_color); 1790 1791 /* Clear out any previously set LED color. */ 1792 gpio_data &= ~GPDX_LED_COLOR_MASK; 1793 1794 /* Set the new input LED color to GPIOD. */ 1795 gpio_data |= led_color; 1796 1797 /* Set the modified gpio_data values. */ 1798 wrt_reg_dword(®->gpiod, gpio_data); 1799 gpio_data = rd_reg_dword(®->gpiod); 1800 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1801 } 1802 1803 static uint32_t 1804 qla83xx_select_led_port(struct qla_hw_data *ha) 1805 { 1806 uint32_t led_select_value = 0; 1807 1808 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) && !IS_QLA28XX(ha)) 1809 goto out; 1810 1811 if (ha->port_no == 0) 1812 led_select_value = QLA83XX_LED_PORT0; 1813 else 1814 led_select_value = QLA83XX_LED_PORT1; 1815 1816 out: 1817 return led_select_value; 1818 } 1819 1820 void 1821 qla83xx_beacon_blink(struct scsi_qla_host *vha) 1822 { 1823 uint32_t led_select_value; 1824 struct qla_hw_data *ha = vha->hw; 1825 uint16_t led_cfg[6]; 1826 uint16_t orig_led_cfg[6]; 1827 uint32_t led_10_value, led_43_value; 1828 1829 if (!IS_QLA83XX(ha) && !IS_QLA81XX(ha) && !IS_QLA27XX(ha) && 1830 !IS_QLA28XX(ha)) 1831 return; 1832 1833 if (!ha->beacon_blink_led) 1834 return; 1835 1836 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 1837 qla2x00_write_ram_word(vha, 0x1003, 0x40000230); 1838 qla2x00_write_ram_word(vha, 0x1004, 0x40000230); 1839 } else if (IS_QLA2031(ha)) { 1840 led_select_value = qla83xx_select_led_port(ha); 1841 1842 qla83xx_wr_reg(vha, led_select_value, 0x40000230); 1843 qla83xx_wr_reg(vha, led_select_value + 4, 0x40000230); 1844 } else if (IS_QLA8031(ha)) { 1845 led_select_value = qla83xx_select_led_port(ha); 1846 1847 qla83xx_rd_reg(vha, led_select_value, &led_10_value); 1848 qla83xx_rd_reg(vha, led_select_value + 0x10, &led_43_value); 1849 qla83xx_wr_reg(vha, led_select_value, 0x01f44000); 1850 msleep(500); 1851 qla83xx_wr_reg(vha, led_select_value, 0x400001f4); 1852 msleep(1000); 1853 qla83xx_wr_reg(vha, led_select_value, led_10_value); 1854 qla83xx_wr_reg(vha, led_select_value + 0x10, led_43_value); 1855 } else if (IS_QLA81XX(ha)) { 1856 int rval; 1857 1858 /* Save Current */ 1859 rval = qla81xx_get_led_config(vha, orig_led_cfg); 1860 /* Do the blink */ 1861 if (rval == QLA_SUCCESS) { 1862 if (IS_QLA81XX(ha)) { 1863 led_cfg[0] = 0x4000; 1864 led_cfg[1] = 0x2000; 1865 led_cfg[2] = 0; 1866 led_cfg[3] = 0; 1867 led_cfg[4] = 0; 1868 led_cfg[5] = 0; 1869 } else { 1870 led_cfg[0] = 0x4000; 1871 led_cfg[1] = 0x4000; 1872 led_cfg[2] = 0x4000; 1873 led_cfg[3] = 0x2000; 1874 led_cfg[4] = 0; 1875 led_cfg[5] = 0x2000; 1876 } 1877 rval = qla81xx_set_led_config(vha, led_cfg); 1878 msleep(1000); 1879 if (IS_QLA81XX(ha)) { 1880 led_cfg[0] = 0x4000; 1881 led_cfg[1] = 0x2000; 1882 led_cfg[2] = 0; 1883 } else { 1884 led_cfg[0] = 0x4000; 1885 led_cfg[1] = 0x2000; 1886 led_cfg[2] = 0x4000; 1887 led_cfg[3] = 0x4000; 1888 led_cfg[4] = 0; 1889 led_cfg[5] = 0x2000; 1890 } 1891 rval = qla81xx_set_led_config(vha, led_cfg); 1892 } 1893 /* On exit, restore original (presumes no status change) */ 1894 qla81xx_set_led_config(vha, orig_led_cfg); 1895 } 1896 } 1897 1898 int 1899 qla24xx_beacon_on(struct scsi_qla_host *vha) 1900 { 1901 uint32_t gpio_data; 1902 unsigned long flags; 1903 struct qla_hw_data *ha = vha->hw; 1904 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1905 1906 if (IS_P3P_TYPE(ha)) 1907 return QLA_SUCCESS; 1908 1909 if (IS_QLA8031(ha) || IS_QLA81XX(ha)) 1910 goto skip_gpio; /* let blink handle it */ 1911 1912 if (ha->beacon_blink_led == 0) { 1913 /* Enable firmware for update */ 1914 ha->fw_options[1] |= ADD_FO1_DISABLE_GPIO_LED_CTRL; 1915 1916 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) 1917 return QLA_FUNCTION_FAILED; 1918 1919 if (qla2x00_get_fw_options(vha, ha->fw_options) != 1920 QLA_SUCCESS) { 1921 ql_log(ql_log_warn, vha, 0x7009, 1922 "Unable to update fw options (beacon on).\n"); 1923 return QLA_FUNCTION_FAILED; 1924 } 1925 1926 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1927 goto skip_gpio; 1928 1929 spin_lock_irqsave(&ha->hardware_lock, flags); 1930 gpio_data = rd_reg_dword(®->gpiod); 1931 1932 /* Enable the gpio_data reg for update. */ 1933 gpio_data |= GPDX_LED_UPDATE_MASK; 1934 wrt_reg_dword(®->gpiod, gpio_data); 1935 rd_reg_dword(®->gpiod); 1936 1937 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1938 } 1939 1940 /* So all colors blink together. */ 1941 ha->beacon_color_state = 0; 1942 1943 skip_gpio: 1944 /* Let the per HBA timer kick off the blinking process. */ 1945 ha->beacon_blink_led = 1; 1946 1947 return QLA_SUCCESS; 1948 } 1949 1950 int 1951 qla24xx_beacon_off(struct scsi_qla_host *vha) 1952 { 1953 uint32_t gpio_data; 1954 unsigned long flags; 1955 struct qla_hw_data *ha = vha->hw; 1956 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24; 1957 1958 if (IS_P3P_TYPE(ha)) 1959 return QLA_SUCCESS; 1960 1961 if (!ha->flags.fw_started) 1962 return QLA_SUCCESS; 1963 1964 ha->beacon_blink_led = 0; 1965 1966 if (IS_QLA2031(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)) 1967 goto set_fw_options; 1968 1969 if (IS_QLA8031(ha) || IS_QLA81XX(ha)) 1970 return QLA_SUCCESS; 1971 1972 ha->beacon_color_state = QLA_LED_ALL_ON; 1973 1974 ha->isp_ops->beacon_blink(vha); /* Will flip to all off. */ 1975 1976 /* Give control back to firmware. */ 1977 spin_lock_irqsave(&ha->hardware_lock, flags); 1978 gpio_data = rd_reg_dword(®->gpiod); 1979 1980 /* Disable the gpio_data reg for update. */ 1981 gpio_data &= ~GPDX_LED_UPDATE_MASK; 1982 wrt_reg_dword(®->gpiod, gpio_data); 1983 rd_reg_dword(®->gpiod); 1984 spin_unlock_irqrestore(&ha->hardware_lock, flags); 1985 1986 set_fw_options: 1987 ha->fw_options[1] &= ~ADD_FO1_DISABLE_GPIO_LED_CTRL; 1988 1989 if (qla2x00_set_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1990 ql_log(ql_log_warn, vha, 0x704d, 1991 "Unable to update fw options (beacon on).\n"); 1992 return QLA_FUNCTION_FAILED; 1993 } 1994 1995 if (qla2x00_get_fw_options(vha, ha->fw_options) != QLA_SUCCESS) { 1996 ql_log(ql_log_warn, vha, 0x704e, 1997 "Unable to update fw options (beacon on).\n"); 1998 return QLA_FUNCTION_FAILED; 1999 } 2000 2001 return QLA_SUCCESS; 2002 } 2003 2004 2005 /* 2006 * Flash support routines 2007 */ 2008 2009 /** 2010 * qla2x00_flash_enable() - Setup flash for reading and writing. 2011 * @ha: HA context 2012 */ 2013 static void 2014 qla2x00_flash_enable(struct qla_hw_data *ha) 2015 { 2016 uint16_t data; 2017 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2018 2019 data = rd_reg_word(®->ctrl_status); 2020 data |= CSR_FLASH_ENABLE; 2021 wrt_reg_word(®->ctrl_status, data); 2022 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2023 } 2024 2025 /** 2026 * qla2x00_flash_disable() - Disable flash and allow RISC to run. 2027 * @ha: HA context 2028 */ 2029 static void 2030 qla2x00_flash_disable(struct qla_hw_data *ha) 2031 { 2032 uint16_t data; 2033 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2034 2035 data = rd_reg_word(®->ctrl_status); 2036 data &= ~(CSR_FLASH_ENABLE); 2037 wrt_reg_word(®->ctrl_status, data); 2038 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2039 } 2040 2041 /** 2042 * qla2x00_read_flash_byte() - Reads a byte from flash 2043 * @ha: HA context 2044 * @addr: Address in flash to read 2045 * 2046 * A word is read from the chip, but, only the lower byte is valid. 2047 * 2048 * Returns the byte read from flash @addr. 2049 */ 2050 static uint8_t 2051 qla2x00_read_flash_byte(struct qla_hw_data *ha, uint32_t addr) 2052 { 2053 uint16_t data; 2054 uint16_t bank_select; 2055 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2056 2057 bank_select = rd_reg_word(®->ctrl_status); 2058 2059 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2060 /* Specify 64K address range: */ 2061 /* clear out Module Select and Flash Address bits [19:16]. */ 2062 bank_select &= ~0xf8; 2063 bank_select |= addr >> 12 & 0xf0; 2064 bank_select |= CSR_FLASH_64K_BANK; 2065 wrt_reg_word(®->ctrl_status, bank_select); 2066 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2067 2068 wrt_reg_word(®->flash_address, (uint16_t)addr); 2069 data = rd_reg_word(®->flash_data); 2070 2071 return (uint8_t)data; 2072 } 2073 2074 /* Setup bit 16 of flash address. */ 2075 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 2076 bank_select |= CSR_FLASH_64K_BANK; 2077 wrt_reg_word(®->ctrl_status, bank_select); 2078 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2079 } else if (((addr & BIT_16) == 0) && 2080 (bank_select & CSR_FLASH_64K_BANK)) { 2081 bank_select &= ~(CSR_FLASH_64K_BANK); 2082 wrt_reg_word(®->ctrl_status, bank_select); 2083 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2084 } 2085 2086 /* Always perform IO mapped accesses to the FLASH registers. */ 2087 if (ha->pio_address) { 2088 uint16_t data2; 2089 2090 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 2091 do { 2092 data = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 2093 barrier(); 2094 cpu_relax(); 2095 data2 = RD_REG_WORD_PIO(PIO_REG(ha, flash_data)); 2096 } while (data != data2); 2097 } else { 2098 wrt_reg_word(®->flash_address, (uint16_t)addr); 2099 data = qla2x00_debounce_register(®->flash_data); 2100 } 2101 2102 return (uint8_t)data; 2103 } 2104 2105 /** 2106 * qla2x00_write_flash_byte() - Write a byte to flash 2107 * @ha: HA context 2108 * @addr: Address in flash to write 2109 * @data: Data to write 2110 */ 2111 static void 2112 qla2x00_write_flash_byte(struct qla_hw_data *ha, uint32_t addr, uint8_t data) 2113 { 2114 uint16_t bank_select; 2115 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2116 2117 bank_select = rd_reg_word(®->ctrl_status); 2118 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2119 /* Specify 64K address range: */ 2120 /* clear out Module Select and Flash Address bits [19:16]. */ 2121 bank_select &= ~0xf8; 2122 bank_select |= addr >> 12 & 0xf0; 2123 bank_select |= CSR_FLASH_64K_BANK; 2124 wrt_reg_word(®->ctrl_status, bank_select); 2125 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2126 2127 wrt_reg_word(®->flash_address, (uint16_t)addr); 2128 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2129 wrt_reg_word(®->flash_data, (uint16_t)data); 2130 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2131 2132 return; 2133 } 2134 2135 /* Setup bit 16 of flash address. */ 2136 if ((addr & BIT_16) && ((bank_select & CSR_FLASH_64K_BANK) == 0)) { 2137 bank_select |= CSR_FLASH_64K_BANK; 2138 wrt_reg_word(®->ctrl_status, bank_select); 2139 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2140 } else if (((addr & BIT_16) == 0) && 2141 (bank_select & CSR_FLASH_64K_BANK)) { 2142 bank_select &= ~(CSR_FLASH_64K_BANK); 2143 wrt_reg_word(®->ctrl_status, bank_select); 2144 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2145 } 2146 2147 /* Always perform IO mapped accesses to the FLASH registers. */ 2148 if (ha->pio_address) { 2149 WRT_REG_WORD_PIO(PIO_REG(ha, flash_address), (uint16_t)addr); 2150 WRT_REG_WORD_PIO(PIO_REG(ha, flash_data), (uint16_t)data); 2151 } else { 2152 wrt_reg_word(®->flash_address, (uint16_t)addr); 2153 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2154 wrt_reg_word(®->flash_data, (uint16_t)data); 2155 rd_reg_word(®->ctrl_status); /* PCI Posting. */ 2156 } 2157 } 2158 2159 /** 2160 * qla2x00_poll_flash() - Polls flash for completion. 2161 * @ha: HA context 2162 * @addr: Address in flash to poll 2163 * @poll_data: Data to be polled 2164 * @man_id: Flash manufacturer ID 2165 * @flash_id: Flash ID 2166 * 2167 * This function polls the device until bit 7 of what is read matches data 2168 * bit 7 or until data bit 5 becomes a 1. If that happens, the flash ROM timed 2169 * out (a fatal error). The flash book recommends reading bit 7 again after 2170 * reading bit 5 as a 1. 2171 * 2172 * Returns 0 on success, else non-zero. 2173 */ 2174 static int 2175 qla2x00_poll_flash(struct qla_hw_data *ha, uint32_t addr, uint8_t poll_data, 2176 uint8_t man_id, uint8_t flash_id) 2177 { 2178 int status; 2179 uint8_t flash_data; 2180 uint32_t cnt; 2181 2182 status = 1; 2183 2184 /* Wait for 30 seconds for command to finish. */ 2185 poll_data &= BIT_7; 2186 for (cnt = 3000000; cnt; cnt--) { 2187 flash_data = qla2x00_read_flash_byte(ha, addr); 2188 if ((flash_data & BIT_7) == poll_data) { 2189 status = 0; 2190 break; 2191 } 2192 2193 if (man_id != 0x40 && man_id != 0xda) { 2194 if ((flash_data & BIT_5) && cnt > 2) 2195 cnt = 2; 2196 } 2197 udelay(10); 2198 barrier(); 2199 cond_resched(); 2200 } 2201 return status; 2202 } 2203 2204 /** 2205 * qla2x00_program_flash_address() - Programs a flash address 2206 * @ha: HA context 2207 * @addr: Address in flash to program 2208 * @data: Data to be written in flash 2209 * @man_id: Flash manufacturer ID 2210 * @flash_id: Flash ID 2211 * 2212 * Returns 0 on success, else non-zero. 2213 */ 2214 static int 2215 qla2x00_program_flash_address(struct qla_hw_data *ha, uint32_t addr, 2216 uint8_t data, uint8_t man_id, uint8_t flash_id) 2217 { 2218 /* Write Program Command Sequence. */ 2219 if (IS_OEM_001(ha)) { 2220 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2221 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2222 qla2x00_write_flash_byte(ha, 0xaaa, 0xa0); 2223 qla2x00_write_flash_byte(ha, addr, data); 2224 } else { 2225 if (man_id == 0xda && flash_id == 0xc1) { 2226 qla2x00_write_flash_byte(ha, addr, data); 2227 if (addr & 0x7e) 2228 return 0; 2229 } else { 2230 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2231 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2232 qla2x00_write_flash_byte(ha, 0x5555, 0xa0); 2233 qla2x00_write_flash_byte(ha, addr, data); 2234 } 2235 } 2236 2237 udelay(150); 2238 2239 /* Wait for write to complete. */ 2240 return qla2x00_poll_flash(ha, addr, data, man_id, flash_id); 2241 } 2242 2243 /** 2244 * qla2x00_erase_flash() - Erase the flash. 2245 * @ha: HA context 2246 * @man_id: Flash manufacturer ID 2247 * @flash_id: Flash ID 2248 * 2249 * Returns 0 on success, else non-zero. 2250 */ 2251 static int 2252 qla2x00_erase_flash(struct qla_hw_data *ha, uint8_t man_id, uint8_t flash_id) 2253 { 2254 /* Individual Sector Erase Command Sequence */ 2255 if (IS_OEM_001(ha)) { 2256 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2257 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2258 qla2x00_write_flash_byte(ha, 0xaaa, 0x80); 2259 qla2x00_write_flash_byte(ha, 0xaaa, 0xaa); 2260 qla2x00_write_flash_byte(ha, 0x555, 0x55); 2261 qla2x00_write_flash_byte(ha, 0xaaa, 0x10); 2262 } else { 2263 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2264 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2265 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 2266 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2267 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2268 qla2x00_write_flash_byte(ha, 0x5555, 0x10); 2269 } 2270 2271 udelay(150); 2272 2273 /* Wait for erase to complete. */ 2274 return qla2x00_poll_flash(ha, 0x00, 0x80, man_id, flash_id); 2275 } 2276 2277 /** 2278 * qla2x00_erase_flash_sector() - Erase a flash sector. 2279 * @ha: HA context 2280 * @addr: Flash sector to erase 2281 * @sec_mask: Sector address mask 2282 * @man_id: Flash manufacturer ID 2283 * @flash_id: Flash ID 2284 * 2285 * Returns 0 on success, else non-zero. 2286 */ 2287 static int 2288 qla2x00_erase_flash_sector(struct qla_hw_data *ha, uint32_t addr, 2289 uint32_t sec_mask, uint8_t man_id, uint8_t flash_id) 2290 { 2291 /* Individual Sector Erase Command Sequence */ 2292 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2293 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2294 qla2x00_write_flash_byte(ha, 0x5555, 0x80); 2295 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2296 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2297 if (man_id == 0x1f && flash_id == 0x13) 2298 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x10); 2299 else 2300 qla2x00_write_flash_byte(ha, addr & sec_mask, 0x30); 2301 2302 udelay(150); 2303 2304 /* Wait for erase to complete. */ 2305 return qla2x00_poll_flash(ha, addr, 0x80, man_id, flash_id); 2306 } 2307 2308 /** 2309 * qla2x00_get_flash_manufacturer() - Read manufacturer ID from flash chip. 2310 * @ha: host adapter 2311 * @man_id: Flash manufacturer ID 2312 * @flash_id: Flash ID 2313 */ 2314 static void 2315 qla2x00_get_flash_manufacturer(struct qla_hw_data *ha, uint8_t *man_id, 2316 uint8_t *flash_id) 2317 { 2318 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2319 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2320 qla2x00_write_flash_byte(ha, 0x5555, 0x90); 2321 *man_id = qla2x00_read_flash_byte(ha, 0x0000); 2322 *flash_id = qla2x00_read_flash_byte(ha, 0x0001); 2323 qla2x00_write_flash_byte(ha, 0x5555, 0xaa); 2324 qla2x00_write_flash_byte(ha, 0x2aaa, 0x55); 2325 qla2x00_write_flash_byte(ha, 0x5555, 0xf0); 2326 } 2327 2328 static void 2329 qla2x00_read_flash_data(struct qla_hw_data *ha, uint8_t *tmp_buf, 2330 uint32_t saddr, uint32_t length) 2331 { 2332 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2333 uint32_t midpoint, ilength; 2334 uint8_t data; 2335 2336 midpoint = length / 2; 2337 2338 wrt_reg_word(®->nvram, 0); 2339 rd_reg_word(®->nvram); 2340 for (ilength = 0; ilength < length; saddr++, ilength++, tmp_buf++) { 2341 if (ilength == midpoint) { 2342 wrt_reg_word(®->nvram, NVR_SELECT); 2343 rd_reg_word(®->nvram); 2344 } 2345 data = qla2x00_read_flash_byte(ha, saddr); 2346 if (saddr % 100) 2347 udelay(10); 2348 *tmp_buf = data; 2349 cond_resched(); 2350 } 2351 } 2352 2353 static inline void 2354 qla2x00_suspend_hba(struct scsi_qla_host *vha) 2355 { 2356 int cnt; 2357 unsigned long flags; 2358 struct qla_hw_data *ha = vha->hw; 2359 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2360 2361 /* Suspend HBA. */ 2362 scsi_block_requests(vha->host); 2363 ha->isp_ops->disable_intrs(ha); 2364 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2365 2366 /* Pause RISC. */ 2367 spin_lock_irqsave(&ha->hardware_lock, flags); 2368 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC); 2369 rd_reg_word(®->hccr); 2370 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) { 2371 for (cnt = 0; cnt < 30000; cnt++) { 2372 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0) 2373 break; 2374 udelay(100); 2375 } 2376 } else { 2377 udelay(10); 2378 } 2379 spin_unlock_irqrestore(&ha->hardware_lock, flags); 2380 } 2381 2382 static inline void 2383 qla2x00_resume_hba(struct scsi_qla_host *vha) 2384 { 2385 struct qla_hw_data *ha = vha->hw; 2386 2387 /* Resume HBA. */ 2388 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2389 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2390 qla2xxx_wake_dpc(vha); 2391 qla2x00_wait_for_chip_reset(vha); 2392 scsi_unblock_requests(vha->host); 2393 } 2394 2395 void * 2396 qla2x00_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2397 uint32_t offset, uint32_t length) 2398 { 2399 uint32_t addr, midpoint; 2400 uint8_t *data; 2401 struct qla_hw_data *ha = vha->hw; 2402 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2403 2404 /* Suspend HBA. */ 2405 qla2x00_suspend_hba(vha); 2406 2407 /* Go with read. */ 2408 midpoint = ha->optrom_size / 2; 2409 2410 qla2x00_flash_enable(ha); 2411 wrt_reg_word(®->nvram, 0); 2412 rd_reg_word(®->nvram); /* PCI Posting. */ 2413 for (addr = offset, data = buf; addr < length; addr++, data++) { 2414 if (addr == midpoint) { 2415 wrt_reg_word(®->nvram, NVR_SELECT); 2416 rd_reg_word(®->nvram); /* PCI Posting. */ 2417 } 2418 2419 *data = qla2x00_read_flash_byte(ha, addr); 2420 } 2421 qla2x00_flash_disable(ha); 2422 2423 /* Resume HBA. */ 2424 qla2x00_resume_hba(vha); 2425 2426 return buf; 2427 } 2428 2429 int 2430 qla2x00_write_optrom_data(struct scsi_qla_host *vha, void *buf, 2431 uint32_t offset, uint32_t length) 2432 { 2433 2434 int rval; 2435 uint8_t man_id, flash_id, sec_number, *data; 2436 uint16_t wd; 2437 uint32_t addr, liter, sec_mask, rest_addr; 2438 struct qla_hw_data *ha = vha->hw; 2439 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp; 2440 2441 /* Suspend HBA. */ 2442 qla2x00_suspend_hba(vha); 2443 2444 rval = QLA_SUCCESS; 2445 sec_number = 0; 2446 2447 /* Reset ISP chip. */ 2448 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET); 2449 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd); 2450 2451 /* Go with write. */ 2452 qla2x00_flash_enable(ha); 2453 do { /* Loop once to provide quick error exit */ 2454 /* Structure of flash memory based on manufacturer */ 2455 if (IS_OEM_001(ha)) { 2456 /* OEM variant with special flash part. */ 2457 man_id = flash_id = 0; 2458 rest_addr = 0xffff; 2459 sec_mask = 0x10000; 2460 goto update_flash; 2461 } 2462 qla2x00_get_flash_manufacturer(ha, &man_id, &flash_id); 2463 switch (man_id) { 2464 case 0x20: /* ST flash. */ 2465 if (flash_id == 0xd2 || flash_id == 0xe3) { 2466 /* 2467 * ST m29w008at part - 64kb sector size with 2468 * 32kb,8kb,8kb,16kb sectors at memory address 2469 * 0xf0000. 2470 */ 2471 rest_addr = 0xffff; 2472 sec_mask = 0x10000; 2473 break; 2474 } 2475 /* 2476 * ST m29w010b part - 16kb sector size 2477 * Default to 16kb sectors 2478 */ 2479 rest_addr = 0x3fff; 2480 sec_mask = 0x1c000; 2481 break; 2482 case 0x40: /* Mostel flash. */ 2483 /* Mostel v29c51001 part - 512 byte sector size. */ 2484 rest_addr = 0x1ff; 2485 sec_mask = 0x1fe00; 2486 break; 2487 case 0xbf: /* SST flash. */ 2488 /* SST39sf10 part - 4kb sector size. */ 2489 rest_addr = 0xfff; 2490 sec_mask = 0x1f000; 2491 break; 2492 case 0xda: /* Winbond flash. */ 2493 /* Winbond W29EE011 part - 256 byte sector size. */ 2494 rest_addr = 0x7f; 2495 sec_mask = 0x1ff80; 2496 break; 2497 case 0xc2: /* Macronix flash. */ 2498 /* 64k sector size. */ 2499 if (flash_id == 0x38 || flash_id == 0x4f) { 2500 rest_addr = 0xffff; 2501 sec_mask = 0x10000; 2502 break; 2503 } 2504 fallthrough; 2505 2506 case 0x1f: /* Atmel flash. */ 2507 /* 512k sector size. */ 2508 if (flash_id == 0x13) { 2509 rest_addr = 0x7fffffff; 2510 sec_mask = 0x80000000; 2511 break; 2512 } 2513 fallthrough; 2514 2515 case 0x01: /* AMD flash. */ 2516 if (flash_id == 0x38 || flash_id == 0x40 || 2517 flash_id == 0x4f) { 2518 /* Am29LV081 part - 64kb sector size. */ 2519 /* Am29LV002BT part - 64kb sector size. */ 2520 rest_addr = 0xffff; 2521 sec_mask = 0x10000; 2522 break; 2523 } else if (flash_id == 0x3e) { 2524 /* 2525 * Am29LV008b part - 64kb sector size with 2526 * 32kb,8kb,8kb,16kb sector at memory address 2527 * h0xf0000. 2528 */ 2529 rest_addr = 0xffff; 2530 sec_mask = 0x10000; 2531 break; 2532 } else if (flash_id == 0x20 || flash_id == 0x6e) { 2533 /* 2534 * Am29LV010 part or AM29f010 - 16kb sector 2535 * size. 2536 */ 2537 rest_addr = 0x3fff; 2538 sec_mask = 0x1c000; 2539 break; 2540 } else if (flash_id == 0x6d) { 2541 /* Am29LV001 part - 8kb sector size. */ 2542 rest_addr = 0x1fff; 2543 sec_mask = 0x1e000; 2544 break; 2545 } 2546 fallthrough; 2547 default: 2548 /* Default to 16 kb sector size. */ 2549 rest_addr = 0x3fff; 2550 sec_mask = 0x1c000; 2551 break; 2552 } 2553 2554 update_flash: 2555 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2556 if (qla2x00_erase_flash(ha, man_id, flash_id)) { 2557 rval = QLA_FUNCTION_FAILED; 2558 break; 2559 } 2560 } 2561 2562 for (addr = offset, liter = 0; liter < length; liter++, 2563 addr++) { 2564 data = buf + liter; 2565 /* Are we at the beginning of a sector? */ 2566 if ((addr & rest_addr) == 0) { 2567 if (IS_QLA2322(ha) || IS_QLA6322(ha)) { 2568 if (addr >= 0x10000UL) { 2569 if (((addr >> 12) & 0xf0) && 2570 ((man_id == 0x01 && 2571 flash_id == 0x3e) || 2572 (man_id == 0x20 && 2573 flash_id == 0xd2))) { 2574 sec_number++; 2575 if (sec_number == 1) { 2576 rest_addr = 2577 0x7fff; 2578 sec_mask = 2579 0x18000; 2580 } else if ( 2581 sec_number == 2 || 2582 sec_number == 3) { 2583 rest_addr = 2584 0x1fff; 2585 sec_mask = 2586 0x1e000; 2587 } else if ( 2588 sec_number == 4) { 2589 rest_addr = 2590 0x3fff; 2591 sec_mask = 2592 0x1c000; 2593 } 2594 } 2595 } 2596 } else if (addr == ha->optrom_size / 2) { 2597 wrt_reg_word(®->nvram, NVR_SELECT); 2598 rd_reg_word(®->nvram); 2599 } 2600 2601 if (flash_id == 0xda && man_id == 0xc1) { 2602 qla2x00_write_flash_byte(ha, 0x5555, 2603 0xaa); 2604 qla2x00_write_flash_byte(ha, 0x2aaa, 2605 0x55); 2606 qla2x00_write_flash_byte(ha, 0x5555, 2607 0xa0); 2608 } else if (!IS_QLA2322(ha) && !IS_QLA6322(ha)) { 2609 /* Then erase it */ 2610 if (qla2x00_erase_flash_sector(ha, 2611 addr, sec_mask, man_id, 2612 flash_id)) { 2613 rval = QLA_FUNCTION_FAILED; 2614 break; 2615 } 2616 if (man_id == 0x01 && flash_id == 0x6d) 2617 sec_number++; 2618 } 2619 } 2620 2621 if (man_id == 0x01 && flash_id == 0x6d) { 2622 if (sec_number == 1 && 2623 addr == (rest_addr - 1)) { 2624 rest_addr = 0x0fff; 2625 sec_mask = 0x1f000; 2626 } else if (sec_number == 3 && (addr & 0x7ffe)) { 2627 rest_addr = 0x3fff; 2628 sec_mask = 0x1c000; 2629 } 2630 } 2631 2632 if (qla2x00_program_flash_address(ha, addr, *data, 2633 man_id, flash_id)) { 2634 rval = QLA_FUNCTION_FAILED; 2635 break; 2636 } 2637 cond_resched(); 2638 } 2639 } while (0); 2640 qla2x00_flash_disable(ha); 2641 2642 /* Resume HBA. */ 2643 qla2x00_resume_hba(vha); 2644 2645 return rval; 2646 } 2647 2648 void * 2649 qla24xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 2650 uint32_t offset, uint32_t length) 2651 { 2652 struct qla_hw_data *ha = vha->hw; 2653 int rc; 2654 2655 /* Suspend HBA. */ 2656 scsi_block_requests(vha->host); 2657 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2658 2659 /* Go with read. */ 2660 rc = qla24xx_read_flash_data(vha, buf, offset >> 2, length >> 2); 2661 if (rc) { 2662 ql_log(ql_log_info, vha, 0x01a0, 2663 "Unable to perform optrom read(%x).\n", rc); 2664 } 2665 2666 /* Resume HBA. */ 2667 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 2668 scsi_unblock_requests(vha->host); 2669 2670 return buf; 2671 } 2672 2673 static int 2674 qla28xx_extract_sfub_and_verify(struct scsi_qla_host *vha, __le32 *buf, 2675 uint32_t len, uint32_t buf_size_without_sfub, uint8_t *sfub_buf) 2676 { 2677 uint32_t check_sum = 0; 2678 __le32 *p; 2679 int i; 2680 2681 p = buf + buf_size_without_sfub; 2682 2683 /* Extract SFUB from end of file */ 2684 memcpy(sfub_buf, (uint8_t *)p, 2685 sizeof(struct secure_flash_update_block)); 2686 2687 for (i = 0; i < (sizeof(struct secure_flash_update_block) >> 2); i++) 2688 check_sum += le32_to_cpu(p[i]); 2689 2690 check_sum = (~check_sum) + 1; 2691 2692 if (check_sum != le32_to_cpu(p[i])) { 2693 ql_log(ql_log_warn, vha, 0x7097, 2694 "SFUB checksum failed, 0x%x, 0x%x\n", 2695 check_sum, le32_to_cpu(p[i])); 2696 return QLA_COMMAND_ERROR; 2697 } 2698 2699 return QLA_SUCCESS; 2700 } 2701 2702 static int 2703 qla28xx_get_flash_region(struct scsi_qla_host *vha, uint32_t start, 2704 struct qla_flt_region *region) 2705 { 2706 struct qla_hw_data *ha = vha->hw; 2707 struct qla_flt_header *flt = ha->flt; 2708 struct qla_flt_region *flt_reg = &flt->region[0]; 2709 uint16_t cnt; 2710 int rval = QLA_FUNCTION_FAILED; 2711 2712 if (!ha->flt) 2713 return QLA_FUNCTION_FAILED; 2714 2715 cnt = le16_to_cpu(flt->length) / sizeof(struct qla_flt_region); 2716 for (; cnt; cnt--, flt_reg++) { 2717 if (le32_to_cpu(flt_reg->start) == start) { 2718 memcpy((uint8_t *)region, flt_reg, 2719 sizeof(struct qla_flt_region)); 2720 rval = QLA_SUCCESS; 2721 break; 2722 } 2723 } 2724 2725 return rval; 2726 } 2727 2728 static int 2729 qla28xx_write_flash_data(scsi_qla_host_t *vha, uint32_t *dwptr, uint32_t faddr, 2730 uint32_t dwords) 2731 { 2732 struct qla_hw_data *ha = vha->hw; 2733 ulong liter; 2734 ulong dburst = OPTROM_BURST_DWORDS; /* burst size in dwords */ 2735 uint32_t sec_mask, rest_addr, fdata; 2736 void *optrom = NULL; 2737 dma_addr_t optrom_dma; 2738 int rval, ret; 2739 struct secure_flash_update_block *sfub; 2740 dma_addr_t sfub_dma; 2741 uint32_t offset = faddr << 2; 2742 uint32_t buf_size_without_sfub = 0; 2743 struct qla_flt_region region; 2744 bool reset_to_rom = false; 2745 uint32_t risc_size, risc_attr = 0; 2746 __be32 *fw_array = NULL; 2747 2748 /* Retrieve region info - must be a start address passed in */ 2749 rval = qla28xx_get_flash_region(vha, offset, ®ion); 2750 2751 if (rval != QLA_SUCCESS) { 2752 ql_log(ql_log_warn, vha, 0xffff, 2753 "Invalid address %x - not a region start address\n", 2754 offset); 2755 goto done; 2756 } 2757 2758 /* Allocate dma buffer for burst write */ 2759 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 2760 &optrom_dma, GFP_KERNEL); 2761 if (!optrom) { 2762 ql_log(ql_log_warn, vha, 0x7095, 2763 "Failed allocate burst (%x bytes)\n", OPTROM_BURST_SIZE); 2764 rval = QLA_COMMAND_ERROR; 2765 goto done; 2766 } 2767 2768 /* 2769 * If adapter supports secure flash and region is secure 2770 * extract secure flash update block (SFUB) and verify 2771 */ 2772 if (ha->flags.secure_adapter && region.attribute) { 2773 2774 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2775 "Region %x is secure\n", le16_to_cpu(region.code)); 2776 2777 switch (le16_to_cpu(region.code)) { 2778 case FLT_REG_FW: 2779 case FLT_REG_FW_SEC_27XX: 2780 case FLT_REG_MPI_PRI_28XX: 2781 case FLT_REG_MPI_SEC_28XX: 2782 fw_array = (__force __be32 *)dwptr; 2783 2784 /* 1st fw array */ 2785 risc_size = be32_to_cpu(fw_array[3]); 2786 risc_attr = be32_to_cpu(fw_array[9]); 2787 2788 buf_size_without_sfub = risc_size; 2789 fw_array += risc_size; 2790 2791 /* 2nd fw array */ 2792 risc_size = be32_to_cpu(fw_array[3]); 2793 2794 buf_size_without_sfub += risc_size; 2795 fw_array += risc_size; 2796 2797 /* 1st dump template */ 2798 risc_size = be32_to_cpu(fw_array[2]); 2799 2800 /* skip header and ignore checksum */ 2801 buf_size_without_sfub += risc_size; 2802 fw_array += risc_size; 2803 2804 if (risc_attr & BIT_9) { 2805 /* 2nd dump template */ 2806 risc_size = be32_to_cpu(fw_array[2]); 2807 2808 /* skip header and ignore checksum */ 2809 buf_size_without_sfub += risc_size; 2810 fw_array += risc_size; 2811 } 2812 break; 2813 2814 case FLT_REG_PEP_PRI_28XX: 2815 case FLT_REG_PEP_SEC_28XX: 2816 fw_array = (__force __be32 *)dwptr; 2817 2818 /* 1st fw array */ 2819 risc_size = be32_to_cpu(fw_array[3]); 2820 risc_attr = be32_to_cpu(fw_array[9]); 2821 2822 buf_size_without_sfub = risc_size; 2823 fw_array += risc_size; 2824 break; 2825 2826 default: 2827 ql_log(ql_log_warn + ql_dbg_verbose, vha, 2828 0xffff, "Secure region %x not supported\n", 2829 le16_to_cpu(region.code)); 2830 rval = QLA_COMMAND_ERROR; 2831 goto done; 2832 } 2833 2834 sfub = dma_alloc_coherent(&ha->pdev->dev, 2835 sizeof(struct secure_flash_update_block), &sfub_dma, 2836 GFP_KERNEL); 2837 if (!sfub) { 2838 ql_log(ql_log_warn, vha, 0xffff, 2839 "Unable to allocate memory for SFUB\n"); 2840 rval = QLA_COMMAND_ERROR; 2841 goto done; 2842 } 2843 2844 rval = qla28xx_extract_sfub_and_verify(vha, (__le32 *)dwptr, 2845 dwords, buf_size_without_sfub, (uint8_t *)sfub); 2846 2847 if (rval != QLA_SUCCESS) 2848 goto done; 2849 2850 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2851 "SFUB extract and verify successful\n"); 2852 } 2853 2854 rest_addr = (ha->fdt_block_size >> 2) - 1; 2855 sec_mask = ~rest_addr; 2856 2857 /* Lock semaphore */ 2858 rval = qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_LOCK); 2859 if (rval != QLA_SUCCESS) { 2860 ql_log(ql_log_warn, vha, 0xffff, 2861 "Unable to lock flash semaphore."); 2862 goto done; 2863 } 2864 2865 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2866 "Unprotect flash...\n"); 2867 rval = qla24xx_unprotect_flash(vha); 2868 if (rval) { 2869 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK); 2870 ql_log(ql_log_warn, vha, 0x7096, "Failed unprotect flash\n"); 2871 goto done; 2872 } 2873 2874 for (liter = 0; liter < dwords; liter++, faddr++) { 2875 fdata = (faddr & sec_mask) << 2; 2876 2877 /* If start of sector */ 2878 if (!(faddr & rest_addr)) { 2879 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2880 "Erase sector %#x...\n", faddr); 2881 rval = qla24xx_erase_sector(vha, fdata); 2882 if (rval) { 2883 ql_dbg(ql_dbg_user, vha, 0x7007, 2884 "Failed erase sector %#x\n", faddr); 2885 goto write_protect; 2886 } 2887 } 2888 } 2889 2890 if (ha->flags.secure_adapter) { 2891 /* 2892 * If adapter supports secure flash but FW doesn't, 2893 * disable write protect, release semaphore and reset 2894 * chip to execute ROM code in order to update region securely 2895 */ 2896 if (!ha->flags.secure_fw) { 2897 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2898 "Disable Write and Release Semaphore."); 2899 rval = qla24xx_protect_flash(vha); 2900 if (rval != QLA_SUCCESS) { 2901 qla81xx_fac_semaphore_access(vha, 2902 FAC_SEMAPHORE_UNLOCK); 2903 ql_log(ql_log_warn, vha, 0xffff, 2904 "Unable to protect flash."); 2905 goto done; 2906 } 2907 2908 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2909 "Reset chip to ROM."); 2910 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 2911 set_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags); 2912 qla2xxx_wake_dpc(vha); 2913 rval = qla2x00_wait_for_chip_reset(vha); 2914 if (rval != QLA_SUCCESS) { 2915 ql_log(ql_log_warn, vha, 0xffff, 2916 "Unable to reset to ROM code."); 2917 goto done; 2918 } 2919 reset_to_rom = true; 2920 ha->flags.fac_supported = 0; 2921 2922 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2923 "Lock Semaphore"); 2924 rval = qla2xxx_write_remote_register(vha, 2925 FLASH_SEMAPHORE_REGISTER_ADDR, 0x00020002); 2926 if (rval != QLA_SUCCESS) { 2927 ql_log(ql_log_warn, vha, 0xffff, 2928 "Unable to lock flash semaphore."); 2929 goto done; 2930 } 2931 2932 /* Unprotect flash */ 2933 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2934 "Enable Write."); 2935 rval = qla2x00_write_ram_word(vha, 0x7ffd0101, 0); 2936 if (rval) { 2937 ql_log(ql_log_warn, vha, 0x7096, 2938 "Failed unprotect flash\n"); 2939 goto done; 2940 } 2941 } 2942 2943 /* If region is secure, send Secure Flash MB Cmd */ 2944 if (region.attribute && buf_size_without_sfub) { 2945 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0xffff, 2946 "Sending Secure Flash MB Cmd\n"); 2947 rval = qla28xx_secure_flash_update(vha, 0, 2948 le16_to_cpu(region.code), 2949 buf_size_without_sfub, sfub_dma, 2950 sizeof(struct secure_flash_update_block) >> 2); 2951 if (rval != QLA_SUCCESS) { 2952 ql_log(ql_log_warn, vha, 0xffff, 2953 "Secure Flash MB Cmd failed %x.", rval); 2954 goto write_protect; 2955 } 2956 } 2957 2958 } 2959 2960 /* re-init flash offset */ 2961 faddr = offset >> 2; 2962 2963 for (liter = 0; liter < dwords; liter++, faddr++, dwptr++) { 2964 fdata = (faddr & sec_mask) << 2; 2965 2966 /* If smaller than a burst remaining */ 2967 if (dwords - liter < dburst) 2968 dburst = dwords - liter; 2969 2970 /* Copy to dma buffer */ 2971 memcpy(optrom, dwptr, dburst << 2); 2972 2973 /* Burst write */ 2974 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2975 "Write burst (%#lx dwords)...\n", dburst); 2976 rval = qla2x00_load_ram(vha, optrom_dma, 2977 flash_data_addr(ha, faddr), dburst); 2978 if (rval != QLA_SUCCESS) { 2979 ql_log(ql_log_warn, vha, 0x7097, 2980 "Failed burst write at %x (%p/%#llx)...\n", 2981 flash_data_addr(ha, faddr), optrom, 2982 (u64)optrom_dma); 2983 break; 2984 } 2985 2986 liter += dburst - 1; 2987 faddr += dburst - 1; 2988 dwptr += dburst - 1; 2989 } 2990 2991 write_protect: 2992 ql_log(ql_log_warn + ql_dbg_verbose, vha, 0x7095, 2993 "Protect flash...\n"); 2994 ret = qla24xx_protect_flash(vha); 2995 if (ret) { 2996 qla81xx_fac_semaphore_access(vha, FAC_SEMAPHORE_UNLOCK); 2997 ql_log(ql_log_warn, vha, 0x7099, 2998 "Failed protect flash\n"); 2999 rval = QLA_COMMAND_ERROR; 3000 } 3001 3002 if (reset_to_rom == true) { 3003 /* Schedule DPC to restart the RISC */ 3004 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags); 3005 qla2xxx_wake_dpc(vha); 3006 3007 ret = qla2x00_wait_for_hba_online(vha); 3008 if (ret != QLA_SUCCESS) { 3009 ql_log(ql_log_warn, vha, 0xffff, 3010 "Adapter did not come out of reset\n"); 3011 rval = QLA_COMMAND_ERROR; 3012 } 3013 } 3014 3015 done: 3016 if (optrom) 3017 dma_free_coherent(&ha->pdev->dev, 3018 OPTROM_BURST_SIZE, optrom, optrom_dma); 3019 3020 return rval; 3021 } 3022 3023 int 3024 qla24xx_write_optrom_data(struct scsi_qla_host *vha, void *buf, 3025 uint32_t offset, uint32_t length) 3026 { 3027 int rval; 3028 struct qla_hw_data *ha = vha->hw; 3029 3030 /* Suspend HBA. */ 3031 scsi_block_requests(vha->host); 3032 set_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 3033 3034 /* Go with write. */ 3035 if (IS_QLA28XX(ha)) 3036 rval = qla28xx_write_flash_data(vha, buf, offset >> 2, 3037 length >> 2); 3038 else 3039 rval = qla24xx_write_flash_data(vha, buf, offset >> 2, 3040 length >> 2); 3041 3042 clear_bit(MBX_UPDATE_FLASH_ACTIVE, &ha->mbx_cmd_flags); 3043 scsi_unblock_requests(vha->host); 3044 3045 return rval; 3046 } 3047 3048 void * 3049 qla25xx_read_optrom_data(struct scsi_qla_host *vha, void *buf, 3050 uint32_t offset, uint32_t length) 3051 { 3052 int rval; 3053 dma_addr_t optrom_dma; 3054 void *optrom; 3055 uint8_t *pbuf; 3056 uint32_t faddr, left, burst; 3057 struct qla_hw_data *ha = vha->hw; 3058 3059 if (IS_QLA25XX(ha) || IS_QLA81XX(ha) || IS_QLA83XX(ha) || 3060 IS_QLA27XX(ha) || IS_QLA28XX(ha)) 3061 goto try_fast; 3062 if (offset & 0xfff) 3063 goto slow_read; 3064 if (length < OPTROM_BURST_SIZE) 3065 goto slow_read; 3066 3067 try_fast: 3068 if (offset & 0xff) 3069 goto slow_read; 3070 optrom = dma_alloc_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3071 &optrom_dma, GFP_KERNEL); 3072 if (!optrom) { 3073 ql_log(ql_log_warn, vha, 0x00cc, 3074 "Unable to allocate memory for optrom burst read (%x KB).\n", 3075 OPTROM_BURST_SIZE / 1024); 3076 goto slow_read; 3077 } 3078 3079 pbuf = buf; 3080 faddr = offset >> 2; 3081 left = length >> 2; 3082 burst = OPTROM_BURST_DWORDS; 3083 while (left != 0) { 3084 if (burst > left) 3085 burst = left; 3086 3087 rval = qla2x00_dump_ram(vha, optrom_dma, 3088 flash_data_addr(ha, faddr), burst); 3089 if (rval) { 3090 ql_log(ql_log_warn, vha, 0x00f5, 3091 "Unable to burst-read optrom segment (%x/%x/%llx).\n", 3092 rval, flash_data_addr(ha, faddr), 3093 (unsigned long long)optrom_dma); 3094 ql_log(ql_log_warn, vha, 0x00f6, 3095 "Reverting to slow-read.\n"); 3096 3097 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, 3098 optrom, optrom_dma); 3099 goto slow_read; 3100 } 3101 3102 memcpy(pbuf, optrom, burst * 4); 3103 3104 left -= burst; 3105 faddr += burst; 3106 pbuf += burst * 4; 3107 } 3108 3109 dma_free_coherent(&ha->pdev->dev, OPTROM_BURST_SIZE, optrom, 3110 optrom_dma); 3111 3112 return buf; 3113 3114 slow_read: 3115 return qla24xx_read_optrom_data(vha, buf, offset, length); 3116 } 3117 3118 /** 3119 * qla2x00_get_fcode_version() - Determine an FCODE image's version. 3120 * @ha: HA context 3121 * @pcids: Pointer to the FCODE PCI data structure 3122 * 3123 * The process of retrieving the FCODE version information is at best 3124 * described as interesting. 3125 * 3126 * Within the first 100h bytes of the image an ASCII string is present 3127 * which contains several pieces of information including the FCODE 3128 * version. Unfortunately it seems the only reliable way to retrieve 3129 * the version is by scanning for another sentinel within the string, 3130 * the FCODE build date: 3131 * 3132 * ... 2.00.02 10/17/02 ... 3133 * 3134 * Returns QLA_SUCCESS on successful retrieval of version. 3135 */ 3136 static void 3137 qla2x00_get_fcode_version(struct qla_hw_data *ha, uint32_t pcids) 3138 { 3139 int ret = QLA_FUNCTION_FAILED; 3140 uint32_t istart, iend, iter, vend; 3141 uint8_t do_next, rbyte, *vbyte; 3142 3143 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3144 3145 /* Skip the PCI data structure. */ 3146 istart = pcids + 3147 ((qla2x00_read_flash_byte(ha, pcids + 0x0B) << 8) | 3148 qla2x00_read_flash_byte(ha, pcids + 0x0A)); 3149 iend = istart + 0x100; 3150 do { 3151 /* Scan for the sentinel date string...eeewww. */ 3152 do_next = 0; 3153 iter = istart; 3154 while ((iter < iend) && !do_next) { 3155 iter++; 3156 if (qla2x00_read_flash_byte(ha, iter) == '/') { 3157 if (qla2x00_read_flash_byte(ha, iter + 2) == 3158 '/') 3159 do_next++; 3160 else if (qla2x00_read_flash_byte(ha, 3161 iter + 3) == '/') 3162 do_next++; 3163 } 3164 } 3165 if (!do_next) 3166 break; 3167 3168 /* Backtrack to previous ' ' (space). */ 3169 do_next = 0; 3170 while ((iter > istart) && !do_next) { 3171 iter--; 3172 if (qla2x00_read_flash_byte(ha, iter) == ' ') 3173 do_next++; 3174 } 3175 if (!do_next) 3176 break; 3177 3178 /* 3179 * Mark end of version tag, and find previous ' ' (space) or 3180 * string length (recent FCODE images -- major hack ahead!!!). 3181 */ 3182 vend = iter - 1; 3183 do_next = 0; 3184 while ((iter > istart) && !do_next) { 3185 iter--; 3186 rbyte = qla2x00_read_flash_byte(ha, iter); 3187 if (rbyte == ' ' || rbyte == 0xd || rbyte == 0x10) 3188 do_next++; 3189 } 3190 if (!do_next) 3191 break; 3192 3193 /* Mark beginning of version tag, and copy data. */ 3194 iter++; 3195 if ((vend - iter) && 3196 ((vend - iter) < sizeof(ha->fcode_revision))) { 3197 vbyte = ha->fcode_revision; 3198 while (iter <= vend) { 3199 *vbyte++ = qla2x00_read_flash_byte(ha, iter); 3200 iter++; 3201 } 3202 ret = QLA_SUCCESS; 3203 } 3204 } while (0); 3205 3206 if (ret != QLA_SUCCESS) 3207 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3208 } 3209 3210 int 3211 qla2x00_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3212 { 3213 int ret = QLA_SUCCESS; 3214 uint8_t code_type, last_image; 3215 uint32_t pcihdr, pcids; 3216 uint8_t *dbyte; 3217 uint16_t *dcode; 3218 struct qla_hw_data *ha = vha->hw; 3219 3220 if (!ha->pio_address || !mbuf) 3221 return QLA_FUNCTION_FAILED; 3222 3223 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3224 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3225 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3226 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3227 3228 qla2x00_flash_enable(ha); 3229 3230 /* Begin with first PCI expansion ROM header. */ 3231 pcihdr = 0; 3232 last_image = 1; 3233 do { 3234 /* Verify PCI expansion ROM header. */ 3235 if (qla2x00_read_flash_byte(ha, pcihdr) != 0x55 || 3236 qla2x00_read_flash_byte(ha, pcihdr + 0x01) != 0xaa) { 3237 /* No signature */ 3238 ql_log(ql_log_fatal, vha, 0x0050, 3239 "No matching ROM signature.\n"); 3240 ret = QLA_FUNCTION_FAILED; 3241 break; 3242 } 3243 3244 /* Locate PCI data structure. */ 3245 pcids = pcihdr + 3246 ((qla2x00_read_flash_byte(ha, pcihdr + 0x19) << 8) | 3247 qla2x00_read_flash_byte(ha, pcihdr + 0x18)); 3248 3249 /* Validate signature of PCI data structure. */ 3250 if (qla2x00_read_flash_byte(ha, pcids) != 'P' || 3251 qla2x00_read_flash_byte(ha, pcids + 0x1) != 'C' || 3252 qla2x00_read_flash_byte(ha, pcids + 0x2) != 'I' || 3253 qla2x00_read_flash_byte(ha, pcids + 0x3) != 'R') { 3254 /* Incorrect header. */ 3255 ql_log(ql_log_fatal, vha, 0x0051, 3256 "PCI data struct not found pcir_adr=%x.\n", pcids); 3257 ret = QLA_FUNCTION_FAILED; 3258 break; 3259 } 3260 3261 /* Read version */ 3262 code_type = qla2x00_read_flash_byte(ha, pcids + 0x14); 3263 switch (code_type) { 3264 case ROM_CODE_TYPE_BIOS: 3265 /* Intel x86, PC-AT compatible. */ 3266 ha->bios_revision[0] = 3267 qla2x00_read_flash_byte(ha, pcids + 0x12); 3268 ha->bios_revision[1] = 3269 qla2x00_read_flash_byte(ha, pcids + 0x13); 3270 ql_dbg(ql_dbg_init, vha, 0x0052, 3271 "Read BIOS %d.%d.\n", 3272 ha->bios_revision[1], ha->bios_revision[0]); 3273 break; 3274 case ROM_CODE_TYPE_FCODE: 3275 /* Open Firmware standard for PCI (FCode). */ 3276 /* Eeeewww... */ 3277 qla2x00_get_fcode_version(ha, pcids); 3278 break; 3279 case ROM_CODE_TYPE_EFI: 3280 /* Extensible Firmware Interface (EFI). */ 3281 ha->efi_revision[0] = 3282 qla2x00_read_flash_byte(ha, pcids + 0x12); 3283 ha->efi_revision[1] = 3284 qla2x00_read_flash_byte(ha, pcids + 0x13); 3285 ql_dbg(ql_dbg_init, vha, 0x0053, 3286 "Read EFI %d.%d.\n", 3287 ha->efi_revision[1], ha->efi_revision[0]); 3288 break; 3289 default: 3290 ql_log(ql_log_warn, vha, 0x0054, 3291 "Unrecognized code type %x at pcids %x.\n", 3292 code_type, pcids); 3293 break; 3294 } 3295 3296 last_image = qla2x00_read_flash_byte(ha, pcids + 0x15) & BIT_7; 3297 3298 /* Locate next PCI expansion ROM. */ 3299 pcihdr += ((qla2x00_read_flash_byte(ha, pcids + 0x11) << 8) | 3300 qla2x00_read_flash_byte(ha, pcids + 0x10)) * 512; 3301 } while (!last_image); 3302 3303 if (IS_QLA2322(ha)) { 3304 /* Read firmware image information. */ 3305 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3306 dbyte = mbuf; 3307 memset(dbyte, 0, 8); 3308 dcode = (uint16_t *)dbyte; 3309 3310 qla2x00_read_flash_data(ha, dbyte, ha->flt_region_fw * 4 + 10, 3311 8); 3312 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010a, 3313 "Dumping fw " 3314 "ver from flash:.\n"); 3315 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010b, 3316 dbyte, 32); 3317 3318 if ((dcode[0] == 0xffff && dcode[1] == 0xffff && 3319 dcode[2] == 0xffff && dcode[3] == 0xffff) || 3320 (dcode[0] == 0 && dcode[1] == 0 && dcode[2] == 0 && 3321 dcode[3] == 0)) { 3322 ql_log(ql_log_warn, vha, 0x0057, 3323 "Unrecognized fw revision at %x.\n", 3324 ha->flt_region_fw * 4); 3325 } else { 3326 /* values are in big endian */ 3327 ha->fw_revision[0] = dbyte[0] << 16 | dbyte[1]; 3328 ha->fw_revision[1] = dbyte[2] << 16 | dbyte[3]; 3329 ha->fw_revision[2] = dbyte[4] << 16 | dbyte[5]; 3330 ql_dbg(ql_dbg_init, vha, 0x0058, 3331 "FW Version: " 3332 "%d.%d.%d.\n", ha->fw_revision[0], 3333 ha->fw_revision[1], ha->fw_revision[2]); 3334 } 3335 } 3336 3337 qla2x00_flash_disable(ha); 3338 3339 return ret; 3340 } 3341 3342 int 3343 qla82xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3344 { 3345 int ret = QLA_SUCCESS; 3346 uint32_t pcihdr, pcids; 3347 uint32_t *dcode = mbuf; 3348 uint8_t *bcode = mbuf; 3349 uint8_t code_type, last_image; 3350 struct qla_hw_data *ha = vha->hw; 3351 3352 if (!mbuf) 3353 return QLA_FUNCTION_FAILED; 3354 3355 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3356 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3357 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3358 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3359 3360 /* Begin with first PCI expansion ROM header. */ 3361 pcihdr = ha->flt_region_boot << 2; 3362 last_image = 1; 3363 do { 3364 /* Verify PCI expansion ROM header. */ 3365 ha->isp_ops->read_optrom(vha, dcode, pcihdr, 0x20 * 4); 3366 bcode = mbuf + (pcihdr % 4); 3367 if (memcmp(bcode, "\x55\xaa", 2)) { 3368 /* No signature */ 3369 ql_log(ql_log_fatal, vha, 0x0154, 3370 "No matching ROM signature.\n"); 3371 ret = QLA_FUNCTION_FAILED; 3372 break; 3373 } 3374 3375 /* Locate PCI data structure. */ 3376 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 3377 3378 ha->isp_ops->read_optrom(vha, dcode, pcids, 0x20 * 4); 3379 bcode = mbuf + (pcihdr % 4); 3380 3381 /* Validate signature of PCI data structure. */ 3382 if (memcmp(bcode, "PCIR", 4)) { 3383 /* Incorrect header. */ 3384 ql_log(ql_log_fatal, vha, 0x0155, 3385 "PCI data struct not found pcir_adr=%x.\n", pcids); 3386 ret = QLA_FUNCTION_FAILED; 3387 break; 3388 } 3389 3390 /* Read version */ 3391 code_type = bcode[0x14]; 3392 switch (code_type) { 3393 case ROM_CODE_TYPE_BIOS: 3394 /* Intel x86, PC-AT compatible. */ 3395 ha->bios_revision[0] = bcode[0x12]; 3396 ha->bios_revision[1] = bcode[0x13]; 3397 ql_dbg(ql_dbg_init, vha, 0x0156, 3398 "Read BIOS %d.%d.\n", 3399 ha->bios_revision[1], ha->bios_revision[0]); 3400 break; 3401 case ROM_CODE_TYPE_FCODE: 3402 /* Open Firmware standard for PCI (FCode). */ 3403 ha->fcode_revision[0] = bcode[0x12]; 3404 ha->fcode_revision[1] = bcode[0x13]; 3405 ql_dbg(ql_dbg_init, vha, 0x0157, 3406 "Read FCODE %d.%d.\n", 3407 ha->fcode_revision[1], ha->fcode_revision[0]); 3408 break; 3409 case ROM_CODE_TYPE_EFI: 3410 /* Extensible Firmware Interface (EFI). */ 3411 ha->efi_revision[0] = bcode[0x12]; 3412 ha->efi_revision[1] = bcode[0x13]; 3413 ql_dbg(ql_dbg_init, vha, 0x0158, 3414 "Read EFI %d.%d.\n", 3415 ha->efi_revision[1], ha->efi_revision[0]); 3416 break; 3417 default: 3418 ql_log(ql_log_warn, vha, 0x0159, 3419 "Unrecognized code type %x at pcids %x.\n", 3420 code_type, pcids); 3421 break; 3422 } 3423 3424 last_image = bcode[0x15] & BIT_7; 3425 3426 /* Locate next PCI expansion ROM. */ 3427 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 3428 } while (!last_image); 3429 3430 /* Read firmware image information. */ 3431 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3432 dcode = mbuf; 3433 ha->isp_ops->read_optrom(vha, dcode, ha->flt_region_fw << 2, 0x20); 3434 bcode = mbuf + (pcihdr % 4); 3435 3436 /* Validate signature of PCI data structure. */ 3437 if (bcode[0x0] == 0x3 && bcode[0x1] == 0x0 && 3438 bcode[0x2] == 0x40 && bcode[0x3] == 0x40) { 3439 ha->fw_revision[0] = bcode[0x4]; 3440 ha->fw_revision[1] = bcode[0x5]; 3441 ha->fw_revision[2] = bcode[0x6]; 3442 ql_dbg(ql_dbg_init, vha, 0x0153, 3443 "Firmware revision %d.%d.%d\n", 3444 ha->fw_revision[0], ha->fw_revision[1], 3445 ha->fw_revision[2]); 3446 } 3447 3448 return ret; 3449 } 3450 3451 int 3452 qla24xx_get_flash_version(scsi_qla_host_t *vha, void *mbuf) 3453 { 3454 int ret = QLA_SUCCESS; 3455 uint32_t pcihdr = 0, pcids = 0; 3456 uint32_t *dcode = mbuf; 3457 uint8_t *bcode = mbuf; 3458 uint8_t code_type, last_image; 3459 int i; 3460 struct qla_hw_data *ha = vha->hw; 3461 uint32_t faddr = 0; 3462 struct active_regions active_regions = { }; 3463 3464 if (IS_P3P_TYPE(ha)) 3465 return QLA_SUCCESS; 3466 3467 if (!mbuf) 3468 return QLA_FUNCTION_FAILED; 3469 3470 memset(ha->bios_revision, 0, sizeof(ha->bios_revision)); 3471 memset(ha->efi_revision, 0, sizeof(ha->efi_revision)); 3472 memset(ha->fcode_revision, 0, sizeof(ha->fcode_revision)); 3473 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3474 3475 pcihdr = ha->flt_region_boot << 2; 3476 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3477 qla27xx_get_active_image(vha, &active_regions); 3478 if (active_regions.global == QLA27XX_SECONDARY_IMAGE) { 3479 pcihdr = ha->flt_region_boot_sec << 2; 3480 } 3481 } 3482 3483 do { 3484 /* Verify PCI expansion ROM header. */ 3485 ret = qla24xx_read_flash_data(vha, dcode, pcihdr >> 2, 0x20); 3486 if (ret) { 3487 ql_log(ql_log_info, vha, 0x017d, 3488 "Unable to read PCI EXP Rom Header(%x).\n", ret); 3489 return QLA_FUNCTION_FAILED; 3490 } 3491 3492 bcode = mbuf + (pcihdr % 4); 3493 if (memcmp(bcode, "\x55\xaa", 2)) { 3494 /* No signature */ 3495 ql_log(ql_log_fatal, vha, 0x0059, 3496 "No matching ROM signature.\n"); 3497 return QLA_FUNCTION_FAILED; 3498 } 3499 3500 /* Locate PCI data structure. */ 3501 pcids = pcihdr + ((bcode[0x19] << 8) | bcode[0x18]); 3502 3503 ret = qla24xx_read_flash_data(vha, dcode, pcids >> 2, 0x20); 3504 if (ret) { 3505 ql_log(ql_log_info, vha, 0x018e, 3506 "Unable to read PCI Data Structure (%x).\n", ret); 3507 return QLA_FUNCTION_FAILED; 3508 } 3509 3510 bcode = mbuf + (pcihdr % 4); 3511 3512 /* Validate signature of PCI data structure. */ 3513 if (memcmp(bcode, "PCIR", 4)) { 3514 /* Incorrect header. */ 3515 ql_log(ql_log_fatal, vha, 0x005a, 3516 "PCI data struct not found pcir_adr=%x.\n", pcids); 3517 ql_dump_buffer(ql_dbg_init, vha, 0x0059, dcode, 32); 3518 return QLA_FUNCTION_FAILED; 3519 } 3520 3521 /* Read version */ 3522 code_type = bcode[0x14]; 3523 switch (code_type) { 3524 case ROM_CODE_TYPE_BIOS: 3525 /* Intel x86, PC-AT compatible. */ 3526 ha->bios_revision[0] = bcode[0x12]; 3527 ha->bios_revision[1] = bcode[0x13]; 3528 ql_dbg(ql_dbg_init, vha, 0x005b, 3529 "Read BIOS %d.%d.\n", 3530 ha->bios_revision[1], ha->bios_revision[0]); 3531 break; 3532 case ROM_CODE_TYPE_FCODE: 3533 /* Open Firmware standard for PCI (FCode). */ 3534 ha->fcode_revision[0] = bcode[0x12]; 3535 ha->fcode_revision[1] = bcode[0x13]; 3536 ql_dbg(ql_dbg_init, vha, 0x005c, 3537 "Read FCODE %d.%d.\n", 3538 ha->fcode_revision[1], ha->fcode_revision[0]); 3539 break; 3540 case ROM_CODE_TYPE_EFI: 3541 /* Extensible Firmware Interface (EFI). */ 3542 ha->efi_revision[0] = bcode[0x12]; 3543 ha->efi_revision[1] = bcode[0x13]; 3544 ql_dbg(ql_dbg_init, vha, 0x005d, 3545 "Read EFI %d.%d.\n", 3546 ha->efi_revision[1], ha->efi_revision[0]); 3547 break; 3548 default: 3549 ql_log(ql_log_warn, vha, 0x005e, 3550 "Unrecognized code type %x at pcids %x.\n", 3551 code_type, pcids); 3552 break; 3553 } 3554 3555 last_image = bcode[0x15] & BIT_7; 3556 3557 /* Locate next PCI expansion ROM. */ 3558 pcihdr += ((bcode[0x11] << 8) | bcode[0x10]) * 512; 3559 } while (!last_image); 3560 3561 /* Read firmware image information. */ 3562 memset(ha->fw_revision, 0, sizeof(ha->fw_revision)); 3563 faddr = ha->flt_region_fw; 3564 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) { 3565 qla27xx_get_active_image(vha, &active_regions); 3566 if (active_regions.global == QLA27XX_SECONDARY_IMAGE) 3567 faddr = ha->flt_region_fw_sec; 3568 } 3569 3570 ret = qla24xx_read_flash_data(vha, dcode, faddr, 8); 3571 if (ret) { 3572 ql_log(ql_log_info, vha, 0x019e, 3573 "Unable to read FW version (%x).\n", ret); 3574 return ret; 3575 } else { 3576 if (qla24xx_risc_firmware_invalid(dcode)) { 3577 ql_log(ql_log_warn, vha, 0x005f, 3578 "Unrecognized fw revision at %x.\n", 3579 ha->flt_region_fw * 4); 3580 ql_dump_buffer(ql_dbg_init, vha, 0x005f, dcode, 32); 3581 } else { 3582 for (i = 0; i < 4; i++) 3583 ha->fw_revision[i] = 3584 be32_to_cpu((__force __be32)dcode[4+i]); 3585 ql_dbg(ql_dbg_init, vha, 0x0060, 3586 "Firmware revision (flash) %u.%u.%u (%x).\n", 3587 ha->fw_revision[0], ha->fw_revision[1], 3588 ha->fw_revision[2], ha->fw_revision[3]); 3589 } 3590 } 3591 3592 /* Check for golden firmware and get version if available */ 3593 if (!IS_QLA81XX(ha)) { 3594 /* Golden firmware is not present in non 81XX adapters */ 3595 return ret; 3596 } 3597 3598 memset(ha->gold_fw_version, 0, sizeof(ha->gold_fw_version)); 3599 faddr = ha->flt_region_gold_fw; 3600 ret = qla24xx_read_flash_data(vha, dcode, ha->flt_region_gold_fw, 8); 3601 if (ret) { 3602 ql_log(ql_log_info, vha, 0x019f, 3603 "Unable to read Gold FW version (%x).\n", ret); 3604 return ret; 3605 } else { 3606 if (qla24xx_risc_firmware_invalid(dcode)) { 3607 ql_log(ql_log_warn, vha, 0x0056, 3608 "Unrecognized golden fw at %#x.\n", faddr); 3609 ql_dump_buffer(ql_dbg_init, vha, 0x0056, dcode, 32); 3610 return QLA_FUNCTION_FAILED; 3611 } 3612 3613 for (i = 0; i < 4; i++) 3614 ha->gold_fw_version[i] = 3615 be32_to_cpu((__force __be32)dcode[4+i]); 3616 } 3617 return ret; 3618 } 3619 3620 static int 3621 qla2xxx_is_vpd_valid(uint8_t *pos, uint8_t *end) 3622 { 3623 if (pos >= end || *pos != 0x82) 3624 return 0; 3625 3626 pos += 3 + pos[1]; 3627 if (pos >= end || *pos != 0x90) 3628 return 0; 3629 3630 pos += 3 + pos[1]; 3631 if (pos >= end || *pos != 0x78) 3632 return 0; 3633 3634 return 1; 3635 } 3636 3637 int 3638 qla2xxx_get_vpd_field(scsi_qla_host_t *vha, char *key, char *str, size_t size) 3639 { 3640 struct qla_hw_data *ha = vha->hw; 3641 uint8_t *pos = ha->vpd; 3642 uint8_t *end = pos + ha->vpd_size; 3643 int len = 0; 3644 3645 if (!IS_FWI2_CAPABLE(ha) || !qla2xxx_is_vpd_valid(pos, end)) 3646 return 0; 3647 3648 while (pos < end && *pos != 0x78) { 3649 len = (*pos == 0x82) ? pos[1] : pos[2]; 3650 3651 if (!strncmp(pos, key, strlen(key))) 3652 break; 3653 3654 if (*pos != 0x90 && *pos != 0x91) 3655 pos += len; 3656 3657 pos += 3; 3658 } 3659 3660 if (pos < end - len && *pos != 0x78) 3661 return scnprintf(str, size, "%.*s", len, pos + 3); 3662 3663 return 0; 3664 } 3665 3666 int 3667 qla24xx_read_fcp_prio_cfg(scsi_qla_host_t *vha) 3668 { 3669 int len, max_len; 3670 uint32_t fcp_prio_addr; 3671 struct qla_hw_data *ha = vha->hw; 3672 3673 if (!ha->fcp_prio_cfg) { 3674 ha->fcp_prio_cfg = vmalloc(FCP_PRIO_CFG_SIZE); 3675 if (!ha->fcp_prio_cfg) { 3676 ql_log(ql_log_warn, vha, 0x00d5, 3677 "Unable to allocate memory for fcp priority data (%x).\n", 3678 FCP_PRIO_CFG_SIZE); 3679 return QLA_FUNCTION_FAILED; 3680 } 3681 } 3682 memset(ha->fcp_prio_cfg, 0, FCP_PRIO_CFG_SIZE); 3683 3684 fcp_prio_addr = ha->flt_region_fcp_prio; 3685 3686 /* first read the fcp priority data header from flash */ 3687 ha->isp_ops->read_optrom(vha, ha->fcp_prio_cfg, 3688 fcp_prio_addr << 2, FCP_PRIO_CFG_HDR_SIZE); 3689 3690 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 0)) 3691 goto fail; 3692 3693 /* read remaining FCP CMD config data from flash */ 3694 fcp_prio_addr += (FCP_PRIO_CFG_HDR_SIZE >> 2); 3695 len = ha->fcp_prio_cfg->num_entries * sizeof(struct qla_fcp_prio_entry); 3696 max_len = FCP_PRIO_CFG_SIZE - FCP_PRIO_CFG_HDR_SIZE; 3697 3698 ha->isp_ops->read_optrom(vha, &ha->fcp_prio_cfg->entry[0], 3699 fcp_prio_addr << 2, (len < max_len ? len : max_len)); 3700 3701 /* revalidate the entire FCP priority config data, including entries */ 3702 if (!qla24xx_fcp_prio_cfg_valid(vha, ha->fcp_prio_cfg, 1)) 3703 goto fail; 3704 3705 ha->flags.fcp_prio_enabled = 1; 3706 return QLA_SUCCESS; 3707 fail: 3708 vfree(ha->fcp_prio_cfg); 3709 ha->fcp_prio_cfg = NULL; 3710 return QLA_FUNCTION_FAILED; 3711 } 3712