1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/err.h> 8 #include <linux/init.h> 9 #include <linux/interrupt.h> 10 #include <linux/irq.h> 11 #include <linux/irqchip.h> 12 #include <linux/irqdomain.h> 13 #include <linux/io.h> 14 #include <linux/kernel.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/of_address.h> 18 #include <linux/of_irq.h> 19 #include <linux/soc/qcom/irq.h> 20 #include <linux/spinlock.h> 21 #include <linux/slab.h> 22 #include <linux/types.h> 23 24 #define PDC_MAX_GPIO_IRQS 256 25 #define PDC_DRV_SIZE 0x10000 26 27 /* Valid only on HW version < 3.2 */ 28 #define IRQ_ENABLE_BANK 0x10 29 #define IRQ_ENABLE_BANK_MAX (IRQ_ENABLE_BANK + BITS_TO_BYTES(PDC_MAX_GPIO_IRQS)) 30 #define IRQ_ENABLE_BANK_INDEX_MASK GENMASK(31, 5) 31 #define IRQ_ENABLE_BANK_BIT_MASK GENMASK(4, 0) 32 #define IRQ_i_CFG 0x110 33 34 /* Valid only on HW version >= 3.2 */ 35 #define IRQ_i_CFG_IRQ_ENABLE 3 36 37 #define IRQ_i_CFG_TYPE_MASK GENMASK(2, 0) 38 39 #define PDC_VERSION_REG 0x1000 40 #define PDC_VERSION_MAJOR GENMASK(23, 16) 41 #define PDC_VERSION_MINOR GENMASK(15, 8) 42 #define PDC_VERSION_STEP GENMASK(7, 0) 43 #define PDC_VERSION(maj, min, step) (FIELD_PREP(PDC_VERSION_MAJOR, (maj)) | \ 44 FIELD_PREP(PDC_VERSION_MINOR, (min)) | \ 45 FIELD_PREP(PDC_VERSION_STEP, (step))) 46 47 /* Notable PDC versions */ 48 #define PDC_VERSION_3_2 PDC_VERSION(3, 2, 0) 49 50 struct pdc_pin_region { 51 u32 pin_base; 52 u32 parent_base; 53 u32 cnt; 54 }; 55 56 #define pin_to_hwirq(r, p) ((r)->parent_base + (p) - (r)->pin_base) 57 58 static DEFINE_RAW_SPINLOCK(pdc_lock); 59 static void __iomem *pdc_base; 60 static void __iomem *pdc_prev_base; 61 static struct pdc_pin_region *pdc_region; 62 static int pdc_region_cnt; 63 static unsigned int pdc_version; 64 static bool pdc_x1e_quirk; 65 66 static void pdc_base_reg_write(void __iomem *base, int reg, u32 i, u32 val) 67 { 68 writel_relaxed(val, base + reg + i * sizeof(u32)); 69 } 70 71 static void pdc_reg_write(int reg, u32 i, u32 val) 72 { 73 pdc_base_reg_write(pdc_base, reg, i, val); 74 } 75 76 static u32 pdc_reg_read(int reg, u32 i) 77 { 78 return readl_relaxed(pdc_base + reg + i * sizeof(u32)); 79 } 80 81 static void pdc_x1e_irq_enable_write(u32 bank, u32 enable) 82 { 83 void __iomem *base; 84 85 /* Remap the write access to work around a hardware bug on X1E */ 86 switch (bank) { 87 case 0 ... 1: 88 /* Use previous DRV (client) region and shift to bank 3-4 */ 89 base = pdc_prev_base; 90 bank += 3; 91 break; 92 case 2 ... 4: 93 /* Use our own region and shift to bank 0-2 */ 94 base = pdc_base; 95 bank -= 2; 96 break; 97 case 5: 98 /* No fixup required for bank 5 */ 99 base = pdc_base; 100 break; 101 default: 102 WARN_ON(1); 103 return; 104 } 105 106 pdc_base_reg_write(base, IRQ_ENABLE_BANK, bank, enable); 107 } 108 109 static void pdc_enable_intr_bank(int pin_out, bool on) 110 { 111 unsigned long enable; 112 u32 index, mask; 113 114 index = FIELD_GET(IRQ_ENABLE_BANK_INDEX_MASK, pin_out); 115 mask = FIELD_GET(IRQ_ENABLE_BANK_BIT_MASK, pin_out); 116 117 enable = pdc_reg_read(IRQ_ENABLE_BANK, index); 118 __assign_bit(mask, &enable, on); 119 120 if (pdc_x1e_quirk) 121 pdc_x1e_irq_enable_write(index, enable); 122 else 123 pdc_reg_write(IRQ_ENABLE_BANK, index, enable); 124 } 125 126 static void pdc_enable_intr_cfg(int pin_out, bool on) 127 { 128 unsigned long enable = pdc_reg_read(IRQ_i_CFG, pin_out); 129 130 __assign_bit(IRQ_i_CFG_IRQ_ENABLE, &enable, on); 131 pdc_reg_write(IRQ_i_CFG, pin_out, enable); 132 } 133 134 static void __pdc_enable_intr(int pin_out, bool on) 135 { 136 if (pdc_version < PDC_VERSION_3_2) 137 pdc_enable_intr_bank(pin_out, on); 138 else 139 pdc_enable_intr_cfg(pin_out, on); 140 } 141 142 static void pdc_enable_intr(struct irq_data *d, bool on) 143 { 144 unsigned long flags; 145 146 raw_spin_lock_irqsave(&pdc_lock, flags); 147 __pdc_enable_intr(d->hwirq, on); 148 raw_spin_unlock_irqrestore(&pdc_lock, flags); 149 } 150 151 static void qcom_pdc_gic_disable(struct irq_data *d) 152 { 153 pdc_enable_intr(d, false); 154 irq_chip_disable_parent(d); 155 } 156 157 static void qcom_pdc_gic_enable(struct irq_data *d) 158 { 159 pdc_enable_intr(d, true); 160 irq_chip_enable_parent(d); 161 } 162 163 /* 164 * GIC does not handle falling edge or active low. To allow falling edge and 165 * active low interrupts to be handled at GIC, PDC has an inverter that inverts 166 * falling edge into a rising edge and active low into an active high. 167 * For the inverter to work, the polarity bit in the IRQ_CONFIG register has to 168 * set as per the table below. 169 * Level sensitive active low LOW 170 * Rising edge sensitive NOT USED 171 * Falling edge sensitive LOW 172 * Dual Edge sensitive NOT USED 173 * Level sensitive active High HIGH 174 * Falling Edge sensitive NOT USED 175 * Rising edge sensitive HIGH 176 * Dual Edge sensitive HIGH 177 */ 178 enum pdc_irq_config_bits { 179 PDC_LEVEL_LOW = 0b000, 180 PDC_EDGE_FALLING = 0b010, 181 PDC_LEVEL_HIGH = 0b100, 182 PDC_EDGE_RISING = 0b110, 183 PDC_EDGE_DUAL = 0b111, 184 }; 185 186 /** 187 * qcom_pdc_gic_set_type: Configure PDC for the interrupt 188 * 189 * @d: the interrupt data 190 * @type: the interrupt type 191 * 192 * If @type is edge triggered, forward that as Rising edge as PDC 193 * takes care of converting falling edge to rising edge signal 194 * If @type is level, then forward that as level high as PDC 195 * takes care of converting falling edge to rising edge signal 196 */ 197 static int qcom_pdc_gic_set_type(struct irq_data *d, unsigned int type) 198 { 199 enum pdc_irq_config_bits pdc_type; 200 enum pdc_irq_config_bits old_pdc_type; 201 int ret; 202 203 switch (type) { 204 case IRQ_TYPE_EDGE_RISING: 205 pdc_type = PDC_EDGE_RISING; 206 break; 207 case IRQ_TYPE_EDGE_FALLING: 208 pdc_type = PDC_EDGE_FALLING; 209 type = IRQ_TYPE_EDGE_RISING; 210 break; 211 case IRQ_TYPE_EDGE_BOTH: 212 pdc_type = PDC_EDGE_DUAL; 213 type = IRQ_TYPE_EDGE_RISING; 214 break; 215 case IRQ_TYPE_LEVEL_HIGH: 216 pdc_type = PDC_LEVEL_HIGH; 217 break; 218 case IRQ_TYPE_LEVEL_LOW: 219 pdc_type = PDC_LEVEL_LOW; 220 type = IRQ_TYPE_LEVEL_HIGH; 221 break; 222 default: 223 WARN_ON(1); 224 return -EINVAL; 225 } 226 227 old_pdc_type = pdc_reg_read(IRQ_i_CFG, d->hwirq); 228 pdc_type |= (old_pdc_type & ~IRQ_i_CFG_TYPE_MASK); 229 pdc_reg_write(IRQ_i_CFG, d->hwirq, pdc_type); 230 231 ret = irq_chip_set_type_parent(d, type); 232 if (ret) 233 return ret; 234 235 /* 236 * When we change types the PDC can give a phantom interrupt. 237 * Clear it. Specifically the phantom shows up when reconfiguring 238 * polarity of interrupt without changing the state of the signal 239 * but let's be consistent and clear it always. 240 * 241 * Doing this works because we have IRQCHIP_SET_TYPE_MASKED so the 242 * interrupt will be cleared before the rest of the system sees it. 243 */ 244 if (old_pdc_type != pdc_type) 245 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false); 246 247 return 0; 248 } 249 250 static struct irq_chip qcom_pdc_gic_chip = { 251 .name = "PDC", 252 .irq_eoi = irq_chip_eoi_parent, 253 .irq_mask = irq_chip_mask_parent, 254 .irq_unmask = irq_chip_unmask_parent, 255 .irq_disable = qcom_pdc_gic_disable, 256 .irq_enable = qcom_pdc_gic_enable, 257 .irq_get_irqchip_state = irq_chip_get_parent_state, 258 .irq_set_irqchip_state = irq_chip_set_parent_state, 259 .irq_retrigger = irq_chip_retrigger_hierarchy, 260 .irq_set_type = qcom_pdc_gic_set_type, 261 .flags = IRQCHIP_MASK_ON_SUSPEND | 262 IRQCHIP_SET_TYPE_MASKED | 263 IRQCHIP_SKIP_SET_WAKE | 264 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND, 265 .irq_set_vcpu_affinity = irq_chip_set_vcpu_affinity_parent, 266 .irq_set_affinity = irq_chip_set_affinity_parent, 267 }; 268 269 static struct pdc_pin_region *get_pin_region(int pin) 270 { 271 int i; 272 273 for (i = 0; i < pdc_region_cnt; i++) { 274 if (pin >= pdc_region[i].pin_base && 275 pin < pdc_region[i].pin_base + pdc_region[i].cnt) 276 return &pdc_region[i]; 277 } 278 279 return NULL; 280 } 281 282 static int qcom_pdc_alloc(struct irq_domain *domain, unsigned int virq, 283 unsigned int nr_irqs, void *data) 284 { 285 struct irq_fwspec *fwspec = data; 286 struct irq_fwspec parent_fwspec; 287 struct pdc_pin_region *region; 288 irq_hw_number_t hwirq; 289 unsigned int type; 290 int ret; 291 292 ret = irq_domain_translate_twocell(domain, fwspec, &hwirq, &type); 293 if (ret) 294 return ret; 295 296 if (hwirq == GPIO_NO_WAKE_IRQ) 297 return irq_domain_disconnect_hierarchy(domain, virq); 298 299 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, 300 &qcom_pdc_gic_chip, NULL); 301 if (ret) 302 return ret; 303 304 region = get_pin_region(hwirq); 305 if (!region) 306 return irq_domain_disconnect_hierarchy(domain->parent, virq); 307 308 if (type & IRQ_TYPE_EDGE_BOTH) 309 type = IRQ_TYPE_EDGE_RISING; 310 311 if (type & IRQ_TYPE_LEVEL_MASK) 312 type = IRQ_TYPE_LEVEL_HIGH; 313 314 parent_fwspec.fwnode = domain->parent->fwnode; 315 parent_fwspec.param_count = 3; 316 parent_fwspec.param[0] = 0; 317 parent_fwspec.param[1] = pin_to_hwirq(region, hwirq); 318 parent_fwspec.param[2] = type; 319 320 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, 321 &parent_fwspec); 322 } 323 324 static const struct irq_domain_ops qcom_pdc_ops = { 325 .translate = irq_domain_translate_twocell, 326 .alloc = qcom_pdc_alloc, 327 .free = irq_domain_free_irqs_common, 328 }; 329 330 static int pdc_setup_pin_mapping(struct device_node *np) 331 { 332 int ret, n, i; 333 334 n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32)); 335 if (n <= 0 || n % 3) 336 return -EINVAL; 337 338 pdc_region_cnt = n / 3; 339 pdc_region = kzalloc_objs(*pdc_region, pdc_region_cnt); 340 if (!pdc_region) { 341 pdc_region_cnt = 0; 342 return -ENOMEM; 343 } 344 345 for (n = 0; n < pdc_region_cnt; n++) { 346 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 347 n * 3 + 0, 348 &pdc_region[n].pin_base); 349 if (ret) 350 return ret; 351 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 352 n * 3 + 1, 353 &pdc_region[n].parent_base); 354 if (ret) 355 return ret; 356 ret = of_property_read_u32_index(np, "qcom,pdc-ranges", 357 n * 3 + 2, 358 &pdc_region[n].cnt); 359 if (ret) 360 return ret; 361 362 for (i = 0; i < pdc_region[n].cnt; i++) 363 __pdc_enable_intr(i + pdc_region[n].pin_base, 0); 364 } 365 366 return 0; 367 } 368 369 370 static int qcom_pdc_probe(struct platform_device *pdev, struct device_node *parent) 371 { 372 struct irq_domain *parent_domain, *pdc_domain; 373 struct device_node *node = pdev->dev.of_node; 374 resource_size_t res_size; 375 struct resource res; 376 int ret; 377 378 /* compat with old sm8150 DT which had very small region for PDC */ 379 if (of_address_to_resource(node, 0, &res)) 380 return -EINVAL; 381 382 res_size = max_t(resource_size_t, resource_size(&res), PDC_DRV_SIZE); 383 if (res_size > resource_size(&res)) 384 pr_warn("%pOF: invalid reg size, please fix DT\n", node); 385 386 /* 387 * PDC has multiple DRV regions, each one provides the same set of 388 * registers for a particular client in the system. Due to a hardware 389 * bug on X1E, some writes to the IRQ_ENABLE_BANK register must be 390 * issued inside the previous region. This region belongs to 391 * a different client and is not described in the device tree. Map the 392 * region with the expected offset to preserve support for old DTs. 393 */ 394 if (of_device_is_compatible(node, "qcom,x1e80100-pdc")) { 395 pdc_prev_base = ioremap(res.start - PDC_DRV_SIZE, IRQ_ENABLE_BANK_MAX); 396 if (!pdc_prev_base) { 397 pr_err("%pOF: unable to map previous PDC DRV region\n", node); 398 return -ENXIO; 399 } 400 401 pdc_x1e_quirk = true; 402 } 403 404 pdc_base = ioremap(res.start, res_size); 405 if (!pdc_base) { 406 pr_err("%pOF: unable to map PDC registers\n", node); 407 ret = -ENXIO; 408 goto fail; 409 } 410 411 pdc_version = pdc_reg_read(PDC_VERSION_REG, 0); 412 413 parent_domain = irq_find_host(parent); 414 if (!parent_domain) { 415 pr_err("%pOF: unable to find PDC's parent domain\n", node); 416 ret = -ENXIO; 417 goto fail; 418 } 419 420 ret = pdc_setup_pin_mapping(node); 421 if (ret) { 422 pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node); 423 goto fail; 424 } 425 426 pdc_domain = irq_domain_create_hierarchy(parent_domain, 427 IRQ_DOMAIN_FLAG_QCOM_PDC_WAKEUP, 428 PDC_MAX_GPIO_IRQS, 429 of_fwnode_handle(node), 430 &qcom_pdc_ops, NULL); 431 if (!pdc_domain) { 432 pr_err("%pOF: PDC domain add failed\n", node); 433 ret = -ENOMEM; 434 goto fail; 435 } 436 437 irq_domain_update_bus_token(pdc_domain, DOMAIN_BUS_WAKEUP); 438 439 return 0; 440 441 fail: 442 kfree(pdc_region); 443 iounmap(pdc_base); 444 iounmap(pdc_prev_base); 445 return ret; 446 } 447 448 IRQCHIP_PLATFORM_DRIVER_BEGIN(qcom_pdc) 449 IRQCHIP_MATCH("qcom,pdc", qcom_pdc_probe) 450 IRQCHIP_PLATFORM_DRIVER_END(qcom_pdc) 451 MODULE_DESCRIPTION("Qualcomm Technologies, Inc. Power Domain Controller"); 452 MODULE_LICENSE("GPL v2"); 453