1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Qualcomm PCIe Endpoint controller driver
4 *
5 * Copyright (c) 2020, The Linux Foundation. All rights reserved.
6 * Author: Siddartha Mohanadoss <smohanad@codeaurora.org
7 *
8 * Copyright (c) 2021, Linaro Ltd.
9 * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org
10 */
11
12 #include <linux/clk.h>
13 #include <linux/debugfs.h>
14 #include <linux/delay.h>
15 #include <linux/gpio/consumer.h>
16 #include <linux/interconnect.h>
17 #include <linux/mfd/syscon.h>
18 #include <linux/phy/pcie.h>
19 #include <linux/phy/phy.h>
20 #include <linux/platform_device.h>
21 #include <linux/pm_domain.h>
22 #include <linux/regmap.h>
23 #include <linux/reset.h>
24 #include <linux/module.h>
25
26 #include "../../pci.h"
27 #include "pcie-designware.h"
28 #include "pcie-qcom-common.h"
29
30 /* PARF registers */
31 #define PARF_SYS_CTRL 0x00
32 #define PARF_DB_CTRL 0x10
33 #define PARF_PM_CTRL 0x20
34 #define PARF_MHI_CLOCK_RESET_CTRL 0x174
35 #define PARF_MHI_BASE_ADDR_LOWER 0x178
36 #define PARF_MHI_BASE_ADDR_UPPER 0x17c
37 #define PARF_DEBUG_INT_EN 0x190
38 #define PARF_AXI_MSTR_RD_HALT_NO_WRITES 0x1a4
39 #define PARF_AXI_MSTR_WR_ADDR_HALT 0x1a8
40 #define PARF_Q2A_FLUSH 0x1ac
41 #define PARF_LTSSM 0x1b0
42 #define PARF_CFG_BITS 0x210
43 #define PARF_INT_ALL_STATUS 0x224
44 #define PARF_INT_ALL_CLEAR 0x228
45 #define PARF_INT_ALL_MASK 0x22c
46 #define PARF_SLV_ADDR_MSB_CTRL 0x2c0
47 #define PARF_DBI_BASE_ADDR 0x350
48 #define PARF_DBI_BASE_ADDR_HI 0x354
49 #define PARF_SLV_ADDR_SPACE_SIZE 0x358
50 #define PARF_SLV_ADDR_SPACE_SIZE_HI 0x35c
51 #define PARF_NO_SNOOP_OVERRIDE 0x3d4
52 #define PARF_ATU_BASE_ADDR 0x634
53 #define PARF_ATU_BASE_ADDR_HI 0x638
54 #define PARF_SRIS_MODE 0x644
55 #define PARF_DEBUG_CNT_PM_LINKST_IN_L2 0xc04
56 #define PARF_DEBUG_CNT_PM_LINKST_IN_L1 0xc0c
57 #define PARF_DEBUG_CNT_PM_LINKST_IN_L0S 0xc10
58 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1 0xc84
59 #define PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2 0xc88
60 #define PARF_DEVICE_TYPE 0x1000
61 #define PARF_BDF_TO_SID_CFG 0x2c00
62 #define PARF_INT_ALL_5_MASK 0x2dcc
63 #define PARF_INT_ALL_3_MASK 0x2e18
64
65 /* PARF_INT_ALL_{STATUS/CLEAR/MASK} register fields */
66 #define PARF_INT_ALL_LINK_DOWN BIT(1)
67 #define PARF_INT_ALL_BME BIT(2)
68 #define PARF_INT_ALL_PM_TURNOFF BIT(3)
69 #define PARF_INT_ALL_DEBUG BIT(4)
70 #define PARF_INT_ALL_LTR BIT(5)
71 #define PARF_INT_ALL_MHI_Q6 BIT(6)
72 #define PARF_INT_ALL_MHI_A7 BIT(7)
73 #define PARF_INT_ALL_DSTATE_CHANGE BIT(8)
74 #define PARF_INT_ALL_L1SUB_TIMEOUT BIT(9)
75 #define PARF_INT_ALL_MMIO_WRITE BIT(10)
76 #define PARF_INT_ALL_CFG_WRITE BIT(11)
77 #define PARF_INT_ALL_BRIDGE_FLUSH_N BIT(12)
78 #define PARF_INT_ALL_LINK_UP BIT(13)
79 #define PARF_INT_ALL_AER_LEGACY BIT(14)
80 #define PARF_INT_ALL_PLS_ERR BIT(15)
81 #define PARF_INT_ALL_PME_LEGACY BIT(16)
82 #define PARF_INT_ALL_PLS_PME BIT(17)
83 #define PARF_INT_ALL_EDMA BIT(22)
84
85 /* PARF_BDF_TO_SID_CFG register fields */
86 #define PARF_BDF_TO_SID_BYPASS BIT(0)
87
88 /* PARF_DEBUG_INT_EN register fields */
89 #define PARF_DEBUG_INT_PM_DSTATE_CHANGE BIT(1)
90 #define PARF_DEBUG_INT_CFG_BUS_MASTER_EN BIT(2)
91 #define PARF_DEBUG_INT_RADM_PM_TURNOFF BIT(3)
92
93 /* PARF_NO_SNOOP_OVERRIDE register fields */
94 #define WR_NO_SNOOP_OVERRIDE_EN BIT(1)
95 #define RD_NO_SNOOP_OVERRIDE_EN BIT(3)
96
97 /* PARF_DEVICE_TYPE register fields */
98 #define PARF_DEVICE_TYPE_EP 0x0
99
100 /* PARF_PM_CTRL register fields */
101 #define PARF_PM_CTRL_REQ_EXIT_L1 BIT(1)
102 #define PARF_PM_CTRL_READY_ENTR_L23 BIT(2)
103 #define PARF_PM_CTRL_REQ_NOT_ENTR_L1 BIT(5)
104
105 /* PARF_MHI_CLOCK_RESET_CTRL fields */
106 #define PARF_MSTR_AXI_CLK_EN BIT(1)
107
108 /* PARF_AXI_MSTR_RD_HALT_NO_WRITES register fields */
109 #define PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN BIT(0)
110
111 /* PARF_AXI_MSTR_WR_ADDR_HALT register fields */
112 #define PARF_AXI_MSTR_WR_ADDR_HALT_EN BIT(31)
113
114 /* PARF_Q2A_FLUSH register fields */
115 #define PARF_Q2A_FLUSH_EN BIT(16)
116
117 /* PARF_SYS_CTRL register fields */
118 #define PARF_SYS_CTRL_AUX_PWR_DET BIT(4)
119 #define PARF_SYS_CTRL_CORE_CLK_CGC_DIS BIT(6)
120 #define PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS BIT(10)
121 #define PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE BIT(11)
122
123 /* PARF_DB_CTRL register fields */
124 #define PARF_DB_CTRL_INSR_DBNCR_BLOCK BIT(0)
125 #define PARF_DB_CTRL_RMVL_DBNCR_BLOCK BIT(1)
126 #define PARF_DB_CTRL_DBI_WKP_BLOCK BIT(4)
127 #define PARF_DB_CTRL_SLV_WKP_BLOCK BIT(5)
128 #define PARF_DB_CTRL_MST_WKP_BLOCK BIT(6)
129
130 /* PARF_CFG_BITS register fields */
131 #define PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN BIT(1)
132
133 /* PARF_INT_ALL_5_MASK fields */
134 #define PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR BIT(0)
135
136 /* PARF_INT_ALL_3_MASK fields */
137 #define PARF_INT_ALL_3_PTM_UPDATING BIT(4)
138
139 /* ELBI registers */
140 #define ELBI_SYS_STTS 0x08
141 #define ELBI_CS2_ENABLE 0xa4
142
143 /* DBI registers */
144 #define DBI_CON_STATUS 0x44
145
146 /* DBI register fields */
147 #define DBI_CON_STATUS_POWER_STATE_MASK GENMASK(1, 0)
148
149 #define XMLH_LINK_UP 0x400
150 #define CORE_RESET_TIME_US_MIN 1000
151 #define CORE_RESET_TIME_US_MAX 1005
152 #define WAKE_DELAY_US 2000 /* 2 ms */
153
154 #define QCOM_PCIE_LINK_SPEED_TO_BW(speed) \
155 Mbps_to_icc(PCIE_SPEED2MBS_ENC(pcie_link_speed[speed]))
156
157 #define to_pcie_ep(x) dev_get_drvdata((x)->dev)
158
159 enum qcom_pcie_ep_link_status {
160 QCOM_PCIE_EP_LINK_DISABLED,
161 QCOM_PCIE_EP_LINK_ENABLED,
162 QCOM_PCIE_EP_LINK_UP,
163 QCOM_PCIE_EP_LINK_DOWN,
164 };
165
166 /**
167 * struct qcom_pcie_ep_cfg - Per SoC config struct
168 * @hdma_support: HDMA support on this SoC
169 * @override_no_snoop: Override NO_SNOOP attribute in TLP to enable cache snooping
170 * @disable_mhi_ram_parity_check: Disable MHI RAM data parity error check
171 */
172 struct qcom_pcie_ep_cfg {
173 bool hdma_support;
174 bool override_no_snoop;
175 bool disable_mhi_ram_parity_check;
176 };
177
178 /**
179 * struct qcom_pcie_ep - Qualcomm PCIe Endpoint Controller
180 * @pci: Designware PCIe controller struct
181 * @parf: Qualcomm PCIe specific PARF register base
182 * @mmio: MMIO register base
183 * @perst_map: PERST regmap
184 * @mmio_res: MMIO region resource
185 * @core_reset: PCIe Endpoint core reset
186 * @reset: PERST# GPIO
187 * @wake: WAKE# GPIO
188 * @phy: PHY controller block
189 * @debugfs: PCIe Endpoint Debugfs directory
190 * @icc_mem: Handle to an interconnect path between PCIe and MEM
191 * @clks: PCIe clocks
192 * @num_clks: PCIe clocks count
193 * @perst_en: Flag for PERST enable
194 * @perst_sep_en: Flag for PERST separation enable
195 * @cfg: PCIe EP config struct
196 * @link_status: PCIe Link status
197 * @global_irq: Qualcomm PCIe specific Global IRQ
198 * @perst_irq: PERST# IRQ
199 */
200 struct qcom_pcie_ep {
201 struct dw_pcie pci;
202
203 void __iomem *parf;
204 void __iomem *mmio;
205 struct regmap *perst_map;
206 struct resource *mmio_res;
207
208 struct reset_control *core_reset;
209 struct gpio_desc *reset;
210 struct gpio_desc *wake;
211 struct phy *phy;
212 struct dentry *debugfs;
213
214 struct icc_path *icc_mem;
215
216 struct clk_bulk_data *clks;
217 int num_clks;
218
219 u32 perst_en;
220 u32 perst_sep_en;
221
222 const struct qcom_pcie_ep_cfg *cfg;
223 enum qcom_pcie_ep_link_status link_status;
224 int global_irq;
225 int perst_irq;
226 };
227
qcom_pcie_ep_core_reset(struct qcom_pcie_ep * pcie_ep)228 static int qcom_pcie_ep_core_reset(struct qcom_pcie_ep *pcie_ep)
229 {
230 struct dw_pcie *pci = &pcie_ep->pci;
231 struct device *dev = pci->dev;
232 int ret;
233
234 ret = reset_control_assert(pcie_ep->core_reset);
235 if (ret) {
236 dev_err(dev, "Cannot assert core reset\n");
237 return ret;
238 }
239
240 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
241
242 ret = reset_control_deassert(pcie_ep->core_reset);
243 if (ret) {
244 dev_err(dev, "Cannot de-assert core reset\n");
245 return ret;
246 }
247
248 usleep_range(CORE_RESET_TIME_US_MIN, CORE_RESET_TIME_US_MAX);
249
250 return 0;
251 }
252
253 /*
254 * Delatch PERST_EN and PERST_SEPARATION_ENABLE with TCSR to avoid
255 * device reset during host reboot and hibernation. The driver is
256 * expected to handle this situation.
257 */
qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep * pcie_ep)258 static void qcom_pcie_ep_configure_tcsr(struct qcom_pcie_ep *pcie_ep)
259 {
260 if (pcie_ep->perst_map) {
261 regmap_write(pcie_ep->perst_map, pcie_ep->perst_en, 0);
262 regmap_write(pcie_ep->perst_map, pcie_ep->perst_sep_en, 0);
263 }
264 }
265
qcom_pcie_dw_link_up(struct dw_pcie * pci)266 static bool qcom_pcie_dw_link_up(struct dw_pcie *pci)
267 {
268 u32 reg;
269
270 reg = readl_relaxed(pci->elbi_base + ELBI_SYS_STTS);
271
272 return reg & XMLH_LINK_UP;
273 }
274
qcom_pcie_dw_start_link(struct dw_pcie * pci)275 static int qcom_pcie_dw_start_link(struct dw_pcie *pci)
276 {
277 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
278
279 enable_irq(pcie_ep->perst_irq);
280
281 return 0;
282 }
283
qcom_pcie_dw_stop_link(struct dw_pcie * pci)284 static void qcom_pcie_dw_stop_link(struct dw_pcie *pci)
285 {
286 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
287
288 disable_irq(pcie_ep->perst_irq);
289 }
290
qcom_pcie_dw_write_dbi2(struct dw_pcie * pci,void __iomem * base,u32 reg,size_t size,u32 val)291 static void qcom_pcie_dw_write_dbi2(struct dw_pcie *pci, void __iomem *base,
292 u32 reg, size_t size, u32 val)
293 {
294 int ret;
295
296 writel(1, pci->elbi_base + ELBI_CS2_ENABLE);
297
298 ret = dw_pcie_write(pci->dbi_base2 + reg, size, val);
299 if (ret)
300 dev_err(pci->dev, "Failed to write DBI2 register (0x%x): %d\n", reg, ret);
301
302 writel(0, pci->elbi_base + ELBI_CS2_ENABLE);
303 }
304
qcom_pcie_ep_icc_update(struct qcom_pcie_ep * pcie_ep)305 static void qcom_pcie_ep_icc_update(struct qcom_pcie_ep *pcie_ep)
306 {
307 struct dw_pcie *pci = &pcie_ep->pci;
308 u32 offset, status;
309 int speed, width;
310 int ret;
311
312 if (!pcie_ep->icc_mem)
313 return;
314
315 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
316 status = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
317
318 speed = FIELD_GET(PCI_EXP_LNKSTA_CLS, status);
319 width = FIELD_GET(PCI_EXP_LNKSTA_NLW, status);
320
321 ret = icc_set_bw(pcie_ep->icc_mem, 0, width * QCOM_PCIE_LINK_SPEED_TO_BW(speed));
322 if (ret)
323 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
324 ret);
325 }
326
qcom_pcie_enable_resources(struct qcom_pcie_ep * pcie_ep)327 static int qcom_pcie_enable_resources(struct qcom_pcie_ep *pcie_ep)
328 {
329 struct dw_pcie *pci = &pcie_ep->pci;
330 int ret;
331
332 ret = clk_bulk_prepare_enable(pcie_ep->num_clks, pcie_ep->clks);
333 if (ret)
334 return ret;
335
336 ret = qcom_pcie_ep_core_reset(pcie_ep);
337 if (ret)
338 goto err_disable_clk;
339
340 ret = phy_init(pcie_ep->phy);
341 if (ret)
342 goto err_disable_clk;
343
344 ret = phy_set_mode_ext(pcie_ep->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_EP);
345 if (ret)
346 goto err_phy_exit;
347
348 ret = phy_power_on(pcie_ep->phy);
349 if (ret)
350 goto err_phy_exit;
351
352 /*
353 * Some Qualcomm platforms require interconnect bandwidth constraints
354 * to be set before enabling interconnect clocks.
355 *
356 * Set an initial peak bandwidth corresponding to single-lane Gen 1
357 * for the pcie-mem path.
358 */
359 ret = icc_set_bw(pcie_ep->icc_mem, 0, QCOM_PCIE_LINK_SPEED_TO_BW(1));
360 if (ret) {
361 dev_err(pci->dev, "failed to set interconnect bandwidth: %d\n",
362 ret);
363 goto err_phy_off;
364 }
365
366 return 0;
367
368 err_phy_off:
369 phy_power_off(pcie_ep->phy);
370 err_phy_exit:
371 phy_exit(pcie_ep->phy);
372 err_disable_clk:
373 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
374
375 return ret;
376 }
377
qcom_pcie_disable_resources(struct qcom_pcie_ep * pcie_ep)378 static void qcom_pcie_disable_resources(struct qcom_pcie_ep *pcie_ep)
379 {
380 icc_set_bw(pcie_ep->icc_mem, 0, 0);
381 phy_power_off(pcie_ep->phy);
382 phy_exit(pcie_ep->phy);
383 clk_bulk_disable_unprepare(pcie_ep->num_clks, pcie_ep->clks);
384 }
385
qcom_pcie_perst_deassert(struct dw_pcie * pci)386 static int qcom_pcie_perst_deassert(struct dw_pcie *pci)
387 {
388 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
389 struct device *dev = pci->dev;
390 u32 val, offset;
391 int ret;
392
393 ret = qcom_pcie_enable_resources(pcie_ep);
394 if (ret) {
395 dev_err(dev, "Failed to enable resources: %d\n", ret);
396 return ret;
397 }
398
399 /* Perform cleanup that requires refclk */
400 pci_epc_deinit_notify(pci->ep.epc);
401 dw_pcie_ep_cleanup(&pci->ep);
402
403 /* Assert WAKE# to RC to indicate device is ready */
404 gpiod_set_value_cansleep(pcie_ep->wake, 1);
405 usleep_range(WAKE_DELAY_US, WAKE_DELAY_US + 500);
406 gpiod_set_value_cansleep(pcie_ep->wake, 0);
407
408 qcom_pcie_ep_configure_tcsr(pcie_ep);
409
410 /* Disable BDF to SID mapping */
411 val = readl_relaxed(pcie_ep->parf + PARF_BDF_TO_SID_CFG);
412 val |= PARF_BDF_TO_SID_BYPASS;
413 writel_relaxed(val, pcie_ep->parf + PARF_BDF_TO_SID_CFG);
414
415 /* Enable debug IRQ */
416 val = readl_relaxed(pcie_ep->parf + PARF_DEBUG_INT_EN);
417 val |= PARF_DEBUG_INT_RADM_PM_TURNOFF |
418 PARF_DEBUG_INT_CFG_BUS_MASTER_EN |
419 PARF_DEBUG_INT_PM_DSTATE_CHANGE;
420 writel_relaxed(val, pcie_ep->parf + PARF_DEBUG_INT_EN);
421
422 /* Configure PCIe to endpoint mode */
423 writel_relaxed(PARF_DEVICE_TYPE_EP, pcie_ep->parf + PARF_DEVICE_TYPE);
424
425 /* Allow entering L1 state */
426 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
427 val &= ~PARF_PM_CTRL_REQ_NOT_ENTR_L1;
428 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
429
430 /* Read halts write */
431 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
432 val &= ~PARF_AXI_MSTR_RD_HALT_NO_WRITE_EN;
433 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_RD_HALT_NO_WRITES);
434
435 /* Write after write halt */
436 val = readl_relaxed(pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
437 val |= PARF_AXI_MSTR_WR_ADDR_HALT_EN;
438 writel_relaxed(val, pcie_ep->parf + PARF_AXI_MSTR_WR_ADDR_HALT);
439
440 /* Q2A flush disable */
441 val = readl_relaxed(pcie_ep->parf + PARF_Q2A_FLUSH);
442 val &= ~PARF_Q2A_FLUSH_EN;
443 writel_relaxed(val, pcie_ep->parf + PARF_Q2A_FLUSH);
444
445 /*
446 * Disable Master AXI clock during idle. Do not allow DBI access
447 * to take the core out of L1. Disable core clock gating that
448 * gates PIPE clock from propagating to core clock. Report to the
449 * host that Vaux is present.
450 */
451 val = readl_relaxed(pcie_ep->parf + PARF_SYS_CTRL);
452 val &= ~PARF_SYS_CTRL_MSTR_ACLK_CGC_DIS;
453 val |= PARF_SYS_CTRL_SLV_DBI_WAKE_DISABLE |
454 PARF_SYS_CTRL_CORE_CLK_CGC_DIS |
455 PARF_SYS_CTRL_AUX_PWR_DET;
456 writel_relaxed(val, pcie_ep->parf + PARF_SYS_CTRL);
457
458 /* Disable the debouncers */
459 val = readl_relaxed(pcie_ep->parf + PARF_DB_CTRL);
460 val |= PARF_DB_CTRL_INSR_DBNCR_BLOCK | PARF_DB_CTRL_RMVL_DBNCR_BLOCK |
461 PARF_DB_CTRL_DBI_WKP_BLOCK | PARF_DB_CTRL_SLV_WKP_BLOCK |
462 PARF_DB_CTRL_MST_WKP_BLOCK;
463 writel_relaxed(val, pcie_ep->parf + PARF_DB_CTRL);
464
465 /* Request to exit from L1SS for MSI and LTR MSG */
466 val = readl_relaxed(pcie_ep->parf + PARF_CFG_BITS);
467 val |= PARF_CFG_BITS_REQ_EXIT_L1SS_MSI_LTR_EN;
468 writel_relaxed(val, pcie_ep->parf + PARF_CFG_BITS);
469
470 dw_pcie_dbi_ro_wr_en(pci);
471
472 /* Set the L0s Exit Latency to 2us-4us = 0x6 */
473 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
474 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
475 val &= ~PCI_EXP_LNKCAP_L0SEL;
476 val |= FIELD_PREP(PCI_EXP_LNKCAP_L0SEL, 0x6);
477 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
478
479 /* Set the L1 Exit Latency to be 32us-64 us = 0x6 */
480 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
481 val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
482 val &= ~PCI_EXP_LNKCAP_L1EL;
483 val |= FIELD_PREP(PCI_EXP_LNKCAP_L1EL, 0x6);
484 dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val);
485
486 dw_pcie_dbi_ro_wr_dis(pci);
487
488 writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK);
489 val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME |
490 PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE |
491 PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA;
492 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK);
493
494 if (pcie_ep->cfg && pcie_ep->cfg->disable_mhi_ram_parity_check) {
495 val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_5_MASK);
496 val &= ~PARF_INT_ALL_5_MHI_RAM_DATA_PARITY_ERR;
497 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_5_MASK);
498 }
499
500 val = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_3_MASK);
501 val &= ~PARF_INT_ALL_3_PTM_UPDATING;
502 writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_3_MASK);
503
504 ret = dw_pcie_ep_init_registers(&pcie_ep->pci.ep);
505 if (ret) {
506 dev_err(dev, "Failed to complete initialization: %d\n", ret);
507 goto err_disable_resources;
508 }
509
510 qcom_pcie_common_set_equalization(pci);
511
512 if (pcie_link_speed[pci->max_link_speed] == PCIE_SPEED_16_0GT)
513 qcom_pcie_common_set_16gt_lane_margining(pci);
514
515 /*
516 * The physical address of the MMIO region which is exposed as the BAR
517 * should be written to MHI BASE registers.
518 */
519 writel_relaxed(pcie_ep->mmio_res->start,
520 pcie_ep->parf + PARF_MHI_BASE_ADDR_LOWER);
521 writel_relaxed(0, pcie_ep->parf + PARF_MHI_BASE_ADDR_UPPER);
522
523 /* Gate Master AXI clock to MHI bus during L1SS */
524 val = readl_relaxed(pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
525 val &= ~PARF_MSTR_AXI_CLK_EN;
526 writel_relaxed(val, pcie_ep->parf + PARF_MHI_CLOCK_RESET_CTRL);
527
528 pci_epc_init_notify(pcie_ep->pci.ep.epc);
529
530 /* Enable LTSSM */
531 val = readl_relaxed(pcie_ep->parf + PARF_LTSSM);
532 val |= BIT(8);
533 writel_relaxed(val, pcie_ep->parf + PARF_LTSSM);
534
535 if (pcie_ep->cfg && pcie_ep->cfg->override_no_snoop)
536 writel_relaxed(WR_NO_SNOOP_OVERRIDE_EN | RD_NO_SNOOP_OVERRIDE_EN,
537 pcie_ep->parf + PARF_NO_SNOOP_OVERRIDE);
538
539 return 0;
540
541 err_disable_resources:
542 qcom_pcie_disable_resources(pcie_ep);
543
544 return ret;
545 }
546
qcom_pcie_perst_assert(struct dw_pcie * pci)547 static void qcom_pcie_perst_assert(struct dw_pcie *pci)
548 {
549 struct qcom_pcie_ep *pcie_ep = to_pcie_ep(pci);
550
551 qcom_pcie_disable_resources(pcie_ep);
552 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DISABLED;
553 }
554
555 /* Common DWC controller ops */
556 static const struct dw_pcie_ops pci_ops = {
557 .link_up = qcom_pcie_dw_link_up,
558 .start_link = qcom_pcie_dw_start_link,
559 .stop_link = qcom_pcie_dw_stop_link,
560 .write_dbi2 = qcom_pcie_dw_write_dbi2,
561 };
562
qcom_pcie_ep_get_io_resources(struct platform_device * pdev,struct qcom_pcie_ep * pcie_ep)563 static int qcom_pcie_ep_get_io_resources(struct platform_device *pdev,
564 struct qcom_pcie_ep *pcie_ep)
565 {
566 struct device *dev = &pdev->dev;
567 struct dw_pcie *pci = &pcie_ep->pci;
568 struct device_node *syscon;
569 struct resource *res;
570 int ret;
571
572 pcie_ep->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
573 if (IS_ERR(pcie_ep->parf))
574 return PTR_ERR(pcie_ep->parf);
575
576 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
577 pci->dbi_base = devm_pci_remap_cfg_resource(dev, res);
578 if (IS_ERR(pci->dbi_base))
579 return PTR_ERR(pci->dbi_base);
580 pci->dbi_base2 = pci->dbi_base;
581
582 pcie_ep->mmio_res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
583 "mmio");
584 if (!pcie_ep->mmio_res) {
585 dev_err(dev, "Failed to get mmio resource\n");
586 return -EINVAL;
587 }
588
589 pcie_ep->mmio = devm_pci_remap_cfg_resource(dev, pcie_ep->mmio_res);
590 if (IS_ERR(pcie_ep->mmio))
591 return PTR_ERR(pcie_ep->mmio);
592
593 syscon = of_parse_phandle(dev->of_node, "qcom,perst-regs", 0);
594 if (!syscon) {
595 dev_dbg(dev, "PERST separation not available\n");
596 return 0;
597 }
598
599 pcie_ep->perst_map = syscon_node_to_regmap(syscon);
600 of_node_put(syscon);
601 if (IS_ERR(pcie_ep->perst_map))
602 return PTR_ERR(pcie_ep->perst_map);
603
604 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
605 1, &pcie_ep->perst_en);
606 if (ret < 0) {
607 dev_err(dev, "No Perst Enable offset in syscon\n");
608 return ret;
609 }
610
611 ret = of_property_read_u32_index(dev->of_node, "qcom,perst-regs",
612 2, &pcie_ep->perst_sep_en);
613 if (ret < 0) {
614 dev_err(dev, "No Perst Separation Enable offset in syscon\n");
615 return ret;
616 }
617
618 return 0;
619 }
620
qcom_pcie_ep_get_resources(struct platform_device * pdev,struct qcom_pcie_ep * pcie_ep)621 static int qcom_pcie_ep_get_resources(struct platform_device *pdev,
622 struct qcom_pcie_ep *pcie_ep)
623 {
624 struct device *dev = &pdev->dev;
625 int ret;
626
627 ret = qcom_pcie_ep_get_io_resources(pdev, pcie_ep);
628 if (ret) {
629 dev_err(dev, "Failed to get io resources %d\n", ret);
630 return ret;
631 }
632
633 pcie_ep->num_clks = devm_clk_bulk_get_all(dev, &pcie_ep->clks);
634 if (pcie_ep->num_clks < 0) {
635 dev_err(dev, "Failed to get clocks\n");
636 return pcie_ep->num_clks;
637 }
638
639 pcie_ep->core_reset = devm_reset_control_get_exclusive(dev, "core");
640 if (IS_ERR(pcie_ep->core_reset))
641 return PTR_ERR(pcie_ep->core_reset);
642
643 pcie_ep->reset = devm_gpiod_get(dev, "reset", GPIOD_IN);
644 if (IS_ERR(pcie_ep->reset))
645 return PTR_ERR(pcie_ep->reset);
646
647 pcie_ep->wake = devm_gpiod_get_optional(dev, "wake", GPIOD_OUT_LOW);
648 if (IS_ERR(pcie_ep->wake))
649 return PTR_ERR(pcie_ep->wake);
650
651 pcie_ep->phy = devm_phy_optional_get(dev, "pciephy");
652 if (IS_ERR(pcie_ep->phy))
653 ret = PTR_ERR(pcie_ep->phy);
654
655 pcie_ep->icc_mem = devm_of_icc_get(dev, "pcie-mem");
656 if (IS_ERR(pcie_ep->icc_mem))
657 ret = PTR_ERR(pcie_ep->icc_mem);
658
659 return ret;
660 }
661
662 /* TODO: Notify clients about PCIe state change */
qcom_pcie_ep_global_irq_thread(int irq,void * data)663 static irqreturn_t qcom_pcie_ep_global_irq_thread(int irq, void *data)
664 {
665 struct qcom_pcie_ep *pcie_ep = data;
666 struct dw_pcie *pci = &pcie_ep->pci;
667 struct device *dev = pci->dev;
668 u32 status = readl_relaxed(pcie_ep->parf + PARF_INT_ALL_STATUS);
669 u32 dstate, val;
670
671 writel_relaxed(status, pcie_ep->parf + PARF_INT_ALL_CLEAR);
672
673 if (FIELD_GET(PARF_INT_ALL_LINK_DOWN, status)) {
674 dev_dbg(dev, "Received Linkdown event\n");
675 pcie_ep->link_status = QCOM_PCIE_EP_LINK_DOWN;
676 dw_pcie_ep_linkdown(&pci->ep);
677 } else if (FIELD_GET(PARF_INT_ALL_BME, status)) {
678 dev_dbg(dev, "Received Bus Master Enable event\n");
679 pcie_ep->link_status = QCOM_PCIE_EP_LINK_ENABLED;
680 qcom_pcie_ep_icc_update(pcie_ep);
681 pci_epc_bus_master_enable_notify(pci->ep.epc);
682 } else if (FIELD_GET(PARF_INT_ALL_PM_TURNOFF, status)) {
683 dev_dbg(dev, "Received PM Turn-off event! Entering L23\n");
684 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
685 val |= PARF_PM_CTRL_READY_ENTR_L23;
686 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
687 } else if (FIELD_GET(PARF_INT_ALL_DSTATE_CHANGE, status)) {
688 dstate = dw_pcie_readl_dbi(pci, DBI_CON_STATUS) &
689 DBI_CON_STATUS_POWER_STATE_MASK;
690 dev_dbg(dev, "Received D%d state event\n", dstate);
691 if (dstate == 3) {
692 val = readl_relaxed(pcie_ep->parf + PARF_PM_CTRL);
693 val |= PARF_PM_CTRL_REQ_EXIT_L1;
694 writel_relaxed(val, pcie_ep->parf + PARF_PM_CTRL);
695 }
696 } else if (FIELD_GET(PARF_INT_ALL_LINK_UP, status)) {
697 dev_dbg(dev, "Received Linkup event. Enumeration complete!\n");
698 dw_pcie_ep_linkup(&pci->ep);
699 pcie_ep->link_status = QCOM_PCIE_EP_LINK_UP;
700 } else {
701 dev_WARN_ONCE(dev, 1, "Received unknown event. INT_STATUS: 0x%08x\n",
702 status);
703 }
704
705 return IRQ_HANDLED;
706 }
707
qcom_pcie_ep_perst_irq_thread(int irq,void * data)708 static irqreturn_t qcom_pcie_ep_perst_irq_thread(int irq, void *data)
709 {
710 struct qcom_pcie_ep *pcie_ep = data;
711 struct dw_pcie *pci = &pcie_ep->pci;
712 struct device *dev = pci->dev;
713 u32 perst;
714
715 perst = gpiod_get_value(pcie_ep->reset);
716 if (perst) {
717 dev_dbg(dev, "PERST asserted by host. Shutting down the PCIe link!\n");
718 qcom_pcie_perst_assert(pci);
719 } else {
720 dev_dbg(dev, "PERST de-asserted by host. Starting link training!\n");
721 qcom_pcie_perst_deassert(pci);
722 }
723
724 irq_set_irq_type(gpiod_to_irq(pcie_ep->reset),
725 (perst ? IRQF_TRIGGER_HIGH : IRQF_TRIGGER_LOW));
726
727 return IRQ_HANDLED;
728 }
729
qcom_pcie_ep_enable_irq_resources(struct platform_device * pdev,struct qcom_pcie_ep * pcie_ep)730 static int qcom_pcie_ep_enable_irq_resources(struct platform_device *pdev,
731 struct qcom_pcie_ep *pcie_ep)
732 {
733 struct device *dev = pcie_ep->pci.dev;
734 char *name;
735 int ret;
736
737 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_global_irq%d",
738 pcie_ep->pci.ep.epc->domain_nr);
739 if (!name)
740 return -ENOMEM;
741
742 pcie_ep->global_irq = platform_get_irq_byname(pdev, "global");
743 if (pcie_ep->global_irq < 0)
744 return pcie_ep->global_irq;
745
746 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->global_irq, NULL,
747 qcom_pcie_ep_global_irq_thread,
748 IRQF_ONESHOT,
749 name, pcie_ep);
750 if (ret) {
751 dev_err(&pdev->dev, "Failed to request Global IRQ\n");
752 return ret;
753 }
754
755 name = devm_kasprintf(dev, GFP_KERNEL, "qcom_pcie_ep_perst_irq%d",
756 pcie_ep->pci.ep.epc->domain_nr);
757 if (!name)
758 return -ENOMEM;
759
760 pcie_ep->perst_irq = gpiod_to_irq(pcie_ep->reset);
761 irq_set_status_flags(pcie_ep->perst_irq, IRQ_NOAUTOEN);
762 ret = devm_request_threaded_irq(&pdev->dev, pcie_ep->perst_irq, NULL,
763 qcom_pcie_ep_perst_irq_thread,
764 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
765 name, pcie_ep);
766 if (ret) {
767 dev_err(&pdev->dev, "Failed to request PERST IRQ\n");
768 disable_irq(pcie_ep->global_irq);
769 return ret;
770 }
771
772 return 0;
773 }
774
qcom_pcie_ep_raise_irq(struct dw_pcie_ep * ep,u8 func_no,unsigned int type,u16 interrupt_num)775 static int qcom_pcie_ep_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
776 unsigned int type, u16 interrupt_num)
777 {
778 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
779
780 switch (type) {
781 case PCI_IRQ_INTX:
782 return dw_pcie_ep_raise_intx_irq(ep, func_no);
783 case PCI_IRQ_MSI:
784 return dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
785 default:
786 dev_err(pci->dev, "Unknown IRQ type\n");
787 return -EINVAL;
788 }
789 }
790
qcom_pcie_ep_link_transition_count(struct seq_file * s,void * data)791 static int qcom_pcie_ep_link_transition_count(struct seq_file *s, void *data)
792 {
793 struct qcom_pcie_ep *pcie_ep = (struct qcom_pcie_ep *)
794 dev_get_drvdata(s->private);
795
796 seq_printf(s, "L0s transition count: %u\n",
797 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L0S));
798
799 seq_printf(s, "L1 transition count: %u\n",
800 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L1));
801
802 seq_printf(s, "L1.1 transition count: %u\n",
803 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L1));
804
805 seq_printf(s, "L1.2 transition count: %u\n",
806 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_AUX_CLK_IN_L1SUB_L2));
807
808 seq_printf(s, "L2 transition count: %u\n",
809 readl_relaxed(pcie_ep->mmio + PARF_DEBUG_CNT_PM_LINKST_IN_L2));
810
811 return 0;
812 }
813
qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep * pcie_ep)814 static void qcom_pcie_ep_init_debugfs(struct qcom_pcie_ep *pcie_ep)
815 {
816 struct dw_pcie *pci = &pcie_ep->pci;
817
818 debugfs_create_devm_seqfile(pci->dev, "link_transition_count", pcie_ep->debugfs,
819 qcom_pcie_ep_link_transition_count);
820 }
821
822 static const struct pci_epc_features qcom_pcie_epc_features = {
823 .linkup_notifier = true,
824 .msi_capable = true,
825 .align = SZ_4K,
826 .bar[BAR_0] = { .only_64bit = true, },
827 .bar[BAR_1] = { .type = BAR_RESERVED, },
828 .bar[BAR_2] = { .only_64bit = true, },
829 .bar[BAR_3] = { .type = BAR_RESERVED, },
830 };
831
832 static const struct pci_epc_features *
qcom_pcie_epc_get_features(struct dw_pcie_ep * pci_ep)833 qcom_pcie_epc_get_features(struct dw_pcie_ep *pci_ep)
834 {
835 return &qcom_pcie_epc_features;
836 }
837
qcom_pcie_ep_init(struct dw_pcie_ep * ep)838 static void qcom_pcie_ep_init(struct dw_pcie_ep *ep)
839 {
840 struct dw_pcie *pci = to_dw_pcie_from_ep(ep);
841 enum pci_barno bar;
842
843 for (bar = BAR_0; bar <= BAR_5; bar++)
844 dw_pcie_ep_reset_bar(pci, bar);
845 }
846
847 static const struct dw_pcie_ep_ops pci_ep_ops = {
848 .init = qcom_pcie_ep_init,
849 .raise_irq = qcom_pcie_ep_raise_irq,
850 .get_features = qcom_pcie_epc_get_features,
851 };
852
qcom_pcie_ep_probe(struct platform_device * pdev)853 static int qcom_pcie_ep_probe(struct platform_device *pdev)
854 {
855 struct device *dev = &pdev->dev;
856 struct qcom_pcie_ep *pcie_ep;
857 char *name;
858 int ret;
859
860 pcie_ep = devm_kzalloc(dev, sizeof(*pcie_ep), GFP_KERNEL);
861 if (!pcie_ep)
862 return -ENOMEM;
863
864 pcie_ep->pci.dev = dev;
865 pcie_ep->pci.ops = &pci_ops;
866 pcie_ep->pci.ep.ops = &pci_ep_ops;
867
868 pcie_ep->cfg = of_device_get_match_data(dev);
869 if (pcie_ep->cfg && pcie_ep->cfg->hdma_support) {
870 pcie_ep->pci.edma.ll_wr_cnt = 8;
871 pcie_ep->pci.edma.ll_rd_cnt = 8;
872 pcie_ep->pci.edma.mf = EDMA_MF_HDMA_NATIVE;
873 }
874
875 platform_set_drvdata(pdev, pcie_ep);
876
877 ret = qcom_pcie_ep_get_resources(pdev, pcie_ep);
878 if (ret)
879 return ret;
880
881 ret = dw_pcie_ep_init(&pcie_ep->pci.ep);
882 if (ret) {
883 dev_err(dev, "Failed to initialize endpoint: %d\n", ret);
884 return ret;
885 }
886
887 ret = qcom_pcie_ep_enable_irq_resources(pdev, pcie_ep);
888 if (ret)
889 goto err_ep_deinit;
890
891 name = devm_kasprintf(dev, GFP_KERNEL, "%pOFP", dev->of_node);
892 if (!name) {
893 ret = -ENOMEM;
894 goto err_disable_irqs;
895 }
896
897 pcie_ep->debugfs = debugfs_create_dir(name, NULL);
898 qcom_pcie_ep_init_debugfs(pcie_ep);
899
900 return 0;
901
902 err_disable_irqs:
903 disable_irq(pcie_ep->global_irq);
904 disable_irq(pcie_ep->perst_irq);
905
906 err_ep_deinit:
907 dw_pcie_ep_deinit(&pcie_ep->pci.ep);
908
909 return ret;
910 }
911
qcom_pcie_ep_remove(struct platform_device * pdev)912 static void qcom_pcie_ep_remove(struct platform_device *pdev)
913 {
914 struct qcom_pcie_ep *pcie_ep = platform_get_drvdata(pdev);
915
916 disable_irq(pcie_ep->global_irq);
917 disable_irq(pcie_ep->perst_irq);
918
919 debugfs_remove_recursive(pcie_ep->debugfs);
920
921 if (pcie_ep->link_status == QCOM_PCIE_EP_LINK_DISABLED)
922 return;
923
924 qcom_pcie_disable_resources(pcie_ep);
925 }
926
927 static const struct qcom_pcie_ep_cfg cfg_1_34_0 = {
928 .hdma_support = true,
929 .override_no_snoop = true,
930 .disable_mhi_ram_parity_check = true,
931 };
932
933 static const struct of_device_id qcom_pcie_ep_match[] = {
934 { .compatible = "qcom,sa8775p-pcie-ep", .data = &cfg_1_34_0},
935 { .compatible = "qcom,sdx55-pcie-ep", },
936 { .compatible = "qcom,sm8450-pcie-ep", },
937 { .compatible = "qcom,sar2130p-pcie-ep", },
938 { }
939 };
940 MODULE_DEVICE_TABLE(of, qcom_pcie_ep_match);
941
942 static struct platform_driver qcom_pcie_ep_driver = {
943 .probe = qcom_pcie_ep_probe,
944 .remove = qcom_pcie_ep_remove,
945 .driver = {
946 .name = "qcom-pcie-ep",
947 .of_match_table = qcom_pcie_ep_match,
948 },
949 };
950 builtin_platform_driver(qcom_pcie_ep_driver);
951
952 MODULE_AUTHOR("Siddartha Mohanadoss <smohanad@codeaurora.org>");
953 MODULE_AUTHOR("Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>");
954 MODULE_DESCRIPTION("Qualcomm PCIe Endpoint controller driver");
955 MODULE_LICENSE("GPL v2");
956