1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved.
4 */
5
6 #include <linux/pci.h>
7
8 #include "pcie-designware.h"
9 #include "pcie-qcom-common.h"
10
qcom_pcie_common_set_equalization(struct dw_pcie * pci)11 void qcom_pcie_common_set_equalization(struct dw_pcie *pci)
12 {
13 struct device *dev = pci->dev;
14 u32 reg;
15 u16 speed;
16
17 /*
18 * GEN3_RELATED_OFF register is repurposed to apply equalization
19 * settings at various data transmission rates through registers namely
20 * GEN3_EQ_*. The RATE_SHADOW_SEL bit field of GEN3_RELATED_OFF
21 * determines the data rate for which these equalization settings are
22 * applied.
23 */
24
25 for (speed = PCIE_SPEED_8_0GT; speed <= pcie_link_speed[pci->max_link_speed]; speed++) {
26 if (speed > PCIE_SPEED_32_0GT) {
27 dev_warn(dev, "Skipped equalization settings for unsupported data rate\n");
28 break;
29 }
30
31 reg = dw_pcie_readl_dbi(pci, GEN3_RELATED_OFF);
32 reg &= ~GEN3_RELATED_OFF_GEN3_ZRXDC_NONCOMPL;
33 reg &= ~GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK;
34 reg |= FIELD_PREP(GEN3_RELATED_OFF_RATE_SHADOW_SEL_MASK,
35 speed - PCIE_SPEED_8_0GT);
36 dw_pcie_writel_dbi(pci, GEN3_RELATED_OFF, reg);
37
38 reg = dw_pcie_readl_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF);
39 reg &= ~(GEN3_EQ_FMDC_T_MIN_PHASE23 |
40 GEN3_EQ_FMDC_N_EVALS |
41 GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA |
42 GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA);
43 reg |= FIELD_PREP(GEN3_EQ_FMDC_T_MIN_PHASE23, 0x1) |
44 FIELD_PREP(GEN3_EQ_FMDC_N_EVALS, 0xd) |
45 FIELD_PREP(GEN3_EQ_FMDC_MAX_PRE_CURSOR_DELTA, 0x5) |
46 FIELD_PREP(GEN3_EQ_FMDC_MAX_POST_CURSOR_DELTA, 0x5);
47 dw_pcie_writel_dbi(pci, GEN3_EQ_FB_MODE_DIR_CHANGE_OFF, reg);
48
49 reg = dw_pcie_readl_dbi(pci, GEN3_EQ_CONTROL_OFF);
50 reg &= ~(GEN3_EQ_CONTROL_OFF_FB_MODE |
51 GEN3_EQ_CONTROL_OFF_PHASE23_EXIT_MODE |
52 GEN3_EQ_CONTROL_OFF_FOM_INC_INITIAL_EVAL |
53 GEN3_EQ_CONTROL_OFF_PSET_REQ_VEC);
54 dw_pcie_writel_dbi(pci, GEN3_EQ_CONTROL_OFF, reg);
55 }
56 }
57 EXPORT_SYMBOL_GPL(qcom_pcie_common_set_equalization);
58
qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie * pci)59 void qcom_pcie_common_set_16gt_lane_margining(struct dw_pcie *pci)
60 {
61 u32 reg;
62
63 reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_1_OFF);
64 reg &= ~(MARGINING_MAX_VOLTAGE_OFFSET |
65 MARGINING_NUM_VOLTAGE_STEPS |
66 MARGINING_MAX_TIMING_OFFSET |
67 MARGINING_NUM_TIMING_STEPS);
68 reg |= FIELD_PREP(MARGINING_MAX_VOLTAGE_OFFSET, 0x24) |
69 FIELD_PREP(MARGINING_NUM_VOLTAGE_STEPS, 0x78) |
70 FIELD_PREP(MARGINING_MAX_TIMING_OFFSET, 0x32) |
71 FIELD_PREP(MARGINING_NUM_TIMING_STEPS, 0x10);
72 dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_1_OFF, reg);
73
74 reg = dw_pcie_readl_dbi(pci, GEN4_LANE_MARGINING_2_OFF);
75 reg |= MARGINING_IND_ERROR_SAMPLER |
76 MARGINING_SAMPLE_REPORTING_METHOD |
77 MARGINING_IND_LEFT_RIGHT_TIMING |
78 MARGINING_VOLTAGE_SUPPORTED;
79 reg &= ~(MARGINING_IND_UP_DOWN_VOLTAGE |
80 MARGINING_MAXLANES |
81 MARGINING_SAMPLE_RATE_TIMING |
82 MARGINING_SAMPLE_RATE_VOLTAGE);
83 reg |= FIELD_PREP(MARGINING_MAXLANES, pci->num_lanes) |
84 FIELD_PREP(MARGINING_SAMPLE_RATE_TIMING, 0x3f) |
85 FIELD_PREP(MARGINING_SAMPLE_RATE_VOLTAGE, 0x3f);
86 dw_pcie_writel_dbi(pci, GEN4_LANE_MARGINING_2_OFF, reg);
87 }
88 EXPORT_SYMBOL_GPL(qcom_pcie_common_set_16gt_lane_margining);
89