1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * IOMMU API for QCOM secure IOMMUs. Somewhat based on arm-smmu.c
4 *
5 * Copyright (C) 2013 ARM Limited
6 * Copyright (C) 2017 Red Hat
7 */
8
9 #include <linux/atomic.h>
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/delay.h>
13 #include <linux/dma-mapping.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/io-64-nonatomic-hi-lo.h>
18 #include <linux/io-pgtable.h>
19 #include <linux/iommu.h>
20 #include <linux/iopoll.h>
21 #include <linux/kconfig.h>
22 #include <linux/init.h>
23 #include <linux/mutex.h>
24 #include <linux/of.h>
25 #include <linux/of_platform.h>
26 #include <linux/platform_device.h>
27 #include <linux/pm.h>
28 #include <linux/pm_runtime.h>
29 #include <linux/firmware/qcom/qcom_scm.h>
30 #include <linux/slab.h>
31 #include <linux/spinlock.h>
32
33 #include "arm-smmu.h"
34
35 #define SMMU_INTR_SEL_NS 0x2000
36
37 enum qcom_iommu_clk {
38 CLK_IFACE,
39 CLK_BUS,
40 CLK_TBU,
41 CLK_NUM,
42 };
43
44 struct qcom_iommu_ctx;
45
46 struct qcom_iommu_dev {
47 /* IOMMU core code handle */
48 struct iommu_device iommu;
49 struct device *dev;
50 struct clk_bulk_data clks[CLK_NUM];
51 void __iomem *local_base;
52 u32 sec_id;
53 u8 max_asid;
54 struct qcom_iommu_ctx *ctxs[]; /* indexed by asid */
55 };
56
57 struct qcom_iommu_ctx {
58 struct device *dev;
59 void __iomem *base;
60 bool secure_init;
61 bool secured_ctx;
62 u8 asid; /* asid and ctx bank # are 1:1 */
63 struct iommu_domain *domain;
64 };
65
66 struct qcom_iommu_domain {
67 struct io_pgtable_ops *pgtbl_ops;
68 spinlock_t pgtbl_lock;
69 struct mutex init_mutex; /* Protects iommu pointer */
70 struct iommu_domain domain;
71 struct qcom_iommu_dev *iommu;
72 struct iommu_fwspec *fwspec;
73 };
74
to_qcom_iommu_domain(struct iommu_domain * dom)75 static struct qcom_iommu_domain *to_qcom_iommu_domain(struct iommu_domain *dom)
76 {
77 return container_of(dom, struct qcom_iommu_domain, domain);
78 }
79
80 static const struct iommu_ops qcom_iommu_ops;
81
to_ctx(struct qcom_iommu_domain * d,unsigned asid)82 static struct qcom_iommu_ctx * to_ctx(struct qcom_iommu_domain *d, unsigned asid)
83 {
84 struct qcom_iommu_dev *qcom_iommu = d->iommu;
85 if (!qcom_iommu)
86 return NULL;
87 return qcom_iommu->ctxs[asid];
88 }
89
90 static inline void
iommu_writel(struct qcom_iommu_ctx * ctx,unsigned reg,u32 val)91 iommu_writel(struct qcom_iommu_ctx *ctx, unsigned reg, u32 val)
92 {
93 writel_relaxed(val, ctx->base + reg);
94 }
95
96 static inline void
iommu_writeq(struct qcom_iommu_ctx * ctx,unsigned reg,u64 val)97 iommu_writeq(struct qcom_iommu_ctx *ctx, unsigned reg, u64 val)
98 {
99 writeq_relaxed(val, ctx->base + reg);
100 }
101
102 static inline u32
iommu_readl(struct qcom_iommu_ctx * ctx,unsigned reg)103 iommu_readl(struct qcom_iommu_ctx *ctx, unsigned reg)
104 {
105 return readl_relaxed(ctx->base + reg);
106 }
107
108 static inline u64
iommu_readq(struct qcom_iommu_ctx * ctx,unsigned reg)109 iommu_readq(struct qcom_iommu_ctx *ctx, unsigned reg)
110 {
111 return readq_relaxed(ctx->base + reg);
112 }
113
qcom_iommu_tlb_sync(void * cookie)114 static void qcom_iommu_tlb_sync(void *cookie)
115 {
116 struct qcom_iommu_domain *qcom_domain = cookie;
117 struct iommu_fwspec *fwspec = qcom_domain->fwspec;
118 unsigned i;
119
120 for (i = 0; i < fwspec->num_ids; i++) {
121 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
122 unsigned int val, ret;
123
124 iommu_writel(ctx, ARM_SMMU_CB_TLBSYNC, 0);
125
126 ret = readl_poll_timeout(ctx->base + ARM_SMMU_CB_TLBSTATUS, val,
127 (val & 0x1) == 0, 0, 5000000);
128 if (ret)
129 dev_err(ctx->dev, "timeout waiting for TLB SYNC\n");
130 }
131 }
132
qcom_iommu_tlb_inv_context(void * cookie)133 static void qcom_iommu_tlb_inv_context(void *cookie)
134 {
135 struct qcom_iommu_domain *qcom_domain = cookie;
136 struct iommu_fwspec *fwspec = qcom_domain->fwspec;
137 unsigned i;
138
139 for (i = 0; i < fwspec->num_ids; i++) {
140 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
141 iommu_writel(ctx, ARM_SMMU_CB_S1_TLBIASID, ctx->asid);
142 }
143
144 qcom_iommu_tlb_sync(cookie);
145 }
146
qcom_iommu_tlb_inv_range_nosync(unsigned long iova,size_t size,size_t granule,bool leaf,void * cookie)147 static void qcom_iommu_tlb_inv_range_nosync(unsigned long iova, size_t size,
148 size_t granule, bool leaf, void *cookie)
149 {
150 struct qcom_iommu_domain *qcom_domain = cookie;
151 struct iommu_fwspec *fwspec = qcom_domain->fwspec;
152 unsigned i, reg;
153
154 reg = leaf ? ARM_SMMU_CB_S1_TLBIVAL : ARM_SMMU_CB_S1_TLBIVA;
155
156 for (i = 0; i < fwspec->num_ids; i++) {
157 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
158 size_t s = size;
159
160 iova = (iova >> 12) << 12;
161 iova |= ctx->asid;
162 do {
163 iommu_writel(ctx, reg, iova);
164 iova += granule;
165 } while (s -= granule);
166 }
167 }
168
qcom_iommu_tlb_flush_walk(unsigned long iova,size_t size,size_t granule,void * cookie)169 static void qcom_iommu_tlb_flush_walk(unsigned long iova, size_t size,
170 size_t granule, void *cookie)
171 {
172 qcom_iommu_tlb_inv_range_nosync(iova, size, granule, false, cookie);
173 qcom_iommu_tlb_sync(cookie);
174 }
175
qcom_iommu_tlb_add_page(struct iommu_iotlb_gather * gather,unsigned long iova,size_t granule,void * cookie)176 static void qcom_iommu_tlb_add_page(struct iommu_iotlb_gather *gather,
177 unsigned long iova, size_t granule,
178 void *cookie)
179 {
180 qcom_iommu_tlb_inv_range_nosync(iova, granule, granule, true, cookie);
181 }
182
183 static const struct iommu_flush_ops qcom_flush_ops = {
184 .tlb_flush_all = qcom_iommu_tlb_inv_context,
185 .tlb_flush_walk = qcom_iommu_tlb_flush_walk,
186 .tlb_add_page = qcom_iommu_tlb_add_page,
187 };
188
qcom_iommu_fault(int irq,void * dev)189 static irqreturn_t qcom_iommu_fault(int irq, void *dev)
190 {
191 struct qcom_iommu_ctx *ctx = dev;
192 u32 fsr, fsynr;
193 u64 iova;
194
195 fsr = iommu_readl(ctx, ARM_SMMU_CB_FSR);
196
197 if (!(fsr & ARM_SMMU_CB_FSR_FAULT))
198 return IRQ_NONE;
199
200 fsynr = iommu_readl(ctx, ARM_SMMU_CB_FSYNR0);
201 iova = iommu_readq(ctx, ARM_SMMU_CB_FAR);
202
203 if (!report_iommu_fault(ctx->domain, ctx->dev, iova, 0)) {
204 dev_err_ratelimited(ctx->dev,
205 "Unhandled context fault: fsr=0x%x, "
206 "iova=0x%016llx, fsynr=0x%x, cb=%d\n",
207 fsr, iova, fsynr, ctx->asid);
208 }
209
210 iommu_writel(ctx, ARM_SMMU_CB_FSR, fsr);
211 iommu_writel(ctx, ARM_SMMU_CB_RESUME, ARM_SMMU_RESUME_TERMINATE);
212
213 return IRQ_HANDLED;
214 }
215
qcom_iommu_init_domain(struct iommu_domain * domain,struct qcom_iommu_dev * qcom_iommu,struct device * dev)216 static int qcom_iommu_init_domain(struct iommu_domain *domain,
217 struct qcom_iommu_dev *qcom_iommu,
218 struct device *dev)
219 {
220 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
221 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
222 struct io_pgtable_ops *pgtbl_ops;
223 struct io_pgtable_cfg pgtbl_cfg;
224 int i, ret = 0;
225 u32 reg;
226
227 mutex_lock(&qcom_domain->init_mutex);
228 if (qcom_domain->iommu)
229 goto out_unlock;
230
231 pgtbl_cfg = (struct io_pgtable_cfg) {
232 .pgsize_bitmap = domain->pgsize_bitmap,
233 .ias = 32,
234 .oas = 40,
235 .tlb = &qcom_flush_ops,
236 .iommu_dev = qcom_iommu->dev,
237 };
238
239 qcom_domain->iommu = qcom_iommu;
240 qcom_domain->fwspec = fwspec;
241
242 pgtbl_ops = alloc_io_pgtable_ops(ARM_32_LPAE_S1, &pgtbl_cfg, qcom_domain);
243 if (!pgtbl_ops) {
244 dev_err(qcom_iommu->dev, "failed to allocate pagetable ops\n");
245 ret = -ENOMEM;
246 goto out_clear_iommu;
247 }
248
249 domain->geometry.aperture_end = (1ULL << pgtbl_cfg.ias) - 1;
250 domain->geometry.force_aperture = true;
251
252 for (i = 0; i < fwspec->num_ids; i++) {
253 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
254
255 if (!ctx->secure_init) {
256 ret = qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, ctx->asid);
257 if (ret) {
258 dev_err(qcom_iommu->dev, "secure init failed: %d\n", ret);
259 goto out_clear_iommu;
260 }
261 ctx->secure_init = true;
262 }
263
264 /* Secured QSMMU-500/QSMMU-v2 contexts cannot be programmed */
265 if (ctx->secured_ctx) {
266 ctx->domain = domain;
267 continue;
268 }
269
270 /* Disable context bank before programming */
271 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
272
273 /* Clear context bank fault address fault status registers */
274 iommu_writel(ctx, ARM_SMMU_CB_FAR, 0);
275 iommu_writel(ctx, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT);
276
277 /* TTBRs */
278 iommu_writeq(ctx, ARM_SMMU_CB_TTBR0,
279 pgtbl_cfg.arm_lpae_s1_cfg.ttbr |
280 FIELD_PREP(ARM_SMMU_TTBRn_ASID, ctx->asid));
281 iommu_writeq(ctx, ARM_SMMU_CB_TTBR1, 0);
282
283 /* TCR */
284 iommu_writel(ctx, ARM_SMMU_CB_TCR2,
285 arm_smmu_lpae_tcr2(&pgtbl_cfg));
286 iommu_writel(ctx, ARM_SMMU_CB_TCR,
287 arm_smmu_lpae_tcr(&pgtbl_cfg) | ARM_SMMU_TCR_EAE);
288
289 /* MAIRs (stage-1 only) */
290 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR0,
291 pgtbl_cfg.arm_lpae_s1_cfg.mair);
292 iommu_writel(ctx, ARM_SMMU_CB_S1_MAIR1,
293 pgtbl_cfg.arm_lpae_s1_cfg.mair >> 32);
294
295 /* SCTLR */
296 reg = ARM_SMMU_SCTLR_CFIE | ARM_SMMU_SCTLR_CFRE |
297 ARM_SMMU_SCTLR_AFE | ARM_SMMU_SCTLR_TRE |
298 ARM_SMMU_SCTLR_M | ARM_SMMU_SCTLR_S1_ASIDPNE |
299 ARM_SMMU_SCTLR_CFCFG;
300
301 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
302 reg |= ARM_SMMU_SCTLR_E;
303
304 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, reg);
305
306 ctx->domain = domain;
307 }
308
309 mutex_unlock(&qcom_domain->init_mutex);
310
311 /* Publish page table ops for map/unmap */
312 qcom_domain->pgtbl_ops = pgtbl_ops;
313
314 return 0;
315
316 out_clear_iommu:
317 qcom_domain->iommu = NULL;
318 out_unlock:
319 mutex_unlock(&qcom_domain->init_mutex);
320 return ret;
321 }
322
qcom_iommu_domain_alloc_paging(struct device * dev)323 static struct iommu_domain *qcom_iommu_domain_alloc_paging(struct device *dev)
324 {
325 struct qcom_iommu_domain *qcom_domain;
326
327 /*
328 * Allocate the domain and initialise some of its data structures.
329 * We can't really do anything meaningful until we've added a
330 * master.
331 */
332 qcom_domain = kzalloc(sizeof(*qcom_domain), GFP_KERNEL);
333 if (!qcom_domain)
334 return NULL;
335
336 mutex_init(&qcom_domain->init_mutex);
337 spin_lock_init(&qcom_domain->pgtbl_lock);
338 qcom_domain->domain.pgsize_bitmap = SZ_4K;
339
340 return &qcom_domain->domain;
341 }
342
qcom_iommu_domain_free(struct iommu_domain * domain)343 static void qcom_iommu_domain_free(struct iommu_domain *domain)
344 {
345 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
346
347 if (qcom_domain->iommu) {
348 /*
349 * NOTE: unmap can be called after client device is powered
350 * off, for example, with GPUs or anything involving dma-buf.
351 * So we cannot rely on the device_link. Make sure the IOMMU
352 * is on to avoid unclocked accesses in the TLB inv path:
353 */
354 pm_runtime_get_sync(qcom_domain->iommu->dev);
355 free_io_pgtable_ops(qcom_domain->pgtbl_ops);
356 pm_runtime_put_sync(qcom_domain->iommu->dev);
357 }
358
359 kfree(qcom_domain);
360 }
361
qcom_iommu_attach_dev(struct iommu_domain * domain,struct device * dev)362 static int qcom_iommu_attach_dev(struct iommu_domain *domain, struct device *dev)
363 {
364 struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev);
365 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
366 int ret;
367
368 if (!qcom_iommu) {
369 dev_err(dev, "cannot attach to IOMMU, is it on the same bus?\n");
370 return -ENXIO;
371 }
372
373 /* Ensure that the domain is finalized */
374 pm_runtime_get_sync(qcom_iommu->dev);
375 ret = qcom_iommu_init_domain(domain, qcom_iommu, dev);
376 pm_runtime_put_sync(qcom_iommu->dev);
377 if (ret < 0)
378 return ret;
379
380 /*
381 * Sanity check the domain. We don't support domains across
382 * different IOMMUs.
383 */
384 if (qcom_domain->iommu != qcom_iommu)
385 return -EINVAL;
386
387 return 0;
388 }
389
qcom_iommu_identity_attach(struct iommu_domain * identity_domain,struct device * dev)390 static int qcom_iommu_identity_attach(struct iommu_domain *identity_domain,
391 struct device *dev)
392 {
393 struct iommu_domain *domain = iommu_get_domain_for_dev(dev);
394 struct qcom_iommu_domain *qcom_domain;
395 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(dev);
396 struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev);
397 unsigned int i;
398
399 if (domain == identity_domain || !domain)
400 return 0;
401
402 qcom_domain = to_qcom_iommu_domain(domain);
403 if (WARN_ON(!qcom_domain->iommu))
404 return -EINVAL;
405
406 pm_runtime_get_sync(qcom_iommu->dev);
407 for (i = 0; i < fwspec->num_ids; i++) {
408 struct qcom_iommu_ctx *ctx = to_ctx(qcom_domain, fwspec->ids[i]);
409
410 /* Disable the context bank: */
411 iommu_writel(ctx, ARM_SMMU_CB_SCTLR, 0);
412
413 ctx->domain = NULL;
414 }
415 pm_runtime_put_sync(qcom_iommu->dev);
416 return 0;
417 }
418
419 static struct iommu_domain_ops qcom_iommu_identity_ops = {
420 .attach_dev = qcom_iommu_identity_attach,
421 };
422
423 static struct iommu_domain qcom_iommu_identity_domain = {
424 .type = IOMMU_DOMAIN_IDENTITY,
425 .ops = &qcom_iommu_identity_ops,
426 };
427
qcom_iommu_map(struct iommu_domain * domain,unsigned long iova,phys_addr_t paddr,size_t pgsize,size_t pgcount,int prot,gfp_t gfp,size_t * mapped)428 static int qcom_iommu_map(struct iommu_domain *domain, unsigned long iova,
429 phys_addr_t paddr, size_t pgsize, size_t pgcount,
430 int prot, gfp_t gfp, size_t *mapped)
431 {
432 int ret;
433 unsigned long flags;
434 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
435 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
436
437 if (!ops)
438 return -ENODEV;
439
440 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
441 ret = ops->map_pages(ops, iova, paddr, pgsize, pgcount, prot, GFP_ATOMIC, mapped);
442 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
443 return ret;
444 }
445
qcom_iommu_unmap(struct iommu_domain * domain,unsigned long iova,size_t pgsize,size_t pgcount,struct iommu_iotlb_gather * gather)446 static size_t qcom_iommu_unmap(struct iommu_domain *domain, unsigned long iova,
447 size_t pgsize, size_t pgcount,
448 struct iommu_iotlb_gather *gather)
449 {
450 size_t ret;
451 unsigned long flags;
452 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
453 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
454
455 if (!ops)
456 return 0;
457
458 /* NOTE: unmap can be called after client device is powered off,
459 * for example, with GPUs or anything involving dma-buf. So we
460 * cannot rely on the device_link. Make sure the IOMMU is on to
461 * avoid unclocked accesses in the TLB inv path:
462 */
463 pm_runtime_get_sync(qcom_domain->iommu->dev);
464 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
465 ret = ops->unmap_pages(ops, iova, pgsize, pgcount, gather);
466 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
467 pm_runtime_put_sync(qcom_domain->iommu->dev);
468
469 return ret;
470 }
471
qcom_iommu_flush_iotlb_all(struct iommu_domain * domain)472 static void qcom_iommu_flush_iotlb_all(struct iommu_domain *domain)
473 {
474 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
475 struct io_pgtable *pgtable = container_of(qcom_domain->pgtbl_ops,
476 struct io_pgtable, ops);
477 if (!qcom_domain->pgtbl_ops)
478 return;
479
480 pm_runtime_get_sync(qcom_domain->iommu->dev);
481 qcom_iommu_tlb_sync(pgtable->cookie);
482 pm_runtime_put_sync(qcom_domain->iommu->dev);
483 }
484
qcom_iommu_iotlb_sync(struct iommu_domain * domain,struct iommu_iotlb_gather * gather)485 static void qcom_iommu_iotlb_sync(struct iommu_domain *domain,
486 struct iommu_iotlb_gather *gather)
487 {
488 qcom_iommu_flush_iotlb_all(domain);
489 }
490
qcom_iommu_iova_to_phys(struct iommu_domain * domain,dma_addr_t iova)491 static phys_addr_t qcom_iommu_iova_to_phys(struct iommu_domain *domain,
492 dma_addr_t iova)
493 {
494 phys_addr_t ret;
495 unsigned long flags;
496 struct qcom_iommu_domain *qcom_domain = to_qcom_iommu_domain(domain);
497 struct io_pgtable_ops *ops = qcom_domain->pgtbl_ops;
498
499 if (!ops)
500 return 0;
501
502 spin_lock_irqsave(&qcom_domain->pgtbl_lock, flags);
503 ret = ops->iova_to_phys(ops, iova);
504 spin_unlock_irqrestore(&qcom_domain->pgtbl_lock, flags);
505
506 return ret;
507 }
508
qcom_iommu_capable(struct device * dev,enum iommu_cap cap)509 static bool qcom_iommu_capable(struct device *dev, enum iommu_cap cap)
510 {
511 switch (cap) {
512 case IOMMU_CAP_CACHE_COHERENCY:
513 /*
514 * Return true here as the SMMU can always send out coherent
515 * requests.
516 */
517 return true;
518 case IOMMU_CAP_NOEXEC:
519 return true;
520 default:
521 return false;
522 }
523 }
524
qcom_iommu_probe_device(struct device * dev)525 static struct iommu_device *qcom_iommu_probe_device(struct device *dev)
526 {
527 struct qcom_iommu_dev *qcom_iommu = dev_iommu_priv_get(dev);
528 struct device_link *link;
529
530 if (!qcom_iommu)
531 return ERR_PTR(-ENODEV);
532
533 /*
534 * Establish the link between iommu and master, so that the
535 * iommu gets runtime enabled/disabled as per the master's
536 * needs.
537 */
538 link = device_link_add(dev, qcom_iommu->dev, DL_FLAG_PM_RUNTIME);
539 if (!link) {
540 dev_err(qcom_iommu->dev, "Unable to create device link between %s and %s\n",
541 dev_name(qcom_iommu->dev), dev_name(dev));
542 return ERR_PTR(-ENODEV);
543 }
544
545 return &qcom_iommu->iommu;
546 }
547
qcom_iommu_of_xlate(struct device * dev,const struct of_phandle_args * args)548 static int qcom_iommu_of_xlate(struct device *dev,
549 const struct of_phandle_args *args)
550 {
551 struct qcom_iommu_dev *qcom_iommu;
552 struct platform_device *iommu_pdev;
553 unsigned asid = args->args[0];
554
555 if (args->args_count != 1) {
556 dev_err(dev, "incorrect number of iommu params found for %s "
557 "(found %d, expected 1)\n",
558 args->np->full_name, args->args_count);
559 return -EINVAL;
560 }
561
562 iommu_pdev = of_find_device_by_node(args->np);
563 if (WARN_ON(!iommu_pdev))
564 return -EINVAL;
565
566 qcom_iommu = platform_get_drvdata(iommu_pdev);
567
568 /* make sure the asid specified in dt is valid, so we don't have
569 * to sanity check this elsewhere:
570 */
571 if (WARN_ON(asid > qcom_iommu->max_asid) ||
572 WARN_ON(qcom_iommu->ctxs[asid] == NULL)) {
573 put_device(&iommu_pdev->dev);
574 return -EINVAL;
575 }
576
577 if (!dev_iommu_priv_get(dev)) {
578 dev_iommu_priv_set(dev, qcom_iommu);
579 } else {
580 /* make sure devices iommus dt node isn't referring to
581 * multiple different iommu devices. Multiple context
582 * banks are ok, but multiple devices are not:
583 */
584 if (WARN_ON(qcom_iommu != dev_iommu_priv_get(dev))) {
585 put_device(&iommu_pdev->dev);
586 return -EINVAL;
587 }
588 }
589
590 return iommu_fwspec_add_ids(dev, &asid, 1);
591 }
592
593 static const struct iommu_ops qcom_iommu_ops = {
594 .identity_domain = &qcom_iommu_identity_domain,
595 .capable = qcom_iommu_capable,
596 .domain_alloc_paging = qcom_iommu_domain_alloc_paging,
597 .probe_device = qcom_iommu_probe_device,
598 .device_group = generic_device_group,
599 .of_xlate = qcom_iommu_of_xlate,
600 .default_domain_ops = &(const struct iommu_domain_ops) {
601 .attach_dev = qcom_iommu_attach_dev,
602 .map_pages = qcom_iommu_map,
603 .unmap_pages = qcom_iommu_unmap,
604 .flush_iotlb_all = qcom_iommu_flush_iotlb_all,
605 .iotlb_sync = qcom_iommu_iotlb_sync,
606 .iova_to_phys = qcom_iommu_iova_to_phys,
607 .free = qcom_iommu_domain_free,
608 }
609 };
610
qcom_iommu_sec_ptbl_init(struct device * dev)611 static int qcom_iommu_sec_ptbl_init(struct device *dev)
612 {
613 size_t psize = 0;
614 unsigned int spare = 0;
615 void *cpu_addr;
616 dma_addr_t paddr;
617 unsigned long attrs;
618 static bool allocated = false;
619 int ret;
620
621 if (allocated)
622 return 0;
623
624 ret = qcom_scm_iommu_secure_ptbl_size(spare, &psize);
625 if (ret) {
626 dev_err(dev, "failed to get iommu secure pgtable size (%d)\n",
627 ret);
628 return ret;
629 }
630
631 dev_info(dev, "iommu sec: pgtable size: %zu\n", psize);
632
633 attrs = DMA_ATTR_NO_KERNEL_MAPPING;
634
635 cpu_addr = dma_alloc_attrs(dev, psize, &paddr, GFP_KERNEL, attrs);
636 if (!cpu_addr) {
637 dev_err(dev, "failed to allocate %zu bytes for pgtable\n",
638 psize);
639 return -ENOMEM;
640 }
641
642 ret = qcom_scm_iommu_secure_ptbl_init(paddr, psize, spare);
643 if (ret) {
644 dev_err(dev, "failed to init iommu pgtable (%d)\n", ret);
645 goto free_mem;
646 }
647
648 allocated = true;
649 return 0;
650
651 free_mem:
652 dma_free_attrs(dev, psize, cpu_addr, paddr, attrs);
653 return ret;
654 }
655
get_asid(const struct device_node * np)656 static int get_asid(const struct device_node *np)
657 {
658 u32 reg, val;
659 int asid;
660
661 /* read the "reg" property directly to get the relative address
662 * of the context bank, and calculate the asid from that:
663 */
664 if (of_property_read_u32_index(np, "reg", 0, ®))
665 return -ENODEV;
666
667 /*
668 * Context banks are 0x1000 apart but, in some cases, the ASID
669 * number doesn't match to this logic and needs to be passed
670 * from the DT configuration explicitly.
671 */
672 if (!of_property_read_u32(np, "qcom,ctx-asid", &val))
673 asid = val;
674 else
675 asid = reg / 0x1000;
676
677 return asid;
678 }
679
qcom_iommu_ctx_probe(struct platform_device * pdev)680 static int qcom_iommu_ctx_probe(struct platform_device *pdev)
681 {
682 struct qcom_iommu_ctx *ctx;
683 struct device *dev = &pdev->dev;
684 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev->parent);
685 int ret, irq;
686
687 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL);
688 if (!ctx)
689 return -ENOMEM;
690
691 ctx->dev = dev;
692 platform_set_drvdata(pdev, ctx);
693
694 ctx->base = devm_platform_ioremap_resource(pdev, 0);
695 if (IS_ERR(ctx->base))
696 return PTR_ERR(ctx->base);
697
698 irq = platform_get_irq(pdev, 0);
699 if (irq < 0)
700 return irq;
701
702 if (of_device_is_compatible(dev->of_node, "qcom,msm-iommu-v2-sec"))
703 ctx->secured_ctx = true;
704
705 /* clear IRQs before registering fault handler, just in case the
706 * boot-loader left us a surprise:
707 */
708 if (!ctx->secured_ctx)
709 iommu_writel(ctx, ARM_SMMU_CB_FSR, iommu_readl(ctx, ARM_SMMU_CB_FSR));
710
711 ret = devm_request_irq(dev, irq,
712 qcom_iommu_fault,
713 IRQF_SHARED,
714 "qcom-iommu-fault",
715 ctx);
716 if (ret) {
717 dev_err(dev, "failed to request IRQ %u\n", irq);
718 return ret;
719 }
720
721 ret = get_asid(dev->of_node);
722 if (ret < 0) {
723 dev_err(dev, "missing reg property\n");
724 return ret;
725 }
726
727 ctx->asid = ret;
728
729 dev_dbg(dev, "found asid %u\n", ctx->asid);
730
731 qcom_iommu->ctxs[ctx->asid] = ctx;
732
733 return 0;
734 }
735
qcom_iommu_ctx_remove(struct platform_device * pdev)736 static void qcom_iommu_ctx_remove(struct platform_device *pdev)
737 {
738 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(pdev->dev.parent);
739 struct qcom_iommu_ctx *ctx = platform_get_drvdata(pdev);
740
741 platform_set_drvdata(pdev, NULL);
742
743 qcom_iommu->ctxs[ctx->asid] = NULL;
744 }
745
746 static const struct of_device_id ctx_of_match[] = {
747 { .compatible = "qcom,msm-iommu-v1-ns" },
748 { .compatible = "qcom,msm-iommu-v1-sec" },
749 { .compatible = "qcom,msm-iommu-v2-ns" },
750 { .compatible = "qcom,msm-iommu-v2-sec" },
751 { /* sentinel */ }
752 };
753
754 static struct platform_driver qcom_iommu_ctx_driver = {
755 .driver = {
756 .name = "qcom-iommu-ctx",
757 .of_match_table = ctx_of_match,
758 },
759 .probe = qcom_iommu_ctx_probe,
760 .remove = qcom_iommu_ctx_remove,
761 };
762
qcom_iommu_has_secure_context(struct qcom_iommu_dev * qcom_iommu)763 static bool qcom_iommu_has_secure_context(struct qcom_iommu_dev *qcom_iommu)
764 {
765 struct device_node *child;
766
767 for_each_child_of_node(qcom_iommu->dev->of_node, child) {
768 if (of_device_is_compatible(child, "qcom,msm-iommu-v1-sec") ||
769 of_device_is_compatible(child, "qcom,msm-iommu-v2-sec")) {
770 of_node_put(child);
771 return true;
772 }
773 }
774
775 return false;
776 }
777
qcom_iommu_device_probe(struct platform_device * pdev)778 static int qcom_iommu_device_probe(struct platform_device *pdev)
779 {
780 struct device_node *child;
781 struct qcom_iommu_dev *qcom_iommu;
782 struct device *dev = &pdev->dev;
783 struct resource *res;
784 struct clk *clk;
785 int ret, max_asid = 0;
786
787 /* find the max asid (which is 1:1 to ctx bank idx), so we know how
788 * many child ctx devices we have:
789 */
790 for_each_child_of_node(dev->of_node, child)
791 max_asid = max(max_asid, get_asid(child));
792
793 qcom_iommu = devm_kzalloc(dev, struct_size(qcom_iommu, ctxs, max_asid + 1),
794 GFP_KERNEL);
795 if (!qcom_iommu)
796 return -ENOMEM;
797 qcom_iommu->max_asid = max_asid;
798 qcom_iommu->dev = dev;
799
800 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
801 if (res) {
802 qcom_iommu->local_base = devm_ioremap_resource(dev, res);
803 if (IS_ERR(qcom_iommu->local_base))
804 return PTR_ERR(qcom_iommu->local_base);
805 }
806
807 clk = devm_clk_get(dev, "iface");
808 if (IS_ERR(clk)) {
809 dev_err(dev, "failed to get iface clock\n");
810 return PTR_ERR(clk);
811 }
812 qcom_iommu->clks[CLK_IFACE].clk = clk;
813
814 clk = devm_clk_get(dev, "bus");
815 if (IS_ERR(clk)) {
816 dev_err(dev, "failed to get bus clock\n");
817 return PTR_ERR(clk);
818 }
819 qcom_iommu->clks[CLK_BUS].clk = clk;
820
821 clk = devm_clk_get_optional(dev, "tbu");
822 if (IS_ERR(clk)) {
823 dev_err(dev, "failed to get tbu clock\n");
824 return PTR_ERR(clk);
825 }
826 qcom_iommu->clks[CLK_TBU].clk = clk;
827
828 if (of_property_read_u32(dev->of_node, "qcom,iommu-secure-id",
829 &qcom_iommu->sec_id)) {
830 dev_err(dev, "missing qcom,iommu-secure-id property\n");
831 return -ENODEV;
832 }
833
834 if (qcom_iommu_has_secure_context(qcom_iommu)) {
835 ret = qcom_iommu_sec_ptbl_init(dev);
836 if (ret) {
837 dev_err(dev, "cannot init secure pg table(%d)\n", ret);
838 return ret;
839 }
840 }
841
842 platform_set_drvdata(pdev, qcom_iommu);
843
844 pm_runtime_enable(dev);
845
846 /* register context bank devices, which are child nodes: */
847 ret = devm_of_platform_populate(dev);
848 if (ret) {
849 dev_err(dev, "Failed to populate iommu contexts\n");
850 goto err_pm_disable;
851 }
852
853 ret = iommu_device_sysfs_add(&qcom_iommu->iommu, dev, NULL,
854 dev_name(dev));
855 if (ret) {
856 dev_err(dev, "Failed to register iommu in sysfs\n");
857 goto err_pm_disable;
858 }
859
860 ret = iommu_device_register(&qcom_iommu->iommu, &qcom_iommu_ops, dev);
861 if (ret) {
862 dev_err(dev, "Failed to register iommu\n");
863 goto err_pm_disable;
864 }
865
866 if (qcom_iommu->local_base) {
867 pm_runtime_get_sync(dev);
868 writel_relaxed(0xffffffff, qcom_iommu->local_base + SMMU_INTR_SEL_NS);
869 pm_runtime_put_sync(dev);
870 }
871
872 return 0;
873
874 err_pm_disable:
875 pm_runtime_disable(dev);
876 return ret;
877 }
878
qcom_iommu_device_remove(struct platform_device * pdev)879 static void qcom_iommu_device_remove(struct platform_device *pdev)
880 {
881 struct qcom_iommu_dev *qcom_iommu = platform_get_drvdata(pdev);
882
883 pm_runtime_force_suspend(&pdev->dev);
884 platform_set_drvdata(pdev, NULL);
885 iommu_device_sysfs_remove(&qcom_iommu->iommu);
886 iommu_device_unregister(&qcom_iommu->iommu);
887 }
888
qcom_iommu_resume(struct device * dev)889 static int __maybe_unused qcom_iommu_resume(struct device *dev)
890 {
891 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);
892 int ret;
893
894 ret = clk_bulk_prepare_enable(CLK_NUM, qcom_iommu->clks);
895 if (ret < 0)
896 return ret;
897
898 if (dev->pm_domain)
899 return qcom_scm_restore_sec_cfg(qcom_iommu->sec_id, 0);
900
901 return ret;
902 }
903
qcom_iommu_suspend(struct device * dev)904 static int __maybe_unused qcom_iommu_suspend(struct device *dev)
905 {
906 struct qcom_iommu_dev *qcom_iommu = dev_get_drvdata(dev);
907
908 clk_bulk_disable_unprepare(CLK_NUM, qcom_iommu->clks);
909
910 return 0;
911 }
912
913 static const struct dev_pm_ops qcom_iommu_pm_ops = {
914 SET_RUNTIME_PM_OPS(qcom_iommu_suspend, qcom_iommu_resume, NULL)
915 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
916 pm_runtime_force_resume)
917 };
918
919 static const struct of_device_id qcom_iommu_of_match[] = {
920 { .compatible = "qcom,msm-iommu-v1" },
921 { .compatible = "qcom,msm-iommu-v2" },
922 { /* sentinel */ }
923 };
924
925 static struct platform_driver qcom_iommu_driver = {
926 .driver = {
927 .name = "qcom-iommu",
928 .of_match_table = qcom_iommu_of_match,
929 .pm = &qcom_iommu_pm_ops,
930 },
931 .probe = qcom_iommu_device_probe,
932 .remove = qcom_iommu_device_remove,
933 };
934
qcom_iommu_init(void)935 static int __init qcom_iommu_init(void)
936 {
937 int ret;
938
939 ret = platform_driver_register(&qcom_iommu_ctx_driver);
940 if (ret)
941 return ret;
942
943 ret = platform_driver_register(&qcom_iommu_driver);
944 if (ret)
945 platform_driver_unregister(&qcom_iommu_ctx_driver);
946
947 return ret;
948 }
949 device_initcall(qcom_iommu_init);
950