xref: /linux/drivers/clk/qcom/hfpll.c (revision 522ba450b56fff29f868b1552bdc2965f55de7ed)
1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2018, The Linux Foundation. All rights reserved.
3 
4 #include <linux/kernel.h>
5 #include <linux/init.h>
6 #include <linux/module.h>
7 #include <linux/platform_device.h>
8 #include <linux/of.h>
9 #include <linux/of_device.h>
10 #include <linux/clk.h>
11 #include <linux/clk-provider.h>
12 #include <linux/regmap.h>
13 
14 #include "clk-regmap.h"
15 #include "clk-hfpll.h"
16 
17 static const struct hfpll_data qcs404 = {
18 	.mode_reg = 0x00,
19 	.l_reg = 0x04,
20 	.m_reg = 0x08,
21 	.n_reg = 0x0c,
22 	.user_reg = 0x10,
23 	.config_reg = 0x14,
24 	.config_val = 0x430405d,
25 	.status_reg = 0x1c,
26 	.lock_bit = 16,
27 
28 	.user_val = 0x8,
29 	.user_vco_mask = 0x100000,
30 	.low_vco_max_rate = 1248000000,
31 	.min_rate = 537600000UL,
32 	.max_rate = 2900000000UL,
33 };
34 
35 static const struct hfpll_data msm8976_a53 = {
36 	.mode_reg = 0x00,
37 	.l_reg = 0x04,
38 	.m_reg = 0x08,
39 	.n_reg = 0x0c,
40 	.user_reg = 0x10,
41 	.config_reg = 0x14,
42 	.config_val = 0x341600,
43 	.status_reg = 0x1c,
44 	.lock_bit = 16,
45 
46 	.l_val = 0x35,
47 	.user_val = 0x109,
48 	.min_rate = 902400000UL,
49 	.max_rate = 1478400000UL,
50 };
51 
52 static const struct hfpll_data msm8976_a72 = {
53 	.mode_reg = 0x00,
54 	.l_reg = 0x04,
55 	.m_reg = 0x08,
56 	.n_reg = 0x0c,
57 	.user_reg = 0x10,
58 	.config_reg = 0x14,
59 	.config_val = 0x4e0405d,
60 	.status_reg = 0x1c,
61 	.lock_bit = 16,
62 
63 	.l_val = 0x3e,
64 	.user_val = 0x100109,
65 	.min_rate = 940800000UL,
66 	.max_rate = 2016000000UL,
67 };
68 
69 static const struct hfpll_data msm8976_cci = {
70 	.mode_reg = 0x00,
71 	.l_reg = 0x04,
72 	.m_reg = 0x08,
73 	.n_reg = 0x0c,
74 	.user_reg = 0x10,
75 	.config_reg = 0x14,
76 	.config_val = 0x141400,
77 	.status_reg = 0x1c,
78 	.lock_bit = 16,
79 
80 	.l_val = 0x20,
81 	.user_val = 0x100109,
82 	.min_rate = 556800000UL,
83 	.max_rate = 902400000UL,
84 };
85 
86 static const struct of_device_id qcom_hfpll_match_table[] = {
87 	{ .compatible = "qcom,msm8976-hfpll-a53", .data = &msm8976_a53 },
88 	{ .compatible = "qcom,msm8976-hfpll-a72", .data = &msm8976_a72 },
89 	{ .compatible = "qcom,msm8976-hfpll-cci", .data = &msm8976_cci },
90 	{ .compatible = "qcom,qcs404-hfpll", .data = &qcs404 },
91 	/* Deprecated in bindings */
92 	{ .compatible = "qcom,hfpll", .data = &qcs404 },
93 	{ }
94 };
95 MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table);
96 
97 static const struct regmap_config hfpll_regmap_config = {
98 	.reg_bits	= 32,
99 	.reg_stride	= 4,
100 	.val_bits	= 32,
101 	.max_register	= 0x30,
102 };
103 
qcom_hfpll_probe(struct platform_device * pdev)104 static int qcom_hfpll_probe(struct platform_device *pdev)
105 {
106 	struct device *dev = &pdev->dev;
107 	void __iomem *base;
108 	struct regmap *regmap;
109 	struct clk_hfpll *h;
110 	struct clk_init_data init = {
111 		.num_parents = 1,
112 		.ops = &clk_ops_hfpll,
113 		/*
114 		 * rather than marking the clock critical and forcing the clock
115 		 * to be always enabled, we make sure that the clock is not
116 		 * disabled: the firmware remains responsible of enabling this
117 		 * clock (for more info check the commit log)
118 		 */
119 		.flags = CLK_IGNORE_UNUSED,
120 	};
121 	int ret;
122 	struct clk_parent_data pdata = { .index = 0 };
123 
124 	h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL);
125 	if (!h)
126 		return -ENOMEM;
127 
128 	base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
129 	if (IS_ERR(base))
130 		return PTR_ERR(base);
131 
132 	regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config);
133 	if (IS_ERR(regmap))
134 		return PTR_ERR(regmap);
135 
136 	if (of_property_read_string_index(dev->of_node, "clock-output-names",
137 					  0, &init.name))
138 		return -ENODEV;
139 
140 	init.parent_data = &pdata;
141 
142 	h->d = of_device_get_match_data(&pdev->dev);
143 	h->clkr.hw.init = &init;
144 	spin_lock_init(&h->lock);
145 
146 	ret = devm_clk_register_regmap(dev, &h->clkr);
147 	if (ret) {
148 		dev_err(dev, "failed to register regmap clock: %d\n", ret);
149 		return ret;
150 	}
151 
152 	return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
153 					   &h->clkr.hw);
154 }
155 
156 static struct platform_driver qcom_hfpll_driver = {
157 	.probe		= qcom_hfpll_probe,
158 	.driver		= {
159 		.name	= "qcom-hfpll",
160 		.of_match_table = qcom_hfpll_match_table,
161 	},
162 };
163 module_platform_driver(qcom_hfpll_driver);
164 
165 MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
166 MODULE_LICENSE("GPL v2");
167 MODULE_ALIAS("platform:qcom-hfpll");
168