1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017-2018, The Linux foundation. All rights reserved.
3
4 /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */
5 #define __DISABLE_TRACE_MMIO__
6
7 #include <linux/clk.h>
8 #include <linux/console.h>
9 #include <linux/io.h>
10 #include <linux/iopoll.h>
11 #include <linux/irq.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/pm_opp.h>
15 #include <linux/platform_device.h>
16 #include <linux/pm_runtime.h>
17 #include <linux/pm_wakeirq.h>
18 #include <linux/soc/qcom/geni-se.h>
19 #include <linux/serial.h>
20 #include <linux/serial_core.h>
21 #include <linux/slab.h>
22 #include <linux/tty.h>
23 #include <linux/tty_flip.h>
24 #include <dt-bindings/interconnect/qcom,icc.h>
25
26 /* UART specific GENI registers */
27 #define SE_UART_LOOPBACK_CFG 0x22c
28 #define SE_UART_IO_MACRO_CTRL 0x240
29 #define SE_UART_TX_TRANS_CFG 0x25c
30 #define SE_UART_TX_WORD_LEN 0x268
31 #define SE_UART_TX_STOP_BIT_LEN 0x26c
32 #define SE_UART_TX_TRANS_LEN 0x270
33 #define SE_UART_RX_TRANS_CFG 0x280
34 #define SE_UART_RX_WORD_LEN 0x28c
35 #define SE_UART_RX_STALE_CNT 0x294
36 #define SE_UART_TX_PARITY_CFG 0x2a4
37 #define SE_UART_RX_PARITY_CFG 0x2a8
38 #define SE_UART_MANUAL_RFR 0x2ac
39
40 /* SE_UART_TRANS_CFG */
41 #define UART_TX_PAR_EN BIT(0)
42 #define UART_CTS_MASK BIT(1)
43
44 /* SE_UART_TX_STOP_BIT_LEN */
45 #define TX_STOP_BIT_LEN_1 0
46 #define TX_STOP_BIT_LEN_2 2
47
48 /* SE_UART_RX_TRANS_CFG */
49 #define UART_RX_PAR_EN BIT(3)
50
51 /* SE_UART_RX_WORD_LEN */
52 #define RX_WORD_LEN_MASK GENMASK(9, 0)
53
54 /* SE_UART_RX_STALE_CNT */
55 #define RX_STALE_CNT GENMASK(23, 0)
56
57 /* SE_UART_TX_PARITY_CFG/RX_PARITY_CFG */
58 #define PAR_CALC_EN BIT(0)
59 #define PAR_EVEN 0x00
60 #define PAR_ODD 0x01
61 #define PAR_SPACE 0x10
62
63 /* SE_UART_MANUAL_RFR register fields */
64 #define UART_MANUAL_RFR_EN BIT(31)
65 #define UART_RFR_NOT_READY BIT(1)
66 #define UART_RFR_READY BIT(0)
67
68 /* UART M_CMD OP codes */
69 #define UART_START_TX 0x1
70 /* UART S_CMD OP codes */
71 #define UART_START_READ 0x1
72 #define UART_PARAM 0x1
73 #define UART_PARAM_RFR_OPEN BIT(7)
74
75 #define UART_OVERSAMPLING 32
76 #define STALE_TIMEOUT 16
77 #define DEFAULT_BITS_PER_CHAR 10
78 #define GENI_UART_CONS_PORTS 1
79 #define GENI_UART_PORTS 3
80 #define DEF_FIFO_DEPTH_WORDS 16
81 #define DEF_TX_WM 2
82 #define DEF_FIFO_WIDTH_BITS 32
83 #define UART_RX_WM 2
84
85 /* SE_UART_LOOPBACK_CFG */
86 #define RX_TX_SORTED BIT(0)
87 #define CTS_RTS_SORTED BIT(1)
88 #define RX_TX_CTS_RTS_SORTED (RX_TX_SORTED | CTS_RTS_SORTED)
89
90 /* UART pin swap value */
91 #define DEFAULT_IO_MACRO_IO0_IO1_MASK GENMASK(3, 0)
92 #define IO_MACRO_IO0_SEL 0x3
93 #define DEFAULT_IO_MACRO_IO2_IO3_MASK GENMASK(15, 4)
94 #define IO_MACRO_IO2_IO3_SWAP 0x4640
95
96 /* We always configure 4 bytes per FIFO word */
97 #define BYTES_PER_FIFO_WORD 4U
98
99 #define DMA_RX_BUF_SIZE 2048
100
101 struct qcom_geni_device_data {
102 bool console;
103 enum geni_se_xfer_mode mode;
104 };
105
106 struct qcom_geni_private_data {
107 /* NOTE: earlycon port will have NULL here */
108 struct uart_driver *drv;
109
110 u32 poll_cached_bytes;
111 unsigned int poll_cached_bytes_cnt;
112
113 u32 write_cached_bytes;
114 unsigned int write_cached_bytes_cnt;
115 };
116
117 struct qcom_geni_serial_port {
118 struct uart_port uport;
119 struct geni_se se;
120 const char *name;
121 u32 tx_fifo_depth;
122 u32 tx_fifo_width;
123 u32 rx_fifo_depth;
124 dma_addr_t tx_dma_addr;
125 dma_addr_t rx_dma_addr;
126 bool setup;
127 unsigned int baud;
128 unsigned long clk_rate;
129 void *rx_buf;
130 u32 loopback;
131 bool brk;
132
133 unsigned int tx_remaining;
134 int wakeup_irq;
135 bool rx_tx_swap;
136 bool cts_rts_swap;
137
138 struct qcom_geni_private_data private_data;
139 const struct qcom_geni_device_data *dev_data;
140 };
141
142 static const struct uart_ops qcom_geni_console_pops;
143 static const struct uart_ops qcom_geni_uart_pops;
144 static struct uart_driver qcom_geni_console_driver;
145 static struct uart_driver qcom_geni_uart_driver;
146
to_dev_port(struct uart_port * uport)147 static inline struct qcom_geni_serial_port *to_dev_port(struct uart_port *uport)
148 {
149 return container_of(uport, struct qcom_geni_serial_port, uport);
150 }
151
152 static struct qcom_geni_serial_port qcom_geni_uart_ports[GENI_UART_PORTS] = {
153 [0] = {
154 .uport = {
155 .iotype = UPIO_MEM,
156 .ops = &qcom_geni_uart_pops,
157 .flags = UPF_BOOT_AUTOCONF,
158 .line = 0,
159 },
160 },
161 [1] = {
162 .uport = {
163 .iotype = UPIO_MEM,
164 .ops = &qcom_geni_uart_pops,
165 .flags = UPF_BOOT_AUTOCONF,
166 .line = 1,
167 },
168 },
169 [2] = {
170 .uport = {
171 .iotype = UPIO_MEM,
172 .ops = &qcom_geni_uart_pops,
173 .flags = UPF_BOOT_AUTOCONF,
174 .line = 2,
175 },
176 },
177 };
178
179 static struct qcom_geni_serial_port qcom_geni_console_port = {
180 .uport = {
181 .iotype = UPIO_MEM,
182 .ops = &qcom_geni_console_pops,
183 .flags = UPF_BOOT_AUTOCONF,
184 .line = 0,
185 },
186 };
187
qcom_geni_serial_request_port(struct uart_port * uport)188 static int qcom_geni_serial_request_port(struct uart_port *uport)
189 {
190 struct platform_device *pdev = to_platform_device(uport->dev);
191 struct qcom_geni_serial_port *port = to_dev_port(uport);
192
193 uport->membase = devm_platform_ioremap_resource(pdev, 0);
194 if (IS_ERR(uport->membase))
195 return PTR_ERR(uport->membase);
196 port->se.base = uport->membase;
197 return 0;
198 }
199
qcom_geni_serial_config_port(struct uart_port * uport,int cfg_flags)200 static void qcom_geni_serial_config_port(struct uart_port *uport, int cfg_flags)
201 {
202 if (cfg_flags & UART_CONFIG_TYPE) {
203 uport->type = PORT_MSM;
204 qcom_geni_serial_request_port(uport);
205 }
206 }
207
qcom_geni_serial_get_mctrl(struct uart_port * uport)208 static unsigned int qcom_geni_serial_get_mctrl(struct uart_port *uport)
209 {
210 unsigned int mctrl = TIOCM_DSR | TIOCM_CAR;
211 u32 geni_ios;
212
213 if (uart_console(uport)) {
214 mctrl |= TIOCM_CTS;
215 } else {
216 geni_ios = readl(uport->membase + SE_GENI_IOS);
217 if (!(geni_ios & IO2_DATA_IN))
218 mctrl |= TIOCM_CTS;
219 }
220
221 return mctrl;
222 }
223
qcom_geni_serial_set_mctrl(struct uart_port * uport,unsigned int mctrl)224 static void qcom_geni_serial_set_mctrl(struct uart_port *uport,
225 unsigned int mctrl)
226 {
227 u32 uart_manual_rfr = 0;
228 struct qcom_geni_serial_port *port = to_dev_port(uport);
229
230 if (uart_console(uport))
231 return;
232
233 if (mctrl & TIOCM_LOOP)
234 port->loopback = RX_TX_CTS_RTS_SORTED;
235
236 if (!(mctrl & TIOCM_RTS) && !uport->suspended)
237 uart_manual_rfr = UART_MANUAL_RFR_EN | UART_RFR_NOT_READY;
238 writel(uart_manual_rfr, uport->membase + SE_UART_MANUAL_RFR);
239 }
240
qcom_geni_serial_get_type(struct uart_port * uport)241 static const char *qcom_geni_serial_get_type(struct uart_port *uport)
242 {
243 return "MSM";
244 }
245
get_port_from_line(int line,bool console)246 static struct qcom_geni_serial_port *get_port_from_line(int line, bool console)
247 {
248 struct qcom_geni_serial_port *port;
249 int nr_ports = console ? GENI_UART_CONS_PORTS : GENI_UART_PORTS;
250
251 if (line < 0 || line >= nr_ports)
252 return ERR_PTR(-ENXIO);
253
254 port = console ? &qcom_geni_console_port : &qcom_geni_uart_ports[line];
255 return port;
256 }
257
qcom_geni_serial_main_active(struct uart_port * uport)258 static bool qcom_geni_serial_main_active(struct uart_port *uport)
259 {
260 return readl(uport->membase + SE_GENI_STATUS) & M_GENI_CMD_ACTIVE;
261 }
262
qcom_geni_serial_secondary_active(struct uart_port * uport)263 static bool qcom_geni_serial_secondary_active(struct uart_port *uport)
264 {
265 return readl(uport->membase + SE_GENI_STATUS) & S_GENI_CMD_ACTIVE;
266 }
267
qcom_geni_serial_poll_bit(struct uart_port * uport,int offset,int field,bool set)268 static bool qcom_geni_serial_poll_bit(struct uart_port *uport,
269 int offset, int field, bool set)
270 {
271 u32 reg;
272 struct qcom_geni_serial_port *port;
273 unsigned int baud;
274 unsigned int fifo_bits;
275 unsigned long timeout_us = 20000;
276 struct qcom_geni_private_data *private_data = uport->private_data;
277
278 if (private_data->drv) {
279 port = to_dev_port(uport);
280 baud = port->baud;
281 if (!baud)
282 baud = 115200;
283 fifo_bits = port->tx_fifo_depth * port->tx_fifo_width;
284 /*
285 * Total polling iterations based on FIFO worth of bytes to be
286 * sent at current baud. Add a little fluff to the wait.
287 */
288 timeout_us = ((fifo_bits * USEC_PER_SEC) / baud) + 500;
289 }
290
291 /*
292 * Use custom implementation instead of readl_poll_atomic since ktimer
293 * is not ready at the time of early console.
294 */
295 timeout_us = DIV_ROUND_UP(timeout_us, 10) * 10;
296 while (timeout_us) {
297 reg = readl(uport->membase + offset);
298 if ((bool)(reg & field) == set)
299 return true;
300 udelay(10);
301 timeout_us -= 10;
302 }
303 return false;
304 }
305
qcom_geni_serial_setup_tx(struct uart_port * uport,u32 xmit_size)306 static void qcom_geni_serial_setup_tx(struct uart_port *uport, u32 xmit_size)
307 {
308 u32 m_cmd;
309
310 writel(xmit_size, uport->membase + SE_UART_TX_TRANS_LEN);
311 m_cmd = UART_START_TX << M_OPCODE_SHFT;
312 writel(m_cmd, uport->membase + SE_GENI_M_CMD0);
313 }
314
qcom_geni_serial_poll_tx_done(struct uart_port * uport)315 static void qcom_geni_serial_poll_tx_done(struct uart_port *uport)
316 {
317 int done;
318 u32 irq_clear = M_CMD_DONE_EN;
319
320 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
321 M_CMD_DONE_EN, true);
322 if (!done) {
323 writel(M_GENI_CMD_ABORT, uport->membase +
324 SE_GENI_M_CMD_CTRL_REG);
325 irq_clear |= M_CMD_ABORT_EN;
326 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
327 M_CMD_ABORT_EN, true);
328 }
329 writel(irq_clear, uport->membase + SE_GENI_M_IRQ_CLEAR);
330 }
331
qcom_geni_serial_abort_rx(struct uart_port * uport)332 static void qcom_geni_serial_abort_rx(struct uart_port *uport)
333 {
334 u32 irq_clear = S_CMD_DONE_EN | S_CMD_ABORT_EN;
335
336 writel(S_GENI_CMD_ABORT, uport->membase + SE_GENI_S_CMD_CTRL_REG);
337 qcom_geni_serial_poll_bit(uport, SE_GENI_S_CMD_CTRL_REG,
338 S_GENI_CMD_ABORT, false);
339 writel(irq_clear, uport->membase + SE_GENI_S_IRQ_CLEAR);
340 writel(FORCE_DEFAULT, uport->membase + GENI_FORCE_DEFAULT_REG);
341 }
342
343 #ifdef CONFIG_CONSOLE_POLL
qcom_geni_serial_get_char(struct uart_port * uport)344 static int qcom_geni_serial_get_char(struct uart_port *uport)
345 {
346 struct qcom_geni_private_data *private_data = uport->private_data;
347 u32 status;
348 u32 word_cnt;
349 int ret;
350
351 if (!private_data->poll_cached_bytes_cnt) {
352 status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
353 writel(status, uport->membase + SE_GENI_M_IRQ_CLEAR);
354
355 status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
356 writel(status, uport->membase + SE_GENI_S_IRQ_CLEAR);
357
358 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
359 word_cnt = status & RX_FIFO_WC_MSK;
360 if (!word_cnt)
361 return NO_POLL_CHAR;
362
363 if (word_cnt == 1 && (status & RX_LAST))
364 /*
365 * NOTE: If RX_LAST_BYTE_VALID is 0 it needs to be
366 * treated as if it was BYTES_PER_FIFO_WORD.
367 */
368 private_data->poll_cached_bytes_cnt =
369 (status & RX_LAST_BYTE_VALID_MSK) >>
370 RX_LAST_BYTE_VALID_SHFT;
371
372 if (private_data->poll_cached_bytes_cnt == 0)
373 private_data->poll_cached_bytes_cnt = BYTES_PER_FIFO_WORD;
374
375 private_data->poll_cached_bytes =
376 readl(uport->membase + SE_GENI_RX_FIFOn);
377 }
378
379 private_data->poll_cached_bytes_cnt--;
380 ret = private_data->poll_cached_bytes & 0xff;
381 private_data->poll_cached_bytes >>= 8;
382
383 return ret;
384 }
385
qcom_geni_serial_poll_put_char(struct uart_port * uport,unsigned char c)386 static void qcom_geni_serial_poll_put_char(struct uart_port *uport,
387 unsigned char c)
388 {
389 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
390 qcom_geni_serial_setup_tx(uport, 1);
391 WARN_ON(!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
392 M_TX_FIFO_WATERMARK_EN, true));
393 writel(c, uport->membase + SE_GENI_TX_FIFOn);
394 writel(M_TX_FIFO_WATERMARK_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
395 qcom_geni_serial_poll_tx_done(uport);
396 }
397 #endif
398
399 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
qcom_geni_serial_wr_char(struct uart_port * uport,unsigned char ch)400 static void qcom_geni_serial_wr_char(struct uart_port *uport, unsigned char ch)
401 {
402 struct qcom_geni_private_data *private_data = uport->private_data;
403
404 private_data->write_cached_bytes =
405 (private_data->write_cached_bytes >> 8) | (ch << 24);
406 private_data->write_cached_bytes_cnt++;
407
408 if (private_data->write_cached_bytes_cnt == BYTES_PER_FIFO_WORD) {
409 writel(private_data->write_cached_bytes,
410 uport->membase + SE_GENI_TX_FIFOn);
411 private_data->write_cached_bytes_cnt = 0;
412 }
413 }
414
415 static void
__qcom_geni_serial_console_write(struct uart_port * uport,const char * s,unsigned int count)416 __qcom_geni_serial_console_write(struct uart_port *uport, const char *s,
417 unsigned int count)
418 {
419 struct qcom_geni_private_data *private_data = uport->private_data;
420
421 int i;
422 u32 bytes_to_send = count;
423
424 for (i = 0; i < count; i++) {
425 /*
426 * uart_console_write() adds a carriage return for each newline.
427 * Account for additional bytes to be written.
428 */
429 if (s[i] == '\n')
430 bytes_to_send++;
431 }
432
433 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
434 qcom_geni_serial_setup_tx(uport, bytes_to_send);
435 for (i = 0; i < count; ) {
436 size_t chars_to_write = 0;
437 size_t avail = DEF_FIFO_DEPTH_WORDS - DEF_TX_WM;
438
439 /*
440 * If the WM bit never set, then the Tx state machine is not
441 * in a valid state, so break, cancel/abort any existing
442 * command. Unfortunately the current data being written is
443 * lost.
444 */
445 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
446 M_TX_FIFO_WATERMARK_EN, true))
447 break;
448 chars_to_write = min_t(size_t, count - i, avail / 2);
449 uart_console_write(uport, s + i, chars_to_write,
450 qcom_geni_serial_wr_char);
451 writel(M_TX_FIFO_WATERMARK_EN, uport->membase +
452 SE_GENI_M_IRQ_CLEAR);
453 i += chars_to_write;
454 }
455
456 if (private_data->write_cached_bytes_cnt) {
457 private_data->write_cached_bytes >>= BITS_PER_BYTE *
458 (BYTES_PER_FIFO_WORD - private_data->write_cached_bytes_cnt);
459 writel(private_data->write_cached_bytes,
460 uport->membase + SE_GENI_TX_FIFOn);
461 private_data->write_cached_bytes_cnt = 0;
462 }
463
464 qcom_geni_serial_poll_tx_done(uport);
465 }
466
qcom_geni_serial_console_write(struct console * co,const char * s,unsigned int count)467 static void qcom_geni_serial_console_write(struct console *co, const char *s,
468 unsigned int count)
469 {
470 struct uart_port *uport;
471 struct qcom_geni_serial_port *port;
472 bool locked = true;
473 unsigned long flags;
474 u32 geni_status;
475 u32 irq_en;
476
477 WARN_ON(co->index < 0 || co->index >= GENI_UART_CONS_PORTS);
478
479 port = get_port_from_line(co->index, true);
480 if (IS_ERR(port))
481 return;
482
483 uport = &port->uport;
484 if (oops_in_progress)
485 locked = uart_port_trylock_irqsave(uport, &flags);
486 else
487 uart_port_lock_irqsave(uport, &flags);
488
489 geni_status = readl(uport->membase + SE_GENI_STATUS);
490
491 if (!locked) {
492 /*
493 * We can only get here if an oops is in progress then we were
494 * unable to get the lock. This means we can't safely access
495 * our state variables like tx_remaining. About the best we
496 * can do is wait for the FIFO to be empty before we start our
497 * transfer, so we'll do that.
498 */
499 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
500 M_TX_FIFO_NOT_EMPTY_EN, false);
501 } else if ((geni_status & M_GENI_CMD_ACTIVE) && !port->tx_remaining) {
502 /*
503 * It seems we can't interrupt existing transfers if all data
504 * has been sent, in which case we need to look for done first.
505 */
506 qcom_geni_serial_poll_tx_done(uport);
507
508 if (!kfifo_is_empty(&uport->state->port.xmit_fifo)) {
509 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
510 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
511 uport->membase + SE_GENI_M_IRQ_EN);
512 }
513 }
514
515 __qcom_geni_serial_console_write(uport, s, count);
516
517
518 if (locked) {
519 if (port->tx_remaining)
520 qcom_geni_serial_setup_tx(uport, port->tx_remaining);
521 uart_port_unlock_irqrestore(uport, flags);
522 }
523 }
524
handle_rx_console(struct uart_port * uport,u32 bytes,bool drop)525 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
526 {
527 u32 i;
528 unsigned char buf[sizeof(u32)];
529 struct tty_port *tport;
530 struct qcom_geni_serial_port *port = to_dev_port(uport);
531
532 tport = &uport->state->port;
533 for (i = 0; i < bytes; ) {
534 int c;
535 int chunk = min_t(int, bytes - i, BYTES_PER_FIFO_WORD);
536
537 ioread32_rep(uport->membase + SE_GENI_RX_FIFOn, buf, 1);
538 i += chunk;
539 if (drop)
540 continue;
541
542 for (c = 0; c < chunk; c++) {
543 int sysrq;
544
545 uport->icount.rx++;
546 if (port->brk && buf[c] == 0) {
547 port->brk = false;
548 if (uart_handle_break(uport))
549 continue;
550 }
551
552 sysrq = uart_prepare_sysrq_char(uport, buf[c]);
553
554 if (!sysrq)
555 tty_insert_flip_char(tport, buf[c], TTY_NORMAL);
556 }
557 }
558 if (!drop)
559 tty_flip_buffer_push(tport);
560 }
561 #else
handle_rx_console(struct uart_port * uport,u32 bytes,bool drop)562 static void handle_rx_console(struct uart_port *uport, u32 bytes, bool drop)
563 {
564
565 }
566 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
567
handle_rx_uart(struct uart_port * uport,u32 bytes,bool drop)568 static void handle_rx_uart(struct uart_port *uport, u32 bytes, bool drop)
569 {
570 struct qcom_geni_serial_port *port = to_dev_port(uport);
571 struct tty_port *tport = &uport->state->port;
572 int ret;
573
574 ret = tty_insert_flip_string(tport, port->rx_buf, bytes);
575 if (ret != bytes) {
576 dev_err(uport->dev, "%s:Unable to push data ret %d_bytes %d\n",
577 __func__, ret, bytes);
578 WARN_ON_ONCE(1);
579 }
580 uport->icount.rx += ret;
581 tty_flip_buffer_push(tport);
582 }
583
qcom_geni_serial_tx_empty(struct uart_port * uport)584 static unsigned int qcom_geni_serial_tx_empty(struct uart_port *uport)
585 {
586 return !readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
587 }
588
qcom_geni_serial_stop_tx_dma(struct uart_port * uport)589 static void qcom_geni_serial_stop_tx_dma(struct uart_port *uport)
590 {
591 struct qcom_geni_serial_port *port = to_dev_port(uport);
592 bool done;
593
594 if (!qcom_geni_serial_main_active(uport))
595 return;
596
597 if (port->tx_dma_addr) {
598 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr,
599 port->tx_remaining);
600 port->tx_dma_addr = 0;
601 port->tx_remaining = 0;
602 }
603
604 geni_se_cancel_m_cmd(&port->se);
605
606 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
607 M_CMD_CANCEL_EN, true);
608 if (!done) {
609 geni_se_abort_m_cmd(&port->se);
610 done = qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
611 M_CMD_ABORT_EN, true);
612 if (!done)
613 dev_err_ratelimited(uport->dev, "M_CMD_ABORT_EN not set");
614 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
615 }
616
617 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
618 }
619
qcom_geni_serial_start_tx_dma(struct uart_port * uport)620 static void qcom_geni_serial_start_tx_dma(struct uart_port *uport)
621 {
622 struct qcom_geni_serial_port *port = to_dev_port(uport);
623 struct tty_port *tport = &uport->state->port;
624 unsigned int xmit_size;
625 u8 *tail;
626 int ret;
627
628 if (port->tx_dma_addr)
629 return;
630
631 if (kfifo_is_empty(&tport->xmit_fifo))
632 return;
633
634 xmit_size = kfifo_out_linear_ptr(&tport->xmit_fifo, &tail,
635 UART_XMIT_SIZE);
636
637 qcom_geni_serial_setup_tx(uport, xmit_size);
638
639 ret = geni_se_tx_dma_prep(&port->se, tail, xmit_size,
640 &port->tx_dma_addr);
641 if (ret) {
642 dev_err(uport->dev, "unable to start TX SE DMA: %d\n", ret);
643 qcom_geni_serial_stop_tx_dma(uport);
644 return;
645 }
646
647 port->tx_remaining = xmit_size;
648 }
649
qcom_geni_serial_start_tx_fifo(struct uart_port * uport)650 static void qcom_geni_serial_start_tx_fifo(struct uart_port *uport)
651 {
652 unsigned char c;
653 u32 irq_en;
654
655 /*
656 * Start a new transfer in case the previous command was cancelled and
657 * left data in the FIFO which may prevent the watermark interrupt
658 * from triggering. Note that the stale data is discarded.
659 */
660 if (!qcom_geni_serial_main_active(uport) &&
661 !qcom_geni_serial_tx_empty(uport)) {
662 if (uart_fifo_out(uport, &c, 1) == 1) {
663 writel(M_CMD_DONE_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
664 qcom_geni_serial_setup_tx(uport, 1);
665 writel(c, uport->membase + SE_GENI_TX_FIFOn);
666 }
667 }
668
669 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
670 irq_en |= M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN;
671 writel(DEF_TX_WM, uport->membase + SE_GENI_TX_WATERMARK_REG);
672 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
673 }
674
qcom_geni_serial_stop_tx_fifo(struct uart_port * uport)675 static void qcom_geni_serial_stop_tx_fifo(struct uart_port *uport)
676 {
677 u32 irq_en;
678
679 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
680 irq_en &= ~(M_CMD_DONE_EN | M_TX_FIFO_WATERMARK_EN);
681 writel(0, uport->membase + SE_GENI_TX_WATERMARK_REG);
682 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
683 }
684
qcom_geni_serial_cancel_tx_cmd(struct uart_port * uport)685 static void qcom_geni_serial_cancel_tx_cmd(struct uart_port *uport)
686 {
687 struct qcom_geni_serial_port *port = to_dev_port(uport);
688
689 if (!qcom_geni_serial_main_active(uport))
690 return;
691
692 geni_se_cancel_m_cmd(&port->se);
693 if (!qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
694 M_CMD_CANCEL_EN, true)) {
695 geni_se_abort_m_cmd(&port->se);
696 qcom_geni_serial_poll_bit(uport, SE_GENI_M_IRQ_STATUS,
697 M_CMD_ABORT_EN, true);
698 writel(M_CMD_ABORT_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
699 }
700 writel(M_CMD_CANCEL_EN, uport->membase + SE_GENI_M_IRQ_CLEAR);
701
702 port->tx_remaining = 0;
703 }
704
qcom_geni_serial_handle_rx_fifo(struct uart_port * uport,bool drop)705 static void qcom_geni_serial_handle_rx_fifo(struct uart_port *uport, bool drop)
706 {
707 u32 status;
708 u32 word_cnt;
709 u32 last_word_byte_cnt;
710 u32 last_word_partial;
711 u32 total_bytes;
712
713 status = readl(uport->membase + SE_GENI_RX_FIFO_STATUS);
714 word_cnt = status & RX_FIFO_WC_MSK;
715 last_word_partial = status & RX_LAST;
716 last_word_byte_cnt = (status & RX_LAST_BYTE_VALID_MSK) >>
717 RX_LAST_BYTE_VALID_SHFT;
718
719 if (!word_cnt)
720 return;
721 total_bytes = BYTES_PER_FIFO_WORD * (word_cnt - 1);
722 if (last_word_partial && last_word_byte_cnt)
723 total_bytes += last_word_byte_cnt;
724 else
725 total_bytes += BYTES_PER_FIFO_WORD;
726 handle_rx_console(uport, total_bytes, drop);
727 }
728
qcom_geni_serial_stop_rx_fifo(struct uart_port * uport)729 static void qcom_geni_serial_stop_rx_fifo(struct uart_port *uport)
730 {
731 u32 irq_en;
732 struct qcom_geni_serial_port *port = to_dev_port(uport);
733 u32 s_irq_status;
734
735 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
736 irq_en &= ~(S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN);
737 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
738
739 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
740 irq_en &= ~(M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN);
741 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
742
743 if (!qcom_geni_serial_secondary_active(uport))
744 return;
745
746 geni_se_cancel_s_cmd(&port->se);
747 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
748 S_CMD_CANCEL_EN, true);
749 /*
750 * If timeout occurs secondary engine remains active
751 * and Abort sequence is executed.
752 */
753 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
754 /* Flush the Rx buffer */
755 if (s_irq_status & S_RX_FIFO_LAST_EN)
756 qcom_geni_serial_handle_rx_fifo(uport, true);
757 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
758
759 if (qcom_geni_serial_secondary_active(uport))
760 qcom_geni_serial_abort_rx(uport);
761 }
762
qcom_geni_serial_start_rx_fifo(struct uart_port * uport)763 static void qcom_geni_serial_start_rx_fifo(struct uart_port *uport)
764 {
765 u32 irq_en;
766 struct qcom_geni_serial_port *port = to_dev_port(uport);
767
768 if (qcom_geni_serial_secondary_active(uport))
769 qcom_geni_serial_stop_rx_fifo(uport);
770
771 geni_se_setup_s_cmd(&port->se, UART_START_READ, 0);
772
773 irq_en = readl(uport->membase + SE_GENI_S_IRQ_EN);
774 irq_en |= S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN;
775 writel(irq_en, uport->membase + SE_GENI_S_IRQ_EN);
776
777 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
778 irq_en |= M_RX_FIFO_WATERMARK_EN | M_RX_FIFO_LAST_EN;
779 writel(irq_en, uport->membase + SE_GENI_M_IRQ_EN);
780 }
781
qcom_geni_serial_stop_rx_dma(struct uart_port * uport)782 static void qcom_geni_serial_stop_rx_dma(struct uart_port *uport)
783 {
784 struct qcom_geni_serial_port *port = to_dev_port(uport);
785
786 if (!qcom_geni_serial_secondary_active(uport))
787 return;
788
789 geni_se_cancel_s_cmd(&port->se);
790 qcom_geni_serial_poll_bit(uport, SE_GENI_S_IRQ_STATUS,
791 S_CMD_CANCEL_EN, true);
792
793 if (qcom_geni_serial_secondary_active(uport))
794 qcom_geni_serial_abort_rx(uport);
795
796 if (port->rx_dma_addr) {
797 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr,
798 DMA_RX_BUF_SIZE);
799 port->rx_dma_addr = 0;
800 }
801 }
802
qcom_geni_serial_start_rx_dma(struct uart_port * uport)803 static void qcom_geni_serial_start_rx_dma(struct uart_port *uport)
804 {
805 struct qcom_geni_serial_port *port = to_dev_port(uport);
806 int ret;
807
808 if (qcom_geni_serial_secondary_active(uport))
809 qcom_geni_serial_stop_rx_dma(uport);
810
811 geni_se_setup_s_cmd(&port->se, UART_START_READ, UART_PARAM_RFR_OPEN);
812
813 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf,
814 DMA_RX_BUF_SIZE,
815 &port->rx_dma_addr);
816 if (ret) {
817 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret);
818 qcom_geni_serial_stop_rx_dma(uport);
819 }
820 }
821
qcom_geni_serial_handle_rx_dma(struct uart_port * uport,bool drop)822 static void qcom_geni_serial_handle_rx_dma(struct uart_port *uport, bool drop)
823 {
824 struct qcom_geni_serial_port *port = to_dev_port(uport);
825 u32 rx_in;
826 int ret;
827
828 if (!qcom_geni_serial_secondary_active(uport))
829 return;
830
831 if (!port->rx_dma_addr)
832 return;
833
834 geni_se_rx_dma_unprep(&port->se, port->rx_dma_addr, DMA_RX_BUF_SIZE);
835 port->rx_dma_addr = 0;
836
837 rx_in = readl(uport->membase + SE_DMA_RX_LEN_IN);
838 if (!rx_in) {
839 dev_warn(uport->dev, "serial engine reports 0 RX bytes in!\n");
840 return;
841 }
842
843 if (!drop)
844 handle_rx_uart(uport, rx_in, drop);
845
846 ret = geni_se_rx_dma_prep(&port->se, port->rx_buf,
847 DMA_RX_BUF_SIZE,
848 &port->rx_dma_addr);
849 if (ret) {
850 dev_err(uport->dev, "unable to start RX SE DMA: %d\n", ret);
851 qcom_geni_serial_stop_rx_dma(uport);
852 }
853 }
854
qcom_geni_serial_start_rx(struct uart_port * uport)855 static void qcom_geni_serial_start_rx(struct uart_port *uport)
856 {
857 uport->ops->start_rx(uport);
858 }
859
qcom_geni_serial_stop_rx(struct uart_port * uport)860 static void qcom_geni_serial_stop_rx(struct uart_port *uport)
861 {
862 uport->ops->stop_rx(uport);
863 }
864
qcom_geni_serial_stop_tx(struct uart_port * uport)865 static void qcom_geni_serial_stop_tx(struct uart_port *uport)
866 {
867 uport->ops->stop_tx(uport);
868 }
869
qcom_geni_serial_send_chunk_fifo(struct uart_port * uport,unsigned int chunk)870 static void qcom_geni_serial_send_chunk_fifo(struct uart_port *uport,
871 unsigned int chunk)
872 {
873 struct qcom_geni_serial_port *port = to_dev_port(uport);
874 unsigned int tx_bytes, remaining = chunk;
875 u8 buf[BYTES_PER_FIFO_WORD];
876
877 while (remaining) {
878 memset(buf, 0, sizeof(buf));
879 tx_bytes = min(remaining, BYTES_PER_FIFO_WORD);
880
881 uart_fifo_out(uport, buf, tx_bytes);
882
883 iowrite32_rep(uport->membase + SE_GENI_TX_FIFOn, buf, 1);
884
885 remaining -= tx_bytes;
886 port->tx_remaining -= tx_bytes;
887 }
888 }
889
qcom_geni_serial_handle_tx_fifo(struct uart_port * uport,bool done,bool active)890 static void qcom_geni_serial_handle_tx_fifo(struct uart_port *uport,
891 bool done, bool active)
892 {
893 struct qcom_geni_serial_port *port = to_dev_port(uport);
894 struct tty_port *tport = &uport->state->port;
895 size_t avail;
896 size_t pending;
897 u32 status;
898 u32 irq_en;
899 unsigned int chunk;
900
901 status = readl(uport->membase + SE_GENI_TX_FIFO_STATUS);
902
903 /* Complete the current tx command before taking newly added data */
904 if (active)
905 pending = port->tx_remaining;
906 else
907 pending = kfifo_len(&tport->xmit_fifo);
908
909 /* All data has been transmitted or command has been cancelled */
910 if (!pending && done) {
911 qcom_geni_serial_stop_tx_fifo(uport);
912 goto out_write_wakeup;
913 }
914
915 if (active)
916 avail = port->tx_fifo_depth - (status & TX_FIFO_WC);
917 else
918 avail = port->tx_fifo_depth;
919
920 avail *= BYTES_PER_FIFO_WORD;
921
922 chunk = min(avail, pending);
923 if (!chunk)
924 goto out_write_wakeup;
925
926 if (!port->tx_remaining) {
927 qcom_geni_serial_setup_tx(uport, pending);
928 port->tx_remaining = pending;
929
930 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
931 if (!(irq_en & M_TX_FIFO_WATERMARK_EN))
932 writel(irq_en | M_TX_FIFO_WATERMARK_EN,
933 uport->membase + SE_GENI_M_IRQ_EN);
934 }
935
936 qcom_geni_serial_send_chunk_fifo(uport, chunk);
937
938 /*
939 * The tx fifo watermark is level triggered and latched. Though we had
940 * cleared it in qcom_geni_serial_isr it will have already reasserted
941 * so we must clear it again here after our writes.
942 */
943 writel(M_TX_FIFO_WATERMARK_EN,
944 uport->membase + SE_GENI_M_IRQ_CLEAR);
945
946 out_write_wakeup:
947 if (!port->tx_remaining) {
948 irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
949 if (irq_en & M_TX_FIFO_WATERMARK_EN)
950 writel(irq_en & ~M_TX_FIFO_WATERMARK_EN,
951 uport->membase + SE_GENI_M_IRQ_EN);
952 }
953
954 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
955 uart_write_wakeup(uport);
956 }
957
qcom_geni_serial_handle_tx_dma(struct uart_port * uport)958 static void qcom_geni_serial_handle_tx_dma(struct uart_port *uport)
959 {
960 struct qcom_geni_serial_port *port = to_dev_port(uport);
961 struct tty_port *tport = &uport->state->port;
962
963 uart_xmit_advance(uport, port->tx_remaining);
964 geni_se_tx_dma_unprep(&port->se, port->tx_dma_addr, port->tx_remaining);
965 port->tx_dma_addr = 0;
966 port->tx_remaining = 0;
967
968 if (!kfifo_is_empty(&tport->xmit_fifo))
969 qcom_geni_serial_start_tx_dma(uport);
970
971 if (kfifo_len(&tport->xmit_fifo) < WAKEUP_CHARS)
972 uart_write_wakeup(uport);
973 }
974
qcom_geni_serial_isr(int isr,void * dev)975 static irqreturn_t qcom_geni_serial_isr(int isr, void *dev)
976 {
977 u32 m_irq_en;
978 u32 m_irq_status;
979 u32 s_irq_status;
980 u32 geni_status;
981 u32 dma;
982 u32 dma_tx_status;
983 u32 dma_rx_status;
984 struct uart_port *uport = dev;
985 bool drop_rx = false;
986 struct tty_port *tport = &uport->state->port;
987 struct qcom_geni_serial_port *port = to_dev_port(uport);
988
989 if (uport->suspended)
990 return IRQ_NONE;
991
992 uart_port_lock(uport);
993
994 m_irq_status = readl(uport->membase + SE_GENI_M_IRQ_STATUS);
995 s_irq_status = readl(uport->membase + SE_GENI_S_IRQ_STATUS);
996 dma_tx_status = readl(uport->membase + SE_DMA_TX_IRQ_STAT);
997 dma_rx_status = readl(uport->membase + SE_DMA_RX_IRQ_STAT);
998 geni_status = readl(uport->membase + SE_GENI_STATUS);
999 dma = readl(uport->membase + SE_GENI_DMA_MODE_EN);
1000 m_irq_en = readl(uport->membase + SE_GENI_M_IRQ_EN);
1001 writel(m_irq_status, uport->membase + SE_GENI_M_IRQ_CLEAR);
1002 writel(s_irq_status, uport->membase + SE_GENI_S_IRQ_CLEAR);
1003 writel(dma_tx_status, uport->membase + SE_DMA_TX_IRQ_CLR);
1004 writel(dma_rx_status, uport->membase + SE_DMA_RX_IRQ_CLR);
1005
1006 if (WARN_ON(m_irq_status & M_ILLEGAL_CMD_EN))
1007 goto out_unlock;
1008
1009 if (s_irq_status & S_RX_FIFO_WR_ERR_EN) {
1010 uport->icount.overrun++;
1011 tty_insert_flip_char(tport, 0, TTY_OVERRUN);
1012 }
1013
1014 if (s_irq_status & (S_GP_IRQ_0_EN | S_GP_IRQ_1_EN)) {
1015 if (s_irq_status & S_GP_IRQ_0_EN)
1016 uport->icount.parity++;
1017 drop_rx = true;
1018 } else if (s_irq_status & (S_GP_IRQ_2_EN | S_GP_IRQ_3_EN)) {
1019 uport->icount.brk++;
1020 port->brk = true;
1021 }
1022
1023 if (dma) {
1024 if (dma_tx_status & TX_DMA_DONE)
1025 qcom_geni_serial_handle_tx_dma(uport);
1026
1027 if (dma_rx_status) {
1028 if (dma_rx_status & RX_RESET_DONE)
1029 goto out_unlock;
1030
1031 if (dma_rx_status & RX_DMA_PARITY_ERR) {
1032 uport->icount.parity++;
1033 drop_rx = true;
1034 }
1035
1036 if (dma_rx_status & RX_DMA_BREAK)
1037 uport->icount.brk++;
1038
1039 if (dma_rx_status & (RX_DMA_DONE | RX_EOT))
1040 qcom_geni_serial_handle_rx_dma(uport, drop_rx);
1041 }
1042 } else {
1043 if (m_irq_status & m_irq_en &
1044 (M_TX_FIFO_WATERMARK_EN | M_CMD_DONE_EN))
1045 qcom_geni_serial_handle_tx_fifo(uport,
1046 m_irq_status & M_CMD_DONE_EN,
1047 geni_status & M_GENI_CMD_ACTIVE);
1048
1049 if (s_irq_status & (S_RX_FIFO_WATERMARK_EN | S_RX_FIFO_LAST_EN))
1050 qcom_geni_serial_handle_rx_fifo(uport, drop_rx);
1051 }
1052
1053 out_unlock:
1054 uart_unlock_and_check_sysrq(uport);
1055
1056 return IRQ_HANDLED;
1057 }
1058
setup_fifos(struct qcom_geni_serial_port * port)1059 static int setup_fifos(struct qcom_geni_serial_port *port)
1060 {
1061 struct uart_port *uport;
1062 u32 old_rx_fifo_depth = port->rx_fifo_depth;
1063
1064 uport = &port->uport;
1065 port->tx_fifo_depth = geni_se_get_tx_fifo_depth(&port->se);
1066 port->tx_fifo_width = geni_se_get_tx_fifo_width(&port->se);
1067 port->rx_fifo_depth = geni_se_get_rx_fifo_depth(&port->se);
1068 uport->fifosize =
1069 (port->tx_fifo_depth * port->tx_fifo_width) / BITS_PER_BYTE;
1070
1071 if (port->rx_buf && (old_rx_fifo_depth != port->rx_fifo_depth) && port->rx_fifo_depth) {
1072 /*
1073 * Use krealloc rather than krealloc_array because rx_buf is
1074 * accessed as 1 byte entries as well as 4 byte entries so it's
1075 * not necessarily an array.
1076 */
1077 port->rx_buf = devm_krealloc(uport->dev, port->rx_buf,
1078 port->rx_fifo_depth * sizeof(u32),
1079 GFP_KERNEL);
1080 if (!port->rx_buf)
1081 return -ENOMEM;
1082 }
1083
1084 return 0;
1085 }
1086
1087
qcom_geni_serial_shutdown(struct uart_port * uport)1088 static void qcom_geni_serial_shutdown(struct uart_port *uport)
1089 {
1090 disable_irq(uport->irq);
1091
1092 qcom_geni_serial_stop_tx(uport);
1093 qcom_geni_serial_stop_rx(uport);
1094
1095 qcom_geni_serial_cancel_tx_cmd(uport);
1096 }
1097
qcom_geni_serial_flush_buffer(struct uart_port * uport)1098 static void qcom_geni_serial_flush_buffer(struct uart_port *uport)
1099 {
1100 qcom_geni_serial_cancel_tx_cmd(uport);
1101 }
1102
qcom_geni_serial_port_setup(struct uart_port * uport)1103 static int qcom_geni_serial_port_setup(struct uart_port *uport)
1104 {
1105 struct qcom_geni_serial_port *port = to_dev_port(uport);
1106 u32 rxstale = DEFAULT_BITS_PER_CHAR * STALE_TIMEOUT;
1107 u32 proto;
1108 u32 pin_swap;
1109 int ret;
1110
1111 proto = geni_se_read_proto(&port->se);
1112 if (proto != GENI_SE_UART) {
1113 dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto);
1114 return -ENXIO;
1115 }
1116
1117 qcom_geni_serial_stop_rx(uport);
1118
1119 ret = setup_fifos(port);
1120 if (ret)
1121 return ret;
1122
1123 writel(rxstale, uport->membase + SE_UART_RX_STALE_CNT);
1124
1125 pin_swap = readl(uport->membase + SE_UART_IO_MACRO_CTRL);
1126 if (port->rx_tx_swap) {
1127 pin_swap &= ~DEFAULT_IO_MACRO_IO2_IO3_MASK;
1128 pin_swap |= IO_MACRO_IO2_IO3_SWAP;
1129 }
1130 if (port->cts_rts_swap) {
1131 pin_swap &= ~DEFAULT_IO_MACRO_IO0_IO1_MASK;
1132 pin_swap |= IO_MACRO_IO0_SEL;
1133 }
1134 /* Configure this register if RX-TX, CTS-RTS pins are swapped */
1135 if (port->rx_tx_swap || port->cts_rts_swap)
1136 writel(pin_swap, uport->membase + SE_UART_IO_MACRO_CTRL);
1137
1138 /*
1139 * Make an unconditional cancel on the main sequencer to reset
1140 * it else we could end up in data loss scenarios.
1141 */
1142 if (uart_console(uport))
1143 qcom_geni_serial_poll_tx_done(uport);
1144 geni_se_config_packing(&port->se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1145 false, true, true);
1146 geni_se_init(&port->se, UART_RX_WM, port->rx_fifo_depth - 2);
1147 geni_se_select_mode(&port->se, port->dev_data->mode);
1148 qcom_geni_serial_start_rx(uport);
1149 port->setup = true;
1150
1151 return 0;
1152 }
1153
qcom_geni_serial_startup(struct uart_port * uport)1154 static int qcom_geni_serial_startup(struct uart_port *uport)
1155 {
1156 int ret;
1157 struct qcom_geni_serial_port *port = to_dev_port(uport);
1158
1159 if (!port->setup) {
1160 ret = qcom_geni_serial_port_setup(uport);
1161 if (ret)
1162 return ret;
1163 }
1164 enable_irq(uport->irq);
1165
1166 return 0;
1167 }
1168
find_clk_rate_in_tol(struct clk * clk,unsigned int desired_clk,unsigned int * clk_div,unsigned int percent_tol)1169 static unsigned long find_clk_rate_in_tol(struct clk *clk, unsigned int desired_clk,
1170 unsigned int *clk_div, unsigned int percent_tol)
1171 {
1172 unsigned long freq;
1173 unsigned long div, maxdiv;
1174 u64 mult;
1175 unsigned long offset, abs_tol, achieved;
1176
1177 abs_tol = div_u64((u64)desired_clk * percent_tol, 100);
1178 maxdiv = CLK_DIV_MSK >> CLK_DIV_SHFT;
1179 div = 1;
1180 while (div <= maxdiv) {
1181 mult = (u64)div * desired_clk;
1182 if (mult != (unsigned long)mult)
1183 break;
1184
1185 offset = div * abs_tol;
1186 freq = clk_round_rate(clk, mult - offset);
1187
1188 /* Can only get lower if we're done */
1189 if (freq < mult - offset)
1190 break;
1191
1192 /*
1193 * Re-calculate div in case rounding skipped rates but we
1194 * ended up at a good one, then check for a match.
1195 */
1196 div = DIV_ROUND_CLOSEST(freq, desired_clk);
1197 achieved = DIV_ROUND_CLOSEST(freq, div);
1198 if (achieved <= desired_clk + abs_tol &&
1199 achieved >= desired_clk - abs_tol) {
1200 *clk_div = div;
1201 return freq;
1202 }
1203
1204 div = DIV_ROUND_UP(freq, desired_clk);
1205 }
1206
1207 return 0;
1208 }
1209
get_clk_div_rate(struct clk * clk,unsigned int baud,unsigned int sampling_rate,unsigned int * clk_div)1210 static unsigned long get_clk_div_rate(struct clk *clk, unsigned int baud,
1211 unsigned int sampling_rate, unsigned int *clk_div)
1212 {
1213 unsigned long ser_clk;
1214 unsigned long desired_clk;
1215
1216 desired_clk = baud * sampling_rate;
1217 if (!desired_clk)
1218 return 0;
1219
1220 /*
1221 * try to find a clock rate within 2% tolerance, then within 5%
1222 */
1223 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 2);
1224 if (!ser_clk)
1225 ser_clk = find_clk_rate_in_tol(clk, desired_clk, clk_div, 5);
1226
1227 return ser_clk;
1228 }
1229
qcom_geni_serial_set_termios(struct uart_port * uport,struct ktermios * termios,const struct ktermios * old)1230 static void qcom_geni_serial_set_termios(struct uart_port *uport,
1231 struct ktermios *termios,
1232 const struct ktermios *old)
1233 {
1234 unsigned int baud;
1235 u32 bits_per_char;
1236 u32 tx_trans_cfg;
1237 u32 tx_parity_cfg;
1238 u32 rx_trans_cfg;
1239 u32 rx_parity_cfg;
1240 u32 stop_bit_len;
1241 unsigned int clk_div;
1242 u32 ser_clk_cfg;
1243 struct qcom_geni_serial_port *port = to_dev_port(uport);
1244 unsigned long clk_rate;
1245 u32 ver, sampling_rate;
1246 unsigned int avg_bw_core;
1247
1248 qcom_geni_serial_stop_rx(uport);
1249 /* baud rate */
1250 baud = uart_get_baud_rate(uport, termios, old, 300, 4000000);
1251 port->baud = baud;
1252
1253 sampling_rate = UART_OVERSAMPLING;
1254 /* Sampling rate is halved for IP versions >= 2.5 */
1255 ver = geni_se_get_qup_hw_version(&port->se);
1256 if (ver >= QUP_SE_VERSION_2_5)
1257 sampling_rate /= 2;
1258
1259 clk_rate = get_clk_div_rate(port->se.clk, baud,
1260 sampling_rate, &clk_div);
1261 if (!clk_rate) {
1262 dev_err(port->se.dev,
1263 "Couldn't find suitable clock rate for %u\n",
1264 baud * sampling_rate);
1265 goto out_restart_rx;
1266 }
1267
1268 dev_dbg(port->se.dev, "desired_rate = %u, clk_rate = %lu, clk_div = %u\n",
1269 baud * sampling_rate, clk_rate, clk_div);
1270
1271 uport->uartclk = clk_rate;
1272 port->clk_rate = clk_rate;
1273 dev_pm_opp_set_rate(uport->dev, clk_rate);
1274 ser_clk_cfg = SER_CLK_EN;
1275 ser_clk_cfg |= clk_div << CLK_DIV_SHFT;
1276
1277 /*
1278 * Bump up BW vote on CPU and CORE path as driver supports FIFO mode
1279 * only.
1280 */
1281 avg_bw_core = (baud > 115200) ? Bps_to_icc(CORE_2X_50_MHZ)
1282 : GENI_DEFAULT_BW;
1283 port->se.icc_paths[GENI_TO_CORE].avg_bw = avg_bw_core;
1284 port->se.icc_paths[CPU_TO_GENI].avg_bw = Bps_to_icc(baud);
1285 geni_icc_set_bw(&port->se);
1286
1287 /* parity */
1288 tx_trans_cfg = readl(uport->membase + SE_UART_TX_TRANS_CFG);
1289 tx_parity_cfg = readl(uport->membase + SE_UART_TX_PARITY_CFG);
1290 rx_trans_cfg = readl(uport->membase + SE_UART_RX_TRANS_CFG);
1291 rx_parity_cfg = readl(uport->membase + SE_UART_RX_PARITY_CFG);
1292 if (termios->c_cflag & PARENB) {
1293 tx_trans_cfg |= UART_TX_PAR_EN;
1294 rx_trans_cfg |= UART_RX_PAR_EN;
1295 tx_parity_cfg |= PAR_CALC_EN;
1296 rx_parity_cfg |= PAR_CALC_EN;
1297 if (termios->c_cflag & PARODD) {
1298 tx_parity_cfg |= PAR_ODD;
1299 rx_parity_cfg |= PAR_ODD;
1300 } else if (termios->c_cflag & CMSPAR) {
1301 tx_parity_cfg |= PAR_SPACE;
1302 rx_parity_cfg |= PAR_SPACE;
1303 } else {
1304 tx_parity_cfg |= PAR_EVEN;
1305 rx_parity_cfg |= PAR_EVEN;
1306 }
1307 } else {
1308 tx_trans_cfg &= ~UART_TX_PAR_EN;
1309 rx_trans_cfg &= ~UART_RX_PAR_EN;
1310 tx_parity_cfg &= ~PAR_CALC_EN;
1311 rx_parity_cfg &= ~PAR_CALC_EN;
1312 }
1313
1314 /* bits per char */
1315 bits_per_char = tty_get_char_size(termios->c_cflag);
1316
1317 /* stop bits */
1318 if (termios->c_cflag & CSTOPB)
1319 stop_bit_len = TX_STOP_BIT_LEN_2;
1320 else
1321 stop_bit_len = TX_STOP_BIT_LEN_1;
1322
1323 /* flow control, clear the CTS_MASK bit if using flow control. */
1324 if (termios->c_cflag & CRTSCTS)
1325 tx_trans_cfg &= ~UART_CTS_MASK;
1326 else
1327 tx_trans_cfg |= UART_CTS_MASK;
1328
1329 if (baud)
1330 uart_update_timeout(uport, termios->c_cflag, baud);
1331
1332 if (!uart_console(uport))
1333 writel(port->loopback,
1334 uport->membase + SE_UART_LOOPBACK_CFG);
1335 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1336 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1337 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1338 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1339 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1340 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1341 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1342 writel(ser_clk_cfg, uport->membase + GENI_SER_M_CLK_CFG);
1343 writel(ser_clk_cfg, uport->membase + GENI_SER_S_CLK_CFG);
1344 out_restart_rx:
1345 qcom_geni_serial_start_rx(uport);
1346 }
1347
1348 #ifdef CONFIG_SERIAL_QCOM_GENI_CONSOLE
qcom_geni_console_setup(struct console * co,char * options)1349 static int qcom_geni_console_setup(struct console *co, char *options)
1350 {
1351 struct uart_port *uport;
1352 struct qcom_geni_serial_port *port;
1353 int baud = 115200;
1354 int bits = 8;
1355 int parity = 'n';
1356 int flow = 'n';
1357 int ret;
1358
1359 if (co->index >= GENI_UART_CONS_PORTS || co->index < 0)
1360 return -ENXIO;
1361
1362 port = get_port_from_line(co->index, true);
1363 if (IS_ERR(port)) {
1364 pr_err("Invalid line %d\n", co->index);
1365 return PTR_ERR(port);
1366 }
1367
1368 uport = &port->uport;
1369
1370 if (unlikely(!uport->membase))
1371 return -ENXIO;
1372
1373 if (!port->setup) {
1374 ret = qcom_geni_serial_port_setup(uport);
1375 if (ret)
1376 return ret;
1377 }
1378
1379 if (options)
1380 uart_parse_options(options, &baud, &parity, &bits, &flow);
1381
1382 return uart_set_options(uport, co, baud, parity, bits, flow);
1383 }
1384
qcom_geni_serial_earlycon_write(struct console * con,const char * s,unsigned int n)1385 static void qcom_geni_serial_earlycon_write(struct console *con,
1386 const char *s, unsigned int n)
1387 {
1388 struct earlycon_device *dev = con->data;
1389
1390 __qcom_geni_serial_console_write(&dev->port, s, n);
1391 }
1392
1393 #ifdef CONFIG_CONSOLE_POLL
qcom_geni_serial_earlycon_read(struct console * con,char * s,unsigned int n)1394 static int qcom_geni_serial_earlycon_read(struct console *con,
1395 char *s, unsigned int n)
1396 {
1397 struct earlycon_device *dev = con->data;
1398 struct uart_port *uport = &dev->port;
1399 int num_read = 0;
1400 int ch;
1401
1402 while (num_read < n) {
1403 ch = qcom_geni_serial_get_char(uport);
1404 if (ch == NO_POLL_CHAR)
1405 break;
1406 s[num_read++] = ch;
1407 }
1408
1409 return num_read;
1410 }
1411
qcom_geni_serial_enable_early_read(struct geni_se * se,struct console * con)1412 static void __init qcom_geni_serial_enable_early_read(struct geni_se *se,
1413 struct console *con)
1414 {
1415 geni_se_setup_s_cmd(se, UART_START_READ, 0);
1416 con->read = qcom_geni_serial_earlycon_read;
1417 }
1418 #else
qcom_geni_serial_enable_early_read(struct geni_se * se,struct console * con)1419 static inline void qcom_geni_serial_enable_early_read(struct geni_se *se,
1420 struct console *con) { }
1421 #endif
1422
1423 static struct qcom_geni_private_data earlycon_private_data;
1424
qcom_geni_serial_earlycon_setup(struct earlycon_device * dev,const char * opt)1425 static int __init qcom_geni_serial_earlycon_setup(struct earlycon_device *dev,
1426 const char *opt)
1427 {
1428 struct uart_port *uport = &dev->port;
1429 u32 tx_trans_cfg;
1430 u32 tx_parity_cfg = 0; /* Disable Tx Parity */
1431 u32 rx_trans_cfg = 0;
1432 u32 rx_parity_cfg = 0; /* Disable Rx Parity */
1433 u32 stop_bit_len = 0; /* Default stop bit length - 1 bit */
1434 u32 bits_per_char;
1435 struct geni_se se;
1436
1437 if (!uport->membase)
1438 return -EINVAL;
1439
1440 uport->private_data = &earlycon_private_data;
1441
1442 memset(&se, 0, sizeof(se));
1443 se.base = uport->membase;
1444 if (geni_se_read_proto(&se) != GENI_SE_UART)
1445 return -ENXIO;
1446 /*
1447 * Ignore Flow control.
1448 * n = 8.
1449 */
1450 tx_trans_cfg = UART_CTS_MASK;
1451 bits_per_char = BITS_PER_BYTE;
1452
1453 /*
1454 * Make an unconditional cancel on the main sequencer to reset
1455 * it else we could end up in data loss scenarios.
1456 */
1457 qcom_geni_serial_poll_tx_done(uport);
1458 qcom_geni_serial_abort_rx(uport);
1459 geni_se_config_packing(&se, BITS_PER_BYTE, BYTES_PER_FIFO_WORD,
1460 false, true, true);
1461 geni_se_init(&se, DEF_FIFO_DEPTH_WORDS / 2, DEF_FIFO_DEPTH_WORDS - 2);
1462 geni_se_select_mode(&se, GENI_SE_FIFO);
1463
1464 writel(tx_trans_cfg, uport->membase + SE_UART_TX_TRANS_CFG);
1465 writel(tx_parity_cfg, uport->membase + SE_UART_TX_PARITY_CFG);
1466 writel(rx_trans_cfg, uport->membase + SE_UART_RX_TRANS_CFG);
1467 writel(rx_parity_cfg, uport->membase + SE_UART_RX_PARITY_CFG);
1468 writel(bits_per_char, uport->membase + SE_UART_TX_WORD_LEN);
1469 writel(bits_per_char, uport->membase + SE_UART_RX_WORD_LEN);
1470 writel(stop_bit_len, uport->membase + SE_UART_TX_STOP_BIT_LEN);
1471
1472 dev->con->write = qcom_geni_serial_earlycon_write;
1473 dev->con->setup = NULL;
1474 qcom_geni_serial_enable_early_read(&se, dev->con);
1475
1476 return 0;
1477 }
1478 OF_EARLYCON_DECLARE(qcom_geni, "qcom,geni-debug-uart",
1479 qcom_geni_serial_earlycon_setup);
1480
console_register(struct uart_driver * drv)1481 static int __init console_register(struct uart_driver *drv)
1482 {
1483 return uart_register_driver(drv);
1484 }
1485
console_unregister(struct uart_driver * drv)1486 static void console_unregister(struct uart_driver *drv)
1487 {
1488 uart_unregister_driver(drv);
1489 }
1490
1491 static struct console cons_ops = {
1492 .name = "ttyMSM",
1493 .write = qcom_geni_serial_console_write,
1494 .device = uart_console_device,
1495 .setup = qcom_geni_console_setup,
1496 .flags = CON_PRINTBUFFER,
1497 .index = -1,
1498 .data = &qcom_geni_console_driver,
1499 };
1500
1501 static struct uart_driver qcom_geni_console_driver = {
1502 .owner = THIS_MODULE,
1503 .driver_name = "qcom_geni_console",
1504 .dev_name = "ttyMSM",
1505 .nr = GENI_UART_CONS_PORTS,
1506 .cons = &cons_ops,
1507 };
1508 #else
console_register(struct uart_driver * drv)1509 static int console_register(struct uart_driver *drv)
1510 {
1511 return 0;
1512 }
1513
console_unregister(struct uart_driver * drv)1514 static void console_unregister(struct uart_driver *drv)
1515 {
1516 }
1517 #endif /* CONFIG_SERIAL_QCOM_GENI_CONSOLE */
1518
1519 static struct uart_driver qcom_geni_uart_driver = {
1520 .owner = THIS_MODULE,
1521 .driver_name = "qcom_geni_uart",
1522 .dev_name = "ttyHS",
1523 .nr = GENI_UART_PORTS,
1524 };
1525
qcom_geni_serial_pm(struct uart_port * uport,unsigned int new_state,unsigned int old_state)1526 static void qcom_geni_serial_pm(struct uart_port *uport,
1527 unsigned int new_state, unsigned int old_state)
1528 {
1529 struct qcom_geni_serial_port *port = to_dev_port(uport);
1530
1531 /* If we've never been called, treat it as off */
1532 if (old_state == UART_PM_STATE_UNDEFINED)
1533 old_state = UART_PM_STATE_OFF;
1534
1535 if (new_state == UART_PM_STATE_ON && old_state == UART_PM_STATE_OFF) {
1536 geni_icc_enable(&port->se);
1537 if (port->clk_rate)
1538 dev_pm_opp_set_rate(uport->dev, port->clk_rate);
1539 geni_se_resources_on(&port->se);
1540 } else if (new_state == UART_PM_STATE_OFF &&
1541 old_state == UART_PM_STATE_ON) {
1542 geni_se_resources_off(&port->se);
1543 dev_pm_opp_set_rate(uport->dev, 0);
1544 geni_icc_disable(&port->se);
1545 }
1546 }
1547
1548 static const struct uart_ops qcom_geni_console_pops = {
1549 .tx_empty = qcom_geni_serial_tx_empty,
1550 .stop_tx = qcom_geni_serial_stop_tx_fifo,
1551 .start_tx = qcom_geni_serial_start_tx_fifo,
1552 .stop_rx = qcom_geni_serial_stop_rx_fifo,
1553 .start_rx = qcom_geni_serial_start_rx_fifo,
1554 .set_termios = qcom_geni_serial_set_termios,
1555 .startup = qcom_geni_serial_startup,
1556 .request_port = qcom_geni_serial_request_port,
1557 .config_port = qcom_geni_serial_config_port,
1558 .shutdown = qcom_geni_serial_shutdown,
1559 .flush_buffer = qcom_geni_serial_flush_buffer,
1560 .type = qcom_geni_serial_get_type,
1561 .set_mctrl = qcom_geni_serial_set_mctrl,
1562 .get_mctrl = qcom_geni_serial_get_mctrl,
1563 #ifdef CONFIG_CONSOLE_POLL
1564 .poll_get_char = qcom_geni_serial_get_char,
1565 .poll_put_char = qcom_geni_serial_poll_put_char,
1566 .poll_init = qcom_geni_serial_port_setup,
1567 #endif
1568 .pm = qcom_geni_serial_pm,
1569 };
1570
1571 static const struct uart_ops qcom_geni_uart_pops = {
1572 .tx_empty = qcom_geni_serial_tx_empty,
1573 .stop_tx = qcom_geni_serial_stop_tx_dma,
1574 .start_tx = qcom_geni_serial_start_tx_dma,
1575 .start_rx = qcom_geni_serial_start_rx_dma,
1576 .stop_rx = qcom_geni_serial_stop_rx_dma,
1577 .set_termios = qcom_geni_serial_set_termios,
1578 .startup = qcom_geni_serial_startup,
1579 .request_port = qcom_geni_serial_request_port,
1580 .config_port = qcom_geni_serial_config_port,
1581 .shutdown = qcom_geni_serial_shutdown,
1582 .type = qcom_geni_serial_get_type,
1583 .set_mctrl = qcom_geni_serial_set_mctrl,
1584 .get_mctrl = qcom_geni_serial_get_mctrl,
1585 .pm = qcom_geni_serial_pm,
1586 };
1587
qcom_geni_serial_probe(struct platform_device * pdev)1588 static int qcom_geni_serial_probe(struct platform_device *pdev)
1589 {
1590 int ret = 0;
1591 int line;
1592 struct qcom_geni_serial_port *port;
1593 struct uart_port *uport;
1594 struct resource *res;
1595 int irq;
1596 struct uart_driver *drv;
1597 const struct qcom_geni_device_data *data;
1598
1599 data = of_device_get_match_data(&pdev->dev);
1600 if (!data)
1601 return -EINVAL;
1602
1603 if (data->console) {
1604 drv = &qcom_geni_console_driver;
1605 line = of_alias_get_id(pdev->dev.of_node, "serial");
1606 } else {
1607 drv = &qcom_geni_uart_driver;
1608 line = of_alias_get_id(pdev->dev.of_node, "serial");
1609 if (line == -ENODEV) /* compat with non-standard aliases */
1610 line = of_alias_get_id(pdev->dev.of_node, "hsuart");
1611 }
1612
1613 port = get_port_from_line(line, data->console);
1614 if (IS_ERR(port)) {
1615 dev_err(&pdev->dev, "Invalid line %d\n", line);
1616 return PTR_ERR(port);
1617 }
1618
1619 uport = &port->uport;
1620 /* Don't allow 2 drivers to access the same port */
1621 if (uport->private_data)
1622 return -ENODEV;
1623
1624 uport->dev = &pdev->dev;
1625 port->dev_data = data;
1626 port->se.dev = &pdev->dev;
1627 port->se.wrapper = dev_get_drvdata(pdev->dev.parent);
1628 port->se.clk = devm_clk_get(&pdev->dev, "se");
1629 if (IS_ERR(port->se.clk)) {
1630 ret = PTR_ERR(port->se.clk);
1631 dev_err(&pdev->dev, "Err getting SE Core clk %d\n", ret);
1632 return ret;
1633 }
1634
1635 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1636 if (!res)
1637 return -EINVAL;
1638 uport->mapbase = res->start;
1639
1640 port->tx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1641 port->rx_fifo_depth = DEF_FIFO_DEPTH_WORDS;
1642 port->tx_fifo_width = DEF_FIFO_WIDTH_BITS;
1643
1644 if (!data->console) {
1645 port->rx_buf = devm_kzalloc(uport->dev,
1646 DMA_RX_BUF_SIZE, GFP_KERNEL);
1647 if (!port->rx_buf)
1648 return -ENOMEM;
1649 }
1650
1651 ret = geni_icc_get(&port->se, NULL);
1652 if (ret)
1653 return ret;
1654 port->se.icc_paths[GENI_TO_CORE].avg_bw = GENI_DEFAULT_BW;
1655 port->se.icc_paths[CPU_TO_GENI].avg_bw = GENI_DEFAULT_BW;
1656
1657 /* Set BW for register access */
1658 ret = geni_icc_set_bw(&port->se);
1659 if (ret)
1660 return ret;
1661
1662 port->name = devm_kasprintf(uport->dev, GFP_KERNEL,
1663 "qcom_geni_serial_%s%d",
1664 uart_console(uport) ? "console" : "uart", uport->line);
1665 if (!port->name)
1666 return -ENOMEM;
1667
1668 irq = platform_get_irq(pdev, 0);
1669 if (irq < 0)
1670 return irq;
1671 uport->irq = irq;
1672 uport->has_sysrq = IS_ENABLED(CONFIG_SERIAL_QCOM_GENI_CONSOLE);
1673
1674 if (!data->console)
1675 port->wakeup_irq = platform_get_irq_optional(pdev, 1);
1676
1677 if (of_property_read_bool(pdev->dev.of_node, "rx-tx-swap"))
1678 port->rx_tx_swap = true;
1679
1680 if (of_property_read_bool(pdev->dev.of_node, "cts-rts-swap"))
1681 port->cts_rts_swap = true;
1682
1683 ret = devm_pm_opp_set_clkname(&pdev->dev, "se");
1684 if (ret)
1685 return ret;
1686 /* OPP table is optional */
1687 ret = devm_pm_opp_of_add_table(&pdev->dev);
1688 if (ret && ret != -ENODEV) {
1689 dev_err(&pdev->dev, "invalid OPP table in device tree\n");
1690 return ret;
1691 }
1692
1693 port->private_data.drv = drv;
1694 uport->private_data = &port->private_data;
1695 platform_set_drvdata(pdev, port);
1696
1697 irq_set_status_flags(uport->irq, IRQ_NOAUTOEN);
1698 ret = devm_request_irq(uport->dev, uport->irq, qcom_geni_serial_isr,
1699 IRQF_TRIGGER_HIGH, port->name, uport);
1700 if (ret) {
1701 dev_err(uport->dev, "Failed to get IRQ ret %d\n", ret);
1702 return ret;
1703 }
1704
1705 ret = uart_add_one_port(drv, uport);
1706 if (ret)
1707 return ret;
1708
1709 if (port->wakeup_irq > 0) {
1710 device_init_wakeup(&pdev->dev, true);
1711 ret = dev_pm_set_dedicated_wake_irq(&pdev->dev,
1712 port->wakeup_irq);
1713 if (ret) {
1714 device_init_wakeup(&pdev->dev, false);
1715 uart_remove_one_port(drv, uport);
1716 return ret;
1717 }
1718 }
1719
1720 return 0;
1721 }
1722
qcom_geni_serial_remove(struct platform_device * pdev)1723 static void qcom_geni_serial_remove(struct platform_device *pdev)
1724 {
1725 struct qcom_geni_serial_port *port = platform_get_drvdata(pdev);
1726 struct uart_driver *drv = port->private_data.drv;
1727
1728 dev_pm_clear_wake_irq(&pdev->dev);
1729 device_init_wakeup(&pdev->dev, false);
1730 uart_remove_one_port(drv, &port->uport);
1731 }
1732
qcom_geni_serial_sys_suspend(struct device * dev)1733 static int qcom_geni_serial_sys_suspend(struct device *dev)
1734 {
1735 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1736 struct uart_port *uport = &port->uport;
1737 struct qcom_geni_private_data *private_data = uport->private_data;
1738
1739 /*
1740 * This is done so we can hit the lowest possible state in suspend
1741 * even with no_console_suspend
1742 */
1743 if (uart_console(uport)) {
1744 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ACTIVE_ONLY);
1745 geni_icc_set_bw(&port->se);
1746 }
1747 return uart_suspend_port(private_data->drv, uport);
1748 }
1749
qcom_geni_serial_sys_resume(struct device * dev)1750 static int qcom_geni_serial_sys_resume(struct device *dev)
1751 {
1752 int ret;
1753 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1754 struct uart_port *uport = &port->uport;
1755 struct qcom_geni_private_data *private_data = uport->private_data;
1756
1757 ret = uart_resume_port(private_data->drv, uport);
1758 if (uart_console(uport)) {
1759 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);
1760 geni_icc_set_bw(&port->se);
1761 }
1762 return ret;
1763 }
1764
qcom_geni_serial_sys_hib_resume(struct device * dev)1765 static int qcom_geni_serial_sys_hib_resume(struct device *dev)
1766 {
1767 int ret = 0;
1768 struct uart_port *uport;
1769 struct qcom_geni_private_data *private_data;
1770 struct qcom_geni_serial_port *port = dev_get_drvdata(dev);
1771
1772 uport = &port->uport;
1773 private_data = uport->private_data;
1774
1775 if (uart_console(uport)) {
1776 geni_icc_set_tag(&port->se, QCOM_ICC_TAG_ALWAYS);
1777 geni_icc_set_bw(&port->se);
1778 ret = uart_resume_port(private_data->drv, uport);
1779 /*
1780 * For hibernation usecase clients for
1781 * console UART won't call port setup during restore,
1782 * hence call port setup for console uart.
1783 */
1784 qcom_geni_serial_port_setup(uport);
1785 } else {
1786 /*
1787 * Peripheral register settings are lost during hibernation.
1788 * Update setup flag such that port setup happens again
1789 * during next session. Clients of HS-UART will close and
1790 * open the port during hibernation.
1791 */
1792 port->setup = false;
1793 }
1794 return ret;
1795 }
1796
1797 static const struct qcom_geni_device_data qcom_geni_console_data = {
1798 .console = true,
1799 .mode = GENI_SE_FIFO,
1800 };
1801
1802 static const struct qcom_geni_device_data qcom_geni_uart_data = {
1803 .console = false,
1804 .mode = GENI_SE_DMA,
1805 };
1806
1807 static const struct dev_pm_ops qcom_geni_serial_pm_ops = {
1808 .suspend = pm_sleep_ptr(qcom_geni_serial_sys_suspend),
1809 .resume = pm_sleep_ptr(qcom_geni_serial_sys_resume),
1810 .freeze = pm_sleep_ptr(qcom_geni_serial_sys_suspend),
1811 .poweroff = pm_sleep_ptr(qcom_geni_serial_sys_suspend),
1812 .restore = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume),
1813 .thaw = pm_sleep_ptr(qcom_geni_serial_sys_hib_resume),
1814 };
1815
1816 static const struct of_device_id qcom_geni_serial_match_table[] = {
1817 {
1818 .compatible = "qcom,geni-debug-uart",
1819 .data = &qcom_geni_console_data,
1820 },
1821 {
1822 .compatible = "qcom,geni-uart",
1823 .data = &qcom_geni_uart_data,
1824 },
1825 {}
1826 };
1827 MODULE_DEVICE_TABLE(of, qcom_geni_serial_match_table);
1828
1829 static struct platform_driver qcom_geni_serial_platform_driver = {
1830 .remove_new = qcom_geni_serial_remove,
1831 .probe = qcom_geni_serial_probe,
1832 .driver = {
1833 .name = "qcom_geni_serial",
1834 .of_match_table = qcom_geni_serial_match_table,
1835 .pm = &qcom_geni_serial_pm_ops,
1836 },
1837 };
1838
qcom_geni_serial_init(void)1839 static int __init qcom_geni_serial_init(void)
1840 {
1841 int ret;
1842
1843 ret = console_register(&qcom_geni_console_driver);
1844 if (ret)
1845 return ret;
1846
1847 ret = uart_register_driver(&qcom_geni_uart_driver);
1848 if (ret) {
1849 console_unregister(&qcom_geni_console_driver);
1850 return ret;
1851 }
1852
1853 ret = platform_driver_register(&qcom_geni_serial_platform_driver);
1854 if (ret) {
1855 console_unregister(&qcom_geni_console_driver);
1856 uart_unregister_driver(&qcom_geni_uart_driver);
1857 }
1858 return ret;
1859 }
1860 module_init(qcom_geni_serial_init);
1861
qcom_geni_serial_exit(void)1862 static void __exit qcom_geni_serial_exit(void)
1863 {
1864 platform_driver_unregister(&qcom_geni_serial_platform_driver);
1865 console_unregister(&qcom_geni_console_driver);
1866 uart_unregister_driver(&qcom_geni_uart_driver);
1867 }
1868 module_exit(qcom_geni_serial_exit);
1869
1870 MODULE_DESCRIPTION("Serial driver for GENI based QUP cores");
1871 MODULE_LICENSE("GPL v2");
1872