1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2 /*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7 #include <linux/types.h>
8 #include <linux/bitops.h>
9 #include <linux/bitfield.h>
10
11 #include "debug.h"
12 #include "core.h"
13 #include "ce.h"
14 #include "hw.h"
15 #include "mhi.h"
16 #include "dp_rx.h"
17 #include "peer.h"
18
19 static const guid_t wcn7850_uuid = GUID_INIT(0xf634f534, 0x6147, 0x11ec,
20 0x90, 0xd6, 0x02, 0x42,
21 0xac, 0x12, 0x00, 0x03);
22
ath12k_hw_qcn9274_mac_from_pdev_id(int pdev_idx)23 static u8 ath12k_hw_qcn9274_mac_from_pdev_id(int pdev_idx)
24 {
25 return pdev_idx;
26 }
27
ath12k_hw_mac_id_to_pdev_id_qcn9274(const struct ath12k_hw_params * hw,int mac_id)28 static int ath12k_hw_mac_id_to_pdev_id_qcn9274(const struct ath12k_hw_params *hw,
29 int mac_id)
30 {
31 return mac_id;
32 }
33
ath12k_hw_mac_id_to_srng_id_qcn9274(const struct ath12k_hw_params * hw,int mac_id)34 static int ath12k_hw_mac_id_to_srng_id_qcn9274(const struct ath12k_hw_params *hw,
35 int mac_id)
36 {
37 return 0;
38 }
39
ath12k_hw_get_ring_selector_qcn9274(struct sk_buff * skb)40 static u8 ath12k_hw_get_ring_selector_qcn9274(struct sk_buff *skb)
41 {
42 return smp_processor_id();
43 }
44
ath12k_dp_srng_is_comp_ring_qcn9274(int ring_num)45 static bool ath12k_dp_srng_is_comp_ring_qcn9274(int ring_num)
46 {
47 if (ring_num < 3 || ring_num == 4)
48 return true;
49
50 return false;
51 }
52
ath12k_is_frame_link_agnostic_qcn9274(struct ath12k_link_vif * arvif,struct ieee80211_mgmt * mgmt)53 static bool ath12k_is_frame_link_agnostic_qcn9274(struct ath12k_link_vif *arvif,
54 struct ieee80211_mgmt *mgmt)
55 {
56 return ieee80211_is_action(mgmt->frame_control);
57 }
58
ath12k_hw_mac_id_to_pdev_id_wcn7850(const struct ath12k_hw_params * hw,int mac_id)59 static int ath12k_hw_mac_id_to_pdev_id_wcn7850(const struct ath12k_hw_params *hw,
60 int mac_id)
61 {
62 return 0;
63 }
64
ath12k_hw_mac_id_to_srng_id_wcn7850(const struct ath12k_hw_params * hw,int mac_id)65 static int ath12k_hw_mac_id_to_srng_id_wcn7850(const struct ath12k_hw_params *hw,
66 int mac_id)
67 {
68 return mac_id;
69 }
70
ath12k_hw_get_ring_selector_wcn7850(struct sk_buff * skb)71 static u8 ath12k_hw_get_ring_selector_wcn7850(struct sk_buff *skb)
72 {
73 return skb_get_queue_mapping(skb);
74 }
75
ath12k_dp_srng_is_comp_ring_wcn7850(int ring_num)76 static bool ath12k_dp_srng_is_comp_ring_wcn7850(int ring_num)
77 {
78 if (ring_num == 0 || ring_num == 2 || ring_num == 4)
79 return true;
80
81 return false;
82 }
83
ath12k_is_addba_resp_action_code(struct ieee80211_mgmt * mgmt)84 static bool ath12k_is_addba_resp_action_code(struct ieee80211_mgmt *mgmt)
85 {
86 if (!ieee80211_is_action(mgmt->frame_control))
87 return false;
88
89 if (mgmt->u.action.category != WLAN_CATEGORY_BACK)
90 return false;
91
92 if (mgmt->u.action.u.addba_resp.action_code != WLAN_ACTION_ADDBA_RESP)
93 return false;
94
95 return true;
96 }
97
ath12k_is_frame_link_agnostic_wcn7850(struct ath12k_link_vif * arvif,struct ieee80211_mgmt * mgmt)98 static bool ath12k_is_frame_link_agnostic_wcn7850(struct ath12k_link_vif *arvif,
99 struct ieee80211_mgmt *mgmt)
100 {
101 struct ieee80211_vif *vif = ath12k_ahvif_to_vif(arvif->ahvif);
102 struct ath12k_hw *ah = ath12k_ar_to_ah(arvif->ar);
103 struct ath12k_base *ab = arvif->ar->ab;
104 __le16 fc = mgmt->frame_control;
105
106 spin_lock_bh(&ab->base_lock);
107 if (!ath12k_peer_find_by_addr(ab, mgmt->da) &&
108 !ath12k_peer_ml_find(ah, mgmt->da)) {
109 spin_unlock_bh(&ab->base_lock);
110 return false;
111 }
112 spin_unlock_bh(&ab->base_lock);
113
114 if (vif->type == NL80211_IFTYPE_STATION)
115 return arvif->is_up &&
116 (vif->valid_links == vif->active_links) &&
117 !ieee80211_is_probe_req(fc) &&
118 !ieee80211_is_auth(fc) &&
119 !ieee80211_is_deauth(fc) &&
120 !ath12k_is_addba_resp_action_code(mgmt);
121
122 if (vif->type == NL80211_IFTYPE_AP)
123 return !(ieee80211_is_probe_resp(fc) || ieee80211_is_auth(fc) ||
124 ieee80211_is_assoc_resp(fc) || ieee80211_is_reassoc_resp(fc) ||
125 ath12k_is_addba_resp_action_code(mgmt));
126
127 return false;
128 }
129
130 static const struct ath12k_hw_ops qcn9274_ops = {
131 .get_hw_mac_from_pdev_id = ath12k_hw_qcn9274_mac_from_pdev_id,
132 .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_qcn9274,
133 .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_qcn9274,
134 .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_qcn9274,
135 .get_ring_selector = ath12k_hw_get_ring_selector_qcn9274,
136 .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_qcn9274,
137 .is_frame_link_agnostic = ath12k_is_frame_link_agnostic_qcn9274,
138 };
139
140 static const struct ath12k_hw_ops wcn7850_ops = {
141 .get_hw_mac_from_pdev_id = ath12k_hw_qcn9274_mac_from_pdev_id,
142 .mac_id_to_pdev_id = ath12k_hw_mac_id_to_pdev_id_wcn7850,
143 .mac_id_to_srng_id = ath12k_hw_mac_id_to_srng_id_wcn7850,
144 .rxdma_ring_sel_config = ath12k_dp_rxdma_ring_sel_config_wcn7850,
145 .get_ring_selector = ath12k_hw_get_ring_selector_wcn7850,
146 .dp_srng_is_tx_comp_ring = ath12k_dp_srng_is_comp_ring_wcn7850,
147 .is_frame_link_agnostic = ath12k_is_frame_link_agnostic_wcn7850,
148 };
149
150 #define ATH12K_TX_RING_MASK_0 0x1
151 #define ATH12K_TX_RING_MASK_1 0x2
152 #define ATH12K_TX_RING_MASK_2 0x4
153 #define ATH12K_TX_RING_MASK_3 0x8
154 #define ATH12K_TX_RING_MASK_4 0x10
155
156 #define ATH12K_RX_RING_MASK_0 0x1
157 #define ATH12K_RX_RING_MASK_1 0x2
158 #define ATH12K_RX_RING_MASK_2 0x4
159 #define ATH12K_RX_RING_MASK_3 0x8
160
161 #define ATH12K_RX_ERR_RING_MASK_0 0x1
162
163 #define ATH12K_RX_WBM_REL_RING_MASK_0 0x1
164
165 #define ATH12K_REO_STATUS_RING_MASK_0 0x1
166
167 #define ATH12K_HOST2RXDMA_RING_MASK_0 0x1
168
169 #define ATH12K_RX_MON_RING_MASK_0 0x1
170 #define ATH12K_RX_MON_RING_MASK_1 0x2
171 #define ATH12K_RX_MON_RING_MASK_2 0x4
172
173 #define ATH12K_TX_MON_RING_MASK_0 0x1
174 #define ATH12K_TX_MON_RING_MASK_1 0x2
175
176 #define ATH12K_RX_MON_STATUS_RING_MASK_0 0x1
177 #define ATH12K_RX_MON_STATUS_RING_MASK_1 0x2
178 #define ATH12K_RX_MON_STATUS_RING_MASK_2 0x4
179
180 /* Target firmware's Copy Engine configuration. */
181 static const struct ce_pipe_config ath12k_target_ce_config_wlan_qcn9274[] = {
182 /* CE0: host->target HTC control and raw streams */
183 {
184 .pipenum = __cpu_to_le32(0),
185 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
186 .nentries = __cpu_to_le32(32),
187 .nbytes_max = __cpu_to_le32(2048),
188 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
189 .reserved = __cpu_to_le32(0),
190 },
191
192 /* CE1: target->host HTT + HTC control */
193 {
194 .pipenum = __cpu_to_le32(1),
195 .pipedir = __cpu_to_le32(PIPEDIR_IN),
196 .nentries = __cpu_to_le32(32),
197 .nbytes_max = __cpu_to_le32(2048),
198 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
199 .reserved = __cpu_to_le32(0),
200 },
201
202 /* CE2: target->host WMI */
203 {
204 .pipenum = __cpu_to_le32(2),
205 .pipedir = __cpu_to_le32(PIPEDIR_IN),
206 .nentries = __cpu_to_le32(32),
207 .nbytes_max = __cpu_to_le32(2048),
208 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
209 .reserved = __cpu_to_le32(0),
210 },
211
212 /* CE3: host->target WMI (mac0) */
213 {
214 .pipenum = __cpu_to_le32(3),
215 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
216 .nentries = __cpu_to_le32(32),
217 .nbytes_max = __cpu_to_le32(2048),
218 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
219 .reserved = __cpu_to_le32(0),
220 },
221
222 /* CE4: host->target HTT */
223 {
224 .pipenum = __cpu_to_le32(4),
225 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
226 .nentries = __cpu_to_le32(256),
227 .nbytes_max = __cpu_to_le32(256),
228 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
229 .reserved = __cpu_to_le32(0),
230 },
231
232 /* CE5: target->host Pktlog */
233 {
234 .pipenum = __cpu_to_le32(5),
235 .pipedir = __cpu_to_le32(PIPEDIR_IN),
236 .nentries = __cpu_to_le32(32),
237 .nbytes_max = __cpu_to_le32(2048),
238 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
239 .reserved = __cpu_to_le32(0),
240 },
241
242 /* CE6: Reserved for target autonomous hif_memcpy */
243 {
244 .pipenum = __cpu_to_le32(6),
245 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
246 .nentries = __cpu_to_le32(32),
247 .nbytes_max = __cpu_to_le32(16384),
248 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
249 .reserved = __cpu_to_le32(0),
250 },
251
252 /* CE7: host->target WMI (mac1) */
253 {
254 .pipenum = __cpu_to_le32(7),
255 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
256 .nentries = __cpu_to_le32(32),
257 .nbytes_max = __cpu_to_le32(2048),
258 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
259 .reserved = __cpu_to_le32(0),
260 },
261
262 /* CE8: Reserved for target autonomous hif_memcpy */
263 {
264 .pipenum = __cpu_to_le32(8),
265 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
266 .nentries = __cpu_to_le32(32),
267 .nbytes_max = __cpu_to_le32(16384),
268 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
269 .reserved = __cpu_to_le32(0),
270 },
271
272 /* CE9, 10 and 11: Reserved for MHI */
273
274 /* CE12: Target CV prefetch */
275 {
276 .pipenum = __cpu_to_le32(12),
277 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
278 .nentries = __cpu_to_le32(32),
279 .nbytes_max = __cpu_to_le32(2048),
280 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
281 .reserved = __cpu_to_le32(0),
282 },
283
284 /* CE13: Target CV prefetch */
285 {
286 .pipenum = __cpu_to_le32(13),
287 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
288 .nentries = __cpu_to_le32(32),
289 .nbytes_max = __cpu_to_le32(2048),
290 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
291 .reserved = __cpu_to_le32(0),
292 },
293
294 /* CE14: WMI logging/CFR/Spectral/Radar */
295 {
296 .pipenum = __cpu_to_le32(14),
297 .pipedir = __cpu_to_le32(PIPEDIR_IN),
298 .nentries = __cpu_to_le32(32),
299 .nbytes_max = __cpu_to_le32(2048),
300 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
301 .reserved = __cpu_to_le32(0),
302 },
303
304 /* CE15: Reserved */
305 };
306
307 /* Target firmware's Copy Engine configuration. */
308 static const struct ce_pipe_config ath12k_target_ce_config_wlan_wcn7850[] = {
309 /* CE0: host->target HTC control and raw streams */
310 {
311 .pipenum = __cpu_to_le32(0),
312 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
313 .nentries = __cpu_to_le32(32),
314 .nbytes_max = __cpu_to_le32(2048),
315 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
316 .reserved = __cpu_to_le32(0),
317 },
318
319 /* CE1: target->host HTT + HTC control */
320 {
321 .pipenum = __cpu_to_le32(1),
322 .pipedir = __cpu_to_le32(PIPEDIR_IN),
323 .nentries = __cpu_to_le32(32),
324 .nbytes_max = __cpu_to_le32(2048),
325 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
326 .reserved = __cpu_to_le32(0),
327 },
328
329 /* CE2: target->host WMI */
330 {
331 .pipenum = __cpu_to_le32(2),
332 .pipedir = __cpu_to_le32(PIPEDIR_IN),
333 .nentries = __cpu_to_le32(32),
334 .nbytes_max = __cpu_to_le32(2048),
335 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
336 .reserved = __cpu_to_le32(0),
337 },
338
339 /* CE3: host->target WMI */
340 {
341 .pipenum = __cpu_to_le32(3),
342 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
343 .nentries = __cpu_to_le32(32),
344 .nbytes_max = __cpu_to_le32(2048),
345 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
346 .reserved = __cpu_to_le32(0),
347 },
348
349 /* CE4: host->target HTT */
350 {
351 .pipenum = __cpu_to_le32(4),
352 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
353 .nentries = __cpu_to_le32(256),
354 .nbytes_max = __cpu_to_le32(256),
355 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
356 .reserved = __cpu_to_le32(0),
357 },
358
359 /* CE5: target->host Pktlog */
360 {
361 .pipenum = __cpu_to_le32(5),
362 .pipedir = __cpu_to_le32(PIPEDIR_IN),
363 .nentries = __cpu_to_le32(32),
364 .nbytes_max = __cpu_to_le32(2048),
365 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
366 .reserved = __cpu_to_le32(0),
367 },
368
369 /* CE6: Reserved for target autonomous hif_memcpy */
370 {
371 .pipenum = __cpu_to_le32(6),
372 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
373 .nentries = __cpu_to_le32(32),
374 .nbytes_max = __cpu_to_le32(16384),
375 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
376 .reserved = __cpu_to_le32(0),
377 },
378
379 /* CE7 used only by Host */
380 {
381 .pipenum = __cpu_to_le32(7),
382 .pipedir = __cpu_to_le32(PIPEDIR_INOUT_H2H),
383 .nentries = __cpu_to_le32(0),
384 .nbytes_max = __cpu_to_le32(0),
385 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
386 .reserved = __cpu_to_le32(0),
387 },
388
389 /* CE8 target->host used only by IPA */
390 {
391 .pipenum = __cpu_to_le32(8),
392 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
393 .nentries = __cpu_to_le32(32),
394 .nbytes_max = __cpu_to_le32(16384),
395 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
396 .reserved = __cpu_to_le32(0),
397 },
398 /* CE 9, 10, 11 are used by MHI driver */
399 };
400
401 /* Map from service/endpoint to Copy Engine.
402 * This table is derived from the CE_PCI TABLE, above.
403 * It is passed to the Target at startup for use by firmware.
404 */
405 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_qcn9274[] = {
406 {
407 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
408 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
409 __cpu_to_le32(3),
410 },
411 {
412 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
413 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
414 __cpu_to_le32(2),
415 },
416 {
417 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
418 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
419 __cpu_to_le32(3),
420 },
421 {
422 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
423 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
424 __cpu_to_le32(2),
425 },
426 {
427 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
428 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
429 __cpu_to_le32(3),
430 },
431 {
432 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
433 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
434 __cpu_to_le32(2),
435 },
436 {
437 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
438 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
439 __cpu_to_le32(3),
440 },
441 {
442 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
443 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
444 __cpu_to_le32(2),
445 },
446 {
447 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
448 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
449 __cpu_to_le32(3),
450 },
451 {
452 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
453 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
454 __cpu_to_le32(2),
455 },
456 {
457 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
458 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
459 __cpu_to_le32(0),
460 },
461 {
462 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
463 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
464 __cpu_to_le32(1),
465 },
466 {
467 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS),
468 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
469 __cpu_to_le32(0),
470 },
471 {
472 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS),
473 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
474 __cpu_to_le32(1),
475 },
476 {
477 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
478 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
479 __cpu_to_le32(4),
480 },
481 {
482 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
483 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
484 __cpu_to_le32(1),
485 },
486 {
487 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1),
488 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
489 __cpu_to_le32(7),
490 },
491 {
492 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_MAC1),
493 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
494 __cpu_to_le32(2),
495 },
496 {
497 __cpu_to_le32(ATH12K_HTC_SVC_ID_PKT_LOG),
498 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
499 __cpu_to_le32(5),
500 },
501 {
502 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_DIAG),
503 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
504 __cpu_to_le32(14),
505 },
506
507 /* (Additions here) */
508
509 { /* must be last */
510 __cpu_to_le32(0),
511 __cpu_to_le32(0),
512 __cpu_to_le32(0),
513 },
514 };
515
516 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_wcn7850[] = {
517 {
518 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
519 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
520 __cpu_to_le32(3),
521 },
522 {
523 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
524 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
525 __cpu_to_le32(2),
526 },
527 {
528 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
529 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
530 __cpu_to_le32(3),
531 },
532 {
533 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
534 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
535 __cpu_to_le32(2),
536 },
537 {
538 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
539 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
540 __cpu_to_le32(3),
541 },
542 {
543 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
544 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
545 __cpu_to_le32(2),
546 },
547 {
548 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
549 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
550 __cpu_to_le32(3),
551 },
552 {
553 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
554 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
555 __cpu_to_le32(2),
556 },
557 {
558 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
559 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
560 __cpu_to_le32(3),
561 },
562 {
563 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
564 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
565 __cpu_to_le32(2),
566 },
567 {
568 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
569 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
570 __cpu_to_le32(0),
571 },
572 {
573 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
574 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
575 __cpu_to_le32(2),
576 },
577 {
578 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
579 __cpu_to_le32(PIPEDIR_OUT), /* out = UL = host -> target */
580 __cpu_to_le32(4),
581 },
582 {
583 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
584 __cpu_to_le32(PIPEDIR_IN), /* in = DL = target -> host */
585 __cpu_to_le32(1),
586 },
587
588 /* (Additions here) */
589
590 { /* must be last */
591 __cpu_to_le32(0),
592 __cpu_to_le32(0),
593 __cpu_to_le32(0),
594 },
595 };
596
597 static const struct ce_pipe_config ath12k_target_ce_config_wlan_ipq5332[] = {
598 /* host->target HTC control and raw streams */
599 {
600 .pipenum = __cpu_to_le32(0),
601 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
602 .nentries = __cpu_to_le32(32),
603 .nbytes_max = __cpu_to_le32(2048),
604 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
605 .reserved = __cpu_to_le32(0),
606 },
607 /* target->host HTT */
608 {
609 .pipenum = __cpu_to_le32(1),
610 .pipedir = __cpu_to_le32(PIPEDIR_IN),
611 .nentries = __cpu_to_le32(32),
612 .nbytes_max = __cpu_to_le32(2048),
613 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
614 .reserved = __cpu_to_le32(0),
615 },
616 /* target->host WMI + HTC control */
617 {
618 .pipenum = __cpu_to_le32(2),
619 .pipedir = __cpu_to_le32(PIPEDIR_IN),
620 .nentries = __cpu_to_le32(32),
621 .nbytes_max = __cpu_to_le32(2048),
622 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
623 .reserved = __cpu_to_le32(0),
624 },
625 /* host->target WMI */
626 {
627 .pipenum = __cpu_to_le32(3),
628 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
629 .nentries = __cpu_to_le32(32),
630 .nbytes_max = __cpu_to_le32(2048),
631 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
632 .reserved = __cpu_to_le32(0),
633 },
634 /* host->target HTT */
635 {
636 .pipenum = __cpu_to_le32(4),
637 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
638 .nentries = __cpu_to_le32(256),
639 .nbytes_max = __cpu_to_le32(256),
640 .flags = __cpu_to_le32(CE_ATTR_FLAGS | CE_ATTR_DIS_INTR),
641 .reserved = __cpu_to_le32(0),
642 },
643 /* Target -> host PKTLOG */
644 {
645 .pipenum = __cpu_to_le32(5),
646 .pipedir = __cpu_to_le32(PIPEDIR_IN),
647 .nentries = __cpu_to_le32(32),
648 .nbytes_max = __cpu_to_le32(2048),
649 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
650 .reserved = __cpu_to_le32(0),
651 },
652 /* Reserved for target autonomous HIF_memcpy */
653 {
654 .pipenum = __cpu_to_le32(6),
655 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
656 .nentries = __cpu_to_le32(32),
657 .nbytes_max = __cpu_to_le32(16384),
658 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
659 .reserved = __cpu_to_le32(0),
660 },
661 /* CE7 Reserved for CV Prefetch */
662 {
663 .pipenum = __cpu_to_le32(7),
664 .pipedir = __cpu_to_le32(PIPEDIR_OUT),
665 .nentries = __cpu_to_le32(32),
666 .nbytes_max = __cpu_to_le32(2048),
667 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
668 .reserved = __cpu_to_le32(0),
669 },
670 /* CE8 Reserved for target generic HIF memcpy */
671 {
672 .pipenum = __cpu_to_le32(8),
673 .pipedir = __cpu_to_le32(PIPEDIR_INOUT),
674 .nentries = __cpu_to_le32(32),
675 .nbytes_max = __cpu_to_le32(16384),
676 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
677 .reserved = __cpu_to_le32(0),
678 },
679 /* CE9 WMI logging/CFR/Spectral/Radar/ */
680 {
681 .pipenum = __cpu_to_le32(9),
682 .pipedir = __cpu_to_le32(PIPEDIR_IN),
683 .nentries = __cpu_to_le32(32),
684 .nbytes_max = __cpu_to_le32(2048),
685 .flags = __cpu_to_le32(CE_ATTR_FLAGS),
686 .reserved = __cpu_to_le32(0),
687 },
688 /* Unused TBD */
689 {
690 .pipenum = __cpu_to_le32(10),
691 .pipedir = __cpu_to_le32(PIPEDIR_NONE),
692 .nentries = __cpu_to_le32(0),
693 .nbytes_max = __cpu_to_le32(0),
694 .flags = __cpu_to_le32(0),
695 .reserved = __cpu_to_le32(0),
696 },
697 /* Unused TBD */
698 {
699 .pipenum = __cpu_to_le32(11),
700 .pipedir = __cpu_to_le32(PIPEDIR_NONE),
701 .nentries = __cpu_to_le32(0),
702 .nbytes_max = __cpu_to_le32(0),
703 .flags = __cpu_to_le32(0),
704 .reserved = __cpu_to_le32(0),
705 },
706 };
707
708 static const struct service_to_pipe ath12k_target_service_to_ce_map_wlan_ipq5332[] = {
709 {
710 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
711 __cpu_to_le32(PIPEDIR_OUT),
712 __cpu_to_le32(3),
713 },
714 {
715 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VO),
716 __cpu_to_le32(PIPEDIR_IN),
717 __cpu_to_le32(2),
718 },
719 {
720 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
721 __cpu_to_le32(PIPEDIR_OUT),
722 __cpu_to_le32(3),
723 },
724 {
725 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BK),
726 __cpu_to_le32(PIPEDIR_IN),
727 __cpu_to_le32(2),
728 },
729 {
730 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
731 __cpu_to_le32(PIPEDIR_OUT),
732 __cpu_to_le32(3),
733 },
734 {
735 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_BE),
736 __cpu_to_le32(PIPEDIR_IN),
737 __cpu_to_le32(2),
738 },
739 {
740 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
741 __cpu_to_le32(PIPEDIR_OUT),
742 __cpu_to_le32(3),
743 },
744 {
745 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_DATA_VI),
746 __cpu_to_le32(PIPEDIR_IN),
747 __cpu_to_le32(2),
748 },
749 {
750 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
751 __cpu_to_le32(PIPEDIR_OUT),
752 __cpu_to_le32(3),
753 },
754 {
755 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL),
756 __cpu_to_le32(PIPEDIR_IN),
757 __cpu_to_le32(2),
758 },
759 {
760 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
761 __cpu_to_le32(PIPEDIR_OUT),
762 __cpu_to_le32(0),
763 },
764 {
765 __cpu_to_le32(ATH12K_HTC_SVC_ID_RSVD_CTRL),
766 __cpu_to_le32(PIPEDIR_IN),
767 __cpu_to_le32(1),
768 },
769 {
770 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS),
771 __cpu_to_le32(PIPEDIR_OUT),
772 __cpu_to_le32(0),
773 },
774 {
775 __cpu_to_le32(ATH12K_HTC_SVC_ID_TEST_RAW_STREAMS),
776 __cpu_to_le32(PIPEDIR_IN),
777 __cpu_to_le32(1),
778 },
779 {
780 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
781 __cpu_to_le32(PIPEDIR_OUT),
782 __cpu_to_le32(4),
783 },
784 {
785 __cpu_to_le32(ATH12K_HTC_SVC_ID_HTT_DATA_MSG),
786 __cpu_to_le32(PIPEDIR_IN),
787 __cpu_to_le32(1),
788 },
789 {
790 __cpu_to_le32(ATH12K_HTC_SVC_ID_PKT_LOG),
791 __cpu_to_le32(PIPEDIR_IN),
792 __cpu_to_le32(5),
793 },
794 {
795 __cpu_to_le32(ATH12K_HTC_SVC_ID_WMI_CONTROL_DIAG),
796 __cpu_to_le32(PIPEDIR_IN),
797 __cpu_to_le32(9),
798 },
799 /* (Additions here) */
800
801 { /* must be last */
802 __cpu_to_le32(0),
803 __cpu_to_le32(0),
804 __cpu_to_le32(0),
805 },
806 };
807
808 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_qcn9274 = {
809 .tx = {
810 ATH12K_TX_RING_MASK_0,
811 ATH12K_TX_RING_MASK_1,
812 ATH12K_TX_RING_MASK_2,
813 ATH12K_TX_RING_MASK_3,
814 },
815 .rx_mon_dest = {
816 0, 0, 0, 0,
817 0, 0, 0, 0,
818 ATH12K_RX_MON_RING_MASK_0,
819 ATH12K_RX_MON_RING_MASK_1,
820 ATH12K_RX_MON_RING_MASK_2,
821 },
822 .rx = {
823 0, 0, 0, 0,
824 ATH12K_RX_RING_MASK_0,
825 ATH12K_RX_RING_MASK_1,
826 ATH12K_RX_RING_MASK_2,
827 ATH12K_RX_RING_MASK_3,
828 },
829 .rx_err = {
830 0, 0, 0,
831 ATH12K_RX_ERR_RING_MASK_0,
832 },
833 .rx_wbm_rel = {
834 0, 0, 0,
835 ATH12K_RX_WBM_REL_RING_MASK_0,
836 },
837 .reo_status = {
838 0, 0, 0,
839 ATH12K_REO_STATUS_RING_MASK_0,
840 },
841 .host2rxdma = {
842 0, 0, 0,
843 ATH12K_HOST2RXDMA_RING_MASK_0,
844 },
845 .tx_mon_dest = {
846 0, 0, 0,
847 },
848 };
849
850 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_ipq5332 = {
851 .tx = {
852 ATH12K_TX_RING_MASK_0,
853 ATH12K_TX_RING_MASK_1,
854 ATH12K_TX_RING_MASK_2,
855 ATH12K_TX_RING_MASK_3,
856 },
857 .rx_mon_dest = {
858 0, 0, 0, 0, 0, 0, 0, 0,
859 ATH12K_RX_MON_RING_MASK_0,
860 },
861 .rx = {
862 0, 0, 0, 0,
863 ATH12K_RX_RING_MASK_0,
864 ATH12K_RX_RING_MASK_1,
865 ATH12K_RX_RING_MASK_2,
866 ATH12K_RX_RING_MASK_3,
867 },
868 .rx_err = {
869 0, 0, 0,
870 ATH12K_RX_ERR_RING_MASK_0,
871 },
872 .rx_wbm_rel = {
873 0, 0, 0,
874 ATH12K_RX_WBM_REL_RING_MASK_0,
875 },
876 .reo_status = {
877 0, 0, 0,
878 ATH12K_REO_STATUS_RING_MASK_0,
879 },
880 .host2rxdma = {
881 0, 0, 0,
882 ATH12K_HOST2RXDMA_RING_MASK_0,
883 },
884 .tx_mon_dest = {
885 ATH12K_TX_MON_RING_MASK_0,
886 ATH12K_TX_MON_RING_MASK_1,
887 },
888 };
889
890 static const struct ath12k_hw_ring_mask ath12k_hw_ring_mask_wcn7850 = {
891 .tx = {
892 ATH12K_TX_RING_MASK_0,
893 ATH12K_TX_RING_MASK_1,
894 ATH12K_TX_RING_MASK_2,
895 },
896 .rx_mon_dest = {
897 },
898 .rx_mon_status = {
899 0, 0, 0, 0,
900 ATH12K_RX_MON_STATUS_RING_MASK_0,
901 ATH12K_RX_MON_STATUS_RING_MASK_1,
902 ATH12K_RX_MON_STATUS_RING_MASK_2,
903 },
904 .rx = {
905 0, 0, 0,
906 ATH12K_RX_RING_MASK_0,
907 ATH12K_RX_RING_MASK_1,
908 ATH12K_RX_RING_MASK_2,
909 ATH12K_RX_RING_MASK_3,
910 },
911 .rx_err = {
912 ATH12K_RX_ERR_RING_MASK_0,
913 },
914 .rx_wbm_rel = {
915 ATH12K_RX_WBM_REL_RING_MASK_0,
916 },
917 .reo_status = {
918 ATH12K_REO_STATUS_RING_MASK_0,
919 },
920 .host2rxdma = {
921 },
922 .tx_mon_dest = {
923 },
924 };
925
926 static const struct ath12k_hw_regs qcn9274_v1_regs = {
927 /* SW2TCL(x) R0 ring configuration address */
928 .hal_tcl1_ring_id = 0x00000908,
929 .hal_tcl1_ring_misc = 0x00000910,
930 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c,
931 .hal_tcl1_ring_tp_addr_msb = 0x00000920,
932 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930,
933 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934,
934 .hal_tcl1_ring_msi1_base_lsb = 0x00000948,
935 .hal_tcl1_ring_msi1_base_msb = 0x0000094c,
936 .hal_tcl1_ring_msi1_data = 0x00000950,
937 .hal_tcl_ring_base_lsb = 0x00000b58,
938 .hal_tcl1_ring_base_lsb = 0x00000900,
939 .hal_tcl1_ring_base_msb = 0x00000904,
940 .hal_tcl2_ring_base_lsb = 0x00000978,
941
942 /* TCL STATUS ring address */
943 .hal_tcl_status_ring_base_lsb = 0x00000d38,
944
945 .hal_wbm_idle_ring_base_lsb = 0x00000d0c,
946 .hal_wbm_idle_ring_misc_addr = 0x00000d1c,
947 .hal_wbm_r0_idle_list_cntl_addr = 0x00000210,
948 .hal_wbm_r0_idle_list_size_addr = 0x00000214,
949 .hal_wbm_scattered_ring_base_lsb = 0x00000220,
950 .hal_wbm_scattered_ring_base_msb = 0x00000224,
951 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000230,
952 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000234,
953 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000240,
954 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000244,
955 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000024c,
956
957 .hal_wbm_sw_release_ring_base_lsb = 0x0000034c,
958 .hal_wbm_sw1_release_ring_base_lsb = 0x000003c4,
959 .hal_wbm0_release_ring_base_lsb = 0x00000dd8,
960 .hal_wbm1_release_ring_base_lsb = 0x00000e50,
961
962 /* PCIe base address */
963 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8,
964 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c,
965
966 /* PPE release ring address */
967 .hal_ppe_rel_ring_base = 0x0000043c,
968
969 /* REO DEST ring address */
970 .hal_reo2_ring_base = 0x0000055c,
971 .hal_reo1_misc_ctrl_addr = 0x00000b7c,
972 .hal_reo1_sw_cookie_cfg0 = 0x00000050,
973 .hal_reo1_sw_cookie_cfg1 = 0x00000054,
974 .hal_reo1_qdesc_lut_base0 = 0x00000058,
975 .hal_reo1_qdesc_lut_base1 = 0x0000005c,
976 .hal_reo1_ring_base_lsb = 0x000004e4,
977 .hal_reo1_ring_base_msb = 0x000004e8,
978 .hal_reo1_ring_id = 0x000004ec,
979 .hal_reo1_ring_misc = 0x000004f4,
980 .hal_reo1_ring_hp_addr_lsb = 0x000004f8,
981 .hal_reo1_ring_hp_addr_msb = 0x000004fc,
982 .hal_reo1_ring_producer_int_setup = 0x00000508,
983 .hal_reo1_ring_msi1_base_lsb = 0x0000052C,
984 .hal_reo1_ring_msi1_base_msb = 0x00000530,
985 .hal_reo1_ring_msi1_data = 0x00000534,
986 .hal_reo1_aging_thres_ix0 = 0x00000b08,
987 .hal_reo1_aging_thres_ix1 = 0x00000b0c,
988 .hal_reo1_aging_thres_ix2 = 0x00000b10,
989 .hal_reo1_aging_thres_ix3 = 0x00000b14,
990
991 /* REO Exception ring address */
992 .hal_reo2_sw0_ring_base = 0x000008a4,
993
994 /* REO Reinject ring address */
995 .hal_sw2reo_ring_base = 0x00000304,
996 .hal_sw2reo1_ring_base = 0x0000037c,
997
998 /* REO cmd ring address */
999 .hal_reo_cmd_ring_base = 0x0000028c,
1000
1001 /* REO status ring address */
1002 .hal_reo_status_ring_base = 0x00000a84,
1003
1004 /* CE base address */
1005 .hal_umac_ce0_src_reg_base = 0x01b80000,
1006 .hal_umac_ce0_dest_reg_base = 0x01b81000,
1007 .hal_umac_ce1_src_reg_base = 0x01b82000,
1008 .hal_umac_ce1_dest_reg_base = 0x01b83000,
1009
1010 .gcc_gcc_pcie_hot_rst = 0x1e38338,
1011 };
1012
1013 static const struct ath12k_hw_regs qcn9274_v2_regs = {
1014 /* SW2TCL(x) R0 ring configuration address */
1015 .hal_tcl1_ring_id = 0x00000908,
1016 .hal_tcl1_ring_misc = 0x00000910,
1017 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c,
1018 .hal_tcl1_ring_tp_addr_msb = 0x00000920,
1019 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930,
1020 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934,
1021 .hal_tcl1_ring_msi1_base_lsb = 0x00000948,
1022 .hal_tcl1_ring_msi1_base_msb = 0x0000094c,
1023 .hal_tcl1_ring_msi1_data = 0x00000950,
1024 .hal_tcl_ring_base_lsb = 0x00000b58,
1025 .hal_tcl1_ring_base_lsb = 0x00000900,
1026 .hal_tcl1_ring_base_msb = 0x00000904,
1027 .hal_tcl2_ring_base_lsb = 0x00000978,
1028
1029 /* TCL STATUS ring address */
1030 .hal_tcl_status_ring_base_lsb = 0x00000d38,
1031
1032 /* WBM idle link ring address */
1033 .hal_wbm_idle_ring_base_lsb = 0x00000d3c,
1034 .hal_wbm_idle_ring_misc_addr = 0x00000d4c,
1035 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240,
1036 .hal_wbm_r0_idle_list_size_addr = 0x00000244,
1037 .hal_wbm_scattered_ring_base_lsb = 0x00000250,
1038 .hal_wbm_scattered_ring_base_msb = 0x00000254,
1039 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260,
1040 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264,
1041 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270,
1042 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274,
1043 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000027c,
1044
1045 /* SW2WBM release ring address */
1046 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c,
1047 .hal_wbm_sw1_release_ring_base_lsb = 0x000003f4,
1048
1049 /* WBM2SW release ring address */
1050 .hal_wbm0_release_ring_base_lsb = 0x00000e08,
1051 .hal_wbm1_release_ring_base_lsb = 0x00000e80,
1052
1053 /* PCIe base address */
1054 .pcie_qserdes_sysclk_en_sel = 0x01e0c0a8,
1055 .pcie_pcs_osc_dtct_config_base = 0x01e0d45c,
1056
1057 /* PPE release ring address */
1058 .hal_ppe_rel_ring_base = 0x0000046c,
1059
1060 /* REO DEST ring address */
1061 .hal_reo2_ring_base = 0x00000578,
1062 .hal_reo1_misc_ctrl_addr = 0x00000b9c,
1063 .hal_reo1_sw_cookie_cfg0 = 0x0000006c,
1064 .hal_reo1_sw_cookie_cfg1 = 0x00000070,
1065 .hal_reo1_qdesc_lut_base0 = 0x00000074,
1066 .hal_reo1_qdesc_lut_base1 = 0x00000078,
1067 .hal_reo1_qdesc_addr = 0x0000007c,
1068 .hal_reo1_qdesc_max_peerid = 0x00000088,
1069 .hal_reo1_ring_base_lsb = 0x00000500,
1070 .hal_reo1_ring_base_msb = 0x00000504,
1071 .hal_reo1_ring_id = 0x00000508,
1072 .hal_reo1_ring_misc = 0x00000510,
1073 .hal_reo1_ring_hp_addr_lsb = 0x00000514,
1074 .hal_reo1_ring_hp_addr_msb = 0x00000518,
1075 .hal_reo1_ring_producer_int_setup = 0x00000524,
1076 .hal_reo1_ring_msi1_base_lsb = 0x00000548,
1077 .hal_reo1_ring_msi1_base_msb = 0x0000054C,
1078 .hal_reo1_ring_msi1_data = 0x00000550,
1079 .hal_reo1_aging_thres_ix0 = 0x00000B28,
1080 .hal_reo1_aging_thres_ix1 = 0x00000B2C,
1081 .hal_reo1_aging_thres_ix2 = 0x00000B30,
1082 .hal_reo1_aging_thres_ix3 = 0x00000B34,
1083
1084 /* REO Exception ring address */
1085 .hal_reo2_sw0_ring_base = 0x000008c0,
1086
1087 /* REO Reinject ring address */
1088 .hal_sw2reo_ring_base = 0x00000320,
1089 .hal_sw2reo1_ring_base = 0x00000398,
1090
1091 /* REO cmd ring address */
1092 .hal_reo_cmd_ring_base = 0x000002A8,
1093
1094 /* REO status ring address */
1095 .hal_reo_status_ring_base = 0x00000aa0,
1096
1097 /* CE base address */
1098 .hal_umac_ce0_src_reg_base = 0x01b80000,
1099 .hal_umac_ce0_dest_reg_base = 0x01b81000,
1100 .hal_umac_ce1_src_reg_base = 0x01b82000,
1101 .hal_umac_ce1_dest_reg_base = 0x01b83000,
1102
1103 .gcc_gcc_pcie_hot_rst = 0x1e38338,
1104 };
1105
1106 static const struct ath12k_hw_regs ipq5332_regs = {
1107 /* SW2TCL(x) R0 ring configuration address */
1108 .hal_tcl1_ring_id = 0x00000918,
1109 .hal_tcl1_ring_misc = 0x00000920,
1110 .hal_tcl1_ring_tp_addr_lsb = 0x0000092c,
1111 .hal_tcl1_ring_tp_addr_msb = 0x00000930,
1112 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000940,
1113 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000944,
1114 .hal_tcl1_ring_msi1_base_lsb = 0x00000958,
1115 .hal_tcl1_ring_msi1_base_msb = 0x0000095c,
1116 .hal_tcl1_ring_base_lsb = 0x00000910,
1117 .hal_tcl1_ring_base_msb = 0x00000914,
1118 .hal_tcl1_ring_msi1_data = 0x00000960,
1119 .hal_tcl2_ring_base_lsb = 0x00000988,
1120 .hal_tcl_ring_base_lsb = 0x00000b68,
1121
1122 /* TCL STATUS ring address */
1123 .hal_tcl_status_ring_base_lsb = 0x00000d48,
1124
1125 /* REO DEST ring address */
1126 .hal_reo2_ring_base = 0x00000578,
1127 .hal_reo1_misc_ctrl_addr = 0x00000b9c,
1128 .hal_reo1_sw_cookie_cfg0 = 0x0000006c,
1129 .hal_reo1_sw_cookie_cfg1 = 0x00000070,
1130 .hal_reo1_qdesc_lut_base0 = 0x00000074,
1131 .hal_reo1_qdesc_lut_base1 = 0x00000078,
1132 .hal_reo1_ring_base_lsb = 0x00000500,
1133 .hal_reo1_ring_base_msb = 0x00000504,
1134 .hal_reo1_ring_id = 0x00000508,
1135 .hal_reo1_ring_misc = 0x00000510,
1136 .hal_reo1_ring_hp_addr_lsb = 0x00000514,
1137 .hal_reo1_ring_hp_addr_msb = 0x00000518,
1138 .hal_reo1_ring_producer_int_setup = 0x00000524,
1139 .hal_reo1_ring_msi1_base_lsb = 0x00000548,
1140 .hal_reo1_ring_msi1_base_msb = 0x0000054C,
1141 .hal_reo1_ring_msi1_data = 0x00000550,
1142 .hal_reo1_aging_thres_ix0 = 0x00000B28,
1143 .hal_reo1_aging_thres_ix1 = 0x00000B2C,
1144 .hal_reo1_aging_thres_ix2 = 0x00000B30,
1145 .hal_reo1_aging_thres_ix3 = 0x00000B34,
1146
1147 /* REO Exception ring address */
1148 .hal_reo2_sw0_ring_base = 0x000008c0,
1149
1150 /* REO Reinject ring address */
1151 .hal_sw2reo_ring_base = 0x00000320,
1152 .hal_sw2reo1_ring_base = 0x00000398,
1153
1154 /* REO cmd ring address */
1155 .hal_reo_cmd_ring_base = 0x000002A8,
1156
1157 /* REO status ring address */
1158 .hal_reo_status_ring_base = 0x00000aa0,
1159
1160 /* WBM idle link ring address */
1161 .hal_wbm_idle_ring_base_lsb = 0x00000d3c,
1162 .hal_wbm_idle_ring_misc_addr = 0x00000d4c,
1163 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240,
1164 .hal_wbm_r0_idle_list_size_addr = 0x00000244,
1165 .hal_wbm_scattered_ring_base_lsb = 0x00000250,
1166 .hal_wbm_scattered_ring_base_msb = 0x00000254,
1167 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260,
1168 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264,
1169 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270,
1170 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274,
1171 .hal_wbm_scattered_desc_ptr_hp_addr = 0x0000027c,
1172
1173 /* SW2WBM release ring address */
1174 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c,
1175
1176 /* WBM2SW release ring address */
1177 .hal_wbm0_release_ring_base_lsb = 0x00000e08,
1178 .hal_wbm1_release_ring_base_lsb = 0x00000e80,
1179
1180 /* PPE release ring address */
1181 .hal_ppe_rel_ring_base = 0x0000046c,
1182
1183 /* CE address */
1184 .hal_umac_ce0_src_reg_base = 0x00740000 -
1185 HAL_IPQ5332_CE_WFSS_REG_BASE,
1186 .hal_umac_ce0_dest_reg_base = 0x00741000 -
1187 HAL_IPQ5332_CE_WFSS_REG_BASE,
1188 .hal_umac_ce1_src_reg_base = 0x00742000 -
1189 HAL_IPQ5332_CE_WFSS_REG_BASE,
1190 .hal_umac_ce1_dest_reg_base = 0x00743000 -
1191 HAL_IPQ5332_CE_WFSS_REG_BASE,
1192 };
1193
1194 static const struct ath12k_hw_regs wcn7850_regs = {
1195 /* SW2TCL(x) R0 ring configuration address */
1196 .hal_tcl1_ring_id = 0x00000908,
1197 .hal_tcl1_ring_misc = 0x00000910,
1198 .hal_tcl1_ring_tp_addr_lsb = 0x0000091c,
1199 .hal_tcl1_ring_tp_addr_msb = 0x00000920,
1200 .hal_tcl1_ring_consumer_int_setup_ix0 = 0x00000930,
1201 .hal_tcl1_ring_consumer_int_setup_ix1 = 0x00000934,
1202 .hal_tcl1_ring_msi1_base_lsb = 0x00000948,
1203 .hal_tcl1_ring_msi1_base_msb = 0x0000094c,
1204 .hal_tcl1_ring_msi1_data = 0x00000950,
1205 .hal_tcl_ring_base_lsb = 0x00000b58,
1206 .hal_tcl1_ring_base_lsb = 0x00000900,
1207 .hal_tcl1_ring_base_msb = 0x00000904,
1208 .hal_tcl2_ring_base_lsb = 0x00000978,
1209
1210 /* TCL STATUS ring address */
1211 .hal_tcl_status_ring_base_lsb = 0x00000d38,
1212
1213 .hal_wbm_idle_ring_base_lsb = 0x00000d3c,
1214 .hal_wbm_idle_ring_misc_addr = 0x00000d4c,
1215 .hal_wbm_r0_idle_list_cntl_addr = 0x00000240,
1216 .hal_wbm_r0_idle_list_size_addr = 0x00000244,
1217 .hal_wbm_scattered_ring_base_lsb = 0x00000250,
1218 .hal_wbm_scattered_ring_base_msb = 0x00000254,
1219 .hal_wbm_scattered_desc_head_info_ix0 = 0x00000260,
1220 .hal_wbm_scattered_desc_head_info_ix1 = 0x00000264,
1221 .hal_wbm_scattered_desc_tail_info_ix0 = 0x00000270,
1222 .hal_wbm_scattered_desc_tail_info_ix1 = 0x00000274,
1223 .hal_wbm_scattered_desc_ptr_hp_addr = 0x00000027c,
1224
1225 .hal_wbm_sw_release_ring_base_lsb = 0x0000037c,
1226 .hal_wbm_sw1_release_ring_base_lsb = 0x00000284,
1227 .hal_wbm0_release_ring_base_lsb = 0x00000e08,
1228 .hal_wbm1_release_ring_base_lsb = 0x00000e80,
1229
1230 /* PCIe base address */
1231 .pcie_qserdes_sysclk_en_sel = 0x01e0e0a8,
1232 .pcie_pcs_osc_dtct_config_base = 0x01e0f45c,
1233
1234 /* PPE release ring address */
1235 .hal_ppe_rel_ring_base = 0x0000043c,
1236
1237 /* REO DEST ring address */
1238 .hal_reo2_ring_base = 0x0000055c,
1239 .hal_reo1_misc_ctrl_addr = 0x00000b7c,
1240 .hal_reo1_sw_cookie_cfg0 = 0x00000050,
1241 .hal_reo1_sw_cookie_cfg1 = 0x00000054,
1242 .hal_reo1_qdesc_lut_base0 = 0x00000058,
1243 .hal_reo1_qdesc_lut_base1 = 0x0000005c,
1244 .hal_reo1_ring_base_lsb = 0x000004e4,
1245 .hal_reo1_ring_base_msb = 0x000004e8,
1246 .hal_reo1_ring_id = 0x000004ec,
1247 .hal_reo1_ring_misc = 0x000004f4,
1248 .hal_reo1_ring_hp_addr_lsb = 0x000004f8,
1249 .hal_reo1_ring_hp_addr_msb = 0x000004fc,
1250 .hal_reo1_ring_producer_int_setup = 0x00000508,
1251 .hal_reo1_ring_msi1_base_lsb = 0x0000052C,
1252 .hal_reo1_ring_msi1_base_msb = 0x00000530,
1253 .hal_reo1_ring_msi1_data = 0x00000534,
1254 .hal_reo1_aging_thres_ix0 = 0x00000b08,
1255 .hal_reo1_aging_thres_ix1 = 0x00000b0c,
1256 .hal_reo1_aging_thres_ix2 = 0x00000b10,
1257 .hal_reo1_aging_thres_ix3 = 0x00000b14,
1258
1259 /* REO Exception ring address */
1260 .hal_reo2_sw0_ring_base = 0x000008a4,
1261
1262 /* REO Reinject ring address */
1263 .hal_sw2reo_ring_base = 0x00000304,
1264 .hal_sw2reo1_ring_base = 0x0000037c,
1265
1266 /* REO cmd ring address */
1267 .hal_reo_cmd_ring_base = 0x0000028c,
1268
1269 /* REO status ring address */
1270 .hal_reo_status_ring_base = 0x00000a84,
1271
1272 /* CE base address */
1273 .hal_umac_ce0_src_reg_base = 0x01b80000,
1274 .hal_umac_ce0_dest_reg_base = 0x01b81000,
1275 .hal_umac_ce1_src_reg_base = 0x01b82000,
1276 .hal_umac_ce1_dest_reg_base = 0x01b83000,
1277
1278 .gcc_gcc_pcie_hot_rst = 0x1e40304,
1279 };
1280
1281 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_qcn9274 = {
1282 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM,
1283 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN |
1284 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN |
1285 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN |
1286 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN |
1287 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN,
1288 };
1289
1290 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_wcn7850 = {
1291 .rx_buf_rbm = HAL_RX_BUF_RBM_SW1_BM,
1292 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN |
1293 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN |
1294 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN |
1295 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN,
1296 };
1297
1298 static const struct ath12k_hw_hal_params ath12k_hw_hal_params_ipq5332 = {
1299 .rx_buf_rbm = HAL_RX_BUF_RBM_SW3_BM,
1300 .wbm2sw_cc_enable = HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW0_EN |
1301 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW1_EN |
1302 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW2_EN |
1303 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW3_EN |
1304 HAL_WBM_SW_COOKIE_CONV_CFG_WBM2SW4_EN,
1305 };
1306
1307 static const struct ce_ie_addr ath12k_ce_ie_addr_ipq5332 = {
1308 .ie1_reg_addr = CE_HOST_IE_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE,
1309 .ie2_reg_addr = CE_HOST_IE_2_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE,
1310 .ie3_reg_addr = CE_HOST_IE_3_ADDRESS - HAL_IPQ5332_CE_WFSS_REG_BASE,
1311 };
1312
1313 static const struct ce_remap ath12k_ce_remap_ipq5332 = {
1314 .base = HAL_IPQ5332_CE_WFSS_REG_BASE,
1315 .size = HAL_IPQ5332_CE_SIZE,
1316 };
1317
1318 static const struct ath12k_hw_params ath12k_hw_params[] = {
1319 {
1320 .name = "qcn9274 hw1.0",
1321 .hw_rev = ATH12K_HW_QCN9274_HW10,
1322 .fw = {
1323 .dir = "QCN9274/hw1.0",
1324 .board_size = 256 * 1024,
1325 .cal_offset = 128 * 1024,
1326 .m3_loader = ath12k_m3_fw_loader_driver,
1327 },
1328 .max_radios = 1,
1329 .single_pdev_only = false,
1330 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274,
1331 .internal_sleep_clock = false,
1332
1333 .hw_ops = &qcn9274_ops,
1334 .ring_mask = &ath12k_hw_ring_mask_qcn9274,
1335 .regs = &qcn9274_v1_regs,
1336
1337 .host_ce_config = ath12k_host_ce_config_qcn9274,
1338 .ce_count = 16,
1339 .target_ce_config = ath12k_target_ce_config_wlan_qcn9274,
1340 .target_ce_count = 12,
1341 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_qcn9274,
1342 .svc_to_ce_map_len = 18,
1343
1344 .hal_params = &ath12k_hw_hal_params_qcn9274,
1345
1346 .rxdma1_enable = false,
1347 .num_rxdma_per_pdev = 1,
1348 .num_rxdma_dst_ring = 0,
1349 .rx_mac_buf_ring = false,
1350 .vdev_start_delay = false,
1351
1352 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
1353 BIT(NL80211_IFTYPE_AP) |
1354 BIT(NL80211_IFTYPE_MESH_POINT) |
1355 BIT(NL80211_IFTYPE_AP_VLAN),
1356 .supports_monitor = false,
1357
1358 .idle_ps = false,
1359 .download_calib = true,
1360 .supports_suspend = false,
1361 .tcl_ring_retry = true,
1362 .reoq_lut_support = true,
1363 .supports_shadow_regs = false,
1364
1365 .num_tcl_banks = 48,
1366 .max_tx_ring = 4,
1367
1368 .mhi_config = &ath12k_mhi_config_qcn9274,
1369
1370 .wmi_init = ath12k_wmi_init_qcn9274,
1371
1372 .hal_ops = &hal_qcn9274_ops,
1373
1374 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01),
1375
1376 .rfkill_pin = 0,
1377 .rfkill_cfg = 0,
1378 .rfkill_on_level = 0,
1379
1380 .rddm_size = 0x600000,
1381
1382 .def_num_link = 0,
1383 .max_mlo_peer = 256,
1384
1385 .otp_board_id_register = QCN9274_QFPROM_RAW_RFA_PDET_ROW13_LSB,
1386
1387 .supports_sta_ps = false,
1388
1389 .acpi_guid = NULL,
1390 .supports_dynamic_smps_6ghz = true,
1391
1392 .iova_mask = 0,
1393
1394 .supports_aspm = false,
1395
1396 .ce_ie_addr = NULL,
1397 .ce_remap = NULL,
1398 .bdf_addr_offset = 0,
1399
1400 .current_cc_support = false,
1401
1402 .dp_primary_link_only = true,
1403 },
1404 {
1405 .name = "wcn7850 hw2.0",
1406 .hw_rev = ATH12K_HW_WCN7850_HW20,
1407
1408 .fw = {
1409 .dir = "WCN7850/hw2.0",
1410 .board_size = 256 * 1024,
1411 .cal_offset = 256 * 1024,
1412 .m3_loader = ath12k_m3_fw_loader_driver,
1413 },
1414
1415 .max_radios = 1,
1416 .single_pdev_only = true,
1417 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850,
1418 .internal_sleep_clock = true,
1419
1420 .hw_ops = &wcn7850_ops,
1421 .ring_mask = &ath12k_hw_ring_mask_wcn7850,
1422 .regs = &wcn7850_regs,
1423
1424 .host_ce_config = ath12k_host_ce_config_wcn7850,
1425 .ce_count = 9,
1426 .target_ce_config = ath12k_target_ce_config_wlan_wcn7850,
1427 .target_ce_count = 9,
1428 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_wcn7850,
1429 .svc_to_ce_map_len = 14,
1430
1431 .hal_params = &ath12k_hw_hal_params_wcn7850,
1432
1433 .rxdma1_enable = false,
1434 .num_rxdma_per_pdev = 2,
1435 .num_rxdma_dst_ring = 1,
1436 .rx_mac_buf_ring = true,
1437 .vdev_start_delay = true,
1438
1439 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
1440 BIT(NL80211_IFTYPE_AP) |
1441 BIT(NL80211_IFTYPE_P2P_DEVICE) |
1442 BIT(NL80211_IFTYPE_P2P_CLIENT) |
1443 BIT(NL80211_IFTYPE_P2P_GO),
1444 .supports_monitor = true,
1445
1446 .idle_ps = true,
1447 .download_calib = false,
1448 .supports_suspend = true,
1449 .tcl_ring_retry = false,
1450 .reoq_lut_support = false,
1451 .supports_shadow_regs = true,
1452
1453 .num_tcl_banks = 7,
1454 .max_tx_ring = 3,
1455
1456 .mhi_config = &ath12k_mhi_config_wcn7850,
1457
1458 .wmi_init = ath12k_wmi_init_wcn7850,
1459
1460 .hal_ops = &hal_wcn7850_ops,
1461
1462 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01) |
1463 BIT(CNSS_PCIE_PERST_NO_PULL_V01),
1464
1465 .rfkill_pin = 48,
1466 .rfkill_cfg = 0,
1467 .rfkill_on_level = 1,
1468
1469 .rddm_size = 0x780000,
1470
1471 .def_num_link = 2,
1472 .max_mlo_peer = 32,
1473
1474 .otp_board_id_register = 0,
1475
1476 .supports_sta_ps = true,
1477
1478 .acpi_guid = &wcn7850_uuid,
1479 .supports_dynamic_smps_6ghz = false,
1480
1481 .iova_mask = ATH12K_PCIE_MAX_PAYLOAD_SIZE - 1,
1482
1483 .supports_aspm = true,
1484
1485 .ce_ie_addr = NULL,
1486 .ce_remap = NULL,
1487 .bdf_addr_offset = 0,
1488
1489 .current_cc_support = true,
1490
1491 .dp_primary_link_only = false,
1492 },
1493 {
1494 .name = "qcn9274 hw2.0",
1495 .hw_rev = ATH12K_HW_QCN9274_HW20,
1496 .fw = {
1497 .dir = "QCN9274/hw2.0",
1498 .board_size = 256 * 1024,
1499 .cal_offset = 128 * 1024,
1500 .m3_loader = ath12k_m3_fw_loader_driver,
1501 },
1502 .max_radios = 2,
1503 .single_pdev_only = false,
1504 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274,
1505 .internal_sleep_clock = false,
1506
1507 .hw_ops = &qcn9274_ops,
1508 .ring_mask = &ath12k_hw_ring_mask_qcn9274,
1509 .regs = &qcn9274_v2_regs,
1510
1511 .host_ce_config = ath12k_host_ce_config_qcn9274,
1512 .ce_count = 16,
1513 .target_ce_config = ath12k_target_ce_config_wlan_qcn9274,
1514 .target_ce_count = 12,
1515 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_qcn9274,
1516 .svc_to_ce_map_len = 18,
1517
1518 .hal_params = &ath12k_hw_hal_params_qcn9274,
1519
1520 .rxdma1_enable = true,
1521 .num_rxdma_per_pdev = 1,
1522 .num_rxdma_dst_ring = 0,
1523 .rx_mac_buf_ring = false,
1524 .vdev_start_delay = false,
1525
1526 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
1527 BIT(NL80211_IFTYPE_AP) |
1528 BIT(NL80211_IFTYPE_MESH_POINT) |
1529 BIT(NL80211_IFTYPE_AP_VLAN),
1530 .supports_monitor = true,
1531
1532 .idle_ps = false,
1533 .download_calib = true,
1534 .supports_suspend = false,
1535 .tcl_ring_retry = true,
1536 .reoq_lut_support = true,
1537 .supports_shadow_regs = false,
1538
1539 .num_tcl_banks = 48,
1540 .max_tx_ring = 4,
1541
1542 .mhi_config = &ath12k_mhi_config_qcn9274,
1543
1544 .wmi_init = ath12k_wmi_init_qcn9274,
1545
1546 .hal_ops = &hal_qcn9274_ops,
1547
1548 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01),
1549
1550 .rfkill_pin = 0,
1551 .rfkill_cfg = 0,
1552 .rfkill_on_level = 0,
1553
1554 .rddm_size = 0x600000,
1555
1556 .def_num_link = 0,
1557 .max_mlo_peer = 256,
1558
1559 .otp_board_id_register = QCN9274_QFPROM_RAW_RFA_PDET_ROW13_LSB,
1560
1561 .supports_sta_ps = false,
1562
1563 .acpi_guid = NULL,
1564 .supports_dynamic_smps_6ghz = true,
1565
1566 .iova_mask = 0,
1567
1568 .supports_aspm = false,
1569
1570 .ce_ie_addr = NULL,
1571 .ce_remap = NULL,
1572 .bdf_addr_offset = 0,
1573
1574 .current_cc_support = false,
1575
1576 .dp_primary_link_only = true,
1577 },
1578 {
1579 .name = "ipq5332 hw1.0",
1580 .hw_rev = ATH12K_HW_IPQ5332_HW10,
1581 .fw = {
1582 .dir = "IPQ5332/hw1.0",
1583 .board_size = 256 * 1024,
1584 .cal_offset = 128 * 1024,
1585 .m3_loader = ath12k_m3_fw_loader_remoteproc,
1586 },
1587 .max_radios = 1,
1588 .single_pdev_only = false,
1589 .qmi_service_ins_id = ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ5332,
1590 .internal_sleep_clock = false,
1591
1592 .hw_ops = &qcn9274_ops,
1593 .regs = &ipq5332_regs,
1594 .ring_mask = &ath12k_hw_ring_mask_ipq5332,
1595
1596 .host_ce_config = ath12k_host_ce_config_ipq5332,
1597 .ce_count = 12,
1598 .target_ce_config = ath12k_target_ce_config_wlan_ipq5332,
1599 .target_ce_count = 12,
1600 .svc_to_ce_map = ath12k_target_service_to_ce_map_wlan_ipq5332,
1601 .svc_to_ce_map_len = 18,
1602
1603 .hal_params = &ath12k_hw_hal_params_ipq5332,
1604
1605 .rxdma1_enable = false,
1606 .num_rxdma_per_pdev = 1,
1607 .num_rxdma_dst_ring = 0,
1608 .rx_mac_buf_ring = false,
1609 .vdev_start_delay = false,
1610
1611 .interface_modes = BIT(NL80211_IFTYPE_STATION) |
1612 BIT(NL80211_IFTYPE_AP) |
1613 BIT(NL80211_IFTYPE_MESH_POINT),
1614 .supports_monitor = false,
1615
1616 .idle_ps = false,
1617 .download_calib = true,
1618 .supports_suspend = false,
1619 .tcl_ring_retry = true,
1620 .reoq_lut_support = false,
1621 .supports_shadow_regs = false,
1622
1623 .num_tcl_banks = 48,
1624 .max_tx_ring = 4,
1625
1626 .wmi_init = &ath12k_wmi_init_qcn9274,
1627
1628 .hal_ops = &hal_qcn9274_ops,
1629
1630 .qmi_cnss_feature_bitmap = BIT(CNSS_QDSS_CFG_MISS_V01),
1631
1632 .rfkill_pin = 0,
1633 .rfkill_cfg = 0,
1634 .rfkill_on_level = 0,
1635
1636 .rddm_size = 0,
1637
1638 .def_num_link = 0,
1639 .max_mlo_peer = 256,
1640
1641 .otp_board_id_register = 0,
1642
1643 .supports_sta_ps = false,
1644
1645 .acpi_guid = NULL,
1646 .supports_dynamic_smps_6ghz = false,
1647 .iova_mask = 0,
1648 .supports_aspm = false,
1649
1650 .ce_ie_addr = &ath12k_ce_ie_addr_ipq5332,
1651 .ce_remap = &ath12k_ce_remap_ipq5332,
1652 .bdf_addr_offset = 0xC00000,
1653
1654 .dp_primary_link_only = true,
1655 },
1656 };
1657
ath12k_hw_init(struct ath12k_base * ab)1658 int ath12k_hw_init(struct ath12k_base *ab)
1659 {
1660 const struct ath12k_hw_params *hw_params = NULL;
1661 int i;
1662
1663 for (i = 0; i < ARRAY_SIZE(ath12k_hw_params); i++) {
1664 hw_params = &ath12k_hw_params[i];
1665
1666 if (hw_params->hw_rev == ab->hw_rev)
1667 break;
1668 }
1669
1670 if (i == ARRAY_SIZE(ath12k_hw_params)) {
1671 ath12k_err(ab, "Unsupported hardware version: 0x%x\n", ab->hw_rev);
1672 return -EINVAL;
1673 }
1674
1675 ab->hw_params = hw_params;
1676
1677 ath12k_info(ab, "Hardware name: %s\n", ab->hw_params->name);
1678
1679 return 0;
1680 }
1681