1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2016-2018 Linaro Ltd. 4 * Copyright (C) 2014 Sony Mobile Communications AB 5 * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. 6 */ 7 #include <linux/clk.h> 8 #include <linux/delay.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/kernel.h> 12 #include <linux/mfd/syscon.h> 13 #include <linux/module.h> 14 #include <linux/of_address.h> 15 #include <linux/of_reserved_mem.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/soc/qcom/mdt_loader.h> 21 #include "qcom_common.h" 22 #include "qcom_pil_info.h" 23 #include "qcom_q6v5.h" 24 25 #define WCSS_CRASH_REASON 421 26 27 /* Q6SS Register Offsets */ 28 #define Q6SS_RESET_REG 0x014 29 #define Q6SS_GFMUX_CTL_REG 0x020 30 #define Q6SS_PWR_CTL_REG 0x030 31 #define Q6SS_MEM_PWR_CTL 0x0B0 32 #define Q6SS_STRAP_ACC 0x110 33 #define Q6SS_CGC_OVERRIDE 0x034 34 #define Q6SS_BCR_REG 0x6000 35 36 /* AXI Halt Register Offsets */ 37 #define AXI_HALTREQ_REG 0x0 38 #define AXI_HALTACK_REG 0x4 39 #define AXI_IDLE_REG 0x8 40 41 #define HALT_ACK_TIMEOUT_MS 100 42 43 /* Q6SS_RESET */ 44 #define Q6SS_STOP_CORE BIT(0) 45 #define Q6SS_CORE_ARES BIT(1) 46 #define Q6SS_BUS_ARES_ENABLE BIT(2) 47 48 /* Q6SS_BRC_RESET */ 49 #define Q6SS_BRC_BLK_ARES BIT(0) 50 51 /* Q6SS_GFMUX_CTL */ 52 #define Q6SS_CLK_ENABLE BIT(1) 53 #define Q6SS_SWITCH_CLK_SRC BIT(8) 54 55 /* Q6SS_PWR_CTL */ 56 #define Q6SS_L2DATA_STBY_N BIT(18) 57 #define Q6SS_SLP_RET_N BIT(19) 58 #define Q6SS_CLAMP_IO BIT(20) 59 #define QDSS_BHS_ON BIT(21) 60 #define QDSS_Q6_MEMORIES GENMASK(15, 0) 61 62 /* Q6SS parameters */ 63 #define Q6SS_LDO_BYP BIT(25) 64 #define Q6SS_BHS_ON BIT(24) 65 #define Q6SS_CLAMP_WL BIT(21) 66 #define Q6SS_CLAMP_QMC_MEM BIT(22) 67 #define HALT_CHECK_MAX_LOOPS 200 68 #define Q6SS_XO_CBCR GENMASK(5, 3) 69 #define Q6SS_SLEEP_CBCR GENMASK(5, 2) 70 71 /* Q6SS config/status registers */ 72 #define TCSR_GLOBAL_CFG0 0x0 73 #define TCSR_GLOBAL_CFG1 0x4 74 #define SSCAON_CONFIG 0x8 75 #define SSCAON_STATUS 0xc 76 #define Q6SS_BHS_STATUS 0x78 77 #define Q6SS_RST_EVB 0x10 78 79 #define BHS_EN_REST_ACK BIT(0) 80 #define SSCAON_ENABLE BIT(13) 81 #define SSCAON_BUS_EN BIT(15) 82 #define SSCAON_BUS_MUX_MASK GENMASK(18, 16) 83 84 #define MEM_BANKS 19 85 #define TCSR_WCSS_CLK_MASK 0x1F 86 #define TCSR_WCSS_CLK_ENABLE 0x14 87 88 #define MAX_HALT_REG 4 89 enum { 90 WCSS_IPQ8074, 91 WCSS_QCS404, 92 }; 93 94 struct wcss_data { 95 const char *firmware_name; 96 unsigned int crash_reason_smem; 97 u32 version; 98 bool aon_reset_required; 99 const char *ssr_name; 100 const char *sysmon_name; 101 int ssctl_id; 102 const struct rproc_ops *ops; 103 bool requires_force_stop; 104 }; 105 106 struct q6v5_wcss { 107 struct device *dev; 108 109 void __iomem *reg_base; 110 void __iomem *rmb_base; 111 112 struct regmap *halt_map; 113 u32 halt_q6; 114 u32 halt_wcss; 115 u32 halt_nc; 116 117 struct clk *xo; 118 struct clk *ahbfabric_cbcr_clk; 119 struct clk *gcc_abhs_cbcr; 120 struct clk *gcc_axim_cbcr; 121 struct clk *lcc_csr_cbcr; 122 struct clk *ahbs_cbcr; 123 struct clk *tcm_slave_cbcr; 124 struct clk *qdsp6ss_abhm_cbcr; 125 struct clk *qdsp6ss_sleep_cbcr; 126 struct clk *qdsp6ss_axim_cbcr; 127 struct clk *qdsp6ss_xo_cbcr; 128 struct clk *qdsp6ss_core_gfmux; 129 struct clk *lcc_bcr_sleep; 130 struct regulator *cx_supply; 131 struct qcom_sysmon *sysmon; 132 133 struct reset_control *wcss_aon_reset; 134 struct reset_control *wcss_reset; 135 struct reset_control *wcss_q6_reset; 136 137 struct qcom_q6v5 q6v5; 138 139 phys_addr_t mem_phys; 140 phys_addr_t mem_reloc; 141 void *mem_region; 142 size_t mem_size; 143 144 unsigned int crash_reason_smem; 145 u32 version; 146 bool requires_force_stop; 147 148 struct qcom_rproc_glink glink_subdev; 149 struct qcom_rproc_pdm pdm_subdev; 150 struct qcom_rproc_ssr ssr_subdev; 151 }; 152 153 static int q6v5_wcss_reset(struct q6v5_wcss *wcss) 154 { 155 int ret; 156 u32 val; 157 int i; 158 159 /* Assert resets, stop core */ 160 val = readl(wcss->reg_base + Q6SS_RESET_REG); 161 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; 162 writel(val, wcss->reg_base + Q6SS_RESET_REG); 163 164 /* BHS require xo cbcr to be enabled */ 165 val = readl(wcss->reg_base + Q6SS_XO_CBCR); 166 val |= 0x1; 167 writel(val, wcss->reg_base + Q6SS_XO_CBCR); 168 169 /* Read CLKOFF bit to go low indicating CLK is enabled */ 170 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, 171 val, !(val & BIT(31)), 1, 172 HALT_CHECK_MAX_LOOPS); 173 if (ret) { 174 dev_err(wcss->dev, 175 "xo cbcr enabling timed out (rc:%d)\n", ret); 176 return ret; 177 } 178 /* Enable power block headswitch and wait for it to stabilize */ 179 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); 180 val |= Q6SS_BHS_ON; 181 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 182 udelay(1); 183 184 /* Put LDO in bypass mode */ 185 val |= Q6SS_LDO_BYP; 186 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 187 188 /* Deassert Q6 compiler memory clamp */ 189 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); 190 val &= ~Q6SS_CLAMP_QMC_MEM; 191 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 192 193 /* Deassert memory peripheral sleep and L2 memory standby */ 194 val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N; 195 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 196 197 /* Turn on L1, L2, ETB and JU memories 1 at a time */ 198 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); 199 for (i = MEM_BANKS; i >= 0; i--) { 200 val |= BIT(i); 201 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); 202 /* 203 * Read back value to ensure the write is done then 204 * wait for 1us for both memory peripheral and data 205 * array to turn on. 206 */ 207 val |= readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); 208 udelay(1); 209 } 210 /* Remove word line clamp */ 211 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); 212 val &= ~Q6SS_CLAMP_WL; 213 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 214 215 /* Remove IO clamp */ 216 val &= ~Q6SS_CLAMP_IO; 217 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 218 219 /* Bring core out of reset */ 220 val = readl(wcss->reg_base + Q6SS_RESET_REG); 221 val &= ~Q6SS_CORE_ARES; 222 writel(val, wcss->reg_base + Q6SS_RESET_REG); 223 224 /* Turn on core clock */ 225 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); 226 val |= Q6SS_CLK_ENABLE; 227 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); 228 229 /* Start core execution */ 230 val = readl(wcss->reg_base + Q6SS_RESET_REG); 231 val &= ~Q6SS_STOP_CORE; 232 writel(val, wcss->reg_base + Q6SS_RESET_REG); 233 234 return 0; 235 } 236 237 static int q6v5_wcss_start(struct rproc *rproc) 238 { 239 struct q6v5_wcss *wcss = rproc->priv; 240 int ret; 241 242 qcom_q6v5_prepare(&wcss->q6v5); 243 244 /* Release Q6 and WCSS reset */ 245 ret = reset_control_deassert(wcss->wcss_reset); 246 if (ret) { 247 dev_err(wcss->dev, "wcss_reset failed\n"); 248 return ret; 249 } 250 251 ret = reset_control_deassert(wcss->wcss_q6_reset); 252 if (ret) { 253 dev_err(wcss->dev, "wcss_q6_reset failed\n"); 254 goto wcss_reset; 255 } 256 257 /* Lithium configuration - clock gating and bus arbitration */ 258 ret = regmap_update_bits(wcss->halt_map, 259 wcss->halt_nc + TCSR_GLOBAL_CFG0, 260 TCSR_WCSS_CLK_MASK, 261 TCSR_WCSS_CLK_ENABLE); 262 if (ret) 263 goto wcss_q6_reset; 264 265 ret = regmap_update_bits(wcss->halt_map, 266 wcss->halt_nc + TCSR_GLOBAL_CFG1, 267 1, 0); 268 if (ret) 269 goto wcss_q6_reset; 270 271 /* Write bootaddr to EVB so that Q6WCSS will jump there after reset */ 272 writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); 273 274 ret = q6v5_wcss_reset(wcss); 275 if (ret) 276 goto wcss_q6_reset; 277 278 ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); 279 if (ret == -ETIMEDOUT) 280 dev_err(wcss->dev, "start timed out\n"); 281 282 return ret; 283 284 wcss_q6_reset: 285 reset_control_assert(wcss->wcss_q6_reset); 286 287 wcss_reset: 288 reset_control_assert(wcss->wcss_reset); 289 290 return ret; 291 } 292 293 static int q6v5_wcss_qcs404_power_on(struct q6v5_wcss *wcss) 294 { 295 unsigned long val; 296 int ret, idx; 297 298 /* Toggle the restart */ 299 reset_control_assert(wcss->wcss_reset); 300 usleep_range(200, 300); 301 reset_control_deassert(wcss->wcss_reset); 302 usleep_range(200, 300); 303 304 /* Enable GCC_WDSP_Q6SS_AHBS_CBCR clock */ 305 ret = clk_prepare_enable(wcss->gcc_abhs_cbcr); 306 if (ret) 307 return ret; 308 309 /* Remove reset to the WCNSS QDSP6SS */ 310 reset_control_deassert(wcss->wcss_q6_reset); 311 312 /* Enable Q6SSTOP_AHBFABRIC_CBCR clock */ 313 ret = clk_prepare_enable(wcss->ahbfabric_cbcr_clk); 314 if (ret) 315 goto disable_gcc_abhs_cbcr_clk; 316 317 /* Enable the LCCCSR CBC clock, Q6SSTOP_Q6SSTOP_LCC_CSR_CBCR clock */ 318 ret = clk_prepare_enable(wcss->lcc_csr_cbcr); 319 if (ret) 320 goto disable_ahbfabric_cbcr_clk; 321 322 /* Enable the Q6AHBS CBC, Q6SSTOP_Q6SS_AHBS_CBCR clock */ 323 ret = clk_prepare_enable(wcss->ahbs_cbcr); 324 if (ret) 325 goto disable_csr_cbcr_clk; 326 327 /* Enable the TCM slave CBC, Q6SSTOP_Q6SS_TCM_SLAVE_CBCR clock */ 328 ret = clk_prepare_enable(wcss->tcm_slave_cbcr); 329 if (ret) 330 goto disable_ahbs_cbcr_clk; 331 332 /* Enable the Q6SS AHB master CBC, Q6SSTOP_Q6SS_AHBM_CBCR clock */ 333 ret = clk_prepare_enable(wcss->qdsp6ss_abhm_cbcr); 334 if (ret) 335 goto disable_tcm_slave_cbcr_clk; 336 337 /* Enable the Q6SS AXI master CBC, Q6SSTOP_Q6SS_AXIM_CBCR clock */ 338 ret = clk_prepare_enable(wcss->qdsp6ss_axim_cbcr); 339 if (ret) 340 goto disable_abhm_cbcr_clk; 341 342 /* Enable the Q6SS XO CBC */ 343 val = readl(wcss->reg_base + Q6SS_XO_CBCR); 344 val |= BIT(0); 345 writel(val, wcss->reg_base + Q6SS_XO_CBCR); 346 /* Read CLKOFF bit to go low indicating CLK is enabled */ 347 ret = readl_poll_timeout(wcss->reg_base + Q6SS_XO_CBCR, 348 val, !(val & BIT(31)), 1, 349 HALT_CHECK_MAX_LOOPS); 350 if (ret) { 351 dev_err(wcss->dev, 352 "xo cbcr enabling timed out (rc:%d)\n", ret); 353 goto disable_xo_cbcr_clk; 354 } 355 356 writel(0, wcss->reg_base + Q6SS_CGC_OVERRIDE); 357 358 /* Enable QDSP6 sleep clock clock */ 359 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); 360 val |= BIT(0); 361 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); 362 363 /* Enable the Enable the Q6 AXI clock, GCC_WDSP_Q6SS_AXIM_CBCR*/ 364 ret = clk_prepare_enable(wcss->gcc_axim_cbcr); 365 if (ret) 366 goto disable_sleep_cbcr_clk; 367 368 /* Assert resets, stop core */ 369 val = readl(wcss->reg_base + Q6SS_RESET_REG); 370 val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE; 371 writel(val, wcss->reg_base + Q6SS_RESET_REG); 372 373 /* Program the QDSP6SS PWR_CTL register */ 374 writel(0x01700000, wcss->reg_base + Q6SS_PWR_CTL_REG); 375 376 writel(0x03700000, wcss->reg_base + Q6SS_PWR_CTL_REG); 377 378 writel(0x03300000, wcss->reg_base + Q6SS_PWR_CTL_REG); 379 380 writel(0x033C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); 381 382 /* 383 * Enable memories by turning on the QDSP6 memory foot/head switch, one 384 * bank at a time to avoid in-rush current 385 */ 386 for (idx = 28; idx >= 0; idx--) { 387 writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) | 388 (1 << idx)), wcss->reg_base + Q6SS_MEM_PWR_CTL); 389 } 390 391 writel(0x031C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); 392 writel(0x030C0000, wcss->reg_base + Q6SS_PWR_CTL_REG); 393 394 val = readl(wcss->reg_base + Q6SS_RESET_REG); 395 val &= ~Q6SS_CORE_ARES; 396 writel(val, wcss->reg_base + Q6SS_RESET_REG); 397 398 /* Enable the Q6 core clock at the GFM, Q6SSTOP_QDSP6SS_GFMUX_CTL */ 399 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); 400 val |= Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC; 401 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); 402 403 /* Enable sleep clock branch needed for BCR circuit */ 404 ret = clk_prepare_enable(wcss->lcc_bcr_sleep); 405 if (ret) 406 goto disable_core_gfmux_clk; 407 408 return 0; 409 410 disable_core_gfmux_clk: 411 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); 412 val &= ~(Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC); 413 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); 414 clk_disable_unprepare(wcss->gcc_axim_cbcr); 415 disable_sleep_cbcr_clk: 416 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); 417 val &= ~Q6SS_CLK_ENABLE; 418 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); 419 disable_xo_cbcr_clk: 420 val = readl(wcss->reg_base + Q6SS_XO_CBCR); 421 val &= ~Q6SS_CLK_ENABLE; 422 writel(val, wcss->reg_base + Q6SS_XO_CBCR); 423 clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr); 424 disable_abhm_cbcr_clk: 425 clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr); 426 disable_tcm_slave_cbcr_clk: 427 clk_disable_unprepare(wcss->tcm_slave_cbcr); 428 disable_ahbs_cbcr_clk: 429 clk_disable_unprepare(wcss->ahbs_cbcr); 430 disable_csr_cbcr_clk: 431 clk_disable_unprepare(wcss->lcc_csr_cbcr); 432 disable_ahbfabric_cbcr_clk: 433 clk_disable_unprepare(wcss->ahbfabric_cbcr_clk); 434 disable_gcc_abhs_cbcr_clk: 435 clk_disable_unprepare(wcss->gcc_abhs_cbcr); 436 437 return ret; 438 } 439 440 static inline int q6v5_wcss_qcs404_reset(struct q6v5_wcss *wcss) 441 { 442 unsigned long val; 443 444 writel(0x80800000, wcss->reg_base + Q6SS_STRAP_ACC); 445 446 /* Start core execution */ 447 val = readl(wcss->reg_base + Q6SS_RESET_REG); 448 val &= ~Q6SS_STOP_CORE; 449 writel(val, wcss->reg_base + Q6SS_RESET_REG); 450 451 return 0; 452 } 453 454 static int q6v5_qcs404_wcss_start(struct rproc *rproc) 455 { 456 struct q6v5_wcss *wcss = rproc->priv; 457 int ret; 458 459 ret = clk_prepare_enable(wcss->xo); 460 if (ret) 461 return ret; 462 463 ret = regulator_enable(wcss->cx_supply); 464 if (ret) 465 goto disable_xo_clk; 466 467 qcom_q6v5_prepare(&wcss->q6v5); 468 469 ret = q6v5_wcss_qcs404_power_on(wcss); 470 if (ret) { 471 dev_err(wcss->dev, "wcss clk_enable failed\n"); 472 goto disable_cx_supply; 473 } 474 475 writel(rproc->bootaddr >> 4, wcss->reg_base + Q6SS_RST_EVB); 476 477 q6v5_wcss_qcs404_reset(wcss); 478 479 ret = qcom_q6v5_wait_for_start(&wcss->q6v5, 5 * HZ); 480 if (ret == -ETIMEDOUT) { 481 dev_err(wcss->dev, "start timed out\n"); 482 goto disable_cx_supply; 483 } 484 485 return 0; 486 487 disable_cx_supply: 488 regulator_disable(wcss->cx_supply); 489 disable_xo_clk: 490 clk_disable_unprepare(wcss->xo); 491 492 return ret; 493 } 494 495 static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss, 496 struct regmap *halt_map, 497 u32 offset) 498 { 499 unsigned long timeout; 500 unsigned int val; 501 int ret; 502 503 /* Check if we're already idle */ 504 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); 505 if (!ret && val) 506 return; 507 508 /* Assert halt request */ 509 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1); 510 511 /* Wait for halt */ 512 timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS); 513 for (;;) { 514 ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val); 515 if (ret || val || time_after(jiffies, timeout)) 516 break; 517 518 msleep(1); 519 } 520 521 ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val); 522 if (ret || !val) 523 dev_err(wcss->dev, "port failed halt\n"); 524 525 /* Clear halt request (port will remain halted until reset) */ 526 regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0); 527 } 528 529 static int q6v5_qcs404_wcss_shutdown(struct q6v5_wcss *wcss) 530 { 531 unsigned long val; 532 int ret; 533 534 q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss); 535 536 /* assert clamps to avoid MX current inrush */ 537 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); 538 val |= (Q6SS_CLAMP_IO | Q6SS_CLAMP_WL | Q6SS_CLAMP_QMC_MEM); 539 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 540 541 /* Disable memories by turning off memory foot/headswitch */ 542 writel((readl(wcss->reg_base + Q6SS_MEM_PWR_CTL) & 543 ~QDSS_Q6_MEMORIES), 544 wcss->reg_base + Q6SS_MEM_PWR_CTL); 545 546 /* Clear the BHS_ON bit */ 547 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); 548 val &= ~Q6SS_BHS_ON; 549 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 550 551 clk_disable_unprepare(wcss->ahbfabric_cbcr_clk); 552 clk_disable_unprepare(wcss->lcc_csr_cbcr); 553 clk_disable_unprepare(wcss->tcm_slave_cbcr); 554 clk_disable_unprepare(wcss->qdsp6ss_abhm_cbcr); 555 clk_disable_unprepare(wcss->qdsp6ss_axim_cbcr); 556 557 val = readl(wcss->reg_base + Q6SS_SLEEP_CBCR); 558 val &= ~BIT(0); 559 writel(val, wcss->reg_base + Q6SS_SLEEP_CBCR); 560 561 val = readl(wcss->reg_base + Q6SS_XO_CBCR); 562 val &= ~BIT(0); 563 writel(val, wcss->reg_base + Q6SS_XO_CBCR); 564 565 clk_disable_unprepare(wcss->ahbs_cbcr); 566 clk_disable_unprepare(wcss->lcc_bcr_sleep); 567 568 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); 569 val &= ~(Q6SS_CLK_ENABLE | Q6SS_SWITCH_CLK_SRC); 570 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); 571 572 clk_disable_unprepare(wcss->gcc_abhs_cbcr); 573 574 ret = reset_control_assert(wcss->wcss_reset); 575 if (ret) { 576 dev_err(wcss->dev, "wcss_reset failed\n"); 577 return ret; 578 } 579 usleep_range(200, 300); 580 581 ret = reset_control_deassert(wcss->wcss_reset); 582 if (ret) { 583 dev_err(wcss->dev, "wcss_reset failed\n"); 584 return ret; 585 } 586 usleep_range(200, 300); 587 588 clk_disable_unprepare(wcss->gcc_axim_cbcr); 589 590 return 0; 591 } 592 593 static int q6v5_wcss_powerdown(struct q6v5_wcss *wcss) 594 { 595 int ret; 596 u32 val; 597 598 /* 1 - Assert WCSS/Q6 HALTREQ */ 599 q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_wcss); 600 601 /* 2 - Enable WCSSAON_CONFIG */ 602 val = readl(wcss->rmb_base + SSCAON_CONFIG); 603 val |= SSCAON_ENABLE; 604 writel(val, wcss->rmb_base + SSCAON_CONFIG); 605 606 /* 3 - Set SSCAON_CONFIG */ 607 val |= SSCAON_BUS_EN; 608 val &= ~SSCAON_BUS_MUX_MASK; 609 writel(val, wcss->rmb_base + SSCAON_CONFIG); 610 611 /* 4 - SSCAON_CONFIG 1 */ 612 val |= BIT(1); 613 writel(val, wcss->rmb_base + SSCAON_CONFIG); 614 615 /* 5 - wait for SSCAON_STATUS */ 616 ret = readl_poll_timeout(wcss->rmb_base + SSCAON_STATUS, 617 val, (val & 0xffff) == 0x400, 1000, 618 HALT_CHECK_MAX_LOOPS); 619 if (ret) { 620 dev_err(wcss->dev, 621 "can't get SSCAON_STATUS rc:%d)\n", ret); 622 return ret; 623 } 624 625 /* 6 - De-assert WCSS_AON reset */ 626 reset_control_assert(wcss->wcss_aon_reset); 627 628 /* 7 - Disable WCSSAON_CONFIG 13 */ 629 val = readl(wcss->rmb_base + SSCAON_CONFIG); 630 val &= ~SSCAON_ENABLE; 631 writel(val, wcss->rmb_base + SSCAON_CONFIG); 632 633 /* 8 - De-assert WCSS/Q6 HALTREQ */ 634 reset_control_assert(wcss->wcss_reset); 635 636 return 0; 637 } 638 639 static int q6v5_q6_powerdown(struct q6v5_wcss *wcss) 640 { 641 int ret; 642 u32 val; 643 int i; 644 645 /* 1 - Halt Q6 bus interface */ 646 q6v5_wcss_halt_axi_port(wcss, wcss->halt_map, wcss->halt_q6); 647 648 /* 2 - Disable Q6 Core clock */ 649 val = readl(wcss->reg_base + Q6SS_GFMUX_CTL_REG); 650 val &= ~Q6SS_CLK_ENABLE; 651 writel(val, wcss->reg_base + Q6SS_GFMUX_CTL_REG); 652 653 /* 3 - Clamp I/O */ 654 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); 655 val |= Q6SS_CLAMP_IO; 656 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 657 658 /* 4 - Clamp WL */ 659 val |= QDSS_BHS_ON; 660 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 661 662 /* 5 - Clear Erase standby */ 663 val &= ~Q6SS_L2DATA_STBY_N; 664 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 665 666 /* 6 - Clear Sleep RTN */ 667 val &= ~Q6SS_SLP_RET_N; 668 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 669 670 /* 7 - turn off Q6 memory foot/head switch one bank at a time */ 671 for (i = 0; i < 20; i++) { 672 val = readl(wcss->reg_base + Q6SS_MEM_PWR_CTL); 673 val &= ~BIT(i); 674 writel(val, wcss->reg_base + Q6SS_MEM_PWR_CTL); 675 mdelay(1); 676 } 677 678 /* 8 - Assert QMC memory RTN */ 679 val = readl(wcss->reg_base + Q6SS_PWR_CTL_REG); 680 val |= Q6SS_CLAMP_QMC_MEM; 681 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 682 683 /* 9 - Turn off BHS */ 684 val &= ~Q6SS_BHS_ON; 685 writel(val, wcss->reg_base + Q6SS_PWR_CTL_REG); 686 udelay(1); 687 688 /* 10 - Wait till BHS Reset is done */ 689 ret = readl_poll_timeout(wcss->reg_base + Q6SS_BHS_STATUS, 690 val, !(val & BHS_EN_REST_ACK), 1000, 691 HALT_CHECK_MAX_LOOPS); 692 if (ret) { 693 dev_err(wcss->dev, "BHS_STATUS not OFF (rc:%d)\n", ret); 694 return ret; 695 } 696 697 /* 11 - Assert WCSS reset */ 698 reset_control_assert(wcss->wcss_reset); 699 700 /* 12 - Assert Q6 reset */ 701 reset_control_assert(wcss->wcss_q6_reset); 702 703 return 0; 704 } 705 706 static int q6v5_wcss_stop(struct rproc *rproc) 707 { 708 struct q6v5_wcss *wcss = rproc->priv; 709 int ret; 710 711 /* WCSS powerdown */ 712 if (wcss->requires_force_stop) { 713 ret = qcom_q6v5_request_stop(&wcss->q6v5, NULL); 714 if (ret == -ETIMEDOUT) { 715 dev_err(wcss->dev, "timed out on wait\n"); 716 return ret; 717 } 718 } 719 720 if (wcss->version == WCSS_QCS404) { 721 ret = q6v5_qcs404_wcss_shutdown(wcss); 722 if (ret) 723 return ret; 724 } else { 725 ret = q6v5_wcss_powerdown(wcss); 726 if (ret) 727 return ret; 728 729 /* Q6 Power down */ 730 ret = q6v5_q6_powerdown(wcss); 731 if (ret) 732 return ret; 733 } 734 735 qcom_q6v5_unprepare(&wcss->q6v5); 736 737 return 0; 738 } 739 740 static void *q6v5_wcss_da_to_va(struct rproc *rproc, u64 da, size_t len, bool *is_iomem) 741 { 742 struct q6v5_wcss *wcss = rproc->priv; 743 int offset; 744 745 offset = da - wcss->mem_reloc; 746 if (offset < 0 || offset + len > wcss->mem_size) 747 return NULL; 748 749 return wcss->mem_region + offset; 750 } 751 752 static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) 753 { 754 struct q6v5_wcss *wcss = rproc->priv; 755 int ret; 756 757 ret = qcom_mdt_load_no_init(wcss->dev, fw, rproc->firmware, 758 wcss->mem_region, wcss->mem_phys, 759 wcss->mem_size, &wcss->mem_reloc); 760 if (ret) 761 return ret; 762 763 qcom_pil_info_store("wcnss", wcss->mem_phys, wcss->mem_size); 764 765 return ret; 766 } 767 768 static const struct rproc_ops q6v5_wcss_ipq8074_ops = { 769 .start = q6v5_wcss_start, 770 .stop = q6v5_wcss_stop, 771 .da_to_va = q6v5_wcss_da_to_va, 772 .load = q6v5_wcss_load, 773 .get_boot_addr = rproc_elf_get_boot_addr, 774 }; 775 776 static const struct rproc_ops q6v5_wcss_qcs404_ops = { 777 .start = q6v5_qcs404_wcss_start, 778 .stop = q6v5_wcss_stop, 779 .da_to_va = q6v5_wcss_da_to_va, 780 .load = q6v5_wcss_load, 781 .get_boot_addr = rproc_elf_get_boot_addr, 782 .parse_fw = qcom_register_dump_segments, 783 }; 784 785 static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss, 786 const struct wcss_data *desc) 787 { 788 struct device *dev = wcss->dev; 789 790 if (desc->aon_reset_required) { 791 wcss->wcss_aon_reset = devm_reset_control_get_exclusive(dev, "wcss_aon_reset"); 792 if (IS_ERR(wcss->wcss_aon_reset)) { 793 dev_err(wcss->dev, "fail to acquire wcss_aon_reset\n"); 794 return PTR_ERR(wcss->wcss_aon_reset); 795 } 796 } 797 798 wcss->wcss_reset = devm_reset_control_get_exclusive(dev, "wcss_reset"); 799 if (IS_ERR(wcss->wcss_reset)) { 800 dev_err(wcss->dev, "unable to acquire wcss_reset\n"); 801 return PTR_ERR(wcss->wcss_reset); 802 } 803 804 wcss->wcss_q6_reset = devm_reset_control_get_exclusive(dev, "wcss_q6_reset"); 805 if (IS_ERR(wcss->wcss_q6_reset)) { 806 dev_err(wcss->dev, "unable to acquire wcss_q6_reset\n"); 807 return PTR_ERR(wcss->wcss_q6_reset); 808 } 809 810 return 0; 811 } 812 813 static int q6v5_wcss_init_mmio(struct q6v5_wcss *wcss, 814 struct platform_device *pdev) 815 { 816 unsigned int halt_reg[MAX_HALT_REG] = {0}; 817 struct device_node *syscon; 818 struct resource *res; 819 int ret; 820 821 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6"); 822 if (!res) 823 return -EINVAL; 824 825 wcss->reg_base = devm_ioremap(&pdev->dev, res->start, 826 resource_size(res)); 827 if (!wcss->reg_base) 828 return -ENOMEM; 829 830 if (wcss->version == WCSS_IPQ8074) { 831 wcss->rmb_base = devm_platform_ioremap_resource_byname(pdev, "rmb"); 832 if (IS_ERR(wcss->rmb_base)) 833 return PTR_ERR(wcss->rmb_base); 834 } 835 836 syscon = of_parse_phandle(pdev->dev.of_node, 837 "qcom,halt-regs", 0); 838 if (!syscon) { 839 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); 840 return -EINVAL; 841 } 842 843 wcss->halt_map = syscon_node_to_regmap(syscon); 844 of_node_put(syscon); 845 if (IS_ERR(wcss->halt_map)) 846 return PTR_ERR(wcss->halt_map); 847 848 ret = of_property_read_variable_u32_array(pdev->dev.of_node, 849 "qcom,halt-regs", 850 halt_reg, 0, 851 MAX_HALT_REG); 852 if (ret < 0) { 853 dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n"); 854 return -EINVAL; 855 } 856 857 wcss->halt_q6 = halt_reg[1]; 858 wcss->halt_wcss = halt_reg[2]; 859 wcss->halt_nc = halt_reg[3]; 860 861 return 0; 862 } 863 864 static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss) 865 { 866 struct device *dev = wcss->dev; 867 struct resource res; 868 int ret; 869 870 ret = of_reserved_mem_region_to_resource(dev->of_node, 0, &res); 871 if (ret) { 872 dev_err(dev, "unable to acquire memory-region\n"); 873 return ret; 874 } 875 876 wcss->mem_phys = res.start; 877 wcss->mem_reloc = res.start; 878 wcss->mem_size = resource_size(&res); 879 wcss->mem_region = devm_ioremap_resource_wc(dev, &res); 880 if (IS_ERR(wcss->mem_region)) { 881 dev_err(dev, "unable to map memory region: %pR\n", &res); 882 return PTR_ERR(wcss->mem_region); 883 } 884 885 return 0; 886 } 887 888 static int q6v5_wcss_init_clock(struct q6v5_wcss *wcss) 889 { 890 wcss->xo = devm_clk_get(wcss->dev, "xo"); 891 if (IS_ERR(wcss->xo)) 892 return dev_err_probe(wcss->dev, PTR_ERR(wcss->xo), 893 "failed to get xo clock"); 894 895 wcss->gcc_abhs_cbcr = devm_clk_get(wcss->dev, "gcc_abhs_cbcr"); 896 if (IS_ERR(wcss->gcc_abhs_cbcr)) 897 return dev_err_probe(wcss->dev, PTR_ERR(wcss->gcc_abhs_cbcr), 898 "failed to get gcc abhs clock"); 899 900 wcss->gcc_axim_cbcr = devm_clk_get(wcss->dev, "gcc_axim_cbcr"); 901 if (IS_ERR(wcss->gcc_axim_cbcr)) 902 return dev_err_probe(wcss->dev, PTR_ERR(wcss->gcc_axim_cbcr), 903 "failed to get gcc axim clock\n"); 904 905 wcss->ahbfabric_cbcr_clk = devm_clk_get(wcss->dev, 906 "lcc_ahbfabric_cbc"); 907 if (IS_ERR(wcss->ahbfabric_cbcr_clk)) 908 return dev_err_probe(wcss->dev, PTR_ERR(wcss->ahbfabric_cbcr_clk), 909 "failed to get ahbfabric clock\n"); 910 911 wcss->lcc_csr_cbcr = devm_clk_get(wcss->dev, "tcsr_lcc_cbc"); 912 if (IS_ERR(wcss->lcc_csr_cbcr)) 913 return dev_err_probe(wcss->dev, PTR_ERR(wcss->lcc_csr_cbcr), 914 "failed to get csr cbcr clk\n"); 915 916 wcss->ahbs_cbcr = devm_clk_get(wcss->dev, 917 "lcc_abhs_cbc"); 918 if (IS_ERR(wcss->ahbs_cbcr)) 919 return dev_err_probe(wcss->dev, PTR_ERR(wcss->ahbs_cbcr), 920 "failed to get ahbs_cbcr clk\n"); 921 922 wcss->tcm_slave_cbcr = devm_clk_get(wcss->dev, 923 "lcc_tcm_slave_cbc"); 924 if (IS_ERR(wcss->tcm_slave_cbcr)) 925 return dev_err_probe(wcss->dev, PTR_ERR(wcss->tcm_slave_cbcr), 926 "failed to get tcm cbcr clk\n"); 927 928 wcss->qdsp6ss_abhm_cbcr = devm_clk_get(wcss->dev, "lcc_abhm_cbc"); 929 if (IS_ERR(wcss->qdsp6ss_abhm_cbcr)) 930 return dev_err_probe(wcss->dev, PTR_ERR(wcss->qdsp6ss_abhm_cbcr), 931 "failed to get abhm cbcr clk\n"); 932 933 wcss->qdsp6ss_axim_cbcr = devm_clk_get(wcss->dev, "lcc_axim_cbc"); 934 if (IS_ERR(wcss->qdsp6ss_axim_cbcr)) 935 return dev_err_probe(wcss->dev, PTR_ERR(wcss->qdsp6ss_axim_cbcr), 936 "failed to get axim cbcr clk\n"); 937 938 wcss->lcc_bcr_sleep = devm_clk_get(wcss->dev, "lcc_bcr_sleep"); 939 if (IS_ERR(wcss->lcc_bcr_sleep)) 940 return dev_err_probe(wcss->dev, PTR_ERR(wcss->lcc_bcr_sleep), 941 "failed to get bcr cbcr clk\n"); 942 943 return 0; 944 } 945 946 static int q6v5_wcss_init_regulator(struct q6v5_wcss *wcss) 947 { 948 wcss->cx_supply = devm_regulator_get(wcss->dev, "cx"); 949 if (IS_ERR(wcss->cx_supply)) 950 return PTR_ERR(wcss->cx_supply); 951 952 regulator_set_load(wcss->cx_supply, 100000); 953 954 return 0; 955 } 956 957 static int q6v5_wcss_probe(struct platform_device *pdev) 958 { 959 const struct wcss_data *desc; 960 struct q6v5_wcss *wcss; 961 struct rproc *rproc; 962 int ret; 963 964 desc = device_get_match_data(&pdev->dev); 965 if (!desc) 966 return -EINVAL; 967 968 rproc = devm_rproc_alloc(&pdev->dev, pdev->name, desc->ops, 969 desc->firmware_name, sizeof(*wcss)); 970 if (!rproc) { 971 dev_err(&pdev->dev, "failed to allocate rproc\n"); 972 return -ENOMEM; 973 } 974 975 wcss = rproc->priv; 976 wcss->dev = &pdev->dev; 977 978 wcss->version = desc->version; 979 wcss->requires_force_stop = desc->requires_force_stop; 980 981 ret = q6v5_wcss_init_mmio(wcss, pdev); 982 if (ret) 983 return ret; 984 985 ret = q6v5_alloc_memory_region(wcss); 986 if (ret) 987 return ret; 988 989 if (wcss->version == WCSS_QCS404) { 990 ret = q6v5_wcss_init_clock(wcss); 991 if (ret) 992 return ret; 993 994 ret = q6v5_wcss_init_regulator(wcss); 995 if (ret) 996 return ret; 997 } 998 999 ret = q6v5_wcss_init_reset(wcss, desc); 1000 if (ret) 1001 return ret; 1002 1003 ret = qcom_q6v5_init(&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, NULL, NULL); 1004 if (ret) 1005 return ret; 1006 1007 qcom_add_glink_subdev(rproc, &wcss->glink_subdev, "q6wcss"); 1008 qcom_add_pdm_subdev(rproc, &wcss->pdm_subdev); 1009 qcom_add_ssr_subdev(rproc, &wcss->ssr_subdev, "q6wcss"); 1010 1011 if (desc->ssctl_id) { 1012 wcss->sysmon = qcom_add_sysmon_subdev(rproc, 1013 desc->sysmon_name, 1014 desc->ssctl_id); 1015 if (IS_ERR(wcss->sysmon)) { 1016 ret = PTR_ERR(wcss->sysmon); 1017 goto deinit_remove_subdevs; 1018 } 1019 } 1020 1021 ret = rproc_add(rproc); 1022 if (ret) 1023 goto remove_sysmon_subdev; 1024 1025 platform_set_drvdata(pdev, rproc); 1026 1027 return 0; 1028 1029 remove_sysmon_subdev: 1030 if (desc->ssctl_id) 1031 qcom_remove_sysmon_subdev(wcss->sysmon); 1032 deinit_remove_subdevs: 1033 qcom_q6v5_deinit(&wcss->q6v5); 1034 qcom_remove_glink_subdev(rproc, &wcss->glink_subdev); 1035 qcom_remove_pdm_subdev(rproc, &wcss->pdm_subdev); 1036 qcom_remove_ssr_subdev(rproc, &wcss->ssr_subdev); 1037 return ret; 1038 } 1039 1040 static void q6v5_wcss_remove(struct platform_device *pdev) 1041 { 1042 struct rproc *rproc = platform_get_drvdata(pdev); 1043 struct q6v5_wcss *wcss = rproc->priv; 1044 1045 qcom_q6v5_deinit(&wcss->q6v5); 1046 qcom_remove_pdm_subdev(rproc, &wcss->pdm_subdev); 1047 rproc_del(rproc); 1048 } 1049 1050 static const struct wcss_data wcss_ipq8074_res_init = { 1051 .firmware_name = "IPQ8074/q6_fw.mdt", 1052 .crash_reason_smem = WCSS_CRASH_REASON, 1053 .aon_reset_required = true, 1054 .ops = &q6v5_wcss_ipq8074_ops, 1055 .requires_force_stop = true, 1056 }; 1057 1058 static const struct wcss_data wcss_qcs404_res_init = { 1059 .crash_reason_smem = WCSS_CRASH_REASON, 1060 .firmware_name = "wcnss.mdt", 1061 .version = WCSS_QCS404, 1062 .aon_reset_required = false, 1063 .ssr_name = "mpss", 1064 .sysmon_name = "wcnss", 1065 .ssctl_id = 0x12, 1066 .ops = &q6v5_wcss_qcs404_ops, 1067 .requires_force_stop = false, 1068 }; 1069 1070 static const struct of_device_id q6v5_wcss_of_match[] = { 1071 { .compatible = "qcom,ipq8074-wcss-pil", .data = &wcss_ipq8074_res_init }, 1072 { .compatible = "qcom,qcs404-wcss-pil", .data = &wcss_qcs404_res_init }, 1073 { }, 1074 }; 1075 MODULE_DEVICE_TABLE(of, q6v5_wcss_of_match); 1076 1077 static struct platform_driver q6v5_wcss_driver = { 1078 .probe = q6v5_wcss_probe, 1079 .remove = q6v5_wcss_remove, 1080 .driver = { 1081 .name = "qcom-q6v5-wcss-pil", 1082 .of_match_table = q6v5_wcss_of_match, 1083 }, 1084 }; 1085 module_platform_driver(q6v5_wcss_driver); 1086 1087 MODULE_DESCRIPTION("Hexagon WCSS Peripheral Image Loader"); 1088 MODULE_LICENSE("GPL v2"); 1089