xref: /linux/drivers/gpu/drm/imagination/pvr_device_info.c (revision 0ea5c948cb64bab5bc7a5516774eb8536f05aa0d)
1 // SPDX-License-Identifier: GPL-2.0-only OR MIT
2 /* Copyright (c) 2023 Imagination Technologies Ltd. */
3 
4 #include "pvr_device.h"
5 #include "pvr_device_info.h"
6 #include "pvr_rogue_fwif_dev_info.h"
7 
8 #include <drm/drm_print.h>
9 
10 #include <linux/bits.h>
11 #include <linux/minmax.h>
12 #include <linux/stddef.h>
13 #include <linux/types.h>
14 
15 #define QUIRK_MAPPING(quirk) \
16 	[PVR_FW_HAS_BRN_##quirk] = offsetof(struct pvr_device, quirks.has_brn##quirk)
17 
18 static const uintptr_t quirks_mapping[] = {
19 	QUIRK_MAPPING(44079),
20 	QUIRK_MAPPING(47217),
21 	QUIRK_MAPPING(48492),
22 	QUIRK_MAPPING(48545),
23 	QUIRK_MAPPING(49927),
24 	QUIRK_MAPPING(50767),
25 	QUIRK_MAPPING(51764),
26 	QUIRK_MAPPING(62269),
27 	QUIRK_MAPPING(63142),
28 	QUIRK_MAPPING(63553),
29 	QUIRK_MAPPING(66011),
30 	QUIRK_MAPPING(71242),
31 };
32 
33 #undef QUIRK_MAPPING
34 
35 #define ENHANCEMENT_MAPPING(enhancement)                             \
36 	[PVR_FW_HAS_ERN_##enhancement] = offsetof(struct pvr_device, \
37 						  enhancements.has_ern##enhancement)
38 
39 static const uintptr_t enhancements_mapping[] = {
40 	ENHANCEMENT_MAPPING(35421),
41 	ENHANCEMENT_MAPPING(38020),
42 	ENHANCEMENT_MAPPING(38748),
43 	ENHANCEMENT_MAPPING(42064),
44 	ENHANCEMENT_MAPPING(42290),
45 	ENHANCEMENT_MAPPING(42606),
46 	ENHANCEMENT_MAPPING(47025),
47 	ENHANCEMENT_MAPPING(57596),
48 };
49 
50 #undef ENHANCEMENT_MAPPING
51 
pvr_device_info_set_common(struct pvr_device * pvr_dev,const u64 * bitmask,u32 bitmask_size,const uintptr_t * mapping,u32 mapping_max)52 static void pvr_device_info_set_common(struct pvr_device *pvr_dev, const u64 *bitmask,
53 				       u32 bitmask_size, const uintptr_t *mapping, u32 mapping_max)
54 {
55 	const u32 mapping_max_size = (mapping_max + 63) >> 6;
56 	const u32 nr_bits = min(bitmask_size * 64, mapping_max);
57 
58 	/* Warn if any unsupported values in the bitmask. */
59 	if (bitmask_size > mapping_max_size) {
60 		if (mapping == quirks_mapping)
61 			drm_warn(from_pvr_device(pvr_dev), "Unsupported quirks in firmware image");
62 		else
63 			drm_warn(from_pvr_device(pvr_dev),
64 				 "Unsupported enhancements in firmware image");
65 	} else if (bitmask_size == mapping_max_size && (mapping_max & 63)) {
66 		u64 invalid_mask = ~0ull << (mapping_max & 63);
67 
68 		if (bitmask[bitmask_size - 1] & invalid_mask) {
69 			if (mapping == quirks_mapping)
70 				drm_warn(from_pvr_device(pvr_dev),
71 					 "Unsupported quirks in firmware image");
72 			else
73 				drm_warn(from_pvr_device(pvr_dev),
74 					 "Unsupported enhancements in firmware image");
75 		}
76 	}
77 
78 	for (u32 i = 0; i < nr_bits; i++) {
79 		if (bitmask[i >> 6] & BIT_ULL(i & 63))
80 			*(bool *)((u8 *)pvr_dev + mapping[i]) = true;
81 	}
82 }
83 
84 /**
85  * pvr_device_info_set_quirks() - Set device quirks from device information in firmware
86  * @pvr_dev: Device pointer.
87  * @quirks: Pointer to quirks mask in device information.
88  * @quirks_size: Size of quirks mask, in u64s.
89  */
pvr_device_info_set_quirks(struct pvr_device * pvr_dev,const u64 * quirks,u32 quirks_size)90 void pvr_device_info_set_quirks(struct pvr_device *pvr_dev, const u64 *quirks, u32 quirks_size)
91 {
92 	BUILD_BUG_ON(ARRAY_SIZE(quirks_mapping) != PVR_FW_HAS_BRN_MAX);
93 
94 	pvr_device_info_set_common(pvr_dev, quirks, quirks_size, quirks_mapping,
95 				   ARRAY_SIZE(quirks_mapping));
96 }
97 
98 /**
99  * pvr_device_info_set_enhancements() - Set device enhancements from device information in firmware
100  * @pvr_dev: Device pointer.
101  * @enhancements: Pointer to enhancements mask in device information.
102  * @enhancements_size: Size of enhancements mask, in u64s.
103  */
pvr_device_info_set_enhancements(struct pvr_device * pvr_dev,const u64 * enhancements,u32 enhancements_size)104 void pvr_device_info_set_enhancements(struct pvr_device *pvr_dev, const u64 *enhancements,
105 				      u32 enhancements_size)
106 {
107 	BUILD_BUG_ON(ARRAY_SIZE(enhancements_mapping) != PVR_FW_HAS_ERN_MAX);
108 
109 	pvr_device_info_set_common(pvr_dev, enhancements, enhancements_size,
110 				   enhancements_mapping, ARRAY_SIZE(enhancements_mapping));
111 }
112 
113 #define FEATURE_MAPPING(fw_feature, feature)                                        \
114 	[PVR_FW_HAS_FEATURE_##fw_feature] = {                                       \
115 		.flag_offset = offsetof(struct pvr_device, features.has_##feature), \
116 		.value_offset = 0                                                   \
117 	}
118 
119 #define FEATURE_MAPPING_VALUE(fw_feature, feature)                                  \
120 	[PVR_FW_HAS_FEATURE_##fw_feature] = {                                       \
121 		.flag_offset = offsetof(struct pvr_device, features.has_##feature), \
122 		.value_offset = offsetof(struct pvr_device, features.feature)       \
123 	}
124 
125 static const struct {
126 	uintptr_t flag_offset;
127 	uintptr_t value_offset;
128 } features_mapping[] = {
129 	FEATURE_MAPPING(AXI_ACELITE, axi_acelite),
130 	FEATURE_MAPPING_VALUE(CDM_CONTROL_STREAM_FORMAT, cdm_control_stream_format),
131 	FEATURE_MAPPING(CLUSTER_GROUPING, cluster_grouping),
132 	FEATURE_MAPPING_VALUE(COMMON_STORE_SIZE_IN_DWORDS, common_store_size_in_dwords),
133 	FEATURE_MAPPING(COMPUTE, compute),
134 	FEATURE_MAPPING(COMPUTE_MORTON_CAPABLE, compute_morton_capable),
135 	FEATURE_MAPPING(COMPUTE_OVERLAP, compute_overlap),
136 	FEATURE_MAPPING(COREID_PER_OS, coreid_per_os),
137 	FEATURE_MAPPING(DYNAMIC_DUST_POWER, dynamic_dust_power),
138 	FEATURE_MAPPING_VALUE(ECC_RAMS, ecc_rams),
139 	FEATURE_MAPPING_VALUE(FBCDC, fbcdc),
140 	FEATURE_MAPPING_VALUE(FBCDC_ALGORITHM, fbcdc_algorithm),
141 	FEATURE_MAPPING_VALUE(FBCDC_ARCHITECTURE, fbcdc_architecture),
142 	FEATURE_MAPPING_VALUE(FBC_MAX_DEFAULT_DESCRIPTORS, fbc_max_default_descriptors),
143 	FEATURE_MAPPING_VALUE(FBC_MAX_LARGE_DESCRIPTORS, fbc_max_large_descriptors),
144 	FEATURE_MAPPING(FB_CDC_V4, fb_cdc_v4),
145 	FEATURE_MAPPING(GPU_MULTICORE_SUPPORT, gpu_multicore_support),
146 	FEATURE_MAPPING(GPU_VIRTUALISATION, gpu_virtualisation),
147 	FEATURE_MAPPING(GS_RTA_SUPPORT, gs_rta_support),
148 	FEATURE_MAPPING(IRQ_PER_OS, irq_per_os),
149 	FEATURE_MAPPING_VALUE(ISP_MAX_TILES_IN_FLIGHT, isp_max_tiles_in_flight),
150 	FEATURE_MAPPING_VALUE(ISP_SAMPLES_PER_PIXEL, isp_samples_per_pixel),
151 	FEATURE_MAPPING(ISP_ZLS_D24_S8_PACKING_OGL_MODE, isp_zls_d24_s8_packing_ogl_mode),
152 	FEATURE_MAPPING_VALUE(LAYOUT_MARS, layout_mars),
153 	FEATURE_MAPPING_VALUE(MAX_PARTITIONS, max_partitions),
154 	FEATURE_MAPPING_VALUE(META, meta),
155 	FEATURE_MAPPING_VALUE(META_COREMEM_SIZE, meta_coremem_size),
156 	FEATURE_MAPPING(MIPS, mips),
157 	FEATURE_MAPPING_VALUE(NUM_CLUSTERS, num_clusters),
158 	FEATURE_MAPPING_VALUE(NUM_ISP_IPP_PIPES, num_isp_ipp_pipes),
159 	FEATURE_MAPPING_VALUE(NUM_OSIDS, num_osids),
160 	FEATURE_MAPPING_VALUE(NUM_RASTER_PIPES, num_raster_pipes),
161 	FEATURE_MAPPING(PBE2_IN_XE, pbe2_in_xe),
162 	FEATURE_MAPPING(PBVNC_COREID_REG, pbvnc_coreid_reg),
163 	FEATURE_MAPPING(PERFBUS, perfbus),
164 	FEATURE_MAPPING(PERF_COUNTER_BATCH, perf_counter_batch),
165 	FEATURE_MAPPING_VALUE(PHYS_BUS_WIDTH, phys_bus_width),
166 	FEATURE_MAPPING(RISCV_FW_PROCESSOR, riscv_fw_processor),
167 	FEATURE_MAPPING(ROGUEXE, roguexe),
168 	FEATURE_MAPPING(S7_TOP_INFRASTRUCTURE, s7_top_infrastructure),
169 	FEATURE_MAPPING(SIMPLE_INTERNAL_PARAMETER_FORMAT, simple_internal_parameter_format),
170 	FEATURE_MAPPING(SIMPLE_INTERNAL_PARAMETER_FORMAT_V2, simple_internal_parameter_format_v2),
171 	FEATURE_MAPPING_VALUE(SIMPLE_PARAMETER_FORMAT_VERSION, simple_parameter_format_version),
172 	FEATURE_MAPPING_VALUE(SLC_BANKS, slc_banks),
173 	FEATURE_MAPPING_VALUE(SLC_CACHE_LINE_SIZE_BITS, slc_cache_line_size_bits),
174 	FEATURE_MAPPING(SLC_SIZE_CONFIGURABLE, slc_size_configurable),
175 	FEATURE_MAPPING_VALUE(SLC_SIZE_IN_KILOBYTES, slc_size_in_kilobytes),
176 	FEATURE_MAPPING(SOC_TIMER, soc_timer),
177 	FEATURE_MAPPING(SYS_BUS_SECURE_RESET, sys_bus_secure_reset),
178 	FEATURE_MAPPING(TESSELLATION, tessellation),
179 	FEATURE_MAPPING(TILE_REGION_PROTECTION, tile_region_protection),
180 	FEATURE_MAPPING_VALUE(TILE_SIZE_X, tile_size_x),
181 	FEATURE_MAPPING_VALUE(TILE_SIZE_Y, tile_size_y),
182 	FEATURE_MAPPING(TLA, tla),
183 	FEATURE_MAPPING(TPU_CEM_DATAMASTER_GLOBAL_REGISTERS, tpu_cem_datamaster_global_registers),
184 	FEATURE_MAPPING(TPU_DM_GLOBAL_REGISTERS, tpu_dm_global_registers),
185 	FEATURE_MAPPING(TPU_FILTERING_MODE_CONTROL, tpu_filtering_mode_control),
186 	FEATURE_MAPPING_VALUE(USC_MIN_OUTPUT_REGISTERS_PER_PIX, usc_min_output_registers_per_pix),
187 	FEATURE_MAPPING(VDM_DRAWINDIRECT, vdm_drawindirect),
188 	FEATURE_MAPPING(VDM_OBJECT_LEVEL_LLS, vdm_object_level_lls),
189 	FEATURE_MAPPING_VALUE(VIRTUAL_ADDRESS_SPACE_BITS, virtual_address_space_bits),
190 	FEATURE_MAPPING(WATCHDOG_TIMER, watchdog_timer),
191 	FEATURE_MAPPING(WORKGROUP_PROTECTION, workgroup_protection),
192 	FEATURE_MAPPING_VALUE(XE_ARCHITECTURE, xe_architecture),
193 	FEATURE_MAPPING(XE_MEMORY_HIERARCHY, xe_memory_hierarchy),
194 	FEATURE_MAPPING(XE_TPU2, xe_tpu2),
195 	FEATURE_MAPPING_VALUE(XPU_MAX_REGBANKS_ADDR_WIDTH, xpu_max_regbanks_addr_width),
196 	FEATURE_MAPPING_VALUE(XPU_MAX_SLAVES, xpu_max_slaves),
197 	FEATURE_MAPPING_VALUE(XPU_REGISTER_BROADCAST, xpu_register_broadcast),
198 	FEATURE_MAPPING(XT_TOP_INFRASTRUCTURE, xt_top_infrastructure),
199 	FEATURE_MAPPING(ZLS_SUBTILE, zls_subtile),
200 };
201 
202 #undef FEATURE_MAPPING_VALUE
203 #undef FEATURE_MAPPING
204 
205 /**
206  * pvr_device_info_set_features() - Set device features from device information in firmware
207  * @pvr_dev: Device pointer.
208  * @features: Pointer to features mask in device information.
209  * @features_size: Size of features mask, in u64s.
210  * @feature_param_size: Size of feature parameters, in u64s.
211  *
212  * Returns:
213  *  * 0 on success, or
214  *  * -%EINVAL on malformed stream.
215  */
pvr_device_info_set_features(struct pvr_device * pvr_dev,const u64 * features,u32 features_size,u32 feature_param_size)216 int pvr_device_info_set_features(struct pvr_device *pvr_dev, const u64 *features, u32 features_size,
217 				 u32 feature_param_size)
218 {
219 	const u32 mapping_max = ARRAY_SIZE(features_mapping);
220 	const u32 mapping_max_size = (mapping_max + 63) >> 6;
221 	const u32 nr_bits = min(features_size * 64, mapping_max);
222 	const u64 *feature_params = features + features_size;
223 	u32 param_idx = 0;
224 
225 	BUILD_BUG_ON(ARRAY_SIZE(features_mapping) != PVR_FW_HAS_FEATURE_MAX);
226 
227 	/* Verify no unsupported values in the bitmask. */
228 	if (features_size > mapping_max_size) {
229 		drm_warn(from_pvr_device(pvr_dev), "Unsupported features in firmware image");
230 	} else if (features_size == mapping_max_size &&
231 		   ((mapping_max & 63) != 0)) {
232 		u64 invalid_mask = ~0ull << (mapping_max & 63);
233 
234 		if (features[features_size - 1] & invalid_mask)
235 			drm_warn(from_pvr_device(pvr_dev),
236 				 "Unsupported features in firmware image");
237 	}
238 
239 	for (u32 i = 0; i < nr_bits; i++) {
240 		if (features[i >> 6] & BIT_ULL(i & 63)) {
241 			*(bool *)((u8 *)pvr_dev + features_mapping[i].flag_offset) = true;
242 
243 			if (features_mapping[i].value_offset) {
244 				if (param_idx >= feature_param_size)
245 					return -EINVAL;
246 
247 				*(u64 *)((u8 *)pvr_dev + features_mapping[i].value_offset) =
248 					feature_params[param_idx];
249 				param_idx++;
250 			}
251 		}
252 	}
253 
254 	return 0;
255 }
256