1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
3
4 #include <linux/bits.h>
5 #include <linux/err.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/xilinx_spi.h>
20 #include <linux/spi/altera.h>
21 #include <net/devlink.h>
22 #include <linux/i2c.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/crc16.h>
26 #include <linux/dpll.h>
27
28 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
29 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
30
31 #define PCI_VENDOR_ID_CELESTICA 0x18d4
32 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
33
34 #define PCI_VENDOR_ID_OROLIA 0x1ad7
35 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
36
37 #define PCI_VENDOR_ID_ADVA 0xad5a
38 #define PCI_DEVICE_ID_ADVA_TIMECARD 0x0400
39
40 static struct class timecard_class = {
41 .name = "timecard",
42 };
43
44 struct ocp_reg {
45 u32 ctrl;
46 u32 status;
47 u32 select;
48 u32 version;
49 u32 time_ns;
50 u32 time_sec;
51 u32 __pad0[2];
52 u32 adjust_ns;
53 u32 adjust_sec;
54 u32 __pad1[2];
55 u32 offset_ns;
56 u32 offset_window_ns;
57 u32 __pad2[2];
58 u32 drift_ns;
59 u32 drift_window_ns;
60 u32 __pad3[6];
61 u32 servo_offset_p;
62 u32 servo_offset_i;
63 u32 servo_drift_p;
64 u32 servo_drift_i;
65 u32 status_offset;
66 u32 status_drift;
67 };
68
69 struct ptp_ocp_servo_conf {
70 u32 servo_offset_p;
71 u32 servo_offset_i;
72 u32 servo_drift_p;
73 u32 servo_drift_i;
74 };
75
76 #define OCP_CTRL_ENABLE BIT(0)
77 #define OCP_CTRL_ADJUST_TIME BIT(1)
78 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
79 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
80 #define OCP_CTRL_ADJUST_SERVO BIT(8)
81 #define OCP_CTRL_READ_TIME_REQ BIT(30)
82 #define OCP_CTRL_READ_TIME_DONE BIT(31)
83
84 #define OCP_STATUS_IN_SYNC BIT(0)
85 #define OCP_STATUS_IN_HOLDOVER BIT(1)
86
87 #define OCP_SELECT_CLK_NONE 0
88 #define OCP_SELECT_CLK_REG 0xfe
89
90 struct tod_reg {
91 u32 ctrl;
92 u32 status;
93 u32 uart_polarity;
94 u32 version;
95 u32 adj_sec;
96 u32 __pad0[3];
97 u32 uart_baud;
98 u32 __pad1[3];
99 u32 utc_status;
100 u32 leap;
101 };
102
103 #define TOD_CTRL_PROTOCOL BIT(28)
104 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
105 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
106 #define TOD_CTRL_ENABLE BIT(0)
107 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
108 #define TOD_CTRL_GNSS_SHIFT 24
109
110 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
111 #define TOD_STATUS_UTC_VALID BIT(8)
112 #define TOD_STATUS_LEAP_ANNOUNCE BIT(12)
113 #define TOD_STATUS_LEAP_VALID BIT(16)
114
115 struct ts_reg {
116 u32 enable;
117 u32 error;
118 u32 polarity;
119 u32 version;
120 u32 __pad0[4];
121 u32 cable_delay;
122 u32 __pad1[3];
123 u32 intr;
124 u32 intr_mask;
125 u32 event_count;
126 u32 __pad2[1];
127 u32 ts_count;
128 u32 time_ns;
129 u32 time_sec;
130 u32 data_width;
131 u32 data;
132 };
133
134 struct pps_reg {
135 u32 ctrl;
136 u32 status;
137 u32 __pad0[6];
138 u32 cable_delay;
139 };
140
141 #define PPS_STATUS_FILTER_ERR BIT(0)
142 #define PPS_STATUS_SUPERV_ERR BIT(1)
143
144 struct img_reg {
145 u32 version;
146 };
147
148 struct gpio_reg {
149 u32 gpio1;
150 u32 __pad0;
151 u32 gpio2;
152 u32 __pad1;
153 };
154
155 struct irig_master_reg {
156 u32 ctrl;
157 u32 status;
158 u32 __pad0;
159 u32 version;
160 u32 adj_sec;
161 u32 mode_ctrl;
162 };
163
164 #define IRIG_M_CTRL_ENABLE BIT(0)
165
166 struct irig_slave_reg {
167 u32 ctrl;
168 u32 status;
169 u32 __pad0;
170 u32 version;
171 u32 adj_sec;
172 u32 mode_ctrl;
173 };
174
175 #define IRIG_S_CTRL_ENABLE BIT(0)
176
177 struct dcf_master_reg {
178 u32 ctrl;
179 u32 status;
180 u32 __pad0;
181 u32 version;
182 u32 adj_sec;
183 };
184
185 #define DCF_M_CTRL_ENABLE BIT(0)
186
187 struct dcf_slave_reg {
188 u32 ctrl;
189 u32 status;
190 u32 __pad0;
191 u32 version;
192 u32 adj_sec;
193 };
194
195 #define DCF_S_CTRL_ENABLE BIT(0)
196
197 struct signal_reg {
198 u32 enable;
199 u32 status;
200 u32 polarity;
201 u32 version;
202 u32 __pad0[4];
203 u32 cable_delay;
204 u32 __pad1[3];
205 u32 intr;
206 u32 intr_mask;
207 u32 __pad2[2];
208 u32 start_ns;
209 u32 start_sec;
210 u32 pulse_ns;
211 u32 pulse_sec;
212 u32 period_ns;
213 u32 period_sec;
214 u32 repeat_count;
215 };
216
217 struct frequency_reg {
218 u32 ctrl;
219 u32 status;
220 };
221
222 struct board_config_reg {
223 u32 mro50_serial_activate;
224 };
225
226 #define FREQ_STATUS_VALID BIT(31)
227 #define FREQ_STATUS_ERROR BIT(30)
228 #define FREQ_STATUS_OVERRUN BIT(29)
229 #define FREQ_STATUS_MASK GENMASK(23, 0)
230
231 struct ptp_ocp_flash_info {
232 const char *name;
233 int pci_offset;
234 int data_size;
235 void *data;
236 };
237
238 struct ptp_ocp_firmware_header {
239 char magic[4];
240 __be16 pci_vendor_id;
241 __be16 pci_device_id;
242 __be32 image_size;
243 __be16 hw_revision;
244 __be16 crc;
245 };
246
247 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
248
249 struct ptp_ocp_i2c_info {
250 const char *name;
251 unsigned long fixed_rate;
252 size_t data_size;
253 void *data;
254 };
255
256 struct ptp_ocp_ext_info {
257 int index;
258 irqreturn_t (*irq_fcn)(int irq, void *priv);
259 int (*enable)(void *priv, u32 req, bool enable);
260 };
261
262 struct ptp_ocp_ext_src {
263 void __iomem *mem;
264 struct ptp_ocp *bp;
265 struct ptp_ocp_ext_info *info;
266 int irq_vec;
267 };
268
269 enum ptp_ocp_sma_mode {
270 SMA_MODE_IN,
271 SMA_MODE_OUT,
272 };
273
274 static struct dpll_pin_frequency ptp_ocp_sma_freq[] = {
275 DPLL_PIN_FREQUENCY_1PPS,
276 DPLL_PIN_FREQUENCY_10MHZ,
277 DPLL_PIN_FREQUENCY_IRIG_B,
278 DPLL_PIN_FREQUENCY_DCF77,
279 };
280
281 struct ptp_ocp_sma_connector {
282 enum ptp_ocp_sma_mode mode;
283 bool fixed_fcn;
284 bool fixed_dir;
285 bool disabled;
286 u8 default_fcn;
287 struct dpll_pin *dpll_pin;
288 struct dpll_pin_properties dpll_prop;
289 };
290
291 struct ocp_attr_group {
292 u64 cap;
293 const struct attribute_group *group;
294 };
295
296 #define OCP_CAP_BASIC BIT(0)
297 #define OCP_CAP_SIGNAL BIT(1)
298 #define OCP_CAP_FREQ BIT(2)
299
300 struct ptp_ocp_signal {
301 ktime_t period;
302 ktime_t pulse;
303 ktime_t phase;
304 ktime_t start;
305 int duty;
306 bool polarity;
307 bool running;
308 };
309
310 struct ptp_ocp_serial_port {
311 int line;
312 int baud;
313 };
314
315 #define OCP_BOARD_ID_LEN 13
316 #define OCP_SERIAL_LEN 6
317 #define OCP_SMA_NUM 4
318
319 enum {
320 PORT_GNSS,
321 PORT_GNSS2,
322 PORT_MAC, /* miniature atomic clock */
323 PORT_NMEA,
324
325 __PORT_COUNT,
326 };
327
328 struct ptp_ocp {
329 struct pci_dev *pdev;
330 struct device dev;
331 spinlock_t lock;
332 struct ocp_reg __iomem *reg;
333 struct tod_reg __iomem *tod;
334 struct pps_reg __iomem *pps_to_ext;
335 struct pps_reg __iomem *pps_to_clk;
336 struct board_config_reg __iomem *board_config;
337 struct gpio_reg __iomem *pps_select;
338 struct gpio_reg __iomem *sma_map1;
339 struct gpio_reg __iomem *sma_map2;
340 struct irig_master_reg __iomem *irig_out;
341 struct irig_slave_reg __iomem *irig_in;
342 struct dcf_master_reg __iomem *dcf_out;
343 struct dcf_slave_reg __iomem *dcf_in;
344 struct tod_reg __iomem *nmea_out;
345 struct frequency_reg __iomem *freq_in[4];
346 struct ptp_ocp_ext_src *signal_out[4];
347 struct ptp_ocp_ext_src *pps;
348 struct ptp_ocp_ext_src *ts0;
349 struct ptp_ocp_ext_src *ts1;
350 struct ptp_ocp_ext_src *ts2;
351 struct ptp_ocp_ext_src *ts3;
352 struct ptp_ocp_ext_src *ts4;
353 struct ocp_art_gpio_reg __iomem *art_sma;
354 struct img_reg __iomem *image;
355 struct ptp_clock *ptp;
356 struct ptp_clock_info ptp_info;
357 struct platform_device *i2c_ctrl;
358 struct platform_device *spi_flash;
359 struct clk_hw *i2c_clk;
360 struct timer_list watchdog;
361 const struct attribute_group **attr_group;
362 const struct ptp_ocp_eeprom_map *eeprom_map;
363 struct dentry *debug_root;
364 bool sync;
365 time64_t gnss_lost;
366 struct delayed_work sync_work;
367 int id;
368 int n_irqs;
369 struct ptp_ocp_serial_port port[__PORT_COUNT];
370 bool fw_loader;
371 u8 fw_tag;
372 u16 fw_version;
373 u8 board_id[OCP_BOARD_ID_LEN];
374 u8 serial[OCP_SERIAL_LEN];
375 bool has_eeprom_data;
376 u32 pps_req_map;
377 int flash_start;
378 u32 utc_tai_offset;
379 u32 ts_window_adjust;
380 u64 fw_cap;
381 struct ptp_ocp_signal signal[4];
382 struct ptp_ocp_sma_connector sma[OCP_SMA_NUM];
383 const struct ocp_sma_op *sma_op;
384 struct dpll_device *dpll;
385 };
386
387 #define OCP_REQ_TIMESTAMP BIT(0)
388 #define OCP_REQ_PPS BIT(1)
389
390 struct ocp_resource {
391 unsigned long offset;
392 int size;
393 int irq_vec;
394 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
395 void *extra;
396 unsigned long bp_offset;
397 const char * const name;
398 };
399
400 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
401 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
402 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
403 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
404 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
405 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
406 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
407 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
408 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
409 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
410 struct ptp_perout_request *req);
411 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
412 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
413
414 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
415
416 static int ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
417
418 static const struct ocp_attr_group fb_timecard_groups[];
419
420 static const struct ocp_attr_group art_timecard_groups[];
421
422 static const struct ocp_attr_group adva_timecard_groups[];
423
424 struct ptp_ocp_eeprom_map {
425 u16 off;
426 u16 len;
427 u32 bp_offset;
428 const void * const tag;
429 };
430
431 #define EEPROM_ENTRY(addr, member) \
432 .off = addr, \
433 .len = sizeof_field(struct ptp_ocp, member), \
434 .bp_offset = offsetof(struct ptp_ocp, member)
435
436 #define BP_MAP_ENTRY_ADDR(bp, map) ({ \
437 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
438 })
439
440 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
441 { EEPROM_ENTRY(0x43, board_id) },
442 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
443 { }
444 };
445
446 static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
447 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
448 { EEPROM_ENTRY(0x200 + 0x63, serial) },
449 { }
450 };
451
452 #define bp_assign_entry(bp, res, val) ({ \
453 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
454 *(typeof(val) *)addr = val; \
455 })
456
457 #define OCP_RES_LOCATION(member) \
458 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
459
460 #define OCP_MEM_RESOURCE(member) \
461 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
462
463 #define OCP_SERIAL_RESOURCE(member) \
464 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
465
466 #define OCP_I2C_RESOURCE(member) \
467 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
468
469 #define OCP_SPI_RESOURCE(member) \
470 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
471
472 #define OCP_EXT_RESOURCE(member) \
473 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
474
475 /* This is the MSI vector mapping used.
476 * 0: PPS (TS5)
477 * 1: TS0
478 * 2: TS1
479 * 3: GNSS1
480 * 4: GNSS2
481 * 5: MAC
482 * 6: TS2
483 * 7: I2C controller
484 * 8: HWICAP (notused)
485 * 9: SPI Flash
486 * 10: NMEA
487 * 11: Signal Generator 1
488 * 12: Signal Generator 2
489 * 13: Signal Generator 3
490 * 14: Signal Generator 4
491 * 15: TS3
492 * 16: TS4
493 --
494 * 8: Orolia TS1
495 * 10: Orolia TS2
496 * 11: Orolia TS0 (GNSS)
497 * 12: Orolia PPS
498 * 14: Orolia TS3
499 * 15: Orolia TS4
500 */
501
502 static struct ocp_resource ocp_fb_resource[] = {
503 {
504 OCP_MEM_RESOURCE(reg),
505 .offset = 0x01000000, .size = 0x10000,
506 },
507 {
508 OCP_EXT_RESOURCE(ts0),
509 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
510 .extra = &(struct ptp_ocp_ext_info) {
511 .index = 0,
512 .irq_fcn = ptp_ocp_ts_irq,
513 .enable = ptp_ocp_ts_enable,
514 },
515 },
516 {
517 OCP_EXT_RESOURCE(ts1),
518 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
519 .extra = &(struct ptp_ocp_ext_info) {
520 .index = 1,
521 .irq_fcn = ptp_ocp_ts_irq,
522 .enable = ptp_ocp_ts_enable,
523 },
524 },
525 {
526 OCP_EXT_RESOURCE(ts2),
527 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
528 .extra = &(struct ptp_ocp_ext_info) {
529 .index = 2,
530 .irq_fcn = ptp_ocp_ts_irq,
531 .enable = ptp_ocp_ts_enable,
532 },
533 },
534 {
535 OCP_EXT_RESOURCE(ts3),
536 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
537 .extra = &(struct ptp_ocp_ext_info) {
538 .index = 3,
539 .irq_fcn = ptp_ocp_ts_irq,
540 .enable = ptp_ocp_ts_enable,
541 },
542 },
543 {
544 OCP_EXT_RESOURCE(ts4),
545 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
546 .extra = &(struct ptp_ocp_ext_info) {
547 .index = 4,
548 .irq_fcn = ptp_ocp_ts_irq,
549 .enable = ptp_ocp_ts_enable,
550 },
551 },
552 /* Timestamp for PHC and/or PPS generator */
553 {
554 OCP_EXT_RESOURCE(pps),
555 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
556 .extra = &(struct ptp_ocp_ext_info) {
557 .index = 5,
558 .irq_fcn = ptp_ocp_ts_irq,
559 .enable = ptp_ocp_ts_enable,
560 },
561 },
562 {
563 OCP_EXT_RESOURCE(signal_out[0]),
564 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
565 .extra = &(struct ptp_ocp_ext_info) {
566 .index = 1,
567 .irq_fcn = ptp_ocp_signal_irq,
568 .enable = ptp_ocp_signal_enable,
569 },
570 },
571 {
572 OCP_EXT_RESOURCE(signal_out[1]),
573 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
574 .extra = &(struct ptp_ocp_ext_info) {
575 .index = 2,
576 .irq_fcn = ptp_ocp_signal_irq,
577 .enable = ptp_ocp_signal_enable,
578 },
579 },
580 {
581 OCP_EXT_RESOURCE(signal_out[2]),
582 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
583 .extra = &(struct ptp_ocp_ext_info) {
584 .index = 3,
585 .irq_fcn = ptp_ocp_signal_irq,
586 .enable = ptp_ocp_signal_enable,
587 },
588 },
589 {
590 OCP_EXT_RESOURCE(signal_out[3]),
591 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
592 .extra = &(struct ptp_ocp_ext_info) {
593 .index = 4,
594 .irq_fcn = ptp_ocp_signal_irq,
595 .enable = ptp_ocp_signal_enable,
596 },
597 },
598 {
599 OCP_MEM_RESOURCE(pps_to_ext),
600 .offset = 0x01030000, .size = 0x10000,
601 },
602 {
603 OCP_MEM_RESOURCE(pps_to_clk),
604 .offset = 0x01040000, .size = 0x10000,
605 },
606 {
607 OCP_MEM_RESOURCE(tod),
608 .offset = 0x01050000, .size = 0x10000,
609 },
610 {
611 OCP_MEM_RESOURCE(irig_in),
612 .offset = 0x01070000, .size = 0x10000,
613 },
614 {
615 OCP_MEM_RESOURCE(irig_out),
616 .offset = 0x01080000, .size = 0x10000,
617 },
618 {
619 OCP_MEM_RESOURCE(dcf_in),
620 .offset = 0x01090000, .size = 0x10000,
621 },
622 {
623 OCP_MEM_RESOURCE(dcf_out),
624 .offset = 0x010A0000, .size = 0x10000,
625 },
626 {
627 OCP_MEM_RESOURCE(nmea_out),
628 .offset = 0x010B0000, .size = 0x10000,
629 },
630 {
631 OCP_MEM_RESOURCE(image),
632 .offset = 0x00020000, .size = 0x1000,
633 },
634 {
635 OCP_MEM_RESOURCE(pps_select),
636 .offset = 0x00130000, .size = 0x1000,
637 },
638 {
639 OCP_MEM_RESOURCE(sma_map1),
640 .offset = 0x00140000, .size = 0x1000,
641 },
642 {
643 OCP_MEM_RESOURCE(sma_map2),
644 .offset = 0x00220000, .size = 0x1000,
645 },
646 {
647 OCP_I2C_RESOURCE(i2c_ctrl),
648 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
649 .extra = &(struct ptp_ocp_i2c_info) {
650 .name = "xiic-i2c",
651 .fixed_rate = 50000000,
652 .data_size = sizeof(struct xiic_i2c_platform_data),
653 .data = &(struct xiic_i2c_platform_data) {
654 .num_devices = 2,
655 .devices = (struct i2c_board_info[]) {
656 { I2C_BOARD_INFO("24c02", 0x50) },
657 { I2C_BOARD_INFO("24mac402", 0x58),
658 .platform_data = "mac" },
659 },
660 },
661 },
662 },
663 {
664 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
665 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
666 .extra = &(struct ptp_ocp_serial_port) {
667 .baud = 115200,
668 },
669 },
670 {
671 OCP_SERIAL_RESOURCE(port[PORT_GNSS2]),
672 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
673 .extra = &(struct ptp_ocp_serial_port) {
674 .baud = 115200,
675 },
676 },
677 {
678 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
679 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
680 .extra = &(struct ptp_ocp_serial_port) {
681 .baud = 57600,
682 },
683 },
684 {
685 OCP_SERIAL_RESOURCE(port[PORT_NMEA]),
686 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
687 },
688 {
689 OCP_SPI_RESOURCE(spi_flash),
690 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
691 .extra = &(struct ptp_ocp_flash_info) {
692 .name = "xilinx_spi", .pci_offset = 0,
693 .data_size = sizeof(struct xspi_platform_data),
694 .data = &(struct xspi_platform_data) {
695 .num_chipselect = 1,
696 .bits_per_word = 8,
697 .num_devices = 1,
698 .force_irq = true,
699 .devices = &(struct spi_board_info) {
700 .modalias = "spi-nor",
701 },
702 },
703 },
704 },
705 {
706 OCP_MEM_RESOURCE(freq_in[0]),
707 .offset = 0x01200000, .size = 0x10000,
708 },
709 {
710 OCP_MEM_RESOURCE(freq_in[1]),
711 .offset = 0x01210000, .size = 0x10000,
712 },
713 {
714 OCP_MEM_RESOURCE(freq_in[2]),
715 .offset = 0x01220000, .size = 0x10000,
716 },
717 {
718 OCP_MEM_RESOURCE(freq_in[3]),
719 .offset = 0x01230000, .size = 0x10000,
720 },
721 {
722 .setup = ptp_ocp_fb_board_init,
723 .extra = &(struct ptp_ocp_servo_conf) {
724 .servo_offset_p = 0x2000,
725 .servo_offset_i = 0x1000,
726 .servo_drift_p = 0,
727 .servo_drift_i = 0,
728 },
729 },
730 { }
731 };
732
733 #define OCP_ART_CONFIG_SIZE 144
734 #define OCP_ART_TEMP_TABLE_SIZE 368
735
736 struct ocp_art_gpio_reg {
737 struct {
738 u32 gpio;
739 u32 __pad[3];
740 } map[4];
741 };
742
743 static struct ocp_resource ocp_art_resource[] = {
744 {
745 OCP_MEM_RESOURCE(reg),
746 .offset = 0x01000000, .size = 0x10000,
747 },
748 {
749 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
750 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
751 .extra = &(struct ptp_ocp_serial_port) {
752 .baud = 115200,
753 },
754 },
755 {
756 OCP_MEM_RESOURCE(art_sma),
757 .offset = 0x003C0000, .size = 0x1000,
758 },
759 /* Timestamp associated with GNSS1 receiver PPS */
760 {
761 OCP_EXT_RESOURCE(ts0),
762 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
763 .extra = &(struct ptp_ocp_ext_info) {
764 .index = 0,
765 .irq_fcn = ptp_ocp_ts_irq,
766 .enable = ptp_ocp_ts_enable,
767 },
768 },
769 {
770 OCP_EXT_RESOURCE(ts1),
771 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
772 .extra = &(struct ptp_ocp_ext_info) {
773 .index = 1,
774 .irq_fcn = ptp_ocp_ts_irq,
775 .enable = ptp_ocp_ts_enable,
776 },
777 },
778 {
779 OCP_EXT_RESOURCE(ts2),
780 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
781 .extra = &(struct ptp_ocp_ext_info) {
782 .index = 2,
783 .irq_fcn = ptp_ocp_ts_irq,
784 .enable = ptp_ocp_ts_enable,
785 },
786 },
787 {
788 OCP_EXT_RESOURCE(ts3),
789 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
790 .extra = &(struct ptp_ocp_ext_info) {
791 .index = 3,
792 .irq_fcn = ptp_ocp_ts_irq,
793 .enable = ptp_ocp_ts_enable,
794 },
795 },
796 {
797 OCP_EXT_RESOURCE(ts4),
798 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
799 .extra = &(struct ptp_ocp_ext_info) {
800 .index = 4,
801 .irq_fcn = ptp_ocp_ts_irq,
802 .enable = ptp_ocp_ts_enable,
803 },
804 },
805 /* Timestamp associated with Internal PPS of the card */
806 {
807 OCP_EXT_RESOURCE(pps),
808 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
809 .extra = &(struct ptp_ocp_ext_info) {
810 .index = 5,
811 .irq_fcn = ptp_ocp_ts_irq,
812 .enable = ptp_ocp_ts_enable,
813 },
814 },
815 {
816 OCP_SPI_RESOURCE(spi_flash),
817 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
818 .extra = &(struct ptp_ocp_flash_info) {
819 .name = "spi_altera", .pci_offset = 0,
820 .data_size = sizeof(struct altera_spi_platform_data),
821 .data = &(struct altera_spi_platform_data) {
822 .num_chipselect = 1,
823 .num_devices = 1,
824 .devices = &(struct spi_board_info) {
825 .modalias = "spi-nor",
826 },
827 },
828 },
829 },
830 {
831 OCP_I2C_RESOURCE(i2c_ctrl),
832 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
833 .extra = &(struct ptp_ocp_i2c_info) {
834 .name = "ocores-i2c",
835 .fixed_rate = 400000,
836 .data_size = sizeof(struct ocores_i2c_platform_data),
837 .data = &(struct ocores_i2c_platform_data) {
838 .clock_khz = 125000,
839 .bus_khz = 400,
840 .num_devices = 1,
841 .devices = &(struct i2c_board_info) {
842 I2C_BOARD_INFO("24c08", 0x50),
843 },
844 },
845 },
846 },
847 {
848 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
849 .offset = 0x00190000, .irq_vec = 7,
850 .extra = &(struct ptp_ocp_serial_port) {
851 .baud = 9600,
852 },
853 },
854 {
855 OCP_MEM_RESOURCE(board_config),
856 .offset = 0x210000, .size = 0x1000,
857 },
858 {
859 .setup = ptp_ocp_art_board_init,
860 .extra = &(struct ptp_ocp_servo_conf) {
861 .servo_offset_p = 0x2000,
862 .servo_offset_i = 0x1000,
863 .servo_drift_p = 0,
864 .servo_drift_i = 0,
865 },
866 },
867 { }
868 };
869
870 static struct ocp_resource ocp_adva_resource[] = {
871 {
872 OCP_MEM_RESOURCE(reg),
873 .offset = 0x01000000, .size = 0x10000,
874 },
875 {
876 OCP_EXT_RESOURCE(ts0),
877 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
878 .extra = &(struct ptp_ocp_ext_info) {
879 .index = 0,
880 .irq_fcn = ptp_ocp_ts_irq,
881 .enable = ptp_ocp_ts_enable,
882 },
883 },
884 {
885 OCP_EXT_RESOURCE(ts1),
886 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
887 .extra = &(struct ptp_ocp_ext_info) {
888 .index = 1,
889 .irq_fcn = ptp_ocp_ts_irq,
890 .enable = ptp_ocp_ts_enable,
891 },
892 },
893 {
894 OCP_EXT_RESOURCE(ts2),
895 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
896 .extra = &(struct ptp_ocp_ext_info) {
897 .index = 2,
898 .irq_fcn = ptp_ocp_ts_irq,
899 .enable = ptp_ocp_ts_enable,
900 },
901 },
902 /* Timestamp for PHC and/or PPS generator */
903 {
904 OCP_EXT_RESOURCE(pps),
905 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
906 .extra = &(struct ptp_ocp_ext_info) {
907 .index = 5,
908 .irq_fcn = ptp_ocp_ts_irq,
909 .enable = ptp_ocp_ts_enable,
910 },
911 },
912 {
913 OCP_EXT_RESOURCE(signal_out[0]),
914 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
915 .extra = &(struct ptp_ocp_ext_info) {
916 .index = 1,
917 .irq_fcn = ptp_ocp_signal_irq,
918 .enable = ptp_ocp_signal_enable,
919 },
920 },
921 {
922 OCP_EXT_RESOURCE(signal_out[1]),
923 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
924 .extra = &(struct ptp_ocp_ext_info) {
925 .index = 2,
926 .irq_fcn = ptp_ocp_signal_irq,
927 .enable = ptp_ocp_signal_enable,
928 },
929 },
930 {
931 OCP_MEM_RESOURCE(pps_to_ext),
932 .offset = 0x01030000, .size = 0x10000,
933 },
934 {
935 OCP_MEM_RESOURCE(pps_to_clk),
936 .offset = 0x01040000, .size = 0x10000,
937 },
938 {
939 OCP_MEM_RESOURCE(tod),
940 .offset = 0x01050000, .size = 0x10000,
941 },
942 {
943 OCP_MEM_RESOURCE(image),
944 .offset = 0x00020000, .size = 0x1000,
945 },
946 {
947 OCP_MEM_RESOURCE(pps_select),
948 .offset = 0x00130000, .size = 0x1000,
949 },
950 {
951 OCP_MEM_RESOURCE(sma_map1),
952 .offset = 0x00140000, .size = 0x1000,
953 },
954 {
955 OCP_MEM_RESOURCE(sma_map2),
956 .offset = 0x00220000, .size = 0x1000,
957 },
958 {
959 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
960 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
961 .extra = &(struct ptp_ocp_serial_port) {
962 .baud = 9600,
963 },
964 },
965 {
966 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
967 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
968 .extra = &(struct ptp_ocp_serial_port) {
969 .baud = 115200,
970 },
971 },
972 {
973 OCP_MEM_RESOURCE(freq_in[0]),
974 .offset = 0x01200000, .size = 0x10000,
975 },
976 {
977 OCP_MEM_RESOURCE(freq_in[1]),
978 .offset = 0x01210000, .size = 0x10000,
979 },
980 {
981 OCP_SPI_RESOURCE(spi_flash),
982 .offset = 0x00310400, .size = 0x10000, .irq_vec = 9,
983 .extra = &(struct ptp_ocp_flash_info) {
984 .name = "spi_altera", .pci_offset = 0,
985 .data_size = sizeof(struct altera_spi_platform_data),
986 .data = &(struct altera_spi_platform_data) {
987 .num_chipselect = 1,
988 .num_devices = 1,
989 .devices = &(struct spi_board_info) {
990 .modalias = "spi-nor",
991 },
992 },
993 },
994 },
995 {
996 OCP_I2C_RESOURCE(i2c_ctrl),
997 .offset = 0x150000, .size = 0x100, .irq_vec = 7,
998 .extra = &(struct ptp_ocp_i2c_info) {
999 .name = "ocores-i2c",
1000 .fixed_rate = 50000000,
1001 .data_size = sizeof(struct ocores_i2c_platform_data),
1002 .data = &(struct ocores_i2c_platform_data) {
1003 .clock_khz = 50000,
1004 .bus_khz = 100,
1005 .reg_io_width = 4, // 32-bit/4-byte
1006 .reg_shift = 2, // 32-bit addressing
1007 .num_devices = 2,
1008 .devices = (struct i2c_board_info[]) {
1009 { I2C_BOARD_INFO("24c02", 0x50) },
1010 { I2C_BOARD_INFO("24mac402", 0x58),
1011 .platform_data = "mac" },
1012 },
1013 },
1014 },
1015 },
1016 {
1017 .setup = ptp_ocp_adva_board_init,
1018 .extra = &(struct ptp_ocp_servo_conf) {
1019 .servo_offset_p = 0xc000,
1020 .servo_offset_i = 0x1000,
1021 .servo_drift_p = 0,
1022 .servo_drift_i = 0,
1023 },
1024 },
1025 { }
1026 };
1027
1028 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
1029 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
1030 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
1031 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
1032 { PCI_DEVICE_DATA(ADVA, TIMECARD, &ocp_adva_resource) },
1033 { }
1034 };
1035 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
1036
1037 static DEFINE_MUTEX(ptp_ocp_lock);
1038 static DEFINE_IDR(ptp_ocp_idr);
1039
1040 struct ocp_selector {
1041 const char *name;
1042 int value;
1043 u64 frequency;
1044 };
1045
1046 static const struct ocp_selector ptp_ocp_clock[] = {
1047 { .name = "NONE", .value = 0 },
1048 { .name = "TOD", .value = 1 },
1049 { .name = "IRIG", .value = 2 },
1050 { .name = "PPS", .value = 3 },
1051 { .name = "PTP", .value = 4 },
1052 { .name = "RTC", .value = 5 },
1053 { .name = "DCF", .value = 6 },
1054 { .name = "REGS", .value = 0xfe },
1055 { .name = "EXT", .value = 0xff },
1056 { }
1057 };
1058
1059 #define SMA_DISABLE BIT(16)
1060 #define SMA_ENABLE BIT(15)
1061 #define SMA_SELECT_MASK GENMASK(14, 0)
1062
1063 static const struct ocp_selector ptp_ocp_sma_in[] = {
1064 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1065 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1066 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1067 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1068 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1069 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1070 { .name = "DCF", .value = 0x0020, .frequency = 77500 },
1071 { .name = "TS3", .value = 0x0040, .frequency = 0 },
1072 { .name = "TS4", .value = 0x0080, .frequency = 0 },
1073 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1074 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1075 { .name = "FREQ3", .value = 0x0400, .frequency = 0 },
1076 { .name = "FREQ4", .value = 0x0800, .frequency = 0 },
1077 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1078 { }
1079 };
1080
1081 static const struct ocp_selector ptp_ocp_sma_out[] = {
1082 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1083 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1084 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1085 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1086 { .name = "GNSS2", .value = 0x0008, .frequency = 1 },
1087 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1088 { .name = "DCF", .value = 0x0020, .frequency = 77000 },
1089 { .name = "GEN1", .value = 0x0040 },
1090 { .name = "GEN2", .value = 0x0080 },
1091 { .name = "GEN3", .value = 0x0100 },
1092 { .name = "GEN4", .value = 0x0200 },
1093 { .name = "GND", .value = 0x2000 },
1094 { .name = "VCC", .value = 0x4000 },
1095 { }
1096 };
1097
1098 static const struct ocp_selector ptp_ocp_art_sma_in[] = {
1099 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1100 { .name = "10Mhz", .value = 0x0008, .frequency = 1000000 },
1101 { }
1102 };
1103
1104 static const struct ocp_selector ptp_ocp_art_sma_out[] = {
1105 { .name = "PHC", .value = 0x0002, .frequency = 1 },
1106 { .name = "GNSS", .value = 0x0004, .frequency = 1 },
1107 { .name = "10Mhz", .value = 0x0010, .frequency = 10000000 },
1108 { }
1109 };
1110
1111 static const struct ocp_selector ptp_ocp_adva_sma_in[] = {
1112 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1113 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1114 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1115 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1116 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1117 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1118 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1119 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1120 { }
1121 };
1122
1123 static const struct ocp_selector ptp_ocp_adva_sma_out[] = {
1124 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1125 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1126 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1127 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1128 { .name = "GEN1", .value = 0x0040 },
1129 { .name = "GEN2", .value = 0x0080 },
1130 { .name = "GND", .value = 0x2000 },
1131 { .name = "VCC", .value = 0x4000 },
1132 { }
1133 };
1134
1135 struct ocp_sma_op {
1136 const struct ocp_selector *tbl[2];
1137 void (*init)(struct ptp_ocp *bp);
1138 u32 (*get)(struct ptp_ocp *bp, int sma_nr);
1139 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
1140 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
1141 };
1142
1143 static void
ptp_ocp_sma_init(struct ptp_ocp * bp)1144 ptp_ocp_sma_init(struct ptp_ocp *bp)
1145 {
1146 return bp->sma_op->init(bp);
1147 }
1148
1149 static u32
ptp_ocp_sma_get(struct ptp_ocp * bp,int sma_nr)1150 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
1151 {
1152 return bp->sma_op->get(bp, sma_nr);
1153 }
1154
1155 static int
ptp_ocp_sma_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)1156 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
1157 {
1158 return bp->sma_op->set_inputs(bp, sma_nr, val);
1159 }
1160
1161 static int
ptp_ocp_sma_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)1162 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
1163 {
1164 return bp->sma_op->set_output(bp, sma_nr, val);
1165 }
1166
1167 static const char *
ptp_ocp_select_name_from_val(const struct ocp_selector * tbl,int val)1168 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
1169 {
1170 int i;
1171
1172 for (i = 0; tbl[i].name; i++)
1173 if (tbl[i].value == val)
1174 return tbl[i].name;
1175 return NULL;
1176 }
1177
1178 static int
ptp_ocp_select_val_from_name(const struct ocp_selector * tbl,const char * name)1179 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
1180 {
1181 const char *select;
1182 int i;
1183
1184 for (i = 0; tbl[i].name; i++) {
1185 select = tbl[i].name;
1186 if (!strncasecmp(name, select, strlen(select)))
1187 return tbl[i].value;
1188 }
1189 return -EINVAL;
1190 }
1191
1192 static ssize_t
ptp_ocp_select_table_show(const struct ocp_selector * tbl,char * buf)1193 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
1194 {
1195 ssize_t count;
1196 int i;
1197
1198 count = 0;
1199 for (i = 0; tbl[i].name; i++)
1200 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
1201 if (count)
1202 count--;
1203 count += sysfs_emit_at(buf, count, "\n");
1204 return count;
1205 }
1206
1207 static int
__ptp_ocp_gettime_locked(struct ptp_ocp * bp,struct timespec64 * ts,struct ptp_system_timestamp * sts)1208 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
1209 struct ptp_system_timestamp *sts)
1210 {
1211 u32 ctrl, time_sec, time_ns;
1212 int i;
1213
1214 ptp_read_system_prets(sts);
1215
1216 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1217 iowrite32(ctrl, &bp->reg->ctrl);
1218
1219 for (i = 0; i < 100; i++) {
1220 ctrl = ioread32(&bp->reg->ctrl);
1221 if (ctrl & OCP_CTRL_READ_TIME_DONE)
1222 break;
1223 }
1224 ptp_read_system_postts(sts);
1225
1226 if (sts && bp->ts_window_adjust) {
1227 s64 ns = timespec64_to_ns(&sts->post_ts);
1228
1229 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
1230 }
1231
1232 time_ns = ioread32(&bp->reg->time_ns);
1233 time_sec = ioread32(&bp->reg->time_sec);
1234
1235 ts->tv_sec = time_sec;
1236 ts->tv_nsec = time_ns;
1237
1238 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1239 }
1240
1241 static int
ptp_ocp_gettimex(struct ptp_clock_info * ptp_info,struct timespec64 * ts,struct ptp_system_timestamp * sts)1242 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1243 struct ptp_system_timestamp *sts)
1244 {
1245 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1246 unsigned long flags;
1247 int err;
1248
1249 spin_lock_irqsave(&bp->lock, flags);
1250 err = __ptp_ocp_gettime_locked(bp, ts, sts);
1251 spin_unlock_irqrestore(&bp->lock, flags);
1252
1253 return err;
1254 }
1255
1256 static void
__ptp_ocp_settime_locked(struct ptp_ocp * bp,const struct timespec64 * ts)1257 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1258 {
1259 u32 ctrl, time_sec, time_ns;
1260 u32 select;
1261
1262 time_ns = ts->tv_nsec;
1263 time_sec = ts->tv_sec;
1264
1265 select = ioread32(&bp->reg->select);
1266 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1267
1268 iowrite32(time_ns, &bp->reg->adjust_ns);
1269 iowrite32(time_sec, &bp->reg->adjust_sec);
1270
1271 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1272 iowrite32(ctrl, &bp->reg->ctrl);
1273
1274 /* restore clock selection */
1275 iowrite32(select >> 16, &bp->reg->select);
1276 }
1277
1278 static int
ptp_ocp_settime(struct ptp_clock_info * ptp_info,const struct timespec64 * ts)1279 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1280 {
1281 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1282 unsigned long flags;
1283
1284 spin_lock_irqsave(&bp->lock, flags);
1285 __ptp_ocp_settime_locked(bp, ts);
1286 spin_unlock_irqrestore(&bp->lock, flags);
1287
1288 return 0;
1289 }
1290
1291 static void
__ptp_ocp_adjtime_locked(struct ptp_ocp * bp,u32 adj_val)1292 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1293 {
1294 u32 select, ctrl;
1295
1296 select = ioread32(&bp->reg->select);
1297 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1298
1299 iowrite32(adj_val, &bp->reg->offset_ns);
1300 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1301
1302 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1303 iowrite32(ctrl, &bp->reg->ctrl);
1304
1305 /* restore clock selection */
1306 iowrite32(select >> 16, &bp->reg->select);
1307 }
1308
1309 static void
ptp_ocp_adjtime_coarse(struct ptp_ocp * bp,s64 delta_ns)1310 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1311 {
1312 struct timespec64 ts;
1313 unsigned long flags;
1314 int err;
1315
1316 spin_lock_irqsave(&bp->lock, flags);
1317 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1318 if (likely(!err)) {
1319 set_normalized_timespec64(&ts, ts.tv_sec,
1320 ts.tv_nsec + delta_ns);
1321 __ptp_ocp_settime_locked(bp, &ts);
1322 }
1323 spin_unlock_irqrestore(&bp->lock, flags);
1324 }
1325
1326 static int
ptp_ocp_adjtime(struct ptp_clock_info * ptp_info,s64 delta_ns)1327 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1328 {
1329 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1330 unsigned long flags;
1331 u32 adj_ns, sign;
1332
1333 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1334 ptp_ocp_adjtime_coarse(bp, delta_ns);
1335 return 0;
1336 }
1337
1338 sign = delta_ns < 0 ? BIT(31) : 0;
1339 adj_ns = sign ? -delta_ns : delta_ns;
1340
1341 spin_lock_irqsave(&bp->lock, flags);
1342 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1343 spin_unlock_irqrestore(&bp->lock, flags);
1344
1345 return 0;
1346 }
1347
1348 static int
ptp_ocp_null_adjfine(struct ptp_clock_info * ptp_info,long scaled_ppm)1349 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1350 {
1351 if (scaled_ppm == 0)
1352 return 0;
1353
1354 return -EOPNOTSUPP;
1355 }
1356
1357 static s32
ptp_ocp_null_getmaxphase(struct ptp_clock_info * ptp_info)1358 ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info)
1359 {
1360 return 0;
1361 }
1362
1363 static int
ptp_ocp_null_adjphase(struct ptp_clock_info * ptp_info,s32 phase_ns)1364 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1365 {
1366 return -EOPNOTSUPP;
1367 }
1368
1369 static int
ptp_ocp_enable(struct ptp_clock_info * ptp_info,struct ptp_clock_request * rq,int on)1370 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1371 int on)
1372 {
1373 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1374 struct ptp_ocp_ext_src *ext = NULL;
1375 u32 req;
1376 int err;
1377
1378 switch (rq->type) {
1379 case PTP_CLK_REQ_EXTTS:
1380 req = OCP_REQ_TIMESTAMP;
1381 switch (rq->extts.index) {
1382 case 0:
1383 ext = bp->ts0;
1384 break;
1385 case 1:
1386 ext = bp->ts1;
1387 break;
1388 case 2:
1389 ext = bp->ts2;
1390 break;
1391 case 3:
1392 ext = bp->ts3;
1393 break;
1394 case 4:
1395 ext = bp->ts4;
1396 break;
1397 case 5:
1398 ext = bp->pps;
1399 break;
1400 }
1401 break;
1402 case PTP_CLK_REQ_PPS:
1403 req = OCP_REQ_PPS;
1404 ext = bp->pps;
1405 break;
1406 case PTP_CLK_REQ_PEROUT:
1407 switch (rq->perout.index) {
1408 case 0:
1409 /* This is a request for 1PPS on an output SMA.
1410 * Allow, but assume manual configuration.
1411 */
1412 if (on && (rq->perout.period.sec != 1 ||
1413 rq->perout.period.nsec != 0))
1414 return -EINVAL;
1415 return 0;
1416 case 1:
1417 case 2:
1418 case 3:
1419 case 4:
1420 req = rq->perout.index - 1;
1421 ext = bp->signal_out[req];
1422 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1423 if (err)
1424 return err;
1425 break;
1426 }
1427 break;
1428 default:
1429 return -EOPNOTSUPP;
1430 }
1431
1432 err = -ENXIO;
1433 if (ext)
1434 err = ext->info->enable(ext, req, on);
1435
1436 return err;
1437 }
1438
1439 static int
ptp_ocp_verify(struct ptp_clock_info * ptp_info,unsigned pin,enum ptp_pin_function func,unsigned chan)1440 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1441 enum ptp_pin_function func, unsigned chan)
1442 {
1443 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1444 char buf[16];
1445
1446 switch (func) {
1447 case PTP_PF_NONE:
1448 snprintf(buf, sizeof(buf), "IN: None");
1449 break;
1450 case PTP_PF_EXTTS:
1451 /* Allow timestamps, but require sysfs configuration. */
1452 return 0;
1453 case PTP_PF_PEROUT:
1454 /* channel 0 is 1PPS from PHC.
1455 * channels 1..4 are the frequency generators.
1456 */
1457 if (chan)
1458 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1459 else
1460 snprintf(buf, sizeof(buf), "OUT: PHC");
1461 break;
1462 default:
1463 return -EOPNOTSUPP;
1464 }
1465
1466 return ptp_ocp_sma_store(bp, buf, pin + 1);
1467 }
1468
1469 static const struct ptp_clock_info ptp_ocp_clock_info = {
1470 .owner = THIS_MODULE,
1471 .name = KBUILD_MODNAME,
1472 .max_adj = 100000000,
1473 .gettimex64 = ptp_ocp_gettimex,
1474 .settime64 = ptp_ocp_settime,
1475 .adjtime = ptp_ocp_adjtime,
1476 .adjfine = ptp_ocp_null_adjfine,
1477 .adjphase = ptp_ocp_null_adjphase,
1478 .getmaxphase = ptp_ocp_null_getmaxphase,
1479 .enable = ptp_ocp_enable,
1480 .verify = ptp_ocp_verify,
1481 .pps = true,
1482 .n_ext_ts = 6,
1483 .n_per_out = 5,
1484 };
1485
1486 static void
__ptp_ocp_clear_drift_locked(struct ptp_ocp * bp)1487 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1488 {
1489 u32 ctrl, select;
1490
1491 select = ioread32(&bp->reg->select);
1492 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1493
1494 iowrite32(0, &bp->reg->drift_ns);
1495
1496 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1497 iowrite32(ctrl, &bp->reg->ctrl);
1498
1499 /* restore clock selection */
1500 iowrite32(select >> 16, &bp->reg->select);
1501 }
1502
1503 static void
ptp_ocp_utc_distribute(struct ptp_ocp * bp,u32 val)1504 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1505 {
1506 unsigned long flags;
1507
1508 spin_lock_irqsave(&bp->lock, flags);
1509
1510 bp->utc_tai_offset = val;
1511
1512 if (bp->irig_out)
1513 iowrite32(val, &bp->irig_out->adj_sec);
1514 if (bp->dcf_out)
1515 iowrite32(val, &bp->dcf_out->adj_sec);
1516 if (bp->nmea_out)
1517 iowrite32(val, &bp->nmea_out->adj_sec);
1518
1519 spin_unlock_irqrestore(&bp->lock, flags);
1520 }
1521
1522 static void
ptp_ocp_watchdog(struct timer_list * t)1523 ptp_ocp_watchdog(struct timer_list *t)
1524 {
1525 struct ptp_ocp *bp = from_timer(bp, t, watchdog);
1526 unsigned long flags;
1527 u32 status, utc_offset;
1528
1529 status = ioread32(&bp->pps_to_clk->status);
1530
1531 if (status & PPS_STATUS_SUPERV_ERR) {
1532 iowrite32(status, &bp->pps_to_clk->status);
1533 if (!bp->gnss_lost) {
1534 spin_lock_irqsave(&bp->lock, flags);
1535 __ptp_ocp_clear_drift_locked(bp);
1536 spin_unlock_irqrestore(&bp->lock, flags);
1537 bp->gnss_lost = ktime_get_real_seconds();
1538 }
1539
1540 } else if (bp->gnss_lost) {
1541 bp->gnss_lost = 0;
1542 }
1543
1544 /* if GNSS provides correct data we can rely on
1545 * it to get leap second information
1546 */
1547 if (bp->tod) {
1548 status = ioread32(&bp->tod->utc_status);
1549 utc_offset = status & TOD_STATUS_UTC_MASK;
1550 if (status & TOD_STATUS_UTC_VALID &&
1551 utc_offset != bp->utc_tai_offset)
1552 ptp_ocp_utc_distribute(bp, utc_offset);
1553 }
1554
1555 mod_timer(&bp->watchdog, jiffies + HZ);
1556 }
1557
1558 static void
ptp_ocp_estimate_pci_timing(struct ptp_ocp * bp)1559 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1560 {
1561 ktime_t start, end, delay = U64_MAX;
1562 u32 ctrl;
1563 int i;
1564
1565 for (i = 0; i < 3; i++) {
1566 ctrl = ioread32(&bp->reg->ctrl);
1567 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1568
1569 iowrite32(ctrl, &bp->reg->ctrl);
1570
1571 start = ktime_get_raw_ns();
1572
1573 ctrl = ioread32(&bp->reg->ctrl);
1574
1575 end = ktime_get_raw_ns();
1576
1577 delay = min(delay, end - start);
1578 }
1579 bp->ts_window_adjust = (delay >> 5) * 3;
1580 }
1581
1582 static int
ptp_ocp_init_clock(struct ptp_ocp * bp,struct ptp_ocp_servo_conf * servo_conf)1583 ptp_ocp_init_clock(struct ptp_ocp *bp, struct ptp_ocp_servo_conf *servo_conf)
1584 {
1585 struct timespec64 ts;
1586 u32 ctrl;
1587
1588 ctrl = OCP_CTRL_ENABLE;
1589 iowrite32(ctrl, &bp->reg->ctrl);
1590
1591 /* servo configuration */
1592 iowrite32(servo_conf->servo_offset_p, &bp->reg->servo_offset_p);
1593 iowrite32(servo_conf->servo_offset_i, &bp->reg->servo_offset_i);
1594 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_p);
1595 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_i);
1596
1597 /* latch servo values */
1598 ctrl |= OCP_CTRL_ADJUST_SERVO;
1599 iowrite32(ctrl, &bp->reg->ctrl);
1600
1601 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1602 dev_err(&bp->pdev->dev, "clock not enabled\n");
1603 return -ENODEV;
1604 }
1605
1606 ptp_ocp_estimate_pci_timing(bp);
1607
1608 bp->sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1609 if (!bp->sync) {
1610 ktime_get_clocktai_ts64(&ts);
1611 ptp_ocp_settime(&bp->ptp_info, &ts);
1612 }
1613
1614 /* If there is a clock supervisor, then enable the watchdog */
1615 if (bp->pps_to_clk) {
1616 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1617 mod_timer(&bp->watchdog, jiffies + HZ);
1618 }
1619
1620 return 0;
1621 }
1622
1623 static void
ptp_ocp_tod_init(struct ptp_ocp * bp)1624 ptp_ocp_tod_init(struct ptp_ocp *bp)
1625 {
1626 u32 ctrl, reg;
1627
1628 ctrl = ioread32(&bp->tod->ctrl);
1629 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1630 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1631 iowrite32(ctrl, &bp->tod->ctrl);
1632
1633 reg = ioread32(&bp->tod->utc_status);
1634 if (reg & TOD_STATUS_UTC_VALID)
1635 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1636 }
1637
1638 static const char *
ptp_ocp_tod_proto_name(const int idx)1639 ptp_ocp_tod_proto_name(const int idx)
1640 {
1641 static const char * const proto_name[] = {
1642 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1643 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1644 };
1645 return proto_name[idx];
1646 }
1647
1648 static const char *
ptp_ocp_tod_gnss_name(int idx)1649 ptp_ocp_tod_gnss_name(int idx)
1650 {
1651 static const char * const gnss_name[] = {
1652 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1653 "Unknown"
1654 };
1655 if (idx >= ARRAY_SIZE(gnss_name))
1656 idx = ARRAY_SIZE(gnss_name) - 1;
1657 return gnss_name[idx];
1658 }
1659
1660 static const char *
ptp_ocp_tty_port_name(int idx)1661 ptp_ocp_tty_port_name(int idx)
1662 {
1663 static const char * const tty_name[] = {
1664 "GNSS", "GNSS2", "MAC", "NMEA"
1665 };
1666 return tty_name[idx];
1667 }
1668
1669 struct ptp_ocp_nvmem_match_info {
1670 struct ptp_ocp *bp;
1671 const void * const tag;
1672 };
1673
1674 static int
ptp_ocp_nvmem_match(struct device * dev,const void * data)1675 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1676 {
1677 const struct ptp_ocp_nvmem_match_info *info = data;
1678
1679 dev = dev->parent;
1680 if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1681 return 0;
1682
1683 while ((dev = dev->parent))
1684 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1685 return info->bp == dev_get_drvdata(dev);
1686 return 0;
1687 }
1688
1689 static inline struct nvmem_device *
ptp_ocp_nvmem_device_get(struct ptp_ocp * bp,const void * const tag)1690 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1691 {
1692 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1693
1694 return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1695 }
1696
1697 static inline void
ptp_ocp_nvmem_device_put(struct nvmem_device ** nvmemp)1698 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1699 {
1700 if (!IS_ERR_OR_NULL(*nvmemp))
1701 nvmem_device_put(*nvmemp);
1702 *nvmemp = NULL;
1703 }
1704
1705 static void
ptp_ocp_read_eeprom(struct ptp_ocp * bp)1706 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1707 {
1708 const struct ptp_ocp_eeprom_map *map;
1709 struct nvmem_device *nvmem;
1710 const void *tag;
1711 int ret;
1712
1713 if (!bp->i2c_ctrl)
1714 return;
1715
1716 tag = NULL;
1717 nvmem = NULL;
1718
1719 for (map = bp->eeprom_map; map->len; map++) {
1720 if (map->tag != tag) {
1721 tag = map->tag;
1722 ptp_ocp_nvmem_device_put(&nvmem);
1723 }
1724 if (!nvmem) {
1725 nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1726 if (IS_ERR(nvmem)) {
1727 ret = PTR_ERR(nvmem);
1728 goto fail;
1729 }
1730 }
1731 ret = nvmem_device_read(nvmem, map->off, map->len,
1732 BP_MAP_ENTRY_ADDR(bp, map));
1733 if (ret != map->len)
1734 goto fail;
1735 }
1736
1737 bp->has_eeprom_data = true;
1738
1739 out:
1740 ptp_ocp_nvmem_device_put(&nvmem);
1741 return;
1742
1743 fail:
1744 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
1745 goto out;
1746 }
1747
1748 static struct device *
ptp_ocp_find_flash(struct ptp_ocp * bp)1749 ptp_ocp_find_flash(struct ptp_ocp *bp)
1750 {
1751 struct device *dev, *last;
1752
1753 last = NULL;
1754 dev = &bp->spi_flash->dev;
1755
1756 while ((dev = device_find_any_child(dev))) {
1757 if (!strcmp("mtd", dev_bus_name(dev)))
1758 break;
1759 put_device(last);
1760 last = dev;
1761 }
1762 put_device(last);
1763
1764 return dev;
1765 }
1766
1767 static int
ptp_ocp_devlink_fw_image(struct devlink * devlink,const struct firmware * fw,const u8 ** data,size_t * size)1768 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
1769 const u8 **data, size_t *size)
1770 {
1771 struct ptp_ocp *bp = devlink_priv(devlink);
1772 const struct ptp_ocp_firmware_header *hdr;
1773 size_t offset, length;
1774 u16 crc;
1775
1776 hdr = (const struct ptp_ocp_firmware_header *)fw->data;
1777 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
1778 devlink_flash_update_status_notify(devlink,
1779 "No firmware header found, cancel firmware upgrade",
1780 NULL, 0, 0);
1781 return -EINVAL;
1782 }
1783
1784 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
1785 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
1786 devlink_flash_update_status_notify(devlink,
1787 "Firmware image compatibility check failed",
1788 NULL, 0, 0);
1789 return -EINVAL;
1790 }
1791
1792 offset = sizeof(*hdr);
1793 length = be32_to_cpu(hdr->image_size);
1794 if (length != (fw->size - offset)) {
1795 devlink_flash_update_status_notify(devlink,
1796 "Firmware image size check failed",
1797 NULL, 0, 0);
1798 return -EINVAL;
1799 }
1800
1801 crc = crc16(0xffff, &fw->data[offset], length);
1802 if (be16_to_cpu(hdr->crc) != crc) {
1803 devlink_flash_update_status_notify(devlink,
1804 "Firmware image CRC check failed",
1805 NULL, 0, 0);
1806 return -EINVAL;
1807 }
1808
1809 *data = &fw->data[offset];
1810 *size = length;
1811
1812 return 0;
1813 }
1814
1815 static int
ptp_ocp_devlink_flash(struct devlink * devlink,struct device * dev,const struct firmware * fw)1816 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1817 const struct firmware *fw)
1818 {
1819 struct mtd_info *mtd = dev_get_drvdata(dev);
1820 struct ptp_ocp *bp = devlink_priv(devlink);
1821 size_t off, len, size, resid, wrote;
1822 struct erase_info erase;
1823 size_t base, blksz;
1824 const u8 *data;
1825 int err;
1826
1827 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
1828 if (err)
1829 goto out;
1830
1831 off = 0;
1832 base = bp->flash_start;
1833 blksz = 4096;
1834 resid = size;
1835
1836 while (resid) {
1837 devlink_flash_update_status_notify(devlink, "Flashing",
1838 NULL, off, size);
1839
1840 len = min_t(size_t, resid, blksz);
1841 erase.addr = base + off;
1842 erase.len = blksz;
1843
1844 err = mtd_erase(mtd, &erase);
1845 if (err)
1846 goto out;
1847
1848 err = mtd_write(mtd, base + off, len, &wrote, data + off);
1849 if (err)
1850 goto out;
1851
1852 off += blksz;
1853 resid -= len;
1854 }
1855 out:
1856 return err;
1857 }
1858
1859 static int
ptp_ocp_devlink_flash_update(struct devlink * devlink,struct devlink_flash_update_params * params,struct netlink_ext_ack * extack)1860 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1861 struct devlink_flash_update_params *params,
1862 struct netlink_ext_ack *extack)
1863 {
1864 struct ptp_ocp *bp = devlink_priv(devlink);
1865 struct device *dev;
1866 const char *msg;
1867 int err;
1868
1869 dev = ptp_ocp_find_flash(bp);
1870 if (!dev) {
1871 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1872 return -ENODEV;
1873 }
1874
1875 devlink_flash_update_status_notify(devlink, "Preparing to flash",
1876 NULL, 0, 0);
1877
1878 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1879
1880 msg = err ? "Flash error" : "Flash complete";
1881 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1882
1883 put_device(dev);
1884 return err;
1885 }
1886
1887 static int
ptp_ocp_devlink_info_get(struct devlink * devlink,struct devlink_info_req * req,struct netlink_ext_ack * extack)1888 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1889 struct netlink_ext_ack *extack)
1890 {
1891 struct ptp_ocp *bp = devlink_priv(devlink);
1892 const char *fw_image;
1893 char buf[32];
1894 int err;
1895
1896 fw_image = bp->fw_loader ? "loader" : "fw";
1897 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
1898 err = devlink_info_version_running_put(req, fw_image, buf);
1899 if (err)
1900 return err;
1901
1902 if (!bp->has_eeprom_data) {
1903 ptp_ocp_read_eeprom(bp);
1904 if (!bp->has_eeprom_data)
1905 return 0;
1906 }
1907
1908 sprintf(buf, "%pM", bp->serial);
1909 err = devlink_info_serial_number_put(req, buf);
1910 if (err)
1911 return err;
1912
1913 err = devlink_info_version_fixed_put(req,
1914 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
1915 bp->board_id);
1916 if (err)
1917 return err;
1918
1919 return 0;
1920 }
1921
1922 static const struct devlink_ops ptp_ocp_devlink_ops = {
1923 .flash_update = ptp_ocp_devlink_flash_update,
1924 .info_get = ptp_ocp_devlink_info_get,
1925 };
1926
1927 static void __iomem *
__ptp_ocp_get_mem(struct ptp_ocp * bp,resource_size_t start,int size)1928 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
1929 {
1930 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1931
1932 return devm_ioremap_resource(&bp->pdev->dev, &res);
1933 }
1934
1935 static void __iomem *
ptp_ocp_get_mem(struct ptp_ocp * bp,struct ocp_resource * r)1936 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1937 {
1938 resource_size_t start;
1939
1940 start = pci_resource_start(bp->pdev, 0) + r->offset;
1941 return __ptp_ocp_get_mem(bp, start, r->size);
1942 }
1943
1944 static int
ptp_ocp_register_spi(struct ptp_ocp * bp,struct ocp_resource * r)1945 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1946 {
1947 struct ptp_ocp_flash_info *info;
1948 struct pci_dev *pdev = bp->pdev;
1949 struct platform_device *p;
1950 struct resource res[2];
1951 resource_size_t start;
1952 int id;
1953
1954 start = pci_resource_start(pdev, 0) + r->offset;
1955 res[0] = DEFINE_RES_MEM(start, r->size);
1956 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
1957
1958 info = r->extra;
1959 id = pci_dev_id(pdev) << 1;
1960 id += info->pci_offset;
1961
1962 p = platform_device_register_resndata(&pdev->dev, info->name, id,
1963 res, ARRAY_SIZE(res), info->data,
1964 info->data_size);
1965 if (IS_ERR(p))
1966 return PTR_ERR(p);
1967
1968 bp_assign_entry(bp, r, p);
1969
1970 return 0;
1971 }
1972
1973 static struct platform_device *
ptp_ocp_i2c_bus(struct pci_dev * pdev,struct ocp_resource * r,int id)1974 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1975 {
1976 struct ptp_ocp_i2c_info *info;
1977 struct resource res[2];
1978 resource_size_t start;
1979
1980 info = r->extra;
1981 start = pci_resource_start(pdev, 0) + r->offset;
1982 res[0] = DEFINE_RES_MEM(start, r->size);
1983 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
1984
1985 return platform_device_register_resndata(&pdev->dev, info->name,
1986 id, res, ARRAY_SIZE(res),
1987 info->data, info->data_size);
1988 }
1989
1990 static int
ptp_ocp_register_i2c(struct ptp_ocp * bp,struct ocp_resource * r)1991 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1992 {
1993 struct pci_dev *pdev = bp->pdev;
1994 struct ptp_ocp_i2c_info *info;
1995 struct platform_device *p;
1996 struct clk_hw *clk;
1997 char buf[32];
1998 int id;
1999
2000 info = r->extra;
2001 id = pci_dev_id(bp->pdev);
2002
2003 sprintf(buf, "AXI.%d", id);
2004 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
2005 info->fixed_rate);
2006 if (IS_ERR(clk))
2007 return PTR_ERR(clk);
2008 bp->i2c_clk = clk;
2009
2010 sprintf(buf, "%s.%d", info->name, id);
2011 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
2012 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
2013 if (IS_ERR(p))
2014 return PTR_ERR(p);
2015
2016 bp_assign_entry(bp, r, p);
2017
2018 return 0;
2019 }
2020
2021 /* The expectation is that this is triggered only on error. */
2022 static irqreturn_t
ptp_ocp_signal_irq(int irq,void * priv)2023 ptp_ocp_signal_irq(int irq, void *priv)
2024 {
2025 struct ptp_ocp_ext_src *ext = priv;
2026 struct signal_reg __iomem *reg = ext->mem;
2027 struct ptp_ocp *bp = ext->bp;
2028 u32 enable, status;
2029 int gen;
2030
2031 gen = ext->info->index - 1;
2032
2033 enable = ioread32(®->enable);
2034 status = ioread32(®->status);
2035
2036 /* disable generator on error */
2037 if (status || !enable) {
2038 iowrite32(0, ®->intr_mask);
2039 iowrite32(0, ®->enable);
2040 bp->signal[gen].running = false;
2041 }
2042
2043 iowrite32(0, ®->intr); /* ack interrupt */
2044
2045 return IRQ_HANDLED;
2046 }
2047
2048 static int
ptp_ocp_signal_set(struct ptp_ocp * bp,int gen,struct ptp_ocp_signal * s)2049 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
2050 {
2051 struct ptp_system_timestamp sts;
2052 struct timespec64 ts;
2053 ktime_t start_ns;
2054 int err;
2055
2056 if (!s->period)
2057 return 0;
2058
2059 if (!s->pulse)
2060 s->pulse = ktime_divns(s->period * s->duty, 100);
2061
2062 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
2063 if (err)
2064 return err;
2065
2066 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
2067 if (!s->start) {
2068 /* roundup() does not work on 32-bit systems */
2069 s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
2070 s->start = ktime_add(s->start, s->phase);
2071 }
2072
2073 if (s->duty < 1 || s->duty > 99)
2074 return -EINVAL;
2075
2076 if (s->pulse < 1 || s->pulse > s->period)
2077 return -EINVAL;
2078
2079 if (s->start < start_ns)
2080 return -EINVAL;
2081
2082 bp->signal[gen] = *s;
2083
2084 return 0;
2085 }
2086
2087 static int
ptp_ocp_signal_from_perout(struct ptp_ocp * bp,int gen,struct ptp_perout_request * req)2088 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
2089 struct ptp_perout_request *req)
2090 {
2091 struct ptp_ocp_signal s = { };
2092
2093 if (req->flags & ~(PTP_PEROUT_DUTY_CYCLE |
2094 PTP_PEROUT_PHASE))
2095 return -EOPNOTSUPP;
2096
2097 s.polarity = bp->signal[gen].polarity;
2098 s.period = ktime_set(req->period.sec, req->period.nsec);
2099 if (!s.period)
2100 return 0;
2101
2102 if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
2103 s.pulse = ktime_set(req->on.sec, req->on.nsec);
2104 s.duty = ktime_divns(s.pulse * 100, s.period);
2105 }
2106
2107 if (req->flags & PTP_PEROUT_PHASE)
2108 s.phase = ktime_set(req->phase.sec, req->phase.nsec);
2109 else
2110 s.start = ktime_set(req->start.sec, req->start.nsec);
2111
2112 return ptp_ocp_signal_set(bp, gen, &s);
2113 }
2114
2115 static int
ptp_ocp_signal_enable(void * priv,u32 req,bool enable)2116 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
2117 {
2118 struct ptp_ocp_ext_src *ext = priv;
2119 struct signal_reg __iomem *reg = ext->mem;
2120 struct ptp_ocp *bp = ext->bp;
2121 struct timespec64 ts;
2122 int gen;
2123
2124 gen = ext->info->index - 1;
2125
2126 iowrite32(0, ®->intr_mask);
2127 iowrite32(0, ®->enable);
2128 bp->signal[gen].running = false;
2129 if (!enable)
2130 return 0;
2131
2132 ts = ktime_to_timespec64(bp->signal[gen].start);
2133 iowrite32(ts.tv_sec, ®->start_sec);
2134 iowrite32(ts.tv_nsec, ®->start_ns);
2135
2136 ts = ktime_to_timespec64(bp->signal[gen].period);
2137 iowrite32(ts.tv_sec, ®->period_sec);
2138 iowrite32(ts.tv_nsec, ®->period_ns);
2139
2140 ts = ktime_to_timespec64(bp->signal[gen].pulse);
2141 iowrite32(ts.tv_sec, ®->pulse_sec);
2142 iowrite32(ts.tv_nsec, ®->pulse_ns);
2143
2144 iowrite32(bp->signal[gen].polarity, ®->polarity);
2145 iowrite32(0, ®->repeat_count);
2146
2147 iowrite32(0, ®->intr); /* clear interrupt state */
2148 iowrite32(1, ®->intr_mask); /* enable interrupt */
2149 iowrite32(3, ®->enable); /* valid & enable */
2150
2151 bp->signal[gen].running = true;
2152
2153 return 0;
2154 }
2155
2156 static irqreturn_t
ptp_ocp_ts_irq(int irq,void * priv)2157 ptp_ocp_ts_irq(int irq, void *priv)
2158 {
2159 struct ptp_ocp_ext_src *ext = priv;
2160 struct ts_reg __iomem *reg = ext->mem;
2161 struct ptp_clock_event ev;
2162 u32 sec, nsec;
2163
2164 if (ext == ext->bp->pps) {
2165 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
2166 ev.type = PTP_CLOCK_PPS;
2167 ptp_clock_event(ext->bp->ptp, &ev);
2168 }
2169
2170 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
2171 goto out;
2172 }
2173
2174 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
2175 sec = ioread32(®->time_sec);
2176 nsec = ioread32(®->time_ns);
2177
2178 ev.type = PTP_CLOCK_EXTTS;
2179 ev.index = ext->info->index;
2180 ev.timestamp = sec * NSEC_PER_SEC + nsec;
2181
2182 ptp_clock_event(ext->bp->ptp, &ev);
2183
2184 out:
2185 iowrite32(1, ®->intr); /* write 1 to ack */
2186
2187 return IRQ_HANDLED;
2188 }
2189
2190 static int
ptp_ocp_ts_enable(void * priv,u32 req,bool enable)2191 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
2192 {
2193 struct ptp_ocp_ext_src *ext = priv;
2194 struct ts_reg __iomem *reg = ext->mem;
2195 struct ptp_ocp *bp = ext->bp;
2196
2197 if (ext == bp->pps) {
2198 u32 old_map = bp->pps_req_map;
2199
2200 if (enable)
2201 bp->pps_req_map |= req;
2202 else
2203 bp->pps_req_map &= ~req;
2204
2205 /* if no state change, just return */
2206 if ((!!old_map ^ !!bp->pps_req_map) == 0)
2207 return 0;
2208 }
2209
2210 if (enable) {
2211 iowrite32(1, ®->enable);
2212 iowrite32(1, ®->intr_mask);
2213 iowrite32(1, ®->intr);
2214 } else {
2215 iowrite32(0, ®->intr_mask);
2216 iowrite32(0, ®->enable);
2217 }
2218
2219 return 0;
2220 }
2221
2222 static void
ptp_ocp_unregister_ext(struct ptp_ocp_ext_src * ext)2223 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
2224 {
2225 ext->info->enable(ext, ~0, false);
2226 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
2227 kfree(ext);
2228 }
2229
2230 static int
ptp_ocp_register_ext(struct ptp_ocp * bp,struct ocp_resource * r)2231 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
2232 {
2233 struct pci_dev *pdev = bp->pdev;
2234 struct ptp_ocp_ext_src *ext;
2235 int err;
2236
2237 ext = kzalloc(sizeof(*ext), GFP_KERNEL);
2238 if (!ext)
2239 return -ENOMEM;
2240
2241 ext->mem = ptp_ocp_get_mem(bp, r);
2242 if (IS_ERR(ext->mem)) {
2243 err = PTR_ERR(ext->mem);
2244 goto out;
2245 }
2246
2247 ext->bp = bp;
2248 ext->info = r->extra;
2249 ext->irq_vec = r->irq_vec;
2250
2251 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2252 ext, "ocp%d.%s", bp->id, r->name);
2253 if (err) {
2254 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2255 goto out;
2256 }
2257
2258 bp_assign_entry(bp, r, ext);
2259
2260 return 0;
2261
2262 out:
2263 kfree(ext);
2264 return err;
2265 }
2266
2267 static int
ptp_ocp_serial_line(struct ptp_ocp * bp,struct ocp_resource * r)2268 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2269 {
2270 struct pci_dev *pdev = bp->pdev;
2271 struct uart_8250_port uart;
2272
2273 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2274 * the serial port device claim and release the pci resource.
2275 */
2276 memset(&uart, 0, sizeof(uart));
2277 uart.port.dev = &pdev->dev;
2278 uart.port.iotype = UPIO_MEM;
2279 uart.port.regshift = 2;
2280 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2281 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2282 uart.port.uartclk = 50000000;
2283 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2284 uart.port.type = PORT_16550A;
2285
2286 return serial8250_register_8250_port(&uart);
2287 }
2288
2289 static int
ptp_ocp_register_serial(struct ptp_ocp * bp,struct ocp_resource * r)2290 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2291 {
2292 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2293 struct ptp_ocp_serial_port port = {};
2294
2295 port.line = ptp_ocp_serial_line(bp, r);
2296 if (port.line < 0)
2297 return port.line;
2298
2299 if (p)
2300 port.baud = p->baud;
2301
2302 bp_assign_entry(bp, r, port);
2303
2304 return 0;
2305 }
2306
2307 static int
ptp_ocp_register_mem(struct ptp_ocp * bp,struct ocp_resource * r)2308 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2309 {
2310 void __iomem *mem;
2311
2312 mem = ptp_ocp_get_mem(bp, r);
2313 if (IS_ERR(mem))
2314 return PTR_ERR(mem);
2315
2316 bp_assign_entry(bp, r, mem);
2317
2318 return 0;
2319 }
2320
2321 static void
ptp_ocp_nmea_out_init(struct ptp_ocp * bp)2322 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2323 {
2324 if (!bp->nmea_out)
2325 return;
2326
2327 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
2328 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
2329 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
2330 }
2331
2332 static void
_ptp_ocp_signal_init(struct ptp_ocp_signal * s,struct signal_reg __iomem * reg)2333 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2334 {
2335 u32 val;
2336
2337 iowrite32(0, ®->enable); /* disable */
2338
2339 val = ioread32(®->polarity);
2340 s->polarity = val ? true : false;
2341 s->duty = 50;
2342 }
2343
2344 static void
ptp_ocp_signal_init(struct ptp_ocp * bp)2345 ptp_ocp_signal_init(struct ptp_ocp *bp)
2346 {
2347 int i;
2348
2349 for (i = 0; i < 4; i++)
2350 if (bp->signal_out[i])
2351 _ptp_ocp_signal_init(&bp->signal[i],
2352 bp->signal_out[i]->mem);
2353 }
2354
2355 static void
ptp_ocp_attr_group_del(struct ptp_ocp * bp)2356 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2357 {
2358 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2359 kfree(bp->attr_group);
2360 }
2361
2362 static int
ptp_ocp_attr_group_add(struct ptp_ocp * bp,const struct ocp_attr_group * attr_tbl)2363 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2364 const struct ocp_attr_group *attr_tbl)
2365 {
2366 int count, i;
2367 int err;
2368
2369 count = 0;
2370 for (i = 0; attr_tbl[i].cap; i++)
2371 if (attr_tbl[i].cap & bp->fw_cap)
2372 count++;
2373
2374 bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *),
2375 GFP_KERNEL);
2376 if (!bp->attr_group)
2377 return -ENOMEM;
2378
2379 count = 0;
2380 for (i = 0; attr_tbl[i].cap; i++)
2381 if (attr_tbl[i].cap & bp->fw_cap)
2382 bp->attr_group[count++] = attr_tbl[i].group;
2383
2384 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2385 if (err)
2386 bp->attr_group[0] = NULL;
2387
2388 return err;
2389 }
2390
2391 static void
ptp_ocp_enable_fpga(u32 __iomem * reg,u32 bit,bool enable)2392 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2393 {
2394 u32 ctrl;
2395 bool on;
2396
2397 ctrl = ioread32(reg);
2398 on = ctrl & bit;
2399 if (on ^ enable) {
2400 ctrl &= ~bit;
2401 ctrl |= enable ? bit : 0;
2402 iowrite32(ctrl, reg);
2403 }
2404 }
2405
2406 static void
ptp_ocp_irig_out(struct ptp_ocp * bp,bool enable)2407 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2408 {
2409 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2410 IRIG_M_CTRL_ENABLE, enable);
2411 }
2412
2413 static void
ptp_ocp_irig_in(struct ptp_ocp * bp,bool enable)2414 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2415 {
2416 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2417 IRIG_S_CTRL_ENABLE, enable);
2418 }
2419
2420 static void
ptp_ocp_dcf_out(struct ptp_ocp * bp,bool enable)2421 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2422 {
2423 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2424 DCF_M_CTRL_ENABLE, enable);
2425 }
2426
2427 static void
ptp_ocp_dcf_in(struct ptp_ocp * bp,bool enable)2428 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2429 {
2430 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2431 DCF_S_CTRL_ENABLE, enable);
2432 }
2433
2434 static void
__handle_signal_outputs(struct ptp_ocp * bp,u32 val)2435 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2436 {
2437 ptp_ocp_irig_out(bp, val & 0x00100010);
2438 ptp_ocp_dcf_out(bp, val & 0x00200020);
2439 }
2440
2441 static void
__handle_signal_inputs(struct ptp_ocp * bp,u32 val)2442 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2443 {
2444 ptp_ocp_irig_in(bp, val & 0x00100010);
2445 ptp_ocp_dcf_in(bp, val & 0x00200020);
2446 }
2447
2448 static u32
ptp_ocp_sma_fb_get(struct ptp_ocp * bp,int sma_nr)2449 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2450 {
2451 u32 __iomem *gpio;
2452 u32 shift;
2453
2454 if (bp->sma[sma_nr - 1].fixed_fcn)
2455 return (sma_nr - 1) & 1;
2456
2457 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2458 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2459 else
2460 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2461 shift = sma_nr & 1 ? 0 : 16;
2462
2463 return (ioread32(gpio) >> shift) & 0xffff;
2464 }
2465
2466 static int
ptp_ocp_sma_fb_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)2467 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2468 {
2469 u32 reg, mask, shift;
2470 unsigned long flags;
2471 u32 __iomem *gpio;
2472
2473 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2474 shift = sma_nr & 1 ? 0 : 16;
2475
2476 mask = 0xffff << (16 - shift);
2477
2478 spin_lock_irqsave(&bp->lock, flags);
2479
2480 reg = ioread32(gpio);
2481 reg = (reg & mask) | (val << shift);
2482
2483 __handle_signal_outputs(bp, reg);
2484
2485 iowrite32(reg, gpio);
2486
2487 spin_unlock_irqrestore(&bp->lock, flags);
2488
2489 return 0;
2490 }
2491
2492 static int
ptp_ocp_sma_fb_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)2493 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2494 {
2495 u32 reg, mask, shift;
2496 unsigned long flags;
2497 u32 __iomem *gpio;
2498
2499 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2500 shift = sma_nr & 1 ? 0 : 16;
2501
2502 mask = 0xffff << (16 - shift);
2503
2504 spin_lock_irqsave(&bp->lock, flags);
2505
2506 reg = ioread32(gpio);
2507 reg = (reg & mask) | (val << shift);
2508
2509 __handle_signal_inputs(bp, reg);
2510
2511 iowrite32(reg, gpio);
2512
2513 spin_unlock_irqrestore(&bp->lock, flags);
2514
2515 return 0;
2516 }
2517
2518 static void
ptp_ocp_sma_fb_init(struct ptp_ocp * bp)2519 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2520 {
2521 struct dpll_pin_properties prop = {
2522 .board_label = NULL,
2523 .type = DPLL_PIN_TYPE_EXT,
2524 .capabilities = DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE,
2525 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2526 .freq_supported = ptp_ocp_sma_freq,
2527
2528 };
2529 u32 reg;
2530 int i;
2531
2532 /* defaults */
2533 for (i = 0; i < OCP_SMA_NUM; i++) {
2534 bp->sma[i].default_fcn = i & 1;
2535 bp->sma[i].dpll_prop = prop;
2536 bp->sma[i].dpll_prop.board_label =
2537 bp->ptp_info.pin_config[i].name;
2538 }
2539 bp->sma[0].mode = SMA_MODE_IN;
2540 bp->sma[1].mode = SMA_MODE_IN;
2541 bp->sma[2].mode = SMA_MODE_OUT;
2542 bp->sma[3].mode = SMA_MODE_OUT;
2543 /* If no SMA1 map, the pin functions and directions are fixed. */
2544 if (!bp->sma_map1) {
2545 for (i = 0; i < OCP_SMA_NUM; i++) {
2546 bp->sma[i].fixed_fcn = true;
2547 bp->sma[i].fixed_dir = true;
2548 bp->sma[1].dpll_prop.capabilities &=
2549 ~DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2550 }
2551 return;
2552 }
2553
2554 /* If SMA2 GPIO output map is all 1, it is not present.
2555 * This indicates the firmware has fixed direction SMA pins.
2556 */
2557 reg = ioread32(&bp->sma_map2->gpio2);
2558 if (reg == 0xffffffff) {
2559 for (i = 0; i < OCP_SMA_NUM; i++)
2560 bp->sma[i].fixed_dir = true;
2561 } else {
2562 reg = ioread32(&bp->sma_map1->gpio1);
2563 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2564 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2565
2566 reg = ioread32(&bp->sma_map1->gpio2);
2567 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2568 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2569 }
2570 }
2571
2572 static const struct ocp_sma_op ocp_fb_sma_op = {
2573 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out },
2574 .init = ptp_ocp_sma_fb_init,
2575 .get = ptp_ocp_sma_fb_get,
2576 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2577 .set_output = ptp_ocp_sma_fb_set_output,
2578 };
2579
2580 static const struct ocp_sma_op ocp_adva_sma_op = {
2581 .tbl = { ptp_ocp_adva_sma_in, ptp_ocp_adva_sma_out },
2582 .init = ptp_ocp_sma_fb_init,
2583 .get = ptp_ocp_sma_fb_get,
2584 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2585 .set_output = ptp_ocp_sma_fb_set_output,
2586 };
2587
2588 static int
ptp_ocp_set_pins(struct ptp_ocp * bp)2589 ptp_ocp_set_pins(struct ptp_ocp *bp)
2590 {
2591 struct ptp_pin_desc *config;
2592 int i;
2593
2594 config = kcalloc(4, sizeof(*config), GFP_KERNEL);
2595 if (!config)
2596 return -ENOMEM;
2597
2598 for (i = 0; i < 4; i++) {
2599 sprintf(config[i].name, "sma%d", i + 1);
2600 config[i].index = i;
2601 }
2602
2603 bp->ptp_info.n_pins = 4;
2604 bp->ptp_info.pin_config = config;
2605
2606 return 0;
2607 }
2608
2609 static void
ptp_ocp_fb_set_version(struct ptp_ocp * bp)2610 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2611 {
2612 u64 cap = OCP_CAP_BASIC;
2613 u32 version;
2614
2615 version = ioread32(&bp->image->version);
2616
2617 /* if lower 16 bits are empty, this is the fw loader. */
2618 if ((version & 0xffff) == 0) {
2619 version = version >> 16;
2620 bp->fw_loader = true;
2621 }
2622
2623 bp->fw_tag = version >> 15;
2624 bp->fw_version = version & 0x7fff;
2625
2626 if (bp->fw_tag) {
2627 /* FPGA firmware */
2628 if (version >= 5)
2629 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2630 } else {
2631 /* SOM firmware */
2632 if (version >= 19)
2633 cap |= OCP_CAP_SIGNAL;
2634 if (version >= 20)
2635 cap |= OCP_CAP_FREQ;
2636 }
2637
2638 bp->fw_cap = cap;
2639 }
2640
2641 /* FB specific board initializers; last "resource" registered. */
2642 static int
ptp_ocp_fb_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2643 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2644 {
2645 int err;
2646
2647 bp->flash_start = 1024 * 4096;
2648 bp->eeprom_map = fb_eeprom_map;
2649 bp->fw_version = ioread32(&bp->image->version);
2650 bp->sma_op = &ocp_fb_sma_op;
2651
2652 ptp_ocp_fb_set_version(bp);
2653
2654 ptp_ocp_tod_init(bp);
2655 ptp_ocp_nmea_out_init(bp);
2656 ptp_ocp_signal_init(bp);
2657
2658 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2659 if (err)
2660 return err;
2661
2662 err = ptp_ocp_set_pins(bp);
2663 if (err)
2664 return err;
2665 ptp_ocp_sma_init(bp);
2666
2667 return ptp_ocp_init_clock(bp, r->extra);
2668 }
2669
2670 static bool
ptp_ocp_allow_irq(struct ptp_ocp * bp,struct ocp_resource * r)2671 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
2672 {
2673 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
2674
2675 if (!allow)
2676 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
2677 r->irq_vec, r->name);
2678 return allow;
2679 }
2680
2681 static int
ptp_ocp_register_resources(struct ptp_ocp * bp,kernel_ulong_t driver_data)2682 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
2683 {
2684 struct ocp_resource *r, *table;
2685 int err = 0;
2686
2687 table = (struct ocp_resource *)driver_data;
2688 for (r = table; r->setup; r++) {
2689 if (!ptp_ocp_allow_irq(bp, r))
2690 continue;
2691 err = r->setup(bp, r);
2692 if (err) {
2693 dev_err(&bp->pdev->dev,
2694 "Could not register %s: err %d\n",
2695 r->name, err);
2696 break;
2697 }
2698 }
2699 return err;
2700 }
2701
2702 static void
ptp_ocp_art_sma_init(struct ptp_ocp * bp)2703 ptp_ocp_art_sma_init(struct ptp_ocp *bp)
2704 {
2705 struct dpll_pin_properties prop = {
2706 .board_label = NULL,
2707 .type = DPLL_PIN_TYPE_EXT,
2708 .capabilities = 0,
2709 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2710 .freq_supported = ptp_ocp_sma_freq,
2711
2712 };
2713 u32 reg;
2714 int i;
2715
2716 /* defaults */
2717 bp->sma[0].mode = SMA_MODE_IN;
2718 bp->sma[1].mode = SMA_MODE_IN;
2719 bp->sma[2].mode = SMA_MODE_OUT;
2720 bp->sma[3].mode = SMA_MODE_OUT;
2721
2722 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */
2723 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */
2724 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */
2725 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */
2726
2727 for (i = 0; i < OCP_SMA_NUM; i++) {
2728 /* If no SMA map, the pin functions and directions are fixed. */
2729 bp->sma[i].dpll_prop = prop;
2730 bp->sma[i].dpll_prop.board_label =
2731 bp->ptp_info.pin_config[i].name;
2732 if (!bp->art_sma) {
2733 bp->sma[i].fixed_fcn = true;
2734 bp->sma[i].fixed_dir = true;
2735 continue;
2736 }
2737 reg = ioread32(&bp->art_sma->map[i].gpio);
2738
2739 switch (reg & 0xff) {
2740 case 0:
2741 bp->sma[i].fixed_fcn = true;
2742 bp->sma[i].fixed_dir = true;
2743 break;
2744 case 1:
2745 case 8:
2746 bp->sma[i].mode = SMA_MODE_IN;
2747 bp->sma[i].dpll_prop.capabilities =
2748 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2749 break;
2750 default:
2751 bp->sma[i].mode = SMA_MODE_OUT;
2752 bp->sma[i].dpll_prop.capabilities =
2753 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2754 break;
2755 }
2756 }
2757 }
2758
2759 static u32
ptp_ocp_art_sma_get(struct ptp_ocp * bp,int sma_nr)2760 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
2761 {
2762 if (bp->sma[sma_nr - 1].fixed_fcn)
2763 return bp->sma[sma_nr - 1].default_fcn;
2764
2765 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
2766 }
2767
2768 /* note: store 0 is considered invalid. */
2769 static int
ptp_ocp_art_sma_set(struct ptp_ocp * bp,int sma_nr,u32 val)2770 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
2771 {
2772 unsigned long flags;
2773 u32 __iomem *gpio;
2774 int err = 0;
2775 u32 reg;
2776
2777 val &= SMA_SELECT_MASK;
2778 if (hweight32(val) > 1)
2779 return -EINVAL;
2780
2781 gpio = &bp->art_sma->map[sma_nr - 1].gpio;
2782
2783 spin_lock_irqsave(&bp->lock, flags);
2784 reg = ioread32(gpio);
2785 if (((reg >> 16) & val) == 0) {
2786 err = -EOPNOTSUPP;
2787 } else {
2788 reg = (reg & 0xff00) | (val & 0xff);
2789 iowrite32(reg, gpio);
2790 }
2791 spin_unlock_irqrestore(&bp->lock, flags);
2792
2793 return err;
2794 }
2795
2796 static const struct ocp_sma_op ocp_art_sma_op = {
2797 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
2798 .init = ptp_ocp_art_sma_init,
2799 .get = ptp_ocp_art_sma_get,
2800 .set_inputs = ptp_ocp_art_sma_set,
2801 .set_output = ptp_ocp_art_sma_set,
2802 };
2803
2804 /* ART specific board initializers; last "resource" registered. */
2805 static int
ptp_ocp_art_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2806 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2807 {
2808 int err;
2809
2810 bp->flash_start = 0x1000000;
2811 bp->eeprom_map = art_eeprom_map;
2812 bp->fw_cap = OCP_CAP_BASIC;
2813 bp->fw_version = ioread32(&bp->reg->version);
2814 bp->fw_tag = 2;
2815 bp->sma_op = &ocp_art_sma_op;
2816
2817 /* Enable MAC serial port during initialisation */
2818 iowrite32(1, &bp->board_config->mro50_serial_activate);
2819
2820 err = ptp_ocp_set_pins(bp);
2821 if (err)
2822 return err;
2823 ptp_ocp_sma_init(bp);
2824
2825 err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
2826 if (err)
2827 return err;
2828
2829 return ptp_ocp_init_clock(bp, r->extra);
2830 }
2831
2832 /* ADVA specific board initializers; last "resource" registered. */
2833 static int
ptp_ocp_adva_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2834 ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2835 {
2836 int err;
2837 u32 version;
2838
2839 bp->flash_start = 0xA00000;
2840 bp->eeprom_map = fb_eeprom_map;
2841 bp->sma_op = &ocp_adva_sma_op;
2842
2843 version = ioread32(&bp->image->version);
2844 /* if lower 16 bits are empty, this is the fw loader. */
2845 if ((version & 0xffff) == 0) {
2846 version = version >> 16;
2847 bp->fw_loader = true;
2848 }
2849 bp->fw_tag = 3;
2850 bp->fw_version = version & 0xffff;
2851 bp->fw_cap = OCP_CAP_BASIC | OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2852
2853 ptp_ocp_tod_init(bp);
2854 ptp_ocp_nmea_out_init(bp);
2855 ptp_ocp_signal_init(bp);
2856
2857 err = ptp_ocp_attr_group_add(bp, adva_timecard_groups);
2858 if (err)
2859 return err;
2860
2861 err = ptp_ocp_set_pins(bp);
2862 if (err)
2863 return err;
2864 ptp_ocp_sma_init(bp);
2865
2866 return ptp_ocp_init_clock(bp, r->extra);
2867 }
2868
2869 static ssize_t
ptp_ocp_show_output(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)2870 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
2871 int def_val)
2872 {
2873 const char *name;
2874 ssize_t count;
2875
2876 count = sysfs_emit(buf, "OUT: ");
2877 name = ptp_ocp_select_name_from_val(tbl, val);
2878 if (!name)
2879 name = ptp_ocp_select_name_from_val(tbl, def_val);
2880 count += sysfs_emit_at(buf, count, "%s\n", name);
2881 return count;
2882 }
2883
2884 static ssize_t
ptp_ocp_show_inputs(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)2885 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
2886 int def_val)
2887 {
2888 const char *name;
2889 ssize_t count;
2890 int i;
2891
2892 count = sysfs_emit(buf, "IN: ");
2893 for (i = 0; tbl[i].name; i++) {
2894 if (val & tbl[i].value) {
2895 name = tbl[i].name;
2896 count += sysfs_emit_at(buf, count, "%s ", name);
2897 }
2898 }
2899 if (!val && def_val >= 0) {
2900 name = ptp_ocp_select_name_from_val(tbl, def_val);
2901 count += sysfs_emit_at(buf, count, "%s ", name);
2902 }
2903 if (count)
2904 count--;
2905 count += sysfs_emit_at(buf, count, "\n");
2906 return count;
2907 }
2908
2909 static int
sma_parse_inputs(const struct ocp_selector * const tbl[],const char * buf,enum ptp_ocp_sma_mode * mode)2910 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
2911 enum ptp_ocp_sma_mode *mode)
2912 {
2913 int idx, count, dir;
2914 char **argv;
2915 int ret;
2916
2917 argv = argv_split(GFP_KERNEL, buf, &count);
2918 if (!argv)
2919 return -ENOMEM;
2920
2921 ret = -EINVAL;
2922 if (!count)
2923 goto out;
2924
2925 idx = 0;
2926 dir = *mode == SMA_MODE_IN ? 0 : 1;
2927 if (!strcasecmp("IN:", argv[0])) {
2928 dir = 0;
2929 idx++;
2930 }
2931 if (!strcasecmp("OUT:", argv[0])) {
2932 dir = 1;
2933 idx++;
2934 }
2935 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
2936
2937 ret = 0;
2938 for (; idx < count; idx++)
2939 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
2940 if (ret < 0)
2941 ret = -EINVAL;
2942
2943 out:
2944 argv_free(argv);
2945 return ret;
2946 }
2947
2948 static ssize_t
ptp_ocp_sma_show(struct ptp_ocp * bp,int sma_nr,char * buf,int default_in_val,int default_out_val)2949 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
2950 int default_in_val, int default_out_val)
2951 {
2952 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2953 const struct ocp_selector * const *tbl;
2954 u32 val;
2955
2956 tbl = bp->sma_op->tbl;
2957 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
2958
2959 if (sma->mode == SMA_MODE_IN) {
2960 if (sma->disabled)
2961 val = SMA_DISABLE;
2962 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
2963 }
2964
2965 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
2966 }
2967
2968 static ssize_t
sma1_show(struct device * dev,struct device_attribute * attr,char * buf)2969 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
2970 {
2971 struct ptp_ocp *bp = dev_get_drvdata(dev);
2972
2973 return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
2974 }
2975
2976 static ssize_t
sma2_show(struct device * dev,struct device_attribute * attr,char * buf)2977 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
2978 {
2979 struct ptp_ocp *bp = dev_get_drvdata(dev);
2980
2981 return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
2982 }
2983
2984 static ssize_t
sma3_show(struct device * dev,struct device_attribute * attr,char * buf)2985 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
2986 {
2987 struct ptp_ocp *bp = dev_get_drvdata(dev);
2988
2989 return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
2990 }
2991
2992 static ssize_t
sma4_show(struct device * dev,struct device_attribute * attr,char * buf)2993 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
2994 {
2995 struct ptp_ocp *bp = dev_get_drvdata(dev);
2996
2997 return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
2998 }
2999
3000 static int
ptp_ocp_sma_store_val(struct ptp_ocp * bp,int val,enum ptp_ocp_sma_mode mode,int sma_nr)3001 ptp_ocp_sma_store_val(struct ptp_ocp *bp, int val, enum ptp_ocp_sma_mode mode, int sma_nr)
3002 {
3003 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3004
3005 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
3006 return -EOPNOTSUPP;
3007
3008 if (sma->fixed_fcn) {
3009 if (val != sma->default_fcn)
3010 return -EOPNOTSUPP;
3011 return 0;
3012 }
3013
3014 sma->disabled = !!(val & SMA_DISABLE);
3015
3016 if (mode != sma->mode) {
3017 if (mode == SMA_MODE_IN)
3018 ptp_ocp_sma_set_output(bp, sma_nr, 0);
3019 else
3020 ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
3021 sma->mode = mode;
3022 }
3023
3024 if (!sma->fixed_dir)
3025 val |= SMA_ENABLE; /* add enable bit */
3026
3027 if (sma->disabled)
3028 val = 0;
3029
3030 if (mode == SMA_MODE_IN)
3031 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
3032 else
3033 val = ptp_ocp_sma_set_output(bp, sma_nr, val);
3034
3035 return val;
3036 }
3037
3038 static int
ptp_ocp_sma_store(struct ptp_ocp * bp,const char * buf,int sma_nr)3039 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
3040 {
3041 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3042 enum ptp_ocp_sma_mode mode;
3043 int val;
3044
3045 mode = sma->mode;
3046 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
3047 if (val < 0)
3048 return val;
3049 return ptp_ocp_sma_store_val(bp, val, mode, sma_nr);
3050 }
3051
3052 static ssize_t
sma1_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3053 sma1_store(struct device *dev, struct device_attribute *attr,
3054 const char *buf, size_t count)
3055 {
3056 struct ptp_ocp *bp = dev_get_drvdata(dev);
3057 int err;
3058
3059 err = ptp_ocp_sma_store(bp, buf, 1);
3060 return err ? err : count;
3061 }
3062
3063 static ssize_t
sma2_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3064 sma2_store(struct device *dev, struct device_attribute *attr,
3065 const char *buf, size_t count)
3066 {
3067 struct ptp_ocp *bp = dev_get_drvdata(dev);
3068 int err;
3069
3070 err = ptp_ocp_sma_store(bp, buf, 2);
3071 return err ? err : count;
3072 }
3073
3074 static ssize_t
sma3_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3075 sma3_store(struct device *dev, struct device_attribute *attr,
3076 const char *buf, size_t count)
3077 {
3078 struct ptp_ocp *bp = dev_get_drvdata(dev);
3079 int err;
3080
3081 err = ptp_ocp_sma_store(bp, buf, 3);
3082 return err ? err : count;
3083 }
3084
3085 static ssize_t
sma4_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3086 sma4_store(struct device *dev, struct device_attribute *attr,
3087 const char *buf, size_t count)
3088 {
3089 struct ptp_ocp *bp = dev_get_drvdata(dev);
3090 int err;
3091
3092 err = ptp_ocp_sma_store(bp, buf, 4);
3093 return err ? err : count;
3094 }
3095 static DEVICE_ATTR_RW(sma1);
3096 static DEVICE_ATTR_RW(sma2);
3097 static DEVICE_ATTR_RW(sma3);
3098 static DEVICE_ATTR_RW(sma4);
3099
3100 static ssize_t
available_sma_inputs_show(struct device * dev,struct device_attribute * attr,char * buf)3101 available_sma_inputs_show(struct device *dev,
3102 struct device_attribute *attr, char *buf)
3103 {
3104 struct ptp_ocp *bp = dev_get_drvdata(dev);
3105
3106 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
3107 }
3108 static DEVICE_ATTR_RO(available_sma_inputs);
3109
3110 static ssize_t
available_sma_outputs_show(struct device * dev,struct device_attribute * attr,char * buf)3111 available_sma_outputs_show(struct device *dev,
3112 struct device_attribute *attr, char *buf)
3113 {
3114 struct ptp_ocp *bp = dev_get_drvdata(dev);
3115
3116 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
3117 }
3118 static DEVICE_ATTR_RO(available_sma_outputs);
3119
3120 #define EXT_ATTR_RO(_group, _name, _val) \
3121 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3122 { __ATTR_RO(_name), (void *)_val }
3123 #define EXT_ATTR_RW(_group, _name, _val) \
3124 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3125 { __ATTR_RW(_name), (void *)_val }
3126 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
3127
3128 /* period [duty [phase [polarity]]] */
3129 static ssize_t
signal_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3130 signal_store(struct device *dev, struct device_attribute *attr,
3131 const char *buf, size_t count)
3132 {
3133 struct dev_ext_attribute *ea = to_ext_attr(attr);
3134 struct ptp_ocp *bp = dev_get_drvdata(dev);
3135 struct ptp_ocp_signal s = { };
3136 int gen = (uintptr_t)ea->var;
3137 int argc, err;
3138 char **argv;
3139
3140 argv = argv_split(GFP_KERNEL, buf, &argc);
3141 if (!argv)
3142 return -ENOMEM;
3143
3144 err = -EINVAL;
3145 s.duty = bp->signal[gen].duty;
3146 s.phase = bp->signal[gen].phase;
3147 s.period = bp->signal[gen].period;
3148 s.polarity = bp->signal[gen].polarity;
3149
3150 switch (argc) {
3151 case 4:
3152 argc--;
3153 err = kstrtobool(argv[argc], &s.polarity);
3154 if (err)
3155 goto out;
3156 fallthrough;
3157 case 3:
3158 argc--;
3159 err = kstrtou64(argv[argc], 0, &s.phase);
3160 if (err)
3161 goto out;
3162 fallthrough;
3163 case 2:
3164 argc--;
3165 err = kstrtoint(argv[argc], 0, &s.duty);
3166 if (err)
3167 goto out;
3168 fallthrough;
3169 case 1:
3170 argc--;
3171 err = kstrtou64(argv[argc], 0, &s.period);
3172 if (err)
3173 goto out;
3174 break;
3175 default:
3176 goto out;
3177 }
3178
3179 err = ptp_ocp_signal_set(bp, gen, &s);
3180 if (err)
3181 goto out;
3182
3183 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
3184
3185 out:
3186 argv_free(argv);
3187 return err ? err : count;
3188 }
3189
3190 static ssize_t
signal_show(struct device * dev,struct device_attribute * attr,char * buf)3191 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
3192 {
3193 struct dev_ext_attribute *ea = to_ext_attr(attr);
3194 struct ptp_ocp *bp = dev_get_drvdata(dev);
3195 struct ptp_ocp_signal *signal;
3196 struct timespec64 ts;
3197 ssize_t count;
3198 int i;
3199
3200 i = (uintptr_t)ea->var;
3201 signal = &bp->signal[i];
3202
3203 count = sysfs_emit(buf, "%llu %d %llu %d", signal->period,
3204 signal->duty, signal->phase, signal->polarity);
3205
3206 ts = ktime_to_timespec64(signal->start);
3207 count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts);
3208
3209 return count;
3210 }
3211 static EXT_ATTR_RW(signal, signal, 0);
3212 static EXT_ATTR_RW(signal, signal, 1);
3213 static EXT_ATTR_RW(signal, signal, 2);
3214 static EXT_ATTR_RW(signal, signal, 3);
3215
3216 static ssize_t
duty_show(struct device * dev,struct device_attribute * attr,char * buf)3217 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
3218 {
3219 struct dev_ext_attribute *ea = to_ext_attr(attr);
3220 struct ptp_ocp *bp = dev_get_drvdata(dev);
3221 int i = (uintptr_t)ea->var;
3222
3223 return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
3224 }
3225 static EXT_ATTR_RO(signal, duty, 0);
3226 static EXT_ATTR_RO(signal, duty, 1);
3227 static EXT_ATTR_RO(signal, duty, 2);
3228 static EXT_ATTR_RO(signal, duty, 3);
3229
3230 static ssize_t
period_show(struct device * dev,struct device_attribute * attr,char * buf)3231 period_show(struct device *dev, struct device_attribute *attr, char *buf)
3232 {
3233 struct dev_ext_attribute *ea = to_ext_attr(attr);
3234 struct ptp_ocp *bp = dev_get_drvdata(dev);
3235 int i = (uintptr_t)ea->var;
3236
3237 return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
3238 }
3239 static EXT_ATTR_RO(signal, period, 0);
3240 static EXT_ATTR_RO(signal, period, 1);
3241 static EXT_ATTR_RO(signal, period, 2);
3242 static EXT_ATTR_RO(signal, period, 3);
3243
3244 static ssize_t
phase_show(struct device * dev,struct device_attribute * attr,char * buf)3245 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
3246 {
3247 struct dev_ext_attribute *ea = to_ext_attr(attr);
3248 struct ptp_ocp *bp = dev_get_drvdata(dev);
3249 int i = (uintptr_t)ea->var;
3250
3251 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
3252 }
3253 static EXT_ATTR_RO(signal, phase, 0);
3254 static EXT_ATTR_RO(signal, phase, 1);
3255 static EXT_ATTR_RO(signal, phase, 2);
3256 static EXT_ATTR_RO(signal, phase, 3);
3257
3258 static ssize_t
polarity_show(struct device * dev,struct device_attribute * attr,char * buf)3259 polarity_show(struct device *dev, struct device_attribute *attr,
3260 char *buf)
3261 {
3262 struct dev_ext_attribute *ea = to_ext_attr(attr);
3263 struct ptp_ocp *bp = dev_get_drvdata(dev);
3264 int i = (uintptr_t)ea->var;
3265
3266 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
3267 }
3268 static EXT_ATTR_RO(signal, polarity, 0);
3269 static EXT_ATTR_RO(signal, polarity, 1);
3270 static EXT_ATTR_RO(signal, polarity, 2);
3271 static EXT_ATTR_RO(signal, polarity, 3);
3272
3273 static ssize_t
running_show(struct device * dev,struct device_attribute * attr,char * buf)3274 running_show(struct device *dev, struct device_attribute *attr, char *buf)
3275 {
3276 struct dev_ext_attribute *ea = to_ext_attr(attr);
3277 struct ptp_ocp *bp = dev_get_drvdata(dev);
3278 int i = (uintptr_t)ea->var;
3279
3280 return sysfs_emit(buf, "%d\n", bp->signal[i].running);
3281 }
3282 static EXT_ATTR_RO(signal, running, 0);
3283 static EXT_ATTR_RO(signal, running, 1);
3284 static EXT_ATTR_RO(signal, running, 2);
3285 static EXT_ATTR_RO(signal, running, 3);
3286
3287 static ssize_t
start_show(struct device * dev,struct device_attribute * attr,char * buf)3288 start_show(struct device *dev, struct device_attribute *attr, char *buf)
3289 {
3290 struct dev_ext_attribute *ea = to_ext_attr(attr);
3291 struct ptp_ocp *bp = dev_get_drvdata(dev);
3292 int i = (uintptr_t)ea->var;
3293 struct timespec64 ts;
3294
3295 ts = ktime_to_timespec64(bp->signal[i].start);
3296 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
3297 }
3298 static EXT_ATTR_RO(signal, start, 0);
3299 static EXT_ATTR_RO(signal, start, 1);
3300 static EXT_ATTR_RO(signal, start, 2);
3301 static EXT_ATTR_RO(signal, start, 3);
3302
3303 static ssize_t
seconds_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3304 seconds_store(struct device *dev, struct device_attribute *attr,
3305 const char *buf, size_t count)
3306 {
3307 struct dev_ext_attribute *ea = to_ext_attr(attr);
3308 struct ptp_ocp *bp = dev_get_drvdata(dev);
3309 int idx = (uintptr_t)ea->var;
3310 u32 val;
3311 int err;
3312
3313 err = kstrtou32(buf, 0, &val);
3314 if (err)
3315 return err;
3316 if (val > 0xff)
3317 return -EINVAL;
3318
3319 if (val)
3320 val = (val << 8) | 0x1;
3321
3322 iowrite32(val, &bp->freq_in[idx]->ctrl);
3323
3324 return count;
3325 }
3326
3327 static ssize_t
seconds_show(struct device * dev,struct device_attribute * attr,char * buf)3328 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3329 {
3330 struct dev_ext_attribute *ea = to_ext_attr(attr);
3331 struct ptp_ocp *bp = dev_get_drvdata(dev);
3332 int idx = (uintptr_t)ea->var;
3333 u32 val;
3334
3335 val = ioread32(&bp->freq_in[idx]->ctrl);
3336 if (val & 1)
3337 val = (val >> 8) & 0xff;
3338 else
3339 val = 0;
3340
3341 return sysfs_emit(buf, "%u\n", val);
3342 }
3343 static EXT_ATTR_RW(freq, seconds, 0);
3344 static EXT_ATTR_RW(freq, seconds, 1);
3345 static EXT_ATTR_RW(freq, seconds, 2);
3346 static EXT_ATTR_RW(freq, seconds, 3);
3347
3348 static ssize_t
frequency_show(struct device * dev,struct device_attribute * attr,char * buf)3349 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3350 {
3351 struct dev_ext_attribute *ea = to_ext_attr(attr);
3352 struct ptp_ocp *bp = dev_get_drvdata(dev);
3353 int idx = (uintptr_t)ea->var;
3354 u32 val;
3355
3356 val = ioread32(&bp->freq_in[idx]->status);
3357 if (val & FREQ_STATUS_ERROR)
3358 return sysfs_emit(buf, "error\n");
3359 if (val & FREQ_STATUS_OVERRUN)
3360 return sysfs_emit(buf, "overrun\n");
3361 if (val & FREQ_STATUS_VALID)
3362 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3363 return 0;
3364 }
3365 static EXT_ATTR_RO(freq, frequency, 0);
3366 static EXT_ATTR_RO(freq, frequency, 1);
3367 static EXT_ATTR_RO(freq, frequency, 2);
3368 static EXT_ATTR_RO(freq, frequency, 3);
3369
3370 static ssize_t
ptp_ocp_tty_show(struct device * dev,struct device_attribute * attr,char * buf)3371 ptp_ocp_tty_show(struct device *dev, struct device_attribute *attr, char *buf)
3372 {
3373 struct dev_ext_attribute *ea = to_ext_attr(attr);
3374 struct ptp_ocp *bp = dev_get_drvdata(dev);
3375
3376 return sysfs_emit(buf, "ttyS%d", bp->port[(uintptr_t)ea->var].line);
3377 }
3378
3379 static umode_t
ptp_ocp_timecard_tty_is_visible(struct kobject * kobj,struct attribute * attr,int n)3380 ptp_ocp_timecard_tty_is_visible(struct kobject *kobj, struct attribute *attr, int n)
3381 {
3382 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3383 struct ptp_ocp_serial_port *port;
3384 struct device_attribute *dattr;
3385 struct dev_ext_attribute *ea;
3386
3387 if (strncmp(attr->name, "tty", 3))
3388 return attr->mode;
3389
3390 dattr = container_of(attr, struct device_attribute, attr);
3391 ea = container_of(dattr, struct dev_ext_attribute, attr);
3392 port = &bp->port[(uintptr_t)ea->var];
3393 return port->line == -1 ? 0 : 0444;
3394 }
3395
3396 #define EXT_TTY_ATTR_RO(_name, _val) \
3397 struct dev_ext_attribute dev_attr_tty##_name = \
3398 { __ATTR(tty##_name, 0444, ptp_ocp_tty_show, NULL), (void *)_val }
3399
3400 static EXT_TTY_ATTR_RO(GNSS, PORT_GNSS);
3401 static EXT_TTY_ATTR_RO(GNSS2, PORT_GNSS2);
3402 static EXT_TTY_ATTR_RO(MAC, PORT_MAC);
3403 static EXT_TTY_ATTR_RO(NMEA, PORT_NMEA);
3404 static struct attribute *ptp_ocp_timecard_tty_attrs[] = {
3405 &dev_attr_ttyGNSS.attr.attr,
3406 &dev_attr_ttyGNSS2.attr.attr,
3407 &dev_attr_ttyMAC.attr.attr,
3408 &dev_attr_ttyNMEA.attr.attr,
3409 NULL,
3410 };
3411
3412 static const struct attribute_group ptp_ocp_timecard_tty_group = {
3413 .name = "tty",
3414 .attrs = ptp_ocp_timecard_tty_attrs,
3415 .is_visible = ptp_ocp_timecard_tty_is_visible,
3416 };
3417
3418 static ssize_t
serialnum_show(struct device * dev,struct device_attribute * attr,char * buf)3419 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3420 {
3421 struct ptp_ocp *bp = dev_get_drvdata(dev);
3422
3423 if (!bp->has_eeprom_data)
3424 ptp_ocp_read_eeprom(bp);
3425
3426 return sysfs_emit(buf, "%pM\n", bp->serial);
3427 }
3428 static DEVICE_ATTR_RO(serialnum);
3429
3430 static ssize_t
gnss_sync_show(struct device * dev,struct device_attribute * attr,char * buf)3431 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3432 {
3433 struct ptp_ocp *bp = dev_get_drvdata(dev);
3434 ssize_t ret;
3435
3436 if (bp->gnss_lost)
3437 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3438 else
3439 ret = sysfs_emit(buf, "SYNC\n");
3440
3441 return ret;
3442 }
3443 static DEVICE_ATTR_RO(gnss_sync);
3444
3445 static ssize_t
utc_tai_offset_show(struct device * dev,struct device_attribute * attr,char * buf)3446 utc_tai_offset_show(struct device *dev,
3447 struct device_attribute *attr, char *buf)
3448 {
3449 struct ptp_ocp *bp = dev_get_drvdata(dev);
3450
3451 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3452 }
3453
3454 static ssize_t
utc_tai_offset_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3455 utc_tai_offset_store(struct device *dev,
3456 struct device_attribute *attr,
3457 const char *buf, size_t count)
3458 {
3459 struct ptp_ocp *bp = dev_get_drvdata(dev);
3460 int err;
3461 u32 val;
3462
3463 err = kstrtou32(buf, 0, &val);
3464 if (err)
3465 return err;
3466
3467 ptp_ocp_utc_distribute(bp, val);
3468
3469 return count;
3470 }
3471 static DEVICE_ATTR_RW(utc_tai_offset);
3472
3473 static ssize_t
ts_window_adjust_show(struct device * dev,struct device_attribute * attr,char * buf)3474 ts_window_adjust_show(struct device *dev,
3475 struct device_attribute *attr, char *buf)
3476 {
3477 struct ptp_ocp *bp = dev_get_drvdata(dev);
3478
3479 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3480 }
3481
3482 static ssize_t
ts_window_adjust_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3483 ts_window_adjust_store(struct device *dev,
3484 struct device_attribute *attr,
3485 const char *buf, size_t count)
3486 {
3487 struct ptp_ocp *bp = dev_get_drvdata(dev);
3488 int err;
3489 u32 val;
3490
3491 err = kstrtou32(buf, 0, &val);
3492 if (err)
3493 return err;
3494
3495 bp->ts_window_adjust = val;
3496
3497 return count;
3498 }
3499 static DEVICE_ATTR_RW(ts_window_adjust);
3500
3501 static ssize_t
irig_b_mode_show(struct device * dev,struct device_attribute * attr,char * buf)3502 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3503 {
3504 struct ptp_ocp *bp = dev_get_drvdata(dev);
3505 u32 val;
3506
3507 val = ioread32(&bp->irig_out->ctrl);
3508 val = (val >> 16) & 0x07;
3509 return sysfs_emit(buf, "%d\n", val);
3510 }
3511
3512 static ssize_t
irig_b_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3513 irig_b_mode_store(struct device *dev,
3514 struct device_attribute *attr,
3515 const char *buf, size_t count)
3516 {
3517 struct ptp_ocp *bp = dev_get_drvdata(dev);
3518 unsigned long flags;
3519 int err;
3520 u32 reg;
3521 u8 val;
3522
3523 err = kstrtou8(buf, 0, &val);
3524 if (err)
3525 return err;
3526 if (val > 7)
3527 return -EINVAL;
3528
3529 reg = ((val & 0x7) << 16);
3530
3531 spin_lock_irqsave(&bp->lock, flags);
3532 iowrite32(0, &bp->irig_out->ctrl); /* disable */
3533 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
3534 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3535 spin_unlock_irqrestore(&bp->lock, flags);
3536
3537 return count;
3538 }
3539 static DEVICE_ATTR_RW(irig_b_mode);
3540
3541 static ssize_t
clock_source_show(struct device * dev,struct device_attribute * attr,char * buf)3542 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3543 {
3544 struct ptp_ocp *bp = dev_get_drvdata(dev);
3545 const char *p;
3546 u32 select;
3547
3548 select = ioread32(&bp->reg->select);
3549 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3550
3551 return sysfs_emit(buf, "%s\n", p);
3552 }
3553
3554 static ssize_t
clock_source_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3555 clock_source_store(struct device *dev, struct device_attribute *attr,
3556 const char *buf, size_t count)
3557 {
3558 struct ptp_ocp *bp = dev_get_drvdata(dev);
3559 unsigned long flags;
3560 int val;
3561
3562 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3563 if (val < 0)
3564 return val;
3565
3566 spin_lock_irqsave(&bp->lock, flags);
3567 iowrite32(val, &bp->reg->select);
3568 spin_unlock_irqrestore(&bp->lock, flags);
3569
3570 return count;
3571 }
3572 static DEVICE_ATTR_RW(clock_source);
3573
3574 static ssize_t
available_clock_sources_show(struct device * dev,struct device_attribute * attr,char * buf)3575 available_clock_sources_show(struct device *dev,
3576 struct device_attribute *attr, char *buf)
3577 {
3578 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
3579 }
3580 static DEVICE_ATTR_RO(available_clock_sources);
3581
3582 static ssize_t
clock_status_drift_show(struct device * dev,struct device_attribute * attr,char * buf)3583 clock_status_drift_show(struct device *dev,
3584 struct device_attribute *attr, char *buf)
3585 {
3586 struct ptp_ocp *bp = dev_get_drvdata(dev);
3587 u32 val;
3588 int res;
3589
3590 val = ioread32(&bp->reg->status_drift);
3591 res = (val & ~INT_MAX) ? -1 : 1;
3592 res *= (val & INT_MAX);
3593 return sysfs_emit(buf, "%d\n", res);
3594 }
3595 static DEVICE_ATTR_RO(clock_status_drift);
3596
3597 static ssize_t
clock_status_offset_show(struct device * dev,struct device_attribute * attr,char * buf)3598 clock_status_offset_show(struct device *dev,
3599 struct device_attribute *attr, char *buf)
3600 {
3601 struct ptp_ocp *bp = dev_get_drvdata(dev);
3602 u32 val;
3603 int res;
3604
3605 val = ioread32(&bp->reg->status_offset);
3606 res = (val & ~INT_MAX) ? -1 : 1;
3607 res *= (val & INT_MAX);
3608 return sysfs_emit(buf, "%d\n", res);
3609 }
3610 static DEVICE_ATTR_RO(clock_status_offset);
3611
3612 static ssize_t
tod_correction_show(struct device * dev,struct device_attribute * attr,char * buf)3613 tod_correction_show(struct device *dev,
3614 struct device_attribute *attr, char *buf)
3615 {
3616 struct ptp_ocp *bp = dev_get_drvdata(dev);
3617 u32 val;
3618 int res;
3619
3620 val = ioread32(&bp->tod->adj_sec);
3621 res = (val & ~INT_MAX) ? -1 : 1;
3622 res *= (val & INT_MAX);
3623 return sysfs_emit(buf, "%d\n", res);
3624 }
3625
3626 static ssize_t
tod_correction_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3627 tod_correction_store(struct device *dev, struct device_attribute *attr,
3628 const char *buf, size_t count)
3629 {
3630 struct ptp_ocp *bp = dev_get_drvdata(dev);
3631 unsigned long flags;
3632 int err, res;
3633 u32 val = 0;
3634
3635 err = kstrtos32(buf, 0, &res);
3636 if (err)
3637 return err;
3638 if (res < 0) {
3639 res *= -1;
3640 val |= BIT(31);
3641 }
3642 val |= res;
3643
3644 spin_lock_irqsave(&bp->lock, flags);
3645 iowrite32(val, &bp->tod->adj_sec);
3646 spin_unlock_irqrestore(&bp->lock, flags);
3647
3648 return count;
3649 }
3650 static DEVICE_ATTR_RW(tod_correction);
3651
3652 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \
3653 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \
3654 &dev_attr_signal##_nr##_signal.attr.attr, \
3655 &dev_attr_signal##_nr##_duty.attr.attr, \
3656 &dev_attr_signal##_nr##_phase.attr.attr, \
3657 &dev_attr_signal##_nr##_period.attr.attr, \
3658 &dev_attr_signal##_nr##_polarity.attr.attr, \
3659 &dev_attr_signal##_nr##_running.attr.attr, \
3660 &dev_attr_signal##_nr##_start.attr.attr, \
3661 NULL, \
3662 }
3663
3664 #define DEVICE_SIGNAL_GROUP(_name, _nr) \
3665 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \
3666 static const struct attribute_group \
3667 fb_timecard_signal##_nr##_group = { \
3668 .name = #_name, \
3669 .attrs = fb_timecard_signal##_nr##_attrs, \
3670 }
3671
3672 DEVICE_SIGNAL_GROUP(gen1, 0);
3673 DEVICE_SIGNAL_GROUP(gen2, 1);
3674 DEVICE_SIGNAL_GROUP(gen3, 2);
3675 DEVICE_SIGNAL_GROUP(gen4, 3);
3676
3677 #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \
3678 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \
3679 &dev_attr_freq##_nr##_seconds.attr.attr, \
3680 &dev_attr_freq##_nr##_frequency.attr.attr, \
3681 NULL, \
3682 }
3683
3684 #define DEVICE_FREQ_GROUP(_name, _nr) \
3685 _DEVICE_FREQ_GROUP_ATTRS(_nr); \
3686 static const struct attribute_group \
3687 fb_timecard_freq##_nr##_group = { \
3688 .name = #_name, \
3689 .attrs = fb_timecard_freq##_nr##_attrs, \
3690 }
3691
3692 DEVICE_FREQ_GROUP(freq1, 0);
3693 DEVICE_FREQ_GROUP(freq2, 1);
3694 DEVICE_FREQ_GROUP(freq3, 2);
3695 DEVICE_FREQ_GROUP(freq4, 3);
3696
3697 static ssize_t
disciplining_config_read(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3698 disciplining_config_read(struct file *filp, struct kobject *kobj,
3699 const struct bin_attribute *bin_attr, char *buf,
3700 loff_t off, size_t count)
3701 {
3702 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3703 size_t size = OCP_ART_CONFIG_SIZE;
3704 struct nvmem_device *nvmem;
3705 ssize_t err;
3706
3707 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3708 if (IS_ERR(nvmem))
3709 return PTR_ERR(nvmem);
3710
3711 if (off > size) {
3712 err = 0;
3713 goto out;
3714 }
3715
3716 if (off + count > size)
3717 count = size - off;
3718
3719 // the configuration is in the very beginning of the EEPROM
3720 err = nvmem_device_read(nvmem, off, count, buf);
3721 if (err != count) {
3722 err = -EFAULT;
3723 goto out;
3724 }
3725
3726 out:
3727 ptp_ocp_nvmem_device_put(&nvmem);
3728
3729 return err;
3730 }
3731
3732 static ssize_t
disciplining_config_write(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3733 disciplining_config_write(struct file *filp, struct kobject *kobj,
3734 const struct bin_attribute *bin_attr, char *buf,
3735 loff_t off, size_t count)
3736 {
3737 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3738 struct nvmem_device *nvmem;
3739 ssize_t err;
3740
3741 /* Allow write of the whole area only */
3742 if (off || count != OCP_ART_CONFIG_SIZE)
3743 return -EFAULT;
3744
3745 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3746 if (IS_ERR(nvmem))
3747 return PTR_ERR(nvmem);
3748
3749 err = nvmem_device_write(nvmem, 0x00, count, buf);
3750 if (err != count)
3751 err = -EFAULT;
3752
3753 ptp_ocp_nvmem_device_put(&nvmem);
3754
3755 return err;
3756 }
3757 static const BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
3758
3759 static ssize_t
temperature_table_read(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3760 temperature_table_read(struct file *filp, struct kobject *kobj,
3761 const struct bin_attribute *bin_attr, char *buf,
3762 loff_t off, size_t count)
3763 {
3764 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3765 size_t size = OCP_ART_TEMP_TABLE_SIZE;
3766 struct nvmem_device *nvmem;
3767 ssize_t err;
3768
3769 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3770 if (IS_ERR(nvmem))
3771 return PTR_ERR(nvmem);
3772
3773 if (off > size) {
3774 err = 0;
3775 goto out;
3776 }
3777
3778 if (off + count > size)
3779 count = size - off;
3780
3781 // the configuration is in the very beginning of the EEPROM
3782 err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
3783 if (err != count) {
3784 err = -EFAULT;
3785 goto out;
3786 }
3787
3788 out:
3789 ptp_ocp_nvmem_device_put(&nvmem);
3790
3791 return err;
3792 }
3793
3794 static ssize_t
temperature_table_write(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3795 temperature_table_write(struct file *filp, struct kobject *kobj,
3796 const struct bin_attribute *bin_attr, char *buf,
3797 loff_t off, size_t count)
3798 {
3799 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3800 struct nvmem_device *nvmem;
3801 ssize_t err;
3802
3803 /* Allow write of the whole area only */
3804 if (off || count != OCP_ART_TEMP_TABLE_SIZE)
3805 return -EFAULT;
3806
3807 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3808 if (IS_ERR(nvmem))
3809 return PTR_ERR(nvmem);
3810
3811 err = nvmem_device_write(nvmem, 0x90, count, buf);
3812 if (err != count)
3813 err = -EFAULT;
3814
3815 ptp_ocp_nvmem_device_put(&nvmem);
3816
3817 return err;
3818 }
3819 static const BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
3820
3821 static struct attribute *fb_timecard_attrs[] = {
3822 &dev_attr_serialnum.attr,
3823 &dev_attr_gnss_sync.attr,
3824 &dev_attr_clock_source.attr,
3825 &dev_attr_available_clock_sources.attr,
3826 &dev_attr_sma1.attr,
3827 &dev_attr_sma2.attr,
3828 &dev_attr_sma3.attr,
3829 &dev_attr_sma4.attr,
3830 &dev_attr_available_sma_inputs.attr,
3831 &dev_attr_available_sma_outputs.attr,
3832 &dev_attr_clock_status_drift.attr,
3833 &dev_attr_clock_status_offset.attr,
3834 &dev_attr_irig_b_mode.attr,
3835 &dev_attr_utc_tai_offset.attr,
3836 &dev_attr_ts_window_adjust.attr,
3837 &dev_attr_tod_correction.attr,
3838 NULL,
3839 };
3840
3841 static const struct attribute_group fb_timecard_group = {
3842 .attrs = fb_timecard_attrs,
3843 };
3844
3845 static const struct ocp_attr_group fb_timecard_groups[] = {
3846 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group },
3847 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3848 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3849 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3850 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },
3851 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },
3852 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3853 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3854 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },
3855 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },
3856 { },
3857 };
3858
3859 static struct attribute *art_timecard_attrs[] = {
3860 &dev_attr_serialnum.attr,
3861 &dev_attr_clock_source.attr,
3862 &dev_attr_available_clock_sources.attr,
3863 &dev_attr_utc_tai_offset.attr,
3864 &dev_attr_ts_window_adjust.attr,
3865 &dev_attr_sma1.attr,
3866 &dev_attr_sma2.attr,
3867 &dev_attr_sma3.attr,
3868 &dev_attr_sma4.attr,
3869 &dev_attr_available_sma_inputs.attr,
3870 &dev_attr_available_sma_outputs.attr,
3871 NULL,
3872 };
3873
3874 static const struct bin_attribute *const bin_art_timecard_attrs[] = {
3875 &bin_attr_disciplining_config,
3876 &bin_attr_temperature_table,
3877 NULL,
3878 };
3879
3880 static const struct attribute_group art_timecard_group = {
3881 .attrs = art_timecard_attrs,
3882 .bin_attrs_new = bin_art_timecard_attrs,
3883 };
3884
3885 static const struct ocp_attr_group art_timecard_groups[] = {
3886 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group },
3887 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3888 { },
3889 };
3890
3891 static struct attribute *adva_timecard_attrs[] = {
3892 &dev_attr_serialnum.attr,
3893 &dev_attr_gnss_sync.attr,
3894 &dev_attr_clock_source.attr,
3895 &dev_attr_available_clock_sources.attr,
3896 &dev_attr_sma1.attr,
3897 &dev_attr_sma2.attr,
3898 &dev_attr_sma3.attr,
3899 &dev_attr_sma4.attr,
3900 &dev_attr_available_sma_inputs.attr,
3901 &dev_attr_available_sma_outputs.attr,
3902 &dev_attr_clock_status_drift.attr,
3903 &dev_attr_clock_status_offset.attr,
3904 &dev_attr_ts_window_adjust.attr,
3905 &dev_attr_tod_correction.attr,
3906 NULL,
3907 };
3908
3909 static const struct attribute_group adva_timecard_group = {
3910 .attrs = adva_timecard_attrs,
3911 };
3912
3913 static const struct ocp_attr_group adva_timecard_groups[] = {
3914 { .cap = OCP_CAP_BASIC, .group = &adva_timecard_group },
3915 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3916 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3917 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3918 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3919 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3920 { },
3921 };
3922
3923 static void
gpio_input_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit,const char * def)3924 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
3925 const char *def)
3926 {
3927 int i;
3928
3929 for (i = 0; i < 4; i++) {
3930 if (bp->sma[i].mode != SMA_MODE_IN)
3931 continue;
3932 if (map[i][0] & (1 << bit)) {
3933 sprintf(buf, "sma%d", i + 1);
3934 return;
3935 }
3936 }
3937 if (!def)
3938 def = "----";
3939 strcpy(buf, def);
3940 }
3941
3942 static void
gpio_output_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit)3943 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
3944 {
3945 char *ans = buf;
3946 int i;
3947
3948 strcpy(ans, "----");
3949 for (i = 0; i < 4; i++) {
3950 if (bp->sma[i].mode != SMA_MODE_OUT)
3951 continue;
3952 if (map[i][1] & (1 << bit))
3953 ans += sprintf(ans, "sma%d ", i + 1);
3954 }
3955 }
3956
3957 static void
_signal_summary_show(struct seq_file * s,struct ptp_ocp * bp,int nr)3958 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
3959 {
3960 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
3961 struct ptp_ocp_signal *signal = &bp->signal[nr];
3962 char label[8];
3963 bool on;
3964 u32 val;
3965
3966 on = signal->running;
3967 sprintf(label, "GEN%d", nr + 1);
3968 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
3969 label, on ? " ON" : "OFF",
3970 signal->period, signal->duty, signal->phase,
3971 signal->polarity);
3972
3973 val = ioread32(®->enable);
3974 seq_printf(s, " [%x", val);
3975 val = ioread32(®->status);
3976 seq_printf(s, " %x]", val);
3977
3978 seq_printf(s, " start:%llu\n", signal->start);
3979 }
3980
3981 static void
_frequency_summary_show(struct seq_file * s,int nr,struct frequency_reg __iomem * reg)3982 _frequency_summary_show(struct seq_file *s, int nr,
3983 struct frequency_reg __iomem *reg)
3984 {
3985 char label[8];
3986 bool on;
3987 u32 val;
3988
3989 if (!reg)
3990 return;
3991
3992 sprintf(label, "FREQ%d", nr + 1);
3993 val = ioread32(®->ctrl);
3994 on = val & 1;
3995 val = (val >> 8) & 0xff;
3996 seq_printf(s, "%7s: %s, sec:%u",
3997 label,
3998 on ? " ON" : "OFF",
3999 val);
4000
4001 val = ioread32(®->status);
4002 if (val & FREQ_STATUS_ERROR)
4003 seq_printf(s, ", error");
4004 if (val & FREQ_STATUS_OVERRUN)
4005 seq_printf(s, ", overrun");
4006 if (val & FREQ_STATUS_VALID)
4007 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
4008 seq_printf(s, " reg:%x\n", val);
4009 }
4010
4011 static int
ptp_ocp_summary_show(struct seq_file * s,void * data)4012 ptp_ocp_summary_show(struct seq_file *s, void *data)
4013 {
4014 struct device *dev = s->private;
4015 struct ptp_system_timestamp sts;
4016 struct ts_reg __iomem *ts_reg;
4017 char *buf, *src, *mac_src;
4018 struct timespec64 ts;
4019 struct ptp_ocp *bp;
4020 u16 sma_val[4][2];
4021 u32 ctrl, val;
4022 bool on, map;
4023 int i;
4024
4025 buf = (char *)__get_free_page(GFP_KERNEL);
4026 if (!buf)
4027 return -ENOMEM;
4028
4029 bp = dev_get_drvdata(dev);
4030
4031 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
4032 for (i = 0; i < __PORT_COUNT; i++) {
4033 if (bp->port[i].line != -1)
4034 seq_printf(s, "%7s: /dev/ttyS%d\n", ptp_ocp_tty_port_name(i),
4035 bp->port[i].line);
4036 }
4037
4038 memset(sma_val, 0xff, sizeof(sma_val));
4039 if (bp->sma_map1) {
4040 u32 reg;
4041
4042 reg = ioread32(&bp->sma_map1->gpio1);
4043 sma_val[0][0] = reg & 0xffff;
4044 sma_val[1][0] = reg >> 16;
4045
4046 reg = ioread32(&bp->sma_map1->gpio2);
4047 sma_val[2][1] = reg & 0xffff;
4048 sma_val[3][1] = reg >> 16;
4049
4050 reg = ioread32(&bp->sma_map2->gpio1);
4051 sma_val[2][0] = reg & 0xffff;
4052 sma_val[3][0] = reg >> 16;
4053
4054 reg = ioread32(&bp->sma_map2->gpio2);
4055 sma_val[0][1] = reg & 0xffff;
4056 sma_val[1][1] = reg >> 16;
4057 }
4058
4059 sma1_show(dev, NULL, buf);
4060 seq_printf(s, " sma1: %04x,%04x %s",
4061 sma_val[0][0], sma_val[0][1], buf);
4062
4063 sma2_show(dev, NULL, buf);
4064 seq_printf(s, " sma2: %04x,%04x %s",
4065 sma_val[1][0], sma_val[1][1], buf);
4066
4067 sma3_show(dev, NULL, buf);
4068 seq_printf(s, " sma3: %04x,%04x %s",
4069 sma_val[2][0], sma_val[2][1], buf);
4070
4071 sma4_show(dev, NULL, buf);
4072 seq_printf(s, " sma4: %04x,%04x %s",
4073 sma_val[3][0], sma_val[3][1], buf);
4074
4075 if (bp->ts0) {
4076 ts_reg = bp->ts0->mem;
4077 on = ioread32(&ts_reg->enable);
4078 src = "GNSS1";
4079 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
4080 on ? " ON" : "OFF", src);
4081 }
4082
4083 if (bp->ts1) {
4084 ts_reg = bp->ts1->mem;
4085 on = ioread32(&ts_reg->enable);
4086 gpio_input_map(buf, bp, sma_val, 2, NULL);
4087 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
4088 on ? " ON" : "OFF", buf);
4089 }
4090
4091 if (bp->ts2) {
4092 ts_reg = bp->ts2->mem;
4093 on = ioread32(&ts_reg->enable);
4094 gpio_input_map(buf, bp, sma_val, 3, NULL);
4095 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
4096 on ? " ON" : "OFF", buf);
4097 }
4098
4099 if (bp->ts3) {
4100 ts_reg = bp->ts3->mem;
4101 on = ioread32(&ts_reg->enable);
4102 gpio_input_map(buf, bp, sma_val, 6, NULL);
4103 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
4104 on ? " ON" : "OFF", buf);
4105 }
4106
4107 if (bp->ts4) {
4108 ts_reg = bp->ts4->mem;
4109 on = ioread32(&ts_reg->enable);
4110 gpio_input_map(buf, bp, sma_val, 7, NULL);
4111 seq_printf(s, "%7s: %s, src: %s\n", "TS4",
4112 on ? " ON" : "OFF", buf);
4113 }
4114
4115 if (bp->pps) {
4116 ts_reg = bp->pps->mem;
4117 src = "PHC";
4118 on = ioread32(&ts_reg->enable);
4119 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
4120 seq_printf(s, "%7s: %s, src: %s\n", "TS5",
4121 on && map ? " ON" : "OFF", src);
4122
4123 map = !!(bp->pps_req_map & OCP_REQ_PPS);
4124 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
4125 on && map ? " ON" : "OFF", src);
4126 }
4127
4128 if (bp->fw_cap & OCP_CAP_SIGNAL)
4129 for (i = 0; i < 4; i++)
4130 _signal_summary_show(s, bp, i);
4131
4132 if (bp->fw_cap & OCP_CAP_FREQ)
4133 for (i = 0; i < 4; i++)
4134 _frequency_summary_show(s, i, bp->freq_in[i]);
4135
4136 if (bp->irig_out) {
4137 ctrl = ioread32(&bp->irig_out->ctrl);
4138 on = ctrl & IRIG_M_CTRL_ENABLE;
4139 val = ioread32(&bp->irig_out->status);
4140 gpio_output_map(buf, bp, sma_val, 4);
4141 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
4142 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
4143 }
4144
4145 if (bp->irig_in) {
4146 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
4147 val = ioread32(&bp->irig_in->status);
4148 gpio_input_map(buf, bp, sma_val, 4, NULL);
4149 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
4150 on ? " ON" : "OFF", val, buf);
4151 }
4152
4153 if (bp->dcf_out) {
4154 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
4155 val = ioread32(&bp->dcf_out->status);
4156 gpio_output_map(buf, bp, sma_val, 5);
4157 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
4158 on ? " ON" : "OFF", val, buf);
4159 }
4160
4161 if (bp->dcf_in) {
4162 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
4163 val = ioread32(&bp->dcf_in->status);
4164 gpio_input_map(buf, bp, sma_val, 5, NULL);
4165 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
4166 on ? " ON" : "OFF", val, buf);
4167 }
4168
4169 if (bp->nmea_out) {
4170 on = ioread32(&bp->nmea_out->ctrl) & 1;
4171 val = ioread32(&bp->nmea_out->status);
4172 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
4173 on ? " ON" : "OFF", val);
4174 }
4175
4176 /* compute src for PPS1, used below. */
4177 if (bp->pps_select) {
4178 val = ioread32(&bp->pps_select->gpio1);
4179 src = &buf[80];
4180 mac_src = "GNSS1";
4181 if (val & 0x01) {
4182 gpio_input_map(src, bp, sma_val, 0, NULL);
4183 mac_src = src;
4184 } else if (val & 0x02) {
4185 src = "MAC";
4186 } else if (val & 0x04) {
4187 src = "GNSS1";
4188 } else {
4189 src = "----";
4190 mac_src = src;
4191 }
4192 } else {
4193 src = "?";
4194 mac_src = src;
4195 }
4196 seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
4197
4198 gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
4199 seq_printf(s, "MAC PPS2 src: %s\n", buf);
4200
4201 /* assumes automatic switchover/selection */
4202 val = ioread32(&bp->reg->select);
4203 switch (val >> 16) {
4204 case 0:
4205 sprintf(buf, "----");
4206 break;
4207 case 2:
4208 sprintf(buf, "IRIG");
4209 break;
4210 case 3:
4211 sprintf(buf, "%s via PPS1", src);
4212 break;
4213 case 6:
4214 sprintf(buf, "DCF");
4215 break;
4216 default:
4217 strcpy(buf, "unknown");
4218 break;
4219 }
4220 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
4221 bp->sync ? "sync" : "unsynced");
4222
4223 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
4224 struct timespec64 sys_ts;
4225 s64 pre_ns, post_ns, ns;
4226
4227 pre_ns = timespec64_to_ns(&sts.pre_ts);
4228 post_ns = timespec64_to_ns(&sts.post_ts);
4229 ns = (pre_ns + post_ns) / 2;
4230 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
4231 sys_ts = ns_to_timespec64(ns);
4232
4233 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
4234 ts.tv_sec, ts.tv_nsec, &ts);
4235 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
4236 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
4237 bp->utc_tai_offset);
4238 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
4239 timespec64_to_ns(&ts) - ns,
4240 post_ns - pre_ns);
4241 }
4242
4243 free_page((unsigned long)buf);
4244 return 0;
4245 }
4246 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
4247
4248 static int
ptp_ocp_tod_status_show(struct seq_file * s,void * data)4249 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
4250 {
4251 struct device *dev = s->private;
4252 struct ptp_ocp *bp;
4253 u32 val;
4254 int idx;
4255
4256 bp = dev_get_drvdata(dev);
4257
4258 val = ioread32(&bp->tod->ctrl);
4259 if (!(val & TOD_CTRL_ENABLE)) {
4260 seq_printf(s, "TOD Slave disabled\n");
4261 return 0;
4262 }
4263 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
4264
4265 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
4266 idx += (val >> 16) & 3;
4267 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
4268
4269 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
4270 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
4271
4272 val = ioread32(&bp->tod->version);
4273 seq_printf(s, "TOD Version %d.%d.%d\n",
4274 val >> 24, (val >> 16) & 0xff, val & 0xffff);
4275
4276 val = ioread32(&bp->tod->status);
4277 seq_printf(s, "Status register: 0x%08X\n", val);
4278
4279 val = ioread32(&bp->tod->adj_sec);
4280 idx = (val & ~INT_MAX) ? -1 : 1;
4281 idx *= (val & INT_MAX);
4282 seq_printf(s, "Correction seconds: %d\n", idx);
4283
4284 val = ioread32(&bp->tod->utc_status);
4285 seq_printf(s, "UTC status register: 0x%08X\n", val);
4286 seq_printf(s, "UTC offset: %ld valid:%d\n",
4287 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
4288 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
4289 val & TOD_STATUS_LEAP_VALID ? 1 : 0,
4290 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
4291
4292 val = ioread32(&bp->tod->leap);
4293 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
4294
4295 return 0;
4296 }
4297 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
4298
4299 static struct dentry *ptp_ocp_debugfs_root;
4300
4301 static void
ptp_ocp_debugfs_add_device(struct ptp_ocp * bp)4302 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
4303 {
4304 struct dentry *d;
4305
4306 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
4307 bp->debug_root = d;
4308 debugfs_create_file("summary", 0444, bp->debug_root,
4309 &bp->dev, &ptp_ocp_summary_fops);
4310 if (bp->tod)
4311 debugfs_create_file("tod_status", 0444, bp->debug_root,
4312 &bp->dev, &ptp_ocp_tod_status_fops);
4313 }
4314
4315 static void
ptp_ocp_debugfs_remove_device(struct ptp_ocp * bp)4316 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
4317 {
4318 debugfs_remove_recursive(bp->debug_root);
4319 }
4320
4321 static void
ptp_ocp_debugfs_init(void)4322 ptp_ocp_debugfs_init(void)
4323 {
4324 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
4325 }
4326
4327 static void
ptp_ocp_debugfs_fini(void)4328 ptp_ocp_debugfs_fini(void)
4329 {
4330 debugfs_remove_recursive(ptp_ocp_debugfs_root);
4331 }
4332
4333 static void
ptp_ocp_dev_release(struct device * dev)4334 ptp_ocp_dev_release(struct device *dev)
4335 {
4336 struct ptp_ocp *bp = dev_get_drvdata(dev);
4337
4338 mutex_lock(&ptp_ocp_lock);
4339 idr_remove(&ptp_ocp_idr, bp->id);
4340 mutex_unlock(&ptp_ocp_lock);
4341 }
4342
4343 static int
ptp_ocp_device_init(struct ptp_ocp * bp,struct pci_dev * pdev)4344 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
4345 {
4346 int i, err;
4347
4348 mutex_lock(&ptp_ocp_lock);
4349 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
4350 mutex_unlock(&ptp_ocp_lock);
4351 if (err < 0) {
4352 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
4353 return err;
4354 }
4355 bp->id = err;
4356
4357 bp->ptp_info = ptp_ocp_clock_info;
4358 spin_lock_init(&bp->lock);
4359
4360 for (i = 0; i < __PORT_COUNT; i++)
4361 bp->port[i].line = -1;
4362
4363 bp->pdev = pdev;
4364
4365 device_initialize(&bp->dev);
4366 dev_set_name(&bp->dev, "ocp%d", bp->id);
4367 bp->dev.class = &timecard_class;
4368 bp->dev.parent = &pdev->dev;
4369 bp->dev.release = ptp_ocp_dev_release;
4370 dev_set_drvdata(&bp->dev, bp);
4371
4372 err = device_add(&bp->dev);
4373 if (err) {
4374 dev_err(&bp->dev, "device add failed: %d\n", err);
4375 goto out;
4376 }
4377
4378 pci_set_drvdata(pdev, bp);
4379
4380 return 0;
4381
4382 out:
4383 put_device(&bp->dev);
4384 return err;
4385 }
4386
4387 static void
ptp_ocp_symlink(struct ptp_ocp * bp,struct device * child,const char * link)4388 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
4389 {
4390 struct device *dev = &bp->dev;
4391
4392 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
4393 dev_err(dev, "%s symlink failed\n", link);
4394 }
4395
4396 static void
ptp_ocp_link_child(struct ptp_ocp * bp,const char * name,const char * link)4397 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
4398 {
4399 struct device *dev, *child;
4400
4401 dev = &bp->pdev->dev;
4402
4403 child = device_find_child_by_name(dev, name);
4404 if (!child) {
4405 dev_err(dev, "Could not find device %s\n", name);
4406 return;
4407 }
4408
4409 ptp_ocp_symlink(bp, child, link);
4410 put_device(child);
4411 }
4412
4413 static int
ptp_ocp_complete(struct ptp_ocp * bp)4414 ptp_ocp_complete(struct ptp_ocp *bp)
4415 {
4416 struct pps_device *pps;
4417 char buf[32];
4418
4419 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
4420 ptp_ocp_link_child(bp, buf, "ptp");
4421
4422 pps = pps_lookup_dev(bp->ptp);
4423 if (pps)
4424 ptp_ocp_symlink(bp, &pps->dev, "pps");
4425
4426 ptp_ocp_debugfs_add_device(bp);
4427
4428 return 0;
4429 }
4430
4431 static void
ptp_ocp_phc_info(struct ptp_ocp * bp)4432 ptp_ocp_phc_info(struct ptp_ocp *bp)
4433 {
4434 struct timespec64 ts;
4435 u32 version, select;
4436
4437 version = ioread32(&bp->reg->version);
4438 select = ioread32(&bp->reg->select);
4439 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
4440 version >> 24, (version >> 16) & 0xff, version & 0xffff,
4441 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
4442 ptp_clock_index(bp->ptp));
4443
4444 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
4445 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
4446 ts.tv_sec, ts.tv_nsec,
4447 bp->sync ? "in-sync" : "UNSYNCED");
4448 }
4449
4450 static void
ptp_ocp_serial_info(struct device * dev,const char * name,int port,int baud)4451 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
4452 {
4453 if (port != -1)
4454 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
4455 }
4456
4457 static void
ptp_ocp_info(struct ptp_ocp * bp)4458 ptp_ocp_info(struct ptp_ocp *bp)
4459 {
4460 static int nmea_baud[] = {
4461 1200, 2400, 4800, 9600, 19200, 38400,
4462 57600, 115200, 230400, 460800, 921600,
4463 1000000, 2000000
4464 };
4465 struct device *dev = &bp->pdev->dev;
4466 u32 reg;
4467 int i;
4468
4469 ptp_ocp_phc_info(bp);
4470
4471 for (i = 0; i < __PORT_COUNT; i++) {
4472 if (i == PORT_NMEA && bp->nmea_out && bp->port[PORT_NMEA].line != -1) {
4473 bp->port[PORT_NMEA].baud = -1;
4474
4475 reg = ioread32(&bp->nmea_out->uart_baud);
4476 if (reg < ARRAY_SIZE(nmea_baud))
4477 bp->port[PORT_NMEA].baud = nmea_baud[reg];
4478 }
4479 ptp_ocp_serial_info(dev, ptp_ocp_tty_port_name(i), bp->port[i].line,
4480 bp->port[i].baud);
4481 }
4482 }
4483
4484 static void
ptp_ocp_detach_sysfs(struct ptp_ocp * bp)4485 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
4486 {
4487 struct device *dev = &bp->dev;
4488
4489 sysfs_remove_link(&dev->kobj, "ptp");
4490 sysfs_remove_link(&dev->kobj, "pps");
4491 }
4492
4493 static void
ptp_ocp_detach(struct ptp_ocp * bp)4494 ptp_ocp_detach(struct ptp_ocp *bp)
4495 {
4496 int i;
4497
4498 ptp_ocp_debugfs_remove_device(bp);
4499 ptp_ocp_detach_sysfs(bp);
4500 ptp_ocp_attr_group_del(bp);
4501 if (timer_pending(&bp->watchdog))
4502 del_timer_sync(&bp->watchdog);
4503 if (bp->ts0)
4504 ptp_ocp_unregister_ext(bp->ts0);
4505 if (bp->ts1)
4506 ptp_ocp_unregister_ext(bp->ts1);
4507 if (bp->ts2)
4508 ptp_ocp_unregister_ext(bp->ts2);
4509 if (bp->ts3)
4510 ptp_ocp_unregister_ext(bp->ts3);
4511 if (bp->ts4)
4512 ptp_ocp_unregister_ext(bp->ts4);
4513 if (bp->pps)
4514 ptp_ocp_unregister_ext(bp->pps);
4515 for (i = 0; i < 4; i++)
4516 if (bp->signal_out[i])
4517 ptp_ocp_unregister_ext(bp->signal_out[i]);
4518 for (i = 0; i < __PORT_COUNT; i++)
4519 if (bp->port[i].line != -1)
4520 serial8250_unregister_port(bp->port[i].line);
4521 platform_device_unregister(bp->spi_flash);
4522 platform_device_unregister(bp->i2c_ctrl);
4523 if (bp->i2c_clk)
4524 clk_hw_unregister_fixed_rate(bp->i2c_clk);
4525 if (bp->n_irqs)
4526 pci_free_irq_vectors(bp->pdev);
4527 if (bp->ptp)
4528 ptp_clock_unregister(bp->ptp);
4529 kfree(bp->ptp_info.pin_config);
4530 device_unregister(&bp->dev);
4531 }
4532
4533 static int
ptp_ocp_dpll_lock_status_get(const struct dpll_device * dpll,void * priv,enum dpll_lock_status * status,enum dpll_lock_status_error * status_error,struct netlink_ext_ack * extack)4534 ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll, void *priv,
4535 enum dpll_lock_status *status,
4536 enum dpll_lock_status_error *status_error,
4537 struct netlink_ext_ack *extack)
4538 {
4539 struct ptp_ocp *bp = priv;
4540
4541 *status = bp->sync ? DPLL_LOCK_STATUS_LOCKED : DPLL_LOCK_STATUS_UNLOCKED;
4542
4543 return 0;
4544 }
4545
ptp_ocp_dpll_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack)4546 static int ptp_ocp_dpll_state_get(const struct dpll_pin *pin, void *pin_priv,
4547 const struct dpll_device *dpll, void *priv,
4548 enum dpll_pin_state *state,
4549 struct netlink_ext_ack *extack)
4550 {
4551 struct ptp_ocp *bp = priv;
4552 int idx;
4553
4554 if (bp->pps_select) {
4555 idx = ioread32(&bp->pps_select->gpio1);
4556 *state = (&bp->sma[idx] == pin_priv) ? DPLL_PIN_STATE_CONNECTED :
4557 DPLL_PIN_STATE_SELECTABLE;
4558 return 0;
4559 }
4560 NL_SET_ERR_MSG(extack, "pin selection is not supported on current HW");
4561 return -EINVAL;
4562 }
4563
ptp_ocp_dpll_mode_get(const struct dpll_device * dpll,void * priv,enum dpll_mode * mode,struct netlink_ext_ack * extack)4564 static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv,
4565 enum dpll_mode *mode, struct netlink_ext_ack *extack)
4566 {
4567 *mode = DPLL_MODE_AUTOMATIC;
4568 return 0;
4569 }
4570
ptp_ocp_dpll_direction_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack)4571 static int ptp_ocp_dpll_direction_get(const struct dpll_pin *pin,
4572 void *pin_priv,
4573 const struct dpll_device *dpll,
4574 void *priv,
4575 enum dpll_pin_direction *direction,
4576 struct netlink_ext_ack *extack)
4577 {
4578 struct ptp_ocp_sma_connector *sma = pin_priv;
4579
4580 *direction = sma->mode == SMA_MODE_IN ?
4581 DPLL_PIN_DIRECTION_INPUT :
4582 DPLL_PIN_DIRECTION_OUTPUT;
4583 return 0;
4584 }
4585
ptp_ocp_dpll_direction_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction direction,struct netlink_ext_ack * extack)4586 static int ptp_ocp_dpll_direction_set(const struct dpll_pin *pin,
4587 void *pin_priv,
4588 const struct dpll_device *dpll,
4589 void *dpll_priv,
4590 enum dpll_pin_direction direction,
4591 struct netlink_ext_ack *extack)
4592 {
4593 struct ptp_ocp_sma_connector *sma = pin_priv;
4594 struct ptp_ocp *bp = dpll_priv;
4595 enum ptp_ocp_sma_mode mode;
4596 int sma_nr = (sma - bp->sma);
4597
4598 if (sma->fixed_dir)
4599 return -EOPNOTSUPP;
4600 mode = direction == DPLL_PIN_DIRECTION_INPUT ?
4601 SMA_MODE_IN : SMA_MODE_OUT;
4602 return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr + 1);
4603 }
4604
ptp_ocp_dpll_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack)4605 static int ptp_ocp_dpll_frequency_set(const struct dpll_pin *pin,
4606 void *pin_priv,
4607 const struct dpll_device *dpll,
4608 void *dpll_priv, u64 frequency,
4609 struct netlink_ext_ack *extack)
4610 {
4611 struct ptp_ocp_sma_connector *sma = pin_priv;
4612 struct ptp_ocp *bp = dpll_priv;
4613 const struct ocp_selector *tbl;
4614 int sma_nr = (sma - bp->sma);
4615 int i;
4616
4617 if (sma->fixed_fcn)
4618 return -EOPNOTSUPP;
4619
4620 tbl = bp->sma_op->tbl[sma->mode];
4621 for (i = 0; tbl[i].name; i++)
4622 if (tbl[i].frequency == frequency)
4623 return ptp_ocp_sma_store_val(bp, i, sma->mode, sma_nr + 1);
4624 return -EINVAL;
4625 }
4626
ptp_ocp_dpll_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack)4627 static int ptp_ocp_dpll_frequency_get(const struct dpll_pin *pin,
4628 void *pin_priv,
4629 const struct dpll_device *dpll,
4630 void *dpll_priv, u64 *frequency,
4631 struct netlink_ext_ack *extack)
4632 {
4633 struct ptp_ocp_sma_connector *sma = pin_priv;
4634 struct ptp_ocp *bp = dpll_priv;
4635 const struct ocp_selector *tbl;
4636 int sma_nr = (sma - bp->sma);
4637 u32 val;
4638 int i;
4639
4640 val = bp->sma_op->get(bp, sma_nr + 1);
4641 tbl = bp->sma_op->tbl[sma->mode];
4642 for (i = 0; tbl[i].name; i++)
4643 if (val == tbl[i].value) {
4644 *frequency = tbl[i].frequency;
4645 return 0;
4646 }
4647
4648 return -EINVAL;
4649 }
4650
4651 static const struct dpll_device_ops dpll_ops = {
4652 .lock_status_get = ptp_ocp_dpll_lock_status_get,
4653 .mode_get = ptp_ocp_dpll_mode_get,
4654 };
4655
4656 static const struct dpll_pin_ops dpll_pins_ops = {
4657 .frequency_get = ptp_ocp_dpll_frequency_get,
4658 .frequency_set = ptp_ocp_dpll_frequency_set,
4659 .direction_get = ptp_ocp_dpll_direction_get,
4660 .direction_set = ptp_ocp_dpll_direction_set,
4661 .state_on_dpll_get = ptp_ocp_dpll_state_get,
4662 };
4663
4664 static void
ptp_ocp_sync_work(struct work_struct * work)4665 ptp_ocp_sync_work(struct work_struct *work)
4666 {
4667 struct ptp_ocp *bp;
4668 bool sync;
4669
4670 bp = container_of(work, struct ptp_ocp, sync_work.work);
4671 sync = !!(ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC);
4672
4673 if (bp->sync != sync)
4674 dpll_device_change_ntf(bp->dpll);
4675
4676 bp->sync = sync;
4677
4678 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
4679 }
4680
4681 static int
ptp_ocp_probe(struct pci_dev * pdev,const struct pci_device_id * id)4682 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4683 {
4684 struct devlink *devlink;
4685 struct ptp_ocp *bp;
4686 int err, i;
4687 u64 clkid;
4688
4689 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
4690 if (!devlink) {
4691 dev_err(&pdev->dev, "devlink_alloc failed\n");
4692 return -ENOMEM;
4693 }
4694
4695 err = pci_enable_device(pdev);
4696 if (err) {
4697 dev_err(&pdev->dev, "pci_enable_device\n");
4698 goto out_free;
4699 }
4700
4701 bp = devlink_priv(devlink);
4702 err = ptp_ocp_device_init(bp, pdev);
4703 if (err)
4704 goto out_disable;
4705
4706 INIT_DELAYED_WORK(&bp->sync_work, ptp_ocp_sync_work);
4707
4708 /* compat mode.
4709 * Older FPGA firmware only returns 2 irq's.
4710 * allow this - if not all of the IRQ's are returned, skip the
4711 * extra devices and just register the clock.
4712 */
4713 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
4714 if (err < 0) {
4715 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
4716 goto out;
4717 }
4718 bp->n_irqs = err;
4719 pci_set_master(pdev);
4720
4721 err = ptp_ocp_register_resources(bp, id->driver_data);
4722 if (err)
4723 goto out;
4724
4725 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
4726 if (IS_ERR(bp->ptp)) {
4727 err = PTR_ERR(bp->ptp);
4728 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
4729 bp->ptp = NULL;
4730 goto out;
4731 }
4732
4733 err = ptp_ocp_complete(bp);
4734 if (err)
4735 goto out;
4736
4737 ptp_ocp_info(bp);
4738 devlink_register(devlink);
4739
4740 clkid = pci_get_dsn(pdev);
4741 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE);
4742 if (IS_ERR(bp->dpll)) {
4743 err = PTR_ERR(bp->dpll);
4744 dev_err(&pdev->dev, "dpll_device_alloc failed\n");
4745 goto out;
4746 }
4747
4748 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);
4749 if (err)
4750 goto out;
4751
4752 for (i = 0; i < OCP_SMA_NUM; i++) {
4753 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop);
4754 if (IS_ERR(bp->sma[i].dpll_pin)) {
4755 err = PTR_ERR(bp->sma[i].dpll_pin);
4756 goto out_dpll;
4757 }
4758
4759 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,
4760 &bp->sma[i]);
4761 if (err) {
4762 dpll_pin_put(bp->sma[i].dpll_pin);
4763 goto out_dpll;
4764 }
4765 }
4766 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
4767
4768 return 0;
4769 out_dpll:
4770 while (i) {
4771 --i;
4772 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
4773 dpll_pin_put(bp->sma[i].dpll_pin);
4774 }
4775 dpll_device_put(bp->dpll);
4776 out:
4777 ptp_ocp_detach(bp);
4778 out_disable:
4779 pci_disable_device(pdev);
4780 out_free:
4781 devlink_free(devlink);
4782 return err;
4783 }
4784
4785 static void
ptp_ocp_remove(struct pci_dev * pdev)4786 ptp_ocp_remove(struct pci_dev *pdev)
4787 {
4788 struct ptp_ocp *bp = pci_get_drvdata(pdev);
4789 struct devlink *devlink = priv_to_devlink(bp);
4790 int i;
4791
4792 cancel_delayed_work_sync(&bp->sync_work);
4793 for (i = 0; i < OCP_SMA_NUM; i++) {
4794 if (bp->sma[i].dpll_pin) {
4795 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
4796 dpll_pin_put(bp->sma[i].dpll_pin);
4797 }
4798 }
4799 dpll_device_unregister(bp->dpll, &dpll_ops, bp);
4800 dpll_device_put(bp->dpll);
4801 devlink_unregister(devlink);
4802 ptp_ocp_detach(bp);
4803 pci_disable_device(pdev);
4804
4805 devlink_free(devlink);
4806 }
4807
4808 static struct pci_driver ptp_ocp_driver = {
4809 .name = KBUILD_MODNAME,
4810 .id_table = ptp_ocp_pcidev_id,
4811 .probe = ptp_ocp_probe,
4812 .remove = ptp_ocp_remove,
4813 };
4814
4815 static int
ptp_ocp_i2c_notifier_call(struct notifier_block * nb,unsigned long action,void * data)4816 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
4817 unsigned long action, void *data)
4818 {
4819 struct device *dev, *child = data;
4820 struct ptp_ocp *bp;
4821 bool add;
4822
4823 switch (action) {
4824 case BUS_NOTIFY_ADD_DEVICE:
4825 case BUS_NOTIFY_DEL_DEVICE:
4826 add = action == BUS_NOTIFY_ADD_DEVICE;
4827 break;
4828 default:
4829 return 0;
4830 }
4831
4832 if (!i2c_verify_adapter(child))
4833 return 0;
4834
4835 dev = child;
4836 while ((dev = dev->parent))
4837 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
4838 goto found;
4839 return 0;
4840
4841 found:
4842 bp = dev_get_drvdata(dev);
4843 if (add)
4844 ptp_ocp_symlink(bp, child, "i2c");
4845 else
4846 sysfs_remove_link(&bp->dev.kobj, "i2c");
4847
4848 return 0;
4849 }
4850
4851 static struct notifier_block ptp_ocp_i2c_notifier = {
4852 .notifier_call = ptp_ocp_i2c_notifier_call,
4853 };
4854
4855 static int __init
ptp_ocp_init(void)4856 ptp_ocp_init(void)
4857 {
4858 const char *what;
4859 int err;
4860
4861 ptp_ocp_debugfs_init();
4862
4863 what = "timecard class";
4864 err = class_register(&timecard_class);
4865 if (err)
4866 goto out;
4867
4868 what = "i2c notifier";
4869 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4870 if (err)
4871 goto out_notifier;
4872
4873 what = "ptp_ocp driver";
4874 err = pci_register_driver(&ptp_ocp_driver);
4875 if (err)
4876 goto out_register;
4877
4878 return 0;
4879
4880 out_register:
4881 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4882 out_notifier:
4883 class_unregister(&timecard_class);
4884 out:
4885 ptp_ocp_debugfs_fini();
4886 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
4887 return err;
4888 }
4889
4890 static void __exit
ptp_ocp_fini(void)4891 ptp_ocp_fini(void)
4892 {
4893 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4894 pci_unregister_driver(&ptp_ocp_driver);
4895 class_unregister(&timecard_class);
4896 ptp_ocp_debugfs_fini();
4897 }
4898
4899 module_init(ptp_ocp_init);
4900 module_exit(ptp_ocp_fini);
4901
4902 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
4903 MODULE_LICENSE("GPL v2");
4904