1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2020 Facebook */
3
4 #include <linux/bits.h>
5 #include <linux/err.h>
6 #include <linux/kernel.h>
7 #include <linux/module.h>
8 #include <linux/debugfs.h>
9 #include <linux/init.h>
10 #include <linux/pci.h>
11 #include <linux/serial_8250.h>
12 #include <linux/clkdev.h>
13 #include <linux/clk-provider.h>
14 #include <linux/platform_device.h>
15 #include <linux/platform_data/i2c-xiic.h>
16 #include <linux/platform_data/i2c-ocores.h>
17 #include <linux/ptp_clock_kernel.h>
18 #include <linux/spi/spi.h>
19 #include <linux/spi/xilinx_spi.h>
20 #include <linux/spi/altera.h>
21 #include <net/devlink.h>
22 #include <linux/i2c.h>
23 #include <linux/mtd/mtd.h>
24 #include <linux/nvmem-consumer.h>
25 #include <linux/crc16.h>
26 #include <linux/dpll.h>
27
28 #define PCI_VENDOR_ID_FACEBOOK 0x1d9b
29 #define PCI_DEVICE_ID_FACEBOOK_TIMECARD 0x0400
30
31 #define PCI_VENDOR_ID_CELESTICA 0x18d4
32 #define PCI_DEVICE_ID_CELESTICA_TIMECARD 0x1008
33
34 #define PCI_VENDOR_ID_OROLIA 0x1ad7
35 #define PCI_DEVICE_ID_OROLIA_ARTCARD 0xa000
36
37 #define PCI_VENDOR_ID_ADVA 0xad5a
38 #define PCI_DEVICE_ID_ADVA_TIMECARD 0x0400
39
40 static struct class timecard_class = {
41 .name = "timecard",
42 };
43
44 struct ocp_reg {
45 u32 ctrl;
46 u32 status;
47 u32 select;
48 u32 version;
49 u32 time_ns;
50 u32 time_sec;
51 u32 __pad0[2];
52 u32 adjust_ns;
53 u32 adjust_sec;
54 u32 __pad1[2];
55 u32 offset_ns;
56 u32 offset_window_ns;
57 u32 __pad2[2];
58 u32 drift_ns;
59 u32 drift_window_ns;
60 u32 __pad3[6];
61 u32 servo_offset_p;
62 u32 servo_offset_i;
63 u32 servo_drift_p;
64 u32 servo_drift_i;
65 u32 status_offset;
66 u32 status_drift;
67 };
68
69 struct ptp_ocp_servo_conf {
70 u32 servo_offset_p;
71 u32 servo_offset_i;
72 u32 servo_drift_p;
73 u32 servo_drift_i;
74 };
75
76 #define OCP_CTRL_ENABLE BIT(0)
77 #define OCP_CTRL_ADJUST_TIME BIT(1)
78 #define OCP_CTRL_ADJUST_OFFSET BIT(2)
79 #define OCP_CTRL_ADJUST_DRIFT BIT(3)
80 #define OCP_CTRL_ADJUST_SERVO BIT(8)
81 #define OCP_CTRL_READ_TIME_REQ BIT(30)
82 #define OCP_CTRL_READ_TIME_DONE BIT(31)
83
84 #define OCP_STATUS_IN_SYNC BIT(0)
85 #define OCP_STATUS_IN_HOLDOVER BIT(1)
86
87 #define OCP_SELECT_CLK_NONE 0
88 #define OCP_SELECT_CLK_REG 0xfe
89
90 struct tod_reg {
91 u32 ctrl;
92 u32 status;
93 u32 uart_polarity;
94 u32 version;
95 u32 adj_sec;
96 u32 __pad0[3];
97 u32 uart_baud;
98 u32 __pad1[3];
99 u32 utc_status;
100 u32 leap;
101 };
102
103 #define TOD_CTRL_PROTOCOL BIT(28)
104 #define TOD_CTRL_DISABLE_FMT_A BIT(17)
105 #define TOD_CTRL_DISABLE_FMT_B BIT(16)
106 #define TOD_CTRL_ENABLE BIT(0)
107 #define TOD_CTRL_GNSS_MASK GENMASK(3, 0)
108 #define TOD_CTRL_GNSS_SHIFT 24
109
110 #define TOD_STATUS_UTC_MASK GENMASK(7, 0)
111 #define TOD_STATUS_UTC_VALID BIT(8)
112 #define TOD_STATUS_LEAP_ANNOUNCE BIT(12)
113 #define TOD_STATUS_LEAP_VALID BIT(16)
114
115 struct ts_reg {
116 u32 enable;
117 u32 error;
118 u32 polarity;
119 u32 version;
120 u32 __pad0[4];
121 u32 cable_delay;
122 u32 __pad1[3];
123 u32 intr;
124 u32 intr_mask;
125 u32 event_count;
126 u32 __pad2[1];
127 u32 ts_count;
128 u32 time_ns;
129 u32 time_sec;
130 u32 data_width;
131 u32 data;
132 };
133
134 struct pps_reg {
135 u32 ctrl;
136 u32 status;
137 u32 __pad0[6];
138 u32 cable_delay;
139 };
140
141 #define PPS_STATUS_FILTER_ERR BIT(0)
142 #define PPS_STATUS_SUPERV_ERR BIT(1)
143
144 struct img_reg {
145 u32 version;
146 };
147
148 struct gpio_reg {
149 u32 gpio1;
150 u32 __pad0;
151 u32 gpio2;
152 u32 __pad1;
153 };
154
155 struct irig_master_reg {
156 u32 ctrl;
157 u32 status;
158 u32 __pad0;
159 u32 version;
160 u32 adj_sec;
161 u32 mode_ctrl;
162 };
163
164 #define IRIG_M_CTRL_ENABLE BIT(0)
165
166 struct irig_slave_reg {
167 u32 ctrl;
168 u32 status;
169 u32 __pad0;
170 u32 version;
171 u32 adj_sec;
172 u32 mode_ctrl;
173 };
174
175 #define IRIG_S_CTRL_ENABLE BIT(0)
176
177 struct dcf_master_reg {
178 u32 ctrl;
179 u32 status;
180 u32 __pad0;
181 u32 version;
182 u32 adj_sec;
183 };
184
185 #define DCF_M_CTRL_ENABLE BIT(0)
186
187 struct dcf_slave_reg {
188 u32 ctrl;
189 u32 status;
190 u32 __pad0;
191 u32 version;
192 u32 adj_sec;
193 };
194
195 #define DCF_S_CTRL_ENABLE BIT(0)
196
197 struct signal_reg {
198 u32 enable;
199 u32 status;
200 u32 polarity;
201 u32 version;
202 u32 __pad0[4];
203 u32 cable_delay;
204 u32 __pad1[3];
205 u32 intr;
206 u32 intr_mask;
207 u32 __pad2[2];
208 u32 start_ns;
209 u32 start_sec;
210 u32 pulse_ns;
211 u32 pulse_sec;
212 u32 period_ns;
213 u32 period_sec;
214 u32 repeat_count;
215 };
216
217 struct frequency_reg {
218 u32 ctrl;
219 u32 status;
220 };
221
222 struct board_config_reg {
223 u32 mro50_serial_activate;
224 };
225
226 #define FREQ_STATUS_VALID BIT(31)
227 #define FREQ_STATUS_ERROR BIT(30)
228 #define FREQ_STATUS_OVERRUN BIT(29)
229 #define FREQ_STATUS_MASK GENMASK(23, 0)
230
231 struct ptp_ocp_flash_info {
232 const char *name;
233 int pci_offset;
234 int data_size;
235 void *data;
236 };
237
238 struct ptp_ocp_firmware_header {
239 char magic[4];
240 __be16 pci_vendor_id;
241 __be16 pci_device_id;
242 __be32 image_size;
243 __be16 hw_revision;
244 __be16 crc;
245 };
246
247 #define OCP_FIRMWARE_MAGIC_HEADER "OCPC"
248
249 struct ptp_ocp_i2c_info {
250 const char *name;
251 unsigned long fixed_rate;
252 size_t data_size;
253 void *data;
254 };
255
256 struct ptp_ocp_ext_info {
257 int index;
258 irqreturn_t (*irq_fcn)(int irq, void *priv);
259 int (*enable)(void *priv, u32 req, bool enable);
260 };
261
262 struct ptp_ocp_ext_src {
263 void __iomem *mem;
264 struct ptp_ocp *bp;
265 struct ptp_ocp_ext_info *info;
266 int irq_vec;
267 };
268
269 enum ptp_ocp_sma_mode {
270 SMA_MODE_IN,
271 SMA_MODE_OUT,
272 };
273
274 static struct dpll_pin_frequency ptp_ocp_sma_freq[] = {
275 DPLL_PIN_FREQUENCY_1PPS,
276 DPLL_PIN_FREQUENCY_10MHZ,
277 DPLL_PIN_FREQUENCY_IRIG_B,
278 DPLL_PIN_FREQUENCY_DCF77,
279 };
280
281 struct ptp_ocp_sma_connector {
282 enum ptp_ocp_sma_mode mode;
283 bool fixed_fcn;
284 bool fixed_dir;
285 bool disabled;
286 u8 default_fcn;
287 struct dpll_pin *dpll_pin;
288 struct dpll_pin_properties dpll_prop;
289 };
290
291 struct ocp_attr_group {
292 u64 cap;
293 const struct attribute_group *group;
294 };
295
296 #define OCP_CAP_BASIC BIT(0)
297 #define OCP_CAP_SIGNAL BIT(1)
298 #define OCP_CAP_FREQ BIT(2)
299
300 struct ptp_ocp_signal {
301 ktime_t period;
302 ktime_t pulse;
303 ktime_t phase;
304 ktime_t start;
305 int duty;
306 bool polarity;
307 bool running;
308 };
309
310 struct ptp_ocp_serial_port {
311 int line;
312 int baud;
313 };
314
315 #define OCP_BOARD_ID_LEN 13
316 #define OCP_SERIAL_LEN 6
317 #define OCP_SMA_NUM 4
318
319 enum {
320 PORT_GNSS,
321 PORT_GNSS2,
322 PORT_MAC, /* miniature atomic clock */
323 PORT_NMEA,
324
325 __PORT_COUNT,
326 };
327
328 struct ptp_ocp {
329 struct pci_dev *pdev;
330 struct device dev;
331 spinlock_t lock;
332 struct ocp_reg __iomem *reg;
333 struct tod_reg __iomem *tod;
334 struct pps_reg __iomem *pps_to_ext;
335 struct pps_reg __iomem *pps_to_clk;
336 struct board_config_reg __iomem *board_config;
337 struct gpio_reg __iomem *pps_select;
338 struct gpio_reg __iomem *sma_map1;
339 struct gpio_reg __iomem *sma_map2;
340 struct irig_master_reg __iomem *irig_out;
341 struct irig_slave_reg __iomem *irig_in;
342 struct dcf_master_reg __iomem *dcf_out;
343 struct dcf_slave_reg __iomem *dcf_in;
344 struct tod_reg __iomem *nmea_out;
345 struct frequency_reg __iomem *freq_in[4];
346 struct ptp_ocp_ext_src *signal_out[4];
347 struct ptp_ocp_ext_src *pps;
348 struct ptp_ocp_ext_src *ts0;
349 struct ptp_ocp_ext_src *ts1;
350 struct ptp_ocp_ext_src *ts2;
351 struct ptp_ocp_ext_src *ts3;
352 struct ptp_ocp_ext_src *ts4;
353 struct ocp_art_gpio_reg __iomem *art_sma;
354 struct img_reg __iomem *image;
355 struct ptp_clock *ptp;
356 struct ptp_clock_info ptp_info;
357 struct platform_device *i2c_ctrl;
358 struct platform_device *spi_flash;
359 struct clk_hw *i2c_clk;
360 struct timer_list watchdog;
361 const struct attribute_group **attr_group;
362 const struct ptp_ocp_eeprom_map *eeprom_map;
363 struct dentry *debug_root;
364 bool sync;
365 time64_t gnss_lost;
366 struct delayed_work sync_work;
367 int id;
368 int n_irqs;
369 struct ptp_ocp_serial_port port[__PORT_COUNT];
370 bool fw_loader;
371 u8 fw_tag;
372 u16 fw_version;
373 u8 board_id[OCP_BOARD_ID_LEN];
374 u8 serial[OCP_SERIAL_LEN];
375 bool has_eeprom_data;
376 u32 pps_req_map;
377 int flash_start;
378 u32 utc_tai_offset;
379 u32 ts_window_adjust;
380 u64 fw_cap;
381 struct ptp_ocp_signal signal[4];
382 struct ptp_ocp_sma_connector sma[OCP_SMA_NUM];
383 const struct ocp_sma_op *sma_op;
384 struct dpll_device *dpll;
385 };
386
387 #define OCP_REQ_TIMESTAMP BIT(0)
388 #define OCP_REQ_PPS BIT(1)
389
390 struct ocp_resource {
391 unsigned long offset;
392 int size;
393 int irq_vec;
394 int (*setup)(struct ptp_ocp *bp, struct ocp_resource *r);
395 void *extra;
396 unsigned long bp_offset;
397 const char * const name;
398 };
399
400 static int ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r);
401 static int ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r);
402 static int ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r);
403 static int ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r);
404 static int ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r);
405 static int ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
406 static irqreturn_t ptp_ocp_ts_irq(int irq, void *priv);
407 static irqreturn_t ptp_ocp_signal_irq(int irq, void *priv);
408 static int ptp_ocp_ts_enable(void *priv, u32 req, bool enable);
409 static int ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
410 struct ptp_perout_request *req);
411 static int ptp_ocp_signal_enable(void *priv, u32 req, bool enable);
412 static int ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr);
413
414 static int ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
415
416 static int ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r);
417
418 static const struct ocp_attr_group fb_timecard_groups[];
419
420 static const struct ocp_attr_group art_timecard_groups[];
421
422 static const struct ocp_attr_group adva_timecard_groups[];
423
424 struct ptp_ocp_eeprom_map {
425 u16 off;
426 u16 len;
427 u32 bp_offset;
428 const void * const tag;
429 };
430
431 #define EEPROM_ENTRY(addr, member) \
432 .off = addr, \
433 .len = sizeof_field(struct ptp_ocp, member), \
434 .bp_offset = offsetof(struct ptp_ocp, member)
435
436 #define BP_MAP_ENTRY_ADDR(bp, map) ({ \
437 (void *)((uintptr_t)(bp) + (map)->bp_offset); \
438 })
439
440 static struct ptp_ocp_eeprom_map fb_eeprom_map[] = {
441 { EEPROM_ENTRY(0x43, board_id) },
442 { EEPROM_ENTRY(0x00, serial), .tag = "mac" },
443 { }
444 };
445
446 static struct ptp_ocp_eeprom_map art_eeprom_map[] = {
447 { EEPROM_ENTRY(0x200 + 0x43, board_id) },
448 { EEPROM_ENTRY(0x200 + 0x63, serial) },
449 { }
450 };
451
452 #define bp_assign_entry(bp, res, val) ({ \
453 uintptr_t addr = (uintptr_t)(bp) + (res)->bp_offset; \
454 *(typeof(val) *)addr = val; \
455 })
456
457 #define OCP_RES_LOCATION(member) \
458 .name = #member, .bp_offset = offsetof(struct ptp_ocp, member)
459
460 #define OCP_MEM_RESOURCE(member) \
461 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_mem
462
463 #define OCP_SERIAL_RESOURCE(member) \
464 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_serial
465
466 #define OCP_I2C_RESOURCE(member) \
467 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_i2c
468
469 #define OCP_SPI_RESOURCE(member) \
470 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_spi
471
472 #define OCP_EXT_RESOURCE(member) \
473 OCP_RES_LOCATION(member), .setup = ptp_ocp_register_ext
474
475 /* This is the MSI vector mapping used.
476 * 0: PPS (TS5)
477 * 1: TS0
478 * 2: TS1
479 * 3: GNSS1
480 * 4: GNSS2
481 * 5: MAC
482 * 6: TS2
483 * 7: I2C controller
484 * 8: HWICAP (notused)
485 * 9: SPI Flash
486 * 10: NMEA
487 * 11: Signal Generator 1
488 * 12: Signal Generator 2
489 * 13: Signal Generator 3
490 * 14: Signal Generator 4
491 * 15: TS3
492 * 16: TS4
493 --
494 * 8: Orolia TS1
495 * 10: Orolia TS2
496 * 11: Orolia TS0 (GNSS)
497 * 12: Orolia PPS
498 * 14: Orolia TS3
499 * 15: Orolia TS4
500 */
501
502 static struct ocp_resource ocp_fb_resource[] = {
503 {
504 OCP_MEM_RESOURCE(reg),
505 .offset = 0x01000000, .size = 0x10000,
506 },
507 {
508 OCP_EXT_RESOURCE(ts0),
509 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
510 .extra = &(struct ptp_ocp_ext_info) {
511 .index = 0,
512 .irq_fcn = ptp_ocp_ts_irq,
513 .enable = ptp_ocp_ts_enable,
514 },
515 },
516 {
517 OCP_EXT_RESOURCE(ts1),
518 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
519 .extra = &(struct ptp_ocp_ext_info) {
520 .index = 1,
521 .irq_fcn = ptp_ocp_ts_irq,
522 .enable = ptp_ocp_ts_enable,
523 },
524 },
525 {
526 OCP_EXT_RESOURCE(ts2),
527 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
528 .extra = &(struct ptp_ocp_ext_info) {
529 .index = 2,
530 .irq_fcn = ptp_ocp_ts_irq,
531 .enable = ptp_ocp_ts_enable,
532 },
533 },
534 {
535 OCP_EXT_RESOURCE(ts3),
536 .offset = 0x01110000, .size = 0x10000, .irq_vec = 15,
537 .extra = &(struct ptp_ocp_ext_info) {
538 .index = 3,
539 .irq_fcn = ptp_ocp_ts_irq,
540 .enable = ptp_ocp_ts_enable,
541 },
542 },
543 {
544 OCP_EXT_RESOURCE(ts4),
545 .offset = 0x01120000, .size = 0x10000, .irq_vec = 16,
546 .extra = &(struct ptp_ocp_ext_info) {
547 .index = 4,
548 .irq_fcn = ptp_ocp_ts_irq,
549 .enable = ptp_ocp_ts_enable,
550 },
551 },
552 /* Timestamp for PHC and/or PPS generator */
553 {
554 OCP_EXT_RESOURCE(pps),
555 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
556 .extra = &(struct ptp_ocp_ext_info) {
557 .index = 5,
558 .irq_fcn = ptp_ocp_ts_irq,
559 .enable = ptp_ocp_ts_enable,
560 },
561 },
562 {
563 OCP_EXT_RESOURCE(signal_out[0]),
564 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
565 .extra = &(struct ptp_ocp_ext_info) {
566 .index = 1,
567 .irq_fcn = ptp_ocp_signal_irq,
568 .enable = ptp_ocp_signal_enable,
569 },
570 },
571 {
572 OCP_EXT_RESOURCE(signal_out[1]),
573 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
574 .extra = &(struct ptp_ocp_ext_info) {
575 .index = 2,
576 .irq_fcn = ptp_ocp_signal_irq,
577 .enable = ptp_ocp_signal_enable,
578 },
579 },
580 {
581 OCP_EXT_RESOURCE(signal_out[2]),
582 .offset = 0x010F0000, .size = 0x10000, .irq_vec = 13,
583 .extra = &(struct ptp_ocp_ext_info) {
584 .index = 3,
585 .irq_fcn = ptp_ocp_signal_irq,
586 .enable = ptp_ocp_signal_enable,
587 },
588 },
589 {
590 OCP_EXT_RESOURCE(signal_out[3]),
591 .offset = 0x01100000, .size = 0x10000, .irq_vec = 14,
592 .extra = &(struct ptp_ocp_ext_info) {
593 .index = 4,
594 .irq_fcn = ptp_ocp_signal_irq,
595 .enable = ptp_ocp_signal_enable,
596 },
597 },
598 {
599 OCP_MEM_RESOURCE(pps_to_ext),
600 .offset = 0x01030000, .size = 0x10000,
601 },
602 {
603 OCP_MEM_RESOURCE(pps_to_clk),
604 .offset = 0x01040000, .size = 0x10000,
605 },
606 {
607 OCP_MEM_RESOURCE(tod),
608 .offset = 0x01050000, .size = 0x10000,
609 },
610 {
611 OCP_MEM_RESOURCE(irig_in),
612 .offset = 0x01070000, .size = 0x10000,
613 },
614 {
615 OCP_MEM_RESOURCE(irig_out),
616 .offset = 0x01080000, .size = 0x10000,
617 },
618 {
619 OCP_MEM_RESOURCE(dcf_in),
620 .offset = 0x01090000, .size = 0x10000,
621 },
622 {
623 OCP_MEM_RESOURCE(dcf_out),
624 .offset = 0x010A0000, .size = 0x10000,
625 },
626 {
627 OCP_MEM_RESOURCE(nmea_out),
628 .offset = 0x010B0000, .size = 0x10000,
629 },
630 {
631 OCP_MEM_RESOURCE(image),
632 .offset = 0x00020000, .size = 0x1000,
633 },
634 {
635 OCP_MEM_RESOURCE(pps_select),
636 .offset = 0x00130000, .size = 0x1000,
637 },
638 {
639 OCP_MEM_RESOURCE(sma_map1),
640 .offset = 0x00140000, .size = 0x1000,
641 },
642 {
643 OCP_MEM_RESOURCE(sma_map2),
644 .offset = 0x00220000, .size = 0x1000,
645 },
646 {
647 OCP_I2C_RESOURCE(i2c_ctrl),
648 .offset = 0x00150000, .size = 0x10000, .irq_vec = 7,
649 .extra = &(struct ptp_ocp_i2c_info) {
650 .name = "xiic-i2c",
651 .fixed_rate = 50000000,
652 .data_size = sizeof(struct xiic_i2c_platform_data),
653 .data = &(struct xiic_i2c_platform_data) {
654 .num_devices = 2,
655 .devices = (struct i2c_board_info[]) {
656 { I2C_BOARD_INFO("24c02", 0x50) },
657 { I2C_BOARD_INFO("24mac402", 0x58),
658 .platform_data = "mac" },
659 },
660 },
661 },
662 },
663 {
664 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
665 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
666 .extra = &(struct ptp_ocp_serial_port) {
667 .baud = 115200,
668 },
669 },
670 {
671 OCP_SERIAL_RESOURCE(port[PORT_GNSS2]),
672 .offset = 0x00170000 + 0x1000, .irq_vec = 4,
673 .extra = &(struct ptp_ocp_serial_port) {
674 .baud = 115200,
675 },
676 },
677 {
678 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
679 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
680 .extra = &(struct ptp_ocp_serial_port) {
681 .baud = 57600,
682 },
683 },
684 {
685 OCP_SERIAL_RESOURCE(port[PORT_NMEA]),
686 .offset = 0x00190000 + 0x1000, .irq_vec = 10,
687 },
688 {
689 OCP_SPI_RESOURCE(spi_flash),
690 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
691 .extra = &(struct ptp_ocp_flash_info) {
692 .name = "xilinx_spi", .pci_offset = 0,
693 .data_size = sizeof(struct xspi_platform_data),
694 .data = &(struct xspi_platform_data) {
695 .num_chipselect = 1,
696 .bits_per_word = 8,
697 .num_devices = 1,
698 .force_irq = true,
699 .devices = &(struct spi_board_info) {
700 .modalias = "spi-nor",
701 },
702 },
703 },
704 },
705 {
706 OCP_MEM_RESOURCE(freq_in[0]),
707 .offset = 0x01200000, .size = 0x10000,
708 },
709 {
710 OCP_MEM_RESOURCE(freq_in[1]),
711 .offset = 0x01210000, .size = 0x10000,
712 },
713 {
714 OCP_MEM_RESOURCE(freq_in[2]),
715 .offset = 0x01220000, .size = 0x10000,
716 },
717 {
718 OCP_MEM_RESOURCE(freq_in[3]),
719 .offset = 0x01230000, .size = 0x10000,
720 },
721 {
722 .setup = ptp_ocp_fb_board_init,
723 .extra = &(struct ptp_ocp_servo_conf) {
724 .servo_offset_p = 0x2000,
725 .servo_offset_i = 0x1000,
726 .servo_drift_p = 0,
727 .servo_drift_i = 0,
728 },
729 },
730 { }
731 };
732
733 #define OCP_ART_CONFIG_SIZE 144
734 #define OCP_ART_TEMP_TABLE_SIZE 368
735
736 struct ocp_art_gpio_reg {
737 struct {
738 u32 gpio;
739 u32 __pad[3];
740 } map[4];
741 };
742
743 static struct ocp_resource ocp_art_resource[] = {
744 {
745 OCP_MEM_RESOURCE(reg),
746 .offset = 0x01000000, .size = 0x10000,
747 },
748 {
749 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
750 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
751 .extra = &(struct ptp_ocp_serial_port) {
752 .baud = 115200,
753 },
754 },
755 {
756 OCP_MEM_RESOURCE(art_sma),
757 .offset = 0x003C0000, .size = 0x1000,
758 },
759 /* Timestamp associated with GNSS1 receiver PPS */
760 {
761 OCP_EXT_RESOURCE(ts0),
762 .offset = 0x360000, .size = 0x20, .irq_vec = 12,
763 .extra = &(struct ptp_ocp_ext_info) {
764 .index = 0,
765 .irq_fcn = ptp_ocp_ts_irq,
766 .enable = ptp_ocp_ts_enable,
767 },
768 },
769 {
770 OCP_EXT_RESOURCE(ts1),
771 .offset = 0x380000, .size = 0x20, .irq_vec = 8,
772 .extra = &(struct ptp_ocp_ext_info) {
773 .index = 1,
774 .irq_fcn = ptp_ocp_ts_irq,
775 .enable = ptp_ocp_ts_enable,
776 },
777 },
778 {
779 OCP_EXT_RESOURCE(ts2),
780 .offset = 0x390000, .size = 0x20, .irq_vec = 10,
781 .extra = &(struct ptp_ocp_ext_info) {
782 .index = 2,
783 .irq_fcn = ptp_ocp_ts_irq,
784 .enable = ptp_ocp_ts_enable,
785 },
786 },
787 {
788 OCP_EXT_RESOURCE(ts3),
789 .offset = 0x3A0000, .size = 0x20, .irq_vec = 14,
790 .extra = &(struct ptp_ocp_ext_info) {
791 .index = 3,
792 .irq_fcn = ptp_ocp_ts_irq,
793 .enable = ptp_ocp_ts_enable,
794 },
795 },
796 {
797 OCP_EXT_RESOURCE(ts4),
798 .offset = 0x3B0000, .size = 0x20, .irq_vec = 15,
799 .extra = &(struct ptp_ocp_ext_info) {
800 .index = 4,
801 .irq_fcn = ptp_ocp_ts_irq,
802 .enable = ptp_ocp_ts_enable,
803 },
804 },
805 /* Timestamp associated with Internal PPS of the card */
806 {
807 OCP_EXT_RESOURCE(pps),
808 .offset = 0x00330000, .size = 0x20, .irq_vec = 11,
809 .extra = &(struct ptp_ocp_ext_info) {
810 .index = 5,
811 .irq_fcn = ptp_ocp_ts_irq,
812 .enable = ptp_ocp_ts_enable,
813 },
814 },
815 {
816 OCP_SPI_RESOURCE(spi_flash),
817 .offset = 0x00310000, .size = 0x10000, .irq_vec = 9,
818 .extra = &(struct ptp_ocp_flash_info) {
819 .name = "spi_altera", .pci_offset = 0,
820 .data_size = sizeof(struct altera_spi_platform_data),
821 .data = &(struct altera_spi_platform_data) {
822 .num_chipselect = 1,
823 .num_devices = 1,
824 .devices = &(struct spi_board_info) {
825 .modalias = "spi-nor",
826 },
827 },
828 },
829 },
830 {
831 OCP_I2C_RESOURCE(i2c_ctrl),
832 .offset = 0x350000, .size = 0x100, .irq_vec = 4,
833 .extra = &(struct ptp_ocp_i2c_info) {
834 .name = "ocores-i2c",
835 .fixed_rate = 400000,
836 .data_size = sizeof(struct ocores_i2c_platform_data),
837 .data = &(struct ocores_i2c_platform_data) {
838 .clock_khz = 125000,
839 .bus_khz = 400,
840 .num_devices = 1,
841 .devices = &(struct i2c_board_info) {
842 I2C_BOARD_INFO("24c08", 0x50),
843 },
844 },
845 },
846 },
847 {
848 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
849 .offset = 0x00190000, .irq_vec = 7,
850 .extra = &(struct ptp_ocp_serial_port) {
851 .baud = 9600,
852 },
853 },
854 {
855 OCP_MEM_RESOURCE(board_config),
856 .offset = 0x210000, .size = 0x1000,
857 },
858 {
859 .setup = ptp_ocp_art_board_init,
860 .extra = &(struct ptp_ocp_servo_conf) {
861 .servo_offset_p = 0x2000,
862 .servo_offset_i = 0x1000,
863 .servo_drift_p = 0,
864 .servo_drift_i = 0,
865 },
866 },
867 { }
868 };
869
870 static struct ocp_resource ocp_adva_resource[] = {
871 {
872 OCP_MEM_RESOURCE(reg),
873 .offset = 0x01000000, .size = 0x10000,
874 },
875 {
876 OCP_EXT_RESOURCE(ts0),
877 .offset = 0x01010000, .size = 0x10000, .irq_vec = 1,
878 .extra = &(struct ptp_ocp_ext_info) {
879 .index = 0,
880 .irq_fcn = ptp_ocp_ts_irq,
881 .enable = ptp_ocp_ts_enable,
882 },
883 },
884 {
885 OCP_EXT_RESOURCE(ts1),
886 .offset = 0x01020000, .size = 0x10000, .irq_vec = 2,
887 .extra = &(struct ptp_ocp_ext_info) {
888 .index = 1,
889 .irq_fcn = ptp_ocp_ts_irq,
890 .enable = ptp_ocp_ts_enable,
891 },
892 },
893 {
894 OCP_EXT_RESOURCE(ts2),
895 .offset = 0x01060000, .size = 0x10000, .irq_vec = 6,
896 .extra = &(struct ptp_ocp_ext_info) {
897 .index = 2,
898 .irq_fcn = ptp_ocp_ts_irq,
899 .enable = ptp_ocp_ts_enable,
900 },
901 },
902 /* Timestamp for PHC and/or PPS generator */
903 {
904 OCP_EXT_RESOURCE(pps),
905 .offset = 0x010C0000, .size = 0x10000, .irq_vec = 0,
906 .extra = &(struct ptp_ocp_ext_info) {
907 .index = 5,
908 .irq_fcn = ptp_ocp_ts_irq,
909 .enable = ptp_ocp_ts_enable,
910 },
911 },
912 {
913 OCP_EXT_RESOURCE(signal_out[0]),
914 .offset = 0x010D0000, .size = 0x10000, .irq_vec = 11,
915 .extra = &(struct ptp_ocp_ext_info) {
916 .index = 1,
917 .irq_fcn = ptp_ocp_signal_irq,
918 .enable = ptp_ocp_signal_enable,
919 },
920 },
921 {
922 OCP_EXT_RESOURCE(signal_out[1]),
923 .offset = 0x010E0000, .size = 0x10000, .irq_vec = 12,
924 .extra = &(struct ptp_ocp_ext_info) {
925 .index = 2,
926 .irq_fcn = ptp_ocp_signal_irq,
927 .enable = ptp_ocp_signal_enable,
928 },
929 },
930 {
931 OCP_MEM_RESOURCE(pps_to_ext),
932 .offset = 0x01030000, .size = 0x10000,
933 },
934 {
935 OCP_MEM_RESOURCE(pps_to_clk),
936 .offset = 0x01040000, .size = 0x10000,
937 },
938 {
939 OCP_MEM_RESOURCE(tod),
940 .offset = 0x01050000, .size = 0x10000,
941 },
942 {
943 OCP_MEM_RESOURCE(image),
944 .offset = 0x00020000, .size = 0x1000,
945 },
946 {
947 OCP_MEM_RESOURCE(pps_select),
948 .offset = 0x00130000, .size = 0x1000,
949 },
950 {
951 OCP_MEM_RESOURCE(sma_map1),
952 .offset = 0x00140000, .size = 0x1000,
953 },
954 {
955 OCP_MEM_RESOURCE(sma_map2),
956 .offset = 0x00220000, .size = 0x1000,
957 },
958 {
959 OCP_SERIAL_RESOURCE(port[PORT_GNSS]),
960 .offset = 0x00160000 + 0x1000, .irq_vec = 3,
961 .extra = &(struct ptp_ocp_serial_port) {
962 .baud = 9600,
963 },
964 },
965 {
966 OCP_SERIAL_RESOURCE(port[PORT_MAC]),
967 .offset = 0x00180000 + 0x1000, .irq_vec = 5,
968 .extra = &(struct ptp_ocp_serial_port) {
969 .baud = 115200,
970 },
971 },
972 {
973 OCP_MEM_RESOURCE(freq_in[0]),
974 .offset = 0x01200000, .size = 0x10000,
975 },
976 {
977 OCP_MEM_RESOURCE(freq_in[1]),
978 .offset = 0x01210000, .size = 0x10000,
979 },
980 {
981 OCP_SPI_RESOURCE(spi_flash),
982 .offset = 0x00310400, .size = 0x10000, .irq_vec = 9,
983 .extra = &(struct ptp_ocp_flash_info) {
984 .name = "spi_altera", .pci_offset = 0,
985 .data_size = sizeof(struct altera_spi_platform_data),
986 .data = &(struct altera_spi_platform_data) {
987 .num_chipselect = 1,
988 .num_devices = 1,
989 .devices = &(struct spi_board_info) {
990 .modalias = "spi-nor",
991 },
992 },
993 },
994 },
995 {
996 OCP_I2C_RESOURCE(i2c_ctrl),
997 .offset = 0x150000, .size = 0x100, .irq_vec = 7,
998 .extra = &(struct ptp_ocp_i2c_info) {
999 .name = "ocores-i2c",
1000 .fixed_rate = 50000000,
1001 .data_size = sizeof(struct ocores_i2c_platform_data),
1002 .data = &(struct ocores_i2c_platform_data) {
1003 .clock_khz = 50000,
1004 .bus_khz = 100,
1005 .reg_io_width = 4, // 32-bit/4-byte
1006 .reg_shift = 2, // 32-bit addressing
1007 .num_devices = 2,
1008 .devices = (struct i2c_board_info[]) {
1009 { I2C_BOARD_INFO("24c02", 0x50) },
1010 { I2C_BOARD_INFO("24mac402", 0x58),
1011 .platform_data = "mac" },
1012 },
1013 },
1014 },
1015 },
1016 {
1017 .setup = ptp_ocp_adva_board_init,
1018 .extra = &(struct ptp_ocp_servo_conf) {
1019 .servo_offset_p = 0xc000,
1020 .servo_offset_i = 0x1000,
1021 .servo_drift_p = 0,
1022 .servo_drift_i = 0,
1023 },
1024 },
1025 { }
1026 };
1027
1028 static const struct pci_device_id ptp_ocp_pcidev_id[] = {
1029 { PCI_DEVICE_DATA(FACEBOOK, TIMECARD, &ocp_fb_resource) },
1030 { PCI_DEVICE_DATA(CELESTICA, TIMECARD, &ocp_fb_resource) },
1031 { PCI_DEVICE_DATA(OROLIA, ARTCARD, &ocp_art_resource) },
1032 { PCI_DEVICE_DATA(ADVA, TIMECARD, &ocp_adva_resource) },
1033 { }
1034 };
1035 MODULE_DEVICE_TABLE(pci, ptp_ocp_pcidev_id);
1036
1037 static DEFINE_MUTEX(ptp_ocp_lock);
1038 static DEFINE_IDR(ptp_ocp_idr);
1039
1040 struct ocp_selector {
1041 const char *name;
1042 int value;
1043 u64 frequency;
1044 };
1045
1046 static const struct ocp_selector ptp_ocp_clock[] = {
1047 { .name = "NONE", .value = 0 },
1048 { .name = "TOD", .value = 1 },
1049 { .name = "IRIG", .value = 2 },
1050 { .name = "PPS", .value = 3 },
1051 { .name = "PTP", .value = 4 },
1052 { .name = "RTC", .value = 5 },
1053 { .name = "DCF", .value = 6 },
1054 { .name = "REGS", .value = 0xfe },
1055 { .name = "EXT", .value = 0xff },
1056 { }
1057 };
1058
1059 #define SMA_DISABLE BIT(16)
1060 #define SMA_ENABLE BIT(15)
1061 #define SMA_SELECT_MASK GENMASK(14, 0)
1062
1063 static const struct ocp_selector ptp_ocp_sma_in[] = {
1064 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1065 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1066 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1067 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1068 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1069 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1070 { .name = "DCF", .value = 0x0020, .frequency = 77500 },
1071 { .name = "TS3", .value = 0x0040, .frequency = 0 },
1072 { .name = "TS4", .value = 0x0080, .frequency = 0 },
1073 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1074 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1075 { .name = "FREQ3", .value = 0x0400, .frequency = 0 },
1076 { .name = "FREQ4", .value = 0x0800, .frequency = 0 },
1077 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1078 { }
1079 };
1080
1081 static const struct ocp_selector ptp_ocp_sma_out[] = {
1082 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000 },
1083 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1084 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1085 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1086 { .name = "GNSS2", .value = 0x0008, .frequency = 1 },
1087 { .name = "IRIG", .value = 0x0010, .frequency = 10000 },
1088 { .name = "DCF", .value = 0x0020, .frequency = 77000 },
1089 { .name = "GEN1", .value = 0x0040 },
1090 { .name = "GEN2", .value = 0x0080 },
1091 { .name = "GEN3", .value = 0x0100 },
1092 { .name = "GEN4", .value = 0x0200 },
1093 { .name = "GND", .value = 0x2000 },
1094 { .name = "VCC", .value = 0x4000 },
1095 { }
1096 };
1097
1098 static const struct ocp_selector ptp_ocp_art_sma_in[] = {
1099 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1100 { .name = "10Mhz", .value = 0x0008, .frequency = 1000000 },
1101 { }
1102 };
1103
1104 static const struct ocp_selector ptp_ocp_art_sma_out[] = {
1105 { .name = "PHC", .value = 0x0002, .frequency = 1 },
1106 { .name = "GNSS", .value = 0x0004, .frequency = 1 },
1107 { .name = "10Mhz", .value = 0x0010, .frequency = 10000000 },
1108 { }
1109 };
1110
1111 static const struct ocp_selector ptp_ocp_adva_sma_in[] = {
1112 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1113 { .name = "PPS1", .value = 0x0001, .frequency = 1 },
1114 { .name = "PPS2", .value = 0x0002, .frequency = 1 },
1115 { .name = "TS1", .value = 0x0004, .frequency = 0 },
1116 { .name = "TS2", .value = 0x0008, .frequency = 0 },
1117 { .name = "FREQ1", .value = 0x0100, .frequency = 0 },
1118 { .name = "FREQ2", .value = 0x0200, .frequency = 0 },
1119 { .name = "None", .value = SMA_DISABLE, .frequency = 0 },
1120 { }
1121 };
1122
1123 static const struct ocp_selector ptp_ocp_adva_sma_out[] = {
1124 { .name = "10Mhz", .value = 0x0000, .frequency = 10000000},
1125 { .name = "PHC", .value = 0x0001, .frequency = 1 },
1126 { .name = "MAC", .value = 0x0002, .frequency = 1 },
1127 { .name = "GNSS1", .value = 0x0004, .frequency = 1 },
1128 { .name = "GEN1", .value = 0x0040 },
1129 { .name = "GEN2", .value = 0x0080 },
1130 { .name = "GND", .value = 0x2000 },
1131 { .name = "VCC", .value = 0x4000 },
1132 { }
1133 };
1134
1135 struct ocp_sma_op {
1136 const struct ocp_selector *tbl[2];
1137 void (*init)(struct ptp_ocp *bp);
1138 u32 (*get)(struct ptp_ocp *bp, int sma_nr);
1139 int (*set_inputs)(struct ptp_ocp *bp, int sma_nr, u32 val);
1140 int (*set_output)(struct ptp_ocp *bp, int sma_nr, u32 val);
1141 };
1142
1143 static void
ptp_ocp_sma_init(struct ptp_ocp * bp)1144 ptp_ocp_sma_init(struct ptp_ocp *bp)
1145 {
1146 return bp->sma_op->init(bp);
1147 }
1148
1149 static u32
ptp_ocp_sma_get(struct ptp_ocp * bp,int sma_nr)1150 ptp_ocp_sma_get(struct ptp_ocp *bp, int sma_nr)
1151 {
1152 return bp->sma_op->get(bp, sma_nr);
1153 }
1154
1155 static int
ptp_ocp_sma_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)1156 ptp_ocp_sma_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
1157 {
1158 return bp->sma_op->set_inputs(bp, sma_nr, val);
1159 }
1160
1161 static int
ptp_ocp_sma_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)1162 ptp_ocp_sma_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
1163 {
1164 return bp->sma_op->set_output(bp, sma_nr, val);
1165 }
1166
1167 static const char *
ptp_ocp_select_name_from_val(const struct ocp_selector * tbl,int val)1168 ptp_ocp_select_name_from_val(const struct ocp_selector *tbl, int val)
1169 {
1170 int i;
1171
1172 for (i = 0; tbl[i].name; i++)
1173 if (tbl[i].value == val)
1174 return tbl[i].name;
1175 return NULL;
1176 }
1177
1178 static int
ptp_ocp_select_val_from_name(const struct ocp_selector * tbl,const char * name)1179 ptp_ocp_select_val_from_name(const struct ocp_selector *tbl, const char *name)
1180 {
1181 const char *select;
1182 int i;
1183
1184 for (i = 0; tbl[i].name; i++) {
1185 select = tbl[i].name;
1186 if (!strncasecmp(name, select, strlen(select)))
1187 return tbl[i].value;
1188 }
1189 return -EINVAL;
1190 }
1191
1192 static ssize_t
ptp_ocp_select_table_show(const struct ocp_selector * tbl,char * buf)1193 ptp_ocp_select_table_show(const struct ocp_selector *tbl, char *buf)
1194 {
1195 ssize_t count;
1196 int i;
1197
1198 count = 0;
1199 for (i = 0; tbl[i].name; i++)
1200 count += sysfs_emit_at(buf, count, "%s ", tbl[i].name);
1201 if (count)
1202 count--;
1203 count += sysfs_emit_at(buf, count, "\n");
1204 return count;
1205 }
1206
1207 static int
__ptp_ocp_gettime_locked(struct ptp_ocp * bp,struct timespec64 * ts,struct ptp_system_timestamp * sts)1208 __ptp_ocp_gettime_locked(struct ptp_ocp *bp, struct timespec64 *ts,
1209 struct ptp_system_timestamp *sts)
1210 {
1211 u32 ctrl, time_sec, time_ns;
1212 int i;
1213
1214 ptp_read_system_prets(sts);
1215
1216 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1217 iowrite32(ctrl, &bp->reg->ctrl);
1218
1219 for (i = 0; i < 100; i++) {
1220 ctrl = ioread32(&bp->reg->ctrl);
1221 if (ctrl & OCP_CTRL_READ_TIME_DONE)
1222 break;
1223 }
1224 ptp_read_system_postts(sts);
1225
1226 if (sts && bp->ts_window_adjust) {
1227 s64 ns = timespec64_to_ns(&sts->post_ts);
1228
1229 sts->post_ts = ns_to_timespec64(ns - bp->ts_window_adjust);
1230 }
1231
1232 time_ns = ioread32(&bp->reg->time_ns);
1233 time_sec = ioread32(&bp->reg->time_sec);
1234
1235 ts->tv_sec = time_sec;
1236 ts->tv_nsec = time_ns;
1237
1238 return ctrl & OCP_CTRL_READ_TIME_DONE ? 0 : -ETIMEDOUT;
1239 }
1240
1241 static int
ptp_ocp_gettimex(struct ptp_clock_info * ptp_info,struct timespec64 * ts,struct ptp_system_timestamp * sts)1242 ptp_ocp_gettimex(struct ptp_clock_info *ptp_info, struct timespec64 *ts,
1243 struct ptp_system_timestamp *sts)
1244 {
1245 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1246 unsigned long flags;
1247 int err;
1248
1249 spin_lock_irqsave(&bp->lock, flags);
1250 err = __ptp_ocp_gettime_locked(bp, ts, sts);
1251 spin_unlock_irqrestore(&bp->lock, flags);
1252
1253 return err;
1254 }
1255
1256 static void
__ptp_ocp_settime_locked(struct ptp_ocp * bp,const struct timespec64 * ts)1257 __ptp_ocp_settime_locked(struct ptp_ocp *bp, const struct timespec64 *ts)
1258 {
1259 u32 ctrl, time_sec, time_ns;
1260 u32 select;
1261
1262 time_ns = ts->tv_nsec;
1263 time_sec = ts->tv_sec;
1264
1265 select = ioread32(&bp->reg->select);
1266 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1267
1268 iowrite32(time_ns, &bp->reg->adjust_ns);
1269 iowrite32(time_sec, &bp->reg->adjust_sec);
1270
1271 ctrl = OCP_CTRL_ADJUST_TIME | OCP_CTRL_ENABLE;
1272 iowrite32(ctrl, &bp->reg->ctrl);
1273
1274 /* restore clock selection */
1275 iowrite32(select >> 16, &bp->reg->select);
1276 }
1277
1278 static int
ptp_ocp_settime(struct ptp_clock_info * ptp_info,const struct timespec64 * ts)1279 ptp_ocp_settime(struct ptp_clock_info *ptp_info, const struct timespec64 *ts)
1280 {
1281 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1282 unsigned long flags;
1283
1284 spin_lock_irqsave(&bp->lock, flags);
1285 __ptp_ocp_settime_locked(bp, ts);
1286 spin_unlock_irqrestore(&bp->lock, flags);
1287
1288 return 0;
1289 }
1290
1291 static void
__ptp_ocp_adjtime_locked(struct ptp_ocp * bp,u32 adj_val)1292 __ptp_ocp_adjtime_locked(struct ptp_ocp *bp, u32 adj_val)
1293 {
1294 u32 select, ctrl;
1295
1296 select = ioread32(&bp->reg->select);
1297 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1298
1299 iowrite32(adj_val, &bp->reg->offset_ns);
1300 iowrite32(NSEC_PER_SEC, &bp->reg->offset_window_ns);
1301
1302 ctrl = OCP_CTRL_ADJUST_OFFSET | OCP_CTRL_ENABLE;
1303 iowrite32(ctrl, &bp->reg->ctrl);
1304
1305 /* restore clock selection */
1306 iowrite32(select >> 16, &bp->reg->select);
1307 }
1308
1309 static void
ptp_ocp_adjtime_coarse(struct ptp_ocp * bp,s64 delta_ns)1310 ptp_ocp_adjtime_coarse(struct ptp_ocp *bp, s64 delta_ns)
1311 {
1312 struct timespec64 ts;
1313 unsigned long flags;
1314 int err;
1315
1316 spin_lock_irqsave(&bp->lock, flags);
1317 err = __ptp_ocp_gettime_locked(bp, &ts, NULL);
1318 if (likely(!err)) {
1319 set_normalized_timespec64(&ts, ts.tv_sec,
1320 ts.tv_nsec + delta_ns);
1321 __ptp_ocp_settime_locked(bp, &ts);
1322 }
1323 spin_unlock_irqrestore(&bp->lock, flags);
1324 }
1325
1326 static int
ptp_ocp_adjtime(struct ptp_clock_info * ptp_info,s64 delta_ns)1327 ptp_ocp_adjtime(struct ptp_clock_info *ptp_info, s64 delta_ns)
1328 {
1329 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1330 unsigned long flags;
1331 u32 adj_ns, sign;
1332
1333 if (delta_ns > NSEC_PER_SEC || -delta_ns > NSEC_PER_SEC) {
1334 ptp_ocp_adjtime_coarse(bp, delta_ns);
1335 return 0;
1336 }
1337
1338 sign = delta_ns < 0 ? BIT(31) : 0;
1339 adj_ns = sign ? -delta_ns : delta_ns;
1340
1341 spin_lock_irqsave(&bp->lock, flags);
1342 __ptp_ocp_adjtime_locked(bp, sign | adj_ns);
1343 spin_unlock_irqrestore(&bp->lock, flags);
1344
1345 return 0;
1346 }
1347
1348 static int
ptp_ocp_null_adjfine(struct ptp_clock_info * ptp_info,long scaled_ppm)1349 ptp_ocp_null_adjfine(struct ptp_clock_info *ptp_info, long scaled_ppm)
1350 {
1351 if (scaled_ppm == 0)
1352 return 0;
1353
1354 return -EOPNOTSUPP;
1355 }
1356
1357 static s32
ptp_ocp_null_getmaxphase(struct ptp_clock_info * ptp_info)1358 ptp_ocp_null_getmaxphase(struct ptp_clock_info *ptp_info)
1359 {
1360 return 0;
1361 }
1362
1363 static int
ptp_ocp_null_adjphase(struct ptp_clock_info * ptp_info,s32 phase_ns)1364 ptp_ocp_null_adjphase(struct ptp_clock_info *ptp_info, s32 phase_ns)
1365 {
1366 return -EOPNOTSUPP;
1367 }
1368
1369 static int
ptp_ocp_enable(struct ptp_clock_info * ptp_info,struct ptp_clock_request * rq,int on)1370 ptp_ocp_enable(struct ptp_clock_info *ptp_info, struct ptp_clock_request *rq,
1371 int on)
1372 {
1373 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1374 struct ptp_ocp_ext_src *ext = NULL;
1375 u32 req;
1376 int err;
1377
1378 switch (rq->type) {
1379 case PTP_CLK_REQ_EXTTS:
1380 req = OCP_REQ_TIMESTAMP;
1381 switch (rq->extts.index) {
1382 case 0:
1383 ext = bp->ts0;
1384 break;
1385 case 1:
1386 ext = bp->ts1;
1387 break;
1388 case 2:
1389 ext = bp->ts2;
1390 break;
1391 case 3:
1392 ext = bp->ts3;
1393 break;
1394 case 4:
1395 ext = bp->ts4;
1396 break;
1397 case 5:
1398 ext = bp->pps;
1399 break;
1400 }
1401 break;
1402 case PTP_CLK_REQ_PPS:
1403 req = OCP_REQ_PPS;
1404 ext = bp->pps;
1405 break;
1406 case PTP_CLK_REQ_PEROUT:
1407 switch (rq->perout.index) {
1408 case 0:
1409 /* This is a request for 1PPS on an output SMA.
1410 * Allow, but assume manual configuration.
1411 */
1412 if (on && (rq->perout.period.sec != 1 ||
1413 rq->perout.period.nsec != 0))
1414 return -EINVAL;
1415 return 0;
1416 case 1:
1417 case 2:
1418 case 3:
1419 case 4:
1420 req = rq->perout.index - 1;
1421 ext = bp->signal_out[req];
1422 err = ptp_ocp_signal_from_perout(bp, req, &rq->perout);
1423 if (err)
1424 return err;
1425 break;
1426 }
1427 break;
1428 default:
1429 return -EOPNOTSUPP;
1430 }
1431
1432 err = -ENXIO;
1433 if (ext)
1434 err = ext->info->enable(ext, req, on);
1435
1436 return err;
1437 }
1438
1439 static int
ptp_ocp_verify(struct ptp_clock_info * ptp_info,unsigned pin,enum ptp_pin_function func,unsigned chan)1440 ptp_ocp_verify(struct ptp_clock_info *ptp_info, unsigned pin,
1441 enum ptp_pin_function func, unsigned chan)
1442 {
1443 struct ptp_ocp *bp = container_of(ptp_info, struct ptp_ocp, ptp_info);
1444 char buf[16];
1445
1446 switch (func) {
1447 case PTP_PF_NONE:
1448 snprintf(buf, sizeof(buf), "IN: None");
1449 break;
1450 case PTP_PF_EXTTS:
1451 /* Allow timestamps, but require sysfs configuration. */
1452 return 0;
1453 case PTP_PF_PEROUT:
1454 /* channel 0 is 1PPS from PHC.
1455 * channels 1..4 are the frequency generators.
1456 */
1457 if (chan)
1458 snprintf(buf, sizeof(buf), "OUT: GEN%d", chan);
1459 else
1460 snprintf(buf, sizeof(buf), "OUT: PHC");
1461 break;
1462 default:
1463 return -EOPNOTSUPP;
1464 }
1465
1466 return ptp_ocp_sma_store(bp, buf, pin + 1);
1467 }
1468
1469 static const struct ptp_clock_info ptp_ocp_clock_info = {
1470 .owner = THIS_MODULE,
1471 .name = KBUILD_MODNAME,
1472 .max_adj = 100000000,
1473 .gettimex64 = ptp_ocp_gettimex,
1474 .settime64 = ptp_ocp_settime,
1475 .adjtime = ptp_ocp_adjtime,
1476 .adjfine = ptp_ocp_null_adjfine,
1477 .adjphase = ptp_ocp_null_adjphase,
1478 .getmaxphase = ptp_ocp_null_getmaxphase,
1479 .enable = ptp_ocp_enable,
1480 .verify = ptp_ocp_verify,
1481 .pps = true,
1482 .n_ext_ts = 6,
1483 .n_per_out = 5,
1484 };
1485
1486 static void
__ptp_ocp_clear_drift_locked(struct ptp_ocp * bp)1487 __ptp_ocp_clear_drift_locked(struct ptp_ocp *bp)
1488 {
1489 u32 ctrl, select;
1490
1491 select = ioread32(&bp->reg->select);
1492 iowrite32(OCP_SELECT_CLK_REG, &bp->reg->select);
1493
1494 iowrite32(0, &bp->reg->drift_ns);
1495
1496 ctrl = OCP_CTRL_ADJUST_DRIFT | OCP_CTRL_ENABLE;
1497 iowrite32(ctrl, &bp->reg->ctrl);
1498
1499 /* restore clock selection */
1500 iowrite32(select >> 16, &bp->reg->select);
1501 }
1502
1503 static void
ptp_ocp_utc_distribute(struct ptp_ocp * bp,u32 val)1504 ptp_ocp_utc_distribute(struct ptp_ocp *bp, u32 val)
1505 {
1506 unsigned long flags;
1507
1508 spin_lock_irqsave(&bp->lock, flags);
1509
1510 bp->utc_tai_offset = val;
1511
1512 if (bp->irig_out)
1513 iowrite32(val, &bp->irig_out->adj_sec);
1514 if (bp->dcf_out)
1515 iowrite32(val, &bp->dcf_out->adj_sec);
1516 if (bp->nmea_out)
1517 iowrite32(val, &bp->nmea_out->adj_sec);
1518
1519 spin_unlock_irqrestore(&bp->lock, flags);
1520 }
1521
1522 static void
ptp_ocp_watchdog(struct timer_list * t)1523 ptp_ocp_watchdog(struct timer_list *t)
1524 {
1525 struct ptp_ocp *bp = from_timer(bp, t, watchdog);
1526 unsigned long flags;
1527 u32 status, utc_offset;
1528
1529 status = ioread32(&bp->pps_to_clk->status);
1530
1531 if (status & PPS_STATUS_SUPERV_ERR) {
1532 iowrite32(status, &bp->pps_to_clk->status);
1533 if (!bp->gnss_lost) {
1534 spin_lock_irqsave(&bp->lock, flags);
1535 __ptp_ocp_clear_drift_locked(bp);
1536 spin_unlock_irqrestore(&bp->lock, flags);
1537 bp->gnss_lost = ktime_get_real_seconds();
1538 }
1539
1540 } else if (bp->gnss_lost) {
1541 bp->gnss_lost = 0;
1542 }
1543
1544 /* if GNSS provides correct data we can rely on
1545 * it to get leap second information
1546 */
1547 if (bp->tod) {
1548 status = ioread32(&bp->tod->utc_status);
1549 utc_offset = status & TOD_STATUS_UTC_MASK;
1550 if (status & TOD_STATUS_UTC_VALID &&
1551 utc_offset != bp->utc_tai_offset)
1552 ptp_ocp_utc_distribute(bp, utc_offset);
1553 }
1554
1555 mod_timer(&bp->watchdog, jiffies + HZ);
1556 }
1557
1558 static void
ptp_ocp_estimate_pci_timing(struct ptp_ocp * bp)1559 ptp_ocp_estimate_pci_timing(struct ptp_ocp *bp)
1560 {
1561 ktime_t start, end, delay = U64_MAX;
1562 u32 ctrl;
1563 int i;
1564
1565 for (i = 0; i < 3; i++) {
1566 ctrl = ioread32(&bp->reg->ctrl);
1567 ctrl = OCP_CTRL_READ_TIME_REQ | OCP_CTRL_ENABLE;
1568
1569 iowrite32(ctrl, &bp->reg->ctrl);
1570
1571 start = ktime_get_raw_ns();
1572
1573 ctrl = ioread32(&bp->reg->ctrl);
1574
1575 end = ktime_get_raw_ns();
1576
1577 delay = min(delay, end - start);
1578 }
1579 bp->ts_window_adjust = (delay >> 5) * 3;
1580 }
1581
1582 static int
ptp_ocp_init_clock(struct ptp_ocp * bp,struct ptp_ocp_servo_conf * servo_conf)1583 ptp_ocp_init_clock(struct ptp_ocp *bp, struct ptp_ocp_servo_conf *servo_conf)
1584 {
1585 struct timespec64 ts;
1586 u32 ctrl;
1587
1588 ctrl = OCP_CTRL_ENABLE;
1589 iowrite32(ctrl, &bp->reg->ctrl);
1590
1591 /* servo configuration */
1592 iowrite32(servo_conf->servo_offset_p, &bp->reg->servo_offset_p);
1593 iowrite32(servo_conf->servo_offset_i, &bp->reg->servo_offset_i);
1594 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_p);
1595 iowrite32(servo_conf->servo_drift_p, &bp->reg->servo_drift_i);
1596
1597 /* latch servo values */
1598 ctrl |= OCP_CTRL_ADJUST_SERVO;
1599 iowrite32(ctrl, &bp->reg->ctrl);
1600
1601 if ((ioread32(&bp->reg->ctrl) & OCP_CTRL_ENABLE) == 0) {
1602 dev_err(&bp->pdev->dev, "clock not enabled\n");
1603 return -ENODEV;
1604 }
1605
1606 ptp_ocp_estimate_pci_timing(bp);
1607
1608 bp->sync = ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC;
1609 if (!bp->sync) {
1610 ktime_get_clocktai_ts64(&ts);
1611 ptp_ocp_settime(&bp->ptp_info, &ts);
1612 }
1613
1614 /* If there is a clock supervisor, then enable the watchdog */
1615 if (bp->pps_to_clk) {
1616 timer_setup(&bp->watchdog, ptp_ocp_watchdog, 0);
1617 mod_timer(&bp->watchdog, jiffies + HZ);
1618 }
1619
1620 return 0;
1621 }
1622
1623 static void
ptp_ocp_tod_init(struct ptp_ocp * bp)1624 ptp_ocp_tod_init(struct ptp_ocp *bp)
1625 {
1626 u32 ctrl, reg;
1627
1628 ctrl = ioread32(&bp->tod->ctrl);
1629 ctrl |= TOD_CTRL_PROTOCOL | TOD_CTRL_ENABLE;
1630 ctrl &= ~(TOD_CTRL_DISABLE_FMT_A | TOD_CTRL_DISABLE_FMT_B);
1631 iowrite32(ctrl, &bp->tod->ctrl);
1632
1633 reg = ioread32(&bp->tod->utc_status);
1634 if (reg & TOD_STATUS_UTC_VALID)
1635 ptp_ocp_utc_distribute(bp, reg & TOD_STATUS_UTC_MASK);
1636 }
1637
1638 static const char *
ptp_ocp_tod_proto_name(const int idx)1639 ptp_ocp_tod_proto_name(const int idx)
1640 {
1641 static const char * const proto_name[] = {
1642 "NMEA", "NMEA_ZDA", "NMEA_RMC", "NMEA_none",
1643 "UBX", "UBX_UTC", "UBX_LS", "UBX_none"
1644 };
1645 return proto_name[idx];
1646 }
1647
1648 static const char *
ptp_ocp_tod_gnss_name(int idx)1649 ptp_ocp_tod_gnss_name(int idx)
1650 {
1651 static const char * const gnss_name[] = {
1652 "ALL", "COMBINED", "GPS", "GLONASS", "GALILEO", "BEIDOU",
1653 "Unknown"
1654 };
1655 if (idx >= ARRAY_SIZE(gnss_name))
1656 idx = ARRAY_SIZE(gnss_name) - 1;
1657 return gnss_name[idx];
1658 }
1659
1660 static const char *
ptp_ocp_tty_port_name(int idx)1661 ptp_ocp_tty_port_name(int idx)
1662 {
1663 static const char * const tty_name[] = {
1664 "GNSS", "GNSS2", "MAC", "NMEA"
1665 };
1666 return tty_name[idx];
1667 }
1668
1669 struct ptp_ocp_nvmem_match_info {
1670 struct ptp_ocp *bp;
1671 const void * const tag;
1672 };
1673
1674 static int
ptp_ocp_nvmem_match(struct device * dev,const void * data)1675 ptp_ocp_nvmem_match(struct device *dev, const void *data)
1676 {
1677 const struct ptp_ocp_nvmem_match_info *info = data;
1678
1679 dev = dev->parent;
1680 if (!i2c_verify_client(dev) || info->tag != dev->platform_data)
1681 return 0;
1682
1683 while ((dev = dev->parent))
1684 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
1685 return info->bp == dev_get_drvdata(dev);
1686 return 0;
1687 }
1688
1689 static inline struct nvmem_device *
ptp_ocp_nvmem_device_get(struct ptp_ocp * bp,const void * const tag)1690 ptp_ocp_nvmem_device_get(struct ptp_ocp *bp, const void * const tag)
1691 {
1692 struct ptp_ocp_nvmem_match_info info = { .bp = bp, .tag = tag };
1693
1694 return nvmem_device_find(&info, ptp_ocp_nvmem_match);
1695 }
1696
1697 static inline void
ptp_ocp_nvmem_device_put(struct nvmem_device ** nvmemp)1698 ptp_ocp_nvmem_device_put(struct nvmem_device **nvmemp)
1699 {
1700 if (!IS_ERR_OR_NULL(*nvmemp))
1701 nvmem_device_put(*nvmemp);
1702 *nvmemp = NULL;
1703 }
1704
1705 static void
ptp_ocp_read_eeprom(struct ptp_ocp * bp)1706 ptp_ocp_read_eeprom(struct ptp_ocp *bp)
1707 {
1708 const struct ptp_ocp_eeprom_map *map;
1709 struct nvmem_device *nvmem;
1710 const void *tag;
1711 int ret;
1712
1713 if (!bp->i2c_ctrl)
1714 return;
1715
1716 tag = NULL;
1717 nvmem = NULL;
1718
1719 for (map = bp->eeprom_map; map->len; map++) {
1720 if (map->tag != tag) {
1721 tag = map->tag;
1722 ptp_ocp_nvmem_device_put(&nvmem);
1723 }
1724 if (!nvmem) {
1725 nvmem = ptp_ocp_nvmem_device_get(bp, tag);
1726 if (IS_ERR(nvmem)) {
1727 ret = PTR_ERR(nvmem);
1728 goto fail;
1729 }
1730 }
1731 ret = nvmem_device_read(nvmem, map->off, map->len,
1732 BP_MAP_ENTRY_ADDR(bp, map));
1733 if (ret != map->len)
1734 goto fail;
1735 }
1736
1737 bp->has_eeprom_data = true;
1738
1739 out:
1740 ptp_ocp_nvmem_device_put(&nvmem);
1741 return;
1742
1743 fail:
1744 dev_err(&bp->pdev->dev, "could not read eeprom: %d\n", ret);
1745 goto out;
1746 }
1747
1748 static struct device *
ptp_ocp_find_flash(struct ptp_ocp * bp)1749 ptp_ocp_find_flash(struct ptp_ocp *bp)
1750 {
1751 struct device *dev, *last;
1752
1753 last = NULL;
1754 dev = &bp->spi_flash->dev;
1755
1756 while ((dev = device_find_any_child(dev))) {
1757 if (!strcmp("mtd", dev_bus_name(dev)))
1758 break;
1759 put_device(last);
1760 last = dev;
1761 }
1762 put_device(last);
1763
1764 return dev;
1765 }
1766
1767 static int
ptp_ocp_devlink_fw_image(struct devlink * devlink,const struct firmware * fw,const u8 ** data,size_t * size)1768 ptp_ocp_devlink_fw_image(struct devlink *devlink, const struct firmware *fw,
1769 const u8 **data, size_t *size)
1770 {
1771 struct ptp_ocp *bp = devlink_priv(devlink);
1772 const struct ptp_ocp_firmware_header *hdr;
1773 size_t offset, length;
1774 u16 crc;
1775
1776 hdr = (const struct ptp_ocp_firmware_header *)fw->data;
1777 if (memcmp(hdr->magic, OCP_FIRMWARE_MAGIC_HEADER, 4)) {
1778 devlink_flash_update_status_notify(devlink,
1779 "No firmware header found, cancel firmware upgrade",
1780 NULL, 0, 0);
1781 return -EINVAL;
1782 }
1783
1784 if (be16_to_cpu(hdr->pci_vendor_id) != bp->pdev->vendor ||
1785 be16_to_cpu(hdr->pci_device_id) != bp->pdev->device) {
1786 devlink_flash_update_status_notify(devlink,
1787 "Firmware image compatibility check failed",
1788 NULL, 0, 0);
1789 return -EINVAL;
1790 }
1791
1792 offset = sizeof(*hdr);
1793 length = be32_to_cpu(hdr->image_size);
1794 if (length != (fw->size - offset)) {
1795 devlink_flash_update_status_notify(devlink,
1796 "Firmware image size check failed",
1797 NULL, 0, 0);
1798 return -EINVAL;
1799 }
1800
1801 crc = crc16(0xffff, &fw->data[offset], length);
1802 if (be16_to_cpu(hdr->crc) != crc) {
1803 devlink_flash_update_status_notify(devlink,
1804 "Firmware image CRC check failed",
1805 NULL, 0, 0);
1806 return -EINVAL;
1807 }
1808
1809 *data = &fw->data[offset];
1810 *size = length;
1811
1812 return 0;
1813 }
1814
1815 static int
ptp_ocp_devlink_flash(struct devlink * devlink,struct device * dev,const struct firmware * fw)1816 ptp_ocp_devlink_flash(struct devlink *devlink, struct device *dev,
1817 const struct firmware *fw)
1818 {
1819 struct mtd_info *mtd = dev_get_drvdata(dev);
1820 struct ptp_ocp *bp = devlink_priv(devlink);
1821 size_t off, len, size, resid, wrote;
1822 struct erase_info erase;
1823 size_t base, blksz;
1824 const u8 *data;
1825 int err;
1826
1827 err = ptp_ocp_devlink_fw_image(devlink, fw, &data, &size);
1828 if (err)
1829 goto out;
1830
1831 off = 0;
1832 base = bp->flash_start;
1833 blksz = 4096;
1834 resid = size;
1835
1836 while (resid) {
1837 devlink_flash_update_status_notify(devlink, "Flashing",
1838 NULL, off, size);
1839
1840 len = min_t(size_t, resid, blksz);
1841 erase.addr = base + off;
1842 erase.len = blksz;
1843
1844 err = mtd_erase(mtd, &erase);
1845 if (err)
1846 goto out;
1847
1848 err = mtd_write(mtd, base + off, len, &wrote, data + off);
1849 if (err)
1850 goto out;
1851
1852 off += blksz;
1853 resid -= len;
1854 }
1855 out:
1856 return err;
1857 }
1858
1859 static int
ptp_ocp_devlink_flash_update(struct devlink * devlink,struct devlink_flash_update_params * params,struct netlink_ext_ack * extack)1860 ptp_ocp_devlink_flash_update(struct devlink *devlink,
1861 struct devlink_flash_update_params *params,
1862 struct netlink_ext_ack *extack)
1863 {
1864 struct ptp_ocp *bp = devlink_priv(devlink);
1865 struct device *dev;
1866 const char *msg;
1867 int err;
1868
1869 dev = ptp_ocp_find_flash(bp);
1870 if (!dev) {
1871 dev_err(&bp->pdev->dev, "Can't find Flash SPI adapter\n");
1872 return -ENODEV;
1873 }
1874
1875 devlink_flash_update_status_notify(devlink, "Preparing to flash",
1876 NULL, 0, 0);
1877
1878 err = ptp_ocp_devlink_flash(devlink, dev, params->fw);
1879
1880 msg = err ? "Flash error" : "Flash complete";
1881 devlink_flash_update_status_notify(devlink, msg, NULL, 0, 0);
1882
1883 put_device(dev);
1884 return err;
1885 }
1886
1887 static int
ptp_ocp_devlink_info_get(struct devlink * devlink,struct devlink_info_req * req,struct netlink_ext_ack * extack)1888 ptp_ocp_devlink_info_get(struct devlink *devlink, struct devlink_info_req *req,
1889 struct netlink_ext_ack *extack)
1890 {
1891 struct ptp_ocp *bp = devlink_priv(devlink);
1892 const char *fw_image;
1893 char buf[32];
1894 int err;
1895
1896 fw_image = bp->fw_loader ? "loader" : "fw";
1897 sprintf(buf, "%d.%d", bp->fw_tag, bp->fw_version);
1898 err = devlink_info_version_running_put(req, fw_image, buf);
1899 if (err)
1900 return err;
1901
1902 if (!bp->has_eeprom_data) {
1903 ptp_ocp_read_eeprom(bp);
1904 if (!bp->has_eeprom_data)
1905 return 0;
1906 }
1907
1908 sprintf(buf, "%pM", bp->serial);
1909 err = devlink_info_serial_number_put(req, buf);
1910 if (err)
1911 return err;
1912
1913 err = devlink_info_version_fixed_put(req,
1914 DEVLINK_INFO_VERSION_GENERIC_BOARD_ID,
1915 bp->board_id);
1916 if (err)
1917 return err;
1918
1919 return 0;
1920 }
1921
1922 static const struct devlink_ops ptp_ocp_devlink_ops = {
1923 .flash_update = ptp_ocp_devlink_flash_update,
1924 .info_get = ptp_ocp_devlink_info_get,
1925 };
1926
1927 static void __iomem *
__ptp_ocp_get_mem(struct ptp_ocp * bp,resource_size_t start,int size)1928 __ptp_ocp_get_mem(struct ptp_ocp *bp, resource_size_t start, int size)
1929 {
1930 struct resource res = DEFINE_RES_MEM_NAMED(start, size, "ptp_ocp");
1931
1932 return devm_ioremap_resource(&bp->pdev->dev, &res);
1933 }
1934
1935 static void __iomem *
ptp_ocp_get_mem(struct ptp_ocp * bp,struct ocp_resource * r)1936 ptp_ocp_get_mem(struct ptp_ocp *bp, struct ocp_resource *r)
1937 {
1938 resource_size_t start;
1939
1940 start = pci_resource_start(bp->pdev, 0) + r->offset;
1941 return __ptp_ocp_get_mem(bp, start, r->size);
1942 }
1943
1944 static int
ptp_ocp_register_spi(struct ptp_ocp * bp,struct ocp_resource * r)1945 ptp_ocp_register_spi(struct ptp_ocp *bp, struct ocp_resource *r)
1946 {
1947 struct ptp_ocp_flash_info *info;
1948 struct pci_dev *pdev = bp->pdev;
1949 struct platform_device *p;
1950 struct resource res[2];
1951 resource_size_t start;
1952 int id;
1953
1954 start = pci_resource_start(pdev, 0) + r->offset;
1955 res[0] = DEFINE_RES_MEM(start, r->size);
1956 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
1957
1958 info = r->extra;
1959 id = pci_dev_id(pdev) << 1;
1960 id += info->pci_offset;
1961
1962 p = platform_device_register_resndata(&pdev->dev, info->name, id,
1963 res, ARRAY_SIZE(res), info->data,
1964 info->data_size);
1965 if (IS_ERR(p))
1966 return PTR_ERR(p);
1967
1968 bp_assign_entry(bp, r, p);
1969
1970 return 0;
1971 }
1972
1973 static struct platform_device *
ptp_ocp_i2c_bus(struct pci_dev * pdev,struct ocp_resource * r,int id)1974 ptp_ocp_i2c_bus(struct pci_dev *pdev, struct ocp_resource *r, int id)
1975 {
1976 struct ptp_ocp_i2c_info *info;
1977 struct resource res[2];
1978 resource_size_t start;
1979
1980 info = r->extra;
1981 start = pci_resource_start(pdev, 0) + r->offset;
1982 res[0] = DEFINE_RES_MEM(start, r->size);
1983 res[1] = DEFINE_RES_IRQ(pci_irq_vector(pdev, r->irq_vec));
1984
1985 return platform_device_register_resndata(&pdev->dev, info->name,
1986 id, res, ARRAY_SIZE(res),
1987 info->data, info->data_size);
1988 }
1989
1990 static int
ptp_ocp_register_i2c(struct ptp_ocp * bp,struct ocp_resource * r)1991 ptp_ocp_register_i2c(struct ptp_ocp *bp, struct ocp_resource *r)
1992 {
1993 struct pci_dev *pdev = bp->pdev;
1994 struct ptp_ocp_i2c_info *info;
1995 struct platform_device *p;
1996 struct clk_hw *clk;
1997 char buf[32];
1998 int id;
1999
2000 info = r->extra;
2001 id = pci_dev_id(bp->pdev);
2002
2003 sprintf(buf, "AXI.%d", id);
2004 clk = clk_hw_register_fixed_rate(&pdev->dev, buf, NULL, 0,
2005 info->fixed_rate);
2006 if (IS_ERR(clk))
2007 return PTR_ERR(clk);
2008 bp->i2c_clk = clk;
2009
2010 sprintf(buf, "%s.%d", info->name, id);
2011 devm_clk_hw_register_clkdev(&pdev->dev, clk, NULL, buf);
2012 p = ptp_ocp_i2c_bus(bp->pdev, r, id);
2013 if (IS_ERR(p))
2014 return PTR_ERR(p);
2015
2016 bp_assign_entry(bp, r, p);
2017
2018 return 0;
2019 }
2020
2021 /* The expectation is that this is triggered only on error. */
2022 static irqreturn_t
ptp_ocp_signal_irq(int irq,void * priv)2023 ptp_ocp_signal_irq(int irq, void *priv)
2024 {
2025 struct ptp_ocp_ext_src *ext = priv;
2026 struct signal_reg __iomem *reg = ext->mem;
2027 struct ptp_ocp *bp = ext->bp;
2028 u32 enable, status;
2029 int gen;
2030
2031 gen = ext->info->index - 1;
2032
2033 enable = ioread32(®->enable);
2034 status = ioread32(®->status);
2035
2036 /* disable generator on error */
2037 if (status || !enable) {
2038 iowrite32(0, ®->intr_mask);
2039 iowrite32(0, ®->enable);
2040 bp->signal[gen].running = false;
2041 }
2042
2043 iowrite32(0, ®->intr); /* ack interrupt */
2044
2045 return IRQ_HANDLED;
2046 }
2047
2048 static int
ptp_ocp_signal_set(struct ptp_ocp * bp,int gen,struct ptp_ocp_signal * s)2049 ptp_ocp_signal_set(struct ptp_ocp *bp, int gen, struct ptp_ocp_signal *s)
2050 {
2051 struct ptp_system_timestamp sts;
2052 struct timespec64 ts;
2053 ktime_t start_ns;
2054 int err;
2055
2056 if (!s->period)
2057 return 0;
2058
2059 if (!s->pulse)
2060 s->pulse = ktime_divns(s->period * s->duty, 100);
2061
2062 err = ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts);
2063 if (err)
2064 return err;
2065
2066 start_ns = ktime_set(ts.tv_sec, ts.tv_nsec) + NSEC_PER_MSEC;
2067 if (!s->start) {
2068 /* roundup() does not work on 32-bit systems */
2069 s->start = DIV64_U64_ROUND_UP(start_ns, s->period);
2070 s->start *= s->period;
2071 s->start = ktime_add(s->start, s->phase);
2072 }
2073
2074 if (s->duty < 1 || s->duty > 99)
2075 return -EINVAL;
2076
2077 if (s->pulse < 1 || s->pulse > s->period)
2078 return -EINVAL;
2079
2080 if (s->start < start_ns)
2081 return -EINVAL;
2082
2083 bp->signal[gen] = *s;
2084
2085 return 0;
2086 }
2087
2088 static int
ptp_ocp_signal_from_perout(struct ptp_ocp * bp,int gen,struct ptp_perout_request * req)2089 ptp_ocp_signal_from_perout(struct ptp_ocp *bp, int gen,
2090 struct ptp_perout_request *req)
2091 {
2092 struct ptp_ocp_signal s = { };
2093
2094 if (req->flags & ~(PTP_PEROUT_DUTY_CYCLE |
2095 PTP_PEROUT_PHASE))
2096 return -EOPNOTSUPP;
2097
2098 s.polarity = bp->signal[gen].polarity;
2099 s.period = ktime_set(req->period.sec, req->period.nsec);
2100 if (!s.period)
2101 return 0;
2102
2103 if (req->flags & PTP_PEROUT_DUTY_CYCLE) {
2104 s.pulse = ktime_set(req->on.sec, req->on.nsec);
2105 s.duty = ktime_divns(s.pulse * 100, s.period);
2106 }
2107
2108 if (req->flags & PTP_PEROUT_PHASE)
2109 s.phase = ktime_set(req->phase.sec, req->phase.nsec);
2110 else
2111 s.start = ktime_set(req->start.sec, req->start.nsec);
2112
2113 return ptp_ocp_signal_set(bp, gen, &s);
2114 }
2115
2116 static int
ptp_ocp_signal_enable(void * priv,u32 req,bool enable)2117 ptp_ocp_signal_enable(void *priv, u32 req, bool enable)
2118 {
2119 struct ptp_ocp_ext_src *ext = priv;
2120 struct signal_reg __iomem *reg = ext->mem;
2121 struct ptp_ocp *bp = ext->bp;
2122 struct timespec64 ts;
2123 int gen;
2124
2125 gen = ext->info->index - 1;
2126
2127 iowrite32(0, ®->intr_mask);
2128 iowrite32(0, ®->enable);
2129 bp->signal[gen].running = false;
2130 if (!enable)
2131 return 0;
2132
2133 ts = ktime_to_timespec64(bp->signal[gen].start);
2134 iowrite32(ts.tv_sec, ®->start_sec);
2135 iowrite32(ts.tv_nsec, ®->start_ns);
2136
2137 ts = ktime_to_timespec64(bp->signal[gen].period);
2138 iowrite32(ts.tv_sec, ®->period_sec);
2139 iowrite32(ts.tv_nsec, ®->period_ns);
2140
2141 ts = ktime_to_timespec64(bp->signal[gen].pulse);
2142 iowrite32(ts.tv_sec, ®->pulse_sec);
2143 iowrite32(ts.tv_nsec, ®->pulse_ns);
2144
2145 iowrite32(bp->signal[gen].polarity, ®->polarity);
2146 iowrite32(0, ®->repeat_count);
2147
2148 iowrite32(0, ®->intr); /* clear interrupt state */
2149 iowrite32(1, ®->intr_mask); /* enable interrupt */
2150 iowrite32(3, ®->enable); /* valid & enable */
2151
2152 bp->signal[gen].running = true;
2153
2154 return 0;
2155 }
2156
2157 static irqreturn_t
ptp_ocp_ts_irq(int irq,void * priv)2158 ptp_ocp_ts_irq(int irq, void *priv)
2159 {
2160 struct ptp_ocp_ext_src *ext = priv;
2161 struct ts_reg __iomem *reg = ext->mem;
2162 struct ptp_clock_event ev;
2163 u32 sec, nsec;
2164
2165 if (ext == ext->bp->pps) {
2166 if (ext->bp->pps_req_map & OCP_REQ_PPS) {
2167 ev.type = PTP_CLOCK_PPS;
2168 ptp_clock_event(ext->bp->ptp, &ev);
2169 }
2170
2171 if ((ext->bp->pps_req_map & ~OCP_REQ_PPS) == 0)
2172 goto out;
2173 }
2174
2175 /* XXX should fix API - this converts s/ns -> ts -> s/ns */
2176 sec = ioread32(®->time_sec);
2177 nsec = ioread32(®->time_ns);
2178
2179 ev.type = PTP_CLOCK_EXTTS;
2180 ev.index = ext->info->index;
2181 ev.timestamp = sec * NSEC_PER_SEC + nsec;
2182
2183 ptp_clock_event(ext->bp->ptp, &ev);
2184
2185 out:
2186 iowrite32(1, ®->intr); /* write 1 to ack */
2187
2188 return IRQ_HANDLED;
2189 }
2190
2191 static int
ptp_ocp_ts_enable(void * priv,u32 req,bool enable)2192 ptp_ocp_ts_enable(void *priv, u32 req, bool enable)
2193 {
2194 struct ptp_ocp_ext_src *ext = priv;
2195 struct ts_reg __iomem *reg = ext->mem;
2196 struct ptp_ocp *bp = ext->bp;
2197
2198 if (ext == bp->pps) {
2199 u32 old_map = bp->pps_req_map;
2200
2201 if (enable)
2202 bp->pps_req_map |= req;
2203 else
2204 bp->pps_req_map &= ~req;
2205
2206 /* if no state change, just return */
2207 if ((!!old_map ^ !!bp->pps_req_map) == 0)
2208 return 0;
2209 }
2210
2211 if (enable) {
2212 iowrite32(1, ®->enable);
2213 iowrite32(1, ®->intr_mask);
2214 iowrite32(1, ®->intr);
2215 } else {
2216 iowrite32(0, ®->intr_mask);
2217 iowrite32(0, ®->enable);
2218 }
2219
2220 return 0;
2221 }
2222
2223 static void
ptp_ocp_unregister_ext(struct ptp_ocp_ext_src * ext)2224 ptp_ocp_unregister_ext(struct ptp_ocp_ext_src *ext)
2225 {
2226 ext->info->enable(ext, ~0, false);
2227 pci_free_irq(ext->bp->pdev, ext->irq_vec, ext);
2228 kfree(ext);
2229 }
2230
2231 static int
ptp_ocp_register_ext(struct ptp_ocp * bp,struct ocp_resource * r)2232 ptp_ocp_register_ext(struct ptp_ocp *bp, struct ocp_resource *r)
2233 {
2234 struct pci_dev *pdev = bp->pdev;
2235 struct ptp_ocp_ext_src *ext;
2236 int err;
2237
2238 ext = kzalloc(sizeof(*ext), GFP_KERNEL);
2239 if (!ext)
2240 return -ENOMEM;
2241
2242 ext->mem = ptp_ocp_get_mem(bp, r);
2243 if (IS_ERR(ext->mem)) {
2244 err = PTR_ERR(ext->mem);
2245 goto out;
2246 }
2247
2248 ext->bp = bp;
2249 ext->info = r->extra;
2250 ext->irq_vec = r->irq_vec;
2251
2252 err = pci_request_irq(pdev, r->irq_vec, ext->info->irq_fcn, NULL,
2253 ext, "ocp%d.%s", bp->id, r->name);
2254 if (err) {
2255 dev_err(&pdev->dev, "Could not get irq %d\n", r->irq_vec);
2256 goto out;
2257 }
2258
2259 bp_assign_entry(bp, r, ext);
2260
2261 return 0;
2262
2263 out:
2264 kfree(ext);
2265 return err;
2266 }
2267
2268 static int
ptp_ocp_serial_line(struct ptp_ocp * bp,struct ocp_resource * r)2269 ptp_ocp_serial_line(struct ptp_ocp *bp, struct ocp_resource *r)
2270 {
2271 struct pci_dev *pdev = bp->pdev;
2272 struct uart_8250_port uart;
2273
2274 /* Setting UPF_IOREMAP and leaving port.membase unspecified lets
2275 * the serial port device claim and release the pci resource.
2276 */
2277 memset(&uart, 0, sizeof(uart));
2278 uart.port.dev = &pdev->dev;
2279 uart.port.iotype = UPIO_MEM;
2280 uart.port.regshift = 2;
2281 uart.port.mapbase = pci_resource_start(pdev, 0) + r->offset;
2282 uart.port.irq = pci_irq_vector(pdev, r->irq_vec);
2283 uart.port.uartclk = 50000000;
2284 uart.port.flags = UPF_FIXED_TYPE | UPF_IOREMAP | UPF_NO_THRE_TEST;
2285 uart.port.type = PORT_16550A;
2286
2287 return serial8250_register_8250_port(&uart);
2288 }
2289
2290 static int
ptp_ocp_register_serial(struct ptp_ocp * bp,struct ocp_resource * r)2291 ptp_ocp_register_serial(struct ptp_ocp *bp, struct ocp_resource *r)
2292 {
2293 struct ptp_ocp_serial_port *p = (struct ptp_ocp_serial_port *)r->extra;
2294 struct ptp_ocp_serial_port port = {};
2295
2296 port.line = ptp_ocp_serial_line(bp, r);
2297 if (port.line < 0)
2298 return port.line;
2299
2300 if (p)
2301 port.baud = p->baud;
2302
2303 bp_assign_entry(bp, r, port);
2304
2305 return 0;
2306 }
2307
2308 static int
ptp_ocp_register_mem(struct ptp_ocp * bp,struct ocp_resource * r)2309 ptp_ocp_register_mem(struct ptp_ocp *bp, struct ocp_resource *r)
2310 {
2311 void __iomem *mem;
2312
2313 mem = ptp_ocp_get_mem(bp, r);
2314 if (IS_ERR(mem))
2315 return PTR_ERR(mem);
2316
2317 bp_assign_entry(bp, r, mem);
2318
2319 return 0;
2320 }
2321
2322 static void
ptp_ocp_nmea_out_init(struct ptp_ocp * bp)2323 ptp_ocp_nmea_out_init(struct ptp_ocp *bp)
2324 {
2325 if (!bp->nmea_out)
2326 return;
2327
2328 iowrite32(0, &bp->nmea_out->ctrl); /* disable */
2329 iowrite32(7, &bp->nmea_out->uart_baud); /* 115200 */
2330 iowrite32(1, &bp->nmea_out->ctrl); /* enable */
2331 }
2332
2333 static void
_ptp_ocp_signal_init(struct ptp_ocp_signal * s,struct signal_reg __iomem * reg)2334 _ptp_ocp_signal_init(struct ptp_ocp_signal *s, struct signal_reg __iomem *reg)
2335 {
2336 u32 val;
2337
2338 iowrite32(0, ®->enable); /* disable */
2339
2340 val = ioread32(®->polarity);
2341 s->polarity = val ? true : false;
2342 s->duty = 50;
2343 }
2344
2345 static void
ptp_ocp_signal_init(struct ptp_ocp * bp)2346 ptp_ocp_signal_init(struct ptp_ocp *bp)
2347 {
2348 int i;
2349
2350 for (i = 0; i < 4; i++)
2351 if (bp->signal_out[i])
2352 _ptp_ocp_signal_init(&bp->signal[i],
2353 bp->signal_out[i]->mem);
2354 }
2355
2356 static void
ptp_ocp_attr_group_del(struct ptp_ocp * bp)2357 ptp_ocp_attr_group_del(struct ptp_ocp *bp)
2358 {
2359 sysfs_remove_groups(&bp->dev.kobj, bp->attr_group);
2360 kfree(bp->attr_group);
2361 }
2362
2363 static int
ptp_ocp_attr_group_add(struct ptp_ocp * bp,const struct ocp_attr_group * attr_tbl)2364 ptp_ocp_attr_group_add(struct ptp_ocp *bp,
2365 const struct ocp_attr_group *attr_tbl)
2366 {
2367 int count, i;
2368 int err;
2369
2370 count = 0;
2371 for (i = 0; attr_tbl[i].cap; i++)
2372 if (attr_tbl[i].cap & bp->fw_cap)
2373 count++;
2374
2375 bp->attr_group = kcalloc(count + 1, sizeof(struct attribute_group *),
2376 GFP_KERNEL);
2377 if (!bp->attr_group)
2378 return -ENOMEM;
2379
2380 count = 0;
2381 for (i = 0; attr_tbl[i].cap; i++)
2382 if (attr_tbl[i].cap & bp->fw_cap)
2383 bp->attr_group[count++] = attr_tbl[i].group;
2384
2385 err = sysfs_create_groups(&bp->dev.kobj, bp->attr_group);
2386 if (err)
2387 bp->attr_group[0] = NULL;
2388
2389 return err;
2390 }
2391
2392 static void
ptp_ocp_enable_fpga(u32 __iomem * reg,u32 bit,bool enable)2393 ptp_ocp_enable_fpga(u32 __iomem *reg, u32 bit, bool enable)
2394 {
2395 u32 ctrl;
2396 bool on;
2397
2398 ctrl = ioread32(reg);
2399 on = ctrl & bit;
2400 if (on ^ enable) {
2401 ctrl &= ~bit;
2402 ctrl |= enable ? bit : 0;
2403 iowrite32(ctrl, reg);
2404 }
2405 }
2406
2407 static void
ptp_ocp_irig_out(struct ptp_ocp * bp,bool enable)2408 ptp_ocp_irig_out(struct ptp_ocp *bp, bool enable)
2409 {
2410 return ptp_ocp_enable_fpga(&bp->irig_out->ctrl,
2411 IRIG_M_CTRL_ENABLE, enable);
2412 }
2413
2414 static void
ptp_ocp_irig_in(struct ptp_ocp * bp,bool enable)2415 ptp_ocp_irig_in(struct ptp_ocp *bp, bool enable)
2416 {
2417 return ptp_ocp_enable_fpga(&bp->irig_in->ctrl,
2418 IRIG_S_CTRL_ENABLE, enable);
2419 }
2420
2421 static void
ptp_ocp_dcf_out(struct ptp_ocp * bp,bool enable)2422 ptp_ocp_dcf_out(struct ptp_ocp *bp, bool enable)
2423 {
2424 return ptp_ocp_enable_fpga(&bp->dcf_out->ctrl,
2425 DCF_M_CTRL_ENABLE, enable);
2426 }
2427
2428 static void
ptp_ocp_dcf_in(struct ptp_ocp * bp,bool enable)2429 ptp_ocp_dcf_in(struct ptp_ocp *bp, bool enable)
2430 {
2431 return ptp_ocp_enable_fpga(&bp->dcf_in->ctrl,
2432 DCF_S_CTRL_ENABLE, enable);
2433 }
2434
2435 static void
__handle_signal_outputs(struct ptp_ocp * bp,u32 val)2436 __handle_signal_outputs(struct ptp_ocp *bp, u32 val)
2437 {
2438 ptp_ocp_irig_out(bp, val & 0x00100010);
2439 ptp_ocp_dcf_out(bp, val & 0x00200020);
2440 }
2441
2442 static void
__handle_signal_inputs(struct ptp_ocp * bp,u32 val)2443 __handle_signal_inputs(struct ptp_ocp *bp, u32 val)
2444 {
2445 ptp_ocp_irig_in(bp, val & 0x00100010);
2446 ptp_ocp_dcf_in(bp, val & 0x00200020);
2447 }
2448
2449 static u32
ptp_ocp_sma_fb_get(struct ptp_ocp * bp,int sma_nr)2450 ptp_ocp_sma_fb_get(struct ptp_ocp *bp, int sma_nr)
2451 {
2452 u32 __iomem *gpio;
2453 u32 shift;
2454
2455 if (bp->sma[sma_nr - 1].fixed_fcn)
2456 return (sma_nr - 1) & 1;
2457
2458 if (bp->sma[sma_nr - 1].mode == SMA_MODE_IN)
2459 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2460 else
2461 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2462 shift = sma_nr & 1 ? 0 : 16;
2463
2464 return (ioread32(gpio) >> shift) & 0xffff;
2465 }
2466
2467 static int
ptp_ocp_sma_fb_set_output(struct ptp_ocp * bp,int sma_nr,u32 val)2468 ptp_ocp_sma_fb_set_output(struct ptp_ocp *bp, int sma_nr, u32 val)
2469 {
2470 u32 reg, mask, shift;
2471 unsigned long flags;
2472 u32 __iomem *gpio;
2473
2474 gpio = sma_nr > 2 ? &bp->sma_map1->gpio2 : &bp->sma_map2->gpio2;
2475 shift = sma_nr & 1 ? 0 : 16;
2476
2477 mask = 0xffff << (16 - shift);
2478
2479 spin_lock_irqsave(&bp->lock, flags);
2480
2481 reg = ioread32(gpio);
2482 reg = (reg & mask) | (val << shift);
2483
2484 __handle_signal_outputs(bp, reg);
2485
2486 iowrite32(reg, gpio);
2487
2488 spin_unlock_irqrestore(&bp->lock, flags);
2489
2490 return 0;
2491 }
2492
2493 static int
ptp_ocp_sma_fb_set_inputs(struct ptp_ocp * bp,int sma_nr,u32 val)2494 ptp_ocp_sma_fb_set_inputs(struct ptp_ocp *bp, int sma_nr, u32 val)
2495 {
2496 u32 reg, mask, shift;
2497 unsigned long flags;
2498 u32 __iomem *gpio;
2499
2500 gpio = sma_nr > 2 ? &bp->sma_map2->gpio1 : &bp->sma_map1->gpio1;
2501 shift = sma_nr & 1 ? 0 : 16;
2502
2503 mask = 0xffff << (16 - shift);
2504
2505 spin_lock_irqsave(&bp->lock, flags);
2506
2507 reg = ioread32(gpio);
2508 reg = (reg & mask) | (val << shift);
2509
2510 __handle_signal_inputs(bp, reg);
2511
2512 iowrite32(reg, gpio);
2513
2514 spin_unlock_irqrestore(&bp->lock, flags);
2515
2516 return 0;
2517 }
2518
2519 static void
ptp_ocp_sma_fb_init(struct ptp_ocp * bp)2520 ptp_ocp_sma_fb_init(struct ptp_ocp *bp)
2521 {
2522 struct dpll_pin_properties prop = {
2523 .board_label = NULL,
2524 .type = DPLL_PIN_TYPE_EXT,
2525 .capabilities = DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE,
2526 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2527 .freq_supported = ptp_ocp_sma_freq,
2528
2529 };
2530 u32 reg;
2531 int i;
2532
2533 /* defaults */
2534 for (i = 0; i < OCP_SMA_NUM; i++) {
2535 bp->sma[i].default_fcn = i & 1;
2536 bp->sma[i].dpll_prop = prop;
2537 bp->sma[i].dpll_prop.board_label =
2538 bp->ptp_info.pin_config[i].name;
2539 }
2540 bp->sma[0].mode = SMA_MODE_IN;
2541 bp->sma[1].mode = SMA_MODE_IN;
2542 bp->sma[2].mode = SMA_MODE_OUT;
2543 bp->sma[3].mode = SMA_MODE_OUT;
2544 /* If no SMA1 map, the pin functions and directions are fixed. */
2545 if (!bp->sma_map1) {
2546 for (i = 0; i < OCP_SMA_NUM; i++) {
2547 bp->sma[i].fixed_fcn = true;
2548 bp->sma[i].fixed_dir = true;
2549 bp->sma[1].dpll_prop.capabilities &=
2550 ~DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2551 }
2552 return;
2553 }
2554
2555 /* If SMA2 GPIO output map is all 1, it is not present.
2556 * This indicates the firmware has fixed direction SMA pins.
2557 */
2558 reg = ioread32(&bp->sma_map2->gpio2);
2559 if (reg == 0xffffffff) {
2560 for (i = 0; i < OCP_SMA_NUM; i++)
2561 bp->sma[i].fixed_dir = true;
2562 } else {
2563 reg = ioread32(&bp->sma_map1->gpio1);
2564 bp->sma[0].mode = reg & BIT(15) ? SMA_MODE_IN : SMA_MODE_OUT;
2565 bp->sma[1].mode = reg & BIT(31) ? SMA_MODE_IN : SMA_MODE_OUT;
2566
2567 reg = ioread32(&bp->sma_map1->gpio2);
2568 bp->sma[2].mode = reg & BIT(15) ? SMA_MODE_OUT : SMA_MODE_IN;
2569 bp->sma[3].mode = reg & BIT(31) ? SMA_MODE_OUT : SMA_MODE_IN;
2570 }
2571 }
2572
2573 static const struct ocp_sma_op ocp_fb_sma_op = {
2574 .tbl = { ptp_ocp_sma_in, ptp_ocp_sma_out },
2575 .init = ptp_ocp_sma_fb_init,
2576 .get = ptp_ocp_sma_fb_get,
2577 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2578 .set_output = ptp_ocp_sma_fb_set_output,
2579 };
2580
2581 static const struct ocp_sma_op ocp_adva_sma_op = {
2582 .tbl = { ptp_ocp_adva_sma_in, ptp_ocp_adva_sma_out },
2583 .init = ptp_ocp_sma_fb_init,
2584 .get = ptp_ocp_sma_fb_get,
2585 .set_inputs = ptp_ocp_sma_fb_set_inputs,
2586 .set_output = ptp_ocp_sma_fb_set_output,
2587 };
2588
2589 static int
ptp_ocp_set_pins(struct ptp_ocp * bp)2590 ptp_ocp_set_pins(struct ptp_ocp *bp)
2591 {
2592 struct ptp_pin_desc *config;
2593 int i;
2594
2595 config = kcalloc(4, sizeof(*config), GFP_KERNEL);
2596 if (!config)
2597 return -ENOMEM;
2598
2599 for (i = 0; i < 4; i++) {
2600 sprintf(config[i].name, "sma%d", i + 1);
2601 config[i].index = i;
2602 }
2603
2604 bp->ptp_info.n_pins = 4;
2605 bp->ptp_info.pin_config = config;
2606
2607 return 0;
2608 }
2609
2610 static void
ptp_ocp_fb_set_version(struct ptp_ocp * bp)2611 ptp_ocp_fb_set_version(struct ptp_ocp *bp)
2612 {
2613 u64 cap = OCP_CAP_BASIC;
2614 u32 version;
2615
2616 version = ioread32(&bp->image->version);
2617
2618 /* if lower 16 bits are empty, this is the fw loader. */
2619 if ((version & 0xffff) == 0) {
2620 version = version >> 16;
2621 bp->fw_loader = true;
2622 }
2623
2624 bp->fw_tag = version >> 15;
2625 bp->fw_version = version & 0x7fff;
2626
2627 if (bp->fw_tag) {
2628 /* FPGA firmware */
2629 if (version >= 5)
2630 cap |= OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2631 } else {
2632 /* SOM firmware */
2633 if (version >= 19)
2634 cap |= OCP_CAP_SIGNAL;
2635 if (version >= 20)
2636 cap |= OCP_CAP_FREQ;
2637 }
2638
2639 bp->fw_cap = cap;
2640 }
2641
2642 /* FB specific board initializers; last "resource" registered. */
2643 static int
ptp_ocp_fb_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2644 ptp_ocp_fb_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2645 {
2646 int err;
2647
2648 bp->flash_start = 1024 * 4096;
2649 bp->eeprom_map = fb_eeprom_map;
2650 bp->fw_version = ioread32(&bp->image->version);
2651 bp->sma_op = &ocp_fb_sma_op;
2652
2653 ptp_ocp_fb_set_version(bp);
2654
2655 ptp_ocp_tod_init(bp);
2656 ptp_ocp_nmea_out_init(bp);
2657 ptp_ocp_signal_init(bp);
2658
2659 err = ptp_ocp_attr_group_add(bp, fb_timecard_groups);
2660 if (err)
2661 return err;
2662
2663 err = ptp_ocp_set_pins(bp);
2664 if (err)
2665 return err;
2666 ptp_ocp_sma_init(bp);
2667
2668 return ptp_ocp_init_clock(bp, r->extra);
2669 }
2670
2671 static bool
ptp_ocp_allow_irq(struct ptp_ocp * bp,struct ocp_resource * r)2672 ptp_ocp_allow_irq(struct ptp_ocp *bp, struct ocp_resource *r)
2673 {
2674 bool allow = !r->irq_vec || r->irq_vec < bp->n_irqs;
2675
2676 if (!allow)
2677 dev_err(&bp->pdev->dev, "irq %d out of range, skipping %s\n",
2678 r->irq_vec, r->name);
2679 return allow;
2680 }
2681
2682 static int
ptp_ocp_register_resources(struct ptp_ocp * bp,kernel_ulong_t driver_data)2683 ptp_ocp_register_resources(struct ptp_ocp *bp, kernel_ulong_t driver_data)
2684 {
2685 struct ocp_resource *r, *table;
2686 int err = 0;
2687
2688 table = (struct ocp_resource *)driver_data;
2689 for (r = table; r->setup; r++) {
2690 if (!ptp_ocp_allow_irq(bp, r))
2691 continue;
2692 err = r->setup(bp, r);
2693 if (err) {
2694 dev_err(&bp->pdev->dev,
2695 "Could not register %s: err %d\n",
2696 r->name, err);
2697 break;
2698 }
2699 }
2700 return err;
2701 }
2702
2703 static void
ptp_ocp_art_sma_init(struct ptp_ocp * bp)2704 ptp_ocp_art_sma_init(struct ptp_ocp *bp)
2705 {
2706 struct dpll_pin_properties prop = {
2707 .board_label = NULL,
2708 .type = DPLL_PIN_TYPE_EXT,
2709 .capabilities = 0,
2710 .freq_supported_num = ARRAY_SIZE(ptp_ocp_sma_freq),
2711 .freq_supported = ptp_ocp_sma_freq,
2712
2713 };
2714 u32 reg;
2715 int i;
2716
2717 /* defaults */
2718 bp->sma[0].mode = SMA_MODE_IN;
2719 bp->sma[1].mode = SMA_MODE_IN;
2720 bp->sma[2].mode = SMA_MODE_OUT;
2721 bp->sma[3].mode = SMA_MODE_OUT;
2722
2723 bp->sma[0].default_fcn = 0x08; /* IN: 10Mhz */
2724 bp->sma[1].default_fcn = 0x01; /* IN: PPS1 */
2725 bp->sma[2].default_fcn = 0x10; /* OUT: 10Mhz */
2726 bp->sma[3].default_fcn = 0x02; /* OUT: PHC */
2727
2728 for (i = 0; i < OCP_SMA_NUM; i++) {
2729 /* If no SMA map, the pin functions and directions are fixed. */
2730 bp->sma[i].dpll_prop = prop;
2731 bp->sma[i].dpll_prop.board_label =
2732 bp->ptp_info.pin_config[i].name;
2733 if (!bp->art_sma) {
2734 bp->sma[i].fixed_fcn = true;
2735 bp->sma[i].fixed_dir = true;
2736 continue;
2737 }
2738 reg = ioread32(&bp->art_sma->map[i].gpio);
2739
2740 switch (reg & 0xff) {
2741 case 0:
2742 bp->sma[i].fixed_fcn = true;
2743 bp->sma[i].fixed_dir = true;
2744 break;
2745 case 1:
2746 case 8:
2747 bp->sma[i].mode = SMA_MODE_IN;
2748 bp->sma[i].dpll_prop.capabilities =
2749 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2750 break;
2751 default:
2752 bp->sma[i].mode = SMA_MODE_OUT;
2753 bp->sma[i].dpll_prop.capabilities =
2754 DPLL_PIN_CAPABILITIES_DIRECTION_CAN_CHANGE;
2755 break;
2756 }
2757 }
2758 }
2759
2760 static u32
ptp_ocp_art_sma_get(struct ptp_ocp * bp,int sma_nr)2761 ptp_ocp_art_sma_get(struct ptp_ocp *bp, int sma_nr)
2762 {
2763 if (bp->sma[sma_nr - 1].fixed_fcn)
2764 return bp->sma[sma_nr - 1].default_fcn;
2765
2766 return ioread32(&bp->art_sma->map[sma_nr - 1].gpio) & 0xff;
2767 }
2768
2769 /* note: store 0 is considered invalid. */
2770 static int
ptp_ocp_art_sma_set(struct ptp_ocp * bp,int sma_nr,u32 val)2771 ptp_ocp_art_sma_set(struct ptp_ocp *bp, int sma_nr, u32 val)
2772 {
2773 unsigned long flags;
2774 u32 __iomem *gpio;
2775 int err = 0;
2776 u32 reg;
2777
2778 val &= SMA_SELECT_MASK;
2779 if (hweight32(val) > 1)
2780 return -EINVAL;
2781
2782 gpio = &bp->art_sma->map[sma_nr - 1].gpio;
2783
2784 spin_lock_irqsave(&bp->lock, flags);
2785 reg = ioread32(gpio);
2786 if (((reg >> 16) & val) == 0) {
2787 err = -EOPNOTSUPP;
2788 } else {
2789 reg = (reg & 0xff00) | (val & 0xff);
2790 iowrite32(reg, gpio);
2791 }
2792 spin_unlock_irqrestore(&bp->lock, flags);
2793
2794 return err;
2795 }
2796
2797 static const struct ocp_sma_op ocp_art_sma_op = {
2798 .tbl = { ptp_ocp_art_sma_in, ptp_ocp_art_sma_out },
2799 .init = ptp_ocp_art_sma_init,
2800 .get = ptp_ocp_art_sma_get,
2801 .set_inputs = ptp_ocp_art_sma_set,
2802 .set_output = ptp_ocp_art_sma_set,
2803 };
2804
2805 /* ART specific board initializers; last "resource" registered. */
2806 static int
ptp_ocp_art_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2807 ptp_ocp_art_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2808 {
2809 int err;
2810
2811 bp->flash_start = 0x1000000;
2812 bp->eeprom_map = art_eeprom_map;
2813 bp->fw_cap = OCP_CAP_BASIC;
2814 bp->fw_version = ioread32(&bp->reg->version);
2815 bp->fw_tag = 2;
2816 bp->sma_op = &ocp_art_sma_op;
2817
2818 /* Enable MAC serial port during initialisation */
2819 iowrite32(1, &bp->board_config->mro50_serial_activate);
2820
2821 err = ptp_ocp_set_pins(bp);
2822 if (err)
2823 return err;
2824 ptp_ocp_sma_init(bp);
2825
2826 err = ptp_ocp_attr_group_add(bp, art_timecard_groups);
2827 if (err)
2828 return err;
2829
2830 return ptp_ocp_init_clock(bp, r->extra);
2831 }
2832
2833 /* ADVA specific board initializers; last "resource" registered. */
2834 static int
ptp_ocp_adva_board_init(struct ptp_ocp * bp,struct ocp_resource * r)2835 ptp_ocp_adva_board_init(struct ptp_ocp *bp, struct ocp_resource *r)
2836 {
2837 int err;
2838 u32 version;
2839
2840 bp->flash_start = 0xA00000;
2841 bp->eeprom_map = fb_eeprom_map;
2842 bp->sma_op = &ocp_adva_sma_op;
2843
2844 version = ioread32(&bp->image->version);
2845 /* if lower 16 bits are empty, this is the fw loader. */
2846 if ((version & 0xffff) == 0) {
2847 version = version >> 16;
2848 bp->fw_loader = true;
2849 }
2850 bp->fw_tag = 3;
2851 bp->fw_version = version & 0xffff;
2852 bp->fw_cap = OCP_CAP_BASIC | OCP_CAP_SIGNAL | OCP_CAP_FREQ;
2853
2854 ptp_ocp_tod_init(bp);
2855 ptp_ocp_nmea_out_init(bp);
2856 ptp_ocp_signal_init(bp);
2857
2858 err = ptp_ocp_attr_group_add(bp, adva_timecard_groups);
2859 if (err)
2860 return err;
2861
2862 err = ptp_ocp_set_pins(bp);
2863 if (err)
2864 return err;
2865 ptp_ocp_sma_init(bp);
2866
2867 return ptp_ocp_init_clock(bp, r->extra);
2868 }
2869
2870 static ssize_t
ptp_ocp_show_output(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)2871 ptp_ocp_show_output(const struct ocp_selector *tbl, u32 val, char *buf,
2872 int def_val)
2873 {
2874 const char *name;
2875 ssize_t count;
2876
2877 count = sysfs_emit(buf, "OUT: ");
2878 name = ptp_ocp_select_name_from_val(tbl, val);
2879 if (!name)
2880 name = ptp_ocp_select_name_from_val(tbl, def_val);
2881 count += sysfs_emit_at(buf, count, "%s\n", name);
2882 return count;
2883 }
2884
2885 static ssize_t
ptp_ocp_show_inputs(const struct ocp_selector * tbl,u32 val,char * buf,int def_val)2886 ptp_ocp_show_inputs(const struct ocp_selector *tbl, u32 val, char *buf,
2887 int def_val)
2888 {
2889 const char *name;
2890 ssize_t count;
2891 int i;
2892
2893 count = sysfs_emit(buf, "IN: ");
2894 for (i = 0; tbl[i].name; i++) {
2895 if (val & tbl[i].value) {
2896 name = tbl[i].name;
2897 count += sysfs_emit_at(buf, count, "%s ", name);
2898 }
2899 }
2900 if (!val && def_val >= 0) {
2901 name = ptp_ocp_select_name_from_val(tbl, def_val);
2902 count += sysfs_emit_at(buf, count, "%s ", name);
2903 }
2904 if (count)
2905 count--;
2906 count += sysfs_emit_at(buf, count, "\n");
2907 return count;
2908 }
2909
2910 static int
sma_parse_inputs(const struct ocp_selector * const tbl[],const char * buf,enum ptp_ocp_sma_mode * mode)2911 sma_parse_inputs(const struct ocp_selector * const tbl[], const char *buf,
2912 enum ptp_ocp_sma_mode *mode)
2913 {
2914 int idx, count, dir;
2915 char **argv;
2916 int ret;
2917
2918 argv = argv_split(GFP_KERNEL, buf, &count);
2919 if (!argv)
2920 return -ENOMEM;
2921
2922 ret = -EINVAL;
2923 if (!count)
2924 goto out;
2925
2926 idx = 0;
2927 dir = *mode == SMA_MODE_IN ? 0 : 1;
2928 if (!strcasecmp("IN:", argv[0])) {
2929 dir = 0;
2930 idx++;
2931 }
2932 if (!strcasecmp("OUT:", argv[0])) {
2933 dir = 1;
2934 idx++;
2935 }
2936 *mode = dir == 0 ? SMA_MODE_IN : SMA_MODE_OUT;
2937
2938 ret = 0;
2939 for (; idx < count; idx++)
2940 ret |= ptp_ocp_select_val_from_name(tbl[dir], argv[idx]);
2941 if (ret < 0)
2942 ret = -EINVAL;
2943
2944 out:
2945 argv_free(argv);
2946 return ret;
2947 }
2948
2949 static ssize_t
ptp_ocp_sma_show(struct ptp_ocp * bp,int sma_nr,char * buf,int default_in_val,int default_out_val)2950 ptp_ocp_sma_show(struct ptp_ocp *bp, int sma_nr, char *buf,
2951 int default_in_val, int default_out_val)
2952 {
2953 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
2954 const struct ocp_selector * const *tbl;
2955 u32 val;
2956
2957 tbl = bp->sma_op->tbl;
2958 val = ptp_ocp_sma_get(bp, sma_nr) & SMA_SELECT_MASK;
2959
2960 if (sma->mode == SMA_MODE_IN) {
2961 if (sma->disabled)
2962 val = SMA_DISABLE;
2963 return ptp_ocp_show_inputs(tbl[0], val, buf, default_in_val);
2964 }
2965
2966 return ptp_ocp_show_output(tbl[1], val, buf, default_out_val);
2967 }
2968
2969 static ssize_t
sma1_show(struct device * dev,struct device_attribute * attr,char * buf)2970 sma1_show(struct device *dev, struct device_attribute *attr, char *buf)
2971 {
2972 struct ptp_ocp *bp = dev_get_drvdata(dev);
2973
2974 return ptp_ocp_sma_show(bp, 1, buf, 0, 1);
2975 }
2976
2977 static ssize_t
sma2_show(struct device * dev,struct device_attribute * attr,char * buf)2978 sma2_show(struct device *dev, struct device_attribute *attr, char *buf)
2979 {
2980 struct ptp_ocp *bp = dev_get_drvdata(dev);
2981
2982 return ptp_ocp_sma_show(bp, 2, buf, -1, 1);
2983 }
2984
2985 static ssize_t
sma3_show(struct device * dev,struct device_attribute * attr,char * buf)2986 sma3_show(struct device *dev, struct device_attribute *attr, char *buf)
2987 {
2988 struct ptp_ocp *bp = dev_get_drvdata(dev);
2989
2990 return ptp_ocp_sma_show(bp, 3, buf, -1, 0);
2991 }
2992
2993 static ssize_t
sma4_show(struct device * dev,struct device_attribute * attr,char * buf)2994 sma4_show(struct device *dev, struct device_attribute *attr, char *buf)
2995 {
2996 struct ptp_ocp *bp = dev_get_drvdata(dev);
2997
2998 return ptp_ocp_sma_show(bp, 4, buf, -1, 1);
2999 }
3000
3001 static int
ptp_ocp_sma_store_val(struct ptp_ocp * bp,int val,enum ptp_ocp_sma_mode mode,int sma_nr)3002 ptp_ocp_sma_store_val(struct ptp_ocp *bp, int val, enum ptp_ocp_sma_mode mode, int sma_nr)
3003 {
3004 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3005
3006 if (sma->fixed_dir && (mode != sma->mode || val & SMA_DISABLE))
3007 return -EOPNOTSUPP;
3008
3009 if (sma->fixed_fcn) {
3010 if (val != sma->default_fcn)
3011 return -EOPNOTSUPP;
3012 return 0;
3013 }
3014
3015 sma->disabled = !!(val & SMA_DISABLE);
3016
3017 if (mode != sma->mode) {
3018 if (mode == SMA_MODE_IN)
3019 ptp_ocp_sma_set_output(bp, sma_nr, 0);
3020 else
3021 ptp_ocp_sma_set_inputs(bp, sma_nr, 0);
3022 sma->mode = mode;
3023 }
3024
3025 if (!sma->fixed_dir)
3026 val |= SMA_ENABLE; /* add enable bit */
3027
3028 if (sma->disabled)
3029 val = 0;
3030
3031 if (mode == SMA_MODE_IN)
3032 val = ptp_ocp_sma_set_inputs(bp, sma_nr, val);
3033 else
3034 val = ptp_ocp_sma_set_output(bp, sma_nr, val);
3035
3036 return val;
3037 }
3038
3039 static int
ptp_ocp_sma_store(struct ptp_ocp * bp,const char * buf,int sma_nr)3040 ptp_ocp_sma_store(struct ptp_ocp *bp, const char *buf, int sma_nr)
3041 {
3042 struct ptp_ocp_sma_connector *sma = &bp->sma[sma_nr - 1];
3043 enum ptp_ocp_sma_mode mode;
3044 int val;
3045
3046 mode = sma->mode;
3047 val = sma_parse_inputs(bp->sma_op->tbl, buf, &mode);
3048 if (val < 0)
3049 return val;
3050 return ptp_ocp_sma_store_val(bp, val, mode, sma_nr);
3051 }
3052
3053 static ssize_t
sma1_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3054 sma1_store(struct device *dev, struct device_attribute *attr,
3055 const char *buf, size_t count)
3056 {
3057 struct ptp_ocp *bp = dev_get_drvdata(dev);
3058 int err;
3059
3060 err = ptp_ocp_sma_store(bp, buf, 1);
3061 return err ? err : count;
3062 }
3063
3064 static ssize_t
sma2_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3065 sma2_store(struct device *dev, struct device_attribute *attr,
3066 const char *buf, size_t count)
3067 {
3068 struct ptp_ocp *bp = dev_get_drvdata(dev);
3069 int err;
3070
3071 err = ptp_ocp_sma_store(bp, buf, 2);
3072 return err ? err : count;
3073 }
3074
3075 static ssize_t
sma3_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3076 sma3_store(struct device *dev, struct device_attribute *attr,
3077 const char *buf, size_t count)
3078 {
3079 struct ptp_ocp *bp = dev_get_drvdata(dev);
3080 int err;
3081
3082 err = ptp_ocp_sma_store(bp, buf, 3);
3083 return err ? err : count;
3084 }
3085
3086 static ssize_t
sma4_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3087 sma4_store(struct device *dev, struct device_attribute *attr,
3088 const char *buf, size_t count)
3089 {
3090 struct ptp_ocp *bp = dev_get_drvdata(dev);
3091 int err;
3092
3093 err = ptp_ocp_sma_store(bp, buf, 4);
3094 return err ? err : count;
3095 }
3096 static DEVICE_ATTR_RW(sma1);
3097 static DEVICE_ATTR_RW(sma2);
3098 static DEVICE_ATTR_RW(sma3);
3099 static DEVICE_ATTR_RW(sma4);
3100
3101 static ssize_t
available_sma_inputs_show(struct device * dev,struct device_attribute * attr,char * buf)3102 available_sma_inputs_show(struct device *dev,
3103 struct device_attribute *attr, char *buf)
3104 {
3105 struct ptp_ocp *bp = dev_get_drvdata(dev);
3106
3107 return ptp_ocp_select_table_show(bp->sma_op->tbl[0], buf);
3108 }
3109 static DEVICE_ATTR_RO(available_sma_inputs);
3110
3111 static ssize_t
available_sma_outputs_show(struct device * dev,struct device_attribute * attr,char * buf)3112 available_sma_outputs_show(struct device *dev,
3113 struct device_attribute *attr, char *buf)
3114 {
3115 struct ptp_ocp *bp = dev_get_drvdata(dev);
3116
3117 return ptp_ocp_select_table_show(bp->sma_op->tbl[1], buf);
3118 }
3119 static DEVICE_ATTR_RO(available_sma_outputs);
3120
3121 #define EXT_ATTR_RO(_group, _name, _val) \
3122 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3123 { __ATTR_RO(_name), (void *)_val }
3124 #define EXT_ATTR_RW(_group, _name, _val) \
3125 struct dev_ext_attribute dev_attr_##_group##_val##_##_name = \
3126 { __ATTR_RW(_name), (void *)_val }
3127 #define to_ext_attr(x) container_of(x, struct dev_ext_attribute, attr)
3128
3129 /* period [duty [phase [polarity]]] */
3130 static ssize_t
signal_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3131 signal_store(struct device *dev, struct device_attribute *attr,
3132 const char *buf, size_t count)
3133 {
3134 struct dev_ext_attribute *ea = to_ext_attr(attr);
3135 struct ptp_ocp *bp = dev_get_drvdata(dev);
3136 struct ptp_ocp_signal s = { };
3137 int gen = (uintptr_t)ea->var;
3138 int argc, err;
3139 char **argv;
3140
3141 argv = argv_split(GFP_KERNEL, buf, &argc);
3142 if (!argv)
3143 return -ENOMEM;
3144
3145 err = -EINVAL;
3146 s.duty = bp->signal[gen].duty;
3147 s.phase = bp->signal[gen].phase;
3148 s.period = bp->signal[gen].period;
3149 s.polarity = bp->signal[gen].polarity;
3150
3151 switch (argc) {
3152 case 4:
3153 argc--;
3154 err = kstrtobool(argv[argc], &s.polarity);
3155 if (err)
3156 goto out;
3157 fallthrough;
3158 case 3:
3159 argc--;
3160 err = kstrtou64(argv[argc], 0, &s.phase);
3161 if (err)
3162 goto out;
3163 fallthrough;
3164 case 2:
3165 argc--;
3166 err = kstrtoint(argv[argc], 0, &s.duty);
3167 if (err)
3168 goto out;
3169 fallthrough;
3170 case 1:
3171 argc--;
3172 err = kstrtou64(argv[argc], 0, &s.period);
3173 if (err)
3174 goto out;
3175 break;
3176 default:
3177 goto out;
3178 }
3179
3180 err = ptp_ocp_signal_set(bp, gen, &s);
3181 if (err)
3182 goto out;
3183
3184 err = ptp_ocp_signal_enable(bp->signal_out[gen], gen, s.period != 0);
3185
3186 out:
3187 argv_free(argv);
3188 return err ? err : count;
3189 }
3190
3191 static ssize_t
signal_show(struct device * dev,struct device_attribute * attr,char * buf)3192 signal_show(struct device *dev, struct device_attribute *attr, char *buf)
3193 {
3194 struct dev_ext_attribute *ea = to_ext_attr(attr);
3195 struct ptp_ocp *bp = dev_get_drvdata(dev);
3196 struct ptp_ocp_signal *signal;
3197 struct timespec64 ts;
3198 ssize_t count;
3199 int i;
3200
3201 i = (uintptr_t)ea->var;
3202 signal = &bp->signal[i];
3203
3204 count = sysfs_emit(buf, "%llu %d %llu %d", signal->period,
3205 signal->duty, signal->phase, signal->polarity);
3206
3207 ts = ktime_to_timespec64(signal->start);
3208 count += sysfs_emit_at(buf, count, " %ptT TAI\n", &ts);
3209
3210 return count;
3211 }
3212 static EXT_ATTR_RW(signal, signal, 0);
3213 static EXT_ATTR_RW(signal, signal, 1);
3214 static EXT_ATTR_RW(signal, signal, 2);
3215 static EXT_ATTR_RW(signal, signal, 3);
3216
3217 static ssize_t
duty_show(struct device * dev,struct device_attribute * attr,char * buf)3218 duty_show(struct device *dev, struct device_attribute *attr, char *buf)
3219 {
3220 struct dev_ext_attribute *ea = to_ext_attr(attr);
3221 struct ptp_ocp *bp = dev_get_drvdata(dev);
3222 int i = (uintptr_t)ea->var;
3223
3224 return sysfs_emit(buf, "%d\n", bp->signal[i].duty);
3225 }
3226 static EXT_ATTR_RO(signal, duty, 0);
3227 static EXT_ATTR_RO(signal, duty, 1);
3228 static EXT_ATTR_RO(signal, duty, 2);
3229 static EXT_ATTR_RO(signal, duty, 3);
3230
3231 static ssize_t
period_show(struct device * dev,struct device_attribute * attr,char * buf)3232 period_show(struct device *dev, struct device_attribute *attr, char *buf)
3233 {
3234 struct dev_ext_attribute *ea = to_ext_attr(attr);
3235 struct ptp_ocp *bp = dev_get_drvdata(dev);
3236 int i = (uintptr_t)ea->var;
3237
3238 return sysfs_emit(buf, "%llu\n", bp->signal[i].period);
3239 }
3240 static EXT_ATTR_RO(signal, period, 0);
3241 static EXT_ATTR_RO(signal, period, 1);
3242 static EXT_ATTR_RO(signal, period, 2);
3243 static EXT_ATTR_RO(signal, period, 3);
3244
3245 static ssize_t
phase_show(struct device * dev,struct device_attribute * attr,char * buf)3246 phase_show(struct device *dev, struct device_attribute *attr, char *buf)
3247 {
3248 struct dev_ext_attribute *ea = to_ext_attr(attr);
3249 struct ptp_ocp *bp = dev_get_drvdata(dev);
3250 int i = (uintptr_t)ea->var;
3251
3252 return sysfs_emit(buf, "%llu\n", bp->signal[i].phase);
3253 }
3254 static EXT_ATTR_RO(signal, phase, 0);
3255 static EXT_ATTR_RO(signal, phase, 1);
3256 static EXT_ATTR_RO(signal, phase, 2);
3257 static EXT_ATTR_RO(signal, phase, 3);
3258
3259 static ssize_t
polarity_show(struct device * dev,struct device_attribute * attr,char * buf)3260 polarity_show(struct device *dev, struct device_attribute *attr,
3261 char *buf)
3262 {
3263 struct dev_ext_attribute *ea = to_ext_attr(attr);
3264 struct ptp_ocp *bp = dev_get_drvdata(dev);
3265 int i = (uintptr_t)ea->var;
3266
3267 return sysfs_emit(buf, "%d\n", bp->signal[i].polarity);
3268 }
3269 static EXT_ATTR_RO(signal, polarity, 0);
3270 static EXT_ATTR_RO(signal, polarity, 1);
3271 static EXT_ATTR_RO(signal, polarity, 2);
3272 static EXT_ATTR_RO(signal, polarity, 3);
3273
3274 static ssize_t
running_show(struct device * dev,struct device_attribute * attr,char * buf)3275 running_show(struct device *dev, struct device_attribute *attr, char *buf)
3276 {
3277 struct dev_ext_attribute *ea = to_ext_attr(attr);
3278 struct ptp_ocp *bp = dev_get_drvdata(dev);
3279 int i = (uintptr_t)ea->var;
3280
3281 return sysfs_emit(buf, "%d\n", bp->signal[i].running);
3282 }
3283 static EXT_ATTR_RO(signal, running, 0);
3284 static EXT_ATTR_RO(signal, running, 1);
3285 static EXT_ATTR_RO(signal, running, 2);
3286 static EXT_ATTR_RO(signal, running, 3);
3287
3288 static ssize_t
start_show(struct device * dev,struct device_attribute * attr,char * buf)3289 start_show(struct device *dev, struct device_attribute *attr, char *buf)
3290 {
3291 struct dev_ext_attribute *ea = to_ext_attr(attr);
3292 struct ptp_ocp *bp = dev_get_drvdata(dev);
3293 int i = (uintptr_t)ea->var;
3294 struct timespec64 ts;
3295
3296 ts = ktime_to_timespec64(bp->signal[i].start);
3297 return sysfs_emit(buf, "%llu.%lu\n", ts.tv_sec, ts.tv_nsec);
3298 }
3299 static EXT_ATTR_RO(signal, start, 0);
3300 static EXT_ATTR_RO(signal, start, 1);
3301 static EXT_ATTR_RO(signal, start, 2);
3302 static EXT_ATTR_RO(signal, start, 3);
3303
3304 static ssize_t
seconds_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3305 seconds_store(struct device *dev, struct device_attribute *attr,
3306 const char *buf, size_t count)
3307 {
3308 struct dev_ext_attribute *ea = to_ext_attr(attr);
3309 struct ptp_ocp *bp = dev_get_drvdata(dev);
3310 int idx = (uintptr_t)ea->var;
3311 u32 val;
3312 int err;
3313
3314 err = kstrtou32(buf, 0, &val);
3315 if (err)
3316 return err;
3317 if (val > 0xff)
3318 return -EINVAL;
3319
3320 if (val)
3321 val = (val << 8) | 0x1;
3322
3323 iowrite32(val, &bp->freq_in[idx]->ctrl);
3324
3325 return count;
3326 }
3327
3328 static ssize_t
seconds_show(struct device * dev,struct device_attribute * attr,char * buf)3329 seconds_show(struct device *dev, struct device_attribute *attr, char *buf)
3330 {
3331 struct dev_ext_attribute *ea = to_ext_attr(attr);
3332 struct ptp_ocp *bp = dev_get_drvdata(dev);
3333 int idx = (uintptr_t)ea->var;
3334 u32 val;
3335
3336 val = ioread32(&bp->freq_in[idx]->ctrl);
3337 if (val & 1)
3338 val = (val >> 8) & 0xff;
3339 else
3340 val = 0;
3341
3342 return sysfs_emit(buf, "%u\n", val);
3343 }
3344 static EXT_ATTR_RW(freq, seconds, 0);
3345 static EXT_ATTR_RW(freq, seconds, 1);
3346 static EXT_ATTR_RW(freq, seconds, 2);
3347 static EXT_ATTR_RW(freq, seconds, 3);
3348
3349 static ssize_t
frequency_show(struct device * dev,struct device_attribute * attr,char * buf)3350 frequency_show(struct device *dev, struct device_attribute *attr, char *buf)
3351 {
3352 struct dev_ext_attribute *ea = to_ext_attr(attr);
3353 struct ptp_ocp *bp = dev_get_drvdata(dev);
3354 int idx = (uintptr_t)ea->var;
3355 u32 val;
3356
3357 val = ioread32(&bp->freq_in[idx]->status);
3358 if (val & FREQ_STATUS_ERROR)
3359 return sysfs_emit(buf, "error\n");
3360 if (val & FREQ_STATUS_OVERRUN)
3361 return sysfs_emit(buf, "overrun\n");
3362 if (val & FREQ_STATUS_VALID)
3363 return sysfs_emit(buf, "%lu\n", val & FREQ_STATUS_MASK);
3364 return 0;
3365 }
3366 static EXT_ATTR_RO(freq, frequency, 0);
3367 static EXT_ATTR_RO(freq, frequency, 1);
3368 static EXT_ATTR_RO(freq, frequency, 2);
3369 static EXT_ATTR_RO(freq, frequency, 3);
3370
3371 static ssize_t
ptp_ocp_tty_show(struct device * dev,struct device_attribute * attr,char * buf)3372 ptp_ocp_tty_show(struct device *dev, struct device_attribute *attr, char *buf)
3373 {
3374 struct dev_ext_attribute *ea = to_ext_attr(attr);
3375 struct ptp_ocp *bp = dev_get_drvdata(dev);
3376
3377 return sysfs_emit(buf, "ttyS%d", bp->port[(uintptr_t)ea->var].line);
3378 }
3379
3380 static umode_t
ptp_ocp_timecard_tty_is_visible(struct kobject * kobj,struct attribute * attr,int n)3381 ptp_ocp_timecard_tty_is_visible(struct kobject *kobj, struct attribute *attr, int n)
3382 {
3383 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3384 struct ptp_ocp_serial_port *port;
3385 struct device_attribute *dattr;
3386 struct dev_ext_attribute *ea;
3387
3388 if (strncmp(attr->name, "tty", 3))
3389 return attr->mode;
3390
3391 dattr = container_of(attr, struct device_attribute, attr);
3392 ea = container_of(dattr, struct dev_ext_attribute, attr);
3393 port = &bp->port[(uintptr_t)ea->var];
3394 return port->line == -1 ? 0 : 0444;
3395 }
3396
3397 #define EXT_TTY_ATTR_RO(_name, _val) \
3398 struct dev_ext_attribute dev_attr_tty##_name = \
3399 { __ATTR(tty##_name, 0444, ptp_ocp_tty_show, NULL), (void *)_val }
3400
3401 static EXT_TTY_ATTR_RO(GNSS, PORT_GNSS);
3402 static EXT_TTY_ATTR_RO(GNSS2, PORT_GNSS2);
3403 static EXT_TTY_ATTR_RO(MAC, PORT_MAC);
3404 static EXT_TTY_ATTR_RO(NMEA, PORT_NMEA);
3405 static struct attribute *ptp_ocp_timecard_tty_attrs[] = {
3406 &dev_attr_ttyGNSS.attr.attr,
3407 &dev_attr_ttyGNSS2.attr.attr,
3408 &dev_attr_ttyMAC.attr.attr,
3409 &dev_attr_ttyNMEA.attr.attr,
3410 NULL,
3411 };
3412
3413 static const struct attribute_group ptp_ocp_timecard_tty_group = {
3414 .name = "tty",
3415 .attrs = ptp_ocp_timecard_tty_attrs,
3416 .is_visible = ptp_ocp_timecard_tty_is_visible,
3417 };
3418
3419 static ssize_t
serialnum_show(struct device * dev,struct device_attribute * attr,char * buf)3420 serialnum_show(struct device *dev, struct device_attribute *attr, char *buf)
3421 {
3422 struct ptp_ocp *bp = dev_get_drvdata(dev);
3423
3424 if (!bp->has_eeprom_data)
3425 ptp_ocp_read_eeprom(bp);
3426
3427 return sysfs_emit(buf, "%pM\n", bp->serial);
3428 }
3429 static DEVICE_ATTR_RO(serialnum);
3430
3431 static ssize_t
gnss_sync_show(struct device * dev,struct device_attribute * attr,char * buf)3432 gnss_sync_show(struct device *dev, struct device_attribute *attr, char *buf)
3433 {
3434 struct ptp_ocp *bp = dev_get_drvdata(dev);
3435 ssize_t ret;
3436
3437 if (bp->gnss_lost)
3438 ret = sysfs_emit(buf, "LOST @ %ptT\n", &bp->gnss_lost);
3439 else
3440 ret = sysfs_emit(buf, "SYNC\n");
3441
3442 return ret;
3443 }
3444 static DEVICE_ATTR_RO(gnss_sync);
3445
3446 static ssize_t
utc_tai_offset_show(struct device * dev,struct device_attribute * attr,char * buf)3447 utc_tai_offset_show(struct device *dev,
3448 struct device_attribute *attr, char *buf)
3449 {
3450 struct ptp_ocp *bp = dev_get_drvdata(dev);
3451
3452 return sysfs_emit(buf, "%d\n", bp->utc_tai_offset);
3453 }
3454
3455 static ssize_t
utc_tai_offset_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3456 utc_tai_offset_store(struct device *dev,
3457 struct device_attribute *attr,
3458 const char *buf, size_t count)
3459 {
3460 struct ptp_ocp *bp = dev_get_drvdata(dev);
3461 int err;
3462 u32 val;
3463
3464 err = kstrtou32(buf, 0, &val);
3465 if (err)
3466 return err;
3467
3468 ptp_ocp_utc_distribute(bp, val);
3469
3470 return count;
3471 }
3472 static DEVICE_ATTR_RW(utc_tai_offset);
3473
3474 static ssize_t
ts_window_adjust_show(struct device * dev,struct device_attribute * attr,char * buf)3475 ts_window_adjust_show(struct device *dev,
3476 struct device_attribute *attr, char *buf)
3477 {
3478 struct ptp_ocp *bp = dev_get_drvdata(dev);
3479
3480 return sysfs_emit(buf, "%d\n", bp->ts_window_adjust);
3481 }
3482
3483 static ssize_t
ts_window_adjust_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3484 ts_window_adjust_store(struct device *dev,
3485 struct device_attribute *attr,
3486 const char *buf, size_t count)
3487 {
3488 struct ptp_ocp *bp = dev_get_drvdata(dev);
3489 int err;
3490 u32 val;
3491
3492 err = kstrtou32(buf, 0, &val);
3493 if (err)
3494 return err;
3495
3496 bp->ts_window_adjust = val;
3497
3498 return count;
3499 }
3500 static DEVICE_ATTR_RW(ts_window_adjust);
3501
3502 static ssize_t
irig_b_mode_show(struct device * dev,struct device_attribute * attr,char * buf)3503 irig_b_mode_show(struct device *dev, struct device_attribute *attr, char *buf)
3504 {
3505 struct ptp_ocp *bp = dev_get_drvdata(dev);
3506 u32 val;
3507
3508 val = ioread32(&bp->irig_out->ctrl);
3509 val = (val >> 16) & 0x07;
3510 return sysfs_emit(buf, "%d\n", val);
3511 }
3512
3513 static ssize_t
irig_b_mode_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3514 irig_b_mode_store(struct device *dev,
3515 struct device_attribute *attr,
3516 const char *buf, size_t count)
3517 {
3518 struct ptp_ocp *bp = dev_get_drvdata(dev);
3519 unsigned long flags;
3520 int err;
3521 u32 reg;
3522 u8 val;
3523
3524 err = kstrtou8(buf, 0, &val);
3525 if (err)
3526 return err;
3527 if (val > 7)
3528 return -EINVAL;
3529
3530 reg = ((val & 0x7) << 16);
3531
3532 spin_lock_irqsave(&bp->lock, flags);
3533 iowrite32(0, &bp->irig_out->ctrl); /* disable */
3534 iowrite32(reg, &bp->irig_out->ctrl); /* change mode */
3535 iowrite32(reg | IRIG_M_CTRL_ENABLE, &bp->irig_out->ctrl);
3536 spin_unlock_irqrestore(&bp->lock, flags);
3537
3538 return count;
3539 }
3540 static DEVICE_ATTR_RW(irig_b_mode);
3541
3542 static ssize_t
clock_source_show(struct device * dev,struct device_attribute * attr,char * buf)3543 clock_source_show(struct device *dev, struct device_attribute *attr, char *buf)
3544 {
3545 struct ptp_ocp *bp = dev_get_drvdata(dev);
3546 const char *p;
3547 u32 select;
3548
3549 select = ioread32(&bp->reg->select);
3550 p = ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16);
3551
3552 return sysfs_emit(buf, "%s\n", p);
3553 }
3554
3555 static ssize_t
clock_source_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3556 clock_source_store(struct device *dev, struct device_attribute *attr,
3557 const char *buf, size_t count)
3558 {
3559 struct ptp_ocp *bp = dev_get_drvdata(dev);
3560 unsigned long flags;
3561 int val;
3562
3563 val = ptp_ocp_select_val_from_name(ptp_ocp_clock, buf);
3564 if (val < 0)
3565 return val;
3566
3567 spin_lock_irqsave(&bp->lock, flags);
3568 iowrite32(val, &bp->reg->select);
3569 spin_unlock_irqrestore(&bp->lock, flags);
3570
3571 return count;
3572 }
3573 static DEVICE_ATTR_RW(clock_source);
3574
3575 static ssize_t
available_clock_sources_show(struct device * dev,struct device_attribute * attr,char * buf)3576 available_clock_sources_show(struct device *dev,
3577 struct device_attribute *attr, char *buf)
3578 {
3579 return ptp_ocp_select_table_show(ptp_ocp_clock, buf);
3580 }
3581 static DEVICE_ATTR_RO(available_clock_sources);
3582
3583 static ssize_t
clock_status_drift_show(struct device * dev,struct device_attribute * attr,char * buf)3584 clock_status_drift_show(struct device *dev,
3585 struct device_attribute *attr, char *buf)
3586 {
3587 struct ptp_ocp *bp = dev_get_drvdata(dev);
3588 u32 val;
3589 int res;
3590
3591 val = ioread32(&bp->reg->status_drift);
3592 res = (val & ~INT_MAX) ? -1 : 1;
3593 res *= (val & INT_MAX);
3594 return sysfs_emit(buf, "%d\n", res);
3595 }
3596 static DEVICE_ATTR_RO(clock_status_drift);
3597
3598 static ssize_t
clock_status_offset_show(struct device * dev,struct device_attribute * attr,char * buf)3599 clock_status_offset_show(struct device *dev,
3600 struct device_attribute *attr, char *buf)
3601 {
3602 struct ptp_ocp *bp = dev_get_drvdata(dev);
3603 u32 val;
3604 int res;
3605
3606 val = ioread32(&bp->reg->status_offset);
3607 res = (val & ~INT_MAX) ? -1 : 1;
3608 res *= (val & INT_MAX);
3609 return sysfs_emit(buf, "%d\n", res);
3610 }
3611 static DEVICE_ATTR_RO(clock_status_offset);
3612
3613 static ssize_t
tod_correction_show(struct device * dev,struct device_attribute * attr,char * buf)3614 tod_correction_show(struct device *dev,
3615 struct device_attribute *attr, char *buf)
3616 {
3617 struct ptp_ocp *bp = dev_get_drvdata(dev);
3618 u32 val;
3619 int res;
3620
3621 val = ioread32(&bp->tod->adj_sec);
3622 res = (val & ~INT_MAX) ? -1 : 1;
3623 res *= (val & INT_MAX);
3624 return sysfs_emit(buf, "%d\n", res);
3625 }
3626
3627 static ssize_t
tod_correction_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)3628 tod_correction_store(struct device *dev, struct device_attribute *attr,
3629 const char *buf, size_t count)
3630 {
3631 struct ptp_ocp *bp = dev_get_drvdata(dev);
3632 unsigned long flags;
3633 int err, res;
3634 u32 val = 0;
3635
3636 err = kstrtos32(buf, 0, &res);
3637 if (err)
3638 return err;
3639 if (res < 0) {
3640 res *= -1;
3641 val |= BIT(31);
3642 }
3643 val |= res;
3644
3645 spin_lock_irqsave(&bp->lock, flags);
3646 iowrite32(val, &bp->tod->adj_sec);
3647 spin_unlock_irqrestore(&bp->lock, flags);
3648
3649 return count;
3650 }
3651 static DEVICE_ATTR_RW(tod_correction);
3652
3653 #define _DEVICE_SIGNAL_GROUP_ATTRS(_nr) \
3654 static struct attribute *fb_timecard_signal##_nr##_attrs[] = { \
3655 &dev_attr_signal##_nr##_signal.attr.attr, \
3656 &dev_attr_signal##_nr##_duty.attr.attr, \
3657 &dev_attr_signal##_nr##_phase.attr.attr, \
3658 &dev_attr_signal##_nr##_period.attr.attr, \
3659 &dev_attr_signal##_nr##_polarity.attr.attr, \
3660 &dev_attr_signal##_nr##_running.attr.attr, \
3661 &dev_attr_signal##_nr##_start.attr.attr, \
3662 NULL, \
3663 }
3664
3665 #define DEVICE_SIGNAL_GROUP(_name, _nr) \
3666 _DEVICE_SIGNAL_GROUP_ATTRS(_nr); \
3667 static const struct attribute_group \
3668 fb_timecard_signal##_nr##_group = { \
3669 .name = #_name, \
3670 .attrs = fb_timecard_signal##_nr##_attrs, \
3671 }
3672
3673 DEVICE_SIGNAL_GROUP(gen1, 0);
3674 DEVICE_SIGNAL_GROUP(gen2, 1);
3675 DEVICE_SIGNAL_GROUP(gen3, 2);
3676 DEVICE_SIGNAL_GROUP(gen4, 3);
3677
3678 #define _DEVICE_FREQ_GROUP_ATTRS(_nr) \
3679 static struct attribute *fb_timecard_freq##_nr##_attrs[] = { \
3680 &dev_attr_freq##_nr##_seconds.attr.attr, \
3681 &dev_attr_freq##_nr##_frequency.attr.attr, \
3682 NULL, \
3683 }
3684
3685 #define DEVICE_FREQ_GROUP(_name, _nr) \
3686 _DEVICE_FREQ_GROUP_ATTRS(_nr); \
3687 static const struct attribute_group \
3688 fb_timecard_freq##_nr##_group = { \
3689 .name = #_name, \
3690 .attrs = fb_timecard_freq##_nr##_attrs, \
3691 }
3692
3693 DEVICE_FREQ_GROUP(freq1, 0);
3694 DEVICE_FREQ_GROUP(freq2, 1);
3695 DEVICE_FREQ_GROUP(freq3, 2);
3696 DEVICE_FREQ_GROUP(freq4, 3);
3697
3698 static ssize_t
disciplining_config_read(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3699 disciplining_config_read(struct file *filp, struct kobject *kobj,
3700 const struct bin_attribute *bin_attr, char *buf,
3701 loff_t off, size_t count)
3702 {
3703 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3704 size_t size = OCP_ART_CONFIG_SIZE;
3705 struct nvmem_device *nvmem;
3706 ssize_t err;
3707
3708 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3709 if (IS_ERR(nvmem))
3710 return PTR_ERR(nvmem);
3711
3712 if (off > size) {
3713 err = 0;
3714 goto out;
3715 }
3716
3717 if (off + count > size)
3718 count = size - off;
3719
3720 // the configuration is in the very beginning of the EEPROM
3721 err = nvmem_device_read(nvmem, off, count, buf);
3722 if (err != count) {
3723 err = -EFAULT;
3724 goto out;
3725 }
3726
3727 out:
3728 ptp_ocp_nvmem_device_put(&nvmem);
3729
3730 return err;
3731 }
3732
3733 static ssize_t
disciplining_config_write(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3734 disciplining_config_write(struct file *filp, struct kobject *kobj,
3735 const struct bin_attribute *bin_attr, char *buf,
3736 loff_t off, size_t count)
3737 {
3738 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3739 struct nvmem_device *nvmem;
3740 ssize_t err;
3741
3742 /* Allow write of the whole area only */
3743 if (off || count != OCP_ART_CONFIG_SIZE)
3744 return -EFAULT;
3745
3746 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3747 if (IS_ERR(nvmem))
3748 return PTR_ERR(nvmem);
3749
3750 err = nvmem_device_write(nvmem, 0x00, count, buf);
3751 if (err != count)
3752 err = -EFAULT;
3753
3754 ptp_ocp_nvmem_device_put(&nvmem);
3755
3756 return err;
3757 }
3758 static const BIN_ATTR_RW(disciplining_config, OCP_ART_CONFIG_SIZE);
3759
3760 static ssize_t
temperature_table_read(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3761 temperature_table_read(struct file *filp, struct kobject *kobj,
3762 const struct bin_attribute *bin_attr, char *buf,
3763 loff_t off, size_t count)
3764 {
3765 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3766 size_t size = OCP_ART_TEMP_TABLE_SIZE;
3767 struct nvmem_device *nvmem;
3768 ssize_t err;
3769
3770 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3771 if (IS_ERR(nvmem))
3772 return PTR_ERR(nvmem);
3773
3774 if (off > size) {
3775 err = 0;
3776 goto out;
3777 }
3778
3779 if (off + count > size)
3780 count = size - off;
3781
3782 // the configuration is in the very beginning of the EEPROM
3783 err = nvmem_device_read(nvmem, 0x90 + off, count, buf);
3784 if (err != count) {
3785 err = -EFAULT;
3786 goto out;
3787 }
3788
3789 out:
3790 ptp_ocp_nvmem_device_put(&nvmem);
3791
3792 return err;
3793 }
3794
3795 static ssize_t
temperature_table_write(struct file * filp,struct kobject * kobj,const struct bin_attribute * bin_attr,char * buf,loff_t off,size_t count)3796 temperature_table_write(struct file *filp, struct kobject *kobj,
3797 const struct bin_attribute *bin_attr, char *buf,
3798 loff_t off, size_t count)
3799 {
3800 struct ptp_ocp *bp = dev_get_drvdata(kobj_to_dev(kobj));
3801 struct nvmem_device *nvmem;
3802 ssize_t err;
3803
3804 /* Allow write of the whole area only */
3805 if (off || count != OCP_ART_TEMP_TABLE_SIZE)
3806 return -EFAULT;
3807
3808 nvmem = ptp_ocp_nvmem_device_get(bp, NULL);
3809 if (IS_ERR(nvmem))
3810 return PTR_ERR(nvmem);
3811
3812 err = nvmem_device_write(nvmem, 0x90, count, buf);
3813 if (err != count)
3814 err = -EFAULT;
3815
3816 ptp_ocp_nvmem_device_put(&nvmem);
3817
3818 return err;
3819 }
3820 static const BIN_ATTR_RW(temperature_table, OCP_ART_TEMP_TABLE_SIZE);
3821
3822 static struct attribute *fb_timecard_attrs[] = {
3823 &dev_attr_serialnum.attr,
3824 &dev_attr_gnss_sync.attr,
3825 &dev_attr_clock_source.attr,
3826 &dev_attr_available_clock_sources.attr,
3827 &dev_attr_sma1.attr,
3828 &dev_attr_sma2.attr,
3829 &dev_attr_sma3.attr,
3830 &dev_attr_sma4.attr,
3831 &dev_attr_available_sma_inputs.attr,
3832 &dev_attr_available_sma_outputs.attr,
3833 &dev_attr_clock_status_drift.attr,
3834 &dev_attr_clock_status_offset.attr,
3835 &dev_attr_irig_b_mode.attr,
3836 &dev_attr_utc_tai_offset.attr,
3837 &dev_attr_ts_window_adjust.attr,
3838 &dev_attr_tod_correction.attr,
3839 NULL,
3840 };
3841
3842 static const struct attribute_group fb_timecard_group = {
3843 .attrs = fb_timecard_attrs,
3844 };
3845
3846 static const struct ocp_attr_group fb_timecard_groups[] = {
3847 { .cap = OCP_CAP_BASIC, .group = &fb_timecard_group },
3848 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3849 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3850 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3851 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal2_group },
3852 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal3_group },
3853 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3854 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3855 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq2_group },
3856 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq3_group },
3857 { },
3858 };
3859
3860 static struct attribute *art_timecard_attrs[] = {
3861 &dev_attr_serialnum.attr,
3862 &dev_attr_clock_source.attr,
3863 &dev_attr_available_clock_sources.attr,
3864 &dev_attr_utc_tai_offset.attr,
3865 &dev_attr_ts_window_adjust.attr,
3866 &dev_attr_sma1.attr,
3867 &dev_attr_sma2.attr,
3868 &dev_attr_sma3.attr,
3869 &dev_attr_sma4.attr,
3870 &dev_attr_available_sma_inputs.attr,
3871 &dev_attr_available_sma_outputs.attr,
3872 NULL,
3873 };
3874
3875 static const struct bin_attribute *const bin_art_timecard_attrs[] = {
3876 &bin_attr_disciplining_config,
3877 &bin_attr_temperature_table,
3878 NULL,
3879 };
3880
3881 static const struct attribute_group art_timecard_group = {
3882 .attrs = art_timecard_attrs,
3883 .bin_attrs_new = bin_art_timecard_attrs,
3884 };
3885
3886 static const struct ocp_attr_group art_timecard_groups[] = {
3887 { .cap = OCP_CAP_BASIC, .group = &art_timecard_group },
3888 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3889 { },
3890 };
3891
3892 static struct attribute *adva_timecard_attrs[] = {
3893 &dev_attr_serialnum.attr,
3894 &dev_attr_gnss_sync.attr,
3895 &dev_attr_clock_source.attr,
3896 &dev_attr_available_clock_sources.attr,
3897 &dev_attr_sma1.attr,
3898 &dev_attr_sma2.attr,
3899 &dev_attr_sma3.attr,
3900 &dev_attr_sma4.attr,
3901 &dev_attr_available_sma_inputs.attr,
3902 &dev_attr_available_sma_outputs.attr,
3903 &dev_attr_clock_status_drift.attr,
3904 &dev_attr_clock_status_offset.attr,
3905 &dev_attr_ts_window_adjust.attr,
3906 &dev_attr_tod_correction.attr,
3907 NULL,
3908 };
3909
3910 static const struct attribute_group adva_timecard_group = {
3911 .attrs = adva_timecard_attrs,
3912 };
3913
3914 static const struct ocp_attr_group adva_timecard_groups[] = {
3915 { .cap = OCP_CAP_BASIC, .group = &adva_timecard_group },
3916 { .cap = OCP_CAP_BASIC, .group = &ptp_ocp_timecard_tty_group },
3917 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal0_group },
3918 { .cap = OCP_CAP_SIGNAL, .group = &fb_timecard_signal1_group },
3919 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq0_group },
3920 { .cap = OCP_CAP_FREQ, .group = &fb_timecard_freq1_group },
3921 { },
3922 };
3923
3924 static void
gpio_input_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit,const char * def)3925 gpio_input_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit,
3926 const char *def)
3927 {
3928 int i;
3929
3930 for (i = 0; i < 4; i++) {
3931 if (bp->sma[i].mode != SMA_MODE_IN)
3932 continue;
3933 if (map[i][0] & (1 << bit)) {
3934 sprintf(buf, "sma%d", i + 1);
3935 return;
3936 }
3937 }
3938 if (!def)
3939 def = "----";
3940 strcpy(buf, def);
3941 }
3942
3943 static void
gpio_output_map(char * buf,struct ptp_ocp * bp,u16 map[][2],u16 bit)3944 gpio_output_map(char *buf, struct ptp_ocp *bp, u16 map[][2], u16 bit)
3945 {
3946 char *ans = buf;
3947 int i;
3948
3949 strcpy(ans, "----");
3950 for (i = 0; i < 4; i++) {
3951 if (bp->sma[i].mode != SMA_MODE_OUT)
3952 continue;
3953 if (map[i][1] & (1 << bit))
3954 ans += sprintf(ans, "sma%d ", i + 1);
3955 }
3956 }
3957
3958 static void
_signal_summary_show(struct seq_file * s,struct ptp_ocp * bp,int nr)3959 _signal_summary_show(struct seq_file *s, struct ptp_ocp *bp, int nr)
3960 {
3961 struct signal_reg __iomem *reg = bp->signal_out[nr]->mem;
3962 struct ptp_ocp_signal *signal = &bp->signal[nr];
3963 char label[8];
3964 bool on;
3965 u32 val;
3966
3967 on = signal->running;
3968 sprintf(label, "GEN%d", nr + 1);
3969 seq_printf(s, "%7s: %s, period:%llu duty:%d%% phase:%llu pol:%d",
3970 label, on ? " ON" : "OFF",
3971 signal->period, signal->duty, signal->phase,
3972 signal->polarity);
3973
3974 val = ioread32(®->enable);
3975 seq_printf(s, " [%x", val);
3976 val = ioread32(®->status);
3977 seq_printf(s, " %x]", val);
3978
3979 seq_printf(s, " start:%llu\n", signal->start);
3980 }
3981
3982 static void
_frequency_summary_show(struct seq_file * s,int nr,struct frequency_reg __iomem * reg)3983 _frequency_summary_show(struct seq_file *s, int nr,
3984 struct frequency_reg __iomem *reg)
3985 {
3986 char label[8];
3987 bool on;
3988 u32 val;
3989
3990 if (!reg)
3991 return;
3992
3993 sprintf(label, "FREQ%d", nr + 1);
3994 val = ioread32(®->ctrl);
3995 on = val & 1;
3996 val = (val >> 8) & 0xff;
3997 seq_printf(s, "%7s: %s, sec:%u",
3998 label,
3999 on ? " ON" : "OFF",
4000 val);
4001
4002 val = ioread32(®->status);
4003 if (val & FREQ_STATUS_ERROR)
4004 seq_printf(s, ", error");
4005 if (val & FREQ_STATUS_OVERRUN)
4006 seq_printf(s, ", overrun");
4007 if (val & FREQ_STATUS_VALID)
4008 seq_printf(s, ", freq %lu Hz", val & FREQ_STATUS_MASK);
4009 seq_printf(s, " reg:%x\n", val);
4010 }
4011
4012 static int
ptp_ocp_summary_show(struct seq_file * s,void * data)4013 ptp_ocp_summary_show(struct seq_file *s, void *data)
4014 {
4015 struct device *dev = s->private;
4016 struct ptp_system_timestamp sts;
4017 struct ts_reg __iomem *ts_reg;
4018 char *buf, *src, *mac_src;
4019 struct timespec64 ts;
4020 struct ptp_ocp *bp;
4021 u16 sma_val[4][2];
4022 u32 ctrl, val;
4023 bool on, map;
4024 int i;
4025
4026 buf = (char *)__get_free_page(GFP_KERNEL);
4027 if (!buf)
4028 return -ENOMEM;
4029
4030 bp = dev_get_drvdata(dev);
4031
4032 seq_printf(s, "%7s: /dev/ptp%d\n", "PTP", ptp_clock_index(bp->ptp));
4033 for (i = 0; i < __PORT_COUNT; i++) {
4034 if (bp->port[i].line != -1)
4035 seq_printf(s, "%7s: /dev/ttyS%d\n", ptp_ocp_tty_port_name(i),
4036 bp->port[i].line);
4037 }
4038
4039 memset(sma_val, 0xff, sizeof(sma_val));
4040 if (bp->sma_map1) {
4041 u32 reg;
4042
4043 reg = ioread32(&bp->sma_map1->gpio1);
4044 sma_val[0][0] = reg & 0xffff;
4045 sma_val[1][0] = reg >> 16;
4046
4047 reg = ioread32(&bp->sma_map1->gpio2);
4048 sma_val[2][1] = reg & 0xffff;
4049 sma_val[3][1] = reg >> 16;
4050
4051 reg = ioread32(&bp->sma_map2->gpio1);
4052 sma_val[2][0] = reg & 0xffff;
4053 sma_val[3][0] = reg >> 16;
4054
4055 reg = ioread32(&bp->sma_map2->gpio2);
4056 sma_val[0][1] = reg & 0xffff;
4057 sma_val[1][1] = reg >> 16;
4058 }
4059
4060 sma1_show(dev, NULL, buf);
4061 seq_printf(s, " sma1: %04x,%04x %s",
4062 sma_val[0][0], sma_val[0][1], buf);
4063
4064 sma2_show(dev, NULL, buf);
4065 seq_printf(s, " sma2: %04x,%04x %s",
4066 sma_val[1][0], sma_val[1][1], buf);
4067
4068 sma3_show(dev, NULL, buf);
4069 seq_printf(s, " sma3: %04x,%04x %s",
4070 sma_val[2][0], sma_val[2][1], buf);
4071
4072 sma4_show(dev, NULL, buf);
4073 seq_printf(s, " sma4: %04x,%04x %s",
4074 sma_val[3][0], sma_val[3][1], buf);
4075
4076 if (bp->ts0) {
4077 ts_reg = bp->ts0->mem;
4078 on = ioread32(&ts_reg->enable);
4079 src = "GNSS1";
4080 seq_printf(s, "%7s: %s, src: %s\n", "TS0",
4081 on ? " ON" : "OFF", src);
4082 }
4083
4084 if (bp->ts1) {
4085 ts_reg = bp->ts1->mem;
4086 on = ioread32(&ts_reg->enable);
4087 gpio_input_map(buf, bp, sma_val, 2, NULL);
4088 seq_printf(s, "%7s: %s, src: %s\n", "TS1",
4089 on ? " ON" : "OFF", buf);
4090 }
4091
4092 if (bp->ts2) {
4093 ts_reg = bp->ts2->mem;
4094 on = ioread32(&ts_reg->enable);
4095 gpio_input_map(buf, bp, sma_val, 3, NULL);
4096 seq_printf(s, "%7s: %s, src: %s\n", "TS2",
4097 on ? " ON" : "OFF", buf);
4098 }
4099
4100 if (bp->ts3) {
4101 ts_reg = bp->ts3->mem;
4102 on = ioread32(&ts_reg->enable);
4103 gpio_input_map(buf, bp, sma_val, 6, NULL);
4104 seq_printf(s, "%7s: %s, src: %s\n", "TS3",
4105 on ? " ON" : "OFF", buf);
4106 }
4107
4108 if (bp->ts4) {
4109 ts_reg = bp->ts4->mem;
4110 on = ioread32(&ts_reg->enable);
4111 gpio_input_map(buf, bp, sma_val, 7, NULL);
4112 seq_printf(s, "%7s: %s, src: %s\n", "TS4",
4113 on ? " ON" : "OFF", buf);
4114 }
4115
4116 if (bp->pps) {
4117 ts_reg = bp->pps->mem;
4118 src = "PHC";
4119 on = ioread32(&ts_reg->enable);
4120 map = !!(bp->pps_req_map & OCP_REQ_TIMESTAMP);
4121 seq_printf(s, "%7s: %s, src: %s\n", "TS5",
4122 on && map ? " ON" : "OFF", src);
4123
4124 map = !!(bp->pps_req_map & OCP_REQ_PPS);
4125 seq_printf(s, "%7s: %s, src: %s\n", "PPS",
4126 on && map ? " ON" : "OFF", src);
4127 }
4128
4129 if (bp->fw_cap & OCP_CAP_SIGNAL)
4130 for (i = 0; i < 4; i++)
4131 _signal_summary_show(s, bp, i);
4132
4133 if (bp->fw_cap & OCP_CAP_FREQ)
4134 for (i = 0; i < 4; i++)
4135 _frequency_summary_show(s, i, bp->freq_in[i]);
4136
4137 if (bp->irig_out) {
4138 ctrl = ioread32(&bp->irig_out->ctrl);
4139 on = ctrl & IRIG_M_CTRL_ENABLE;
4140 val = ioread32(&bp->irig_out->status);
4141 gpio_output_map(buf, bp, sma_val, 4);
4142 seq_printf(s, "%7s: %s, error: %d, mode %d, out: %s\n", "IRIG",
4143 on ? " ON" : "OFF", val, (ctrl >> 16), buf);
4144 }
4145
4146 if (bp->irig_in) {
4147 on = ioread32(&bp->irig_in->ctrl) & IRIG_S_CTRL_ENABLE;
4148 val = ioread32(&bp->irig_in->status);
4149 gpio_input_map(buf, bp, sma_val, 4, NULL);
4150 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "IRIG in",
4151 on ? " ON" : "OFF", val, buf);
4152 }
4153
4154 if (bp->dcf_out) {
4155 on = ioread32(&bp->dcf_out->ctrl) & DCF_M_CTRL_ENABLE;
4156 val = ioread32(&bp->dcf_out->status);
4157 gpio_output_map(buf, bp, sma_val, 5);
4158 seq_printf(s, "%7s: %s, error: %d, out: %s\n", "DCF",
4159 on ? " ON" : "OFF", val, buf);
4160 }
4161
4162 if (bp->dcf_in) {
4163 on = ioread32(&bp->dcf_in->ctrl) & DCF_S_CTRL_ENABLE;
4164 val = ioread32(&bp->dcf_in->status);
4165 gpio_input_map(buf, bp, sma_val, 5, NULL);
4166 seq_printf(s, "%7s: %s, error: %d, src: %s\n", "DCF in",
4167 on ? " ON" : "OFF", val, buf);
4168 }
4169
4170 if (bp->nmea_out) {
4171 on = ioread32(&bp->nmea_out->ctrl) & 1;
4172 val = ioread32(&bp->nmea_out->status);
4173 seq_printf(s, "%7s: %s, error: %d\n", "NMEA",
4174 on ? " ON" : "OFF", val);
4175 }
4176
4177 /* compute src for PPS1, used below. */
4178 if (bp->pps_select) {
4179 val = ioread32(&bp->pps_select->gpio1);
4180 src = &buf[80];
4181 mac_src = "GNSS1";
4182 if (val & 0x01) {
4183 gpio_input_map(src, bp, sma_val, 0, NULL);
4184 mac_src = src;
4185 } else if (val & 0x02) {
4186 src = "MAC";
4187 } else if (val & 0x04) {
4188 src = "GNSS1";
4189 } else {
4190 src = "----";
4191 mac_src = src;
4192 }
4193 } else {
4194 src = "?";
4195 mac_src = src;
4196 }
4197 seq_printf(s, "MAC PPS1 src: %s\n", mac_src);
4198
4199 gpio_input_map(buf, bp, sma_val, 1, "GNSS2");
4200 seq_printf(s, "MAC PPS2 src: %s\n", buf);
4201
4202 /* assumes automatic switchover/selection */
4203 val = ioread32(&bp->reg->select);
4204 switch (val >> 16) {
4205 case 0:
4206 sprintf(buf, "----");
4207 break;
4208 case 2:
4209 sprintf(buf, "IRIG");
4210 break;
4211 case 3:
4212 sprintf(buf, "%s via PPS1", src);
4213 break;
4214 case 6:
4215 sprintf(buf, "DCF");
4216 break;
4217 default:
4218 strcpy(buf, "unknown");
4219 break;
4220 }
4221 seq_printf(s, "%7s: %s, state: %s\n", "PHC src", buf,
4222 bp->sync ? "sync" : "unsynced");
4223
4224 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, &sts)) {
4225 struct timespec64 sys_ts;
4226 s64 pre_ns, post_ns, ns;
4227
4228 pre_ns = timespec64_to_ns(&sts.pre_ts);
4229 post_ns = timespec64_to_ns(&sts.post_ts);
4230 ns = (pre_ns + post_ns) / 2;
4231 ns += (s64)bp->utc_tai_offset * NSEC_PER_SEC;
4232 sys_ts = ns_to_timespec64(ns);
4233
4234 seq_printf(s, "%7s: %lld.%ld == %ptT TAI\n", "PHC",
4235 ts.tv_sec, ts.tv_nsec, &ts);
4236 seq_printf(s, "%7s: %lld.%ld == %ptT UTC offset %d\n", "SYS",
4237 sys_ts.tv_sec, sys_ts.tv_nsec, &sys_ts,
4238 bp->utc_tai_offset);
4239 seq_printf(s, "%7s: PHC:SYS offset: %lld window: %lld\n", "",
4240 timespec64_to_ns(&ts) - ns,
4241 post_ns - pre_ns);
4242 }
4243
4244 free_page((unsigned long)buf);
4245 return 0;
4246 }
4247 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_summary);
4248
4249 static int
ptp_ocp_tod_status_show(struct seq_file * s,void * data)4250 ptp_ocp_tod_status_show(struct seq_file *s, void *data)
4251 {
4252 struct device *dev = s->private;
4253 struct ptp_ocp *bp;
4254 u32 val;
4255 int idx;
4256
4257 bp = dev_get_drvdata(dev);
4258
4259 val = ioread32(&bp->tod->ctrl);
4260 if (!(val & TOD_CTRL_ENABLE)) {
4261 seq_printf(s, "TOD Slave disabled\n");
4262 return 0;
4263 }
4264 seq_printf(s, "TOD Slave enabled, Control Register 0x%08X\n", val);
4265
4266 idx = val & TOD_CTRL_PROTOCOL ? 4 : 0;
4267 idx += (val >> 16) & 3;
4268 seq_printf(s, "Protocol %s\n", ptp_ocp_tod_proto_name(idx));
4269
4270 idx = (val >> TOD_CTRL_GNSS_SHIFT) & TOD_CTRL_GNSS_MASK;
4271 seq_printf(s, "GNSS %s\n", ptp_ocp_tod_gnss_name(idx));
4272
4273 val = ioread32(&bp->tod->version);
4274 seq_printf(s, "TOD Version %d.%d.%d\n",
4275 val >> 24, (val >> 16) & 0xff, val & 0xffff);
4276
4277 val = ioread32(&bp->tod->status);
4278 seq_printf(s, "Status register: 0x%08X\n", val);
4279
4280 val = ioread32(&bp->tod->adj_sec);
4281 idx = (val & ~INT_MAX) ? -1 : 1;
4282 idx *= (val & INT_MAX);
4283 seq_printf(s, "Correction seconds: %d\n", idx);
4284
4285 val = ioread32(&bp->tod->utc_status);
4286 seq_printf(s, "UTC status register: 0x%08X\n", val);
4287 seq_printf(s, "UTC offset: %ld valid:%d\n",
4288 val & TOD_STATUS_UTC_MASK, val & TOD_STATUS_UTC_VALID ? 1 : 0);
4289 seq_printf(s, "Leap second info valid:%d, Leap second announce %d\n",
4290 val & TOD_STATUS_LEAP_VALID ? 1 : 0,
4291 val & TOD_STATUS_LEAP_ANNOUNCE ? 1 : 0);
4292
4293 val = ioread32(&bp->tod->leap);
4294 seq_printf(s, "Time to next leap second (in sec): %d\n", (s32) val);
4295
4296 return 0;
4297 }
4298 DEFINE_SHOW_ATTRIBUTE(ptp_ocp_tod_status);
4299
4300 static struct dentry *ptp_ocp_debugfs_root;
4301
4302 static void
ptp_ocp_debugfs_add_device(struct ptp_ocp * bp)4303 ptp_ocp_debugfs_add_device(struct ptp_ocp *bp)
4304 {
4305 struct dentry *d;
4306
4307 d = debugfs_create_dir(dev_name(&bp->dev), ptp_ocp_debugfs_root);
4308 bp->debug_root = d;
4309 debugfs_create_file("summary", 0444, bp->debug_root,
4310 &bp->dev, &ptp_ocp_summary_fops);
4311 if (bp->tod)
4312 debugfs_create_file("tod_status", 0444, bp->debug_root,
4313 &bp->dev, &ptp_ocp_tod_status_fops);
4314 }
4315
4316 static void
ptp_ocp_debugfs_remove_device(struct ptp_ocp * bp)4317 ptp_ocp_debugfs_remove_device(struct ptp_ocp *bp)
4318 {
4319 debugfs_remove_recursive(bp->debug_root);
4320 }
4321
4322 static void
ptp_ocp_debugfs_init(void)4323 ptp_ocp_debugfs_init(void)
4324 {
4325 ptp_ocp_debugfs_root = debugfs_create_dir("timecard", NULL);
4326 }
4327
4328 static void
ptp_ocp_debugfs_fini(void)4329 ptp_ocp_debugfs_fini(void)
4330 {
4331 debugfs_remove_recursive(ptp_ocp_debugfs_root);
4332 }
4333
4334 static void
ptp_ocp_dev_release(struct device * dev)4335 ptp_ocp_dev_release(struct device *dev)
4336 {
4337 struct ptp_ocp *bp = dev_get_drvdata(dev);
4338
4339 mutex_lock(&ptp_ocp_lock);
4340 idr_remove(&ptp_ocp_idr, bp->id);
4341 mutex_unlock(&ptp_ocp_lock);
4342 }
4343
4344 static int
ptp_ocp_device_init(struct ptp_ocp * bp,struct pci_dev * pdev)4345 ptp_ocp_device_init(struct ptp_ocp *bp, struct pci_dev *pdev)
4346 {
4347 int i, err;
4348
4349 mutex_lock(&ptp_ocp_lock);
4350 err = idr_alloc(&ptp_ocp_idr, bp, 0, 0, GFP_KERNEL);
4351 mutex_unlock(&ptp_ocp_lock);
4352 if (err < 0) {
4353 dev_err(&pdev->dev, "idr_alloc failed: %d\n", err);
4354 return err;
4355 }
4356 bp->id = err;
4357
4358 bp->ptp_info = ptp_ocp_clock_info;
4359 spin_lock_init(&bp->lock);
4360
4361 for (i = 0; i < __PORT_COUNT; i++)
4362 bp->port[i].line = -1;
4363
4364 bp->pdev = pdev;
4365
4366 device_initialize(&bp->dev);
4367 dev_set_name(&bp->dev, "ocp%d", bp->id);
4368 bp->dev.class = &timecard_class;
4369 bp->dev.parent = &pdev->dev;
4370 bp->dev.release = ptp_ocp_dev_release;
4371 dev_set_drvdata(&bp->dev, bp);
4372
4373 err = device_add(&bp->dev);
4374 if (err) {
4375 dev_err(&bp->dev, "device add failed: %d\n", err);
4376 goto out;
4377 }
4378
4379 pci_set_drvdata(pdev, bp);
4380
4381 return 0;
4382
4383 out:
4384 put_device(&bp->dev);
4385 return err;
4386 }
4387
4388 static void
ptp_ocp_symlink(struct ptp_ocp * bp,struct device * child,const char * link)4389 ptp_ocp_symlink(struct ptp_ocp *bp, struct device *child, const char *link)
4390 {
4391 struct device *dev = &bp->dev;
4392
4393 if (sysfs_create_link(&dev->kobj, &child->kobj, link))
4394 dev_err(dev, "%s symlink failed\n", link);
4395 }
4396
4397 static void
ptp_ocp_link_child(struct ptp_ocp * bp,const char * name,const char * link)4398 ptp_ocp_link_child(struct ptp_ocp *bp, const char *name, const char *link)
4399 {
4400 struct device *dev, *child;
4401
4402 dev = &bp->pdev->dev;
4403
4404 child = device_find_child_by_name(dev, name);
4405 if (!child) {
4406 dev_err(dev, "Could not find device %s\n", name);
4407 return;
4408 }
4409
4410 ptp_ocp_symlink(bp, child, link);
4411 put_device(child);
4412 }
4413
4414 static int
ptp_ocp_complete(struct ptp_ocp * bp)4415 ptp_ocp_complete(struct ptp_ocp *bp)
4416 {
4417 struct pps_device *pps;
4418 char buf[32];
4419
4420 sprintf(buf, "ptp%d", ptp_clock_index(bp->ptp));
4421 ptp_ocp_link_child(bp, buf, "ptp");
4422
4423 pps = pps_lookup_dev(bp->ptp);
4424 if (pps)
4425 ptp_ocp_symlink(bp, &pps->dev, "pps");
4426
4427 ptp_ocp_debugfs_add_device(bp);
4428
4429 return 0;
4430 }
4431
4432 static void
ptp_ocp_phc_info(struct ptp_ocp * bp)4433 ptp_ocp_phc_info(struct ptp_ocp *bp)
4434 {
4435 struct timespec64 ts;
4436 u32 version, select;
4437
4438 version = ioread32(&bp->reg->version);
4439 select = ioread32(&bp->reg->select);
4440 dev_info(&bp->pdev->dev, "Version %d.%d.%d, clock %s, device ptp%d\n",
4441 version >> 24, (version >> 16) & 0xff, version & 0xffff,
4442 ptp_ocp_select_name_from_val(ptp_ocp_clock, select >> 16),
4443 ptp_clock_index(bp->ptp));
4444
4445 if (!ptp_ocp_gettimex(&bp->ptp_info, &ts, NULL))
4446 dev_info(&bp->pdev->dev, "Time: %lld.%ld, %s\n",
4447 ts.tv_sec, ts.tv_nsec,
4448 bp->sync ? "in-sync" : "UNSYNCED");
4449 }
4450
4451 static void
ptp_ocp_serial_info(struct device * dev,const char * name,int port,int baud)4452 ptp_ocp_serial_info(struct device *dev, const char *name, int port, int baud)
4453 {
4454 if (port != -1)
4455 dev_info(dev, "%5s: /dev/ttyS%-2d @ %6d\n", name, port, baud);
4456 }
4457
4458 static void
ptp_ocp_info(struct ptp_ocp * bp)4459 ptp_ocp_info(struct ptp_ocp *bp)
4460 {
4461 static int nmea_baud[] = {
4462 1200, 2400, 4800, 9600, 19200, 38400,
4463 57600, 115200, 230400, 460800, 921600,
4464 1000000, 2000000
4465 };
4466 struct device *dev = &bp->pdev->dev;
4467 u32 reg;
4468 int i;
4469
4470 ptp_ocp_phc_info(bp);
4471
4472 for (i = 0; i < __PORT_COUNT; i++) {
4473 if (i == PORT_NMEA && bp->nmea_out && bp->port[PORT_NMEA].line != -1) {
4474 bp->port[PORT_NMEA].baud = -1;
4475
4476 reg = ioread32(&bp->nmea_out->uart_baud);
4477 if (reg < ARRAY_SIZE(nmea_baud))
4478 bp->port[PORT_NMEA].baud = nmea_baud[reg];
4479 }
4480 ptp_ocp_serial_info(dev, ptp_ocp_tty_port_name(i), bp->port[i].line,
4481 bp->port[i].baud);
4482 }
4483 }
4484
4485 static void
ptp_ocp_detach_sysfs(struct ptp_ocp * bp)4486 ptp_ocp_detach_sysfs(struct ptp_ocp *bp)
4487 {
4488 struct device *dev = &bp->dev;
4489
4490 sysfs_remove_link(&dev->kobj, "ptp");
4491 sysfs_remove_link(&dev->kobj, "pps");
4492 }
4493
4494 static void
ptp_ocp_detach(struct ptp_ocp * bp)4495 ptp_ocp_detach(struct ptp_ocp *bp)
4496 {
4497 int i;
4498
4499 ptp_ocp_debugfs_remove_device(bp);
4500 ptp_ocp_detach_sysfs(bp);
4501 ptp_ocp_attr_group_del(bp);
4502 if (timer_pending(&bp->watchdog))
4503 timer_delete_sync(&bp->watchdog);
4504 if (bp->ts0)
4505 ptp_ocp_unregister_ext(bp->ts0);
4506 if (bp->ts1)
4507 ptp_ocp_unregister_ext(bp->ts1);
4508 if (bp->ts2)
4509 ptp_ocp_unregister_ext(bp->ts2);
4510 if (bp->ts3)
4511 ptp_ocp_unregister_ext(bp->ts3);
4512 if (bp->ts4)
4513 ptp_ocp_unregister_ext(bp->ts4);
4514 if (bp->pps)
4515 ptp_ocp_unregister_ext(bp->pps);
4516 for (i = 0; i < 4; i++)
4517 if (bp->signal_out[i])
4518 ptp_ocp_unregister_ext(bp->signal_out[i]);
4519 for (i = 0; i < __PORT_COUNT; i++)
4520 if (bp->port[i].line != -1)
4521 serial8250_unregister_port(bp->port[i].line);
4522 platform_device_unregister(bp->spi_flash);
4523 platform_device_unregister(bp->i2c_ctrl);
4524 if (bp->i2c_clk)
4525 clk_hw_unregister_fixed_rate(bp->i2c_clk);
4526 if (bp->n_irqs)
4527 pci_free_irq_vectors(bp->pdev);
4528 if (bp->ptp)
4529 ptp_clock_unregister(bp->ptp);
4530 kfree(bp->ptp_info.pin_config);
4531 device_unregister(&bp->dev);
4532 }
4533
4534 static int
ptp_ocp_dpll_lock_status_get(const struct dpll_device * dpll,void * priv,enum dpll_lock_status * status,enum dpll_lock_status_error * status_error,struct netlink_ext_ack * extack)4535 ptp_ocp_dpll_lock_status_get(const struct dpll_device *dpll, void *priv,
4536 enum dpll_lock_status *status,
4537 enum dpll_lock_status_error *status_error,
4538 struct netlink_ext_ack *extack)
4539 {
4540 struct ptp_ocp *bp = priv;
4541
4542 *status = bp->sync ? DPLL_LOCK_STATUS_LOCKED : DPLL_LOCK_STATUS_UNLOCKED;
4543
4544 return 0;
4545 }
4546
ptp_ocp_dpll_state_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * priv,enum dpll_pin_state * state,struct netlink_ext_ack * extack)4547 static int ptp_ocp_dpll_state_get(const struct dpll_pin *pin, void *pin_priv,
4548 const struct dpll_device *dpll, void *priv,
4549 enum dpll_pin_state *state,
4550 struct netlink_ext_ack *extack)
4551 {
4552 struct ptp_ocp *bp = priv;
4553 int idx;
4554
4555 if (bp->pps_select) {
4556 idx = ioread32(&bp->pps_select->gpio1);
4557 *state = (&bp->sma[idx] == pin_priv) ? DPLL_PIN_STATE_CONNECTED :
4558 DPLL_PIN_STATE_SELECTABLE;
4559 return 0;
4560 }
4561 NL_SET_ERR_MSG(extack, "pin selection is not supported on current HW");
4562 return -EINVAL;
4563 }
4564
ptp_ocp_dpll_mode_get(const struct dpll_device * dpll,void * priv,enum dpll_mode * mode,struct netlink_ext_ack * extack)4565 static int ptp_ocp_dpll_mode_get(const struct dpll_device *dpll, void *priv,
4566 enum dpll_mode *mode, struct netlink_ext_ack *extack)
4567 {
4568 *mode = DPLL_MODE_AUTOMATIC;
4569 return 0;
4570 }
4571
ptp_ocp_dpll_direction_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * priv,enum dpll_pin_direction * direction,struct netlink_ext_ack * extack)4572 static int ptp_ocp_dpll_direction_get(const struct dpll_pin *pin,
4573 void *pin_priv,
4574 const struct dpll_device *dpll,
4575 void *priv,
4576 enum dpll_pin_direction *direction,
4577 struct netlink_ext_ack *extack)
4578 {
4579 struct ptp_ocp_sma_connector *sma = pin_priv;
4580
4581 *direction = sma->mode == SMA_MODE_IN ?
4582 DPLL_PIN_DIRECTION_INPUT :
4583 DPLL_PIN_DIRECTION_OUTPUT;
4584 return 0;
4585 }
4586
ptp_ocp_dpll_direction_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,enum dpll_pin_direction direction,struct netlink_ext_ack * extack)4587 static int ptp_ocp_dpll_direction_set(const struct dpll_pin *pin,
4588 void *pin_priv,
4589 const struct dpll_device *dpll,
4590 void *dpll_priv,
4591 enum dpll_pin_direction direction,
4592 struct netlink_ext_ack *extack)
4593 {
4594 struct ptp_ocp_sma_connector *sma = pin_priv;
4595 struct ptp_ocp *bp = dpll_priv;
4596 enum ptp_ocp_sma_mode mode;
4597 int sma_nr = (sma - bp->sma);
4598
4599 if (sma->fixed_dir)
4600 return -EOPNOTSUPP;
4601 mode = direction == DPLL_PIN_DIRECTION_INPUT ?
4602 SMA_MODE_IN : SMA_MODE_OUT;
4603 return ptp_ocp_sma_store_val(bp, 0, mode, sma_nr + 1);
4604 }
4605
ptp_ocp_dpll_frequency_set(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 frequency,struct netlink_ext_ack * extack)4606 static int ptp_ocp_dpll_frequency_set(const struct dpll_pin *pin,
4607 void *pin_priv,
4608 const struct dpll_device *dpll,
4609 void *dpll_priv, u64 frequency,
4610 struct netlink_ext_ack *extack)
4611 {
4612 struct ptp_ocp_sma_connector *sma = pin_priv;
4613 struct ptp_ocp *bp = dpll_priv;
4614 const struct ocp_selector *tbl;
4615 int sma_nr = (sma - bp->sma);
4616 int i;
4617
4618 if (sma->fixed_fcn)
4619 return -EOPNOTSUPP;
4620
4621 tbl = bp->sma_op->tbl[sma->mode];
4622 for (i = 0; tbl[i].name; i++)
4623 if (tbl[i].frequency == frequency)
4624 return ptp_ocp_sma_store_val(bp, i, sma->mode, sma_nr + 1);
4625 return -EINVAL;
4626 }
4627
ptp_ocp_dpll_frequency_get(const struct dpll_pin * pin,void * pin_priv,const struct dpll_device * dpll,void * dpll_priv,u64 * frequency,struct netlink_ext_ack * extack)4628 static int ptp_ocp_dpll_frequency_get(const struct dpll_pin *pin,
4629 void *pin_priv,
4630 const struct dpll_device *dpll,
4631 void *dpll_priv, u64 *frequency,
4632 struct netlink_ext_ack *extack)
4633 {
4634 struct ptp_ocp_sma_connector *sma = pin_priv;
4635 struct ptp_ocp *bp = dpll_priv;
4636 const struct ocp_selector *tbl;
4637 int sma_nr = (sma - bp->sma);
4638 u32 val;
4639 int i;
4640
4641 val = bp->sma_op->get(bp, sma_nr + 1);
4642 tbl = bp->sma_op->tbl[sma->mode];
4643 for (i = 0; tbl[i].name; i++)
4644 if (val == tbl[i].value) {
4645 *frequency = tbl[i].frequency;
4646 return 0;
4647 }
4648
4649 return -EINVAL;
4650 }
4651
4652 static const struct dpll_device_ops dpll_ops = {
4653 .lock_status_get = ptp_ocp_dpll_lock_status_get,
4654 .mode_get = ptp_ocp_dpll_mode_get,
4655 };
4656
4657 static const struct dpll_pin_ops dpll_pins_ops = {
4658 .frequency_get = ptp_ocp_dpll_frequency_get,
4659 .frequency_set = ptp_ocp_dpll_frequency_set,
4660 .direction_get = ptp_ocp_dpll_direction_get,
4661 .direction_set = ptp_ocp_dpll_direction_set,
4662 .state_on_dpll_get = ptp_ocp_dpll_state_get,
4663 };
4664
4665 static void
ptp_ocp_sync_work(struct work_struct * work)4666 ptp_ocp_sync_work(struct work_struct *work)
4667 {
4668 struct ptp_ocp *bp;
4669 bool sync;
4670
4671 bp = container_of(work, struct ptp_ocp, sync_work.work);
4672 sync = !!(ioread32(&bp->reg->status) & OCP_STATUS_IN_SYNC);
4673
4674 if (bp->sync != sync)
4675 dpll_device_change_ntf(bp->dpll);
4676
4677 bp->sync = sync;
4678
4679 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
4680 }
4681
4682 static int
ptp_ocp_probe(struct pci_dev * pdev,const struct pci_device_id * id)4683 ptp_ocp_probe(struct pci_dev *pdev, const struct pci_device_id *id)
4684 {
4685 struct devlink *devlink;
4686 struct ptp_ocp *bp;
4687 int err, i;
4688 u64 clkid;
4689
4690 devlink = devlink_alloc(&ptp_ocp_devlink_ops, sizeof(*bp), &pdev->dev);
4691 if (!devlink) {
4692 dev_err(&pdev->dev, "devlink_alloc failed\n");
4693 return -ENOMEM;
4694 }
4695
4696 err = pci_enable_device(pdev);
4697 if (err) {
4698 dev_err(&pdev->dev, "pci_enable_device\n");
4699 goto out_free;
4700 }
4701
4702 bp = devlink_priv(devlink);
4703 err = ptp_ocp_device_init(bp, pdev);
4704 if (err)
4705 goto out_disable;
4706
4707 INIT_DELAYED_WORK(&bp->sync_work, ptp_ocp_sync_work);
4708
4709 /* compat mode.
4710 * Older FPGA firmware only returns 2 irq's.
4711 * allow this - if not all of the IRQ's are returned, skip the
4712 * extra devices and just register the clock.
4713 */
4714 err = pci_alloc_irq_vectors(pdev, 1, 17, PCI_IRQ_MSI | PCI_IRQ_MSIX);
4715 if (err < 0) {
4716 dev_err(&pdev->dev, "alloc_irq_vectors err: %d\n", err);
4717 goto out;
4718 }
4719 bp->n_irqs = err;
4720 pci_set_master(pdev);
4721
4722 err = ptp_ocp_register_resources(bp, id->driver_data);
4723 if (err)
4724 goto out;
4725
4726 bp->ptp = ptp_clock_register(&bp->ptp_info, &pdev->dev);
4727 if (IS_ERR(bp->ptp)) {
4728 err = PTR_ERR(bp->ptp);
4729 dev_err(&pdev->dev, "ptp_clock_register: %d\n", err);
4730 bp->ptp = NULL;
4731 goto out;
4732 }
4733
4734 err = ptp_ocp_complete(bp);
4735 if (err)
4736 goto out;
4737
4738 ptp_ocp_info(bp);
4739 devlink_register(devlink);
4740
4741 clkid = pci_get_dsn(pdev);
4742 bp->dpll = dpll_device_get(clkid, 0, THIS_MODULE);
4743 if (IS_ERR(bp->dpll)) {
4744 err = PTR_ERR(bp->dpll);
4745 dev_err(&pdev->dev, "dpll_device_alloc failed\n");
4746 goto out;
4747 }
4748
4749 err = dpll_device_register(bp->dpll, DPLL_TYPE_PPS, &dpll_ops, bp);
4750 if (err)
4751 goto out;
4752
4753 for (i = 0; i < OCP_SMA_NUM; i++) {
4754 bp->sma[i].dpll_pin = dpll_pin_get(clkid, i, THIS_MODULE, &bp->sma[i].dpll_prop);
4755 if (IS_ERR(bp->sma[i].dpll_pin)) {
4756 err = PTR_ERR(bp->sma[i].dpll_pin);
4757 goto out_dpll;
4758 }
4759
4760 err = dpll_pin_register(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops,
4761 &bp->sma[i]);
4762 if (err) {
4763 dpll_pin_put(bp->sma[i].dpll_pin);
4764 goto out_dpll;
4765 }
4766 }
4767 queue_delayed_work(system_power_efficient_wq, &bp->sync_work, HZ);
4768
4769 return 0;
4770 out_dpll:
4771 while (i) {
4772 --i;
4773 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
4774 dpll_pin_put(bp->sma[i].dpll_pin);
4775 }
4776 dpll_device_put(bp->dpll);
4777 out:
4778 ptp_ocp_detach(bp);
4779 out_disable:
4780 pci_disable_device(pdev);
4781 out_free:
4782 devlink_free(devlink);
4783 return err;
4784 }
4785
4786 static void
ptp_ocp_remove(struct pci_dev * pdev)4787 ptp_ocp_remove(struct pci_dev *pdev)
4788 {
4789 struct ptp_ocp *bp = pci_get_drvdata(pdev);
4790 struct devlink *devlink = priv_to_devlink(bp);
4791 int i;
4792
4793 cancel_delayed_work_sync(&bp->sync_work);
4794 for (i = 0; i < OCP_SMA_NUM; i++) {
4795 if (bp->sma[i].dpll_pin) {
4796 dpll_pin_unregister(bp->dpll, bp->sma[i].dpll_pin, &dpll_pins_ops, &bp->sma[i]);
4797 dpll_pin_put(bp->sma[i].dpll_pin);
4798 }
4799 }
4800 dpll_device_unregister(bp->dpll, &dpll_ops, bp);
4801 dpll_device_put(bp->dpll);
4802 devlink_unregister(devlink);
4803 ptp_ocp_detach(bp);
4804 pci_disable_device(pdev);
4805
4806 devlink_free(devlink);
4807 }
4808
4809 static struct pci_driver ptp_ocp_driver = {
4810 .name = KBUILD_MODNAME,
4811 .id_table = ptp_ocp_pcidev_id,
4812 .probe = ptp_ocp_probe,
4813 .remove = ptp_ocp_remove,
4814 };
4815
4816 static int
ptp_ocp_i2c_notifier_call(struct notifier_block * nb,unsigned long action,void * data)4817 ptp_ocp_i2c_notifier_call(struct notifier_block *nb,
4818 unsigned long action, void *data)
4819 {
4820 struct device *dev, *child = data;
4821 struct ptp_ocp *bp;
4822 bool add;
4823
4824 switch (action) {
4825 case BUS_NOTIFY_ADD_DEVICE:
4826 case BUS_NOTIFY_DEL_DEVICE:
4827 add = action == BUS_NOTIFY_ADD_DEVICE;
4828 break;
4829 default:
4830 return 0;
4831 }
4832
4833 if (!i2c_verify_adapter(child))
4834 return 0;
4835
4836 dev = child;
4837 while ((dev = dev->parent))
4838 if (dev->driver && !strcmp(dev->driver->name, KBUILD_MODNAME))
4839 goto found;
4840 return 0;
4841
4842 found:
4843 bp = dev_get_drvdata(dev);
4844 if (add)
4845 ptp_ocp_symlink(bp, child, "i2c");
4846 else
4847 sysfs_remove_link(&bp->dev.kobj, "i2c");
4848
4849 return 0;
4850 }
4851
4852 static struct notifier_block ptp_ocp_i2c_notifier = {
4853 .notifier_call = ptp_ocp_i2c_notifier_call,
4854 };
4855
4856 static int __init
ptp_ocp_init(void)4857 ptp_ocp_init(void)
4858 {
4859 const char *what;
4860 int err;
4861
4862 ptp_ocp_debugfs_init();
4863
4864 what = "timecard class";
4865 err = class_register(&timecard_class);
4866 if (err)
4867 goto out;
4868
4869 what = "i2c notifier";
4870 err = bus_register_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4871 if (err)
4872 goto out_notifier;
4873
4874 what = "ptp_ocp driver";
4875 err = pci_register_driver(&ptp_ocp_driver);
4876 if (err)
4877 goto out_register;
4878
4879 return 0;
4880
4881 out_register:
4882 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4883 out_notifier:
4884 class_unregister(&timecard_class);
4885 out:
4886 ptp_ocp_debugfs_fini();
4887 pr_err(KBUILD_MODNAME ": failed to register %s: %d\n", what, err);
4888 return err;
4889 }
4890
4891 static void __exit
ptp_ocp_fini(void)4892 ptp_ocp_fini(void)
4893 {
4894 bus_unregister_notifier(&i2c_bus_type, &ptp_ocp_i2c_notifier);
4895 pci_unregister_driver(&ptp_ocp_driver);
4896 class_unregister(&timecard_class);
4897 ptp_ocp_debugfs_fini();
4898 }
4899
4900 module_init(ptp_ocp_init);
4901 module_exit(ptp_ocp_fini);
4902
4903 MODULE_DESCRIPTION("OpenCompute TimeCard driver");
4904 MODULE_LICENSE("GPL v2");
4905