1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3 * Copyright (C) 2008-2009 Michal Simek <monstr@monstr.eu>
4 * Copyright (C) 2008-2009 PetaLogix
5 * Copyright (C) 2006 Atmark Techno, Inc.
6 */
7
8 #ifndef _ASM_MICROBLAZE_PGTABLE_H
9 #define _ASM_MICROBLAZE_PGTABLE_H
10
11 #include <asm/setup.h>
12
13 #ifndef __ASSEMBLER__
14 extern int mem_init_done;
15 #endif
16
17 #include <asm-generic/pgtable-nopmd.h>
18
19 #ifdef __KERNEL__
20 #ifndef __ASSEMBLER__
21
22 #include <linux/sched.h>
23 #include <linux/threads.h>
24 #include <asm/processor.h> /* For TASK_SIZE */
25 #include <asm/mmu.h>
26 #include <asm/page.h>
27
28 extern unsigned long va_to_phys(unsigned long address);
29 extern pte_t *va_to_pte(unsigned long address);
30
31 /*
32 * The following only work if pte_present() is true.
33 * Undefined behaviour if not..
34 */
35
36 /* Start and end of the vmalloc area. */
37 /* Make sure to map the vmalloc area above the pinned kernel memory area
38 of 32Mb. */
39 #define VMALLOC_START (CONFIG_KERNEL_START + CONFIG_LOWMEM_SIZE)
40 #define VMALLOC_END ioremap_bot
41
42 #endif /* __ASSEMBLER__ */
43
44 /*
45 * Macro to mark a page protection value as "uncacheable".
46 */
47
48 #define _PAGE_CACHE_CTL (_PAGE_GUARDED | _PAGE_NO_CACHE | \
49 _PAGE_WRITETHRU)
50
51 #define pgprot_noncached(prot) \
52 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
53 _PAGE_NO_CACHE | _PAGE_GUARDED))
54
55 #define pgprot_noncached_wc(prot) \
56 (__pgprot((pgprot_val(prot) & ~_PAGE_CACHE_CTL) | \
57 _PAGE_NO_CACHE))
58
59 /*
60 * The MicroBlaze MMU is identical to the PPC-40x MMU, and uses a hash
61 * table containing PTEs, together with a set of 16 segment registers, to
62 * define the virtual to physical address mapping.
63 *
64 * We use the hash table as an extended TLB, i.e. a cache of currently
65 * active mappings. We maintain a two-level page table tree, much
66 * like that used by the i386, for the sake of the Linux memory
67 * management code. Low-level assembler code in hashtable.S
68 * (procedure hash_page) is responsible for extracting ptes from the
69 * tree and putting them into the hash table when necessary, and
70 * updating the accessed and modified bits in the page table tree.
71 */
72
73 /*
74 * The MicroBlaze processor has a TLB architecture identical to PPC-40x. The
75 * instruction and data sides share a unified, 64-entry, semi-associative
76 * TLB which is maintained totally under software control. In addition, the
77 * instruction side has a hardware-managed, 2,4, or 8-entry, fully-associative
78 * TLB which serves as a first level to the shared TLB. These two TLBs are
79 * known as the UTLB and ITLB, respectively (see "mmu.h" for definitions).
80 */
81
82 /*
83 * The normal case is that PTEs are 32-bits and we have a 1-page
84 * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages. -- paulus
85 *
86 */
87
88 /* PGDIR_SHIFT determines what a top-level page table entry can map */
89 #define PGDIR_SHIFT (PAGE_SHIFT + PTE_SHIFT)
90 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
91 #define PGDIR_MASK (~(PGDIR_SIZE-1))
92
93 /*
94 * entries per page directory level: our page-table tree is two-level, so
95 * we don't really have any PMD directory.
96 */
97 #define PTRS_PER_PTE (1 << PTE_SHIFT)
98 #define PTRS_PER_PMD 1
99 #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
100
101 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
102
103 #define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
104 #define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
105
106 #define pte_ERROR(e) \
107 printk(KERN_ERR "%s:%d: bad pte "PTE_FMT".\n", \
108 __FILE__, __LINE__, pte_val(e))
109 #define pgd_ERROR(e) \
110 printk(KERN_ERR "%s:%d: bad pgd %08lx.\n", \
111 __FILE__, __LINE__, pgd_val(e))
112
113 /*
114 * Bits in a linux-style PTE. These match the bits in the
115 * (hardware-defined) PTE as closely as possible.
116 */
117
118 /* There are several potential gotchas here. The hardware TLBLO
119 * field looks like this:
120 *
121 * 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
122 * RPN..................... 0 0 EX WR ZSEL....... W I M G
123 *
124 * Where possible we make the Linux PTE bits match up with this
125 *
126 * - bits 20 and 21 must be cleared, because we use 4k pages (4xx can
127 * support down to 1k pages), this is done in the TLBMiss exception
128 * handler.
129 * - We use only zones 0 (for kernel pages) and 1 (for user pages)
130 * of the 16 available. Bit 24-26 of the TLB are cleared in the TLB
131 * miss handler. Bit 27 is PAGE_USER, thus selecting the correct
132 * zone.
133 * - PRESENT *must* be in the bottom two bits because swap PTEs use the top
134 * 30 bits. Because 4xx doesn't support SMP anyway, M is irrelevant so we
135 * borrow it for PAGE_PRESENT. Bit 30 is cleared in the TLB miss handler
136 * before the TLB entry is loaded.
137 * - All other bits of the PTE are loaded into TLBLO without
138 * * modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
139 * software PTE bits. We actually use bits 21, 24, 25, and
140 * 30 respectively for the software bits: ACCESSED, DIRTY, RW, and
141 * PRESENT.
142 */
143
144 /* Definitions for MicroBlaze. */
145 #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */
146 #define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */
147 #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */
148 #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */
149 #define _PAGE_USER 0x010 /* matches one of the zone permission bits */
150 #define _PAGE_RW 0x040 /* software: Writes permitted */
151 #define _PAGE_DIRTY 0x080 /* software: dirty page */
152 #define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */
153 #define _PAGE_HWEXEC 0x200 /* hardware: EX permission */
154 #define _PAGE_ACCESSED 0x400 /* software: R: page referenced */
155 #define _PMD_PRESENT PAGE_MASK
156
157 /* We borrow bit 24 to store the exclusive marker in swap PTEs. */
158 #define _PAGE_SWP_EXCLUSIVE _PAGE_DIRTY
159
160 /*
161 * Some bits are unused...
162 */
163 #ifndef _PAGE_HASHPTE
164 #define _PAGE_HASHPTE 0
165 #endif
166 #ifndef _PTE_NONE_MASK
167 #define _PTE_NONE_MASK 0
168 #endif
169 #ifndef _PAGE_SHARED
170 #define _PAGE_SHARED 0
171 #endif
172 #ifndef _PAGE_EXEC
173 #define _PAGE_EXEC 0
174 #endif
175
176 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
177
178 /*
179 * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
180 * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
181 * to have it in the Linux PTE, and in fact the bit could be reused for
182 * another purpose. -- paulus.
183 */
184 #define _PAGE_BASE (_PAGE_PRESENT | _PAGE_ACCESSED)
185 #define _PAGE_WRENABLE (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
186
187 #define _PAGE_KERNEL \
188 (_PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC)
189
190 #define _PAGE_IO (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
191
192 #define PAGE_NONE __pgprot(_PAGE_BASE)
193 #define PAGE_READONLY __pgprot(_PAGE_BASE | _PAGE_USER)
194 #define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
195 #define PAGE_SHARED __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
196 #define PAGE_SHARED_X \
197 __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
198 #define PAGE_COPY __pgprot(_PAGE_BASE | _PAGE_USER)
199 #define PAGE_COPY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
200
201 #define PAGE_KERNEL __pgprot(_PAGE_KERNEL)
202 #define PAGE_KERNEL_RO __pgprot(_PAGE_BASE | _PAGE_SHARED)
203 #define PAGE_KERNEL_CI __pgprot(_PAGE_IO)
204
205 /*
206 * We consider execute permission the same as read.
207 * Also, write permissions imply read permissions.
208 */
209
210 #ifndef __ASSEMBLER__
211 /*
212 * ZERO_PAGE is a global shared page that is always zero: used
213 * for zero-mapped memory areas etc..
214 */
215 extern unsigned long empty_zero_page[1024];
216 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
217
218 #endif /* __ASSEMBLER__ */
219
220 #define pte_none(pte) ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
221 #define pte_present(pte) (pte_val(pte) & _PAGE_PRESENT)
222 #define pte_clear(mm, addr, ptep) \
223 do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
224
225 #define pmd_none(pmd) (!pmd_val(pmd))
226 #define pmd_bad(pmd) ((pmd_val(pmd) & _PMD_PRESENT) == 0)
227 #define pmd_present(pmd) ((pmd_val(pmd) & _PMD_PRESENT) != 0)
228 #define pmd_clear(pmdp) do { pmd_val(*(pmdp)) = 0; } while (0)
229
230 #define pte_page(x) (mem_map + (unsigned long) \
231 ((pte_val(x) - memory_start) >> PAGE_SHIFT))
232 #define PFN_PTE_SHIFT PAGE_SHIFT
233
234 #define pte_pfn(x) (pte_val(x) >> PFN_PTE_SHIFT)
235
236 #define pfn_pte(pfn, prot) \
237 __pte(((pte_basic_t)(pfn) << PFN_PTE_SHIFT) | pgprot_val(prot))
238
239 #ifndef __ASSEMBLER__
240 /*
241 * The following only work if pte_present() is true.
242 * Undefined behaviour if not..
243 */
pte_read(pte_t pte)244 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_USER; }
pte_write(pte_t pte)245 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW; }
pte_exec(pte_t pte)246 static inline int pte_exec(pte_t pte) { return pte_val(pte) & _PAGE_EXEC; }
pte_dirty(pte_t pte)247 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY; }
pte_young(pte_t pte)248 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
249
pte_uncache(pte_t pte)250 static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
pte_cache(pte_t pte)251 static inline void pte_cache(pte_t pte) { pte_val(pte) &= ~_PAGE_NO_CACHE; }
252
pte_rdprotect(pte_t pte)253 static inline pte_t pte_rdprotect(pte_t pte) \
254 { pte_val(pte) &= ~_PAGE_USER; return pte; }
pte_wrprotect(pte_t pte)255 static inline pte_t pte_wrprotect(pte_t pte) \
256 { pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
pte_exprotect(pte_t pte)257 static inline pte_t pte_exprotect(pte_t pte) \
258 { pte_val(pte) &= ~_PAGE_EXEC; return pte; }
pte_mkclean(pte_t pte)259 static inline pte_t pte_mkclean(pte_t pte) \
260 { pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
pte_mkold(pte_t pte)261 static inline pte_t pte_mkold(pte_t pte) \
262 { pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
263
pte_mkread(pte_t pte)264 static inline pte_t pte_mkread(pte_t pte) \
265 { pte_val(pte) |= _PAGE_USER; return pte; }
pte_mkexec(pte_t pte)266 static inline pte_t pte_mkexec(pte_t pte) \
267 { pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
pte_mkwrite_novma(pte_t pte)268 static inline pte_t pte_mkwrite_novma(pte_t pte) \
269 { pte_val(pte) |= _PAGE_RW; return pte; }
pte_mkdirty(pte_t pte)270 static inline pte_t pte_mkdirty(pte_t pte) \
271 { pte_val(pte) |= _PAGE_DIRTY; return pte; }
pte_mkyoung(pte_t pte)272 static inline pte_t pte_mkyoung(pte_t pte) \
273 { pte_val(pte) |= _PAGE_ACCESSED; return pte; }
274
275 /*
276 * Conversion functions: convert a page and protection to a page entry,
277 * and a page entry and page directory to the page they refer to.
278 */
279
mk_pte_phys(phys_addr_t physpage,pgprot_t pgprot)280 static inline pte_t mk_pte_phys(phys_addr_t physpage, pgprot_t pgprot)
281 {
282 pte_t pte;
283 pte_val(pte) = physpage | pgprot_val(pgprot);
284 return pte;
285 }
286
pte_modify(pte_t pte,pgprot_t newprot)287 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
288 {
289 pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
290 return pte;
291 }
292
293 /*
294 * Atomic PTE updates.
295 *
296 * pte_update clears and sets bit atomically, and returns
297 * the old pte value.
298 * The ((unsigned long)(p+1) - 4) hack is to get to the least-significant
299 * 32 bits of the PTE regardless of whether PTEs are 32 or 64 bits.
300 */
pte_update(pte_t * p,unsigned long clr,unsigned long set)301 static inline unsigned long pte_update(pte_t *p, unsigned long clr,
302 unsigned long set)
303 {
304 unsigned long flags, old, tmp;
305
306 raw_local_irq_save(flags);
307
308 __asm__ __volatile__( "lw %0, %2, r0 \n"
309 "andn %1, %0, %3 \n"
310 "or %1, %1, %4 \n"
311 "sw %1, %2, r0 \n"
312 : "=&r" (old), "=&r" (tmp)
313 : "r" ((unsigned long)(p + 1) - 4), "r" (clr), "r" (set)
314 : "cc");
315
316 raw_local_irq_restore(flags);
317
318 return old;
319 }
320
321 /*
322 * set_pte stores a linux PTE into the linux page table.
323 */
set_pte(pte_t * ptep,pte_t pte)324 static inline void set_pte(pte_t *ptep, pte_t pte)
325 {
326 *ptep = pte;
327 }
328
329 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
330 struct vm_area_struct;
ptep_test_and_clear_young(struct vm_area_struct * vma,unsigned long address,pte_t * ptep)331 static inline int ptep_test_and_clear_young(struct vm_area_struct *vma,
332 unsigned long address, pte_t *ptep)
333 {
334 return (pte_update(ptep, _PAGE_ACCESSED, 0) & _PAGE_ACCESSED) != 0;
335 }
336
ptep_test_and_clear_dirty(struct mm_struct * mm,unsigned long addr,pte_t * ptep)337 static inline int ptep_test_and_clear_dirty(struct mm_struct *mm,
338 unsigned long addr, pte_t *ptep)
339 {
340 return (pte_update(ptep, \
341 (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
342 }
343
344 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
ptep_get_and_clear(struct mm_struct * mm,unsigned long addr,pte_t * ptep)345 static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
346 unsigned long addr, pte_t *ptep)
347 {
348 return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
349 }
350
351 /*static inline void ptep_set_wrprotect(struct mm_struct *mm,
352 unsigned long addr, pte_t *ptep)
353 {
354 pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
355 }*/
356
ptep_mkdirty(struct mm_struct * mm,unsigned long addr,pte_t * ptep)357 static inline void ptep_mkdirty(struct mm_struct *mm,
358 unsigned long addr, pte_t *ptep)
359 {
360 pte_update(ptep, 0, _PAGE_DIRTY);
361 }
362
363 /*#define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)*/
364
365 /* Convert pmd entry to page */
366 /* our pmd entry is an effective address of pte table*/
367 /* returns effective address of the pmd entry*/
pmd_page_vaddr(pmd_t pmd)368 static inline unsigned long pmd_page_vaddr(pmd_t pmd)
369 {
370 return ((unsigned long) (pmd_val(pmd) & PAGE_MASK));
371 }
372
373 /* returns pfn of the pmd entry*/
374 #define pmd_pfn(pmd) (__pa(pmd_val(pmd)) >> PAGE_SHIFT)
375
376 /* returns struct *page of the pmd entry*/
377 #define pmd_page(pmd) (pfn_to_page(__pa(pmd_val(pmd)) >> PAGE_SHIFT))
378
379 /* Find an entry in the third-level page table.. */
380
381 extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
382
383 /*
384 * Encode/decode swap entries and swap PTEs. Swap PTEs are all PTEs that
385 * are !pte_none() && !pte_present().
386 *
387 * 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 2 3 3
388 * 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1 2 3 4 5 6 7 8 9 0 1
389 * <------------------ offset -------------------> E < type -> 0 0
390 *
391 * E is the exclusive marker that is not stored in swap entries.
392 */
393 #define __swp_type(entry) ((entry).val & 0x1f)
394 #define __swp_offset(entry) ((entry).val >> 6)
395 #define __swp_entry(type, offset) \
396 ((swp_entry_t) { ((type) & 0x1f) | ((offset) << 6) })
397 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) >> 2 })
398 #define __swp_entry_to_pte(x) ((pte_t) { (x).val << 2 })
399
pte_swp_exclusive(pte_t pte)400 static inline bool pte_swp_exclusive(pte_t pte)
401 {
402 return pte_val(pte) & _PAGE_SWP_EXCLUSIVE;
403 }
404
pte_swp_mkexclusive(pte_t pte)405 static inline pte_t pte_swp_mkexclusive(pte_t pte)
406 {
407 pte_val(pte) |= _PAGE_SWP_EXCLUSIVE;
408 return pte;
409 }
410
pte_swp_clear_exclusive(pte_t pte)411 static inline pte_t pte_swp_clear_exclusive(pte_t pte)
412 {
413 pte_val(pte) &= ~_PAGE_SWP_EXCLUSIVE;
414 return pte;
415 }
416
417 extern unsigned long iopa(unsigned long addr);
418
419 /* Values for nocacheflag and cmode */
420 /* These are not used by the APUS kernel_map, but prevents
421 * compilation errors.
422 */
423 #define IOMAP_FULL_CACHING 0
424 #define IOMAP_NOCACHE_SER 1
425 #define IOMAP_NOCACHE_NONSER 2
426 #define IOMAP_NO_COPYBACK 3
427
428 void do_page_fault(struct pt_regs *regs, unsigned long address,
429 unsigned long error_code);
430
431 void mapin_ram(void);
432 int map_page(unsigned long va, phys_addr_t pa, int flags);
433
434 extern int mem_init_done;
435
436 asmlinkage void __init mmu_init(void);
437
438 #endif /* __ASSEMBLER__ */
439 #endif /* __KERNEL__ */
440
441 #ifndef __ASSEMBLER__
442 extern unsigned long ioremap_bot, ioremap_base;
443
444 void setup_memory(void);
445 #endif /* __ASSEMBLER__ */
446
447 #endif /* _ASM_MICROBLAZE_PGTABLE_H */
448