1 /* 2 * Copyright 2012-2023 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef DC_INTERFACE_H_ 27 #define DC_INTERFACE_H_ 28 29 #include "dc_types.h" 30 #include "dc_state.h" 31 #include "dc_plane.h" 32 #include "grph_object_defs.h" 33 #include "logger_types.h" 34 #include "hdcp_msg_types.h" 35 #include "gpio_types.h" 36 #include "link_service_types.h" 37 #include "grph_object_ctrl_defs.h" 38 #include <inc/hw/opp.h> 39 40 #include "hwss/hw_sequencer.h" 41 #include "inc/compressor.h" 42 #include "inc/hw/dmcu.h" 43 #include "dml/display_mode_lib.h" 44 45 #include "dml2/dml2_wrapper.h" 46 47 #include "dmub/inc/dmub_cmd.h" 48 49 struct abm_save_restore; 50 51 /* forward declaration */ 52 struct aux_payload; 53 struct set_config_cmd_payload; 54 struct dmub_notification; 55 56 #define DC_VER "3.2.325" 57 58 /** 59 * MAX_SURFACES - representative of the upper bound of surfaces that can be piped to a single CRTC 60 */ 61 #define MAX_SURFACES 4 62 /** 63 * MAX_PLANES - representative of the upper bound of planes that are supported by the HW 64 */ 65 #define MAX_PLANES 6 66 #define MAX_STREAMS 6 67 #define MIN_VIEWPORT_SIZE 12 68 #define MAX_NUM_EDP 2 69 #define MAX_HOST_ROUTERS_NUM 2 70 71 /* Display Core Interfaces */ 72 struct dc_versions { 73 const char *dc_ver; 74 struct dmcu_version dmcu_version; 75 }; 76 77 enum dp_protocol_version { 78 DP_VERSION_1_4 = 0, 79 DP_VERSION_2_1, 80 DP_VERSION_UNKNOWN, 81 }; 82 83 enum dc_plane_type { 84 DC_PLANE_TYPE_INVALID, 85 DC_PLANE_TYPE_DCE_RGB, 86 DC_PLANE_TYPE_DCE_UNDERLAY, 87 DC_PLANE_TYPE_DCN_UNIVERSAL, 88 }; 89 90 // Sizes defined as multiples of 64KB 91 enum det_size { 92 DET_SIZE_DEFAULT = 0, 93 DET_SIZE_192KB = 3, 94 DET_SIZE_256KB = 4, 95 DET_SIZE_320KB = 5, 96 DET_SIZE_384KB = 6 97 }; 98 99 100 struct dc_plane_cap { 101 enum dc_plane_type type; 102 uint32_t per_pixel_alpha : 1; 103 struct { 104 uint32_t argb8888 : 1; 105 uint32_t nv12 : 1; 106 uint32_t fp16 : 1; 107 uint32_t p010 : 1; 108 uint32_t ayuv : 1; 109 } pixel_format_support; 110 // max upscaling factor x1000 111 // upscaling factors are always >= 1 112 // for example, 1080p -> 8K is 4.0, or 4000 raw value 113 struct { 114 uint32_t argb8888; 115 uint32_t nv12; 116 uint32_t fp16; 117 } max_upscale_factor; 118 // max downscale factor x1000 119 // downscale factors are always <= 1 120 // for example, 8K -> 1080p is 0.25, or 250 raw value 121 struct { 122 uint32_t argb8888; 123 uint32_t nv12; 124 uint32_t fp16; 125 } max_downscale_factor; 126 // minimal width/height 127 uint32_t min_width; 128 uint32_t min_height; 129 }; 130 131 /** 132 * DOC: color-management-caps 133 * 134 * **Color management caps (DPP and MPC)** 135 * 136 * Modules/color calculates various color operations which are translated to 137 * abstracted HW. DCE 5-12 had almost no important changes, but starting with 138 * DCN1, every new generation comes with fairly major differences in color 139 * pipeline. Therefore, we abstract color pipe capabilities so modules/DM can 140 * decide mapping to HW block based on logical capabilities. 141 */ 142 143 /** 144 * struct rom_curve_caps - predefined transfer function caps for degamma and regamma 145 * @srgb: RGB color space transfer func 146 * @bt2020: BT.2020 transfer func 147 * @gamma2_2: standard gamma 148 * @pq: perceptual quantizer transfer function 149 * @hlg: hybrid log–gamma transfer function 150 */ 151 struct rom_curve_caps { 152 uint16_t srgb : 1; 153 uint16_t bt2020 : 1; 154 uint16_t gamma2_2 : 1; 155 uint16_t pq : 1; 156 uint16_t hlg : 1; 157 }; 158 159 /** 160 * struct dpp_color_caps - color pipeline capabilities for display pipe and 161 * plane blocks 162 * 163 * @dcn_arch: all DCE generations treated the same 164 * @input_lut_shared: shared with DGAM. Input LUT is different than most LUTs, 165 * just plain 256-entry lookup 166 * @icsc: input color space conversion 167 * @dgam_ram: programmable degamma LUT 168 * @post_csc: post color space conversion, before gamut remap 169 * @gamma_corr: degamma correction 170 * @hw_3d_lut: 3D LUT support. It implies a shaper LUT before. It may be shared 171 * with MPC by setting mpc:shared_3d_lut flag 172 * @ogam_ram: programmable out/blend gamma LUT 173 * @ocsc: output color space conversion 174 * @dgam_rom_for_yuv: pre-defined degamma LUT for YUV planes 175 * @dgam_rom_caps: pre-definied curve caps for degamma 1D LUT 176 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 177 * 178 * Note: hdr_mult and gamut remap (CTM) are always available in DPP (in that order) 179 */ 180 struct dpp_color_caps { 181 uint16_t dcn_arch : 1; 182 uint16_t input_lut_shared : 1; 183 uint16_t icsc : 1; 184 uint16_t dgam_ram : 1; 185 uint16_t post_csc : 1; 186 uint16_t gamma_corr : 1; 187 uint16_t hw_3d_lut : 1; 188 uint16_t ogam_ram : 1; 189 uint16_t ocsc : 1; 190 uint16_t dgam_rom_for_yuv : 1; 191 struct rom_curve_caps dgam_rom_caps; 192 struct rom_curve_caps ogam_rom_caps; 193 }; 194 195 /** 196 * struct mpc_color_caps - color pipeline capabilities for multiple pipe and 197 * plane combined blocks 198 * 199 * @gamut_remap: color transformation matrix 200 * @ogam_ram: programmable out gamma LUT 201 * @ocsc: output color space conversion matrix 202 * @num_3dluts: MPC 3D LUT; always assumes a preceding shaper LUT 203 * @shared_3d_lut: shared 3D LUT flag. Can be either DPP or MPC, but single 204 * instance 205 * @ogam_rom_caps: pre-definied curve caps for regamma 1D LUT 206 */ 207 struct mpc_color_caps { 208 uint16_t gamut_remap : 1; 209 uint16_t ogam_ram : 1; 210 uint16_t ocsc : 1; 211 uint16_t num_3dluts : 3; 212 uint16_t shared_3d_lut:1; 213 struct rom_curve_caps ogam_rom_caps; 214 }; 215 216 /** 217 * struct dc_color_caps - color pipes capabilities for DPP and MPC hw blocks 218 * @dpp: color pipes caps for DPP 219 * @mpc: color pipes caps for MPC 220 */ 221 struct dc_color_caps { 222 struct dpp_color_caps dpp; 223 struct mpc_color_caps mpc; 224 }; 225 226 struct dc_dmub_caps { 227 bool psr; 228 bool mclk_sw; 229 bool subvp_psr; 230 bool gecc_enable; 231 uint8_t fams_ver; 232 bool aux_backlight_support; 233 }; 234 235 struct dc_scl_caps { 236 bool sharpener_support; 237 }; 238 239 struct dc_caps { 240 uint32_t max_streams; 241 uint32_t max_links; 242 uint32_t max_audios; 243 uint32_t max_slave_planes; 244 uint32_t max_slave_yuv_planes; 245 uint32_t max_slave_rgb_planes; 246 uint32_t max_planes; 247 uint32_t max_downscale_ratio; 248 uint32_t i2c_speed_in_khz; 249 uint32_t i2c_speed_in_khz_hdcp; 250 uint32_t dmdata_alloc_size; 251 unsigned int max_cursor_size; 252 unsigned int max_video_width; 253 /* 254 * max video plane width that can be safely assumed to be always 255 * supported by single DPP pipe. 256 */ 257 unsigned int max_optimizable_video_width; 258 unsigned int min_horizontal_blanking_period; 259 int linear_pitch_alignment; 260 bool dcc_const_color; 261 bool dynamic_audio; 262 bool is_apu; 263 bool dual_link_dvi; 264 bool post_blend_color_processing; 265 bool force_dp_tps4_for_cp2520; 266 bool disable_dp_clk_share; 267 bool psp_setup_panel_mode; 268 bool extended_aux_timeout_support; 269 bool dmcub_support; 270 bool zstate_support; 271 bool ips_support; 272 uint32_t num_of_internal_disp; 273 enum dp_protocol_version max_dp_protocol_version; 274 unsigned int mall_size_per_mem_channel; 275 unsigned int mall_size_total; 276 unsigned int cursor_cache_size; 277 struct dc_plane_cap planes[MAX_PLANES]; 278 struct dc_color_caps color; 279 struct dc_dmub_caps dmub_caps; 280 bool dp_hpo; 281 bool dp_hdmi21_pcon_support; 282 bool edp_dsc_support; 283 bool vbios_lttpr_aware; 284 bool vbios_lttpr_enable; 285 uint32_t max_otg_num; 286 uint32_t max_cab_allocation_bytes; 287 uint32_t cache_line_size; 288 uint32_t cache_num_ways; 289 uint16_t subvp_fw_processing_delay_us; 290 uint8_t subvp_drr_max_vblank_margin_us; 291 uint16_t subvp_prefetch_end_to_mall_start_us; 292 uint8_t subvp_swath_height_margin_lines; // subvp start line must be aligned to 2 x swath height 293 uint16_t subvp_pstate_allow_width_us; 294 uint16_t subvp_vertical_int_margin_us; 295 bool seamless_odm; 296 uint32_t max_v_total; 297 bool vtotal_limited_by_fp2; 298 uint32_t max_disp_clock_khz_at_vmin; 299 uint8_t subvp_drr_vblank_start_margin_us; 300 bool cursor_not_scaled; 301 bool dcmode_power_limits_present; 302 bool sequential_ono; 303 /* Conservative limit for DCC cases which require ODM4:1 to support*/ 304 uint32_t dcc_plane_width_limit; 305 struct dc_scl_caps scl_caps; 306 }; 307 308 struct dc_bug_wa { 309 bool no_connect_phy_config; 310 bool dedcn20_305_wa; 311 bool skip_clock_update; 312 bool lt_early_cr_pattern; 313 struct { 314 uint8_t uclk : 1; 315 uint8_t fclk : 1; 316 uint8_t dcfclk : 1; 317 uint8_t dcfclk_ds: 1; 318 } clock_update_disable_mask; 319 bool skip_psr_ips_crtc_disable; 320 }; 321 struct dc_dcc_surface_param { 322 struct dc_size surface_size; 323 enum surface_pixel_format format; 324 unsigned int plane0_pitch; 325 struct dc_size plane1_size; 326 unsigned int plane1_pitch; 327 union { 328 enum swizzle_mode_values swizzle_mode; 329 enum swizzle_mode_addr3_values swizzle_mode_addr3; 330 }; 331 enum dc_scan_direction scan; 332 }; 333 334 struct dc_dcc_setting { 335 unsigned int max_compressed_blk_size; 336 unsigned int max_uncompressed_blk_size; 337 bool independent_64b_blks; 338 //These bitfields to be used starting with DCN 3.0 339 struct { 340 uint32_t dcc_256_64_64 : 1;//available in ASICs before DCN 3.0 (the worst compression case) 341 uint32_t dcc_128_128_uncontrained : 1; //available in ASICs before DCN 3.0 342 uint32_t dcc_256_128_128 : 1; //available starting with DCN 3.0 343 uint32_t dcc_256_256_unconstrained : 1; //available in ASICs before DCN 3.0 (the best compression case) 344 uint32_t dcc_256_256 : 1; //available in ASICs starting with DCN 4.0x (the best compression case) 345 uint32_t dcc_256_128 : 1; //available in ASICs starting with DCN 4.0x 346 uint32_t dcc_256_64 : 1; //available in ASICs starting with DCN 4.0x (the worst compression case) 347 } dcc_controls; 348 }; 349 350 struct dc_surface_dcc_cap { 351 union { 352 struct { 353 struct dc_dcc_setting rgb; 354 } grph; 355 356 struct { 357 struct dc_dcc_setting luma; 358 struct dc_dcc_setting chroma; 359 } video; 360 }; 361 362 bool capable; 363 bool const_color_support; 364 }; 365 366 struct dc_static_screen_params { 367 struct { 368 bool force_trigger; 369 bool cursor_update; 370 bool surface_update; 371 bool overlay_update; 372 } triggers; 373 unsigned int num_frames; 374 }; 375 376 377 /* Surface update type is used by dc_update_surfaces_and_stream 378 * The update type is determined at the very beginning of the function based 379 * on parameters passed in and decides how much programming (or updating) is 380 * going to be done during the call. 381 * 382 * UPDATE_TYPE_FAST is used for really fast updates that do not require much 383 * logical calculations or hardware register programming. This update MUST be 384 * ISR safe on windows. Currently fast update will only be used to flip surface 385 * address. 386 * 387 * UPDATE_TYPE_MED is used for slower updates which require significant hw 388 * re-programming however do not affect bandwidth consumption or clock 389 * requirements. At present, this is the level at which front end updates 390 * that do not require us to run bw_calcs happen. These are in/out transfer func 391 * updates, viewport offset changes, recout size changes and pixel depth changes. 392 * This update can be done at ISR, but we want to minimize how often this happens. 393 * 394 * UPDATE_TYPE_FULL is slow. Really slow. This requires us to recalculate our 395 * bandwidth and clocks, possibly rearrange some pipes and reprogram anything front 396 * end related. Any time viewport dimensions, recout dimensions, scaling ratios or 397 * gamma need to be adjusted or pipe needs to be turned on (or disconnected) we do 398 * a full update. This cannot be done at ISR level and should be a rare event. 399 * Unless someone is stress testing mpo enter/exit, playing with colour or adjusting 400 * underscan we don't expect to see this call at all. 401 */ 402 403 enum surface_update_type { 404 UPDATE_TYPE_FAST, /* super fast, safe to execute in isr */ 405 UPDATE_TYPE_MED, /* ISR safe, most of programming needed, no bw/clk change*/ 406 UPDATE_TYPE_FULL, /* may need to shuffle resources */ 407 }; 408 409 /* Forward declaration*/ 410 struct dc; 411 struct dc_plane_state; 412 struct dc_state; 413 414 struct dc_cap_funcs { 415 bool (*get_dcc_compression_cap)(const struct dc *dc, 416 const struct dc_dcc_surface_param *input, 417 struct dc_surface_dcc_cap *output); 418 bool (*get_subvp_en)(struct dc *dc, struct dc_state *context); 419 }; 420 421 struct link_training_settings; 422 423 union allow_lttpr_non_transparent_mode { 424 struct { 425 bool DP1_4A : 1; 426 bool DP2_0 : 1; 427 } bits; 428 unsigned char raw; 429 }; 430 431 /* Structure to hold configuration flags set by dm at dc creation. */ 432 struct dc_config { 433 bool gpu_vm_support; 434 bool disable_disp_pll_sharing; 435 bool fbc_support; 436 bool disable_fractional_pwm; 437 bool allow_seamless_boot_optimization; 438 bool seamless_boot_edp_requested; 439 bool edp_not_connected; 440 bool edp_no_power_sequencing; 441 bool force_enum_edp; 442 bool forced_clocks; 443 union allow_lttpr_non_transparent_mode allow_lttpr_non_transparent_mode; 444 bool multi_mon_pp_mclk_switch; 445 bool disable_dmcu; 446 bool enable_4to1MPC; 447 bool enable_windowed_mpo_odm; 448 bool forceHBR2CP2520; // Used for switching between test patterns TPS4 and CP2520 449 uint32_t allow_edp_hotplug_detection; 450 bool clamp_min_dcfclk; 451 uint64_t vblank_alignment_dto_params; 452 uint8_t vblank_alignment_max_frame_time_diff; 453 bool is_asymmetric_memory; 454 bool is_single_rank_dimm; 455 bool is_vmin_only_asic; 456 bool use_spl; 457 bool prefer_easf; 458 bool use_pipe_ctx_sync_logic; 459 bool ignore_dpref_ss; 460 bool enable_mipi_converter_optimization; 461 bool use_default_clock_table; 462 bool force_bios_enable_lttpr; 463 uint8_t force_bios_fixed_vs; 464 int sdpif_request_limit_words_per_umc; 465 bool dc_mode_clk_limit_support; 466 bool EnableMinDispClkODM; 467 bool enable_auto_dpm_test_logs; 468 unsigned int disable_ips; 469 unsigned int disable_ips_in_vpb; 470 bool disable_ips_in_dpms_off; 471 bool usb4_bw_alloc_support; 472 bool allow_0_dtb_clk; 473 bool use_assr_psp_message; 474 bool support_edp0_on_dp1; 475 unsigned int enable_fpo_flicker_detection; 476 bool disable_hbr_audio_dp2; 477 bool consolidated_dpia_dp_lt; 478 bool set_pipe_unlock_order; 479 bool enable_dpia_pre_training; 480 bool unify_link_enc_assignment; 481 }; 482 483 enum visual_confirm { 484 VISUAL_CONFIRM_DISABLE = 0, 485 VISUAL_CONFIRM_SURFACE = 1, 486 VISUAL_CONFIRM_HDR = 2, 487 VISUAL_CONFIRM_MPCTREE = 4, 488 VISUAL_CONFIRM_PSR = 5, 489 VISUAL_CONFIRM_SWAPCHAIN = 6, 490 VISUAL_CONFIRM_FAMS = 7, 491 VISUAL_CONFIRM_SWIZZLE = 9, 492 VISUAL_CONFIRM_REPLAY = 12, 493 VISUAL_CONFIRM_SUBVP = 14, 494 VISUAL_CONFIRM_MCLK_SWITCH = 16, 495 VISUAL_CONFIRM_FAMS2 = 19, 496 VISUAL_CONFIRM_HW_CURSOR = 20, 497 VISUAL_CONFIRM_VABC = 21, 498 VISUAL_CONFIRM_DCC = 22, 499 }; 500 501 enum dc_psr_power_opts { 502 psr_power_opt_invalid = 0x0, 503 psr_power_opt_smu_opt_static_screen = 0x1, 504 psr_power_opt_z10_static_screen = 0x10, 505 psr_power_opt_ds_disable_allow = 0x100, 506 }; 507 508 enum dml_hostvm_override_opts { 509 DML_HOSTVM_NO_OVERRIDE = 0x0, 510 DML_HOSTVM_OVERRIDE_FALSE = 0x1, 511 DML_HOSTVM_OVERRIDE_TRUE = 0x2, 512 }; 513 514 enum dc_replay_power_opts { 515 replay_power_opt_invalid = 0x0, 516 replay_power_opt_smu_opt_static_screen = 0x1, 517 replay_power_opt_z10_static_screen = 0x10, 518 }; 519 520 enum dcc_option { 521 DCC_ENABLE = 0, 522 DCC_DISABLE = 1, 523 DCC_HALF_REQ_DISALBE = 2, 524 }; 525 526 enum in_game_fams_config { 527 INGAME_FAMS_SINGLE_DISP_ENABLE, // enable in-game fams 528 INGAME_FAMS_DISABLE, // disable in-game fams 529 INGAME_FAMS_MULTI_DISP_ENABLE, //enable in-game fams for multi-display 530 INGAME_FAMS_MULTI_DISP_CLAMPED_ONLY, //enable in-game fams for multi-display only for clamped RR strategies 531 }; 532 533 /** 534 * enum pipe_split_policy - Pipe split strategy supported by DCN 535 * 536 * This enum is used to define the pipe split policy supported by DCN. By 537 * default, DC favors MPC_SPLIT_DYNAMIC. 538 */ 539 enum pipe_split_policy { 540 /** 541 * @MPC_SPLIT_DYNAMIC: DC will automatically decide how to split the 542 * pipe in order to bring the best trade-off between performance and 543 * power consumption. This is the recommended option. 544 */ 545 MPC_SPLIT_DYNAMIC = 0, 546 547 /** 548 * @MPC_SPLIT_AVOID: Avoid pipe split, which means that DC will not 549 * try any sort of split optimization. 550 */ 551 MPC_SPLIT_AVOID = 1, 552 553 /** 554 * @MPC_SPLIT_AVOID_MULT_DISP: With this option, DC will only try to 555 * optimize the pipe utilization when using a single display; if the 556 * user connects to a second display, DC will avoid pipe split. 557 */ 558 MPC_SPLIT_AVOID_MULT_DISP = 2, 559 }; 560 561 enum wm_report_mode { 562 WM_REPORT_DEFAULT = 0, 563 WM_REPORT_OVERRIDE = 1, 564 }; 565 enum dtm_pstate{ 566 dtm_level_p0 = 0,/*highest voltage*/ 567 dtm_level_p1, 568 dtm_level_p2, 569 dtm_level_p3, 570 dtm_level_p4,/*when active_display_count = 0*/ 571 }; 572 573 enum dcn_pwr_state { 574 DCN_PWR_STATE_UNKNOWN = -1, 575 DCN_PWR_STATE_MISSION_MODE = 0, 576 DCN_PWR_STATE_LOW_POWER = 3, 577 }; 578 579 enum dcn_zstate_support_state { 580 DCN_ZSTATE_SUPPORT_UNKNOWN, 581 DCN_ZSTATE_SUPPORT_ALLOW, 582 DCN_ZSTATE_SUPPORT_ALLOW_Z8_ONLY, 583 DCN_ZSTATE_SUPPORT_ALLOW_Z8_Z10_ONLY, 584 DCN_ZSTATE_SUPPORT_ALLOW_Z10_ONLY, 585 DCN_ZSTATE_SUPPORT_DISALLOW, 586 }; 587 588 /* 589 * struct dc_clocks - DC pipe clocks 590 * 591 * For any clocks that may differ per pipe only the max is stored in this 592 * structure 593 */ 594 struct dc_clocks { 595 int dispclk_khz; 596 int actual_dispclk_khz; 597 int dppclk_khz; 598 int actual_dppclk_khz; 599 int disp_dpp_voltage_level_khz; 600 int dcfclk_khz; 601 int socclk_khz; 602 int dcfclk_deep_sleep_khz; 603 int fclk_khz; 604 int phyclk_khz; 605 int dramclk_khz; 606 bool p_state_change_support; 607 enum dcn_zstate_support_state zstate_support; 608 bool dtbclk_en; 609 int ref_dtbclk_khz; 610 bool fclk_p_state_change_support; 611 enum dcn_pwr_state pwr_state; 612 /* 613 * Elements below are not compared for the purposes of 614 * optimization required 615 */ 616 bool prev_p_state_change_support; 617 bool fclk_prev_p_state_change_support; 618 int num_ways; 619 int host_router_bw_kbps[MAX_HOST_ROUTERS_NUM]; 620 621 /* 622 * @fw_based_mclk_switching 623 * 624 * DC has a mechanism that leverage the variable refresh rate to switch 625 * memory clock in cases that we have a large latency to achieve the 626 * memory clock change and a short vblank window. DC has some 627 * requirements to enable this feature, and this field describes if the 628 * system support or not such a feature. 629 */ 630 bool fw_based_mclk_switching; 631 bool fw_based_mclk_switching_shut_down; 632 int prev_num_ways; 633 enum dtm_pstate dtm_level; 634 int max_supported_dppclk_khz; 635 int max_supported_dispclk_khz; 636 int bw_dppclk_khz; /*a copy of dppclk_khz*/ 637 int bw_dispclk_khz; 638 int idle_dramclk_khz; 639 int idle_fclk_khz; 640 int subvp_prefetch_dramclk_khz; 641 int subvp_prefetch_fclk_khz; 642 }; 643 644 struct dc_bw_validation_profile { 645 bool enable; 646 647 unsigned long long total_ticks; 648 unsigned long long voltage_level_ticks; 649 unsigned long long watermark_ticks; 650 unsigned long long rq_dlg_ticks; 651 652 unsigned long long total_count; 653 unsigned long long skip_fast_count; 654 unsigned long long skip_pass_count; 655 unsigned long long skip_fail_count; 656 }; 657 658 #define BW_VAL_TRACE_SETUP() \ 659 unsigned long long end_tick = 0; \ 660 unsigned long long voltage_level_tick = 0; \ 661 unsigned long long watermark_tick = 0; \ 662 unsigned long long start_tick = dc->debug.bw_val_profile.enable ? \ 663 dm_get_timestamp(dc->ctx) : 0 664 665 #define BW_VAL_TRACE_COUNT() \ 666 if (dc->debug.bw_val_profile.enable) \ 667 dc->debug.bw_val_profile.total_count++ 668 669 #define BW_VAL_TRACE_SKIP(status) \ 670 if (dc->debug.bw_val_profile.enable) { \ 671 if (!voltage_level_tick) \ 672 voltage_level_tick = dm_get_timestamp(dc->ctx); \ 673 dc->debug.bw_val_profile.skip_ ## status ## _count++; \ 674 } 675 676 #define BW_VAL_TRACE_END_VOLTAGE_LEVEL() \ 677 if (dc->debug.bw_val_profile.enable) \ 678 voltage_level_tick = dm_get_timestamp(dc->ctx) 679 680 #define BW_VAL_TRACE_END_WATERMARKS() \ 681 if (dc->debug.bw_val_profile.enable) \ 682 watermark_tick = dm_get_timestamp(dc->ctx) 683 684 #define BW_VAL_TRACE_FINISH() \ 685 if (dc->debug.bw_val_profile.enable) { \ 686 end_tick = dm_get_timestamp(dc->ctx); \ 687 dc->debug.bw_val_profile.total_ticks += end_tick - start_tick; \ 688 dc->debug.bw_val_profile.voltage_level_ticks += voltage_level_tick - start_tick; \ 689 if (watermark_tick) { \ 690 dc->debug.bw_val_profile.watermark_ticks += watermark_tick - voltage_level_tick; \ 691 dc->debug.bw_val_profile.rq_dlg_ticks += end_tick - watermark_tick; \ 692 } \ 693 } 694 695 union mem_low_power_enable_options { 696 struct { 697 bool vga: 1; 698 bool i2c: 1; 699 bool dmcu: 1; 700 bool dscl: 1; 701 bool cm: 1; 702 bool mpc: 1; 703 bool optc: 1; 704 bool vpg: 1; 705 bool afmt: 1; 706 } bits; 707 uint32_t u32All; 708 }; 709 710 union root_clock_optimization_options { 711 struct { 712 bool dpp: 1; 713 bool dsc: 1; 714 bool hdmistream: 1; 715 bool hdmichar: 1; 716 bool dpstream: 1; 717 bool symclk32_se: 1; 718 bool symclk32_le: 1; 719 bool symclk_fe: 1; 720 bool physymclk: 1; 721 bool dpiasymclk: 1; 722 uint32_t reserved: 22; 723 } bits; 724 uint32_t u32All; 725 }; 726 727 union fine_grain_clock_gating_enable_options { 728 struct { 729 bool dccg_global_fgcg_rep : 1; /* Global fine grain clock gating of repeaters */ 730 bool dchub : 1; /* Display controller hub */ 731 bool dchubbub : 1; 732 bool dpp : 1; /* Display pipes and planes */ 733 bool opp : 1; /* Output pixel processing */ 734 bool optc : 1; /* Output pipe timing combiner */ 735 bool dio : 1; /* Display output */ 736 bool dwb : 1; /* Display writeback */ 737 bool mmhubbub : 1; /* Multimedia hub */ 738 bool dmu : 1; /* Display core management unit */ 739 bool az : 1; /* Azalia */ 740 bool dchvm : 1; 741 bool dsc : 1; /* Display stream compression */ 742 743 uint32_t reserved : 19; 744 } bits; 745 uint32_t u32All; 746 }; 747 748 enum pg_hw_pipe_resources { 749 PG_HUBP = 0, 750 PG_DPP, 751 PG_DSC, 752 PG_MPCC, 753 PG_OPP, 754 PG_OPTC, 755 PG_DPSTREAM, 756 PG_HDMISTREAM, 757 PG_PHYSYMCLK, 758 PG_HW_PIPE_RESOURCES_NUM_ELEMENT 759 }; 760 761 enum pg_hw_resources { 762 PG_DCCG = 0, 763 PG_DCIO, 764 PG_DIO, 765 PG_DCHUBBUB, 766 PG_DCHVM, 767 PG_DWB, 768 PG_HPO, 769 PG_HW_RESOURCES_NUM_ELEMENT 770 }; 771 772 struct pg_block_update { 773 bool pg_pipe_res_update[PG_HW_PIPE_RESOURCES_NUM_ELEMENT][MAX_PIPES]; 774 bool pg_res_update[PG_HW_RESOURCES_NUM_ELEMENT]; 775 }; 776 777 union dpia_debug_options { 778 struct { 779 uint32_t disable_dpia:1; /* bit 0 */ 780 uint32_t force_non_lttpr:1; /* bit 1 */ 781 uint32_t extend_aux_rd_interval:1; /* bit 2 */ 782 uint32_t disable_mst_dsc_work_around:1; /* bit 3 */ 783 uint32_t enable_force_tbt3_work_around:1; /* bit 4 */ 784 uint32_t disable_usb4_pm_support:1; /* bit 5 */ 785 uint32_t enable_consolidated_dpia_dp_lt:1; /* bit 6 */ 786 uint32_t enable_dpia_pre_training:1; /* bit 7 */ 787 uint32_t unify_link_enc_assignment:1; /* bit 8 */ 788 uint32_t reserved:24; 789 } bits; 790 uint32_t raw; 791 }; 792 793 /* AUX wake work around options 794 * 0: enable/disable work around 795 * 1: use default timeout LINK_AUX_WAKE_TIMEOUT_MS 796 * 15-2: reserved 797 * 31-16: timeout in ms 798 */ 799 union aux_wake_wa_options { 800 struct { 801 uint32_t enable_wa : 1; 802 uint32_t use_default_timeout : 1; 803 uint32_t rsvd: 14; 804 uint32_t timeout_ms : 16; 805 } bits; 806 uint32_t raw; 807 }; 808 809 struct dc_debug_data { 810 uint32_t ltFailCount; 811 uint32_t i2cErrorCount; 812 uint32_t auxErrorCount; 813 }; 814 815 struct dc_phy_addr_space_config { 816 struct { 817 uint64_t start_addr; 818 uint64_t end_addr; 819 uint64_t fb_top; 820 uint64_t fb_offset; 821 uint64_t fb_base; 822 uint64_t agp_top; 823 uint64_t agp_bot; 824 uint64_t agp_base; 825 } system_aperture; 826 827 struct { 828 uint64_t page_table_start_addr; 829 uint64_t page_table_end_addr; 830 uint64_t page_table_base_addr; 831 bool base_addr_is_mc_addr; 832 } gart_config; 833 834 bool valid; 835 bool is_hvm_enabled; 836 uint64_t page_table_default_page_addr; 837 }; 838 839 struct dc_virtual_addr_space_config { 840 uint64_t page_table_base_addr; 841 uint64_t page_table_start_addr; 842 uint64_t page_table_end_addr; 843 uint32_t page_table_block_size_in_bytes; 844 uint8_t page_table_depth; // 1 = 1 level, 2 = 2 level, etc. 0 = invalid 845 }; 846 847 struct dc_bounding_box_overrides { 848 int sr_exit_time_ns; 849 int sr_enter_plus_exit_time_ns; 850 int sr_exit_z8_time_ns; 851 int sr_enter_plus_exit_z8_time_ns; 852 int urgent_latency_ns; 853 int percent_of_ideal_drambw; 854 int dram_clock_change_latency_ns; 855 int dummy_clock_change_latency_ns; 856 int fclk_clock_change_latency_ns; 857 /* This forces a hard min on the DCFCLK we use 858 * for DML. Unlike the debug option for forcing 859 * DCFCLK, this override affects watermark calculations 860 */ 861 int min_dcfclk_mhz; 862 }; 863 864 struct dc_state; 865 struct resource_pool; 866 struct dce_hwseq; 867 struct link_service; 868 869 /* 870 * struct dc_debug_options - DC debug struct 871 * 872 * This struct provides a simple mechanism for developers to change some 873 * configurations, enable/disable features, and activate extra debug options. 874 * This can be very handy to narrow down whether some specific feature is 875 * causing an issue or not. 876 */ 877 struct dc_debug_options { 878 bool native422_support; 879 bool disable_dsc; 880 enum visual_confirm visual_confirm; 881 int visual_confirm_rect_height; 882 883 bool sanity_checks; 884 bool max_disp_clk; 885 bool surface_trace; 886 bool clock_trace; 887 bool validation_trace; 888 bool bandwidth_calcs_trace; 889 int max_downscale_src_width; 890 891 /* stutter efficiency related */ 892 bool disable_stutter; 893 bool use_max_lb; 894 enum dcc_option disable_dcc; 895 896 /* 897 * @pipe_split_policy: Define which pipe split policy is used by the 898 * display core. 899 */ 900 enum pipe_split_policy pipe_split_policy; 901 bool force_single_disp_pipe_split; 902 bool voltage_align_fclk; 903 bool disable_min_fclk; 904 905 bool disable_dfs_bypass; 906 bool disable_dpp_power_gate; 907 bool disable_hubp_power_gate; 908 bool disable_dsc_power_gate; 909 bool disable_optc_power_gate; 910 bool disable_hpo_power_gate; 911 int dsc_min_slice_height_override; 912 int dsc_bpp_increment_div; 913 bool disable_pplib_wm_range; 914 enum wm_report_mode pplib_wm_report_mode; 915 unsigned int min_disp_clk_khz; 916 unsigned int min_dpp_clk_khz; 917 unsigned int min_dram_clk_khz; 918 int sr_exit_time_dpm0_ns; 919 int sr_enter_plus_exit_time_dpm0_ns; 920 int sr_exit_time_ns; 921 int sr_enter_plus_exit_time_ns; 922 int sr_exit_z8_time_ns; 923 int sr_enter_plus_exit_z8_time_ns; 924 int urgent_latency_ns; 925 uint32_t underflow_assert_delay_us; 926 int percent_of_ideal_drambw; 927 int dram_clock_change_latency_ns; 928 bool optimized_watermark; 929 int always_scale; 930 bool disable_pplib_clock_request; 931 bool disable_clock_gate; 932 bool disable_mem_low_power; 933 bool pstate_enabled; 934 bool disable_dmcu; 935 bool force_abm_enable; 936 bool disable_stereo_support; 937 bool vsr_support; 938 bool performance_trace; 939 bool az_endpoint_mute_only; 940 bool always_use_regamma; 941 bool recovery_enabled; 942 bool avoid_vbios_exec_table; 943 bool scl_reset_length10; 944 bool hdmi20_disable; 945 bool skip_detection_link_training; 946 uint32_t edid_read_retry_times; 947 unsigned int force_odm_combine; //bit vector based on otg inst 948 unsigned int seamless_boot_odm_combine; 949 unsigned int force_odm_combine_4to1; //bit vector based on otg inst 950 int minimum_z8_residency_time; 951 int minimum_z10_residency_time; 952 bool disable_z9_mpc; 953 unsigned int force_fclk_khz; 954 bool enable_tri_buf; 955 bool ips_disallow_entry; 956 bool dmub_offload_enabled; 957 bool dmcub_emulation; 958 bool disable_idle_power_optimizations; 959 unsigned int mall_size_override; 960 unsigned int mall_additional_timer_percent; 961 bool mall_error_as_fatal; 962 bool dmub_command_table; /* for testing only */ 963 struct dc_bw_validation_profile bw_val_profile; 964 bool disable_fec; 965 bool disable_48mhz_pwrdwn; 966 /* This forces a hard min on the DCFCLK requested to SMU/PP 967 * watermarks are not affected. 968 */ 969 unsigned int force_min_dcfclk_mhz; 970 int dwb_fi_phase; 971 bool disable_timing_sync; 972 bool cm_in_bypass; 973 int force_clock_mode;/*every mode change.*/ 974 975 bool disable_dram_clock_change_vactive_support; 976 bool validate_dml_output; 977 bool enable_dmcub_surface_flip; 978 bool usbc_combo_phy_reset_wa; 979 bool enable_dram_clock_change_one_display_vactive; 980 /* TODO - remove once tested */ 981 bool legacy_dp2_lt; 982 bool set_mst_en_for_sst; 983 bool disable_uhbr; 984 bool force_dp2_lt_fallback_method; 985 bool ignore_cable_id; 986 union mem_low_power_enable_options enable_mem_low_power; 987 union root_clock_optimization_options root_clock_optimization; 988 union fine_grain_clock_gating_enable_options enable_fine_grain_clock_gating; 989 bool hpo_optimization; 990 bool force_vblank_alignment; 991 992 /* Enable dmub aux for legacy ddc */ 993 bool enable_dmub_aux_for_legacy_ddc; 994 bool disable_fams; 995 enum in_game_fams_config disable_fams_gaming; 996 /* FEC/PSR1 sequence enable delay in 100us */ 997 uint8_t fec_enable_delay_in100us; 998 bool enable_driver_sequence_debug; 999 enum det_size crb_alloc_policy; 1000 int crb_alloc_policy_min_disp_count; 1001 bool disable_z10; 1002 bool enable_z9_disable_interface; 1003 bool psr_skip_crtc_disable; 1004 uint32_t ips_skip_crtc_disable_mask; 1005 union dpia_debug_options dpia_debug; 1006 bool disable_fixed_vs_aux_timeout_wa; 1007 uint32_t fixed_vs_aux_delay_config_wa; 1008 bool force_disable_subvp; 1009 bool force_subvp_mclk_switch; 1010 bool allow_sw_cursor_fallback; 1011 unsigned int force_subvp_num_ways; 1012 unsigned int force_mall_ss_num_ways; 1013 bool alloc_extra_way_for_cursor; 1014 uint32_t subvp_extra_lines; 1015 bool force_usr_allow; 1016 /* uses value at boot and disables switch */ 1017 bool disable_dtb_ref_clk_switch; 1018 bool extended_blank_optimization; 1019 union aux_wake_wa_options aux_wake_wa; 1020 uint32_t mst_start_top_delay; 1021 uint8_t psr_power_use_phy_fsm; 1022 enum dml_hostvm_override_opts dml_hostvm_override; 1023 bool dml_disallow_alternate_prefetch_modes; 1024 bool use_legacy_soc_bb_mechanism; 1025 bool exit_idle_opt_for_cursor_updates; 1026 bool using_dml2; 1027 bool enable_single_display_2to1_odm_policy; 1028 bool enable_double_buffered_dsc_pg_support; 1029 bool enable_dp_dig_pixel_rate_div_policy; 1030 bool using_dml21; 1031 enum lttpr_mode lttpr_mode_override; 1032 unsigned int dsc_delay_factor_wa_x1000; 1033 unsigned int min_prefetch_in_strobe_ns; 1034 bool disable_unbounded_requesting; 1035 bool dig_fifo_off_in_blank; 1036 bool override_dispclk_programming; 1037 bool otg_crc_db; 1038 bool disallow_dispclk_dppclk_ds; 1039 bool disable_fpo_optimizations; 1040 bool support_eDP1_5; 1041 uint32_t fpo_vactive_margin_us; 1042 bool disable_fpo_vactive; 1043 bool disable_boot_optimizations; 1044 bool override_odm_optimization; 1045 bool minimize_dispclk_using_odm; 1046 bool disable_subvp_high_refresh; 1047 bool disable_dp_plus_plus_wa; 1048 uint32_t fpo_vactive_min_active_margin_us; 1049 uint32_t fpo_vactive_max_blank_us; 1050 bool enable_hpo_pg_support; 1051 bool enable_legacy_fast_update; 1052 bool disable_dc_mode_overwrite; 1053 bool replay_skip_crtc_disabled; 1054 bool ignore_pg;/*do nothing, let pmfw control it*/ 1055 bool psp_disabled_wa; 1056 unsigned int ips2_eval_delay_us; 1057 unsigned int ips2_entry_delay_us; 1058 bool optimize_ips_handshake; 1059 bool disable_dmub_reallow_idle; 1060 bool disable_timeout; 1061 bool disable_extblankadj; 1062 bool enable_idle_reg_checks; 1063 unsigned int static_screen_wait_frames; 1064 uint32_t pwm_freq; 1065 bool force_chroma_subsampling_1tap; 1066 unsigned int dcc_meta_propagation_delay_us; 1067 bool disable_422_left_edge_pixel; 1068 bool dml21_force_pstate_method; 1069 uint32_t dml21_force_pstate_method_values[MAX_PIPES]; 1070 uint32_t dml21_disable_pstate_method_mask; 1071 union fw_assisted_mclk_switch_version fams_version; 1072 union dmub_fams2_global_feature_config fams2_config; 1073 unsigned int force_cositing; 1074 unsigned int disable_spl; 1075 unsigned int force_easf; 1076 unsigned int force_sharpness; 1077 unsigned int force_sharpness_level; 1078 unsigned int force_lls; 1079 bool notify_dpia_hr_bw; 1080 bool enable_ips_visual_confirm; 1081 unsigned int sharpen_policy; 1082 unsigned int scale_to_sharpness_policy; 1083 bool skip_full_updated_if_possible; 1084 unsigned int enable_oled_edp_power_up_opt; 1085 bool enable_hblank_borrow; 1086 bool force_subvp_df_throttle; 1087 uint32_t acpi_transition_bitmasks[MAX_PIPES]; 1088 }; 1089 1090 1091 /* Generic structure that can be used to query properties of DC. More fields 1092 * can be added as required. 1093 */ 1094 struct dc_current_properties { 1095 unsigned int cursor_size_limit; 1096 }; 1097 1098 enum frame_buffer_mode { 1099 FRAME_BUFFER_MODE_LOCAL_ONLY = 0, 1100 FRAME_BUFFER_MODE_ZFB_ONLY, 1101 FRAME_BUFFER_MODE_MIXED_ZFB_AND_LOCAL, 1102 } ; 1103 1104 struct dchub_init_data { 1105 int64_t zfb_phys_addr_base; 1106 int64_t zfb_mc_base_addr; 1107 uint64_t zfb_size_in_byte; 1108 enum frame_buffer_mode fb_mode; 1109 bool dchub_initialzied; 1110 bool dchub_info_valid; 1111 }; 1112 1113 struct dml2_soc_bb; 1114 1115 struct dc_init_data { 1116 struct hw_asic_id asic_id; 1117 void *driver; /* ctx */ 1118 struct cgs_device *cgs_device; 1119 struct dc_bounding_box_overrides bb_overrides; 1120 1121 int num_virtual_links; 1122 /* 1123 * If 'vbios_override' not NULL, it will be called instead 1124 * of the real VBIOS. Intended use is Diagnostics on FPGA. 1125 */ 1126 struct dc_bios *vbios_override; 1127 enum dce_environment dce_environment; 1128 1129 struct dmub_offload_funcs *dmub_if; 1130 struct dc_reg_helper_state *dmub_offload; 1131 1132 struct dc_config flags; 1133 uint64_t log_mask; 1134 1135 struct dpcd_vendor_signature vendor_signature; 1136 bool force_smu_not_present; 1137 /* 1138 * IP offset for run time initializaion of register addresses 1139 * 1140 * DCN3.5+ will fail dc_create() if these fields are null for them. They are 1141 * applicable starting with DCN32/321 and are not used for ASICs upstreamed 1142 * before them. 1143 */ 1144 uint32_t *dcn_reg_offsets; 1145 uint32_t *nbio_reg_offsets; 1146 uint32_t *clk_reg_offsets; 1147 struct dml2_soc_bb *bb_from_dmub; 1148 }; 1149 1150 struct dc_callback_init { 1151 struct cp_psp cp_psp; 1152 }; 1153 1154 struct dc *dc_create(const struct dc_init_data *init_params); 1155 void dc_hardware_init(struct dc *dc); 1156 1157 int dc_get_vmid_use_vector(struct dc *dc); 1158 void dc_setup_vm_context(struct dc *dc, struct dc_virtual_addr_space_config *va_config, int vmid); 1159 /* Returns the number of vmids supported */ 1160 int dc_setup_system_context(struct dc *dc, struct dc_phy_addr_space_config *pa_config); 1161 void dc_init_callbacks(struct dc *dc, 1162 const struct dc_callback_init *init_params); 1163 void dc_deinit_callbacks(struct dc *dc); 1164 void dc_destroy(struct dc **dc); 1165 1166 /* Surface Interfaces */ 1167 1168 enum { 1169 TRANSFER_FUNC_POINTS = 1025 1170 }; 1171 1172 struct dc_hdr_static_metadata { 1173 /* display chromaticities and white point in units of 0.00001 */ 1174 unsigned int chromaticity_green_x; 1175 unsigned int chromaticity_green_y; 1176 unsigned int chromaticity_blue_x; 1177 unsigned int chromaticity_blue_y; 1178 unsigned int chromaticity_red_x; 1179 unsigned int chromaticity_red_y; 1180 unsigned int chromaticity_white_point_x; 1181 unsigned int chromaticity_white_point_y; 1182 1183 uint32_t min_luminance; 1184 uint32_t max_luminance; 1185 uint32_t maximum_content_light_level; 1186 uint32_t maximum_frame_average_light_level; 1187 }; 1188 1189 enum dc_transfer_func_type { 1190 TF_TYPE_PREDEFINED, 1191 TF_TYPE_DISTRIBUTED_POINTS, 1192 TF_TYPE_BYPASS, 1193 TF_TYPE_HWPWL 1194 }; 1195 1196 struct dc_transfer_func_distributed_points { 1197 struct fixed31_32 red[TRANSFER_FUNC_POINTS]; 1198 struct fixed31_32 green[TRANSFER_FUNC_POINTS]; 1199 struct fixed31_32 blue[TRANSFER_FUNC_POINTS]; 1200 1201 uint16_t end_exponent; 1202 uint16_t x_point_at_y1_red; 1203 uint16_t x_point_at_y1_green; 1204 uint16_t x_point_at_y1_blue; 1205 }; 1206 1207 enum dc_transfer_func_predefined { 1208 TRANSFER_FUNCTION_SRGB, 1209 TRANSFER_FUNCTION_BT709, 1210 TRANSFER_FUNCTION_PQ, 1211 TRANSFER_FUNCTION_LINEAR, 1212 TRANSFER_FUNCTION_UNITY, 1213 TRANSFER_FUNCTION_HLG, 1214 TRANSFER_FUNCTION_HLG12, 1215 TRANSFER_FUNCTION_GAMMA22, 1216 TRANSFER_FUNCTION_GAMMA24, 1217 TRANSFER_FUNCTION_GAMMA26 1218 }; 1219 1220 1221 struct dc_transfer_func { 1222 struct kref refcount; 1223 enum dc_transfer_func_type type; 1224 enum dc_transfer_func_predefined tf; 1225 /* FP16 1.0 reference level in nits, default is 80 nits, only for PQ*/ 1226 uint32_t sdr_ref_white_level; 1227 union { 1228 struct pwl_params pwl; 1229 struct dc_transfer_func_distributed_points tf_pts; 1230 }; 1231 }; 1232 1233 1234 union dc_3dlut_state { 1235 struct { 1236 uint32_t initialized:1; /*if 3dlut is went through color module for initialization */ 1237 uint32_t rmu_idx_valid:1; /*if mux settings are valid*/ 1238 uint32_t rmu_mux_num:3; /*index of mux to use*/ 1239 uint32_t mpc_rmu0_mux:4; /*select mpcc on mux, one of the following : mpcc0, mpcc1, mpcc2, mpcc3*/ 1240 uint32_t mpc_rmu1_mux:4; 1241 uint32_t mpc_rmu2_mux:4; 1242 uint32_t reserved:15; 1243 } bits; 1244 uint32_t raw; 1245 }; 1246 1247 1248 struct dc_3dlut { 1249 struct kref refcount; 1250 struct tetrahedral_params lut_3d; 1251 struct fixed31_32 hdr_multiplier; 1252 union dc_3dlut_state state; 1253 }; 1254 /* 1255 * This structure is filled in by dc_surface_get_status and contains 1256 * the last requested address and the currently active address so the called 1257 * can determine if there are any outstanding flips 1258 */ 1259 struct dc_plane_status { 1260 struct dc_plane_address requested_address; 1261 struct dc_plane_address current_address; 1262 bool is_flip_pending; 1263 bool is_right_eye; 1264 }; 1265 1266 union surface_update_flags { 1267 1268 struct { 1269 uint32_t addr_update:1; 1270 /* Medium updates */ 1271 uint32_t dcc_change:1; 1272 uint32_t color_space_change:1; 1273 uint32_t horizontal_mirror_change:1; 1274 uint32_t per_pixel_alpha_change:1; 1275 uint32_t global_alpha_change:1; 1276 uint32_t hdr_mult:1; 1277 uint32_t rotation_change:1; 1278 uint32_t swizzle_change:1; 1279 uint32_t scaling_change:1; 1280 uint32_t position_change:1; 1281 uint32_t in_transfer_func_change:1; 1282 uint32_t input_csc_change:1; 1283 uint32_t coeff_reduction_change:1; 1284 uint32_t output_tf_change:1; 1285 uint32_t pixel_format_change:1; 1286 uint32_t plane_size_change:1; 1287 uint32_t gamut_remap_change:1; 1288 1289 /* Full updates */ 1290 uint32_t new_plane:1; 1291 uint32_t bpp_change:1; 1292 uint32_t gamma_change:1; 1293 uint32_t bandwidth_change:1; 1294 uint32_t clock_change:1; 1295 uint32_t stereo_format_change:1; 1296 uint32_t lut_3d:1; 1297 uint32_t tmz_changed:1; 1298 uint32_t mcm_transfer_function_enable_change:1; /* disable or enable MCM transfer func */ 1299 uint32_t full_update:1; 1300 uint32_t sdr_white_level_nits:1; 1301 } bits; 1302 1303 uint32_t raw; 1304 }; 1305 1306 #define DC_REMOVE_PLANE_POINTERS 1 1307 1308 struct dc_plane_state { 1309 struct dc_plane_address address; 1310 struct dc_plane_flip_time time; 1311 bool triplebuffer_flips; 1312 struct scaling_taps scaling_quality; 1313 struct rect src_rect; 1314 struct rect dst_rect; 1315 struct rect clip_rect; 1316 1317 struct plane_size plane_size; 1318 struct dc_tiling_info tiling_info; 1319 1320 struct dc_plane_dcc_param dcc; 1321 1322 struct dc_gamma gamma_correction; 1323 struct dc_transfer_func in_transfer_func; 1324 struct dc_bias_and_scale bias_and_scale; 1325 struct dc_csc_transform input_csc_color_matrix; 1326 struct fixed31_32 coeff_reduction_factor; 1327 struct fixed31_32 hdr_mult; 1328 struct colorspace_transform gamut_remap_matrix; 1329 1330 // TODO: No longer used, remove 1331 struct dc_hdr_static_metadata hdr_static_ctx; 1332 1333 enum dc_color_space color_space; 1334 1335 struct dc_3dlut lut3d_func; 1336 struct dc_transfer_func in_shaper_func; 1337 struct dc_transfer_func blend_tf; 1338 1339 struct dc_transfer_func *gamcor_tf; 1340 enum surface_pixel_format format; 1341 enum dc_rotation_angle rotation; 1342 enum plane_stereo_format stereo_format; 1343 1344 bool is_tiling_rotated; 1345 bool per_pixel_alpha; 1346 bool pre_multiplied_alpha; 1347 bool global_alpha; 1348 int global_alpha_value; 1349 bool visible; 1350 bool flip_immediate; 1351 bool horizontal_mirror; 1352 int layer_index; 1353 1354 union surface_update_flags update_flags; 1355 bool flip_int_enabled; 1356 bool skip_manual_trigger; 1357 1358 /* private to DC core */ 1359 struct dc_plane_status status; 1360 struct dc_context *ctx; 1361 1362 /* HACK: Workaround for forcing full reprogramming under some conditions */ 1363 bool force_full_update; 1364 1365 bool is_phantom; // TODO: Change mall_stream_config into mall_plane_config instead 1366 1367 /* private to dc_surface.c */ 1368 enum dc_irq_source irq_source; 1369 struct kref refcount; 1370 struct tg_color visual_confirm_color; 1371 1372 bool is_statically_allocated; 1373 enum chroma_cositing cositing; 1374 enum dc_cm2_shaper_3dlut_setting mcm_shaper_3dlut_setting; 1375 bool mcm_lut1d_enable; 1376 struct dc_cm2_func_luts mcm_luts; 1377 bool lut_bank_a; 1378 enum mpcc_movable_cm_location mcm_location; 1379 struct dc_csc_transform cursor_csc_color_matrix; 1380 bool adaptive_sharpness_en; 1381 int adaptive_sharpness_policy; 1382 int sharpness_level; 1383 enum linear_light_scaling linear_light_scaling; 1384 unsigned int sdr_white_level_nits; 1385 }; 1386 1387 struct dc_plane_info { 1388 struct plane_size plane_size; 1389 struct dc_tiling_info tiling_info; 1390 struct dc_plane_dcc_param dcc; 1391 enum surface_pixel_format format; 1392 enum dc_rotation_angle rotation; 1393 enum plane_stereo_format stereo_format; 1394 enum dc_color_space color_space; 1395 bool horizontal_mirror; 1396 bool visible; 1397 bool per_pixel_alpha; 1398 bool pre_multiplied_alpha; 1399 bool global_alpha; 1400 int global_alpha_value; 1401 bool input_csc_enabled; 1402 int layer_index; 1403 enum chroma_cositing cositing; 1404 }; 1405 1406 #include "dc_stream.h" 1407 1408 struct dc_scratch_space { 1409 /* used to temporarily backup plane states of a stream during 1410 * dc update. The reason is that plane states are overwritten 1411 * with surface updates in dc update. Once they are overwritten 1412 * current state is no longer valid. We want to temporarily 1413 * store current value in plane states so we can still recover 1414 * a valid current state during dc update. 1415 */ 1416 struct dc_plane_state plane_states[MAX_SURFACES]; 1417 1418 struct dc_stream_state stream_state; 1419 }; 1420 1421 struct dc { 1422 struct dc_debug_options debug; 1423 struct dc_versions versions; 1424 struct dc_caps caps; 1425 struct dc_cap_funcs cap_funcs; 1426 struct dc_config config; 1427 struct dc_bounding_box_overrides bb_overrides; 1428 struct dc_bug_wa work_arounds; 1429 struct dc_context *ctx; 1430 struct dc_phy_addr_space_config vm_pa_config; 1431 1432 uint8_t link_count; 1433 struct dc_link *links[MAX_LINKS]; 1434 struct link_service *link_srv; 1435 1436 struct dc_state *current_state; 1437 struct resource_pool *res_pool; 1438 1439 struct clk_mgr *clk_mgr; 1440 1441 /* Display Engine Clock levels */ 1442 struct dm_pp_clock_levels sclk_lvls; 1443 1444 /* Inputs into BW and WM calculations. */ 1445 struct bw_calcs_dceip *bw_dceip; 1446 struct bw_calcs_vbios *bw_vbios; 1447 struct dcn_soc_bounding_box *dcn_soc; 1448 struct dcn_ip_params *dcn_ip; 1449 struct display_mode_lib dml; 1450 1451 /* HW functions */ 1452 struct hw_sequencer_funcs hwss; 1453 struct dce_hwseq *hwseq; 1454 1455 /* Require to optimize clocks and bandwidth for added/removed planes */ 1456 bool optimized_required; 1457 bool wm_optimized_required; 1458 bool idle_optimizations_allowed; 1459 bool enable_c20_dtm_b0; 1460 1461 /* Require to maintain clocks and bandwidth for UEFI enabled HW */ 1462 1463 /* FBC compressor */ 1464 struct compressor *fbc_compressor; 1465 1466 struct dc_debug_data debug_data; 1467 struct dpcd_vendor_signature vendor_signature; 1468 1469 const char *build_id; 1470 struct vm_helper *vm_helper; 1471 1472 uint32_t *dcn_reg_offsets; 1473 uint32_t *nbio_reg_offsets; 1474 uint32_t *clk_reg_offsets; 1475 1476 /* Scratch memory */ 1477 struct { 1478 struct { 1479 /* 1480 * For matching clock_limits table in driver with table 1481 * from PMFW. 1482 */ 1483 struct _vcs_dpi_voltage_scaling_st clock_limits[DC__VOLTAGE_STATES]; 1484 } update_bw_bounding_box; 1485 struct dc_scratch_space current_state; 1486 struct dc_scratch_space new_state; 1487 struct dc_stream_state temp_stream; // Used so we don't need to allocate stream on the stack 1488 bool pipes_to_unlock_first[MAX_PIPES]; /* Any of the pipes indicated here should be unlocked first */ 1489 } scratch; 1490 1491 struct dml2_configuration_options dml2_options; 1492 struct dml2_configuration_options dml2_tmp; 1493 enum dc_acpi_cm_power_state power_state; 1494 1495 }; 1496 1497 struct dc_scaling_info { 1498 struct rect src_rect; 1499 struct rect dst_rect; 1500 struct rect clip_rect; 1501 struct scaling_taps scaling_quality; 1502 }; 1503 1504 struct dc_fast_update { 1505 const struct dc_flip_addrs *flip_addr; 1506 const struct dc_gamma *gamma; 1507 const struct colorspace_transform *gamut_remap_matrix; 1508 const struct dc_csc_transform *input_csc_color_matrix; 1509 const struct fixed31_32 *coeff_reduction_factor; 1510 struct dc_transfer_func *out_transfer_func; 1511 struct dc_csc_transform *output_csc_transform; 1512 const struct dc_csc_transform *cursor_csc_color_matrix; 1513 }; 1514 1515 struct dc_surface_update { 1516 struct dc_plane_state *surface; 1517 1518 /* isr safe update parameters. null means no updates */ 1519 const struct dc_flip_addrs *flip_addr; 1520 const struct dc_plane_info *plane_info; 1521 const struct dc_scaling_info *scaling_info; 1522 struct fixed31_32 hdr_mult; 1523 /* following updates require alloc/sleep/spin that is not isr safe, 1524 * null means no updates 1525 */ 1526 const struct dc_gamma *gamma; 1527 const struct dc_transfer_func *in_transfer_func; 1528 1529 const struct dc_csc_transform *input_csc_color_matrix; 1530 const struct fixed31_32 *coeff_reduction_factor; 1531 const struct dc_transfer_func *func_shaper; 1532 const struct dc_3dlut *lut3d_func; 1533 const struct dc_transfer_func *blend_tf; 1534 const struct colorspace_transform *gamut_remap_matrix; 1535 /* 1536 * Color Transformations for pre-blend MCM (Shaper, 3DLUT, 1DLUT) 1537 * 1538 * change cm2_params.component_settings: Full update 1539 * change cm2_params.cm2_luts: Fast update 1540 */ 1541 const struct dc_cm2_parameters *cm2_params; 1542 const struct dc_csc_transform *cursor_csc_color_matrix; 1543 unsigned int sdr_white_level_nits; 1544 struct dc_bias_and_scale bias_and_scale; 1545 }; 1546 1547 /* 1548 * Create a new surface with default parameters; 1549 */ 1550 void dc_gamma_retain(struct dc_gamma *dc_gamma); 1551 void dc_gamma_release(struct dc_gamma **dc_gamma); 1552 struct dc_gamma *dc_create_gamma(void); 1553 1554 void dc_transfer_func_retain(struct dc_transfer_func *dc_tf); 1555 void dc_transfer_func_release(struct dc_transfer_func *dc_tf); 1556 struct dc_transfer_func *dc_create_transfer_func(void); 1557 1558 struct dc_3dlut *dc_create_3dlut_func(void); 1559 void dc_3dlut_func_release(struct dc_3dlut *lut); 1560 void dc_3dlut_func_retain(struct dc_3dlut *lut); 1561 1562 void dc_post_update_surfaces_to_stream( 1563 struct dc *dc); 1564 1565 #include "dc_stream.h" 1566 1567 /** 1568 * struct dc_validation_set - Struct to store surface/stream associations for validation 1569 */ 1570 struct dc_validation_set { 1571 /** 1572 * @stream: Stream state properties 1573 */ 1574 struct dc_stream_state *stream; 1575 1576 /** 1577 * @plane_states: Surface state 1578 */ 1579 struct dc_plane_state *plane_states[MAX_SURFACES]; 1580 1581 /** 1582 * @plane_count: Total of active planes 1583 */ 1584 uint8_t plane_count; 1585 }; 1586 1587 bool dc_validate_boot_timing(const struct dc *dc, 1588 const struct dc_sink *sink, 1589 struct dc_crtc_timing *crtc_timing); 1590 1591 enum dc_status dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state); 1592 1593 enum dc_status dc_validate_with_context(struct dc *dc, 1594 const struct dc_validation_set set[], 1595 int set_count, 1596 struct dc_state *context, 1597 bool fast_validate); 1598 1599 bool dc_set_generic_gpio_for_stereo(bool enable, 1600 struct gpio_service *gpio_service); 1601 1602 /* 1603 * fast_validate: we return after determining if we can support the new state, 1604 * but before we populate the programming info 1605 */ 1606 enum dc_status dc_validate_global_state( 1607 struct dc *dc, 1608 struct dc_state *new_ctx, 1609 bool fast_validate); 1610 1611 bool dc_acquire_release_mpc_3dlut( 1612 struct dc *dc, bool acquire, 1613 struct dc_stream_state *stream, 1614 struct dc_3dlut **lut, 1615 struct dc_transfer_func **shaper); 1616 1617 bool dc_resource_is_dsc_encoding_supported(const struct dc *dc); 1618 void get_audio_check(struct audio_info *aud_modes, 1619 struct audio_check *aud_chk); 1620 1621 bool fast_nonaddr_updates_exist(struct dc_fast_update *fast_update, int surface_count); 1622 void populate_fast_updates(struct dc_fast_update *fast_update, 1623 struct dc_surface_update *srf_updates, 1624 int surface_count, 1625 struct dc_stream_update *stream_update); 1626 /* 1627 * Set up streams and links associated to drive sinks 1628 * The streams parameter is an absolute set of all active streams. 1629 * 1630 * After this call: 1631 * Phy, Encoder, Timing Generator are programmed and enabled. 1632 * New streams are enabled with blank stream; no memory read. 1633 */ 1634 enum dc_status dc_commit_streams(struct dc *dc, struct dc_commit_streams_params *params); 1635 1636 1637 struct dc_plane_state *dc_get_surface_for_mpcc(struct dc *dc, 1638 struct dc_stream_state *stream, 1639 int mpcc_inst); 1640 1641 1642 uint32_t dc_get_opp_for_plane(struct dc *dc, struct dc_plane_state *plane); 1643 1644 void dc_set_disable_128b_132b_stream_overhead(bool disable); 1645 1646 /* The function returns minimum bandwidth required to drive a given timing 1647 * return - minimum required timing bandwidth in kbps. 1648 */ 1649 uint32_t dc_bandwidth_in_kbps_from_timing( 1650 const struct dc_crtc_timing *timing, 1651 const enum dc_link_encoding_format link_encoding); 1652 1653 /* Link Interfaces */ 1654 /* 1655 * A link contains one or more sinks and their connected status. 1656 * The currently active signal type (HDMI, DP-SST, DP-MST) is also reported. 1657 */ 1658 struct dc_link { 1659 struct dc_sink *remote_sinks[MAX_SINKS_PER_LINK]; 1660 unsigned int sink_count; 1661 struct dc_sink *local_sink; 1662 unsigned int link_index; 1663 enum dc_connection_type type; 1664 enum signal_type connector_signal; 1665 enum dc_irq_source irq_source_hpd; 1666 enum dc_irq_source irq_source_hpd_rx;/* aka DP Short Pulse */ 1667 1668 bool is_hpd_filter_disabled; 1669 bool dp_ss_off; 1670 1671 /** 1672 * @link_state_valid: 1673 * 1674 * If there is no link and local sink, this variable should be set to 1675 * false. Otherwise, it should be set to true; usually, the function 1676 * core_link_enable_stream sets this field to true. 1677 */ 1678 bool link_state_valid; 1679 bool aux_access_disabled; 1680 bool sync_lt_in_progress; 1681 bool skip_stream_reenable; 1682 bool is_internal_display; 1683 /** @todo Rename. Flag an endpoint as having a programmable mapping to a DIG encoder. */ 1684 bool is_dig_mapping_flexible; 1685 bool hpd_status; /* HPD status of link without physical HPD pin. */ 1686 bool is_hpd_pending; /* Indicates a new received hpd */ 1687 1688 /* USB4 DPIA links skip verifying link cap, instead performing the fallback method 1689 * for every link training. This is incompatible with DP LL compliance automation, 1690 * which expects the same link settings to be used every retry on a link loss. 1691 * This flag is used to skip the fallback when link loss occurs during automation. 1692 */ 1693 bool skip_fallback_on_link_loss; 1694 1695 bool edp_sink_present; 1696 1697 struct dp_trace dp_trace; 1698 1699 /* caps is the same as reported_link_cap. link_traing use 1700 * reported_link_cap. Will clean up. TODO 1701 */ 1702 struct dc_link_settings reported_link_cap; 1703 struct dc_link_settings verified_link_cap; 1704 struct dc_link_settings cur_link_settings; 1705 struct dc_lane_settings cur_lane_setting[LANE_COUNT_DP_MAX]; 1706 struct dc_link_settings preferred_link_setting; 1707 /* preferred_training_settings are override values that 1708 * come from DM. DM is responsible for the memory 1709 * management of the override pointers. 1710 */ 1711 struct dc_link_training_overrides preferred_training_settings; 1712 struct dp_audio_test_data audio_test_data; 1713 1714 uint8_t ddc_hw_inst; 1715 1716 uint8_t hpd_src; 1717 1718 uint8_t link_enc_hw_inst; 1719 /* DIG link encoder ID. Used as index in link encoder resource pool. 1720 * For links with fixed mapping to DIG, this is not changed after dc_link 1721 * object creation. 1722 */ 1723 enum engine_id eng_id; 1724 enum engine_id dpia_preferred_eng_id; 1725 1726 bool test_pattern_enabled; 1727 /* Pending/Current test pattern are only used to perform and track 1728 * FIXED_VS retimer test pattern/lane adjustment override state. 1729 * Pending allows link HWSS to differentiate PHY vs non-PHY pattern, 1730 * to perform specific lane adjust overrides before setting certain 1731 * PHY test patterns. In cases when lane adjust and set test pattern 1732 * calls are not performed atomically (i.e. performing link training), 1733 * pending_test_pattern will be invalid or contain a non-PHY test pattern 1734 * and current_test_pattern will contain required context for any future 1735 * set pattern/set lane adjust to transition between override state(s). 1736 * */ 1737 enum dp_test_pattern current_test_pattern; 1738 enum dp_test_pattern pending_test_pattern; 1739 1740 union compliance_test_state compliance_test_state; 1741 1742 void *priv; 1743 1744 struct ddc_service *ddc; 1745 1746 enum dp_panel_mode panel_mode; 1747 bool aux_mode; 1748 1749 /* Private to DC core */ 1750 1751 const struct dc *dc; 1752 1753 struct dc_context *ctx; 1754 1755 struct panel_cntl *panel_cntl; 1756 struct link_encoder *link_enc; 1757 struct graphics_object_id link_id; 1758 /* Endpoint type distinguishes display endpoints which do not have entries 1759 * in the BIOS connector table from those that do. Helps when tracking link 1760 * encoder to display endpoint assignments. 1761 */ 1762 enum display_endpoint_type ep_type; 1763 union ddi_channel_mapping ddi_channel_mapping; 1764 struct connector_device_tag_info device_tag; 1765 struct dpcd_caps dpcd_caps; 1766 uint32_t dongle_max_pix_clk; 1767 unsigned short chip_caps; 1768 unsigned int dpcd_sink_count; 1769 struct hdcp_caps hdcp_caps; 1770 enum edp_revision edp_revision; 1771 union dpcd_sink_ext_caps dpcd_sink_ext_caps; 1772 1773 struct psr_settings psr_settings; 1774 struct replay_settings replay_settings; 1775 1776 /* Drive settings read from integrated info table */ 1777 struct dc_lane_settings bios_forced_drive_settings; 1778 1779 /* Vendor specific LTTPR workaround variables */ 1780 uint8_t vendor_specific_lttpr_link_rate_wa; 1781 bool apply_vendor_specific_lttpr_link_rate_wa; 1782 1783 /* MST record stream using this link */ 1784 struct link_flags { 1785 bool dp_keep_receiver_powered; 1786 bool dp_skip_DID2; 1787 bool dp_skip_reset_segment; 1788 bool dp_skip_fs_144hz; 1789 bool dp_mot_reset_segment; 1790 /* Some USB4 docks do not handle turning off MST DSC once it has been enabled. */ 1791 bool dpia_mst_dsc_always_on; 1792 /* Forced DPIA into TBT3 compatibility mode. */ 1793 bool dpia_forced_tbt3_mode; 1794 bool dongle_mode_timing_override; 1795 bool blank_stream_on_ocs_change; 1796 bool read_dpcd204h_on_irq_hpd; 1797 bool force_dp_ffe_preset; 1798 } wa_flags; 1799 union dc_dp_ffe_preset forced_dp_ffe_preset; 1800 struct link_mst_stream_allocation_table mst_stream_alloc_table; 1801 1802 struct dc_link_status link_status; 1803 struct dprx_states dprx_states; 1804 1805 struct gpio *hpd_gpio; 1806 enum dc_link_fec_state fec_state; 1807 bool link_powered_externally; // Used to bypass hardware sequencing delays when panel is powered down forcibly 1808 1809 struct dc_panel_config panel_config; 1810 struct phy_state phy_state; 1811 uint32_t phy_transition_bitmask; 1812 // BW ALLOCATON USB4 ONLY 1813 struct dc_dpia_bw_alloc dpia_bw_alloc_config; 1814 bool skip_implict_edp_power_control; 1815 enum backlight_control_type backlight_control_type; 1816 }; 1817 1818 /* Return an enumerated dc_link. 1819 * dc_link order is constant and determined at 1820 * boot time. They cannot be created or destroyed. 1821 * Use dc_get_caps() to get number of links. 1822 */ 1823 struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index); 1824 1825 /* Return instance id of the edp link. Inst 0 is primary edp link. */ 1826 bool dc_get_edp_link_panel_inst(const struct dc *dc, 1827 const struct dc_link *link, 1828 unsigned int *inst_out); 1829 1830 /* Return an array of link pointers to edp links. */ 1831 void dc_get_edp_links(const struct dc *dc, 1832 struct dc_link **edp_links, 1833 int *edp_num); 1834 1835 void dc_set_edp_power(const struct dc *dc, struct dc_link *edp_link, 1836 bool powerOn); 1837 1838 /* The function initiates detection handshake over the given link. It first 1839 * determines if there are display connections over the link. If so it initiates 1840 * detection protocols supported by the connected receiver device. The function 1841 * contains protocol specific handshake sequences which are sometimes mandatory 1842 * to establish a proper connection between TX and RX. So it is always 1843 * recommended to call this function as the first link operation upon HPD event 1844 * or power up event. Upon completion, the function will update link structure 1845 * in place based on latest RX capabilities. The function may also cause dpms 1846 * to be reset to off for all currently enabled streams to the link. It is DM's 1847 * responsibility to serialize detection and DPMS updates. 1848 * 1849 * @reason - Indicate which event triggers this detection. dc may customize 1850 * detection flow depending on the triggering events. 1851 * return false - if detection is not fully completed. This could happen when 1852 * there is an unrecoverable error during detection or detection is partially 1853 * completed (detection has been delegated to dm mst manager ie. 1854 * link->connection_type == dc_connection_mst_branch when returning false). 1855 * return true - detection is completed, link has been fully updated with latest 1856 * detection result. 1857 */ 1858 bool dc_link_detect(struct dc_link *link, enum dc_detect_reason reason); 1859 1860 struct dc_sink_init_data; 1861 1862 /* When link connection type is dc_connection_mst_branch, remote sink can be 1863 * added to the link. The interface creates a remote sink and associates it with 1864 * current link. The sink will be retained by link until remove remote sink is 1865 * called. 1866 * 1867 * @dc_link - link the remote sink will be added to. 1868 * @edid - byte array of EDID raw data. 1869 * @len - size of the edid in byte 1870 * @init_data - 1871 */ 1872 struct dc_sink *dc_link_add_remote_sink( 1873 struct dc_link *dc_link, 1874 const uint8_t *edid, 1875 int len, 1876 struct dc_sink_init_data *init_data); 1877 1878 /* Remove remote sink from a link with dc_connection_mst_branch connection type. 1879 * @link - link the sink should be removed from 1880 * @sink - sink to be removed. 1881 */ 1882 void dc_link_remove_remote_sink( 1883 struct dc_link *link, 1884 struct dc_sink *sink); 1885 1886 /* Enable HPD interrupt handler for a given link */ 1887 void dc_link_enable_hpd(const struct dc_link *link); 1888 1889 /* Disable HPD interrupt handler for a given link */ 1890 void dc_link_disable_hpd(const struct dc_link *link); 1891 1892 /* determine if there is a sink connected to the link 1893 * 1894 * @type - dc_connection_single if connected, dc_connection_none otherwise. 1895 * return - false if an unexpected error occurs, true otherwise. 1896 * 1897 * NOTE: This function doesn't detect downstream sink connections i.e 1898 * dc_connection_mst_branch, dc_connection_sst_branch. In this case, it will 1899 * return dc_connection_single if the branch device is connected despite of 1900 * downstream sink's connection status. 1901 */ 1902 bool dc_link_detect_connection_type(struct dc_link *link, 1903 enum dc_connection_type *type); 1904 1905 /* query current hpd pin value 1906 * return - true HPD is asserted (HPD high), false otherwise (HPD low) 1907 * 1908 */ 1909 bool dc_link_get_hpd_state(struct dc_link *link); 1910 1911 /* Getter for cached link status from given link */ 1912 const struct dc_link_status *dc_link_get_status(const struct dc_link *link); 1913 1914 /* enable/disable hardware HPD filter. 1915 * 1916 * @link - The link the HPD pin is associated with. 1917 * @enable = true - enable hardware HPD filter. HPD event will only queued to irq 1918 * handler once after no HPD change has been detected within dc default HPD 1919 * filtering interval since last HPD event. i.e if display keeps toggling hpd 1920 * pulses within default HPD interval, no HPD event will be received until HPD 1921 * toggles have stopped. Then HPD event will be queued to irq handler once after 1922 * dc default HPD filtering interval since last HPD event. 1923 * 1924 * @enable = false - disable hardware HPD filter. HPD event will be queued 1925 * immediately to irq handler after no HPD change has been detected within 1926 * IRQ_HPD (aka HPD short pulse) interval (i.e 2ms). 1927 */ 1928 void dc_link_enable_hpd_filter(struct dc_link *link, bool enable); 1929 1930 /* submit i2c read/write payloads through ddc channel 1931 * @link_index - index to a link with ddc in i2c mode 1932 * @cmd - i2c command structure 1933 * return - true if success, false otherwise. 1934 */ 1935 bool dc_submit_i2c( 1936 struct dc *dc, 1937 uint32_t link_index, 1938 struct i2c_command *cmd); 1939 1940 /* submit i2c read/write payloads through oem channel 1941 * @link_index - index to a link with ddc in i2c mode 1942 * @cmd - i2c command structure 1943 * return - true if success, false otherwise. 1944 */ 1945 bool dc_submit_i2c_oem( 1946 struct dc *dc, 1947 struct i2c_command *cmd); 1948 1949 enum aux_return_code_type; 1950 /* Attempt to transfer the given aux payload. This function does not perform 1951 * retries or handle error states. The reply is returned in the payload->reply 1952 * and the result through operation_result. Returns the number of bytes 1953 * transferred,or -1 on a failure. 1954 */ 1955 int dc_link_aux_transfer_raw(struct ddc_service *ddc, 1956 struct aux_payload *payload, 1957 enum aux_return_code_type *operation_result); 1958 1959 struct ddc_service * 1960 dc_get_oem_i2c_device(struct dc *dc); 1961 1962 bool dc_is_oem_i2c_device_present( 1963 struct dc *dc, 1964 size_t slave_address 1965 ); 1966 1967 /* return true if the connected receiver supports the hdcp version */ 1968 bool dc_link_is_hdcp14(struct dc_link *link, enum signal_type signal); 1969 bool dc_link_is_hdcp22(struct dc_link *link, enum signal_type signal); 1970 1971 /* Notify DC about DP RX Interrupt (aka DP IRQ_HPD). 1972 * 1973 * TODO - When defer_handling is true the function will have a different purpose. 1974 * It no longer does complete hpd rx irq handling. We should create a separate 1975 * interface specifically for this case. 1976 * 1977 * Return: 1978 * true - Downstream port status changed. DM should call DC to do the 1979 * detection. 1980 * false - no change in Downstream port status. No further action required 1981 * from DM. 1982 */ 1983 bool dc_link_handle_hpd_rx_irq(struct dc_link *dc_link, 1984 union hpd_irq_data *hpd_irq_dpcd_data, bool *out_link_loss, 1985 bool defer_handling, bool *has_left_work); 1986 /* handle DP specs define test automation sequence*/ 1987 void dc_link_dp_handle_automated_test(struct dc_link *link); 1988 1989 /* handle DP Link loss sequence and try to recover RX link loss with best 1990 * effort 1991 */ 1992 void dc_link_dp_handle_link_loss(struct dc_link *link); 1993 1994 /* Determine if hpd rx irq should be handled or ignored 1995 * return true - hpd rx irq should be handled. 1996 * return false - it is safe to ignore hpd rx irq event 1997 */ 1998 bool dc_link_dp_allow_hpd_rx_irq(const struct dc_link *link); 1999 2000 /* Determine if link loss is indicated with a given hpd_irq_dpcd_data. 2001 * @link - link the hpd irq data associated with 2002 * @hpd_irq_dpcd_data - input hpd irq data 2003 * return - true if hpd irq data indicates a link lost 2004 */ 2005 bool dc_link_check_link_loss_status(struct dc_link *link, 2006 union hpd_irq_data *hpd_irq_dpcd_data); 2007 2008 /* Read hpd rx irq data from a given link 2009 * @link - link where the hpd irq data should be read from 2010 * @irq_data - output hpd irq data 2011 * return - DC_OK if hpd irq data is read successfully, otherwise hpd irq data 2012 * read has failed. 2013 */ 2014 enum dc_status dc_link_dp_read_hpd_rx_irq_data( 2015 struct dc_link *link, 2016 union hpd_irq_data *irq_data); 2017 2018 /* The function clears recorded DP RX states in the link. DM should call this 2019 * function when it is resuming from S3 power state to previously connected links. 2020 * 2021 * TODO - in the future we should consider to expand link resume interface to 2022 * support clearing previous rx states. So we don't have to rely on dm to call 2023 * this interface explicitly. 2024 */ 2025 void dc_link_clear_dprx_states(struct dc_link *link); 2026 2027 /* Destruct the mst topology of the link and reset the allocated payload table 2028 * 2029 * NOTE: this should only be called if DM chooses not to call dc_link_detect but 2030 * still wants to reset MST topology on an unplug event */ 2031 bool dc_link_reset_cur_dp_mst_topology(struct dc_link *link); 2032 2033 /* The function calculates effective DP link bandwidth when a given link is 2034 * using the given link settings. 2035 * 2036 * return - total effective link bandwidth in kbps. 2037 */ 2038 uint32_t dc_link_bandwidth_kbps( 2039 const struct dc_link *link, 2040 const struct dc_link_settings *link_setting); 2041 2042 struct dp_audio_bandwidth_params { 2043 const struct dc_crtc_timing *crtc_timing; 2044 enum dp_link_encoding link_encoding; 2045 uint32_t channel_count; 2046 uint32_t sample_rate_hz; 2047 }; 2048 2049 /* The function calculates the minimum size of hblank (in bytes) needed to 2050 * support the specified channel count and sample rate combination, given the 2051 * link encoding and timing to be used. This calculation is not supported 2052 * for 8b/10b SST. 2053 * 2054 * return - min hblank size in bytes, 0 if 8b/10b SST. 2055 */ 2056 uint32_t dc_link_required_hblank_size_bytes( 2057 const struct dc_link *link, 2058 struct dp_audio_bandwidth_params *audio_params); 2059 2060 /* The function takes a snapshot of current link resource allocation state 2061 * @dc: pointer to dc of the dm calling this 2062 * @map: a dc link resource snapshot defined internally to dc. 2063 * 2064 * DM needs to capture a snapshot of current link resource allocation mapping 2065 * and store it in its persistent storage. 2066 * 2067 * Some of the link resource is using first come first serve policy. 2068 * The allocation mapping depends on original hotplug order. This information 2069 * is lost after driver is loaded next time. The snapshot is used in order to 2070 * restore link resource to its previous state so user will get consistent 2071 * link capability allocation across reboot. 2072 * 2073 */ 2074 void dc_get_cur_link_res_map(const struct dc *dc, uint32_t *map); 2075 2076 /* This function restores link resource allocation state from a snapshot 2077 * @dc: pointer to dc of the dm calling this 2078 * @map: a dc link resource snapshot defined internally to dc. 2079 * 2080 * DM needs to call this function after initial link detection on boot and 2081 * before first commit streams to restore link resource allocation state 2082 * from previous boot session. 2083 * 2084 * Some of the link resource is using first come first serve policy. 2085 * The allocation mapping depends on original hotplug order. This information 2086 * is lost after driver is loaded next time. The snapshot is used in order to 2087 * restore link resource to its previous state so user will get consistent 2088 * link capability allocation across reboot. 2089 * 2090 */ 2091 void dc_restore_link_res_map(const struct dc *dc, uint32_t *map); 2092 2093 /* TODO: this is not meant to be exposed to DM. Should switch to stream update 2094 * interface i.e stream_update->dsc_config 2095 */ 2096 bool dc_link_update_dsc_config(struct pipe_ctx *pipe_ctx); 2097 2098 /* translate a raw link rate data to bandwidth in kbps */ 2099 uint32_t dc_link_bw_kbps_from_raw_frl_link_rate_data(const struct dc *dc, uint8_t bw); 2100 2101 /* determine the optimal bandwidth given link and required bw. 2102 * @link - current detected link 2103 * @req_bw - requested bandwidth in kbps 2104 * @link_settings - returned most optimal link settings that can fit the 2105 * requested bandwidth 2106 * return - false if link can't support requested bandwidth, true if link 2107 * settings is found. 2108 */ 2109 bool dc_link_decide_edp_link_settings(struct dc_link *link, 2110 struct dc_link_settings *link_settings, 2111 uint32_t req_bw); 2112 2113 /* return the max dp link settings can be driven by the link without considering 2114 * connected RX device and its capability 2115 */ 2116 bool dc_link_dp_get_max_link_enc_cap(const struct dc_link *link, 2117 struct dc_link_settings *max_link_enc_cap); 2118 2119 /* determine when the link is driving MST mode, what DP link channel coding 2120 * format will be used. The decision will remain unchanged until next HPD event. 2121 * 2122 * @link - a link with DP RX connection 2123 * return - if stream is committed to this link with MST signal type, type of 2124 * channel coding format dc will choose. 2125 */ 2126 enum dp_link_encoding dc_link_dp_mst_decide_link_encoding_format( 2127 const struct dc_link *link); 2128 2129 /* get max dp link settings the link can enable with all things considered. (i.e 2130 * TX/RX/Cable capabilities and dp override policies. 2131 * 2132 * @link - a link with DP RX connection 2133 * return - max dp link settings the link can enable. 2134 * 2135 */ 2136 const struct dc_link_settings *dc_link_get_link_cap(const struct dc_link *link); 2137 2138 /* Get the highest encoding format that the link supports; highest meaning the 2139 * encoding format which supports the maximum bandwidth. 2140 * 2141 * @link - a link with DP RX connection 2142 * return - highest encoding format link supports. 2143 */ 2144 enum dc_link_encoding_format dc_link_get_highest_encoding_format(const struct dc_link *link); 2145 2146 /* Check if a RX (ex. DP sink, MST hub, passive or active dongle) is connected 2147 * to a link with dp connector signal type. 2148 * @link - a link with dp connector signal type 2149 * return - true if connected, false otherwise 2150 */ 2151 bool dc_link_is_dp_sink_present(struct dc_link *link); 2152 2153 /* Force DP lane settings update to main-link video signal and notify the change 2154 * to DP RX via DPCD. This is a debug interface used for video signal integrity 2155 * tuning purpose. The interface assumes link has already been enabled with DP 2156 * signal. 2157 * 2158 * @lt_settings - a container structure with desired hw_lane_settings 2159 */ 2160 void dc_link_set_drive_settings(struct dc *dc, 2161 struct link_training_settings *lt_settings, 2162 struct dc_link *link); 2163 2164 /* Enable a test pattern in Link or PHY layer in an active link for compliance 2165 * test or debugging purpose. The test pattern will remain until next un-plug. 2166 * 2167 * @link - active link with DP signal output enabled. 2168 * @test_pattern - desired test pattern to output. 2169 * NOTE: set to DP_TEST_PATTERN_VIDEO_MODE to disable previous test pattern. 2170 * @test_pattern_color_space - for video test pattern choose a desired color 2171 * space. 2172 * @p_link_settings - For PHY pattern choose a desired link settings 2173 * @p_custom_pattern - some test pattern will require a custom input to 2174 * customize some pattern details. Otherwise keep it to NULL. 2175 * @cust_pattern_size - size of the custom pattern input. 2176 * 2177 */ 2178 bool dc_link_dp_set_test_pattern( 2179 struct dc_link *link, 2180 enum dp_test_pattern test_pattern, 2181 enum dp_test_pattern_color_space test_pattern_color_space, 2182 const struct link_training_settings *p_link_settings, 2183 const unsigned char *p_custom_pattern, 2184 unsigned int cust_pattern_size); 2185 2186 /* Force DP link settings to always use a specific value until reboot to a 2187 * specific link. If link has already been enabled, the interface will also 2188 * switch to desired link settings immediately. This is a debug interface to 2189 * generic dp issue trouble shooting. 2190 */ 2191 void dc_link_set_preferred_link_settings(struct dc *dc, 2192 struct dc_link_settings *link_setting, 2193 struct dc_link *link); 2194 2195 /* Force DP link to customize a specific link training behavior by overriding to 2196 * standard DP specs defined protocol. This is a debug interface to trouble shoot 2197 * display specific link training issues or apply some display specific 2198 * workaround in link training. 2199 * 2200 * @link_settings - if not NULL, force preferred link settings to the link. 2201 * @lt_override - a set of override pointers. If any pointer is none NULL, dc 2202 * will apply this particular override in future link training. If NULL is 2203 * passed in, dc resets previous overrides. 2204 * NOTE: DM must keep the memory from override pointers until DM resets preferred 2205 * training settings. 2206 */ 2207 void dc_link_set_preferred_training_settings(struct dc *dc, 2208 struct dc_link_settings *link_setting, 2209 struct dc_link_training_overrides *lt_overrides, 2210 struct dc_link *link, 2211 bool skip_immediate_retrain); 2212 2213 /* return - true if FEC is supported with connected DP RX, false otherwise */ 2214 bool dc_link_is_fec_supported(const struct dc_link *link); 2215 2216 /* query FEC enablement policy to determine if FEC will be enabled by dc during 2217 * link enablement. 2218 * return - true if FEC should be enabled, false otherwise. 2219 */ 2220 bool dc_link_should_enable_fec(const struct dc_link *link); 2221 2222 /* determine lttpr mode the current link should be enabled with a specific link 2223 * settings. 2224 */ 2225 enum lttpr_mode dc_link_decide_lttpr_mode(struct dc_link *link, 2226 struct dc_link_settings *link_setting); 2227 2228 /* Force DP RX to update its power state. 2229 * NOTE: this interface doesn't update dp main-link. Calling this function will 2230 * cause DP TX main-link and DP RX power states out of sync. DM has to restore 2231 * RX power state back upon finish DM specific execution requiring DP RX in a 2232 * specific power state. 2233 * @on - true to set DP RX in D0 power state, false to set DP RX in D3 power 2234 * state. 2235 */ 2236 void dc_link_dp_receiver_power_ctrl(struct dc_link *link, bool on); 2237 2238 /* Force link to read base dp receiver caps from dpcd 000h - 00Fh and overwrite 2239 * current value read from extended receiver cap from 02200h - 0220Fh. 2240 * Some DP RX has problems of providing accurate DP receiver caps from extended 2241 * field, this interface is a workaround to revert link back to use base caps. 2242 */ 2243 void dc_link_overwrite_extended_receiver_cap( 2244 struct dc_link *link); 2245 2246 void dc_link_edp_panel_backlight_power_on(struct dc_link *link, 2247 bool wait_for_hpd); 2248 2249 /* Set backlight level of an embedded panel (eDP, LVDS). 2250 * backlight_pwm_u16_16 is unsigned 32 bit with 16 bit integer 2251 * and 16 bit fractional, where 1.0 is max backlight value. 2252 */ 2253 bool dc_link_set_backlight_level(const struct dc_link *dc_link, 2254 struct set_backlight_level_params *backlight_level_params); 2255 2256 /* Set/get nits-based backlight level of an embedded panel (eDP, LVDS). */ 2257 bool dc_link_set_backlight_level_nits(struct dc_link *link, 2258 bool isHDR, 2259 uint32_t backlight_millinits, 2260 uint32_t transition_time_in_ms); 2261 2262 bool dc_link_get_backlight_level_nits(struct dc_link *link, 2263 uint32_t *backlight_millinits, 2264 uint32_t *backlight_millinits_peak); 2265 2266 int dc_link_get_backlight_level(const struct dc_link *dc_link); 2267 2268 int dc_link_get_target_backlight_pwm(const struct dc_link *link); 2269 2270 bool dc_link_set_psr_allow_active(struct dc_link *dc_link, const bool *enable, 2271 bool wait, bool force_static, const unsigned int *power_opts); 2272 2273 bool dc_link_get_psr_state(const struct dc_link *dc_link, enum dc_psr_state *state); 2274 2275 bool dc_link_setup_psr(struct dc_link *dc_link, 2276 const struct dc_stream_state *stream, struct psr_config *psr_config, 2277 struct psr_context *psr_context); 2278 2279 /* 2280 * Communicate with DMUB to allow or disallow Panel Replay on the specified link: 2281 * 2282 * @link: pointer to the dc_link struct instance 2283 * @enable: enable(active) or disable(inactive) replay 2284 * @wait: state transition need to wait the active set completed. 2285 * @force_static: force disable(inactive) the replay 2286 * @power_opts: set power optimazation parameters to DMUB. 2287 * 2288 * return: allow Replay active will return true, else will return false. 2289 */ 2290 bool dc_link_set_replay_allow_active(struct dc_link *dc_link, const bool *enable, 2291 bool wait, bool force_static, const unsigned int *power_opts); 2292 2293 bool dc_link_get_replay_state(const struct dc_link *dc_link, uint64_t *state); 2294 2295 /* On eDP links this function call will stall until T12 has elapsed. 2296 * If the panel is not in power off state, this function will return 2297 * immediately. 2298 */ 2299 bool dc_link_wait_for_t12(struct dc_link *link); 2300 2301 /* Determine if dp trace has been initialized to reflect upto date result * 2302 * return - true if trace is initialized and has valid data. False dp trace 2303 * doesn't have valid result. 2304 */ 2305 bool dc_dp_trace_is_initialized(struct dc_link *link); 2306 2307 /* Query a dp trace flag to indicate if the current dp trace data has been 2308 * logged before 2309 */ 2310 bool dc_dp_trace_is_logged(struct dc_link *link, 2311 bool in_detection); 2312 2313 /* Set dp trace flag to indicate whether DM has already logged the current dp 2314 * trace data. DM can set is_logged to true upon logging and check 2315 * dc_dp_trace_is_logged before logging to avoid logging the same result twice. 2316 */ 2317 void dc_dp_trace_set_is_logged_flag(struct dc_link *link, 2318 bool in_detection, 2319 bool is_logged); 2320 2321 /* Obtain driver time stamp for last dp link training end. The time stamp is 2322 * formatted based on dm_get_timestamp DM function. 2323 * @in_detection - true to get link training end time stamp of last link 2324 * training in detection sequence. false to get link training end time stamp 2325 * of last link training in commit (dpms) sequence 2326 */ 2327 unsigned long long dc_dp_trace_get_lt_end_timestamp(struct dc_link *link, 2328 bool in_detection); 2329 2330 /* Get how many link training attempts dc has done with latest sequence. 2331 * @in_detection - true to get link training count of last link 2332 * training in detection sequence. false to get link training count of last link 2333 * training in commit (dpms) sequence 2334 */ 2335 const struct dp_trace_lt_counts *dc_dp_trace_get_lt_counts(struct dc_link *link, 2336 bool in_detection); 2337 2338 /* Get how many link loss has happened since last link training attempts */ 2339 unsigned int dc_dp_trace_get_link_loss_count(struct dc_link *link); 2340 2341 /* 2342 * USB4 DPIA BW ALLOCATION PUBLIC FUNCTIONS 2343 */ 2344 /* 2345 * Send a request from DP-Tx requesting to allocate BW remotely after 2346 * allocating it locally. This will get processed by CM and a CB function 2347 * will be called. 2348 * 2349 * @link: pointer to the dc_link struct instance 2350 * @req_bw: The requested bw in Kbyte to allocated 2351 * 2352 * return: none 2353 */ 2354 void dc_link_set_usb4_req_bw_req(struct dc_link *link, int req_bw); 2355 2356 /* 2357 * Handle the USB4 BW Allocation related functionality here: 2358 * Plug => Try to allocate max bw from timing parameters supported by the sink 2359 * Unplug => de-allocate bw 2360 * 2361 * @link: pointer to the dc_link struct instance 2362 * @peak_bw: Peak bw used by the link/sink 2363 * 2364 */ 2365 void dc_link_dp_dpia_handle_usb4_bandwidth_allocation_for_link( 2366 struct dc_link *link, int peak_bw); 2367 2368 /* 2369 * Validate the BW of all the valid DPIA links to make sure it doesn't exceed 2370 * available BW for each host router 2371 * 2372 * @dc: pointer to dc struct 2373 * @stream: pointer to all possible streams 2374 * @count: number of valid DPIA streams 2375 * 2376 * return: TRUE if bw used by DPIAs doesn't exceed available BW else return FALSE 2377 */ 2378 bool dc_link_dp_dpia_validate(struct dc *dc, const struct dc_stream_state *streams, 2379 const unsigned int count); 2380 2381 /* Sink Interfaces - A sink corresponds to a display output device */ 2382 2383 struct dc_container_id { 2384 // 128bit GUID in binary form 2385 unsigned char guid[16]; 2386 // 8 byte port ID -> ELD.PortID 2387 unsigned int portId[2]; 2388 // 128bit GUID in binary formufacturer name -> ELD.ManufacturerName 2389 unsigned short manufacturerName; 2390 // 2 byte product code -> ELD.ProductCode 2391 unsigned short productCode; 2392 }; 2393 2394 2395 struct dc_sink_dsc_caps { 2396 // 'true' if these are virtual DPCD's DSC caps (immediately upstream of sink in MST topology), 2397 // 'false' if they are sink's DSC caps 2398 bool is_virtual_dpcd_dsc; 2399 // 'true' if MST topology supports DSC passthrough for sink 2400 // 'false' if MST topology does not support DSC passthrough 2401 bool is_dsc_passthrough_supported; 2402 struct dsc_dec_dpcd_caps dsc_dec_caps; 2403 }; 2404 2405 struct dc_sink_hblank_expansion_caps { 2406 // 'true' if these are virtual DPCD's HBlank expansion caps (immediately upstream of sink in MST topology), 2407 // 'false' if they are sink's HBlank expansion caps 2408 bool is_virtual_dpcd_hblank_expansion; 2409 struct hblank_expansion_dpcd_caps dpcd_caps; 2410 }; 2411 2412 struct dc_sink_fec_caps { 2413 bool is_rx_fec_supported; 2414 bool is_topology_fec_supported; 2415 }; 2416 2417 struct scdc_caps { 2418 union hdmi_scdc_manufacturer_OUI_data manufacturer_OUI; 2419 union hdmi_scdc_device_id_data device_id; 2420 }; 2421 2422 /* 2423 * The sink structure contains EDID and other display device properties 2424 */ 2425 struct dc_sink { 2426 enum signal_type sink_signal; 2427 struct dc_edid dc_edid; /* raw edid */ 2428 struct dc_edid_caps edid_caps; /* parse display caps */ 2429 struct dc_container_id *dc_container_id; 2430 uint32_t dongle_max_pix_clk; 2431 void *priv; 2432 struct stereo_3d_features features_3d[TIMING_3D_FORMAT_MAX]; 2433 bool converter_disable_audio; 2434 2435 struct scdc_caps scdc_caps; 2436 struct dc_sink_dsc_caps dsc_caps; 2437 struct dc_sink_fec_caps fec_caps; 2438 struct dc_sink_hblank_expansion_caps hblank_expansion_caps; 2439 2440 bool is_vsc_sdp_colorimetry_supported; 2441 2442 /* private to DC core */ 2443 struct dc_link *link; 2444 struct dc_context *ctx; 2445 2446 uint32_t sink_id; 2447 2448 /* private to dc_sink.c */ 2449 // refcount must be the last member in dc_sink, since we want the 2450 // sink structure to be logically cloneable up to (but not including) 2451 // refcount 2452 struct kref refcount; 2453 }; 2454 2455 void dc_sink_retain(struct dc_sink *sink); 2456 void dc_sink_release(struct dc_sink *sink); 2457 2458 struct dc_sink_init_data { 2459 enum signal_type sink_signal; 2460 struct dc_link *link; 2461 uint32_t dongle_max_pix_clk; 2462 bool converter_disable_audio; 2463 }; 2464 2465 struct dc_sink *dc_sink_create(const struct dc_sink_init_data *init_params); 2466 2467 /* Newer interfaces */ 2468 struct dc_cursor { 2469 struct dc_plane_address address; 2470 struct dc_cursor_attributes attributes; 2471 }; 2472 2473 2474 /* Interrupt interfaces */ 2475 enum dc_irq_source dc_interrupt_to_irq_source( 2476 struct dc *dc, 2477 uint32_t src_id, 2478 uint32_t ext_id); 2479 bool dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable); 2480 void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src); 2481 enum dc_irq_source dc_get_hpd_irq_source_at_index( 2482 struct dc *dc, uint32_t link_index); 2483 2484 void dc_notify_vsync_int_state(struct dc *dc, struct dc_stream_state *stream, bool enable); 2485 2486 /* Power Interfaces */ 2487 2488 void dc_set_power_state( 2489 struct dc *dc, 2490 enum dc_acpi_cm_power_state power_state); 2491 void dc_resume(struct dc *dc); 2492 2493 void dc_power_down_on_boot(struct dc *dc); 2494 2495 /* 2496 * HDCP Interfaces 2497 */ 2498 enum hdcp_message_status dc_process_hdcp_msg( 2499 enum signal_type signal, 2500 struct dc_link *link, 2501 struct hdcp_protection_message *message_info); 2502 bool dc_is_dmcu_initialized(struct dc *dc); 2503 2504 enum dc_status dc_set_clock(struct dc *dc, enum dc_clock_type clock_type, uint32_t clk_khz, uint32_t stepping); 2505 void dc_get_clock(struct dc *dc, enum dc_clock_type clock_type, struct dc_clock_config *clock_cfg); 2506 2507 bool dc_is_plane_eligible_for_idle_optimizations(struct dc *dc, 2508 unsigned int pitch, 2509 unsigned int height, 2510 enum surface_pixel_format format, 2511 struct dc_cursor_attributes *cursor_attr); 2512 2513 #define dc_allow_idle_optimizations(dc, allow) dc_allow_idle_optimizations_internal(dc, allow, __func__) 2514 #define dc_exit_ips_for_hw_access(dc) dc_exit_ips_for_hw_access_internal(dc, __func__) 2515 2516 void dc_allow_idle_optimizations_internal(struct dc *dc, bool allow, const char *caller_name); 2517 void dc_exit_ips_for_hw_access_internal(struct dc *dc, const char *caller_name); 2518 bool dc_dmub_is_ips_idle_state(struct dc *dc); 2519 2520 /* set min and max memory clock to lowest and highest DPM level, respectively */ 2521 void dc_unlock_memory_clock_frequency(struct dc *dc); 2522 2523 /* set min memory clock to the min required for current mode, max to maxDPM */ 2524 void dc_lock_memory_clock_frequency(struct dc *dc); 2525 2526 /* set soft max for memclk, to be used for AC/DC switching clock limitations */ 2527 void dc_enable_dcmode_clk_limit(struct dc *dc, bool enable); 2528 2529 /* cleanup on driver unload */ 2530 void dc_hardware_release(struct dc *dc); 2531 2532 /* disables fw based mclk switch */ 2533 void dc_mclk_switch_using_fw_based_vblank_stretch_shut_down(struct dc *dc); 2534 2535 bool dc_set_psr_allow_active(struct dc *dc, bool enable); 2536 2537 bool dc_set_replay_allow_active(struct dc *dc, bool active); 2538 2539 bool dc_set_ips_disable(struct dc *dc, unsigned int disable_ips); 2540 2541 void dc_z10_restore(const struct dc *dc); 2542 void dc_z10_save_init(struct dc *dc); 2543 2544 bool dc_is_dmub_outbox_supported(struct dc *dc); 2545 bool dc_enable_dmub_notifications(struct dc *dc); 2546 2547 bool dc_abm_save_restore( 2548 struct dc *dc, 2549 struct dc_stream_state *stream, 2550 struct abm_save_restore *pData); 2551 2552 void dc_enable_dmub_outbox(struct dc *dc); 2553 2554 bool dc_process_dmub_aux_transfer_async(struct dc *dc, 2555 uint32_t link_index, 2556 struct aux_payload *payload); 2557 2558 /* Get dc link index from dpia port index */ 2559 uint8_t get_link_index_from_dpia_port_index(const struct dc *dc, 2560 uint8_t dpia_port_index); 2561 2562 bool dc_process_dmub_set_config_async(struct dc *dc, 2563 uint32_t link_index, 2564 struct set_config_cmd_payload *payload, 2565 struct dmub_notification *notify); 2566 2567 enum dc_status dc_process_dmub_set_mst_slots(const struct dc *dc, 2568 uint32_t link_index, 2569 uint8_t mst_alloc_slots, 2570 uint8_t *mst_slots_in_use); 2571 2572 void dc_process_dmub_dpia_set_tps_notification(const struct dc *dc, uint32_t link_index, uint8_t tps); 2573 2574 void dc_process_dmub_dpia_hpd_int_enable(const struct dc *dc, 2575 uint32_t hpd_int_enable); 2576 2577 void dc_print_dmub_diagnostic_data(const struct dc *dc); 2578 2579 void dc_query_current_properties(struct dc *dc, struct dc_current_properties *properties); 2580 2581 struct dc_power_profile { 2582 int power_level; /* Lower is better */ 2583 }; 2584 2585 struct dc_power_profile dc_get_power_profile_for_dc_state(const struct dc_state *context); 2586 2587 unsigned int dc_get_det_buffer_size_from_state(const struct dc_state *context); 2588 2589 /* DSC Interfaces */ 2590 #include "dc_dsc.h" 2591 2592 /* Disable acc mode Interfaces */ 2593 void dc_disable_accelerated_mode(struct dc *dc); 2594 2595 bool dc_is_timing_changed(struct dc_stream_state *cur_stream, 2596 struct dc_stream_state *new_stream); 2597 2598 #endif /* DC_INTERFACE_H_ */ 2599