1 /*
2 * Copyright 2023 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <drm/drm_drv.h>
24 #include <linux/vmalloc.h>
25 #include "amdgpu.h"
26 #include "amdgpu_psp.h"
27 #include "amdgpu_ucode.h"
28 #include "soc15_common.h"
29 #include "psp_v14_0.h"
30
31 #include "mp/mp_14_0_2_offset.h"
32 #include "mp/mp_14_0_2_sh_mask.h"
33
34 MODULE_FIRMWARE("amdgpu/psp_14_0_2_sos.bin");
35 MODULE_FIRMWARE("amdgpu/psp_14_0_2_ta.bin");
36 MODULE_FIRMWARE("amdgpu/psp_14_0_3_sos.bin");
37 MODULE_FIRMWARE("amdgpu/psp_14_0_3_ta.bin");
38 MODULE_FIRMWARE("amdgpu/psp_14_0_5_toc.bin");
39 MODULE_FIRMWARE("amdgpu/psp_14_0_5_ta.bin");
40
41 /* For large FW files the time to complete can be very long */
42 #define USBC_PD_POLLING_LIMIT_S 240
43
44 /* Read USB-PD from LFB */
45 #define GFX_CMD_USB_PD_USE_LFB 0x480
46
47 /* VBIOS gfl defines */
48 #define MBOX_READY_MASK 0x80000000
49 #define MBOX_STATUS_MASK 0x0000FFFF
50 #define MBOX_COMMAND_MASK 0x00FF0000
51 #define MBOX_READY_FLAG 0x80000000
52 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
53 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
54 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
55
56 /* memory training timeout define */
57 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
58
psp_v14_0_init_microcode(struct psp_context * psp)59 static int psp_v14_0_init_microcode(struct psp_context *psp)
60 {
61 struct amdgpu_device *adev = psp->adev;
62 char ucode_prefix[30];
63 int err = 0;
64
65 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
66
67 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
68 case IP_VERSION(14, 0, 2):
69 case IP_VERSION(14, 0, 3):
70 err = psp_init_sos_microcode(psp, ucode_prefix);
71 if (err)
72 return err;
73 err = psp_init_ta_microcode(psp, ucode_prefix);
74 if (err)
75 return err;
76 break;
77 case IP_VERSION(14, 0, 5):
78 err = psp_init_toc_microcode(psp, ucode_prefix);
79 if (err)
80 return err;
81 err = psp_init_ta_microcode(psp, ucode_prefix);
82 if (err)
83 return err;
84 break;
85 default:
86 BUG();
87 }
88
89 return 0;
90 }
91
psp_v14_0_is_sos_alive(struct psp_context * psp)92 static bool psp_v14_0_is_sos_alive(struct psp_context *psp)
93 {
94 struct amdgpu_device *adev = psp->adev;
95 uint32_t sol_reg;
96
97 sol_reg = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81);
98
99 return sol_reg != 0x0;
100 }
101
psp_v14_0_wait_for_bootloader(struct psp_context * psp)102 static int psp_v14_0_wait_for_bootloader(struct psp_context *psp)
103 {
104 struct amdgpu_device *adev = psp->adev;
105
106 int ret;
107 int retry_loop;
108
109 for (retry_loop = 0; retry_loop < 10; retry_loop++) {
110 /* Wait for bootloader to signify that is
111 ready having bit 31 of C2PMSG_35 set to 1 */
112 ret = psp_wait_for(psp,
113 SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
114 0x80000000,
115 0x80000000,
116 false);
117
118 if (ret == 0)
119 return 0;
120 }
121
122 return ret;
123 }
124
psp_v14_0_bootloader_load_component(struct psp_context * psp,struct psp_bin_desc * bin_desc,enum psp_bootloader_cmd bl_cmd)125 static int psp_v14_0_bootloader_load_component(struct psp_context *psp,
126 struct psp_bin_desc *bin_desc,
127 enum psp_bootloader_cmd bl_cmd)
128 {
129 int ret;
130 uint32_t psp_gfxdrv_command_reg = 0;
131 struct amdgpu_device *adev = psp->adev;
132
133 /* Check tOS sign of life register to confirm sys driver and sOS
134 * are already been loaded.
135 */
136 if (psp_v14_0_is_sos_alive(psp))
137 return 0;
138
139 ret = psp_v14_0_wait_for_bootloader(psp);
140 if (ret)
141 return ret;
142
143 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
144
145 /* Copy PSP KDB binary to memory */
146 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
147
148 /* Provide the PSP KDB to bootloader */
149 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36,
150 (uint32_t)(psp->fw_pri_mc_addr >> 20));
151 psp_gfxdrv_command_reg = bl_cmd;
152 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35,
153 psp_gfxdrv_command_reg);
154
155 ret = psp_v14_0_wait_for_bootloader(psp);
156
157 return ret;
158 }
159
psp_v14_0_bootloader_load_kdb(struct psp_context * psp)160 static int psp_v14_0_bootloader_load_kdb(struct psp_context *psp)
161 {
162 return psp_v14_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
163 }
164
psp_v14_0_bootloader_load_spl(struct psp_context * psp)165 static int psp_v14_0_bootloader_load_spl(struct psp_context *psp)
166 {
167 return psp_v14_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE);
168 }
169
psp_v14_0_bootloader_load_sysdrv(struct psp_context * psp)170 static int psp_v14_0_bootloader_load_sysdrv(struct psp_context *psp)
171 {
172 return psp_v14_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
173 }
174
psp_v14_0_bootloader_load_soc_drv(struct psp_context * psp)175 static int psp_v14_0_bootloader_load_soc_drv(struct psp_context *psp)
176 {
177 return psp_v14_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
178 }
179
psp_v14_0_bootloader_load_intf_drv(struct psp_context * psp)180 static int psp_v14_0_bootloader_load_intf_drv(struct psp_context *psp)
181 {
182 return psp_v14_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
183 }
184
psp_v14_0_bootloader_load_dbg_drv(struct psp_context * psp)185 static int psp_v14_0_bootloader_load_dbg_drv(struct psp_context *psp)
186 {
187 /* dbg_drv was renamed to had_drv in psp v14 */
188 return psp_v14_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_HADDRV);
189 }
190
psp_v14_0_bootloader_load_ras_drv(struct psp_context * psp)191 static int psp_v14_0_bootloader_load_ras_drv(struct psp_context *psp)
192 {
193 return psp_v14_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
194 }
195
psp_v14_0_bootloader_load_ipkeymgr_drv(struct psp_context * psp)196 static int psp_v14_0_bootloader_load_ipkeymgr_drv(struct psp_context *psp)
197 {
198 return psp_v14_0_bootloader_load_component(psp, &psp->ipkeymgr_drv, PSP_BL__LOAD_IPKEYMGRDRV);
199 }
200
psp_v14_0_bootloader_load_sos(struct psp_context * psp)201 static int psp_v14_0_bootloader_load_sos(struct psp_context *psp)
202 {
203 int ret;
204 unsigned int psp_gfxdrv_command_reg = 0;
205 struct amdgpu_device *adev = psp->adev;
206
207 /* Check sOS sign of life register to confirm sys driver and sOS
208 * are already been loaded.
209 */
210 if (psp_v14_0_is_sos_alive(psp))
211 return 0;
212
213 ret = psp_v14_0_wait_for_bootloader(psp);
214 if (ret)
215 return ret;
216
217 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
218
219 /* Copy Secure OS binary to PSP memory */
220 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
221
222 /* Provide the PSP secure OS to bootloader */
223 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36,
224 (uint32_t)(psp->fw_pri_mc_addr >> 20));
225 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
226 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35,
227 psp_gfxdrv_command_reg);
228
229 /* there might be handshake issue with hardware which needs delay */
230 mdelay(20);
231 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_81),
232 RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_81),
233 0, true);
234
235 return ret;
236 }
237
psp_v14_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)238 static int psp_v14_0_ring_stop(struct psp_context *psp,
239 enum psp_ring_type ring_type)
240 {
241 int ret = 0;
242 struct amdgpu_device *adev = psp->adev;
243
244 if (amdgpu_sriov_vf(adev)) {
245 /* Write the ring destroy command*/
246 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
247 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
248 /* there might be handshake issue with hardware which needs delay */
249 mdelay(20);
250 /* Wait for response flag (bit 31) */
251 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
252 0x80000000, 0x80000000, false);
253 } else {
254 /* Write the ring destroy command*/
255 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64,
256 GFX_CTRL_CMD_ID_DESTROY_RINGS);
257 /* there might be handshake issue with hardware which needs delay */
258 mdelay(20);
259 /* Wait for response flag (bit 31) */
260 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
261 0x80000000, 0x80000000, false);
262 }
263
264 return ret;
265 }
266
psp_v14_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)267 static int psp_v14_0_ring_create(struct psp_context *psp,
268 enum psp_ring_type ring_type)
269 {
270 int ret = 0;
271 unsigned int psp_ring_reg = 0;
272 struct psp_ring *ring = &psp->km_ring;
273 struct amdgpu_device *adev = psp->adev;
274
275 if (amdgpu_sriov_vf(adev)) {
276 ret = psp_v14_0_ring_stop(psp, ring_type);
277 if (ret) {
278 DRM_ERROR("psp_v14_0_ring_stop_sriov failed!\n");
279 return ret;
280 }
281
282 /* Write low address of the ring to C2PMSG_102 */
283 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
284 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, psp_ring_reg);
285 /* Write high address of the ring to C2PMSG_103 */
286 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
287 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_103, psp_ring_reg);
288
289 /* Write the ring initialization command to C2PMSG_101 */
290 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
291 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
292
293 /* there might be handshake issue with hardware which needs delay */
294 mdelay(20);
295
296 /* Wait for response flag (bit 31) in C2PMSG_101 */
297 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_101),
298 0x80000000, 0x8000FFFF, false);
299
300 } else {
301 /* Wait for sOS ready for ring creation */
302 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
303 0x80000000, 0x80000000, false);
304 if (ret) {
305 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
306 return ret;
307 }
308
309 /* Write low address of the ring to C2PMSG_69 */
310 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
311 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_69, psp_ring_reg);
312 /* Write high address of the ring to C2PMSG_70 */
313 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
314 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_70, psp_ring_reg);
315 /* Write size of ring to C2PMSG_71 */
316 psp_ring_reg = ring->ring_size;
317 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_71, psp_ring_reg);
318 /* Write the ring initialization command to C2PMSG_64 */
319 psp_ring_reg = ring_type;
320 psp_ring_reg = psp_ring_reg << 16;
321 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_64, psp_ring_reg);
322
323 /* there might be handshake issue with hardware which needs delay */
324 mdelay(20);
325
326 /* Wait for response flag (bit 31) in C2PMSG_64 */
327 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_64),
328 0x80000000, 0x8000FFFF, false);
329 }
330
331 return ret;
332 }
333
psp_v14_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)334 static int psp_v14_0_ring_destroy(struct psp_context *psp,
335 enum psp_ring_type ring_type)
336 {
337 int ret = 0;
338 struct psp_ring *ring = &psp->km_ring;
339 struct amdgpu_device *adev = psp->adev;
340
341 ret = psp_v14_0_ring_stop(psp, ring_type);
342 if (ret)
343 DRM_ERROR("Fail to stop psp ring\n");
344
345 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
346 &ring->ring_mem_mc_addr,
347 (void **)&ring->ring_mem);
348
349 return ret;
350 }
351
psp_v14_0_ring_get_wptr(struct psp_context * psp)352 static uint32_t psp_v14_0_ring_get_wptr(struct psp_context *psp)
353 {
354 uint32_t data;
355 struct amdgpu_device *adev = psp->adev;
356
357 if (amdgpu_sriov_vf(adev))
358 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102);
359 else
360 data = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67);
361
362 return data;
363 }
364
psp_v14_0_ring_set_wptr(struct psp_context * psp,uint32_t value)365 static void psp_v14_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
366 {
367 struct amdgpu_device *adev = psp->adev;
368
369 if (amdgpu_sriov_vf(adev)) {
370 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_102, value);
371 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_101,
372 GFX_CTRL_CMD_ID_CONSUME_CMD);
373 } else
374 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_67, value);
375 }
376
psp_v14_0_memory_training_send_msg(struct psp_context * psp,int msg)377 static int psp_v14_0_memory_training_send_msg(struct psp_context *psp, int msg)
378 {
379 int ret;
380 int i;
381 uint32_t data_32;
382 int max_wait;
383 struct amdgpu_device *adev = psp->adev;
384
385 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
386 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, data_32);
387 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, msg);
388
389 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
390 for (i = 0; i < max_wait; i++) {
391 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
392 0x80000000, 0x80000000, false);
393 if (ret == 0)
394 break;
395 }
396 if (i < max_wait)
397 ret = 0;
398 else
399 ret = -ETIME;
400
401 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
402 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
403 (ret == 0) ? "succeed" : "failed",
404 i, adev->usec_timeout/1000);
405 return ret;
406 }
407
408
psp_v14_0_memory_training(struct psp_context * psp,uint32_t ops)409 static int psp_v14_0_memory_training(struct psp_context *psp, uint32_t ops)
410 {
411 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
412 uint32_t *pcache = (uint32_t *)ctx->sys_cache;
413 struct amdgpu_device *adev = psp->adev;
414 uint32_t p2c_header[4];
415 uint32_t sz;
416 void *buf;
417 int ret, idx;
418
419 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
420 dev_dbg(adev->dev, "Memory training is not supported.\n");
421 return 0;
422 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
423 dev_err(adev->dev, "Memory training initialization failure.\n");
424 return -EINVAL;
425 }
426
427 if (psp_v14_0_is_sos_alive(psp)) {
428 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
429 return 0;
430 }
431
432 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
433 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
434 pcache[0], pcache[1], pcache[2], pcache[3],
435 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
436
437 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
438 dev_dbg(adev->dev, "Short training depends on restore.\n");
439 ops |= PSP_MEM_TRAIN_RESTORE;
440 }
441
442 if ((ops & PSP_MEM_TRAIN_RESTORE) &&
443 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
444 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
445 ops |= PSP_MEM_TRAIN_SAVE;
446 }
447
448 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
449 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
450 pcache[3] == p2c_header[3])) {
451 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
452 ops |= PSP_MEM_TRAIN_SAVE;
453 }
454
455 if ((ops & PSP_MEM_TRAIN_SAVE) &&
456 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
457 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
458 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
459 }
460
461 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
462 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
463 ops |= PSP_MEM_TRAIN_SAVE;
464 }
465
466 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
467
468 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
469 /*
470 * Long training will encroach a certain amount on the bottom of VRAM;
471 * save the content from the bottom of VRAM to system memory
472 * before training, and restore it after training to avoid
473 * VRAM corruption.
474 */
475 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;
476
477 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
478 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
479 adev->gmc.visible_vram_size,
480 adev->mman.aper_base_kaddr);
481 return -EINVAL;
482 }
483
484 buf = vmalloc(sz);
485 if (!buf) {
486 dev_err(adev->dev, "failed to allocate system memory.\n");
487 return -ENOMEM;
488 }
489
490 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
491 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
492 ret = psp_v14_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
493 if (ret) {
494 DRM_ERROR("Send long training msg failed.\n");
495 vfree(buf);
496 drm_dev_exit(idx);
497 return ret;
498 }
499
500 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
501 amdgpu_device_flush_hdp(adev, NULL);
502 vfree(buf);
503 drm_dev_exit(idx);
504 } else {
505 vfree(buf);
506 return -ENODEV;
507 }
508 }
509
510 if (ops & PSP_MEM_TRAIN_SAVE) {
511 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
512 }
513
514 if (ops & PSP_MEM_TRAIN_RESTORE) {
515 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
516 }
517
518 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
519 ret = psp_v14_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
520 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
521 if (ret) {
522 dev_err(adev->dev, "send training msg failed.\n");
523 return ret;
524 }
525 }
526 ctx->training_cnt++;
527 return 0;
528 }
529
psp_v14_0_load_usbc_pd_fw(struct psp_context * psp,uint64_t fw_pri_mc_addr)530 static int psp_v14_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
531 {
532 struct amdgpu_device *adev = psp->adev;
533 uint32_t reg_status;
534 int ret, i = 0;
535
536 /*
537 * LFB address which is aligned to 1MB address and has to be
538 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
539 * register
540 */
541 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
542
543 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
544 0x80000000, 0x80000000, false);
545 if (ret)
546 return ret;
547
548 /* Fireup interrupt so PSP can pick up the address */
549 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
550
551 /* FW load takes very long time */
552 do {
553 msleep(1000);
554 reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35);
555
556 if (reg_status & 0x80000000)
557 goto done;
558
559 } while (++i < USBC_PD_POLLING_LIMIT_S);
560
561 return -ETIME;
562 done:
563
564 if ((reg_status & 0xFFFF) != 0) {
565 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
566 reg_status & 0xFFFF);
567 return -EIO;
568 }
569
570 return 0;
571 }
572
psp_v14_0_read_usbc_pd_fw(struct psp_context * psp,uint32_t * fw_ver)573 static int psp_v14_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
574 {
575 struct amdgpu_device *adev = psp->adev;
576 int ret;
577
578 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
579
580 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_35),
581 0x80000000, 0x80000000, false);
582 if (!ret)
583 *fw_ver = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_36);
584
585 return ret;
586 }
587
psp_v14_0_exec_spi_cmd(struct psp_context * psp,int cmd)588 static int psp_v14_0_exec_spi_cmd(struct psp_context *psp, int cmd)
589 {
590 uint32_t reg_status = 0, reg_val = 0;
591 struct amdgpu_device *adev = psp->adev;
592 int ret;
593
594 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
595 reg_val |= (cmd << 16);
596 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115, reg_val);
597
598 /* Ring the doorbell */
599 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_73, 1);
600
601 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
602 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
603 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
604 else
605 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
606 MBOX_READY_FLAG, MBOX_READY_MASK, false);
607
608 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
609 MBOX_READY_FLAG, MBOX_READY_MASK, false);
610 if (ret) {
611 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
612 return ret;
613 }
614
615 reg_status = RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115);
616 if ((reg_status & 0xFFFF) != 0) {
617 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
618 cmd, reg_status & 0xFFFF);
619 return -EIO;
620 }
621
622 return 0;
623 }
624
psp_v14_0_update_spirom(struct psp_context * psp,uint64_t fw_pri_mc_addr)625 static int psp_v14_0_update_spirom(struct psp_context *psp,
626 uint64_t fw_pri_mc_addr)
627 {
628 struct amdgpu_device *adev = psp->adev;
629 int ret;
630
631 /* Confirm PSP is ready to start */
632 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMPASP_SMN_C2PMSG_115),
633 MBOX_READY_FLAG, MBOX_READY_MASK, false);
634 if (ret) {
635 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
636 return ret;
637 }
638
639 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
640
641 ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
642 if (ret)
643 return ret;
644
645 WREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
646
647 ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
648 if (ret)
649 return ret;
650
651 psp->vbflash_done = true;
652
653 ret = psp_v14_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
654 if (ret)
655 return ret;
656
657 return 0;
658 }
659
psp_v14_0_vbflash_status(struct psp_context * psp)660 static int psp_v14_0_vbflash_status(struct psp_context *psp)
661 {
662 struct amdgpu_device *adev = psp->adev;
663
664 return RREG32_SOC15(MP0, 0, regMPASP_SMN_C2PMSG_115);
665 }
666
667 static const struct psp_funcs psp_v14_0_funcs = {
668 .init_microcode = psp_v14_0_init_microcode,
669 .bootloader_load_kdb = psp_v14_0_bootloader_load_kdb,
670 .bootloader_load_spl = psp_v14_0_bootloader_load_spl,
671 .bootloader_load_sysdrv = psp_v14_0_bootloader_load_sysdrv,
672 .bootloader_load_soc_drv = psp_v14_0_bootloader_load_soc_drv,
673 .bootloader_load_intf_drv = psp_v14_0_bootloader_load_intf_drv,
674 .bootloader_load_dbg_drv = psp_v14_0_bootloader_load_dbg_drv,
675 .bootloader_load_ras_drv = psp_v14_0_bootloader_load_ras_drv,
676 .bootloader_load_ipkeymgr_drv = psp_v14_0_bootloader_load_ipkeymgr_drv,
677 .bootloader_load_sos = psp_v14_0_bootloader_load_sos,
678 .ring_create = psp_v14_0_ring_create,
679 .ring_stop = psp_v14_0_ring_stop,
680 .ring_destroy = psp_v14_0_ring_destroy,
681 .ring_get_wptr = psp_v14_0_ring_get_wptr,
682 .ring_set_wptr = psp_v14_0_ring_set_wptr,
683 .mem_training = psp_v14_0_memory_training,
684 .load_usbc_pd_fw = psp_v14_0_load_usbc_pd_fw,
685 .read_usbc_pd_fw = psp_v14_0_read_usbc_pd_fw,
686 .update_spirom = psp_v14_0_update_spirom,
687 .vbflash_stat = psp_v14_0_vbflash_status
688 };
689
psp_v14_0_set_psp_funcs(struct psp_context * psp)690 void psp_v14_0_set_psp_funcs(struct psp_context *psp)
691 {
692 psp->funcs = &psp_v14_0_funcs;
693 }
694