1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <drm/drm_drv.h>
24 #include <linux/vmalloc.h>
25 #include "amdgpu.h"
26 #include "amdgpu_psp.h"
27 #include "amdgpu_ucode.h"
28 #include "soc15_common.h"
29 #include "psp_v13_0.h"
30 #include "amdgpu_ras.h"
31
32 #include "mp/mp_13_0_2_offset.h"
33 #include "mp/mp_13_0_2_sh_mask.h"
34
35 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
36 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
37 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
38 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
39 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
41 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
45 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
46 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
47 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
48 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
49 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
50 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
51 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
52 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");
53 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");
54 MODULE_FIRMWARE("amdgpu/psp_13_0_12_sos.bin");
55 MODULE_FIRMWARE("amdgpu/psp_13_0_12_ta.bin");
56 MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin");
57 MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin");
58 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
59 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
60 MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin");
61 MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin");
62 MODULE_FIRMWARE("amdgpu/psp_14_0_4_toc.bin");
63 MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin");
64
65 /* For large FW files the time to complete can be very long */
66 #define USBC_PD_POLLING_LIMIT_S 240
67
68 /* Read USB-PD from LFB */
69 #define GFX_CMD_USB_PD_USE_LFB 0x480
70
71 /* Retry times for vmbx ready wait */
72 #define PSP_VMBX_POLLING_LIMIT 3000
73
74 /* VBIOS gfl defines */
75 #define MBOX_READY_MASK 0x80000000
76 #define MBOX_STATUS_MASK 0x0000FFFF
77 #define MBOX_COMMAND_MASK 0x00FF0000
78 #define MBOX_READY_FLAG 0x80000000
79 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO 0x2
80 #define C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI 0x3
81 #define C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE 0x4
82
83 /* memory training timeout define */
84 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
85
86 #define regMP1_PUB_SCRATCH0 0x3b10090
87
psp_v13_0_init_microcode(struct psp_context * psp)88 static int psp_v13_0_init_microcode(struct psp_context *psp)
89 {
90 struct amdgpu_device *adev = psp->adev;
91 char ucode_prefix[30];
92 int err = 0;
93
94 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
95
96 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
97 case IP_VERSION(13, 0, 2):
98 err = psp_init_sos_microcode(psp, ucode_prefix);
99 if (err)
100 return err;
101 /* It's not necessary to load ras ta on Guest side */
102 if (!amdgpu_sriov_vf(adev)) {
103 err = psp_init_ta_microcode(psp, ucode_prefix);
104 if (err)
105 return err;
106 }
107 break;
108 case IP_VERSION(13, 0, 1):
109 case IP_VERSION(13, 0, 3):
110 case IP_VERSION(13, 0, 5):
111 case IP_VERSION(13, 0, 8):
112 case IP_VERSION(13, 0, 11):
113 case IP_VERSION(14, 0, 0):
114 case IP_VERSION(14, 0, 1):
115 case IP_VERSION(14, 0, 4):
116 err = psp_init_toc_microcode(psp, ucode_prefix);
117 if (err)
118 return err;
119 err = psp_init_ta_microcode(psp, ucode_prefix);
120 if (err)
121 return err;
122 break;
123 case IP_VERSION(13, 0, 0):
124 case IP_VERSION(13, 0, 6):
125 case IP_VERSION(13, 0, 7):
126 case IP_VERSION(13, 0, 10):
127 case IP_VERSION(13, 0, 12):
128 case IP_VERSION(13, 0, 14):
129 err = psp_init_sos_microcode(psp, ucode_prefix);
130 if (err)
131 return err;
132 /* It's not necessary to load ras ta on Guest side */
133 err = psp_init_ta_microcode(psp, ucode_prefix);
134 if (err)
135 return err;
136 break;
137 default:
138 BUG();
139 }
140
141 return 0;
142 }
143
psp_v13_0_is_sos_alive(struct psp_context * psp)144 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
145 {
146 struct amdgpu_device *adev = psp->adev;
147 uint32_t sol_reg;
148
149 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
150
151 return sol_reg != 0x0;
152 }
153
psp_v13_0_wait_for_vmbx_ready(struct psp_context * psp)154 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)
155 {
156 struct amdgpu_device *adev = psp->adev;
157 int retry_loop, ret;
158
159 for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
160 /* Wait for bootloader to signify that is
161 ready having bit 31 of C2PMSG_33 set to 1 */
162 ret = psp_wait_for(
163 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33),
164 0x80000000, 0xffffffff, false);
165
166 if (ret == 0)
167 break;
168 }
169
170 if (ret)
171 dev_warn(adev->dev, "Bootloader wait timed out");
172
173 return ret;
174 }
175
psp_v13_0_wait_for_bootloader(struct psp_context * psp)176 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
177 {
178 struct amdgpu_device *adev = psp->adev;
179 int retry_loop, retry_cnt, ret;
180
181 retry_cnt =
182 ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
183 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
184 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ?
185 PSP_VMBX_POLLING_LIMIT :
186 10;
187 /* Wait for bootloader to signify that it is ready having bit 31 of
188 * C2PMSG_35 set to 1. All other bits are expected to be cleared.
189 * If there is an error in processing command, bits[7:0] will be set.
190 * This is applicable for PSP v13.0.6 and newer.
191 */
192 for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) {
193 ret = psp_wait_for(
194 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
195 0x80000000, 0xffffffff, false);
196
197 if (ret == 0)
198 return 0;
199 }
200
201 return ret;
202 }
203
psp_v13_0_wait_for_bootloader_steady_state(struct psp_context * psp)204 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp)
205 {
206 struct amdgpu_device *adev = psp->adev;
207 int ret;
208
209 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
210 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
211 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {
212 ret = psp_v13_0_wait_for_vmbx_ready(psp);
213 if (ret)
214 amdgpu_ras_query_boot_status(adev, 4);
215
216 ret = psp_v13_0_wait_for_bootloader(psp);
217 if (ret)
218 amdgpu_ras_query_boot_status(adev, 4);
219
220 return ret;
221 }
222
223 return 0;
224 }
225
psp_v13_0_bootloader_load_component(struct psp_context * psp,struct psp_bin_desc * bin_desc,enum psp_bootloader_cmd bl_cmd)226 static int psp_v13_0_bootloader_load_component(struct psp_context *psp,
227 struct psp_bin_desc *bin_desc,
228 enum psp_bootloader_cmd bl_cmd)
229 {
230 int ret;
231 uint32_t psp_gfxdrv_command_reg = 0;
232 struct amdgpu_device *adev = psp->adev;
233
234 /* Check tOS sign of life register to confirm sys driver and sOS
235 * are already been loaded.
236 */
237 if (psp_v13_0_is_sos_alive(psp))
238 return 0;
239
240 ret = psp_v13_0_wait_for_bootloader(psp);
241 if (ret)
242 return ret;
243
244 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
245
246 /* Copy PSP KDB binary to memory */
247 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
248
249 /* Provide the PSP KDB to bootloader */
250 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
251 (uint32_t)(psp->fw_pri_mc_addr >> 20));
252 psp_gfxdrv_command_reg = bl_cmd;
253 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
254 psp_gfxdrv_command_reg);
255
256 ret = psp_v13_0_wait_for_bootloader(psp);
257
258 return ret;
259 }
260
psp_v13_0_bootloader_load_kdb(struct psp_context * psp)261 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
262 {
263 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
264 }
265
psp_v13_0_bootloader_load_spl(struct psp_context * psp)266 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
267 {
268 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
269 }
270
psp_v13_0_bootloader_load_sysdrv(struct psp_context * psp)271 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
272 {
273 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
274 }
275
psp_v13_0_bootloader_load_soc_drv(struct psp_context * psp)276 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
277 {
278 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
279 }
280
psp_v13_0_bootloader_load_intf_drv(struct psp_context * psp)281 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
282 {
283 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
284 }
285
psp_v13_0_bootloader_load_dbg_drv(struct psp_context * psp)286 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
287 {
288 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
289 }
290
psp_v13_0_bootloader_load_ras_drv(struct psp_context * psp)291 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
292 {
293 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
294 }
295
psp_v13_0_bootloader_load_spdm_drv(struct psp_context * psp)296 static int psp_v13_0_bootloader_load_spdm_drv(struct psp_context *psp)
297 {
298 return psp_v13_0_bootloader_load_component(psp, &psp->spdm_drv, PSP_BL__LOAD_SPDMDRV);
299 }
300
psp_v13_0_init_sos_version(struct psp_context * psp)301 static inline void psp_v13_0_init_sos_version(struct psp_context *psp)
302 {
303 struct amdgpu_device *adev = psp->adev;
304
305 psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58);
306 }
307
psp_v13_0_bootloader_load_sos(struct psp_context * psp)308 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
309 {
310 int ret;
311 unsigned int psp_gfxdrv_command_reg = 0;
312 struct amdgpu_device *adev = psp->adev;
313
314 /* Check sOS sign of life register to confirm sys driver and sOS
315 * are already been loaded.
316 */
317 if (psp_v13_0_is_sos_alive(psp)) {
318 psp_v13_0_init_sos_version(psp);
319 return 0;
320 }
321
322 ret = psp_v13_0_wait_for_bootloader(psp);
323 if (ret)
324 return ret;
325
326 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
327
328 /* Copy Secure OS binary to PSP memory */
329 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
330
331 /* Provide the PSP secure OS to bootloader */
332 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
333 (uint32_t)(psp->fw_pri_mc_addr >> 20));
334 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
335 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
336 psp_gfxdrv_command_reg);
337
338 /* there might be handshake issue with hardware which needs delay */
339 mdelay(20);
340 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
341 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
342 0, true);
343
344 if (!ret)
345 psp_v13_0_init_sos_version(psp);
346
347 return ret;
348 }
349
psp_v13_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)350 static int psp_v13_0_ring_stop(struct psp_context *psp,
351 enum psp_ring_type ring_type)
352 {
353 int ret = 0;
354 struct amdgpu_device *adev = psp->adev;
355
356 if (amdgpu_sriov_vf(adev)) {
357 /* Write the ring destroy command*/
358 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
359 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
360 /* there might be handshake issue with hardware which needs delay */
361 mdelay(20);
362 /* Wait for response flag (bit 31) */
363 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
364 0x80000000, 0x80000000, false);
365 } else {
366 /* Write the ring destroy command*/
367 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
368 GFX_CTRL_CMD_ID_DESTROY_RINGS);
369 /* there might be handshake issue with hardware which needs delay */
370 mdelay(20);
371 /* Wait for response flag (bit 31) */
372 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
373 0x80000000, 0x80000000, false);
374 }
375
376 return ret;
377 }
378
psp_v13_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)379 static int psp_v13_0_ring_create(struct psp_context *psp,
380 enum psp_ring_type ring_type)
381 {
382 int ret = 0;
383 unsigned int psp_ring_reg = 0;
384 struct psp_ring *ring = &psp->km_ring;
385 struct amdgpu_device *adev = psp->adev;
386
387 if (amdgpu_sriov_vf(adev)) {
388 ret = psp_v13_0_ring_stop(psp, ring_type);
389 if (ret) {
390 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
391 return ret;
392 }
393
394 /* Write low address of the ring to C2PMSG_102 */
395 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
396 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
397 /* Write high address of the ring to C2PMSG_103 */
398 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
399 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
400
401 /* Write the ring initialization command to C2PMSG_101 */
402 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
403 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
404
405 /* there might be handshake issue with hardware which needs delay */
406 mdelay(20);
407
408 /* Wait for response flag (bit 31) in C2PMSG_101 */
409 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
410 0x80000000, 0x8000FFFF, false);
411
412 } else {
413 /* Wait for sOS ready for ring creation */
414 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
415 0x80000000, 0x80000000, false);
416 if (ret) {
417 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
418 return ret;
419 }
420
421 /* Write low address of the ring to C2PMSG_69 */
422 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
423 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
424 /* Write high address of the ring to C2PMSG_70 */
425 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
426 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
427 /* Write size of ring to C2PMSG_71 */
428 psp_ring_reg = ring->ring_size;
429 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
430 /* Write the ring initialization command to C2PMSG_64 */
431 psp_ring_reg = ring_type;
432 psp_ring_reg = psp_ring_reg << 16;
433 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
434
435 /* there might be handshake issue with hardware which needs delay */
436 mdelay(20);
437
438 /* Wait for response flag (bit 31) in C2PMSG_64 */
439 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
440 0x80000000, 0x8000FFFF, false);
441 }
442
443 return ret;
444 }
445
psp_v13_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)446 static int psp_v13_0_ring_destroy(struct psp_context *psp,
447 enum psp_ring_type ring_type)
448 {
449 int ret = 0;
450 struct psp_ring *ring = &psp->km_ring;
451 struct amdgpu_device *adev = psp->adev;
452
453 ret = psp_v13_0_ring_stop(psp, ring_type);
454 if (ret)
455 DRM_ERROR("Fail to stop psp ring\n");
456
457 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
458 &ring->ring_mem_mc_addr,
459 (void **)&ring->ring_mem);
460
461 return ret;
462 }
463
psp_v13_0_ring_get_wptr(struct psp_context * psp)464 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
465 {
466 uint32_t data;
467 struct amdgpu_device *adev = psp->adev;
468
469 if (amdgpu_sriov_vf(adev))
470 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
471 else
472 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
473
474 return data;
475 }
476
psp_v13_0_ring_set_wptr(struct psp_context * psp,uint32_t value)477 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
478 {
479 struct amdgpu_device *adev = psp->adev;
480
481 if (amdgpu_sriov_vf(adev)) {
482 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
483 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
484 GFX_CTRL_CMD_ID_CONSUME_CMD);
485 } else
486 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
487 }
488
psp_v13_0_memory_training_send_msg(struct psp_context * psp,int msg)489 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
490 {
491 int ret;
492 int i;
493 uint32_t data_32;
494 int max_wait;
495 struct amdgpu_device *adev = psp->adev;
496
497 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
498 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
499 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
500
501 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
502 for (i = 0; i < max_wait; i++) {
503 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
504 0x80000000, 0x80000000, false);
505 if (ret == 0)
506 break;
507 }
508 if (i < max_wait)
509 ret = 0;
510 else
511 ret = -ETIME;
512
513 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
514 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
515 (ret == 0) ? "succeed" : "failed",
516 i, adev->usec_timeout/1000);
517 return ret;
518 }
519
520
psp_v13_0_memory_training(struct psp_context * psp,uint32_t ops)521 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
522 {
523 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
524 uint32_t *pcache = (uint32_t *)ctx->sys_cache;
525 struct amdgpu_device *adev = psp->adev;
526 uint32_t p2c_header[4];
527 uint32_t sz;
528 void *buf;
529 int ret, idx;
530
531 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
532 dev_dbg(adev->dev, "Memory training is not supported.\n");
533 return 0;
534 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
535 dev_err(adev->dev, "Memory training initialization failure.\n");
536 return -EINVAL;
537 }
538
539 if (psp_v13_0_is_sos_alive(psp)) {
540 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
541 return 0;
542 }
543
544 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
545 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
546 pcache[0], pcache[1], pcache[2], pcache[3],
547 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
548
549 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
550 dev_dbg(adev->dev, "Short training depends on restore.\n");
551 ops |= PSP_MEM_TRAIN_RESTORE;
552 }
553
554 if ((ops & PSP_MEM_TRAIN_RESTORE) &&
555 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
556 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
557 ops |= PSP_MEM_TRAIN_SAVE;
558 }
559
560 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
561 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
562 pcache[3] == p2c_header[3])) {
563 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
564 ops |= PSP_MEM_TRAIN_SAVE;
565 }
566
567 if ((ops & PSP_MEM_TRAIN_SAVE) &&
568 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
569 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
570 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
571 }
572
573 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
574 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
575 ops |= PSP_MEM_TRAIN_SAVE;
576 }
577
578 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
579
580 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
581 /*
582 * Long training will encroach a certain amount on the bottom of VRAM;
583 * save the content from the bottom of VRAM to system memory
584 * before training, and restore it after training to avoid
585 * VRAM corruption.
586 */
587 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;
588
589 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
590 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
591 adev->gmc.visible_vram_size,
592 adev->mman.aper_base_kaddr);
593 return -EINVAL;
594 }
595
596 buf = vmalloc(sz);
597 if (!buf) {
598 dev_err(adev->dev, "failed to allocate system memory.\n");
599 return -ENOMEM;
600 }
601
602 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
603 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
604 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
605 if (ret) {
606 DRM_ERROR("Send long training msg failed.\n");
607 vfree(buf);
608 drm_dev_exit(idx);
609 return ret;
610 }
611
612 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
613 adev->hdp.funcs->flush_hdp(adev, NULL);
614 vfree(buf);
615 drm_dev_exit(idx);
616 } else {
617 vfree(buf);
618 return -ENODEV;
619 }
620 }
621
622 if (ops & PSP_MEM_TRAIN_SAVE) {
623 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
624 }
625
626 if (ops & PSP_MEM_TRAIN_RESTORE) {
627 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
628 }
629
630 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
631 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
632 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
633 if (ret) {
634 dev_err(adev->dev, "send training msg failed.\n");
635 return ret;
636 }
637 }
638 ctx->training_cnt++;
639 return 0;
640 }
641
psp_v13_0_load_usbc_pd_fw(struct psp_context * psp,uint64_t fw_pri_mc_addr)642 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
643 {
644 struct amdgpu_device *adev = psp->adev;
645 uint32_t reg_status;
646 int ret, i = 0;
647
648 /*
649 * LFB address which is aligned to 1MB address and has to be
650 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
651 * register
652 */
653 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
654
655 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
656 0x80000000, 0x80000000, false);
657 if (ret)
658 return ret;
659
660 /* Fireup interrupt so PSP can pick up the address */
661 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
662
663 /* FW load takes very long time */
664 do {
665 msleep(1000);
666 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
667
668 if (reg_status & 0x80000000)
669 goto done;
670
671 } while (++i < USBC_PD_POLLING_LIMIT_S);
672
673 return -ETIME;
674 done:
675
676 if ((reg_status & 0xFFFF) != 0) {
677 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
678 reg_status & 0xFFFF);
679 return -EIO;
680 }
681
682 return 0;
683 }
684
psp_v13_0_read_usbc_pd_fw(struct psp_context * psp,uint32_t * fw_ver)685 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
686 {
687 struct amdgpu_device *adev = psp->adev;
688 int ret;
689
690 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
691
692 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
693 0x80000000, 0x80000000, false);
694 if (!ret)
695 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
696
697 return ret;
698 }
699
psp_v13_0_exec_spi_cmd(struct psp_context * psp,int cmd)700 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
701 {
702 uint32_t reg_status = 0, reg_val = 0;
703 struct amdgpu_device *adev = psp->adev;
704 int ret;
705
706 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
707 reg_val |= (cmd << 16);
708 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val);
709
710 /* Ring the doorbell */
711 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
712
713 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE)
714 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
715 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
716 else
717 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
718 MBOX_READY_FLAG, MBOX_READY_MASK, false);
719 if (ret) {
720 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
721 return ret;
722 }
723
724 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
725 if ((reg_status & 0xFFFF) != 0) {
726 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
727 cmd, reg_status & 0xFFFF);
728 return -EIO;
729 }
730
731 return 0;
732 }
733
psp_v13_0_update_spirom(struct psp_context * psp,uint64_t fw_pri_mc_addr)734 static int psp_v13_0_update_spirom(struct psp_context *psp,
735 uint64_t fw_pri_mc_addr)
736 {
737 struct amdgpu_device *adev = psp->adev;
738 int ret;
739
740 /* Confirm PSP is ready to start */
741 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
742 MBOX_READY_FLAG, MBOX_READY_MASK, false);
743 if (ret) {
744 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
745 return ret;
746 }
747
748 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
749
750 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
751 if (ret)
752 return ret;
753
754 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
755
756 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
757 if (ret)
758 return ret;
759
760 psp->vbflash_done = true;
761
762 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
763 if (ret)
764 return ret;
765
766 return 0;
767 }
768
psp_v13_0_vbflash_status(struct psp_context * psp)769 static int psp_v13_0_vbflash_status(struct psp_context *psp)
770 {
771 struct amdgpu_device *adev = psp->adev;
772
773 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
774 }
775
psp_v13_0_fatal_error_recovery_quirk(struct psp_context * psp)776 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp)
777 {
778 struct amdgpu_device *adev = psp->adev;
779
780 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) {
781 uint32_t reg_data;
782 /* MP1 fatal error: trigger PSP dram read to unhalt PSP
783 * during MP1 triggered sync flood.
784 */
785 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
786 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
787
788 /* delay 1000ms for the mode1 reset for fatal error
789 * to be recovered back.
790 */
791 msleep(1000);
792 }
793
794 return 0;
795 }
796
psp_v13_0_get_ras_capability(struct psp_context * psp)797 static bool psp_v13_0_get_ras_capability(struct psp_context *psp)
798 {
799 struct amdgpu_device *adev = psp->adev;
800 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
801 u32 reg_data;
802
803 /* query ras cap should be done from host side */
804 if (amdgpu_sriov_vf(adev))
805 return false;
806
807 if (!con)
808 return false;
809
810 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
811 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
812 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) &&
813 (!(adev->flags & AMD_IS_APU))) {
814 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127);
815 adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0));
816 con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false;
817 return true;
818 } else {
819 return false;
820 }
821 }
822
psp_v13_0_is_aux_sos_load_required(struct psp_context * psp)823 static bool psp_v13_0_is_aux_sos_load_required(struct psp_context *psp)
824 {
825 struct amdgpu_device *adev = psp->adev;
826 u32 pmfw_ver;
827
828 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))
829 return false;
830
831 /* load 4e version of sos if pmfw version less than 85.115.0 */
832 pmfw_ver = RREG32(regMP1_PUB_SCRATCH0 / 4);
833
834 return (pmfw_ver < 0x557300);
835 }
836
psp_v13_0_is_reload_needed(struct psp_context * psp)837 static bool psp_v13_0_is_reload_needed(struct psp_context *psp)
838 {
839 uint32_t ucode_ver;
840
841 if (!psp_v13_0_is_sos_alive(psp))
842 return false;
843
844 /* Restrict reload support only to specific IP versions */
845 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) {
846 case IP_VERSION(13, 0, 2):
847 case IP_VERSION(13, 0, 6):
848 case IP_VERSION(13, 0, 14):
849 /* TOS version read from microcode header */
850 ucode_ver = psp->sos.fw_version;
851 /* Read TOS version from hardware */
852 psp_v13_0_init_sos_version(psp);
853 return (ucode_ver != psp->sos.fw_version);
854 default:
855 return false;
856 }
857
858 return false;
859 }
860
861 static const struct psp_funcs psp_v13_0_funcs = {
862 .init_microcode = psp_v13_0_init_microcode,
863 .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state,
864 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
865 .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
866 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
867 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
868 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
869 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
870 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
871 .bootloader_load_spdm_drv = psp_v13_0_bootloader_load_spdm_drv,
872 .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
873 .ring_create = psp_v13_0_ring_create,
874 .ring_stop = psp_v13_0_ring_stop,
875 .ring_destroy = psp_v13_0_ring_destroy,
876 .ring_get_wptr = psp_v13_0_ring_get_wptr,
877 .ring_set_wptr = psp_v13_0_ring_set_wptr,
878 .mem_training = psp_v13_0_memory_training,
879 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
880 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
881 .update_spirom = psp_v13_0_update_spirom,
882 .vbflash_stat = psp_v13_0_vbflash_status,
883 .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk,
884 .get_ras_capability = psp_v13_0_get_ras_capability,
885 .is_aux_sos_load_required = psp_v13_0_is_aux_sos_load_required,
886 .is_reload_needed = psp_v13_0_is_reload_needed,
887 };
888
psp_v13_0_set_psp_funcs(struct psp_context * psp)889 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
890 {
891 psp->funcs = &psp_v13_0_funcs;
892 }
893