1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <drm/drm_drv.h>
24 #include <linux/vmalloc.h>
25 #include "amdgpu.h"
26 #include "amdgpu_psp.h"
27 #include "amdgpu_ucode.h"
28 #include "soc15_common.h"
29 #include "psp_v13_0.h"
30 #include "amdgpu_ras.h"
31
32 #include "mp/mp_13_0_2_offset.h"
33 #include "mp/mp_13_0_2_sh_mask.h"
34
35 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
36 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
37 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
38 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
39 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
41 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
45 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos_kicker.bin");
46 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
47 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta_kicker.bin");
48 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
49 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
50 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
51 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
52 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
53 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
54 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");
55 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");
56 MODULE_FIRMWARE("amdgpu/psp_13_0_12_sos.bin");
57 MODULE_FIRMWARE("amdgpu/psp_13_0_12_ta.bin");
58 MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin");
59 MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin");
60 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
61 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
62 MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin");
63 MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin");
64 MODULE_FIRMWARE("amdgpu/psp_14_0_4_toc.bin");
65 MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin");
66
67 /* For large FW files the time to complete can be very long */
68 #define USBC_PD_POLLING_LIMIT_S 240
69
70 /* Read USB-PD from LFB */
71 #define GFX_CMD_USB_PD_USE_LFB 0x480
72
73 /* Retry times for vmbx ready wait */
74 #define PSP_VMBX_POLLING_LIMIT 3000
75
76 /* memory training timeout define */
77 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
78
79 #define regMP1_PUB_SCRATCH0 0x3b10090
80
81 #define PSP13_BL_STATUS_SIZE 100
82
psp_v13_0_init_microcode(struct psp_context * psp)83 static int psp_v13_0_init_microcode(struct psp_context *psp)
84 {
85 struct amdgpu_device *adev = psp->adev;
86 char ucode_prefix[30];
87 int err = 0;
88
89 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
90
91 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
92 case IP_VERSION(13, 0, 2):
93 err = psp_init_sos_microcode(psp, ucode_prefix);
94 if (err)
95 return err;
96 /* It's not necessary to load ras ta on Guest side */
97 if (!amdgpu_sriov_vf(adev)) {
98 err = psp_init_ta_microcode(psp, ucode_prefix);
99 if (err)
100 return err;
101 }
102 break;
103 case IP_VERSION(13, 0, 1):
104 case IP_VERSION(13, 0, 3):
105 case IP_VERSION(13, 0, 5):
106 case IP_VERSION(13, 0, 8):
107 case IP_VERSION(13, 0, 11):
108 case IP_VERSION(14, 0, 0):
109 case IP_VERSION(14, 0, 1):
110 case IP_VERSION(14, 0, 4):
111 err = psp_init_toc_microcode(psp, ucode_prefix);
112 if (err)
113 return err;
114 err = psp_init_ta_microcode(psp, ucode_prefix);
115 if (err)
116 return err;
117 break;
118 case IP_VERSION(13, 0, 0):
119 case IP_VERSION(13, 0, 6):
120 case IP_VERSION(13, 0, 7):
121 case IP_VERSION(13, 0, 10):
122 case IP_VERSION(13, 0, 12):
123 case IP_VERSION(13, 0, 14):
124 err = psp_init_sos_microcode(psp, ucode_prefix);
125 if (err)
126 return err;
127 /* It's not necessary to load ras ta on Guest side */
128 err = psp_init_ta_microcode(psp, ucode_prefix);
129 if (err)
130 return err;
131 break;
132 default:
133 BUG();
134 }
135
136 return 0;
137 }
138
psp_v13_0_is_sos_alive(struct psp_context * psp)139 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
140 {
141 struct amdgpu_device *adev = psp->adev;
142 uint32_t sol_reg;
143
144 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
145
146 return sol_reg != 0x0;
147 }
148
psp_v13_0_bootloader_print_status(struct psp_context * psp,const char * msg)149 static void psp_v13_0_bootloader_print_status(struct psp_context *psp,
150 const char *msg)
151 {
152 struct amdgpu_device *adev = psp->adev;
153 u32 bl_status_reg;
154 char bl_status_msg[PSP13_BL_STATUS_SIZE];
155 int i, at;
156
157 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
158 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
159 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {
160 at = 0;
161 for_each_inst(i, adev->aid_mask) {
162 bl_status_reg =
163 (SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_92)
164 << 2) +
165 adev->asic_funcs->encode_ext_smn_addressing(i);
166 at += snprintf(bl_status_msg + at,
167 PSP13_BL_STATUS_SIZE - at,
168 " status(%02i): 0x%08x", i,
169 RREG32_PCIE_EXT(bl_status_reg));
170 }
171 dev_info(adev->dev, "%s - %s", msg, bl_status_msg);
172 }
173 }
174
psp_v13_0_wait_for_vmbx_ready(struct psp_context * psp)175 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)
176 {
177 struct amdgpu_device *adev = psp->adev;
178 int retry_loop, ret;
179
180 for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
181 /* Wait for bootloader to signify that is
182 ready having bit 31 of C2PMSG_33 set to 1 */
183 ret = psp_wait_for(
184 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33),
185 0x80000000, 0xffffffff, PSP_WAITREG_NOVERBOSE);
186
187 if (ret == 0)
188 break;
189 }
190
191 if (ret)
192 dev_warn(adev->dev, "Bootloader wait timed out");
193
194 return ret;
195 }
196
psp_v13_0_wait_for_bootloader(struct psp_context * psp)197 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
198 {
199 struct amdgpu_device *adev = psp->adev;
200 int retry_loop, retry_cnt, ret;
201
202 retry_cnt =
203 ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
204 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
205 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ?
206 PSP_VMBX_POLLING_LIMIT :
207 10;
208 /* Wait for bootloader to signify that it is ready having bit 31 of
209 * C2PMSG_35 set to 1. All other bits are expected to be cleared.
210 * If there is an error in processing command, bits[7:0] will be set.
211 * This is applicable for PSP v13.0.6 and newer.
212 */
213 for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) {
214 ret = psp_wait_for(
215 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
216 0x80000000, 0xffffffff, PSP_WAITREG_NOVERBOSE);
217
218 if (ret == 0)
219 return 0;
220 if (retry_loop && !(retry_loop % 10))
221 psp_v13_0_bootloader_print_status(
222 psp, "Waiting for bootloader completion");
223 }
224
225 return ret;
226 }
227
psp_v13_0_wait_for_bootloader_steady_state(struct psp_context * psp)228 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp)
229 {
230 struct amdgpu_device *adev = psp->adev;
231 int ret;
232
233 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
234 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
235 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {
236 ret = psp_v13_0_wait_for_vmbx_ready(psp);
237 if (ret)
238 amdgpu_ras_query_boot_status(adev, 4);
239
240 ret = psp_v13_0_wait_for_bootloader(psp);
241 if (ret)
242 amdgpu_ras_query_boot_status(adev, 4);
243
244 return ret;
245 }
246
247 return 0;
248 }
249
psp_v13_0_bootloader_load_component(struct psp_context * psp,struct psp_bin_desc * bin_desc,enum psp_bootloader_cmd bl_cmd)250 static int psp_v13_0_bootloader_load_component(struct psp_context *psp,
251 struct psp_bin_desc *bin_desc,
252 enum psp_bootloader_cmd bl_cmd)
253 {
254 int ret;
255 uint32_t psp_gfxdrv_command_reg = 0;
256 struct amdgpu_device *adev = psp->adev;
257
258 /* Check tOS sign of life register to confirm sys driver and sOS
259 * are already been loaded.
260 */
261 if (psp_v13_0_is_sos_alive(psp))
262 return 0;
263
264 ret = psp_v13_0_wait_for_bootloader(psp);
265 if (ret)
266 return ret;
267
268 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
269
270 /* Copy PSP KDB binary to memory */
271 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
272
273 /* Provide the PSP KDB to bootloader */
274 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
275 (uint32_t)(psp->fw_pri_mc_addr >> 20));
276 psp_gfxdrv_command_reg = bl_cmd;
277 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
278 psp_gfxdrv_command_reg);
279
280 ret = psp_v13_0_wait_for_bootloader(psp);
281
282 return ret;
283 }
284
psp_v13_0_bootloader_load_kdb(struct psp_context * psp)285 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
286 {
287 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
288 }
289
psp_v13_0_bootloader_load_spl(struct psp_context * psp)290 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
291 {
292 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
293 }
294
psp_v13_0_bootloader_load_sysdrv(struct psp_context * psp)295 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
296 {
297 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
298 }
299
psp_v13_0_bootloader_load_soc_drv(struct psp_context * psp)300 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
301 {
302 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
303 }
304
psp_v13_0_bootloader_load_intf_drv(struct psp_context * psp)305 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
306 {
307 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
308 }
309
psp_v13_0_bootloader_load_dbg_drv(struct psp_context * psp)310 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
311 {
312 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
313 }
314
psp_v13_0_bootloader_load_ras_drv(struct psp_context * psp)315 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
316 {
317 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
318 }
319
psp_v13_0_bootloader_load_spdm_drv(struct psp_context * psp)320 static int psp_v13_0_bootloader_load_spdm_drv(struct psp_context *psp)
321 {
322 return psp_v13_0_bootloader_load_component(psp, &psp->spdm_drv, PSP_BL__LOAD_SPDMDRV);
323 }
324
psp_v13_0_init_sos_version(struct psp_context * psp)325 static inline void psp_v13_0_init_sos_version(struct psp_context *psp)
326 {
327 struct amdgpu_device *adev = psp->adev;
328
329 psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58);
330 }
331
psp_v13_0_bootloader_load_sos(struct psp_context * psp)332 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
333 {
334 int ret;
335 unsigned int psp_gfxdrv_command_reg = 0;
336 struct amdgpu_device *adev = psp->adev;
337
338 /* Check sOS sign of life register to confirm sys driver and sOS
339 * are already been loaded.
340 */
341 if (psp_v13_0_is_sos_alive(psp)) {
342 psp_v13_0_init_sos_version(psp);
343 return 0;
344 }
345
346 ret = psp_v13_0_wait_for_bootloader(psp);
347 if (ret)
348 return ret;
349
350 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
351
352 /* Copy Secure OS binary to PSP memory */
353 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
354
355 /* Provide the PSP secure OS to bootloader */
356 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
357 (uint32_t)(psp->fw_pri_mc_addr >> 20));
358 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
359 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
360 psp_gfxdrv_command_reg);
361
362 /* there might be handshake issue with hardware which needs delay */
363 mdelay(20);
364 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
365 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81), 0,
366 PSP_WAITREG_CHANGED);
367
368 if (!ret)
369 psp_v13_0_init_sos_version(psp);
370
371 return ret;
372 }
373
psp_v13_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)374 static int psp_v13_0_ring_stop(struct psp_context *psp,
375 enum psp_ring_type ring_type)
376 {
377 int ret = 0;
378 struct amdgpu_device *adev = psp->adev;
379
380 if (amdgpu_sriov_vf(adev)) {
381 /* Write the ring destroy command*/
382 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
383 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
384 /* there might be handshake issue with hardware which needs delay */
385 mdelay(20);
386 /* Wait for response flag (bit 31) */
387 ret = psp_wait_for(
388 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
389 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
390 } else {
391 /* Write the ring destroy command*/
392 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
393 GFX_CTRL_CMD_ID_DESTROY_RINGS);
394 /* there might be handshake issue with hardware which needs delay */
395 mdelay(20);
396 /* Wait for response flag (bit 31) */
397 ret = psp_wait_for(
398 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
399 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
400 }
401
402 return ret;
403 }
404
psp_v13_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)405 static int psp_v13_0_ring_create(struct psp_context *psp,
406 enum psp_ring_type ring_type)
407 {
408 int ret = 0;
409 unsigned int psp_ring_reg = 0;
410 struct psp_ring *ring = &psp->km_ring;
411 struct amdgpu_device *adev = psp->adev;
412
413 if (amdgpu_sriov_vf(adev)) {
414 ret = psp_v13_0_ring_stop(psp, ring_type);
415 if (ret) {
416 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
417 return ret;
418 }
419
420 /* Write low address of the ring to C2PMSG_102 */
421 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
422 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
423 /* Write high address of the ring to C2PMSG_103 */
424 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
425 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
426
427 /* Write the ring initialization command to C2PMSG_101 */
428 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
429 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
430
431 /* there might be handshake issue with hardware which needs delay */
432 mdelay(20);
433
434 /* Wait for response flag (bit 31) in C2PMSG_101 */
435 ret = psp_wait_for(
436 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
437 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
438
439 } else {
440 /* Wait for sOS ready for ring creation */
441 ret = psp_wait_for(
442 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
443 MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);
444 if (ret) {
445 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
446 return ret;
447 }
448
449 /* Write low address of the ring to C2PMSG_69 */
450 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
451 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
452 /* Write high address of the ring to C2PMSG_70 */
453 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
454 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
455 /* Write size of ring to C2PMSG_71 */
456 psp_ring_reg = ring->ring_size;
457 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
458 /* Write the ring initialization command to C2PMSG_64 */
459 psp_ring_reg = ring_type;
460 psp_ring_reg = psp_ring_reg << 16;
461 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
462
463 /* there might be handshake issue with hardware which needs delay */
464 mdelay(20);
465
466 /* Wait for response flag (bit 31) in C2PMSG_64 */
467 ret = psp_wait_for(
468 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
469 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
470 }
471
472 return ret;
473 }
474
psp_v13_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)475 static int psp_v13_0_ring_destroy(struct psp_context *psp,
476 enum psp_ring_type ring_type)
477 {
478 int ret = 0;
479 struct psp_ring *ring = &psp->km_ring;
480 struct amdgpu_device *adev = psp->adev;
481
482 ret = psp_v13_0_ring_stop(psp, ring_type);
483 if (ret)
484 DRM_ERROR("Fail to stop psp ring\n");
485
486 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
487 &ring->ring_mem_mc_addr,
488 (void **)&ring->ring_mem);
489
490 return ret;
491 }
492
psp_v13_0_ring_get_wptr(struct psp_context * psp)493 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
494 {
495 uint32_t data;
496 struct amdgpu_device *adev = psp->adev;
497
498 if (amdgpu_sriov_vf(adev))
499 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
500 else
501 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
502
503 return data;
504 }
505
psp_v13_0_ring_set_wptr(struct psp_context * psp,uint32_t value)506 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
507 {
508 struct amdgpu_device *adev = psp->adev;
509
510 if (amdgpu_sriov_vf(adev)) {
511 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
512 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
513 GFX_CTRL_CMD_ID_CONSUME_CMD);
514 } else
515 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
516 }
517
psp_v13_0_memory_training_send_msg(struct psp_context * psp,int msg)518 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
519 {
520 int ret;
521 int i;
522 uint32_t data_32;
523 int max_wait;
524 struct amdgpu_device *adev = psp->adev;
525
526 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
527 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
528 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
529
530 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
531 for (i = 0; i < max_wait; i++) {
532 ret = psp_wait_for(
533 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
534 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
535 if (ret == 0)
536 break;
537 }
538 if (i < max_wait)
539 ret = 0;
540 else
541 ret = -ETIME;
542
543 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
544 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
545 (ret == 0) ? "succeed" : "failed",
546 i, adev->usec_timeout/1000);
547 return ret;
548 }
549
550
psp_v13_0_memory_training(struct psp_context * psp,uint32_t ops)551 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
552 {
553 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
554 uint32_t *pcache = (uint32_t *)ctx->sys_cache;
555 struct amdgpu_device *adev = psp->adev;
556 uint32_t p2c_header[4];
557 uint32_t sz;
558 void *buf;
559 int ret, idx;
560
561 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
562 dev_dbg(adev->dev, "Memory training is not supported.\n");
563 return 0;
564 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
565 dev_err(adev->dev, "Memory training initialization failure.\n");
566 return -EINVAL;
567 }
568
569 if (psp_v13_0_is_sos_alive(psp)) {
570 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
571 return 0;
572 }
573
574 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
575 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
576 pcache[0], pcache[1], pcache[2], pcache[3],
577 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
578
579 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
580 dev_dbg(adev->dev, "Short training depends on restore.\n");
581 ops |= PSP_MEM_TRAIN_RESTORE;
582 }
583
584 if ((ops & PSP_MEM_TRAIN_RESTORE) &&
585 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
586 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
587 ops |= PSP_MEM_TRAIN_SAVE;
588 }
589
590 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
591 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
592 pcache[3] == p2c_header[3])) {
593 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
594 ops |= PSP_MEM_TRAIN_SAVE;
595 }
596
597 if ((ops & PSP_MEM_TRAIN_SAVE) &&
598 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
599 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
600 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
601 }
602
603 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
604 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
605 ops |= PSP_MEM_TRAIN_SAVE;
606 }
607
608 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
609
610 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
611 /*
612 * Long training will encroach a certain amount on the bottom of VRAM;
613 * save the content from the bottom of VRAM to system memory
614 * before training, and restore it after training to avoid
615 * VRAM corruption.
616 */
617 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;
618
619 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
620 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
621 adev->gmc.visible_vram_size,
622 adev->mman.aper_base_kaddr);
623 return -EINVAL;
624 }
625
626 buf = vmalloc(sz);
627 if (!buf) {
628 dev_err(adev->dev, "failed to allocate system memory.\n");
629 return -ENOMEM;
630 }
631
632 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
633 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
634 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
635 if (ret) {
636 DRM_ERROR("Send long training msg failed.\n");
637 vfree(buf);
638 drm_dev_exit(idx);
639 return ret;
640 }
641
642 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
643 amdgpu_device_flush_hdp(adev, NULL);
644 vfree(buf);
645 drm_dev_exit(idx);
646 } else {
647 vfree(buf);
648 return -ENODEV;
649 }
650 }
651
652 if (ops & PSP_MEM_TRAIN_SAVE) {
653 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
654 }
655
656 if (ops & PSP_MEM_TRAIN_RESTORE) {
657 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
658 }
659
660 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
661 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
662 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
663 if (ret) {
664 dev_err(adev->dev, "send training msg failed.\n");
665 return ret;
666 }
667 }
668 ctx->training_cnt++;
669 return 0;
670 }
671
psp_v13_0_load_usbc_pd_fw(struct psp_context * psp,uint64_t fw_pri_mc_addr)672 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
673 {
674 struct amdgpu_device *adev = psp->adev;
675 uint32_t reg_status;
676 int ret, i = 0;
677
678 /*
679 * LFB address which is aligned to 1MB address and has to be
680 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
681 * register
682 */
683 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
684
685 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
686 0x80000000, 0x80000000, 0);
687 if (ret)
688 return ret;
689
690 /* Fireup interrupt so PSP can pick up the address */
691 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
692
693 /* FW load takes very long time */
694 do {
695 msleep(1000);
696 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
697
698 if (reg_status & 0x80000000)
699 goto done;
700
701 } while (++i < USBC_PD_POLLING_LIMIT_S);
702
703 return -ETIME;
704 done:
705
706 if ((reg_status & 0xFFFF) != 0) {
707 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
708 reg_status & 0xFFFF);
709 return -EIO;
710 }
711
712 return 0;
713 }
714
psp_v13_0_read_usbc_pd_fw(struct psp_context * psp,uint32_t * fw_ver)715 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
716 {
717 struct amdgpu_device *adev = psp->adev;
718 int ret;
719
720 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
721
722 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
723 0x80000000, 0x80000000, 0);
724 if (!ret)
725 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
726
727 return ret;
728 }
729
psp_v13_0_exec_spi_cmd(struct psp_context * psp,int cmd)730 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
731 {
732 uint32_t reg_status = 0, reg_val = 0;
733 struct amdgpu_device *adev = psp->adev;
734 int ret;
735
736 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
737 reg_val |= (cmd << 16);
738 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val);
739
740 /* Ring the doorbell */
741 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
742
743 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE ||
744 cmd == C2PMSG_CMD_SPI_GET_FLASH_IMAGE)
745 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
746 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
747 else
748 ret = psp_wait_for(
749 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
750 MBOX_READY_FLAG, MBOX_READY_MASK, 0);
751 if (ret) {
752 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
753 return ret;
754 }
755
756 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
757 if ((reg_status & 0xFFFF) != 0) {
758 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
759 cmd, reg_status & 0xFFFF);
760 return -EIO;
761 }
762
763 return 0;
764 }
765
psp_v13_0_update_spirom(struct psp_context * psp,uint64_t fw_pri_mc_addr)766 static int psp_v13_0_update_spirom(struct psp_context *psp,
767 uint64_t fw_pri_mc_addr)
768 {
769 struct amdgpu_device *adev = psp->adev;
770 int ret;
771
772 /* Confirm PSP is ready to start */
773 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
774 MBOX_READY_FLAG, MBOX_READY_MASK, 0);
775 if (ret) {
776 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
777 return ret;
778 }
779
780 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
781
782 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
783 if (ret)
784 return ret;
785
786 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
787
788 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
789 if (ret)
790 return ret;
791
792 psp->vbflash_done = true;
793
794 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
795 if (ret)
796 return ret;
797
798 return 0;
799 }
800
psp_v13_0_dump_spirom(struct psp_context * psp,uint64_t fw_pri_mc_addr)801 static int psp_v13_0_dump_spirom(struct psp_context *psp,
802 uint64_t fw_pri_mc_addr)
803 {
804 struct amdgpu_device *adev = psp->adev;
805 int ret;
806
807 /* Confirm PSP is ready to start */
808 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
809 MBOX_READY_FLAG, MBOX_READY_MASK, 0);
810 if (ret) {
811 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
812 return ret;
813 }
814
815 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
816
817 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_LO);
818 if (ret)
819 return ret;
820
821 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
822
823 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI);
824 if (ret)
825 return ret;
826
827 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_FLASH_IMAGE);
828
829 return ret;
830 }
831
psp_v13_0_vbflash_status(struct psp_context * psp)832 static int psp_v13_0_vbflash_status(struct psp_context *psp)
833 {
834 struct amdgpu_device *adev = psp->adev;
835
836 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
837 }
838
psp_v13_0_fatal_error_recovery_quirk(struct psp_context * psp)839 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp)
840 {
841 struct amdgpu_device *adev = psp->adev;
842
843 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) {
844 uint32_t reg_data;
845 /* MP1 fatal error: trigger PSP dram read to unhalt PSP
846 * during MP1 triggered sync flood.
847 */
848 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
849 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
850
851 /* delay 1000ms for the mode1 reset for fatal error
852 * to be recovered back.
853 */
854 msleep(1000);
855 }
856
857 return 0;
858 }
859
psp_v13_0_get_ras_capability(struct psp_context * psp)860 static bool psp_v13_0_get_ras_capability(struct psp_context *psp)
861 {
862 struct amdgpu_device *adev = psp->adev;
863 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
864 u32 reg_data;
865
866 /* query ras cap should be done from host side */
867 if (amdgpu_sriov_vf(adev))
868 return false;
869
870 if (!con)
871 return false;
872
873 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
874 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
875 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) &&
876 (!(adev->flags & AMD_IS_APU))) {
877 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127);
878 adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0));
879 con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false;
880 return true;
881 } else {
882 return false;
883 }
884 }
885
psp_v13_0_is_aux_sos_load_required(struct psp_context * psp)886 static bool psp_v13_0_is_aux_sos_load_required(struct psp_context *psp)
887 {
888 struct amdgpu_device *adev = psp->adev;
889 u32 pmfw_ver;
890
891 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))
892 return false;
893
894 /* load 4e version of sos if pmfw version less than 85.115.0 */
895 pmfw_ver = RREG32(regMP1_PUB_SCRATCH0 / 4);
896
897 return (pmfw_ver < 0x557300);
898 }
899
psp_v13_0_is_reload_needed(struct psp_context * psp)900 static bool psp_v13_0_is_reload_needed(struct psp_context *psp)
901 {
902 uint32_t ucode_ver;
903
904 if (!psp_v13_0_is_sos_alive(psp))
905 return false;
906
907 /* Restrict reload support only to specific IP versions */
908 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) {
909 case IP_VERSION(13, 0, 2):
910 case IP_VERSION(13, 0, 6):
911 case IP_VERSION(13, 0, 14):
912 /* TOS version read from microcode header */
913 ucode_ver = psp->sos.fw_version;
914 /* Read TOS version from hardware */
915 psp_v13_0_init_sos_version(psp);
916 return (ucode_ver != psp->sos.fw_version);
917 default:
918 return false;
919 }
920
921 return false;
922 }
923
psp_v13_0_reg_program_no_ring(struct psp_context * psp,uint32_t val,enum psp_reg_prog_id id)924 static int psp_v13_0_reg_program_no_ring(struct psp_context *psp, uint32_t val,
925 enum psp_reg_prog_id id)
926 {
927 struct amdgpu_device *adev = psp->adev;
928 int ret = -EOPNOTSUPP;
929
930 /* PSP will broadcast the value to all instances */
931 if (amdgpu_sriov_vf(adev)) {
932 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_GBR_IH_SET);
933 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, id);
934 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, val);
935
936 ret = psp_wait_for(
937 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
938 0x80000000, 0x80000000, 0);
939 }
940
941 return ret;
942 }
943
944 static const struct psp_funcs psp_v13_0_funcs = {
945 .init_microcode = psp_v13_0_init_microcode,
946 .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state,
947 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
948 .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
949 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
950 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
951 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
952 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
953 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
954 .bootloader_load_spdm_drv = psp_v13_0_bootloader_load_spdm_drv,
955 .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
956 .ring_create = psp_v13_0_ring_create,
957 .ring_stop = psp_v13_0_ring_stop,
958 .ring_destroy = psp_v13_0_ring_destroy,
959 .ring_get_wptr = psp_v13_0_ring_get_wptr,
960 .ring_set_wptr = psp_v13_0_ring_set_wptr,
961 .mem_training = psp_v13_0_memory_training,
962 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
963 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
964 .update_spirom = psp_v13_0_update_spirom,
965 .dump_spirom = psp_v13_0_dump_spirom,
966 .vbflash_stat = psp_v13_0_vbflash_status,
967 .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk,
968 .get_ras_capability = psp_v13_0_get_ras_capability,
969 .is_aux_sos_load_required = psp_v13_0_is_aux_sos_load_required,
970 .is_reload_needed = psp_v13_0_is_reload_needed,
971 .reg_program_no_ring = psp_v13_0_reg_program_no_ring,
972 };
973
psp_v13_0_set_psp_funcs(struct psp_context * psp)974 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
975 {
976 psp->funcs = &psp_v13_0_funcs;
977 }
978