1 /*
2 * Copyright 2020 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include <drm/drm_drv.h>
24 #include <linux/vmalloc.h>
25 #include "amdgpu.h"
26 #include "amdgpu_psp.h"
27 #include "amdgpu_ucode.h"
28 #include "soc15_common.h"
29 #include "psp_v13_0.h"
30 #include "amdgpu_ras.h"
31
32 #include "mp/mp_13_0_2_offset.h"
33 #include "mp/mp_13_0_2_sh_mask.h"
34
35 MODULE_FIRMWARE("amdgpu/aldebaran_sos.bin");
36 MODULE_FIRMWARE("amdgpu/aldebaran_ta.bin");
37 MODULE_FIRMWARE("amdgpu/aldebaran_cap.bin");
38 MODULE_FIRMWARE("amdgpu/yellow_carp_toc.bin");
39 MODULE_FIRMWARE("amdgpu/yellow_carp_ta.bin");
40 MODULE_FIRMWARE("amdgpu/psp_13_0_5_toc.bin");
41 MODULE_FIRMWARE("amdgpu/psp_13_0_5_ta.bin");
42 MODULE_FIRMWARE("amdgpu/psp_13_0_8_toc.bin");
43 MODULE_FIRMWARE("amdgpu/psp_13_0_8_ta.bin");
44 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos.bin");
45 MODULE_FIRMWARE("amdgpu/psp_13_0_0_sos_kicker.bin");
46 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta.bin");
47 MODULE_FIRMWARE("amdgpu/psp_13_0_0_ta_kicker.bin");
48 MODULE_FIRMWARE("amdgpu/psp_13_0_7_sos.bin");
49 MODULE_FIRMWARE("amdgpu/psp_13_0_7_ta.bin");
50 MODULE_FIRMWARE("amdgpu/psp_13_0_10_sos.bin");
51 MODULE_FIRMWARE("amdgpu/psp_13_0_10_ta.bin");
52 MODULE_FIRMWARE("amdgpu/psp_13_0_11_toc.bin");
53 MODULE_FIRMWARE("amdgpu/psp_13_0_11_ta.bin");
54 MODULE_FIRMWARE("amdgpu/psp_13_0_6_sos.bin");
55 MODULE_FIRMWARE("amdgpu/psp_13_0_6_ta.bin");
56 MODULE_FIRMWARE("amdgpu/psp_13_0_12_sos.bin");
57 MODULE_FIRMWARE("amdgpu/psp_13_0_12_ta.bin");
58 MODULE_FIRMWARE("amdgpu/psp_13_0_14_sos.bin");
59 MODULE_FIRMWARE("amdgpu/psp_13_0_14_ta.bin");
60 MODULE_FIRMWARE("amdgpu/psp_14_0_0_toc.bin");
61 MODULE_FIRMWARE("amdgpu/psp_14_0_0_ta.bin");
62 MODULE_FIRMWARE("amdgpu/psp_14_0_1_toc.bin");
63 MODULE_FIRMWARE("amdgpu/psp_14_0_1_ta.bin");
64 MODULE_FIRMWARE("amdgpu/psp_14_0_4_toc.bin");
65 MODULE_FIRMWARE("amdgpu/psp_14_0_4_ta.bin");
66
67 /* For large FW files the time to complete can be very long */
68 #define USBC_PD_POLLING_LIMIT_S 240
69
70 /* Read USB-PD from LFB */
71 #define GFX_CMD_USB_PD_USE_LFB 0x480
72
73 /* Retry times for vmbx ready wait */
74 #define PSP_VMBX_POLLING_LIMIT 3000
75
76 /* memory training timeout define */
77 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
78
79 #define regMP1_PUB_SCRATCH0 0x3b10090
80
81 #define PSP13_BL_STATUS_SIZE 100
82
psp_v13_0_init_microcode(struct psp_context * psp)83 static int psp_v13_0_init_microcode(struct psp_context *psp)
84 {
85 struct amdgpu_device *adev = psp->adev;
86 char ucode_prefix[30];
87 int err = 0;
88
89 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
90
91 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
92 case IP_VERSION(13, 0, 2):
93 err = psp_init_sos_microcode(psp, ucode_prefix);
94 if (err)
95 return err;
96 /* It's not necessary to load ras ta on Guest side */
97 if (!amdgpu_sriov_vf(adev)) {
98 err = psp_init_ta_microcode(psp, ucode_prefix);
99 if (err)
100 return err;
101 }
102 break;
103 case IP_VERSION(13, 0, 1):
104 case IP_VERSION(13, 0, 3):
105 case IP_VERSION(13, 0, 5):
106 case IP_VERSION(13, 0, 8):
107 case IP_VERSION(13, 0, 11):
108 case IP_VERSION(14, 0, 0):
109 case IP_VERSION(14, 0, 1):
110 case IP_VERSION(14, 0, 4):
111 err = psp_init_toc_microcode(psp, ucode_prefix);
112 if (err)
113 return err;
114 err = psp_init_ta_microcode(psp, ucode_prefix);
115 if (err)
116 return err;
117 break;
118 case IP_VERSION(13, 0, 0):
119 case IP_VERSION(13, 0, 6):
120 case IP_VERSION(13, 0, 7):
121 case IP_VERSION(13, 0, 10):
122 case IP_VERSION(13, 0, 12):
123 case IP_VERSION(13, 0, 14):
124 err = psp_init_sos_microcode(psp, ucode_prefix);
125 if (err)
126 return err;
127 /* It's not necessary to load ras ta on Guest side */
128 err = psp_init_ta_microcode(psp, ucode_prefix);
129 if (err)
130 return err;
131 break;
132 default:
133 BUG();
134 }
135
136 return 0;
137 }
138
psp_v13_0_is_sos_alive(struct psp_context * psp)139 static bool psp_v13_0_is_sos_alive(struct psp_context *psp)
140 {
141 struct amdgpu_device *adev = psp->adev;
142 uint32_t sol_reg;
143
144 sol_reg = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81);
145
146 return sol_reg != 0x0;
147 }
148
psp_v13_0_bootloader_print_status(struct psp_context * psp,const char * msg)149 static void psp_v13_0_bootloader_print_status(struct psp_context *psp,
150 const char *msg)
151 {
152 struct amdgpu_device *adev = psp->adev;
153 u32 bl_status_reg;
154 char bl_status_msg[PSP13_BL_STATUS_SIZE];
155 int i, at;
156
157 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
158 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
159 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {
160 at = 0;
161 for_each_inst(i, adev->aid_mask) {
162 bl_status_reg =
163 (SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_92)
164 << 2) +
165 adev->asic_funcs->encode_ext_smn_addressing(i);
166 at += snprintf(bl_status_msg + at,
167 PSP13_BL_STATUS_SIZE - at,
168 " status(%02i): 0x%08x", i,
169 RREG32_PCIE_EXT(bl_status_reg));
170 }
171 dev_info(adev->dev, "%s - %s", msg, bl_status_msg);
172 }
173 }
174
psp_v13_0_wait_for_vmbx_ready(struct psp_context * psp)175 static int psp_v13_0_wait_for_vmbx_ready(struct psp_context *psp)
176 {
177 struct amdgpu_device *adev = psp->adev;
178 int retry_loop, ret;
179
180 for (retry_loop = 0; retry_loop < PSP_VMBX_POLLING_LIMIT; retry_loop++) {
181 /* Wait for bootloader to signify that is
182 ready having bit 31 of C2PMSG_33 set to 1 */
183 ret = psp_wait_for(
184 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_33),
185 0x80000000, 0xffffffff, false);
186
187 if (ret == 0)
188 break;
189 }
190
191 if (ret)
192 dev_warn(adev->dev, "Bootloader wait timed out");
193
194 return ret;
195 }
196
psp_v13_0_wait_for_bootloader(struct psp_context * psp)197 static int psp_v13_0_wait_for_bootloader(struct psp_context *psp)
198 {
199 struct amdgpu_device *adev = psp->adev;
200 int retry_loop, retry_cnt, ret;
201
202 retry_cnt =
203 ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
204 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
205 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14))) ?
206 PSP_VMBX_POLLING_LIMIT :
207 10;
208 /* Wait for bootloader to signify that it is ready having bit 31 of
209 * C2PMSG_35 set to 1. All other bits are expected to be cleared.
210 * If there is an error in processing command, bits[7:0] will be set.
211 * This is applicable for PSP v13.0.6 and newer.
212 */
213 for (retry_loop = 0; retry_loop < retry_cnt; retry_loop++) {
214 ret = psp_wait_for(
215 psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
216 0x80000000, 0xffffffff, false);
217
218 if (ret == 0)
219 return 0;
220 if (retry_loop && !(retry_loop % 10))
221 psp_v13_0_bootloader_print_status(
222 psp, "Waiting for bootloader completion");
223 }
224
225 return ret;
226 }
227
psp_v13_0_wait_for_bootloader_steady_state(struct psp_context * psp)228 static int psp_v13_0_wait_for_bootloader_steady_state(struct psp_context *psp)
229 {
230 struct amdgpu_device *adev = psp->adev;
231 int ret;
232
233 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
234 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
235 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) {
236 ret = psp_v13_0_wait_for_vmbx_ready(psp);
237 if (ret)
238 amdgpu_ras_query_boot_status(adev, 4);
239
240 ret = psp_v13_0_wait_for_bootloader(psp);
241 if (ret)
242 amdgpu_ras_query_boot_status(adev, 4);
243
244 return ret;
245 }
246
247 return 0;
248 }
249
psp_v13_0_bootloader_load_component(struct psp_context * psp,struct psp_bin_desc * bin_desc,enum psp_bootloader_cmd bl_cmd)250 static int psp_v13_0_bootloader_load_component(struct psp_context *psp,
251 struct psp_bin_desc *bin_desc,
252 enum psp_bootloader_cmd bl_cmd)
253 {
254 int ret;
255 uint32_t psp_gfxdrv_command_reg = 0;
256 struct amdgpu_device *adev = psp->adev;
257
258 /* Check tOS sign of life register to confirm sys driver and sOS
259 * are already been loaded.
260 */
261 if (psp_v13_0_is_sos_alive(psp))
262 return 0;
263
264 ret = psp_v13_0_wait_for_bootloader(psp);
265 if (ret)
266 return ret;
267
268 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
269
270 /* Copy PSP KDB binary to memory */
271 memcpy(psp->fw_pri_buf, bin_desc->start_addr, bin_desc->size_bytes);
272
273 /* Provide the PSP KDB to bootloader */
274 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
275 (uint32_t)(psp->fw_pri_mc_addr >> 20));
276 psp_gfxdrv_command_reg = bl_cmd;
277 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
278 psp_gfxdrv_command_reg);
279
280 ret = psp_v13_0_wait_for_bootloader(psp);
281
282 return ret;
283 }
284
psp_v13_0_bootloader_load_kdb(struct psp_context * psp)285 static int psp_v13_0_bootloader_load_kdb(struct psp_context *psp)
286 {
287 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
288 }
289
psp_v13_0_bootloader_load_spl(struct psp_context * psp)290 static int psp_v13_0_bootloader_load_spl(struct psp_context *psp)
291 {
292 return psp_v13_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_TOS_SPL_TABLE);
293 }
294
psp_v13_0_bootloader_load_sysdrv(struct psp_context * psp)295 static int psp_v13_0_bootloader_load_sysdrv(struct psp_context *psp)
296 {
297 return psp_v13_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
298 }
299
psp_v13_0_bootloader_load_soc_drv(struct psp_context * psp)300 static int psp_v13_0_bootloader_load_soc_drv(struct psp_context *psp)
301 {
302 return psp_v13_0_bootloader_load_component(psp, &psp->soc_drv, PSP_BL__LOAD_SOCDRV);
303 }
304
psp_v13_0_bootloader_load_intf_drv(struct psp_context * psp)305 static int psp_v13_0_bootloader_load_intf_drv(struct psp_context *psp)
306 {
307 return psp_v13_0_bootloader_load_component(psp, &psp->intf_drv, PSP_BL__LOAD_INTFDRV);
308 }
309
psp_v13_0_bootloader_load_dbg_drv(struct psp_context * psp)310 static int psp_v13_0_bootloader_load_dbg_drv(struct psp_context *psp)
311 {
312 return psp_v13_0_bootloader_load_component(psp, &psp->dbg_drv, PSP_BL__LOAD_DBGDRV);
313 }
314
psp_v13_0_bootloader_load_ras_drv(struct psp_context * psp)315 static int psp_v13_0_bootloader_load_ras_drv(struct psp_context *psp)
316 {
317 return psp_v13_0_bootloader_load_component(psp, &psp->ras_drv, PSP_BL__LOAD_RASDRV);
318 }
319
psp_v13_0_bootloader_load_spdm_drv(struct psp_context * psp)320 static int psp_v13_0_bootloader_load_spdm_drv(struct psp_context *psp)
321 {
322 return psp_v13_0_bootloader_load_component(psp, &psp->spdm_drv, PSP_BL__LOAD_SPDMDRV);
323 }
324
psp_v13_0_init_sos_version(struct psp_context * psp)325 static inline void psp_v13_0_init_sos_version(struct psp_context *psp)
326 {
327 struct amdgpu_device *adev = psp->adev;
328
329 psp->sos.fw_version = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_58);
330 }
331
psp_v13_0_bootloader_load_sos(struct psp_context * psp)332 static int psp_v13_0_bootloader_load_sos(struct psp_context *psp)
333 {
334 int ret;
335 unsigned int psp_gfxdrv_command_reg = 0;
336 struct amdgpu_device *adev = psp->adev;
337
338 /* Check sOS sign of life register to confirm sys driver and sOS
339 * are already been loaded.
340 */
341 if (psp_v13_0_is_sos_alive(psp)) {
342 psp_v13_0_init_sos_version(psp);
343 return 0;
344 }
345
346 ret = psp_v13_0_wait_for_bootloader(psp);
347 if (ret)
348 return ret;
349
350 memset(psp->fw_pri_buf, 0, PSP_1_MEG);
351
352 /* Copy Secure OS binary to PSP memory */
353 memcpy(psp->fw_pri_buf, psp->sos.start_addr, psp->sos.size_bytes);
354
355 /* Provide the PSP secure OS to bootloader */
356 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36,
357 (uint32_t)(psp->fw_pri_mc_addr >> 20));
358 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
359 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35,
360 psp_gfxdrv_command_reg);
361
362 /* there might be handshake issue with hardware which needs delay */
363 mdelay(20);
364 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_81),
365 RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_81),
366 0, true);
367
368 if (!ret)
369 psp_v13_0_init_sos_version(psp);
370
371 return ret;
372 }
373
psp_v13_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)374 static int psp_v13_0_ring_stop(struct psp_context *psp,
375 enum psp_ring_type ring_type)
376 {
377 int ret = 0;
378 struct amdgpu_device *adev = psp->adev;
379
380 if (amdgpu_sriov_vf(adev)) {
381 /* Write the ring destroy command*/
382 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
383 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
384 /* there might be handshake issue with hardware which needs delay */
385 mdelay(20);
386 /* Wait for response flag (bit 31) */
387 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
388 0x80000000, 0x80000000, false);
389 } else {
390 /* Write the ring destroy command*/
391 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64,
392 GFX_CTRL_CMD_ID_DESTROY_RINGS);
393 /* there might be handshake issue with hardware which needs delay */
394 mdelay(20);
395 /* Wait for response flag (bit 31) */
396 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
397 0x80000000, 0x80000000, false);
398 }
399
400 return ret;
401 }
402
psp_v13_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)403 static int psp_v13_0_ring_create(struct psp_context *psp,
404 enum psp_ring_type ring_type)
405 {
406 int ret = 0;
407 unsigned int psp_ring_reg = 0;
408 struct psp_ring *ring = &psp->km_ring;
409 struct amdgpu_device *adev = psp->adev;
410
411 if (amdgpu_sriov_vf(adev)) {
412 ret = psp_v13_0_ring_stop(psp, ring_type);
413 if (ret) {
414 DRM_ERROR("psp_v13_0_ring_stop_sriov failed!\n");
415 return ret;
416 }
417
418 /* Write low address of the ring to C2PMSG_102 */
419 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
420 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, psp_ring_reg);
421 /* Write high address of the ring to C2PMSG_103 */
422 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
423 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, psp_ring_reg);
424
425 /* Write the ring initialization command to C2PMSG_101 */
426 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
427 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
428
429 /* there might be handshake issue with hardware which needs delay */
430 mdelay(20);
431
432 /* Wait for response flag (bit 31) in C2PMSG_101 */
433 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
434 0x80000000, 0x8000FFFF, false);
435
436 } else {
437 /* Wait for sOS ready for ring creation */
438 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
439 0x80000000, 0x80000000, false);
440 if (ret) {
441 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
442 return ret;
443 }
444
445 /* Write low address of the ring to C2PMSG_69 */
446 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
447 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_69, psp_ring_reg);
448 /* Write high address of the ring to C2PMSG_70 */
449 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
450 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_70, psp_ring_reg);
451 /* Write size of ring to C2PMSG_71 */
452 psp_ring_reg = ring->ring_size;
453 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_71, psp_ring_reg);
454 /* Write the ring initialization command to C2PMSG_64 */
455 psp_ring_reg = ring_type;
456 psp_ring_reg = psp_ring_reg << 16;
457 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_64, psp_ring_reg);
458
459 /* there might be handshake issue with hardware which needs delay */
460 mdelay(20);
461
462 /* Wait for response flag (bit 31) in C2PMSG_64 */
463 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_64),
464 0x80000000, 0x8000FFFF, false);
465 }
466
467 return ret;
468 }
469
psp_v13_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)470 static int psp_v13_0_ring_destroy(struct psp_context *psp,
471 enum psp_ring_type ring_type)
472 {
473 int ret = 0;
474 struct psp_ring *ring = &psp->km_ring;
475 struct amdgpu_device *adev = psp->adev;
476
477 ret = psp_v13_0_ring_stop(psp, ring_type);
478 if (ret)
479 DRM_ERROR("Fail to stop psp ring\n");
480
481 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
482 &ring->ring_mem_mc_addr,
483 (void **)&ring->ring_mem);
484
485 return ret;
486 }
487
psp_v13_0_ring_get_wptr(struct psp_context * psp)488 static uint32_t psp_v13_0_ring_get_wptr(struct psp_context *psp)
489 {
490 uint32_t data;
491 struct amdgpu_device *adev = psp->adev;
492
493 if (amdgpu_sriov_vf(adev))
494 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102);
495 else
496 data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
497
498 return data;
499 }
500
psp_v13_0_ring_set_wptr(struct psp_context * psp,uint32_t value)501 static void psp_v13_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
502 {
503 struct amdgpu_device *adev = psp->adev;
504
505 if (amdgpu_sriov_vf(adev)) {
506 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, value);
507 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101,
508 GFX_CTRL_CMD_ID_CONSUME_CMD);
509 } else
510 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, value);
511 }
512
psp_v13_0_memory_training_send_msg(struct psp_context * psp,int msg)513 static int psp_v13_0_memory_training_send_msg(struct psp_context *psp, int msg)
514 {
515 int ret;
516 int i;
517 uint32_t data_32;
518 int max_wait;
519 struct amdgpu_device *adev = psp->adev;
520
521 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
522 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, data_32);
523 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, msg);
524
525 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
526 for (i = 0; i < max_wait; i++) {
527 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
528 0x80000000, 0x80000000, false);
529 if (ret == 0)
530 break;
531 }
532 if (i < max_wait)
533 ret = 0;
534 else
535 ret = -ETIME;
536
537 dev_dbg(adev->dev, "training %s %s, cost %d @ %d ms\n",
538 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
539 (ret == 0) ? "succeed" : "failed",
540 i, adev->usec_timeout/1000);
541 return ret;
542 }
543
544
psp_v13_0_memory_training(struct psp_context * psp,uint32_t ops)545 static int psp_v13_0_memory_training(struct psp_context *psp, uint32_t ops)
546 {
547 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
548 uint32_t *pcache = (uint32_t *)ctx->sys_cache;
549 struct amdgpu_device *adev = psp->adev;
550 uint32_t p2c_header[4];
551 uint32_t sz;
552 void *buf;
553 int ret, idx;
554
555 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
556 dev_dbg(adev->dev, "Memory training is not supported.\n");
557 return 0;
558 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
559 dev_err(adev->dev, "Memory training initialization failure.\n");
560 return -EINVAL;
561 }
562
563 if (psp_v13_0_is_sos_alive(psp)) {
564 dev_dbg(adev->dev, "SOS is alive, skip memory training.\n");
565 return 0;
566 }
567
568 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
569 dev_dbg(adev->dev, "sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
570 pcache[0], pcache[1], pcache[2], pcache[3],
571 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
572
573 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
574 dev_dbg(adev->dev, "Short training depends on restore.\n");
575 ops |= PSP_MEM_TRAIN_RESTORE;
576 }
577
578 if ((ops & PSP_MEM_TRAIN_RESTORE) &&
579 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
580 dev_dbg(adev->dev, "sys_cache[0] is invalid, restore depends on save.\n");
581 ops |= PSP_MEM_TRAIN_SAVE;
582 }
583
584 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
585 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
586 pcache[3] == p2c_header[3])) {
587 dev_dbg(adev->dev, "sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
588 ops |= PSP_MEM_TRAIN_SAVE;
589 }
590
591 if ((ops & PSP_MEM_TRAIN_SAVE) &&
592 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
593 dev_dbg(adev->dev, "p2c_header[0] is invalid, save depends on long training.\n");
594 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
595 }
596
597 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
598 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
599 ops |= PSP_MEM_TRAIN_SAVE;
600 }
601
602 dev_dbg(adev->dev, "Memory training ops:%x.\n", ops);
603
604 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
605 /*
606 * Long training will encroach a certain amount on the bottom of VRAM;
607 * save the content from the bottom of VRAM to system memory
608 * before training, and restore it after training to avoid
609 * VRAM corruption.
610 */
611 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;
612
613 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
614 dev_err(adev->dev, "visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
615 adev->gmc.visible_vram_size,
616 adev->mman.aper_base_kaddr);
617 return -EINVAL;
618 }
619
620 buf = vmalloc(sz);
621 if (!buf) {
622 dev_err(adev->dev, "failed to allocate system memory.\n");
623 return -ENOMEM;
624 }
625
626 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
627 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
628 ret = psp_v13_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
629 if (ret) {
630 DRM_ERROR("Send long training msg failed.\n");
631 vfree(buf);
632 drm_dev_exit(idx);
633 return ret;
634 }
635
636 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
637 amdgpu_device_flush_hdp(adev, NULL);
638 vfree(buf);
639 drm_dev_exit(idx);
640 } else {
641 vfree(buf);
642 return -ENODEV;
643 }
644 }
645
646 if (ops & PSP_MEM_TRAIN_SAVE) {
647 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
648 }
649
650 if (ops & PSP_MEM_TRAIN_RESTORE) {
651 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
652 }
653
654 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
655 ret = psp_v13_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
656 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
657 if (ret) {
658 dev_err(adev->dev, "send training msg failed.\n");
659 return ret;
660 }
661 }
662 ctx->training_cnt++;
663 return 0;
664 }
665
psp_v13_0_load_usbc_pd_fw(struct psp_context * psp,uint64_t fw_pri_mc_addr)666 static int psp_v13_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
667 {
668 struct amdgpu_device *adev = psp->adev;
669 uint32_t reg_status;
670 int ret, i = 0;
671
672 /*
673 * LFB address which is aligned to 1MB address and has to be
674 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
675 * register
676 */
677 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
678
679 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
680 0x80000000, 0x80000000, false);
681 if (ret)
682 return ret;
683
684 /* Fireup interrupt so PSP can pick up the address */
685 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
686
687 /* FW load takes very long time */
688 do {
689 msleep(1000);
690 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35);
691
692 if (reg_status & 0x80000000)
693 goto done;
694
695 } while (++i < USBC_PD_POLLING_LIMIT_S);
696
697 return -ETIME;
698 done:
699
700 if ((reg_status & 0xFFFF) != 0) {
701 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = %04x\n",
702 reg_status & 0xFFFF);
703 return -EIO;
704 }
705
706 return 0;
707 }
708
psp_v13_0_read_usbc_pd_fw(struct psp_context * psp,uint32_t * fw_ver)709 static int psp_v13_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
710 {
711 struct amdgpu_device *adev = psp->adev;
712 int ret;
713
714 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
715
716 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_35),
717 0x80000000, 0x80000000, false);
718 if (!ret)
719 *fw_ver = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_36);
720
721 return ret;
722 }
723
psp_v13_0_exec_spi_cmd(struct psp_context * psp,int cmd)724 static int psp_v13_0_exec_spi_cmd(struct psp_context *psp, int cmd)
725 {
726 uint32_t reg_status = 0, reg_val = 0;
727 struct amdgpu_device *adev = psp->adev;
728 int ret;
729
730 /* clear MBX ready (MBOX_READY_MASK bit is 0) and set update command */
731 reg_val |= (cmd << 16);
732 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115, reg_val);
733
734 /* Ring the doorbell */
735 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_73, 1);
736
737 if (cmd == C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE ||
738 cmd == C2PMSG_CMD_SPI_GET_FLASH_IMAGE)
739 ret = psp_wait_for_spirom_update(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
740 MBOX_READY_FLAG, MBOX_READY_MASK, PSP_SPIROM_UPDATE_TIMEOUT);
741 else
742 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
743 MBOX_READY_FLAG, MBOX_READY_MASK, false);
744 if (ret) {
745 dev_err(adev->dev, "SPI cmd %x timed out, ret = %d", cmd, ret);
746 return ret;
747 }
748
749 reg_status = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
750 if ((reg_status & 0xFFFF) != 0) {
751 dev_err(adev->dev, "SPI cmd %x failed, fail status = %04x\n",
752 cmd, reg_status & 0xFFFF);
753 return -EIO;
754 }
755
756 return 0;
757 }
758
psp_v13_0_update_spirom(struct psp_context * psp,uint64_t fw_pri_mc_addr)759 static int psp_v13_0_update_spirom(struct psp_context *psp,
760 uint64_t fw_pri_mc_addr)
761 {
762 struct amdgpu_device *adev = psp->adev;
763 int ret;
764
765 /* Confirm PSP is ready to start */
766 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
767 MBOX_READY_FLAG, MBOX_READY_MASK, false);
768 if (ret) {
769 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
770 return ret;
771 }
772
773 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
774
775 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_LO);
776 if (ret)
777 return ret;
778
779 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
780
781 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_ROM_IMAGE_ADDR_HI);
782 if (ret)
783 return ret;
784
785 psp->vbflash_done = true;
786
787 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_UPDATE_FLASH_IMAGE);
788 if (ret)
789 return ret;
790
791 return 0;
792 }
793
psp_v13_0_dump_spirom(struct psp_context * psp,uint64_t fw_pri_mc_addr)794 static int psp_v13_0_dump_spirom(struct psp_context *psp,
795 uint64_t fw_pri_mc_addr)
796 {
797 struct amdgpu_device *adev = psp->adev;
798 int ret;
799
800 /* Confirm PSP is ready to start */
801 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_115),
802 MBOX_READY_FLAG, MBOX_READY_MASK, false);
803 if (ret) {
804 dev_err(adev->dev, "PSP Not ready to start processing, ret = %d", ret);
805 return ret;
806 }
807
808 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, lower_32_bits(fw_pri_mc_addr));
809
810 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_LO);
811 if (ret)
812 return ret;
813
814 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_116, upper_32_bits(fw_pri_mc_addr));
815
816 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_ROM_IMAGE_ADDR_HI);
817 if (ret)
818 return ret;
819
820 ret = psp_v13_0_exec_spi_cmd(psp, C2PMSG_CMD_SPI_GET_FLASH_IMAGE);
821
822 return ret;
823 }
824
psp_v13_0_vbflash_status(struct psp_context * psp)825 static int psp_v13_0_vbflash_status(struct psp_context *psp)
826 {
827 struct amdgpu_device *adev = psp->adev;
828
829 return RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_115);
830 }
831
psp_v13_0_fatal_error_recovery_quirk(struct psp_context * psp)832 static int psp_v13_0_fatal_error_recovery_quirk(struct psp_context *psp)
833 {
834 struct amdgpu_device *adev = psp->adev;
835
836 if (amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 10)) {
837 uint32_t reg_data;
838 /* MP1 fatal error: trigger PSP dram read to unhalt PSP
839 * during MP1 triggered sync flood.
840 */
841 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67);
842 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_67, reg_data + 0x10);
843
844 /* delay 1000ms for the mode1 reset for fatal error
845 * to be recovered back.
846 */
847 msleep(1000);
848 }
849
850 return 0;
851 }
852
psp_v13_0_get_ras_capability(struct psp_context * psp)853 static bool psp_v13_0_get_ras_capability(struct psp_context *psp)
854 {
855 struct amdgpu_device *adev = psp->adev;
856 struct amdgpu_ras *con = amdgpu_ras_get_context(adev);
857 u32 reg_data;
858
859 /* query ras cap should be done from host side */
860 if (amdgpu_sriov_vf(adev))
861 return false;
862
863 if (!con)
864 return false;
865
866 if ((amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 6) ||
867 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 12) ||
868 amdgpu_ip_version(adev, MP0_HWIP, 0) == IP_VERSION(13, 0, 14)) &&
869 (!(adev->flags & AMD_IS_APU))) {
870 reg_data = RREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_127);
871 adev->ras_hw_enabled = (reg_data & GENMASK_ULL(23, 0));
872 con->poison_supported = ((reg_data & GENMASK_ULL(24, 24)) >> 24) ? true : false;
873 return true;
874 } else {
875 return false;
876 }
877 }
878
psp_v13_0_is_aux_sos_load_required(struct psp_context * psp)879 static bool psp_v13_0_is_aux_sos_load_required(struct psp_context *psp)
880 {
881 struct amdgpu_device *adev = psp->adev;
882 u32 pmfw_ver;
883
884 if (amdgpu_ip_version(adev, MP0_HWIP, 0) != IP_VERSION(13, 0, 6))
885 return false;
886
887 /* load 4e version of sos if pmfw version less than 85.115.0 */
888 pmfw_ver = RREG32(regMP1_PUB_SCRATCH0 / 4);
889
890 return (pmfw_ver < 0x557300);
891 }
892
psp_v13_0_is_reload_needed(struct psp_context * psp)893 static bool psp_v13_0_is_reload_needed(struct psp_context *psp)
894 {
895 uint32_t ucode_ver;
896
897 if (!psp_v13_0_is_sos_alive(psp))
898 return false;
899
900 /* Restrict reload support only to specific IP versions */
901 switch (amdgpu_ip_version(psp->adev, MP0_HWIP, 0)) {
902 case IP_VERSION(13, 0, 2):
903 case IP_VERSION(13, 0, 6):
904 case IP_VERSION(13, 0, 14):
905 /* TOS version read from microcode header */
906 ucode_ver = psp->sos.fw_version;
907 /* Read TOS version from hardware */
908 psp_v13_0_init_sos_version(psp);
909 return (ucode_ver != psp->sos.fw_version);
910 default:
911 return false;
912 }
913
914 return false;
915 }
916
psp_v13_0_reg_program_no_ring(struct psp_context * psp,uint32_t val,enum psp_reg_prog_id id)917 static int psp_v13_0_reg_program_no_ring(struct psp_context *psp, uint32_t val,
918 enum psp_reg_prog_id id)
919 {
920 struct amdgpu_device *adev = psp->adev;
921 int ret = -EOPNOTSUPP;
922
923 /* PSP will broadcast the value to all instances */
924 if (amdgpu_sriov_vf(adev)) {
925 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_GBR_IH_SET);
926 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_102, id);
927 WREG32_SOC15(MP0, 0, regMP0_SMN_C2PMSG_103, val);
928
929 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, regMP0_SMN_C2PMSG_101),
930 0x80000000, 0x80000000, false);
931 }
932
933 return ret;
934 }
935
936 static const struct psp_funcs psp_v13_0_funcs = {
937 .init_microcode = psp_v13_0_init_microcode,
938 .wait_for_bootloader = psp_v13_0_wait_for_bootloader_steady_state,
939 .bootloader_load_kdb = psp_v13_0_bootloader_load_kdb,
940 .bootloader_load_spl = psp_v13_0_bootloader_load_spl,
941 .bootloader_load_sysdrv = psp_v13_0_bootloader_load_sysdrv,
942 .bootloader_load_soc_drv = psp_v13_0_bootloader_load_soc_drv,
943 .bootloader_load_intf_drv = psp_v13_0_bootloader_load_intf_drv,
944 .bootloader_load_dbg_drv = psp_v13_0_bootloader_load_dbg_drv,
945 .bootloader_load_ras_drv = psp_v13_0_bootloader_load_ras_drv,
946 .bootloader_load_spdm_drv = psp_v13_0_bootloader_load_spdm_drv,
947 .bootloader_load_sos = psp_v13_0_bootloader_load_sos,
948 .ring_create = psp_v13_0_ring_create,
949 .ring_stop = psp_v13_0_ring_stop,
950 .ring_destroy = psp_v13_0_ring_destroy,
951 .ring_get_wptr = psp_v13_0_ring_get_wptr,
952 .ring_set_wptr = psp_v13_0_ring_set_wptr,
953 .mem_training = psp_v13_0_memory_training,
954 .load_usbc_pd_fw = psp_v13_0_load_usbc_pd_fw,
955 .read_usbc_pd_fw = psp_v13_0_read_usbc_pd_fw,
956 .update_spirom = psp_v13_0_update_spirom,
957 .dump_spirom = psp_v13_0_dump_spirom,
958 .vbflash_stat = psp_v13_0_vbflash_status,
959 .fatal_error_recovery_quirk = psp_v13_0_fatal_error_recovery_quirk,
960 .get_ras_capability = psp_v13_0_get_ras_capability,
961 .is_aux_sos_load_required = psp_v13_0_is_aux_sos_load_required,
962 .is_reload_needed = psp_v13_0_is_reload_needed,
963 .reg_program_no_ring = psp_v13_0_reg_program_no_ring,
964 };
965
psp_v13_0_set_psp_funcs(struct psp_context * psp)966 void psp_v13_0_set_psp_funcs(struct psp_context *psp)
967 {
968 psp->funcs = &psp_v13_0_funcs;
969 }
970