1 /*
2 * Copyright 2018 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <linux/module.h>
25 #include <linux/vmalloc.h>
26 #include <drm/drm_drv.h>
27
28 #include "amdgpu.h"
29 #include "amdgpu_psp.h"
30 #include "amdgpu_ras.h"
31 #include "amdgpu_ucode.h"
32 #include "soc15_common.h"
33 #include "psp_v11_0.h"
34
35 #include "mp/mp_11_0_offset.h"
36 #include "mp/mp_11_0_sh_mask.h"
37 #include "gc/gc_9_0_offset.h"
38 #include "sdma0/sdma0_4_0_offset.h"
39 #include "nbio/nbio_7_4_offset.h"
40
41 #include "oss/osssys_4_0_offset.h"
42 #include "oss/osssys_4_0_sh_mask.h"
43
44 MODULE_FIRMWARE("amdgpu/vega20_sos.bin");
45 MODULE_FIRMWARE("amdgpu/vega20_asd.bin");
46 MODULE_FIRMWARE("amdgpu/vega20_ta.bin");
47 MODULE_FIRMWARE("amdgpu/navi10_sos.bin");
48 MODULE_FIRMWARE("amdgpu/navi10_asd.bin");
49 MODULE_FIRMWARE("amdgpu/navi10_ta.bin");
50 MODULE_FIRMWARE("amdgpu/navi14_sos.bin");
51 MODULE_FIRMWARE("amdgpu/navi14_asd.bin");
52 MODULE_FIRMWARE("amdgpu/navi14_ta.bin");
53 MODULE_FIRMWARE("amdgpu/navi12_sos.bin");
54 MODULE_FIRMWARE("amdgpu/navi12_asd.bin");
55 MODULE_FIRMWARE("amdgpu/navi12_ta.bin");
56 MODULE_FIRMWARE("amdgpu/navi12_cap.bin");
57 MODULE_FIRMWARE("amdgpu/arcturus_sos.bin");
58 MODULE_FIRMWARE("amdgpu/arcturus_asd.bin");
59 MODULE_FIRMWARE("amdgpu/arcturus_ta.bin");
60 MODULE_FIRMWARE("amdgpu/sienna_cichlid_sos.bin");
61 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ta.bin");
62 MODULE_FIRMWARE("amdgpu/sienna_cichlid_cap.bin");
63 MODULE_FIRMWARE("amdgpu/navy_flounder_sos.bin");
64 MODULE_FIRMWARE("amdgpu/navy_flounder_ta.bin");
65 MODULE_FIRMWARE("amdgpu/vangogh_asd.bin");
66 MODULE_FIRMWARE("amdgpu/vangogh_toc.bin");
67 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_sos.bin");
68 MODULE_FIRMWARE("amdgpu/dimgrey_cavefish_ta.bin");
69 MODULE_FIRMWARE("amdgpu/beige_goby_sos.bin");
70 MODULE_FIRMWARE("amdgpu/beige_goby_ta.bin");
71
72 /* address block */
73 #define smnMP1_FIRMWARE_FLAGS 0x3010024
74 /* navi10 reg offset define */
75 #define mmRLC_GPM_UCODE_ADDR_NV10 0x5b61
76 #define mmRLC_GPM_UCODE_DATA_NV10 0x5b62
77 #define mmSDMA0_UCODE_ADDR_NV10 0x5880
78 #define mmSDMA0_UCODE_DATA_NV10 0x5881
79 /* memory training timeout define */
80 #define MEM_TRAIN_SEND_MSG_TIMEOUT_US 3000000
81
82 /* For large FW files the time to complete can be very long */
83 #define USBC_PD_POLLING_LIMIT_S 240
84
85 /* Read USB-PD from LFB */
86 #define GFX_CMD_USB_PD_USE_LFB 0x480
87
psp_v11_0_init_microcode(struct psp_context * psp)88 static int psp_v11_0_init_microcode(struct psp_context *psp)
89 {
90 struct amdgpu_device *adev = psp->adev;
91 char ucode_prefix[30];
92 int err = 0;
93
94 DRM_DEBUG("\n");
95
96 amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
97
98 switch (amdgpu_ip_version(adev, MP0_HWIP, 0)) {
99 case IP_VERSION(11, 0, 2):
100 case IP_VERSION(11, 0, 4):
101 err = psp_init_sos_microcode(psp, ucode_prefix);
102 if (err)
103 return err;
104 err = psp_init_asd_microcode(psp, ucode_prefix);
105 if (err)
106 return err;
107 err = psp_init_ta_microcode(psp, ucode_prefix);
108 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;
109 break;
110 case IP_VERSION(11, 0, 0):
111 case IP_VERSION(11, 0, 5):
112 case IP_VERSION(11, 0, 9):
113 err = psp_init_sos_microcode(psp, ucode_prefix);
114 if (err)
115 return err;
116 err = psp_init_asd_microcode(psp, ucode_prefix);
117 if (err)
118 return err;
119 err = psp_init_ta_microcode(psp, ucode_prefix);
120 adev->psp.securedisplay_context.context.bin_desc.size_bytes = 0;
121 break;
122 case IP_VERSION(11, 0, 7):
123 case IP_VERSION(11, 0, 11):
124 case IP_VERSION(11, 0, 12):
125 case IP_VERSION(11, 0, 13):
126 err = psp_init_sos_microcode(psp, ucode_prefix);
127 if (err)
128 return err;
129 err = psp_init_ta_microcode(psp, ucode_prefix);
130 break;
131 case IP_VERSION(11, 5, 0):
132 case IP_VERSION(11, 5, 2):
133 err = psp_init_asd_microcode(psp, ucode_prefix);
134 if (err)
135 return err;
136 err = psp_init_toc_microcode(psp, ucode_prefix);
137 break;
138 default:
139 BUG();
140 }
141
142 return err;
143 }
144
psp_v11_0_wait_for_bootloader(struct psp_context * psp)145 static int psp_v11_0_wait_for_bootloader(struct psp_context *psp)
146 {
147 struct amdgpu_device *adev = psp->adev;
148
149 int ret;
150 int retry_loop;
151
152 for (retry_loop = 0; retry_loop < 20; retry_loop++) {
153 /* Wait for bootloader to signify that is
154 ready having bit 31 of C2PMSG_35 set to 1 */
155 ret = psp_wait_for(
156 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
157 0x80000000, 0x8000FFFF, PSP_WAITREG_NOVERBOSE);
158
159 if (ret == 0)
160 return 0;
161 }
162
163 return ret;
164 }
165
psp_v11_0_is_sos_alive(struct psp_context * psp)166 static bool psp_v11_0_is_sos_alive(struct psp_context *psp)
167 {
168 struct amdgpu_device *adev = psp->adev;
169 uint32_t sol_reg;
170
171 sol_reg = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81);
172
173 return sol_reg != 0x0;
174 }
175
psp_v11_0_bootloader_load_component(struct psp_context * psp,struct psp_bin_desc * bin_desc,enum psp_bootloader_cmd bl_cmd)176 static int psp_v11_0_bootloader_load_component(struct psp_context *psp,
177 struct psp_bin_desc *bin_desc,
178 enum psp_bootloader_cmd bl_cmd)
179 {
180 int ret;
181 uint32_t psp_gfxdrv_command_reg = 0;
182 struct amdgpu_device *adev = psp->adev;
183
184 /* Check sOS sign of life register to confirm sys driver and sOS
185 * are already been loaded.
186 */
187 if (psp_v11_0_is_sos_alive(psp))
188 return 0;
189
190 ret = psp_v11_0_wait_for_bootloader(psp);
191 if (ret)
192 return ret;
193
194 /* Copy PSP System Driver binary to memory */
195 psp_copy_fw(psp, bin_desc->start_addr, bin_desc->size_bytes);
196
197 /* Provide the sys driver to bootloader */
198 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
199 (uint32_t)(psp->fw_pri_mc_addr >> 20));
200 psp_gfxdrv_command_reg = bl_cmd;
201 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
202 psp_gfxdrv_command_reg);
203
204 ret = psp_v11_0_wait_for_bootloader(psp);
205
206 return ret;
207 }
208
psp_v11_0_bootloader_load_kdb(struct psp_context * psp)209 static int psp_v11_0_bootloader_load_kdb(struct psp_context *psp)
210 {
211 return psp_v11_0_bootloader_load_component(psp, &psp->kdb, PSP_BL__LOAD_KEY_DATABASE);
212 }
213
psp_v11_0_bootloader_load_spl(struct psp_context * psp)214 static int psp_v11_0_bootloader_load_spl(struct psp_context *psp)
215 {
216 return psp_v11_0_bootloader_load_component(psp, &psp->spl, PSP_BL__LOAD_TOS_SPL_TABLE);
217 }
218
psp_v11_0_bootloader_load_sysdrv(struct psp_context * psp)219 static int psp_v11_0_bootloader_load_sysdrv(struct psp_context *psp)
220 {
221 return psp_v11_0_bootloader_load_component(psp, &psp->sys, PSP_BL__LOAD_SYSDRV);
222 }
223
psp_v11_0_bootloader_load_sos(struct psp_context * psp)224 static int psp_v11_0_bootloader_load_sos(struct psp_context *psp)
225 {
226 int ret;
227 unsigned int psp_gfxdrv_command_reg = 0;
228 struct amdgpu_device *adev = psp->adev;
229
230 /* Check sOS sign of life register to confirm sys driver and sOS
231 * are already been loaded.
232 */
233 if (psp_v11_0_is_sos_alive(psp))
234 return 0;
235
236 ret = psp_v11_0_wait_for_bootloader(psp);
237 if (ret)
238 return ret;
239
240 /* Copy Secure OS binary to PSP memory */
241 psp_copy_fw(psp, psp->sos.start_addr, psp->sos.size_bytes);
242
243 /* Provide the PSP secure OS to bootloader */
244 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36,
245 (uint32_t)(psp->fw_pri_mc_addr >> 20));
246 psp_gfxdrv_command_reg = PSP_BL__LOAD_SOSDRV;
247 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35,
248 psp_gfxdrv_command_reg);
249
250 /* there might be handshake issue with hardware which needs delay */
251 mdelay(20);
252 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_81),
253 RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_81), 0,
254 PSP_WAITREG_CHANGED);
255
256 return ret;
257 }
258
psp_v11_0_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)259 static int psp_v11_0_ring_stop(struct psp_context *psp,
260 enum psp_ring_type ring_type)
261 {
262 int ret = 0;
263 struct amdgpu_device *adev = psp->adev;
264
265 /* Write the ring destroy command*/
266 if (amdgpu_sriov_vf(adev))
267 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
268 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
269 else
270 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
271 GFX_CTRL_CMD_ID_DESTROY_RINGS);
272
273 /* there might be handshake issue with hardware which needs delay */
274 mdelay(20);
275
276 /* Wait for response flag (bit 31) */
277 if (amdgpu_sriov_vf(adev))
278 ret = psp_wait_for(
279 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
280 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
281 else
282 ret = psp_wait_for(
283 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
284 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
285
286 return ret;
287 }
288
psp_v11_0_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)289 static int psp_v11_0_ring_create(struct psp_context *psp,
290 enum psp_ring_type ring_type)
291 {
292 int ret = 0;
293 unsigned int psp_ring_reg = 0;
294 struct psp_ring *ring = &psp->km_ring;
295 struct amdgpu_device *adev = psp->adev;
296
297 if (amdgpu_sriov_vf(adev)) {
298 ring->ring_wptr = 0;
299 ret = psp_v11_0_ring_stop(psp, ring_type);
300 if (ret) {
301 DRM_ERROR("psp_v11_0_ring_stop_sriov failed!\n");
302 return ret;
303 }
304
305 /* Write low address of the ring to C2PMSG_102 */
306 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
307 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
308 /* Write high address of the ring to C2PMSG_103 */
309 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
310 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
311
312 /* Write the ring initialization command to C2PMSG_101 */
313 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
314 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
315
316 /* there might be handshake issue with hardware which needs delay */
317 mdelay(20);
318
319 /* Wait for response flag (bit 31) in C2PMSG_101 */
320 ret = psp_wait_for(
321 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
322 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
323
324 } else {
325 /* Wait for sOS ready for ring creation */
326 ret = psp_wait_for(
327 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
328 MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);
329 if (ret) {
330 DRM_ERROR("Failed to wait for sOS ready for ring creation\n");
331 return ret;
332 }
333
334 /* Write low address of the ring to C2PMSG_69 */
335 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
336 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
337 /* Write high address of the ring to C2PMSG_70 */
338 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
339 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
340 /* Write size of ring to C2PMSG_71 */
341 psp_ring_reg = ring->ring_size;
342 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
343 /* Write the ring initialization command to C2PMSG_64 */
344 psp_ring_reg = ring_type;
345 psp_ring_reg = psp_ring_reg << 16;
346 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
347
348 /* there might be handshake issue with hardware which needs delay */
349 mdelay(20);
350
351 /* Wait for response flag (bit 31) in C2PMSG_64 */
352 ret = psp_wait_for(
353 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
354 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
355 }
356
357 return ret;
358 }
359
360
psp_v11_0_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)361 static int psp_v11_0_ring_destroy(struct psp_context *psp,
362 enum psp_ring_type ring_type)
363 {
364 int ret = 0;
365 struct psp_ring *ring = &psp->km_ring;
366 struct amdgpu_device *adev = psp->adev;
367
368 ret = psp_v11_0_ring_stop(psp, ring_type);
369 if (ret)
370 DRM_ERROR("Fail to stop psp ring\n");
371
372 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
373 &ring->ring_mem_mc_addr,
374 (void **)&ring->ring_mem);
375
376 return ret;
377 }
378
psp_v11_0_mode1_reset(struct psp_context * psp)379 static int psp_v11_0_mode1_reset(struct psp_context *psp)
380 {
381 int ret;
382 uint32_t offset;
383 struct amdgpu_device *adev = psp->adev;
384
385 offset = SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64);
386
387 ret = psp_wait_for(psp, offset, MBOX_TOS_READY_FLAG,
388 MBOX_TOS_READY_MASK, 0);
389
390 if (ret) {
391 DRM_INFO("psp is not working correctly before mode1 reset!\n");
392 return -EINVAL;
393 }
394
395 /*send the mode 1 reset command*/
396 WREG32(offset, GFX_CTRL_CMD_ID_MODE1_RST);
397
398 msleep(500);
399
400 return 0;
401 }
402
psp_v11_0_memory_training_send_msg(struct psp_context * psp,int msg)403 static int psp_v11_0_memory_training_send_msg(struct psp_context *psp, int msg)
404 {
405 int ret;
406 int i;
407 uint32_t data_32;
408 int max_wait;
409 struct amdgpu_device *adev = psp->adev;
410
411 data_32 = (psp->mem_train_ctx.c2p_train_data_offset >> 20);
412 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, data_32);
413 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, msg);
414
415 max_wait = MEM_TRAIN_SEND_MSG_TIMEOUT_US / adev->usec_timeout;
416 for (i = 0; i < max_wait; i++) {
417 ret = psp_wait_for(
418 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
419 0x80000000, 0x80000000, PSP_WAITREG_NOVERBOSE);
420 if (ret == 0)
421 break;
422 }
423 if (i < max_wait)
424 ret = 0;
425 else
426 ret = -ETIME;
427
428 DRM_DEBUG("training %s %s, cost %d @ %d ms\n",
429 (msg == PSP_BL__DRAM_SHORT_TRAIN) ? "short" : "long",
430 (ret == 0) ? "succeed" : "failed",
431 i, adev->usec_timeout/1000);
432 return ret;
433 }
434
435 /*
436 * save and restore process
437 */
psp_v11_0_memory_training(struct psp_context * psp,uint32_t ops)438 static int psp_v11_0_memory_training(struct psp_context *psp, uint32_t ops)
439 {
440 struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
441 uint32_t *pcache = (uint32_t *)ctx->sys_cache;
442 struct amdgpu_device *adev = psp->adev;
443 uint32_t p2c_header[4];
444 uint32_t sz;
445 void *buf;
446 int ret, idx;
447
448 if (ctx->init == PSP_MEM_TRAIN_NOT_SUPPORT) {
449 DRM_DEBUG("Memory training is not supported.\n");
450 return 0;
451 } else if (ctx->init != PSP_MEM_TRAIN_INIT_SUCCESS) {
452 DRM_ERROR("Memory training initialization failure.\n");
453 return -EINVAL;
454 }
455
456 if (psp_v11_0_is_sos_alive(psp)) {
457 DRM_DEBUG("SOS is alive, skip memory training.\n");
458 return 0;
459 }
460
461 amdgpu_device_vram_access(adev, ctx->p2c_train_data_offset, p2c_header, sizeof(p2c_header), false);
462 DRM_DEBUG("sys_cache[%08x,%08x,%08x,%08x] p2c_header[%08x,%08x,%08x,%08x]\n",
463 pcache[0], pcache[1], pcache[2], pcache[3],
464 p2c_header[0], p2c_header[1], p2c_header[2], p2c_header[3]);
465
466 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
467 DRM_DEBUG("Short training depends on restore.\n");
468 ops |= PSP_MEM_TRAIN_RESTORE;
469 }
470
471 if ((ops & PSP_MEM_TRAIN_RESTORE) &&
472 pcache[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
473 DRM_DEBUG("sys_cache[0] is invalid, restore depends on save.\n");
474 ops |= PSP_MEM_TRAIN_SAVE;
475 }
476
477 if (p2c_header[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
478 !(pcache[0] == MEM_TRAIN_SYSTEM_SIGNATURE &&
479 pcache[3] == p2c_header[3])) {
480 DRM_DEBUG("sys_cache is invalid or out-of-date, need save training data to sys_cache.\n");
481 ops |= PSP_MEM_TRAIN_SAVE;
482 }
483
484 if ((ops & PSP_MEM_TRAIN_SAVE) &&
485 p2c_header[0] != MEM_TRAIN_SYSTEM_SIGNATURE) {
486 DRM_DEBUG("p2c_header[0] is invalid, save depends on long training.\n");
487 ops |= PSP_MEM_TRAIN_SEND_LONG_MSG;
488 }
489
490 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
491 ops &= ~PSP_MEM_TRAIN_SEND_SHORT_MSG;
492 ops |= PSP_MEM_TRAIN_SAVE;
493 }
494
495 DRM_DEBUG("Memory training ops:%x.\n", ops);
496
497 if (ops & PSP_MEM_TRAIN_SEND_LONG_MSG) {
498 /*
499 * Long training will encroach a certain amount on the bottom of VRAM;
500 * save the content from the bottom of VRAM to system memory
501 * before training, and restore it after training to avoid
502 * VRAM corruption.
503 */
504 sz = BIST_MEM_TRAINING_ENCROACHED_SIZE;
505
506 if (adev->gmc.visible_vram_size < sz || !adev->mman.aper_base_kaddr) {
507 DRM_ERROR("visible_vram_size %llx or aper_base_kaddr %p is not initialized.\n",
508 adev->gmc.visible_vram_size,
509 adev->mman.aper_base_kaddr);
510 return -EINVAL;
511 }
512
513 buf = vmalloc(sz);
514 if (!buf) {
515 DRM_ERROR("failed to allocate system memory.\n");
516 return -ENOMEM;
517 }
518
519 if (drm_dev_enter(adev_to_drm(adev), &idx)) {
520 memcpy_fromio(buf, adev->mman.aper_base_kaddr, sz);
521 ret = psp_v11_0_memory_training_send_msg(psp, PSP_BL__DRAM_LONG_TRAIN);
522 if (ret) {
523 DRM_ERROR("Send long training msg failed.\n");
524 vfree(buf);
525 drm_dev_exit(idx);
526 return ret;
527 }
528
529 memcpy_toio(adev->mman.aper_base_kaddr, buf, sz);
530 amdgpu_device_flush_hdp(adev, NULL);
531 vfree(buf);
532 drm_dev_exit(idx);
533 } else {
534 vfree(buf);
535 return -ENODEV;
536 }
537 }
538
539 if (ops & PSP_MEM_TRAIN_SAVE) {
540 amdgpu_device_vram_access(psp->adev, ctx->p2c_train_data_offset, ctx->sys_cache, ctx->train_data_size, false);
541 }
542
543 if (ops & PSP_MEM_TRAIN_RESTORE) {
544 amdgpu_device_vram_access(psp->adev, ctx->c2p_train_data_offset, ctx->sys_cache, ctx->train_data_size, true);
545 }
546
547 if (ops & PSP_MEM_TRAIN_SEND_SHORT_MSG) {
548 ret = psp_v11_0_memory_training_send_msg(psp, (amdgpu_force_long_training > 0) ?
549 PSP_BL__DRAM_LONG_TRAIN : PSP_BL__DRAM_SHORT_TRAIN);
550 if (ret) {
551 DRM_ERROR("send training msg failed.\n");
552 return ret;
553 }
554 }
555 ctx->training_cnt++;
556 return 0;
557 }
558
psp_v11_0_ring_get_wptr(struct psp_context * psp)559 static uint32_t psp_v11_0_ring_get_wptr(struct psp_context *psp)
560 {
561 uint32_t data;
562 struct amdgpu_device *adev = psp->adev;
563
564 if (amdgpu_sriov_vf(adev))
565 data = psp->km_ring.ring_wptr;
566 else
567 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
568
569 return data;
570 }
571
psp_v11_0_ring_set_wptr(struct psp_context * psp,uint32_t value)572 static void psp_v11_0_ring_set_wptr(struct psp_context *psp, uint32_t value)
573 {
574 struct amdgpu_device *adev = psp->adev;
575
576 if (amdgpu_sriov_vf(adev)) {
577 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
578 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101, GFX_CTRL_CMD_ID_CONSUME_CMD);
579 psp->km_ring.ring_wptr = value;
580 } else
581 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
582 }
583
psp_v11_0_load_usbc_pd_fw(struct psp_context * psp,uint64_t fw_pri_mc_addr)584 static int psp_v11_0_load_usbc_pd_fw(struct psp_context *psp, uint64_t fw_pri_mc_addr)
585 {
586 struct amdgpu_device *adev = psp->adev;
587 uint32_t reg_status;
588 int ret, i = 0;
589
590 /*
591 * LFB address which is aligned to 1MB address and has to be
592 * right-shifted by 20 so that LFB address can be passed on a 32-bit C2P
593 * register
594 */
595 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36, (fw_pri_mc_addr >> 20));
596
597 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
598 0x80000000, 0x80000000, 0);
599 if (ret)
600 return ret;
601
602 /* Fireup interrupt so PSP can pick up the address */
603 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, (GFX_CMD_USB_PD_USE_LFB << 16));
604
605 /* FW load takes very long time */
606 do {
607 msleep(1000);
608 reg_status = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35);
609
610 if (reg_status & 0x80000000)
611 goto done;
612
613 } while (++i < USBC_PD_POLLING_LIMIT_S);
614
615 return -ETIME;
616 done:
617
618 if ((reg_status & 0xFFFF) != 0) {
619 DRM_ERROR("Address load failed - MP0_SMN_C2PMSG_35.Bits [15:0] = 0x%04x\n",
620 reg_status & 0xFFFF);
621 return -EIO;
622 }
623
624 return 0;
625 }
626
psp_v11_0_read_usbc_pd_fw(struct psp_context * psp,uint32_t * fw_ver)627 static int psp_v11_0_read_usbc_pd_fw(struct psp_context *psp, uint32_t *fw_ver)
628 {
629 struct amdgpu_device *adev = psp->adev;
630 int ret;
631
632 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_35, C2PMSG_CMD_GFX_USB_PD_FW_VER);
633
634 ret = psp_wait_for(psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_35),
635 0x80000000, 0x80000000, 0);
636 if (!ret)
637 *fw_ver = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_36);
638
639 return ret;
640 }
641
642 static const struct psp_funcs psp_v11_0_funcs = {
643 .init_microcode = psp_v11_0_init_microcode,
644 .bootloader_load_kdb = psp_v11_0_bootloader_load_kdb,
645 .bootloader_load_spl = psp_v11_0_bootloader_load_spl,
646 .bootloader_load_sysdrv = psp_v11_0_bootloader_load_sysdrv,
647 .bootloader_load_sos = psp_v11_0_bootloader_load_sos,
648 .ring_create = psp_v11_0_ring_create,
649 .ring_stop = psp_v11_0_ring_stop,
650 .ring_destroy = psp_v11_0_ring_destroy,
651 .mode1_reset = psp_v11_0_mode1_reset,
652 .mem_training = psp_v11_0_memory_training,
653 .ring_get_wptr = psp_v11_0_ring_get_wptr,
654 .ring_set_wptr = psp_v11_0_ring_set_wptr,
655 .load_usbc_pd_fw = psp_v11_0_load_usbc_pd_fw,
656 .read_usbc_pd_fw = psp_v11_0_read_usbc_pd_fw,
657 .wait_for_bootloader = psp_v11_0_wait_for_bootloader
658 };
659
psp_v11_0_set_psp_funcs(struct psp_context * psp)660 void psp_v11_0_set_psp_funcs(struct psp_context *psp)
661 {
662 psp->funcs = &psp_v11_0_funcs;
663 }
664