1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23 #include "amdgpu.h"
24 #include "amdgpu_psp.h"
25 #include "amdgpu_ucode.h"
26 #include "soc15_common.h"
27 #include "psp_v11_0_8.h"
28
29 #include "mp/mp_11_0_8_offset.h"
30
psp_v11_0_8_ring_stop(struct psp_context * psp,enum psp_ring_type ring_type)31 static int psp_v11_0_8_ring_stop(struct psp_context *psp,
32 enum psp_ring_type ring_type)
33 {
34 int ret = 0;
35 struct amdgpu_device *adev = psp->adev;
36
37 if (amdgpu_sriov_vf(adev)) {
38 /* Write the ring destroy command*/
39 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
40 GFX_CTRL_CMD_ID_DESTROY_GPCOM_RING);
41 /* there might be handshake issue with hardware which needs delay */
42 mdelay(20);
43 /* Wait for response flag (bit 31) */
44 ret = psp_wait_for(
45 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
46 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
47 } else {
48 /* Write the ring destroy command*/
49 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64,
50 GFX_CTRL_CMD_ID_DESTROY_RINGS);
51 /* there might be handshake issue with hardware which needs delay */
52 mdelay(20);
53 /* Wait for response flag (bit 31) */
54 ret = psp_wait_for(
55 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
56 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
57 }
58
59 return ret;
60 }
61
psp_v11_0_8_ring_create(struct psp_context * psp,enum psp_ring_type ring_type)62 static int psp_v11_0_8_ring_create(struct psp_context *psp,
63 enum psp_ring_type ring_type)
64 {
65 int ret = 0;
66 unsigned int psp_ring_reg = 0;
67 struct psp_ring *ring = &psp->km_ring;
68 struct amdgpu_device *adev = psp->adev;
69
70 if (amdgpu_sriov_vf(adev)) {
71 ret = psp_v11_0_8_ring_stop(psp, ring_type);
72 if (ret) {
73 DRM_ERROR("psp_v11_0_8_ring_stop_sriov failed!\n");
74 return ret;
75 }
76
77 /* Write low address of the ring to C2PMSG_102 */
78 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
79 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, psp_ring_reg);
80 /* Write high address of the ring to C2PMSG_103 */
81 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
82 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_103, psp_ring_reg);
83
84 /* Write the ring initialization command to C2PMSG_101 */
85 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
86 GFX_CTRL_CMD_ID_INIT_GPCOM_RING);
87
88 /* there might be handshake issue with hardware which needs delay */
89 mdelay(20);
90
91 /* Wait for response flag (bit 31) in C2PMSG_101 */
92 ret = psp_wait_for(
93 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_101),
94 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
95
96 } else {
97 /* Wait for sOS ready for ring creation */
98 ret = psp_wait_for(
99 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
100 MBOX_TOS_READY_FLAG, MBOX_TOS_READY_MASK, 0);
101 if (ret) {
102 DRM_ERROR("Failed to wait for trust OS ready for ring creation\n");
103 return ret;
104 }
105
106 /* Write low address of the ring to C2PMSG_69 */
107 psp_ring_reg = lower_32_bits(ring->ring_mem_mc_addr);
108 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_69, psp_ring_reg);
109 /* Write high address of the ring to C2PMSG_70 */
110 psp_ring_reg = upper_32_bits(ring->ring_mem_mc_addr);
111 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_70, psp_ring_reg);
112 /* Write size of ring to C2PMSG_71 */
113 psp_ring_reg = ring->ring_size;
114 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_71, psp_ring_reg);
115 /* Write the ring initialization command to C2PMSG_64 */
116 psp_ring_reg = ring_type;
117 psp_ring_reg = psp_ring_reg << 16;
118 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_64, psp_ring_reg);
119
120 /* there might be handshake issue with hardware which needs delay */
121 mdelay(20);
122
123 /* Wait for response flag (bit 31) in C2PMSG_64 */
124 ret = psp_wait_for(
125 psp, SOC15_REG_OFFSET(MP0, 0, mmMP0_SMN_C2PMSG_64),
126 MBOX_TOS_RESP_FLAG, MBOX_TOS_RESP_MASK, 0);
127 }
128
129 return ret;
130 }
131
psp_v11_0_8_ring_destroy(struct psp_context * psp,enum psp_ring_type ring_type)132 static int psp_v11_0_8_ring_destroy(struct psp_context *psp,
133 enum psp_ring_type ring_type)
134 {
135 int ret = 0;
136 struct psp_ring *ring = &psp->km_ring;
137 struct amdgpu_device *adev = psp->adev;
138
139 ret = psp_v11_0_8_ring_stop(psp, ring_type);
140 if (ret)
141 DRM_ERROR("Fail to stop psp ring\n");
142
143 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
144 &ring->ring_mem_mc_addr,
145 (void **)&ring->ring_mem);
146
147 return ret;
148 }
149
psp_v11_0_8_ring_get_wptr(struct psp_context * psp)150 static uint32_t psp_v11_0_8_ring_get_wptr(struct psp_context *psp)
151 {
152 uint32_t data;
153 struct amdgpu_device *adev = psp->adev;
154
155 if (amdgpu_sriov_vf(adev))
156 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102);
157 else
158 data = RREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67);
159
160 return data;
161 }
162
psp_v11_0_8_ring_set_wptr(struct psp_context * psp,uint32_t value)163 static void psp_v11_0_8_ring_set_wptr(struct psp_context *psp, uint32_t value)
164 {
165 struct amdgpu_device *adev = psp->adev;
166
167 if (amdgpu_sriov_vf(adev)) {
168 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_102, value);
169 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_101,
170 GFX_CTRL_CMD_ID_CONSUME_CMD);
171 } else
172 WREG32_SOC15(MP0, 0, mmMP0_SMN_C2PMSG_67, value);
173 }
174
175 static const struct psp_funcs psp_v11_0_8_funcs = {
176 .ring_create = psp_v11_0_8_ring_create,
177 .ring_stop = psp_v11_0_8_ring_stop,
178 .ring_destroy = psp_v11_0_8_ring_destroy,
179 .ring_get_wptr = psp_v11_0_8_ring_get_wptr,
180 .ring_set_wptr = psp_v11_0_8_ring_set_wptr,
181 };
182
psp_v11_0_8_set_psp_funcs(struct psp_context * psp)183 void psp_v11_0_8_set_psp_funcs(struct psp_context *psp)
184 {
185 psp->funcs = &psp_v11_0_8_funcs;
186 }
187