xref: /linux/sound/soc/sof/amd/acp.c (revision 6537cfb395f352782918d8ee7b7f10ba2cc3cbf2)
1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause)
2 //
3 // This file is provided under a dual BSD/GPLv2 license. When using or
4 // redistributing this file, you may do so under either license.
5 //
6 // Copyright(c) 2021, 2023 Advanced Micro Devices, Inc. All rights reserved.
7 //
8 // Authors: Vijendar Mukunda <Vijendar.Mukunda@amd.com>
9 //	    Ajit Kumar Pandey <AjitKumar.Pandey@amd.com>
10 
11 /*
12  * Hardware interface for generic AMD ACP processor
13  */
14 
15 #include <linux/io.h>
16 #include <linux/module.h>
17 #include <linux/pci.h>
18 
19 #include "../ops.h"
20 #include "acp.h"
21 #include "acp-dsp-offset.h"
22 
23 static bool enable_fw_debug;
24 module_param(enable_fw_debug, bool, 0444);
25 MODULE_PARM_DESC(enable_fw_debug, "Enable Firmware debug");
26 
27 static struct acp_quirk_entry quirk_valve_galileo = {
28 	.signed_fw_image = true,
29 	.skip_iram_dram_size_mod = true,
30 	.post_fw_run_delay = true,
31 };
32 
33 const struct dmi_system_id acp_sof_quirk_table[] = {
34 	{
35 		/* Steam Deck OLED device */
36 		.matches = {
37 			DMI_MATCH(DMI_SYS_VENDOR, "Valve"),
38 			DMI_MATCH(DMI_PRODUCT_NAME, "Galileo"),
39 		},
40 		.driver_data = &quirk_valve_galileo,
41 	},
42 	{}
43 };
44 EXPORT_SYMBOL_GPL(acp_sof_quirk_table);
45 
smn_write(struct pci_dev * dev,u32 smn_addr,u32 data)46 static int smn_write(struct pci_dev *dev, u32 smn_addr, u32 data)
47 {
48 	pci_write_config_dword(dev, 0x60, smn_addr);
49 	pci_write_config_dword(dev, 0x64, data);
50 
51 	return 0;
52 }
53 
smn_read(struct pci_dev * dev,u32 smn_addr)54 static int smn_read(struct pci_dev *dev, u32 smn_addr)
55 {
56 	u32 data = 0;
57 
58 	pci_write_config_dword(dev, 0x60, smn_addr);
59 	pci_read_config_dword(dev, 0x64, &data);
60 
61 	return data;
62 }
63 
init_dma_descriptor(struct acp_dev_data * adata)64 static void init_dma_descriptor(struct acp_dev_data *adata)
65 {
66 	struct snd_sof_dev *sdev = adata->dev;
67 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
68 	struct acp_dev_data *acp_data = sdev->pdata->hw_pdata;
69 	unsigned int addr;
70 	unsigned int acp_dma_desc_base_addr, acp_dma_desc_max_num_dscr;
71 
72 	addr = desc->sram_pte_offset + sdev->debug_box.offset +
73 	       offsetof(struct scratch_reg_conf, dma_desc);
74 
75 	switch (acp_data->pci_rev) {
76 	case ACP70_PCI_ID:
77 		acp_dma_desc_base_addr = ACP70_DMA_DESC_BASE_ADDR;
78 		acp_dma_desc_max_num_dscr = ACP70_DMA_DESC_MAX_NUM_DSCR;
79 		break;
80 	default:
81 		acp_dma_desc_base_addr = ACP_DMA_DESC_BASE_ADDR;
82 		acp_dma_desc_max_num_dscr = ACP_DMA_DESC_MAX_NUM_DSCR;
83 	}
84 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_base_addr, addr);
85 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_desc_max_num_dscr, ACP_MAX_DESC_CNT);
86 }
87 
configure_dma_descriptor(struct acp_dev_data * adata,unsigned short idx,struct dma_descriptor * dscr_info)88 static void configure_dma_descriptor(struct acp_dev_data *adata, unsigned short idx,
89 				     struct dma_descriptor *dscr_info)
90 {
91 	struct snd_sof_dev *sdev = adata->dev;
92 	unsigned int offset;
93 
94 	offset = ACP_SCRATCH_REG_0 + sdev->debug_box.offset +
95 		offsetof(struct scratch_reg_conf, dma_desc) +
96 		idx * sizeof(struct dma_descriptor);
97 
98 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset, dscr_info->src_addr);
99 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x4, dscr_info->dest_addr);
100 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, offset + 0x8, dscr_info->tx_cnt.u32_all);
101 }
102 
config_dma_channel(struct acp_dev_data * adata,unsigned int ch,unsigned int idx,unsigned int dscr_count)103 static int config_dma_channel(struct acp_dev_data *adata, unsigned int ch,
104 			      unsigned int idx, unsigned int dscr_count)
105 {
106 	struct snd_sof_dev *sdev = adata->dev;
107 	struct acp_dev_data *acp_data = sdev->pdata->hw_pdata;
108 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
109 	unsigned int val, status;
110 	unsigned int acp_dma_cntl_0, acp_dma_ch_rst_sts, acp_dma_dscr_err_sts_0;
111 	unsigned int acp_dma_dscr_cnt_0, acp_dma_prio_0, acp_dma_dscr_strt_idx_0;
112 	int ret;
113 
114 	switch (acp_data->pci_rev) {
115 	case ACP70_PCI_ID:
116 		acp_dma_cntl_0 = ACP70_DMA_CNTL_0;
117 		acp_dma_ch_rst_sts = ACP70_DMA_CH_RST_STS;
118 		acp_dma_dscr_err_sts_0 = ACP70_DMA_ERR_STS_0;
119 		acp_dma_dscr_cnt_0 = ACP70_DMA_DSCR_CNT_0;
120 		acp_dma_prio_0 = ACP70_DMA_PRIO_0;
121 		acp_dma_dscr_strt_idx_0 = ACP70_DMA_DSCR_STRT_IDX_0;
122 		break;
123 	default:
124 		acp_dma_cntl_0 = ACP_DMA_CNTL_0;
125 		acp_dma_ch_rst_sts = ACP_DMA_CH_RST_STS;
126 		acp_dma_dscr_err_sts_0 = ACP_DMA_ERR_STS_0;
127 		acp_dma_dscr_cnt_0 = ACP_DMA_DSCR_CNT_0;
128 		acp_dma_prio_0 = ACP_DMA_PRIO_0;
129 		acp_dma_dscr_strt_idx_0 = ACP_DMA_DSCR_STRT_IDX_0;
130 	}
131 
132 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32),
133 			  ACP_DMA_CH_RST | ACP_DMA_CH_GRACEFUL_RST_EN);
134 
135 	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_rst_sts, val,
136 					    val & (1 << ch), ACP_REG_POLL_INTERVAL,
137 					    ACP_REG_POLL_TIMEOUT_US);
138 	if (ret < 0) {
139 		status = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->acp_error_stat);
140 		val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, acp_dma_dscr_err_sts_0 +
141 				       ch * sizeof(u32));
142 
143 		dev_err(sdev->dev, "ACP_DMA_ERR_STS :0x%x ACP_ERROR_STATUS :0x%x\n", val, status);
144 		return ret;
145 	}
146 
147 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, (acp_dma_cntl_0 + ch * sizeof(u32)), 0);
148 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_cnt_0 + ch * sizeof(u32), dscr_count);
149 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_dscr_strt_idx_0 + ch * sizeof(u32), idx);
150 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_prio_0 + ch * sizeof(u32), 0);
151 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, acp_dma_cntl_0 + ch * sizeof(u32), ACP_DMA_CH_RUN);
152 
153 	return ret;
154 }
155 
acpbus_dma_start(struct acp_dev_data * adata,unsigned int ch,unsigned int dscr_count,struct dma_descriptor * dscr_info)156 static int acpbus_dma_start(struct acp_dev_data *adata, unsigned int ch,
157 			    unsigned int dscr_count, struct dma_descriptor *dscr_info)
158 {
159 	struct snd_sof_dev *sdev = adata->dev;
160 	int ret;
161 	u16 dscr;
162 
163 	if (!dscr_info || !dscr_count)
164 		return -EINVAL;
165 
166 	for (dscr = 0; dscr < dscr_count; dscr++)
167 		configure_dma_descriptor(adata, dscr, dscr_info++);
168 
169 	ret = config_dma_channel(adata, ch, 0, dscr_count);
170 	if (ret < 0)
171 		dev_err(sdev->dev, "config dma ch failed:%d\n", ret);
172 
173 	return ret;
174 }
175 
configure_and_run_dma(struct acp_dev_data * adata,unsigned int src_addr,unsigned int dest_addr,int dsp_data_size)176 int configure_and_run_dma(struct acp_dev_data *adata, unsigned int src_addr,
177 			  unsigned int dest_addr, int dsp_data_size)
178 {
179 	struct snd_sof_dev *sdev = adata->dev;
180 	unsigned int desc_count, index;
181 	int ret;
182 
183 	for (desc_count = 0; desc_count < ACP_MAX_DESC && dsp_data_size >= 0;
184 	     desc_count++, dsp_data_size -= ACP_PAGE_SIZE) {
185 		adata->dscr_info[desc_count].src_addr = src_addr + desc_count * ACP_PAGE_SIZE;
186 		adata->dscr_info[desc_count].dest_addr = dest_addr + desc_count * ACP_PAGE_SIZE;
187 		adata->dscr_info[desc_count].tx_cnt.bits.count = ACP_PAGE_SIZE;
188 		if (dsp_data_size < ACP_PAGE_SIZE)
189 			adata->dscr_info[desc_count].tx_cnt.bits.count = dsp_data_size;
190 	}
191 
192 	ret = acpbus_dma_start(adata, 0, desc_count, adata->dscr_info);
193 	if (ret)
194 		dev_err(sdev->dev, "acpbus_dma_start failed\n");
195 
196 	/* Clear descriptor array */
197 	for (index = 0; index < desc_count; index++)
198 		memset(&adata->dscr_info[index], 0x00, sizeof(struct dma_descriptor));
199 
200 	return ret;
201 }
202 
203 /*
204  * psp_mbox_ready- function to poll ready bit of psp mbox
205  * @adata: acp device data
206  * @ack: bool variable to check ready bit status or psp ack
207  */
208 
psp_mbox_ready(struct acp_dev_data * adata,bool ack)209 static int psp_mbox_ready(struct acp_dev_data *adata, bool ack)
210 {
211 	struct snd_sof_dev *sdev = adata->dev;
212 	int ret;
213 	u32 data;
214 
215 	ret = read_poll_timeout(smn_read, data, data & MBOX_READY_MASK, MBOX_DELAY_US,
216 				ACP_PSP_TIMEOUT_US, false, adata->smn_dev, MP0_C2PMSG_114_REG);
217 	if (!ret)
218 		return 0;
219 
220 	dev_err(sdev->dev, "PSP error status %x\n", data & MBOX_STATUS_MASK);
221 
222 	if (ack)
223 		return -ETIMEDOUT;
224 
225 	return -EBUSY;
226 }
227 
228 /*
229  * psp_send_cmd - function to send psp command over mbox
230  * @adata: acp device data
231  * @cmd: non zero integer value for command type
232  */
233 
psp_send_cmd(struct acp_dev_data * adata,int cmd)234 static int psp_send_cmd(struct acp_dev_data *adata, int cmd)
235 {
236 	struct snd_sof_dev *sdev = adata->dev;
237 	int ret;
238 	u32 data;
239 
240 	if (!cmd)
241 		return -EINVAL;
242 
243 	/* Get a non-zero Doorbell value from PSP */
244 	ret = read_poll_timeout(smn_read, data, data, MBOX_DELAY_US, ACP_PSP_TIMEOUT_US, false,
245 				adata->smn_dev, MP0_C2PMSG_73_REG);
246 
247 	if (ret) {
248 		dev_err(sdev->dev, "Failed to get Doorbell from MBOX %x\n", MP0_C2PMSG_73_REG);
249 		return ret;
250 	}
251 
252 	/* Check if PSP is ready for new command */
253 	ret = psp_mbox_ready(adata, 0);
254 	if (ret)
255 		return ret;
256 
257 	smn_write(adata->smn_dev, MP0_C2PMSG_114_REG, cmd);
258 
259 	/* Ring the Doorbell for PSP */
260 	smn_write(adata->smn_dev, MP0_C2PMSG_73_REG, data);
261 
262 	/* Check MBOX ready as PSP ack */
263 	ret = psp_mbox_ready(adata, 1);
264 
265 	return ret;
266 }
267 
configure_and_run_sha_dma(struct acp_dev_data * adata,void * image_addr,unsigned int start_addr,unsigned int dest_addr,unsigned int image_length)268 int configure_and_run_sha_dma(struct acp_dev_data *adata, void *image_addr,
269 			      unsigned int start_addr, unsigned int dest_addr,
270 			      unsigned int image_length)
271 {
272 	struct snd_sof_dev *sdev = adata->dev;
273 	unsigned int tx_count, fw_qualifier, val;
274 	int ret;
275 
276 	if (!image_addr) {
277 		dev_err(sdev->dev, "SHA DMA image address is NULL\n");
278 		return -EINVAL;
279 	}
280 
281 	val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD);
282 	if (val & ACP_SHA_RUN) {
283 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RESET);
284 		ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD_STS,
285 						    val, val & ACP_SHA_RESET,
286 						    ACP_REG_POLL_INTERVAL,
287 						    ACP_REG_POLL_TIMEOUT_US);
288 		if (ret < 0) {
289 			dev_err(sdev->dev, "SHA DMA Failed to Reset\n");
290 			return ret;
291 		}
292 	}
293 
294 	if (adata->quirks && adata->quirks->signed_fw_image)
295 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_INCLUDE_HDR, ACP_SHA_HEADER);
296 
297 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_STRT_ADDR, start_addr);
298 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_DESTINATION_ADDR, dest_addr);
299 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_MSG_LENGTH, image_length);
300 
301 	/* psp_send_cmd only required for vangogh platform */
302 	if (adata->pci_rev == ACP_VANGOGH_PCI_ID &&
303 	    !(adata->quirks && adata->quirks->skip_iram_dram_size_mod)) {
304 		/* Modify IRAM and DRAM size */
305 		ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | IRAM_DRAM_FENCE_2);
306 		if (ret)
307 			return ret;
308 		ret = psp_send_cmd(adata, MBOX_ACP_IRAM_DRAM_FENCE_COMMAND | MBOX_ISREADY_FLAG);
309 		if (ret)
310 			return ret;
311 	}
312 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SHA_DMA_CMD, ACP_SHA_RUN);
313 
314 	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_TRANSFER_BYTE_CNT,
315 					    tx_count, tx_count == image_length,
316 					    ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);
317 	if (ret < 0) {
318 		dev_err(sdev->dev, "SHA DMA Failed to Transfer Length %x\n", tx_count);
319 		return ret;
320 	}
321 
322 	/* psp_send_cmd only required for renoir platform*/
323 	if (adata->pci_rev == ACP_RN_PCI_ID) {
324 		ret = psp_send_cmd(adata, MBOX_ACP_SHA_DMA_COMMAND);
325 		if (ret)
326 			return ret;
327 	}
328 
329 	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SHA_DSP_FW_QUALIFIER,
330 					    fw_qualifier, fw_qualifier & DSP_FW_RUN_ENABLE,
331 					    ACP_REG_POLL_INTERVAL, ACP_DMA_COMPLETE_TIMEOUT_US);
332 	if (ret < 0) {
333 		val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SHA_PSP_ACK);
334 		dev_err(sdev->dev, "PSP validation failed: fw_qualifier = %#x, ACP_SHA_PSP_ACK = %#x\n",
335 			fw_qualifier, val);
336 		return ret;
337 	}
338 
339 	return 0;
340 }
341 
acp_dma_status(struct acp_dev_data * adata,unsigned char ch)342 int acp_dma_status(struct acp_dev_data *adata, unsigned char ch)
343 {
344 	struct snd_sof_dev *sdev = adata->dev;
345 	unsigned int val;
346 	unsigned int acp_dma_ch_sts;
347 	int ret = 0;
348 
349 	switch (adata->pci_rev) {
350 	case ACP70_PCI_ID:
351 		acp_dma_ch_sts = ACP70_DMA_CH_STS;
352 		break;
353 	default:
354 		acp_dma_ch_sts = ACP_DMA_CH_STS;
355 	}
356 	val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_DMA_CNTL_0 + ch * sizeof(u32));
357 	if (val & ACP_DMA_CH_RUN) {
358 		ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, acp_dma_ch_sts, val, !val,
359 						    ACP_REG_POLL_INTERVAL,
360 						    ACP_DMA_COMPLETE_TIMEOUT_US);
361 		if (ret < 0)
362 			dev_err(sdev->dev, "DMA_CHANNEL %d status timeout\n", ch);
363 	}
364 
365 	return ret;
366 }
367 
memcpy_from_scratch(struct snd_sof_dev * sdev,u32 offset,unsigned int * dst,size_t bytes)368 void memcpy_from_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *dst, size_t bytes)
369 {
370 	unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;
371 	int i, j;
372 
373 	for (i = 0, j = 0; i < bytes; i = i + 4, j++)
374 		dst[j] = snd_sof_dsp_read(sdev, ACP_DSP_BAR, reg_offset + i);
375 }
376 
memcpy_to_scratch(struct snd_sof_dev * sdev,u32 offset,unsigned int * src,size_t bytes)377 void memcpy_to_scratch(struct snd_sof_dev *sdev, u32 offset, unsigned int *src, size_t bytes)
378 {
379 	unsigned int reg_offset = offset + ACP_SCRATCH_REG_0;
380 	int i, j;
381 
382 	for (i = 0, j = 0; i < bytes; i = i + 4, j++)
383 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, reg_offset + i, src[j]);
384 }
385 
acp_memory_init(struct snd_sof_dev * sdev)386 static int acp_memory_init(struct snd_sof_dev *sdev)
387 {
388 	struct acp_dev_data *adata = sdev->pdata->hw_pdata;
389 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
390 
391 	snd_sof_dsp_update_bits(sdev, ACP_DSP_BAR, desc->dsp_intr_base + DSP_SW_INTR_CNTL_OFFSET,
392 				ACP_DSP_INTR_EN_MASK, ACP_DSP_INTR_EN_MASK);
393 	init_dma_descriptor(adata);
394 
395 	return 0;
396 }
397 
acp_irq_thread(int irq,void * context)398 static irqreturn_t acp_irq_thread(int irq, void *context)
399 {
400 	struct snd_sof_dev *sdev = context;
401 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
402 	unsigned int count = ACP_HW_SEM_RETRY_COUNT;
403 
404 	spin_lock_irq(&sdev->ipc_lock);
405 	/* Wait until acquired HW Semaphore lock or timeout */
406 	while (snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset) && --count)
407 		;
408 	spin_unlock_irq(&sdev->ipc_lock);
409 
410 	if (!count) {
411 		dev_err(sdev->dev, "%s: Failed to acquire HW lock\n", __func__);
412 		return IRQ_NONE;
413 	}
414 
415 	sof_ops(sdev)->irq_thread(irq, sdev);
416 	/* Unlock or Release HW Semaphore */
417 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->hw_semaphore_offset, 0x0);
418 
419 	return IRQ_HANDLED;
420 };
421 
acp_irq_handler(int irq,void * dev_id)422 static irqreturn_t acp_irq_handler(int irq, void *dev_id)
423 {
424 	struct amd_sdw_manager *amd_manager;
425 	struct snd_sof_dev *sdev = dev_id;
426 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
427 	struct acp_dev_data *adata = sdev->pdata->hw_pdata;
428 	unsigned int base = desc->dsp_intr_base;
429 	unsigned int val;
430 	int irq_flag = 0;
431 
432 	val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET);
433 	if (val & ACP_DSP_TO_HOST_IRQ) {
434 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + DSP_SW_INTR_STAT_OFFSET,
435 				  ACP_DSP_TO_HOST_IRQ);
436 		return IRQ_WAKE_THREAD;
437 	}
438 
439 	val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat);
440 	if (val & ACP_SDW0_IRQ_MASK) {
441 		amd_manager = dev_get_drvdata(&adata->sdw->pdev[0]->dev);
442 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_SDW0_IRQ_MASK);
443 		if (amd_manager)
444 			schedule_work(&amd_manager->amd_sdw_irq_thread);
445 		irq_flag = 1;
446 	}
447 
448 	if (val & ACP_ERROR_IRQ_MASK) {
449 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat, ACP_ERROR_IRQ_MASK);
450 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_sw0_i2s_err_reason, 0);
451 		/* ACP_SW1_I2S_ERROR_REASON is newly added register from rmb platform onwards */
452 		if (adata->pci_rev >= ACP_RMB_PCI_ID)
453 			snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SW1_I2S_ERROR_REASON, 0);
454 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_error_stat, 0);
455 		irq_flag = 1;
456 	}
457 
458 	if (desc->ext_intr_stat1) {
459 		val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, desc->ext_intr_stat1);
460 		if (val & ACP_SDW1_IRQ_MASK) {
461 			amd_manager = dev_get_drvdata(&adata->sdw->pdev[1]->dev);
462 			snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_stat1,
463 					  ACP_SDW1_IRQ_MASK);
464 			if (amd_manager)
465 				schedule_work(&amd_manager->amd_sdw_irq_thread);
466 			irq_flag = 1;
467 		}
468 	}
469 	if (irq_flag)
470 		return IRQ_HANDLED;
471 	else
472 		return IRQ_NONE;
473 }
474 
acp_power_on(struct snd_sof_dev * sdev)475 static int acp_power_on(struct snd_sof_dev *sdev)
476 {
477 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
478 	struct acp_dev_data *adata = sdev->pdata->hw_pdata;
479 	unsigned int base = desc->pgfsm_base;
480 	unsigned int val;
481 	unsigned int acp_pgfsm_status_mask, acp_pgfsm_cntl_mask;
482 	int ret;
483 
484 	val = snd_sof_dsp_read(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET);
485 
486 	if (val == ACP_POWERED_ON)
487 		return 0;
488 
489 	switch (adata->pci_rev) {
490 	case ACP_RN_PCI_ID:
491 	case ACP_VANGOGH_PCI_ID:
492 		acp_pgfsm_status_mask = ACP3X_PGFSM_STATUS_MASK;
493 		acp_pgfsm_cntl_mask = ACP3X_PGFSM_CNTL_POWER_ON_MASK;
494 		break;
495 	case ACP_RMB_PCI_ID:
496 	case ACP63_PCI_ID:
497 		acp_pgfsm_status_mask = ACP6X_PGFSM_STATUS_MASK;
498 		acp_pgfsm_cntl_mask = ACP6X_PGFSM_CNTL_POWER_ON_MASK;
499 		break;
500 	case ACP70_PCI_ID:
501 		acp_pgfsm_status_mask = ACP70_PGFSM_STATUS_MASK;
502 		acp_pgfsm_cntl_mask = ACP70_PGFSM_CNTL_POWER_ON_MASK;
503 		break;
504 	default:
505 		return -EINVAL;
506 	}
507 
508 	if (val & acp_pgfsm_status_mask)
509 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, base + PGFSM_CONTROL_OFFSET,
510 				  acp_pgfsm_cntl_mask);
511 
512 	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, base + PGFSM_STATUS_OFFSET, val,
513 					    !val, ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
514 	if (ret < 0)
515 		dev_err(sdev->dev, "timeout in ACP_PGFSM_STATUS read\n");
516 
517 	return ret;
518 }
519 
acp_reset(struct snd_sof_dev * sdev)520 static int acp_reset(struct snd_sof_dev *sdev)
521 {
522 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
523 	unsigned int val;
524 	int ret;
525 
526 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_ASSERT_RESET);
527 
528 	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val,
529 					    val & ACP_SOFT_RESET_DONE_MASK,
530 					    ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
531 	if (ret < 0) {
532 		dev_err(sdev->dev, "timeout asserting reset\n");
533 		return ret;
534 	}
535 
536 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_RELEASE_RESET);
537 
538 	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val,
539 					    ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
540 	if (ret < 0)
541 		dev_err(sdev->dev, "timeout in releasing reset\n");
542 
543 	if (desc->acp_clkmux_sel)
544 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->acp_clkmux_sel, ACP_CLOCK_ACLK);
545 
546 	if (desc->ext_intr_enb)
547 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_enb, 0x01);
548 
549 	if (desc->ext_intr_cntl)
550 		snd_sof_dsp_write(sdev, ACP_DSP_BAR, desc->ext_intr_cntl, ACP_ERROR_IRQ_MASK);
551 	return ret;
552 }
553 
acp_dsp_reset(struct snd_sof_dev * sdev)554 static int acp_dsp_reset(struct snd_sof_dev *sdev)
555 {
556 	unsigned int val;
557 	int ret;
558 
559 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_ASSERT_RESET);
560 
561 	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val,
562 					    val & ACP_DSP_SOFT_RESET_DONE_MASK,
563 					    ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
564 	if (ret < 0) {
565 		dev_err(sdev->dev, "timeout asserting reset\n");
566 		return ret;
567 	}
568 
569 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, ACP_DSP_RELEASE_RESET);
570 
571 	ret = snd_sof_dsp_read_poll_timeout(sdev, ACP_DSP_BAR, ACP_SOFT_RESET, val, !val,
572 					    ACP_REG_POLL_INTERVAL, ACP_REG_POLL_TIMEOUT_US);
573 	if (ret < 0)
574 		dev_err(sdev->dev, "timeout in releasing reset\n");
575 
576 	return ret;
577 }
578 
acp_init(struct snd_sof_dev * sdev)579 static int acp_init(struct snd_sof_dev *sdev)
580 {
581 	int ret;
582 
583 	/* power on */
584 	ret = acp_power_on(sdev);
585 	if (ret) {
586 		dev_err(sdev->dev, "ACP power on failed\n");
587 		return ret;
588 	}
589 
590 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, 0x01);
591 	/* Reset */
592 	return acp_reset(sdev);
593 }
594 
check_acp_sdw_enable_status(struct snd_sof_dev * sdev)595 static bool check_acp_sdw_enable_status(struct snd_sof_dev *sdev)
596 {
597 	struct acp_dev_data *acp_data;
598 	u32 sdw0_en, sdw1_en;
599 
600 	acp_data = sdev->pdata->hw_pdata;
601 	if (!acp_data->sdw)
602 		return false;
603 
604 	sdw0_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW0_EN);
605 	sdw1_en = snd_sof_dsp_read(sdev, ACP_DSP_BAR, ACP_SW1_EN);
606 	acp_data->sdw_en_stat = sdw0_en || sdw1_en;
607 	return acp_data->sdw_en_stat;
608 }
609 
amd_sof_acp_suspend(struct snd_sof_dev * sdev,u32 target_state)610 int amd_sof_acp_suspend(struct snd_sof_dev *sdev, u32 target_state)
611 {
612 	struct acp_dev_data *acp_data;
613 	int ret;
614 	bool enable = false;
615 
616 	acp_data = sdev->pdata->hw_pdata;
617 	/* When acp_reset() function is invoked, it will apply ACP SOFT reset and
618 	 * DSP reset. ACP Soft reset sequence will cause all ACP IP registers will
619 	 * be reset to default values which will break the ClockStop Mode functionality.
620 	 * Add a condition check to apply DSP reset when SoundWire ClockStop mode
621 	 * is selected. For the rest of the scenarios, apply acp reset sequence.
622 	 */
623 	if (check_acp_sdw_enable_status(sdev))
624 		return acp_dsp_reset(sdev);
625 
626 	ret = acp_reset(sdev);
627 	if (ret) {
628 		dev_err(sdev->dev, "ACP Reset failed\n");
629 		return ret;
630 	}
631 	if (acp_data->pci_rev == ACP70_PCI_ID)
632 		enable = true;
633 	snd_sof_dsp_write(sdev, ACP_DSP_BAR, ACP_CONTROL, enable);
634 
635 	return 0;
636 }
637 EXPORT_SYMBOL_NS(amd_sof_acp_suspend, "SND_SOC_SOF_AMD_COMMON");
638 
amd_sof_acp_resume(struct snd_sof_dev * sdev)639 int amd_sof_acp_resume(struct snd_sof_dev *sdev)
640 {
641 	int ret;
642 	struct acp_dev_data *acp_data;
643 
644 	acp_data = sdev->pdata->hw_pdata;
645 	if (!acp_data->sdw_en_stat) {
646 		ret = acp_init(sdev);
647 		if (ret) {
648 			dev_err(sdev->dev, "ACP Init failed\n");
649 			return ret;
650 		}
651 		return acp_memory_init(sdev);
652 	} else {
653 		return acp_dsp_reset(sdev);
654 	}
655 }
656 EXPORT_SYMBOL_NS(amd_sof_acp_resume, "SND_SOC_SOF_AMD_COMMON");
657 
658 #if IS_ENABLED(CONFIG_SND_SOC_SOF_AMD_SOUNDWIRE)
acp_sof_scan_sdw_devices(struct snd_sof_dev * sdev,u64 addr)659 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr)
660 {
661 	struct acpi_device *sdw_dev;
662 	struct acp_dev_data *acp_data;
663 	const struct sof_amd_acp_desc *desc = get_chip_info(sdev->pdata);
664 
665 	if (!addr)
666 		return -ENODEV;
667 
668 	acp_data = sdev->pdata->hw_pdata;
669 	sdw_dev = acpi_find_child_device(ACPI_COMPANION(sdev->dev), addr, 0);
670 	if (!sdw_dev)
671 		return -ENODEV;
672 
673 	acp_data->info.handle = sdw_dev->handle;
674 	acp_data->info.count = desc->sdw_max_link_count;
675 
676 	return amd_sdw_scan_controller(&acp_data->info);
677 }
678 
amd_sof_sdw_probe(struct snd_sof_dev * sdev)679 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev)
680 {
681 	struct acp_dev_data *acp_data;
682 	struct sdw_amd_res sdw_res;
683 	int ret;
684 
685 	acp_data = sdev->pdata->hw_pdata;
686 
687 	memset(&sdw_res, 0, sizeof(sdw_res));
688 	sdw_res.addr = acp_data->addr;
689 	sdw_res.reg_range = acp_data->reg_range;
690 	sdw_res.handle = acp_data->info.handle;
691 	sdw_res.parent = sdev->dev;
692 	sdw_res.dev = sdev->dev;
693 	sdw_res.acp_lock = &acp_data->acp_lock;
694 	sdw_res.count = acp_data->info.count;
695 	sdw_res.link_mask = acp_data->info.link_mask;
696 	sdw_res.mmio_base = sdev->bar[ACP_DSP_BAR];
697 	sdw_res.acp_rev = acp_data->pci_rev;
698 
699 	ret = sdw_amd_probe(&sdw_res, &acp_data->sdw);
700 	if (ret)
701 		dev_err(sdev->dev, "SoundWire probe failed\n");
702 	return ret;
703 }
704 
amd_sof_sdw_exit(struct snd_sof_dev * sdev)705 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev)
706 {
707 	struct acp_dev_data *acp_data;
708 
709 	acp_data = sdev->pdata->hw_pdata;
710 	if (acp_data->sdw)
711 		sdw_amd_exit(acp_data->sdw);
712 	acp_data->sdw = NULL;
713 
714 	return 0;
715 }
716 
717 #else
acp_sof_scan_sdw_devices(struct snd_sof_dev * sdev,u64 addr)718 static int acp_sof_scan_sdw_devices(struct snd_sof_dev *sdev, u64 addr)
719 {
720 	return 0;
721 }
722 
amd_sof_sdw_probe(struct snd_sof_dev * sdev)723 static int amd_sof_sdw_probe(struct snd_sof_dev *sdev)
724 {
725 	return 0;
726 }
727 
amd_sof_sdw_exit(struct snd_sof_dev * sdev)728 static int amd_sof_sdw_exit(struct snd_sof_dev *sdev)
729 {
730 	return 0;
731 }
732 #endif
733 
amd_sof_acp_probe(struct snd_sof_dev * sdev)734 int amd_sof_acp_probe(struct snd_sof_dev *sdev)
735 {
736 	struct pci_dev *pci = to_pci_dev(sdev->dev);
737 	struct acp_dev_data *adata;
738 	const struct sof_amd_acp_desc *chip;
739 	const struct dmi_system_id *dmi_id;
740 	unsigned int addr;
741 	int ret;
742 
743 	chip = get_chip_info(sdev->pdata);
744 	if (!chip) {
745 		dev_err(sdev->dev, "no such device supported, chip id:%x\n", pci->device);
746 		return -EIO;
747 	}
748 	adata = devm_kzalloc(sdev->dev, sizeof(struct acp_dev_data),
749 			     GFP_KERNEL);
750 	if (!adata)
751 		return -ENOMEM;
752 
753 	adata->dev = sdev;
754 	adata->dmic_dev = platform_device_register_data(sdev->dev, "dmic-codec",
755 							PLATFORM_DEVID_NONE, NULL, 0);
756 	if (IS_ERR(adata->dmic_dev)) {
757 		dev_err(sdev->dev, "failed to register platform for dmic codec\n");
758 		return PTR_ERR(adata->dmic_dev);
759 	}
760 	addr = pci_resource_start(pci, ACP_DSP_BAR);
761 	sdev->bar[ACP_DSP_BAR] = devm_ioremap(sdev->dev, addr, pci_resource_len(pci, ACP_DSP_BAR));
762 	if (!sdev->bar[ACP_DSP_BAR]) {
763 		dev_err(sdev->dev, "ioremap error\n");
764 		ret = -ENXIO;
765 		goto unregister_dev;
766 	}
767 
768 	pci_set_master(pci);
769 	adata->addr = addr;
770 	adata->reg_range = chip->reg_end_addr - chip->reg_start_addr;
771 	adata->pci_rev = pci->revision;
772 	mutex_init(&adata->acp_lock);
773 	sdev->pdata->hw_pdata = adata;
774 	adata->smn_dev = pci_get_device(PCI_VENDOR_ID_AMD, chip->host_bridge_id, NULL);
775 	if (!adata->smn_dev) {
776 		dev_err(sdev->dev, "Failed to get host bridge device\n");
777 		ret = -ENODEV;
778 		goto unregister_dev;
779 	}
780 
781 	ret = acp_init(sdev);
782 	if (ret < 0)
783 		goto free_smn_dev;
784 
785 	sdev->ipc_irq = pci->irq;
786 	ret = request_threaded_irq(sdev->ipc_irq, acp_irq_handler, acp_irq_thread,
787 				   IRQF_SHARED, "AudioDSP", sdev);
788 	if (ret < 0) {
789 		dev_err(sdev->dev, "failed to register IRQ %d\n",
790 			sdev->ipc_irq);
791 		goto free_smn_dev;
792 	}
793 
794 	/* scan SoundWire capabilities exposed by DSDT */
795 	ret = acp_sof_scan_sdw_devices(sdev, chip->sdw_acpi_dev_addr);
796 	if (ret < 0) {
797 		dev_dbg(sdev->dev, "skipping SoundWire, not detected with ACPI scan\n");
798 		goto skip_soundwire;
799 	}
800 	ret = amd_sof_sdw_probe(sdev);
801 	if (ret < 0) {
802 		dev_err(sdev->dev, "error: SoundWire probe error\n");
803 		free_irq(sdev->ipc_irq, sdev);
804 		pci_dev_put(adata->smn_dev);
805 		return ret;
806 	}
807 
808 skip_soundwire:
809 	sdev->dsp_box.offset = 0;
810 	sdev->dsp_box.size = BOX_SIZE_512;
811 
812 	sdev->host_box.offset = sdev->dsp_box.offset + sdev->dsp_box.size;
813 	sdev->host_box.size = BOX_SIZE_512;
814 
815 	sdev->debug_box.offset = sdev->host_box.offset + sdev->host_box.size;
816 	sdev->debug_box.size = BOX_SIZE_1024;
817 
818 	dmi_id = dmi_first_match(acp_sof_quirk_table);
819 	if (dmi_id) {
820 		adata->quirks = dmi_id->driver_data;
821 
822 		if (adata->quirks->signed_fw_image) {
823 			adata->fw_code_bin = devm_kasprintf(sdev->dev, GFP_KERNEL,
824 							    "sof-%s-code.bin",
825 							    chip->name);
826 			if (!adata->fw_code_bin) {
827 				ret = -ENOMEM;
828 				goto free_ipc_irq;
829 			}
830 
831 			adata->fw_data_bin = devm_kasprintf(sdev->dev, GFP_KERNEL,
832 							    "sof-%s-data.bin",
833 							    chip->name);
834 			if (!adata->fw_data_bin) {
835 				ret = -ENOMEM;
836 				goto free_ipc_irq;
837 			}
838 		}
839 	}
840 
841 	adata->enable_fw_debug = enable_fw_debug;
842 	acp_memory_init(sdev);
843 
844 	acp_dsp_stream_init(sdev);
845 
846 	return 0;
847 
848 free_ipc_irq:
849 	free_irq(sdev->ipc_irq, sdev);
850 free_smn_dev:
851 	pci_dev_put(adata->smn_dev);
852 unregister_dev:
853 	platform_device_unregister(adata->dmic_dev);
854 	return ret;
855 }
856 EXPORT_SYMBOL_NS(amd_sof_acp_probe, "SND_SOC_SOF_AMD_COMMON");
857 
amd_sof_acp_remove(struct snd_sof_dev * sdev)858 void amd_sof_acp_remove(struct snd_sof_dev *sdev)
859 {
860 	struct acp_dev_data *adata = sdev->pdata->hw_pdata;
861 
862 	if (adata->smn_dev)
863 		pci_dev_put(adata->smn_dev);
864 
865 	if (adata->sdw)
866 		amd_sof_sdw_exit(sdev);
867 
868 	if (sdev->ipc_irq)
869 		free_irq(sdev->ipc_irq, sdev);
870 
871 	if (adata->dmic_dev)
872 		platform_device_unregister(adata->dmic_dev);
873 
874 	acp_reset(sdev);
875 }
876 EXPORT_SYMBOL_NS(amd_sof_acp_remove, "SND_SOC_SOF_AMD_COMMON");
877 
878 MODULE_LICENSE("Dual BSD/GPL");
879 MODULE_DESCRIPTION("AMD ACP sof driver");
880 MODULE_IMPORT_NS("SOUNDWIRE_AMD_INIT");
881 MODULE_IMPORT_NS("SND_AMD_SOUNDWIRE_ACPI");
882