1 /* 2 * Copyright 2015 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #include "dm_services.h" 27 #include "dc.h" 28 #include "dc_bios_types.h" 29 #include "core_types.h" 30 #include "core_status.h" 31 #include "resource.h" 32 #include "dm_helpers.h" 33 #include "dce110_hwseq.h" 34 #include "dce110/dce110_timing_generator.h" 35 #include "dce/dce_hwseq.h" 36 #include "dce100/dce100_hwseq.h" 37 #include "gpio_service_interface.h" 38 39 #include "dce110/dce110_compressor.h" 40 41 #include "bios/bios_parser_helper.h" 42 #include "timing_generator.h" 43 #include "mem_input.h" 44 #include "opp.h" 45 #include "ipp.h" 46 #include "transform.h" 47 #include "stream_encoder.h" 48 #include "link_encoder.h" 49 #include "link_enc_cfg.h" 50 #include "link_hwss.h" 51 #include "link_service.h" 52 #include "dccg.h" 53 #include "clock_source.h" 54 #include "clk_mgr.h" 55 #include "abm.h" 56 #include "audio.h" 57 #include "reg_helper.h" 58 #include "panel_cntl.h" 59 #include "dc_state_priv.h" 60 #include "dpcd_defs.h" 61 #include "dsc.h" 62 #include "dc_dp_types.h" 63 /* include DCE11 register header files */ 64 #include "dce/dce_11_0_d.h" 65 #include "dce/dce_11_0_sh_mask.h" 66 #include "custom_float.h" 67 68 #include "atomfirmware.h" 69 70 #include "dcn10/dcn10_hwseq.h" 71 72 #define GAMMA_HW_POINTS_NUM 256 73 74 /* 75 * All values are in milliseconds; 76 * For eDP, after power-up/power/down, 77 * 300/500 msec max. delay from LCDVCC to black video generation 78 */ 79 #define PANEL_POWER_UP_TIMEOUT 300 80 #define PANEL_POWER_DOWN_TIMEOUT 500 81 #define HPD_CHECK_INTERVAL 10 82 #define OLED_POST_T7_DELAY 100 83 #define OLED_PRE_T11_DELAY 150 84 85 #define CTX \ 86 hws->ctx 87 88 #define DC_LOGGER \ 89 dc_ctx->logger 90 #define DC_LOGGER_INIT(ctx) \ 91 struct dc_context *dc_ctx = ctx 92 93 #define REG(reg)\ 94 hws->regs->reg 95 96 #undef FN 97 #define FN(reg_name, field_name) \ 98 hws->shifts->field_name, hws->masks->field_name 99 100 struct dce110_hw_seq_reg_offsets { 101 uint32_t crtc; 102 }; 103 104 static const struct dce110_hw_seq_reg_offsets reg_offsets[] = { 105 { 106 .crtc = (mmCRTC0_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 107 }, 108 { 109 .crtc = (mmCRTC1_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 110 }, 111 { 112 .crtc = (mmCRTC2_CRTC_GSL_CONTROL - mmCRTC_GSL_CONTROL), 113 }, 114 { 115 .crtc = (mmCRTCV_GSL_CONTROL - mmCRTC_GSL_CONTROL), 116 } 117 }; 118 119 #define HW_REG_BLND(reg, id)\ 120 (reg + reg_offsets[id].blnd) 121 122 #define HW_REG_CRTC(reg, id)\ 123 (reg + reg_offsets[id].crtc) 124 125 #define MAX_WATERMARK 0xFFFF 126 #define SAFE_NBP_MARK 0x7FFF 127 128 /******************************************************************************* 129 * Private definitions 130 ******************************************************************************/ 131 /***************************PIPE_CONTROL***********************************/ 132 static void dce110_init_pte(struct dc_context *ctx) 133 { 134 uint32_t addr; 135 uint32_t value = 0; 136 uint32_t chunk_int = 0; 137 uint32_t chunk_mul = 0; 138 139 addr = mmUNP_DVMM_PTE_CONTROL; 140 value = dm_read_reg(ctx, addr); 141 142 set_reg_field_value( 143 value, 144 0, 145 DVMM_PTE_CONTROL, 146 DVMM_USE_SINGLE_PTE); 147 148 set_reg_field_value( 149 value, 150 1, 151 DVMM_PTE_CONTROL, 152 DVMM_PTE_BUFFER_MODE0); 153 154 set_reg_field_value( 155 value, 156 1, 157 DVMM_PTE_CONTROL, 158 DVMM_PTE_BUFFER_MODE1); 159 160 dm_write_reg(ctx, addr, value); 161 162 addr = mmDVMM_PTE_REQ; 163 value = dm_read_reg(ctx, addr); 164 165 chunk_int = get_reg_field_value( 166 value, 167 DVMM_PTE_REQ, 168 HFLIP_PTEREQ_PER_CHUNK_INT); 169 170 chunk_mul = get_reg_field_value( 171 value, 172 DVMM_PTE_REQ, 173 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 174 175 if (chunk_int != 0x4 || chunk_mul != 0x4) { 176 177 set_reg_field_value( 178 value, 179 255, 180 DVMM_PTE_REQ, 181 MAX_PTEREQ_TO_ISSUE); 182 183 set_reg_field_value( 184 value, 185 4, 186 DVMM_PTE_REQ, 187 HFLIP_PTEREQ_PER_CHUNK_INT); 188 189 set_reg_field_value( 190 value, 191 4, 192 DVMM_PTE_REQ, 193 HFLIP_PTEREQ_PER_CHUNK_MULTIPLIER); 194 195 dm_write_reg(ctx, addr, value); 196 } 197 } 198 /**************************************************************************/ 199 200 static void enable_display_pipe_clock_gating( 201 struct dc_context *ctx, 202 bool clock_gating) 203 { 204 (void)ctx; 205 (void)clock_gating; 206 /*TODO*/ 207 } 208 209 static bool dce110_enable_display_power_gating( 210 struct dc *dc, 211 uint8_t controller_id, 212 struct dc_bios *dcb, 213 enum pipe_gating_control power_gating) 214 { 215 enum bp_result bp_result = BP_RESULT_OK; 216 enum bp_pipe_control_action cntl; 217 struct dc_context *ctx = dc->ctx; 218 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 219 220 if (power_gating == PIPE_GATING_CONTROL_INIT) 221 cntl = ASIC_PIPE_INIT; 222 else if (power_gating == PIPE_GATING_CONTROL_ENABLE) 223 cntl = ASIC_PIPE_ENABLE; 224 else 225 cntl = ASIC_PIPE_DISABLE; 226 227 if (controller_id == underlay_idx) 228 controller_id = CONTROLLER_ID_UNDERLAY0 - 1; 229 230 if (power_gating != PIPE_GATING_CONTROL_INIT || controller_id == 0) { 231 232 bp_result = dcb->funcs->enable_disp_power_gating( 233 dcb, controller_id + 1, cntl); 234 235 /* Revert MASTER_UPDATE_MODE to 0 because bios sets it 2 236 * by default when command table is called 237 * 238 * Bios parser accepts controller_id = 6 as indicative of 239 * underlay pipe in dce110. But we do not support more 240 * than 3. 241 */ 242 if (controller_id < CONTROLLER_ID_MAX - 1) 243 dm_write_reg(ctx, 244 HW_REG_CRTC(mmCRTC_MASTER_UPDATE_MODE, controller_id), 245 0); 246 } 247 248 if (power_gating != PIPE_GATING_CONTROL_ENABLE) 249 dce110_init_pte(ctx); 250 251 if (bp_result == BP_RESULT_OK) 252 return true; 253 else 254 return false; 255 } 256 257 static void dce110_prescale_params(struct ipp_prescale_params *prescale_params, 258 const struct dc_plane_state *plane_state) 259 { 260 prescale_params->mode = IPP_PRESCALE_MODE_FIXED_UNSIGNED; 261 262 switch (plane_state->format) { 263 case SURFACE_PIXEL_FORMAT_GRPH_RGB565: 264 prescale_params->scale = 0x2082; 265 break; 266 case SURFACE_PIXEL_FORMAT_GRPH_ARGB8888: 267 case SURFACE_PIXEL_FORMAT_GRPH_ABGR8888: 268 prescale_params->scale = 0x2020; 269 break; 270 case SURFACE_PIXEL_FORMAT_GRPH_ARGB2101010: 271 case SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010: 272 prescale_params->scale = 0x2008; 273 break; 274 case SURFACE_PIXEL_FORMAT_GRPH_ARGB16161616: 275 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616: 276 case SURFACE_PIXEL_FORMAT_GRPH_ABGR16161616F: 277 prescale_params->scale = 0x2000; 278 break; 279 default: 280 ASSERT(false); 281 break; 282 } 283 } 284 285 static bool 286 dce110_set_input_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 287 const struct dc_plane_state *plane_state) 288 { 289 (void)dc; 290 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 291 const struct dc_transfer_func *tf = NULL; 292 struct ipp_prescale_params prescale_params = { 0 }; 293 bool result = true; 294 295 if (ipp == NULL) 296 return false; 297 298 tf = &plane_state->in_transfer_func; 299 300 dce110_prescale_params(&prescale_params, plane_state); 301 ipp->funcs->ipp_program_prescale(ipp, &prescale_params); 302 303 if (!plane_state->gamma_correction.is_identity && 304 dce_use_lut(plane_state->format)) 305 ipp->funcs->ipp_program_input_lut(ipp, &plane_state->gamma_correction); 306 307 if (tf->type == TF_TYPE_PREDEFINED) { 308 switch (tf->tf) { 309 case TRANSFER_FUNCTION_SRGB: 310 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_sRGB); 311 break; 312 case TRANSFER_FUNCTION_BT709: 313 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_HW_xvYCC); 314 break; 315 case TRANSFER_FUNCTION_LINEAR: 316 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 317 break; 318 case TRANSFER_FUNCTION_PQ: 319 default: 320 result = false; 321 break; 322 } 323 } else if (tf->type == TF_TYPE_BYPASS) { 324 ipp->funcs->ipp_set_degamma(ipp, IPP_DEGAMMA_MODE_BYPASS); 325 } else { 326 /*TF_TYPE_DISTRIBUTED_POINTS - Not supported in DCE 11*/ 327 result = false; 328 } 329 330 return result; 331 } 332 333 static bool convert_to_custom_float(struct pwl_result_data *rgb_resulted, 334 struct curve_points *arr_points, 335 uint32_t hw_points_num) 336 { 337 struct custom_float_format fmt; 338 339 struct pwl_result_data *rgb = rgb_resulted; 340 341 uint32_t i = 0; 342 343 fmt.exponenta_bits = 6; 344 fmt.mantissa_bits = 12; 345 fmt.sign = true; 346 347 if (!convert_to_custom_float_format(arr_points[0].x, &fmt, 348 &arr_points[0].custom_float_x)) { 349 BREAK_TO_DEBUGGER(); 350 return false; 351 } 352 353 if (!convert_to_custom_float_format(arr_points[0].offset, &fmt, 354 &arr_points[0].custom_float_offset)) { 355 BREAK_TO_DEBUGGER(); 356 return false; 357 } 358 359 if (!convert_to_custom_float_format(arr_points[0].slope, &fmt, 360 &arr_points[0].custom_float_slope)) { 361 BREAK_TO_DEBUGGER(); 362 return false; 363 } 364 365 fmt.mantissa_bits = 10; 366 fmt.sign = false; 367 368 if (!convert_to_custom_float_format(arr_points[1].x, &fmt, 369 &arr_points[1].custom_float_x)) { 370 BREAK_TO_DEBUGGER(); 371 return false; 372 } 373 374 if (!convert_to_custom_float_format(arr_points[1].y, &fmt, 375 &arr_points[1].custom_float_y)) { 376 BREAK_TO_DEBUGGER(); 377 return false; 378 } 379 380 if (!convert_to_custom_float_format(arr_points[1].slope, &fmt, 381 &arr_points[1].custom_float_slope)) { 382 BREAK_TO_DEBUGGER(); 383 return false; 384 } 385 386 fmt.mantissa_bits = 12; 387 fmt.sign = true; 388 389 while (i != hw_points_num) { 390 if (!convert_to_custom_float_format(rgb->red, &fmt, 391 &rgb->red_reg)) { 392 BREAK_TO_DEBUGGER(); 393 return false; 394 } 395 396 if (!convert_to_custom_float_format(rgb->green, &fmt, 397 &rgb->green_reg)) { 398 BREAK_TO_DEBUGGER(); 399 return false; 400 } 401 402 if (!convert_to_custom_float_format(rgb->blue, &fmt, 403 &rgb->blue_reg)) { 404 BREAK_TO_DEBUGGER(); 405 return false; 406 } 407 408 if (!convert_to_custom_float_format(rgb->delta_red, &fmt, 409 &rgb->delta_red_reg)) { 410 BREAK_TO_DEBUGGER(); 411 return false; 412 } 413 414 if (!convert_to_custom_float_format(rgb->delta_green, &fmt, 415 &rgb->delta_green_reg)) { 416 BREAK_TO_DEBUGGER(); 417 return false; 418 } 419 420 if (!convert_to_custom_float_format(rgb->delta_blue, &fmt, 421 &rgb->delta_blue_reg)) { 422 BREAK_TO_DEBUGGER(); 423 return false; 424 } 425 426 ++rgb; 427 ++i; 428 } 429 430 return true; 431 } 432 433 #define MAX_LOW_POINT 25 434 #define NUMBER_REGIONS 16 435 #define NUMBER_SW_SEGMENTS 16 436 437 static bool 438 dce110_translate_regamma_to_hw_format(const struct dc_transfer_func *output_tf, 439 struct pwl_params *regamma_params) 440 { 441 struct curve_points *arr_points; 442 struct pwl_result_data *rgb_resulted; 443 struct pwl_result_data *rgb; 444 struct pwl_result_data *rgb_plus_1; 445 struct fixed31_32 y_r; 446 struct fixed31_32 y_g; 447 struct fixed31_32 y_b; 448 struct fixed31_32 y1_min; 449 struct fixed31_32 y3_max; 450 451 int32_t region_start, region_end; 452 uint32_t i, j, k, seg_distr[NUMBER_REGIONS], increment, start_index, hw_points; 453 454 if (output_tf == NULL || regamma_params == NULL || output_tf->type == TF_TYPE_BYPASS) 455 return false; 456 457 arr_points = regamma_params->arr_points; 458 rgb_resulted = regamma_params->rgb_resulted; 459 hw_points = 0; 460 461 memset(regamma_params, 0, sizeof(struct pwl_params)); 462 463 if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 464 /* 16 segments 465 * segments are from 2^-11 to 2^5 466 */ 467 region_start = -11; 468 region_end = region_start + NUMBER_REGIONS; 469 470 for (i = 0; i < NUMBER_REGIONS; i++) 471 seg_distr[i] = 4; 472 473 } else { 474 /* 10 segments 475 * segment is from 2^-10 to 2^1 476 * We include an extra segment for range [2^0, 2^1). This is to 477 * ensure that colors with normalized values of 1 don't miss the 478 * LUT. 479 */ 480 region_start = -10; 481 region_end = 1; 482 483 seg_distr[0] = 4; 484 seg_distr[1] = 4; 485 seg_distr[2] = 4; 486 seg_distr[3] = 4; 487 seg_distr[4] = 4; 488 seg_distr[5] = 4; 489 seg_distr[6] = 4; 490 seg_distr[7] = 4; 491 seg_distr[8] = 4; 492 seg_distr[9] = 4; 493 seg_distr[10] = 0; 494 seg_distr[11] = (uint32_t)-1; 495 seg_distr[12] = (uint32_t)-1; 496 seg_distr[13] = (uint32_t)-1; 497 seg_distr[14] = (uint32_t)-1; 498 seg_distr[15] = (uint32_t)-1; 499 } 500 501 for (k = 0; k < 16; k++) { 502 if (seg_distr[k] != (uint32_t)-1) 503 hw_points += (1 << seg_distr[k]); 504 } 505 506 j = 0; 507 for (k = 0; k < (uint32_t)(region_end - region_start); k++) { 508 increment = NUMBER_SW_SEGMENTS / (1 << seg_distr[k]); 509 start_index = (region_start + k + MAX_LOW_POINT) * 510 NUMBER_SW_SEGMENTS; 511 for (i = start_index; i < start_index + NUMBER_SW_SEGMENTS; 512 i += increment) { 513 if (j == hw_points - 1) 514 break; 515 rgb_resulted[j].red = output_tf->tf_pts.red[i]; 516 rgb_resulted[j].green = output_tf->tf_pts.green[i]; 517 rgb_resulted[j].blue = output_tf->tf_pts.blue[i]; 518 j++; 519 } 520 } 521 522 /* last point */ 523 start_index = (region_end + MAX_LOW_POINT) * NUMBER_SW_SEGMENTS; 524 rgb_resulted[hw_points - 1].red = output_tf->tf_pts.red[start_index]; 525 rgb_resulted[hw_points - 1].green = output_tf->tf_pts.green[start_index]; 526 rgb_resulted[hw_points - 1].blue = output_tf->tf_pts.blue[start_index]; 527 528 arr_points[0].x = dc_fixpt_pow(dc_fixpt_from_int(2), 529 dc_fixpt_from_int(region_start)); 530 arr_points[1].x = dc_fixpt_pow(dc_fixpt_from_int(2), 531 dc_fixpt_from_int(region_end)); 532 533 y_r = rgb_resulted[0].red; 534 y_g = rgb_resulted[0].green; 535 y_b = rgb_resulted[0].blue; 536 537 y1_min = dc_fixpt_min(y_r, dc_fixpt_min(y_g, y_b)); 538 539 arr_points[0].y = y1_min; 540 arr_points[0].slope = dc_fixpt_div(arr_points[0].y, 541 arr_points[0].x); 542 543 y_r = rgb_resulted[hw_points - 1].red; 544 y_g = rgb_resulted[hw_points - 1].green; 545 y_b = rgb_resulted[hw_points - 1].blue; 546 547 /* see comment above, m_arrPoints[1].y should be the Y value for the 548 * region end (m_numOfHwPoints), not last HW point(m_numOfHwPoints - 1) 549 */ 550 y3_max = dc_fixpt_max(y_r, dc_fixpt_max(y_g, y_b)); 551 552 arr_points[1].y = y3_max; 553 554 arr_points[1].slope = dc_fixpt_zero; 555 556 if (output_tf->tf == TRANSFER_FUNCTION_PQ) { 557 /* for PQ, we want to have a straight line from last HW X point, 558 * and the slope to be such that we hit 1.0 at 10000 nits. 559 */ 560 const struct fixed31_32 end_value = dc_fixpt_from_int(125); 561 562 arr_points[1].slope = dc_fixpt_div( 563 dc_fixpt_sub(dc_fixpt_one, arr_points[1].y), 564 dc_fixpt_sub(end_value, arr_points[1].x)); 565 } 566 567 regamma_params->hw_points_num = hw_points; 568 569 k = 0; 570 for (i = 1; i < 16; i++) { 571 if (seg_distr[k] != -1) { 572 regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 573 regamma_params->arr_curve_points[i].offset = 574 regamma_params->arr_curve_points[k].offset + (1 << seg_distr[k]); 575 } 576 k++; 577 } 578 579 if (seg_distr[k] != -1) 580 regamma_params->arr_curve_points[k].segments_num = seg_distr[k]; 581 582 rgb = rgb_resulted; 583 rgb_plus_1 = rgb_resulted + 1; 584 585 i = 1; 586 587 while (i != hw_points + 1) { 588 if (dc_fixpt_lt(rgb_plus_1->red, rgb->red)) 589 rgb_plus_1->red = rgb->red; 590 if (dc_fixpt_lt(rgb_plus_1->green, rgb->green)) 591 rgb_plus_1->green = rgb->green; 592 if (dc_fixpt_lt(rgb_plus_1->blue, rgb->blue)) 593 rgb_plus_1->blue = rgb->blue; 594 595 rgb->delta_red = dc_fixpt_sub(rgb_plus_1->red, rgb->red); 596 rgb->delta_green = dc_fixpt_sub(rgb_plus_1->green, rgb->green); 597 rgb->delta_blue = dc_fixpt_sub(rgb_plus_1->blue, rgb->blue); 598 599 ++rgb_plus_1; 600 ++rgb; 601 ++i; 602 } 603 604 convert_to_custom_float(rgb_resulted, arr_points, hw_points); 605 606 return true; 607 } 608 609 static bool 610 dce110_set_output_transfer_func(struct dc *dc, struct pipe_ctx *pipe_ctx, 611 const struct dc_stream_state *stream) 612 { 613 (void)dc; 614 struct transform *xfm = pipe_ctx->plane_res.xfm; 615 616 xfm->funcs->opp_power_on_regamma_lut(xfm, true); 617 xfm->regamma_params.hw_points_num = GAMMA_HW_POINTS_NUM; 618 619 if (stream->out_transfer_func.type == TF_TYPE_PREDEFINED && 620 stream->out_transfer_func.tf == TRANSFER_FUNCTION_SRGB) { 621 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_SRGB); 622 } else if (dce110_translate_regamma_to_hw_format(&stream->out_transfer_func, 623 &xfm->regamma_params)) { 624 xfm->funcs->opp_program_regamma_pwl(xfm, &xfm->regamma_params); 625 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_USER); 626 } else { 627 xfm->funcs->opp_set_regamma_mode(xfm, OPP_REGAMMA_BYPASS); 628 } 629 630 xfm->funcs->opp_power_on_regamma_lut(xfm, false); 631 632 return true; 633 } 634 635 void dce110_update_info_frame(struct pipe_ctx *pipe_ctx) 636 { 637 bool is_hdmi_tmds; 638 bool is_dp; 639 640 ASSERT(pipe_ctx->stream); 641 642 if (pipe_ctx->stream_res.stream_enc == NULL) 643 return; /* this is not root pipe */ 644 645 is_hdmi_tmds = dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal); 646 is_dp = dc_is_dp_signal(pipe_ctx->stream->signal); 647 648 if (!is_hdmi_tmds && !is_dp) 649 return; 650 651 if (is_hdmi_tmds) 652 pipe_ctx->stream_res.stream_enc->funcs->update_hdmi_info_packets( 653 pipe_ctx->stream_res.stream_enc, 654 &pipe_ctx->stream_res.encoder_info_frame); 655 else { 656 if (pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num) 657 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets_sdp_line_num( 658 pipe_ctx->stream_res.stream_enc, 659 &pipe_ctx->stream_res.encoder_info_frame); 660 661 pipe_ctx->stream_res.stream_enc->funcs->update_dp_info_packets( 662 pipe_ctx->stream_res.stream_enc, 663 &pipe_ctx->stream_res.encoder_info_frame); 664 } 665 } 666 667 static void 668 dce110_external_encoder_control(enum bp_external_encoder_control_action action, 669 struct dc_link *link, 670 struct dc_crtc_timing *timing) 671 { 672 struct dc *dc = link->ctx->dc; 673 struct dc_bios *bios = link->ctx->dc_bios; 674 const struct dc_link_settings *link_settings = &link->cur_link_settings; 675 enum bp_result bp_result = BP_RESULT_OK; 676 struct bp_external_encoder_control ext_cntl = { 677 .action = action, 678 .connector_obj_id = link->link_enc->connector, 679 .encoder_id = link->ext_enc_id, 680 .lanes_number = link_settings->lane_count, 681 .link_rate = link_settings->link_rate, 682 683 /* Use signal type of the real link encoder, ie. DP */ 684 .signal = link->connector_signal, 685 686 /* We don't know the timing yet when executing the SETUP action, 687 * so use a reasonably high default value. It seems that ENABLE 688 * can change the actual pixel clock but doesn't work with higher 689 * pixel clocks than what SETUP was called with. 690 */ 691 .pixel_clock = timing ? timing->pix_clk_100hz / 10 : 300000, 692 .color_depth = timing ? timing->display_color_depth : COLOR_DEPTH_888, 693 }; 694 DC_LOGGER_INIT(dc->ctx); 695 696 bp_result = bios->funcs->external_encoder_control(bios, &ext_cntl); 697 698 if (bp_result != BP_RESULT_OK) 699 DC_LOG_ERROR("Failed to execute external encoder action: 0x%x\n", action); 700 } 701 702 static void 703 dce110_prepare_ddc(struct dc_link *link) 704 { 705 if (link->ext_enc_id.id) 706 dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DDC_SETUP, link, NULL); 707 } 708 709 static bool 710 dce110_dac_load_detect(struct dc_link *link) 711 { 712 struct dc_bios *bios = link->ctx->dc_bios; 713 struct link_encoder *link_enc = link->link_enc; 714 enum bp_result bp_result; 715 716 bp_result = bios->funcs->dac_load_detection( 717 bios, link_enc->analog_engine, link->ext_enc_id); 718 return bp_result == BP_RESULT_OK; 719 } 720 721 void dce110_enable_stream(struct pipe_ctx *pipe_ctx) 722 { 723 enum dc_lane_count lane_count = 724 pipe_ctx->stream->link->cur_link_settings.lane_count; 725 struct dc_crtc_timing *timing = &pipe_ctx->stream->timing; 726 struct dc_link *link = pipe_ctx->stream->link; 727 const struct dc *dc = link->dc; 728 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 729 uint32_t active_total_with_borders; 730 uint32_t early_control = 0; 731 struct timing_generator *tg = pipe_ctx->stream_res.tg; 732 733 link_hwss->setup_stream_encoder(pipe_ctx); 734 735 dc->hwss.update_info_frame(pipe_ctx); 736 737 /* enable early control to avoid corruption on DP monitor*/ 738 active_total_with_borders = 739 timing->h_addressable 740 + timing->h_border_left 741 + timing->h_border_right; 742 743 if (lane_count != 0) 744 early_control = active_total_with_borders % lane_count; 745 746 if (early_control == 0) 747 early_control = lane_count; 748 749 tg->funcs->set_early_control(tg, early_control); 750 751 if (link->ext_enc_id.id) 752 dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_ENABLE, link, timing); 753 } 754 755 static enum bp_result link_transmitter_control( 756 struct dc_bios *bios, 757 struct bp_transmitter_control *cntl) 758 { 759 enum bp_result result; 760 761 result = bios->funcs->transmitter_control(bios, cntl); 762 763 return result; 764 } 765 766 /* 767 * @brief 768 * eDP only. 769 */ 770 void dce110_edp_wait_for_hpd_ready( 771 struct dc_link *link, 772 bool power_up) 773 { 774 struct graphics_object_id connector = link->link_enc->connector; 775 bool edp_hpd_high = false; 776 uint32_t time_elapsed = 0; 777 uint32_t timeout = power_up ? 778 PANEL_POWER_UP_TIMEOUT : PANEL_POWER_DOWN_TIMEOUT; 779 780 DC_LOGGER_INIT(link->ctx); 781 782 if (dal_graphics_object_id_get_connector_id(connector) 783 != CONNECTOR_ID_EDP) { 784 BREAK_TO_DEBUGGER(); 785 return; 786 } 787 788 if (!power_up) 789 /* 790 * From KV, we will not HPD low after turning off VCC - 791 * instead, we will check the SW timer in power_up(). 792 */ 793 return; 794 795 /* 796 * When we power on/off the eDP panel, 797 * we need to wait until SENSE bit is high/low. 798 */ 799 800 if (link->panel_config.pps.extra_t3_ms > 0) { 801 int extra_t3_in_ms = link->panel_config.pps.extra_t3_ms; 802 803 msleep(extra_t3_in_ms); 804 } 805 806 /* wait until timeout or panel detected */ 807 808 do { 809 if (!(link->dc->link_srv->get_hpd_state(link) ^ power_up)) { 810 edp_hpd_high = true; 811 break; 812 } 813 814 msleep(HPD_CHECK_INTERVAL); 815 816 time_elapsed += HPD_CHECK_INTERVAL; 817 } while (time_elapsed < timeout); 818 819 /* ensure that the panel is detected */ 820 if (!edp_hpd_high) 821 DC_LOG_DC("%s: wait timed out!\n", __func__); 822 } 823 824 void dce110_edp_power_control( 825 struct dc_link *link, 826 bool power_up) 827 { 828 struct dc_context *ctx = link->ctx; 829 struct bp_transmitter_control cntl = { 0 }; 830 enum bp_result bp_result; 831 uint8_t pwrseq_instance; 832 833 DC_LOGGER_INIT(ctx); 834 835 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 836 != CONNECTOR_ID_EDP) { 837 BREAK_TO_DEBUGGER(); 838 return; 839 } 840 841 if (!link->panel_cntl) 842 return; 843 if (power_up != 844 link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl)) { 845 846 unsigned long long current_ts = dm_get_timestamp(ctx); 847 unsigned long long time_since_edp_poweroff_ms = 848 div64_u64(dm_get_elapse_time_in_ns( 849 ctx, 850 current_ts, 851 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000); 852 unsigned long long time_since_edp_poweron_ms = 853 div64_u64(dm_get_elapse_time_in_ns( 854 ctx, 855 current_ts, 856 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)), 1000000); 857 DC_LOG_HW_RESUME_S3( 858 "%s: transition: power_up=%d current_ts=%llu edp_poweroff=%llu edp_poweron=%llu time_since_edp_poweroff_ms=%llu time_since_edp_poweron_ms=%llu", 859 __func__, 860 power_up, 861 current_ts, 862 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link), 863 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link), 864 time_since_edp_poweroff_ms, 865 time_since_edp_poweron_ms); 866 867 /* Send VBIOS command to prompt eDP panel power */ 868 if (power_up) { 869 /* edp requires a min of 500ms from LCDVDD off to on */ 870 unsigned long long remaining_min_edp_poweroff_time_ms = 500; 871 872 /* add time defined by a patch, if any (usually patch extra_t12_ms is 0) */ 873 if (link->local_sink != NULL) 874 remaining_min_edp_poweroff_time_ms += 875 link->panel_config.pps.extra_t12_ms; 876 877 /* Adjust remaining_min_edp_poweroff_time_ms if this is not the first time. */ 878 if (ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) { 879 if (time_since_edp_poweroff_ms < remaining_min_edp_poweroff_time_ms) 880 remaining_min_edp_poweroff_time_ms = 881 remaining_min_edp_poweroff_time_ms - time_since_edp_poweroff_ms; 882 else 883 remaining_min_edp_poweroff_time_ms = 0; 884 } 885 886 if (remaining_min_edp_poweroff_time_ms) { 887 DC_LOG_HW_RESUME_S3( 888 "%s: remaining_min_edp_poweroff_time_ms=%llu: begin wait.\n", 889 __func__, remaining_min_edp_poweroff_time_ms); 890 msleep((unsigned int)remaining_min_edp_poweroff_time_ms); 891 DC_LOG_HW_RESUME_S3( 892 "%s: remaining_min_edp_poweroff_time_ms=%llu: end wait.\n", 893 __func__, remaining_min_edp_poweroff_time_ms); 894 dm_output_to_console("%s: wait %lld ms to power on eDP.\n", 895 __func__, remaining_min_edp_poweroff_time_ms); 896 } else { 897 DC_LOG_HW_RESUME_S3( 898 "%s: remaining_min_edp_poweroff_time_ms=%llu: no wait required.\n", 899 __func__, remaining_min_edp_poweroff_time_ms); 900 } 901 } 902 903 DC_LOG_HW_RESUME_S3( 904 "%s: BEGIN: Panel Power action: %s\n", 905 __func__, (power_up ? "On":"Off")); 906 907 cntl.action = power_up ? 908 TRANSMITTER_CONTROL_POWER_ON : 909 TRANSMITTER_CONTROL_POWER_OFF; 910 cntl.transmitter = link->link_enc->transmitter; 911 cntl.connector_obj_id = link->link_enc->connector; 912 cntl.coherent = false; 913 cntl.lanes_number = LANE_COUNT_FOUR; 914 cntl.hpd_sel = link->link_enc->hpd_source; 915 pwrseq_instance = (uint8_t)link->panel_cntl->pwrseq_inst; 916 917 if (ctx->dc->ctx->dmub_srv && 918 ctx->dc->debug.dmub_command_table) { 919 920 if (cntl.action == TRANSMITTER_CONTROL_POWER_ON) { 921 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 922 LVTMA_CONTROL_POWER_ON, 923 pwrseq_instance, link->link_powered_externally); 924 } else { 925 bp_result = ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 926 LVTMA_CONTROL_POWER_OFF, 927 pwrseq_instance, link->link_powered_externally); 928 } 929 } 930 931 bp_result = link_transmitter_control(ctx->dc_bios, &cntl); 932 933 DC_LOG_HW_RESUME_S3( 934 "%s: END: Panel Power action: %s bp_result=%u\n", 935 __func__, (power_up ? "On":"Off"), 936 bp_result); 937 938 ctx->dc->link_srv->dp_trace_set_edp_power_timestamp(link, power_up); 939 940 DC_LOG_HW_RESUME_S3( 941 "%s: updated values: edp_poweroff=%llu edp_poweron=%llu\n", 942 __func__, 943 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link), 944 ctx->dc->link_srv->dp_trace_get_edp_poweron_timestamp(link)); 945 946 if (bp_result != BP_RESULT_OK) 947 DC_LOG_ERROR( 948 "%s: Panel Power bp_result: %d\n", 949 __func__, bp_result); 950 } else { 951 DC_LOG_HW_RESUME_S3( 952 "%s: Skipping Panel Power action: %s\n", 953 __func__, (power_up ? "On":"Off")); 954 } 955 } 956 957 void dce110_edp_wait_for_T12( 958 struct dc_link *link) 959 { 960 struct dc_context *ctx = link->ctx; 961 962 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 963 != CONNECTOR_ID_EDP) { 964 BREAK_TO_DEBUGGER(); 965 return; 966 } 967 968 if (!link->panel_cntl) 969 return; 970 971 if (!link->panel_cntl->funcs->is_panel_powered_on(link->panel_cntl) && 972 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link) != 0) { 973 unsigned int t12_duration = 500; // Default T12 as per spec 974 unsigned long long current_ts = dm_get_timestamp(ctx); 975 unsigned long long time_since_edp_poweroff_ms = 976 div64_u64(dm_get_elapse_time_in_ns( 977 ctx, 978 current_ts, 979 ctx->dc->link_srv->dp_trace_get_edp_poweroff_timestamp(link)), 1000000); 980 981 t12_duration += link->panel_config.pps.extra_t12_ms; // Add extra T12 982 983 if (time_since_edp_poweroff_ms < t12_duration) 984 msleep((unsigned int)(t12_duration - time_since_edp_poweroff_ms)); 985 } 986 } 987 /*todo: cloned in stream enc, fix*/ 988 /* 989 * @brief 990 * eDP only. Control the backlight of the eDP panel 991 */ 992 void dce110_edp_backlight_control( 993 struct dc_link *link, 994 bool enable) 995 { 996 struct dc_context *ctx = link->ctx; 997 struct bp_transmitter_control cntl = { 0 }; 998 uint8_t pwrseq_instance = 0; 999 unsigned int pre_T11_delay = (link->dpcd_sink_ext_caps.bits.oled ? OLED_PRE_T11_DELAY : 0); 1000 unsigned int post_T7_delay = (link->dpcd_sink_ext_caps.bits.oled ? OLED_POST_T7_DELAY : 0); 1001 1002 DC_LOGGER_INIT(ctx); 1003 1004 if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) 1005 != CONNECTOR_ID_EDP) { 1006 BREAK_TO_DEBUGGER(); 1007 return; 1008 } 1009 1010 if (link->panel_cntl && !(link->dpcd_sink_ext_caps.bits.oled || 1011 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || 1012 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1)) { 1013 bool is_backlight_on = link->panel_cntl->funcs->is_panel_backlight_on(link->panel_cntl); 1014 1015 if ((enable && is_backlight_on) || (!enable && !is_backlight_on)) { 1016 DC_LOG_HW_RESUME_S3( 1017 "%s: panel already powered up/off. Do nothing.\n", 1018 __func__); 1019 return; 1020 } 1021 } 1022 1023 /* Send VBIOS command to control eDP panel backlight */ 1024 1025 DC_LOG_HW_RESUME_S3( 1026 "%s: backlight action: %s\n", 1027 __func__, (enable ? "On":"Off")); 1028 1029 cntl.action = enable ? 1030 TRANSMITTER_CONTROL_BACKLIGHT_ON : 1031 TRANSMITTER_CONTROL_BACKLIGHT_OFF; 1032 1033 /*cntl.engine_id = ctx->engine;*/ 1034 cntl.transmitter = link->link_enc->transmitter; 1035 cntl.connector_obj_id = link->link_enc->connector; 1036 /*todo: unhardcode*/ 1037 cntl.lanes_number = LANE_COUNT_FOUR; 1038 cntl.hpd_sel = link->link_enc->hpd_source; 1039 cntl.signal = SIGNAL_TYPE_EDP; 1040 1041 /* For eDP, the following delays might need to be considered 1042 * after link training completed: 1043 * idle period - min. accounts for required BS-Idle pattern, 1044 * max. allows for source frame synchronization); 1045 * 50 msec max. delay from valid video data from source 1046 * to video on dislpay or backlight enable. 1047 * 1048 * Disable the delay for now. 1049 * Enable it in the future if necessary. 1050 */ 1051 /* dc_service_sleep_in_milliseconds(50); */ 1052 /*edp 1.2*/ 1053 if (link->panel_cntl) { 1054 pwrseq_instance = (uint8_t)link->panel_cntl->pwrseq_inst; 1055 } 1056 1057 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) { 1058 if (!link->dc->config.edp_no_power_sequencing) 1059 /* 1060 * Sometimes, DP receiver chip power-controlled externally by an 1061 * Embedded Controller could be treated and used as eDP, 1062 * if it drives mobile display. In this case, 1063 * we shouldn't be doing power-sequencing, hence we can skip 1064 * waiting for T7-ready. 1065 */ 1066 ctx->dc->link_srv->edp_receiver_ready_T7(link); 1067 else 1068 DC_LOG_DC("edp_receiver_ready_T7 skipped\n"); 1069 } 1070 1071 /* Setting link_powered_externally will bypass delays in the backlight 1072 * as they are not required if the link is being powered by a different 1073 * source. 1074 */ 1075 if (ctx->dc->ctx->dmub_srv && 1076 ctx->dc->debug.dmub_command_table) { 1077 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_ON) 1078 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 1079 LVTMA_CONTROL_LCD_BLON, 1080 pwrseq_instance, link->link_powered_externally); 1081 else 1082 ctx->dc_bios->funcs->enable_lvtma_control(ctx->dc_bios, 1083 LVTMA_CONTROL_LCD_BLOFF, 1084 pwrseq_instance, link->link_powered_externally); 1085 } 1086 1087 link_transmitter_control(ctx->dc_bios, &cntl); 1088 1089 if (enable && link->dpcd_sink_ext_caps.bits.oled && 1090 !link->dc->config.edp_no_power_sequencing && 1091 !link->local_sink->edid_caps.panel_patch.oled_optimize_display_on) { 1092 post_T7_delay += link->panel_config.pps.extra_post_t7_ms; 1093 msleep(post_T7_delay); 1094 } 1095 1096 if (link->dpcd_sink_ext_caps.bits.oled || 1097 link->dpcd_sink_ext_caps.bits.hdr_aux_backlight_control == 1 || 1098 link->dpcd_sink_ext_caps.bits.sdr_aux_backlight_control == 1) 1099 ctx->dc->link_srv->edp_backlight_enable_aux(link, enable); 1100 1101 /*edp 1.2*/ 1102 if (cntl.action == TRANSMITTER_CONTROL_BACKLIGHT_OFF) { 1103 if (!link->dc->config.edp_no_power_sequencing) 1104 /* 1105 * Sometimes, DP receiver chip power-controlled externally by an 1106 * Embedded Controller could be treated and used as eDP, 1107 * if it drives mobile display. In this case, 1108 * we shouldn't be doing power-sequencing, hence we can skip 1109 * waiting for T9-ready. 1110 */ 1111 ctx->dc->link_srv->edp_add_delay_for_T9(link); 1112 else 1113 DC_LOG_DC("edp_receiver_ready_T9 skipped\n"); 1114 } 1115 1116 if (!enable) { 1117 /*follow oem panel config's requirement*/ 1118 pre_T11_delay += link->panel_config.pps.extra_pre_t11_ms; 1119 if (pre_T11_delay) 1120 msleep(pre_T11_delay); 1121 } 1122 } 1123 1124 void dce110_enable_audio_stream(struct pipe_ctx *pipe_ctx) 1125 { 1126 /* notify audio driver for audio modes of monitor */ 1127 struct dc *dc; 1128 struct clk_mgr *clk_mgr; 1129 unsigned int i, num_audio = 1; 1130 const struct link_hwss *link_hwss; 1131 1132 if (!pipe_ctx->stream) 1133 return; 1134 1135 if (dc_is_rgb_signal(pipe_ctx->stream->signal)) 1136 return; 1137 1138 dc = pipe_ctx->stream->ctx->dc; 1139 clk_mgr = dc->clk_mgr; 1140 link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res); 1141 1142 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == true) 1143 return; 1144 1145 if (pipe_ctx->stream_res.audio) { 1146 for (i = 0; i < MAX_PIPES; i++) { 1147 /*current_state not updated yet*/ 1148 if (dc->current_state->res_ctx.pipe_ctx[i].stream_res.audio != NULL) 1149 num_audio++; 1150 } 1151 if (num_audio >= 1 && clk_mgr->funcs->enable_pme_wa) { 1152 /*wake AZ from D3 first before access az endpoint*/ 1153 clk_mgr->funcs->enable_pme_wa(clk_mgr); 1154 } 1155 1156 pipe_ctx->stream_res.audio->funcs->az_enable(pipe_ctx->stream_res.audio); 1157 1158 link_hwss->enable_audio_packet(pipe_ctx); 1159 1160 if (pipe_ctx->stream_res.audio) 1161 pipe_ctx->stream_res.audio->enabled = true; 1162 } 1163 } 1164 1165 void dce110_disable_audio_stream(struct pipe_ctx *pipe_ctx) 1166 { 1167 struct dc *dc; 1168 struct clk_mgr *clk_mgr; 1169 const struct link_hwss *link_hwss; 1170 1171 if (!pipe_ctx || !pipe_ctx->stream) 1172 return; 1173 1174 if (dc_is_rgb_signal(pipe_ctx->stream->signal)) 1175 return; 1176 1177 dc = pipe_ctx->stream->ctx->dc; 1178 clk_mgr = dc->clk_mgr; 1179 link_hwss = get_link_hwss(pipe_ctx->stream->link, &pipe_ctx->link_res); 1180 1181 if (pipe_ctx->stream_res.audio && pipe_ctx->stream_res.audio->enabled == false) 1182 return; 1183 1184 link_hwss->disable_audio_packet(pipe_ctx); 1185 1186 if (pipe_ctx->stream_res.audio) { 1187 pipe_ctx->stream_res.audio->enabled = false; 1188 1189 if (clk_mgr->funcs->enable_pme_wa) 1190 /*this is the first audio. apply the PME w/a in order to wake AZ from D3*/ 1191 clk_mgr->funcs->enable_pme_wa(clk_mgr); 1192 1193 /* TODO: notify audio driver for if audio modes list changed 1194 * add audio mode list change flag */ 1195 /* dal_audio_disable_azalia_audio_jack_presence(stream->audio, 1196 * stream->stream_engine_id); 1197 */ 1198 } 1199 } 1200 1201 void dce110_disable_stream(struct pipe_ctx *pipe_ctx) 1202 { 1203 struct dc_stream_state *stream = pipe_ctx->stream; 1204 struct dc_link *link = stream->link; 1205 struct dc *dc = pipe_ctx->stream->ctx->dc; 1206 const struct link_hwss *link_hwss = get_link_hwss(link, &pipe_ctx->link_res); 1207 struct dccg *dccg = dc->res_pool->dccg; 1208 struct timing_generator *tg = pipe_ctx->stream_res.tg; 1209 struct dtbclk_dto_params dto_params = {0}; 1210 int dp_hpo_inst; 1211 struct link_encoder *link_enc = pipe_ctx->link_res.dio_link_enc; 1212 struct stream_encoder *stream_enc = pipe_ctx->stream_res.stream_enc; 1213 1214 if (!dc->config.unify_link_enc_assignment) 1215 link_enc = link_enc_cfg_get_link_enc(link); 1216 1217 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal)) { 1218 pipe_ctx->stream_res.stream_enc->funcs->stop_hdmi_info_packets( 1219 pipe_ctx->stream_res.stream_enc); 1220 pipe_ctx->stream_res.stream_enc->funcs->hdmi_reset_stream_attribute( 1221 pipe_ctx->stream_res.stream_enc); 1222 } 1223 1224 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 1225 pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->stop_hdmi_info_packets( 1226 pipe_ctx->stream_res.hpo_frl_stream_enc); 1227 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1228 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->stop_dp_info_packets( 1229 pipe_ctx->stream_res.hpo_dp_stream_enc); 1230 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1231 pipe_ctx->stream_res.stream_enc->funcs->stop_dp_info_packets( 1232 pipe_ctx->stream_res.stream_enc); 1233 1234 dc->hwss.disable_audio_stream(pipe_ctx); 1235 1236 link_hwss->reset_stream_encoder(pipe_ctx); 1237 1238 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx) && dccg) { 1239 dto_params.otg_inst = tg->inst; 1240 dto_params.timing = &pipe_ctx->stream->timing; 1241 dp_hpo_inst = pipe_ctx->stream_res.hpo_dp_stream_enc->inst; 1242 if (dccg) { 1243 dccg->funcs->disable_symclk32_se(dccg, dp_hpo_inst); 1244 dccg->funcs->set_dpstreamclk(dccg, REFCLK, tg->inst, dp_hpo_inst); 1245 if (!(dc->ctx->dce_version >= DCN_VERSION_3_5)) { 1246 if (dccg && dccg->funcs->set_dtbclk_dto) 1247 dccg->funcs->set_dtbclk_dto(dccg, &dto_params); 1248 } 1249 } 1250 } else if (dccg && dccg->funcs->disable_symclk_se) { 1251 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_FRL) 1252 dccg->funcs->disable_symclk_se(dccg, stream_enc->stream_enc_inst, 1253 link_enc->transmitter - TRANSMITTER_UNIPHY_A); 1254 } 1255 1256 if (link->ext_enc_id.id) 1257 dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_DISABLE, link, NULL); 1258 } 1259 1260 void dce110_unblank_stream(struct pipe_ctx *pipe_ctx, 1261 struct dc_link_settings *link_settings) 1262 { 1263 struct encoder_unblank_param params = { { 0 } }; 1264 struct dc_stream_state *stream = pipe_ctx->stream; 1265 struct dc_link *link = stream->link; 1266 struct dce_hwseq *hws = link->dc->hwseq; 1267 1268 /* only 3 items below are used by unblank */ 1269 params.timing = pipe_ctx->stream->timing; 1270 params.link_settings.link_rate = link_settings->link_rate; 1271 1272 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1273 pipe_ctx->stream_res.stream_enc->funcs->dp_unblank(link, pipe_ctx->stream_res.stream_enc, ¶ms); 1274 1275 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1276 hws->funcs.edp_backlight_control(link, true); 1277 } 1278 } 1279 1280 void dce110_blank_stream(struct pipe_ctx *pipe_ctx) 1281 { 1282 struct dc_stream_state *stream = pipe_ctx->stream; 1283 struct dc_link *link = stream->link; 1284 struct dce_hwseq *hws = link->dc->hwseq; 1285 1286 if (hws && hws->wa_state.skip_blank_stream) 1287 return; 1288 1289 if (link->local_sink && link->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1290 if (!link->skip_implict_edp_power_control && hws) 1291 hws->funcs.edp_backlight_control(link, false); 1292 link->dc->hwss.set_abm_immediate_disable(pipe_ctx); 1293 } 1294 1295 if (link->dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1296 /* TODO - DP2.0 HW: Set ODM mode in dp hpo encoder here */ 1297 pipe_ctx->stream_res.hpo_dp_stream_enc->funcs->dp_blank( 1298 pipe_ctx->stream_res.hpo_dp_stream_enc); 1299 } else if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1300 pipe_ctx->stream_res.stream_enc->funcs->dp_blank(link, pipe_ctx->stream_res.stream_enc); 1301 1302 if (!dc_is_embedded_signal(pipe_ctx->stream->signal)) { 1303 /* 1304 * After output is idle pattern some sinks need time to recognize the stream 1305 * has changed or they enter protection state and hang. 1306 */ 1307 msleep(60); 1308 } 1309 } 1310 1311 if (pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 1312 !link->dc->config.edp_no_power_sequencing) { 1313 /* 1314 * Sometimes, DP receiver chip power-controlled externally by an 1315 * Embedded Controller could be treated and used as eDP, 1316 * if it drives mobile display. In this case, 1317 * we shouldn't be doing power-sequencing, hence we can skip 1318 * waiting for T9-ready. 1319 */ 1320 link->dc->link_srv->edp_receiver_ready_T9(link); 1321 } 1322 1323 if (dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) { 1324 pipe_ctx->stream_res.hpo_frl_stream_enc->funcs->hdmi_frl_blank(pipe_ctx->stream_res.hpo_frl_stream_enc); 1325 1326 /* Set HDMISTREAMCLK source to REFCLK */ 1327 if (link->dc->res_pool->dccg && 1328 link->dc->res_pool->dccg->funcs->set_hdmistreamclk) { 1329 link->dc->res_pool->dccg->funcs->set_hdmistreamclk( 1330 link->dc->res_pool->dccg, 1331 REFCLK, 1332 pipe_ctx->stream_res.tg->inst); 1333 } 1334 } 1335 } 1336 1337 1338 void dce110_set_avmute(struct pipe_ctx *pipe_ctx, bool enable) 1339 { 1340 if (pipe_ctx != NULL && pipe_ctx->stream_res.stream_enc != NULL) 1341 pipe_ctx->stream_res.stream_enc->funcs->set_avmute(pipe_ctx->stream_res.stream_enc, enable); 1342 } 1343 1344 enum audio_dto_source translate_to_dto_source(enum controller_id crtc_id) 1345 { 1346 switch (crtc_id) { 1347 case CONTROLLER_ID_D0: 1348 return DTO_SOURCE_ID0; 1349 case CONTROLLER_ID_D1: 1350 return DTO_SOURCE_ID1; 1351 case CONTROLLER_ID_D2: 1352 return DTO_SOURCE_ID2; 1353 case CONTROLLER_ID_D3: 1354 return DTO_SOURCE_ID3; 1355 case CONTROLLER_ID_D4: 1356 return DTO_SOURCE_ID4; 1357 case CONTROLLER_ID_D5: 1358 return DTO_SOURCE_ID5; 1359 default: 1360 return DTO_SOURCE_UNKNOWN; 1361 } 1362 } 1363 1364 void populate_audio_dp_link_info( 1365 const struct pipe_ctx *pipe_ctx, 1366 struct audio_dp_link_info *dp_link_info) 1367 { 1368 const struct dc_stream_state *stream = pipe_ctx->stream; 1369 const struct dc_link *link = stream->link; 1370 struct fixed31_32 link_bw_kbps; 1371 1372 dp_link_info->encoding = link->dc->link_srv->dp_get_encoding_format( 1373 &pipe_ctx->link_config.dp_link_settings); 1374 dp_link_info->is_mst = (stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST); 1375 dp_link_info->lane_count = pipe_ctx->link_config.dp_link_settings.lane_count; 1376 dp_link_info->link_rate = pipe_ctx->link_config.dp_link_settings.link_rate; 1377 1378 link_bw_kbps = dc_fixpt_from_int(dc_link_bandwidth_kbps(link, 1379 &pipe_ctx->link_config.dp_link_settings)); 1380 1381 /* For audio stream calculations, the video stream should not include FEC or SSC 1382 * in order to get the most pessimistic values. 1383 */ 1384 if (dp_link_info->encoding == DP_8b_10b_ENCODING && 1385 link->dc->link_srv->dp_is_fec_supported(link)) { 1386 link_bw_kbps = dc_fixpt_mul(link_bw_kbps, 1387 dc_fixpt_from_fraction(100, DATA_EFFICIENCY_8b_10b_FEC_EFFICIENCY_x100)); 1388 } else if (dp_link_info->encoding == DP_128b_132b_ENCODING) { 1389 link_bw_kbps = dc_fixpt_mul(link_bw_kbps, 1390 dc_fixpt_from_fraction(10000, 9975)); /* 99.75% SSC overhead*/ 1391 } 1392 1393 dp_link_info->link_bandwidth_kbps = dc_fixpt_floor(link_bw_kbps); 1394 1395 /* Calculates hblank_min_symbol_width for 128b/132b 1396 * Corresponding HBLANK_MIN_SYMBOL_WIDTH register is calculated as: 1397 * floor(h_blank * bits_per_pixel / 128) 1398 */ 1399 if (dp_link_info->encoding == DP_128b_132b_ENCODING) { 1400 struct dc_crtc_timing *crtc_timing = &pipe_ctx->stream->timing; 1401 1402 uint32_t h_active = crtc_timing->h_addressable + crtc_timing->h_border_left 1403 + crtc_timing->h_border_right; 1404 uint32_t h_blank = crtc_timing->h_total - h_active; 1405 1406 uint32_t bpp; 1407 1408 if (crtc_timing->flags.DSC) { 1409 bpp = crtc_timing->dsc_cfg.bits_per_pixel; 1410 } else { 1411 /* When the timing is using DSC, dsc_cfg.bits_per_pixel is in 16th bits. 1412 * The bpp in this path is scaled to 16th bits so the final calculation 1413 * is correct for both cases. 1414 */ 1415 bpp = 16; 1416 switch (crtc_timing->display_color_depth) { 1417 case COLOR_DEPTH_666: 1418 bpp *= 18; 1419 break; 1420 case COLOR_DEPTH_888: 1421 bpp *= 24; 1422 break; 1423 case COLOR_DEPTH_101010: 1424 bpp *= 30; 1425 break; 1426 case COLOR_DEPTH_121212: 1427 bpp *= 36; 1428 break; 1429 default: 1430 bpp = 0; 1431 break; 1432 } 1433 1434 switch (crtc_timing->pixel_encoding) { 1435 case PIXEL_ENCODING_YCBCR422: 1436 bpp = bpp * 2 / 3; 1437 break; 1438 case PIXEL_ENCODING_YCBCR420: 1439 bpp /= 2; 1440 break; 1441 default: 1442 break; 1443 } 1444 } 1445 1446 /* Min symbol width = floor(h_blank * (bpp/16) / 128) */ 1447 dp_link_info->hblank_min_symbol_width = dc_fixpt_floor( 1448 dc_fixpt_div(dc_fixpt_from_int(h_blank * bpp), 1449 dc_fixpt_from_int(128 / 16))); 1450 1451 } else { 1452 dp_link_info->hblank_min_symbol_width = 0; 1453 } 1454 } 1455 1456 void build_audio_output( 1457 struct dc_state *state, 1458 const struct pipe_ctx *pipe_ctx, 1459 struct audio_output *audio_output) 1460 { 1461 const struct dc_stream_state *stream = pipe_ctx->stream; 1462 audio_output->engine_id = pipe_ctx->stream_res.stream_enc->id; 1463 1464 audio_output->signal = pipe_ctx->stream->signal; 1465 1466 /* audio_crtc_info */ 1467 1468 audio_output->crtc_info.h_total = 1469 stream->timing.h_total; 1470 1471 /* 1472 * Audio packets are sent during actual CRTC blank physical signal, we 1473 * need to specify actual active signal portion 1474 */ 1475 audio_output->crtc_info.h_active = 1476 stream->timing.h_addressable 1477 + stream->timing.h_border_left 1478 + stream->timing.h_border_right; 1479 1480 audio_output->crtc_info.v_active = 1481 stream->timing.v_addressable 1482 + stream->timing.v_border_top 1483 + stream->timing.v_border_bottom; 1484 1485 audio_output->crtc_info.pixel_repetition = 1; 1486 1487 audio_output->crtc_info.interlaced = 1488 (stream->timing.flags.INTERLACE != 0); 1489 1490 audio_output->crtc_info.refresh_rate = 1491 (uint16_t)((stream->timing.pix_clk_100hz*100)/ 1492 (stream->timing.h_total*stream->timing.v_total)); 1493 1494 audio_output->crtc_info.color_depth = 1495 stream->timing.display_color_depth; 1496 1497 audio_output->crtc_info.requested_pixel_clock_100Hz = 1498 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 1499 1500 audio_output->crtc_info.calculated_pixel_clock_100Hz = 1501 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz; 1502 1503 audio_output->crtc_info.pixel_encoding = 1504 stream->timing.pixel_encoding; 1505 1506 audio_output->crtc_info.dsc_bits_per_pixel = 1507 stream->timing.dsc_cfg.bits_per_pixel; 1508 1509 audio_output->crtc_info.dsc_num_slices = 1510 stream->timing.dsc_cfg.num_slices_h; 1511 1512 /*for HDMI, audio ACR is with deep color ratio factor*/ 1513 if (dc_is_hdmi_tmds_signal(pipe_ctx->stream->signal) && 1514 audio_output->crtc_info.requested_pixel_clock_100Hz == 1515 (stream->timing.pix_clk_100hz)) { 1516 if (pipe_ctx->stream_res.pix_clk_params.pixel_encoding == PIXEL_ENCODING_YCBCR420) { 1517 audio_output->crtc_info.requested_pixel_clock_100Hz = 1518 audio_output->crtc_info.requested_pixel_clock_100Hz/2; 1519 audio_output->crtc_info.calculated_pixel_clock_100Hz = 1520 pipe_ctx->stream_res.pix_clk_params.requested_pix_clk_100hz/2; 1521 1522 } 1523 } 1524 if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_FRL) { 1525 switch (pipe_ctx->stream->link->frl_link_settings.frl_link_rate) { 1526 case HDMI_FRL_LINK_RATE_3GBPS: 1527 audio_output->crtc_info.frl_character_clock_kHz = 166667; 1528 break; 1529 case HDMI_FRL_LINK_RATE_6GBPS: 1530 case HDMI_FRL_LINK_RATE_6GBPS_4LANE: 1531 audio_output->crtc_info.frl_character_clock_kHz = 333333; 1532 break; 1533 case HDMI_FRL_LINK_RATE_8GBPS: 1534 audio_output->crtc_info.frl_character_clock_kHz = 444444; 1535 break; 1536 case HDMI_FRL_LINK_RATE_10GBPS: 1537 audio_output->crtc_info.frl_character_clock_kHz = 555555; 1538 break; 1539 case HDMI_FRL_LINK_RATE_12GBPS: 1540 default: 1541 audio_output->crtc_info.frl_character_clock_kHz = 666667; 1542 break; 1543 } 1544 } else 1545 audio_output->crtc_info.frl_character_clock_kHz = 0; 1546 1547 if (state->clk_mgr && 1548 (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT || 1549 pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_FRL || 1550 pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)) { 1551 audio_output->pll_info.audio_dto_source_clock_in_khz = 1552 state->clk_mgr->funcs->get_dp_ref_clk_frequency( 1553 state->clk_mgr); 1554 } 1555 1556 audio_output->pll_info.dto_source = 1557 translate_to_dto_source( 1558 pipe_ctx->stream_res.tg->inst + 1); 1559 1560 /* TODO hard code to enable for now. Need get from stream */ 1561 audio_output->pll_info.ss_enabled = true; 1562 1563 audio_output->pll_info.ss_percentage = 1564 pipe_ctx->pll_settings.ss_percentage; 1565 1566 if (dc_is_dp_signal(pipe_ctx->stream->signal)) { 1567 populate_audio_dp_link_info(pipe_ctx, &audio_output->dp_link_info); 1568 } 1569 } 1570 1571 static void program_scaler(const struct dc *dc, 1572 const struct pipe_ctx *pipe_ctx) 1573 { 1574 struct tg_color color = {0}; 1575 1576 /* TOFPGA */ 1577 if (pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth == NULL) 1578 return; 1579 1580 if (dc->debug.visual_confirm == VISUAL_CONFIRM_SURFACE) 1581 get_surface_visual_confirm_color(pipe_ctx, &color); 1582 else 1583 color_space_to_black_color(dc, 1584 pipe_ctx->stream->output_color_space, 1585 &color); 1586 1587 pipe_ctx->plane_res.xfm->funcs->transform_set_pixel_storage_depth( 1588 pipe_ctx->plane_res.xfm, 1589 pipe_ctx->plane_res.scl_data.lb_params.depth, 1590 &pipe_ctx->stream->bit_depth_params); 1591 1592 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { 1593 /* 1594 * The way 420 is packed, 2 channels carry Y component, 1 channel 1595 * alternate between Cb and Cr, so both channels need the pixel 1596 * value for Y 1597 */ 1598 if (pipe_ctx->stream->timing.pixel_encoding == PIXEL_ENCODING_YCBCR420) 1599 color.color_r_cr = color.color_g_y; 1600 1601 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( 1602 pipe_ctx->stream_res.tg, 1603 &color); 1604 } 1605 1606 pipe_ctx->plane_res.xfm->funcs->transform_set_scaler(pipe_ctx->plane_res.xfm, 1607 &pipe_ctx->plane_res.scl_data); 1608 } 1609 1610 static enum dc_status dce110_enable_stream_timing( 1611 struct pipe_ctx *pipe_ctx, 1612 struct dc_state *context, 1613 struct dc *dc) 1614 { 1615 (void)context; 1616 struct dc_stream_state *stream = pipe_ctx->stream; 1617 struct pipe_ctx *pipe_ctx_old = &dc->current_state->res_ctx. 1618 pipe_ctx[pipe_ctx->pipe_idx]; 1619 struct tg_color black_color = {0}; 1620 1621 if (!pipe_ctx_old->stream) { 1622 1623 /* program blank color */ 1624 color_space_to_black_color(dc, 1625 stream->output_color_space, &black_color); 1626 pipe_ctx->stream_res.tg->funcs->set_blank_color( 1627 pipe_ctx->stream_res.tg, 1628 &black_color); 1629 1630 /* 1631 * Must blank CRTC after disabling power gating and before any 1632 * programming, otherwise CRTC will be hung in bad state 1633 */ 1634 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); 1635 1636 if (false == pipe_ctx->clock_source->funcs->program_pix_clk( 1637 pipe_ctx->clock_source, 1638 &pipe_ctx->stream_res.pix_clk_params, 1639 dc->link_srv->dp_get_encoding_format(&pipe_ctx->link_config.dp_link_settings), 1640 &pipe_ctx->pll_settings)) { 1641 BREAK_TO_DEBUGGER(); 1642 return DC_ERROR_UNEXPECTED; 1643 } 1644 1645 if (dc_is_tmds_signal(stream->signal)) { 1646 stream->link->phy_state.symclk_ref_cnts.otg = 1; 1647 if (stream->link->phy_state.symclk_state == SYMCLK_OFF_TX_OFF) 1648 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_OFF; 1649 else 1650 stream->link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 1651 } 1652 1653 pipe_ctx->stream_res.tg->funcs->program_timing( 1654 pipe_ctx->stream_res.tg, 1655 &stream->timing, 1656 0, 1657 0, 1658 0, 1659 0, 1660 0, 1661 pipe_ctx->stream->signal, 1662 true); 1663 } 1664 1665 if (!pipe_ctx_old->stream) { 1666 if (false == pipe_ctx->stream_res.tg->funcs->enable_crtc( 1667 pipe_ctx->stream_res.tg)) { 1668 BREAK_TO_DEBUGGER(); 1669 return DC_ERROR_UNEXPECTED; 1670 } 1671 } 1672 1673 return DC_OK; 1674 } 1675 1676 enum dc_status dce110_apply_single_controller_ctx_to_hw( 1677 struct pipe_ctx *pipe_ctx, 1678 struct dc_state *context, 1679 struct dc *dc) 1680 { 1681 struct dc_stream_state *stream = pipe_ctx->stream; 1682 struct dc_link *link = stream->link; 1683 struct drr_params params = {0}; 1684 unsigned int event_triggers = 0; 1685 struct pipe_ctx *odm_pipe = pipe_ctx->next_odm_pipe; 1686 struct dce_hwseq *hws = dc->hwseq; 1687 const struct link_hwss *link_hwss = get_link_hwss( 1688 link, &pipe_ctx->link_res); 1689 1690 1691 if (hws->funcs.disable_stream_gating) { 1692 hws->funcs.disable_stream_gating(dc, pipe_ctx); 1693 } 1694 1695 if (pipe_ctx->stream_res.audio != NULL) { 1696 struct audio_output audio_output = {0}; 1697 1698 build_audio_output(context, pipe_ctx, &audio_output); 1699 1700 link_hwss->setup_audio_output(pipe_ctx, &audio_output, 1701 pipe_ctx->stream_res.audio->inst); 1702 1703 pipe_ctx->stream_res.audio->funcs->az_configure( 1704 pipe_ctx->stream_res.audio, 1705 pipe_ctx->stream->signal, 1706 &audio_output.crtc_info, 1707 &pipe_ctx->stream->audio_info, 1708 &audio_output.dp_link_info); 1709 1710 if (dc->config.disable_hbr_audio_dp2) 1711 if (pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio && 1712 dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) 1713 pipe_ctx->stream_res.audio->funcs->az_disable_hbr_audio(pipe_ctx->stream_res.audio); 1714 } 1715 1716 /* make sure no pipes syncd to the pipe being enabled */ 1717 if (!pipe_ctx->stream->apply_seamless_boot_optimization && dc->config.use_pipe_ctx_sync_logic) 1718 check_syncd_pipes_for_disabled_master_pipe(dc, context, pipe_ctx->pipe_idx); 1719 1720 pipe_ctx->stream_res.opp->funcs->opp_program_fmt( 1721 pipe_ctx->stream_res.opp, 1722 &stream->bit_depth_params, 1723 &stream->clamping); 1724 1725 pipe_ctx->stream_res.opp->funcs->opp_set_dyn_expansion( 1726 pipe_ctx->stream_res.opp, 1727 COLOR_SPACE_YCBCR601, 1728 stream->timing.display_color_depth, 1729 stream->signal); 1730 1731 while (odm_pipe) { 1732 odm_pipe->stream_res.opp->funcs->opp_set_dyn_expansion( 1733 odm_pipe->stream_res.opp, 1734 COLOR_SPACE_YCBCR601, 1735 stream->timing.display_color_depth, 1736 stream->signal); 1737 1738 odm_pipe->stream_res.opp->funcs->opp_program_fmt( 1739 odm_pipe->stream_res.opp, 1740 &stream->bit_depth_params, 1741 &stream->clamping); 1742 odm_pipe = odm_pipe->next_odm_pipe; 1743 } 1744 1745 /* DCN3.1 FPGA Workaround 1746 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1747 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1748 * function core_link_enable_stream 1749 */ 1750 if (!(hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx))) 1751 /* */ 1752 /* Do not touch stream timing on seamless boot optimization. */ 1753 if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1754 hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 1755 1756 if (hws->funcs.setup_vupdate_interrupt) 1757 hws->funcs.setup_vupdate_interrupt(dc, pipe_ctx); 1758 1759 params.vertical_total_min = stream->adjust.v_total_min; 1760 params.vertical_total_max = stream->adjust.v_total_max; 1761 set_drr_and_clear_adjust_pending(pipe_ctx, stream, ¶ms); 1762 1763 // DRR should set trigger event to monitor surface update event 1764 if (stream->adjust.v_total_min != 0 && stream->adjust.v_total_max != 0) 1765 event_triggers = 0x80; 1766 /* Event triggers and num frames initialized for DRR, but can be 1767 * later updated for PSR use. Note DRR trigger events are generated 1768 * regardless of whether num frames met. 1769 */ 1770 if (pipe_ctx->stream_res.tg->funcs->set_static_screen_control) 1771 pipe_ctx->stream_res.tg->funcs->set_static_screen_control( 1772 pipe_ctx->stream_res.tg, event_triggers, 2); 1773 1774 if (!dc_is_virtual_signal(pipe_ctx->stream->signal) && 1775 !dc_is_hdmi_frl_signal(pipe_ctx->stream->signal)) 1776 pipe_ctx->stream_res.stream_enc->funcs->dig_connect_to_otg( 1777 pipe_ctx->stream_res.stream_enc, 1778 pipe_ctx->stream_res.tg->inst); 1779 1780 if (dc_is_dp_signal(pipe_ctx->stream->signal)) 1781 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_CONNECT_DIG_FE_OTG); 1782 1783 /* Temporary workaround to perform DSC programming ahead of stream enablement 1784 * for smartmux/SPRS 1785 * TODO: Remove SmartMux/SPRS checks once movement of DSC programming is generalized 1786 */ 1787 if (pipe_ctx->stream->timing.flags.DSC) { 1788 if ((pipe_ctx->stream->signal == SIGNAL_TYPE_EDP && 1789 ((link->dc->config.smart_mux_version && link->dc->is_switch_in_progress_dest) 1790 || link->is_dds || link->skip_implict_edp_power_control)) && 1791 (dc_is_dp_signal(pipe_ctx->stream->signal) || 1792 dc_is_virtual_signal(pipe_ctx->stream->signal))) 1793 dc->link_srv->set_dsc_enable(pipe_ctx, true); 1794 } 1795 1796 if (!stream->dpms_off) 1797 dc->link_srv->set_dpms_on(context, pipe_ctx); 1798 1799 /* DCN3.1 FPGA Workaround 1800 * Need to enable HPO DP Stream Encoder before setting OTG master enable. 1801 * To do so, move calling function enable_stream_timing to only be done AFTER calling 1802 * function core_link_enable_stream 1803 */ 1804 if (hws->wa.dp_hpo_and_otg_sequence && dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 1805 if (!pipe_ctx->stream->apply_seamless_boot_optimization) 1806 hws->funcs.enable_stream_timing(pipe_ctx, context, dc); 1807 } 1808 1809 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; 1810 1811 /* Phantom and main stream share the same link (because the stream 1812 * is constructed with the same sink). Make sure not to override 1813 * and link programming on the main. 1814 */ 1815 if (dc_state_get_pipe_subvp_type(context, pipe_ctx) != SUBVP_PHANTOM) { 1816 pipe_ctx->stream->link->psr_settings.psr_feature_enabled = false; 1817 pipe_ctx->stream->link->replay_settings.replay_feature_enabled = false; 1818 } 1819 return DC_OK; 1820 } 1821 1822 /******************************************************************************/ 1823 1824 static void power_down_encoders(struct dc *dc) 1825 { 1826 int i; 1827 1828 for (i = 0; i < dc->link_count; i++) { 1829 struct dc_link *link = dc->links[i]; 1830 struct link_encoder *link_enc = link_enc_cfg_get_link_enc(link); 1831 enum signal_type signal = link->connector_signal; 1832 1833 dc->link_srv->blank_dp_stream(link, false); 1834 if (signal != SIGNAL_TYPE_EDP) 1835 signal = SIGNAL_TYPE_NONE; 1836 1837 if (link->ep_type == DISPLAY_ENDPOINT_PHY && link_enc) 1838 link_enc->funcs->disable_output(link_enc, signal); 1839 1840 if (link->fec_state == dc_link_fec_enabled) { 1841 if (link_enc && link_enc->funcs->fec_set_enable && link_enc->funcs->fec_set_ready) { 1842 link_enc->funcs->fec_set_enable(link_enc, false); 1843 link_enc->funcs->fec_set_ready(link_enc, false); 1844 link->fec_state = dc_link_fec_not_ready; 1845 } 1846 } 1847 1848 link->link_status.link_active = false; 1849 memset(&link->cur_link_settings, 0, sizeof(link->cur_link_settings)); 1850 } 1851 } 1852 1853 static void power_down_controllers(struct dc *dc) 1854 { 1855 unsigned int i; 1856 1857 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 1858 dc->res_pool->timing_generators[i]->funcs->disable_crtc( 1859 dc->res_pool->timing_generators[i]); 1860 } 1861 } 1862 1863 static void power_down_clock_sources(struct dc *dc) 1864 { 1865 unsigned int i; 1866 1867 if (dc->res_pool->dp_clock_source->funcs->cs_power_down( 1868 dc->res_pool->dp_clock_source) == false) 1869 dm_error("Failed to power down pll! (dp clk src)\n"); 1870 1871 for (i = 0; i < dc->res_pool->clk_src_count; i++) { 1872 if (dc->res_pool->clock_sources[i]->funcs->cs_power_down( 1873 dc->res_pool->clock_sources[i]) == false) 1874 dm_error("Failed to power down pll! (clk src index=%u)\n", i); 1875 } 1876 } 1877 1878 static void power_down_all_hw_blocks(struct dc *dc) 1879 { 1880 power_down_encoders(dc); 1881 1882 power_down_controllers(dc); 1883 1884 power_down_clock_sources(dc); 1885 1886 if (dc->fbc_compressor) 1887 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 1888 } 1889 1890 static void disable_vga_and_power_gate_all_controllers( 1891 struct dc *dc) 1892 { 1893 uint8_t i; 1894 struct timing_generator *tg; 1895 struct dc_context *ctx = dc->ctx; 1896 1897 if (dc->caps.ips_support) 1898 return; 1899 1900 for (i = 0; i < dc->res_pool->timing_generator_count; i++) { 1901 tg = dc->res_pool->timing_generators[i]; 1902 1903 if (tg->funcs->disable_vga) 1904 tg->funcs->disable_vga(tg); 1905 } 1906 for (i = 0; i < dc->res_pool->pipe_count; i++) { 1907 /* Enable CLOCK gating for each pipe BEFORE controller 1908 * powergating. */ 1909 enable_display_pipe_clock_gating(ctx, 1910 true); 1911 1912 dc->current_state->res_ctx.pipe_ctx[i].pipe_idx = i; 1913 dc->hwss.disable_plane(dc, dc->current_state, 1914 &dc->current_state->res_ctx.pipe_ctx[i]); 1915 } 1916 } 1917 1918 1919 static void get_edp_streams(struct dc_state *context, 1920 struct dc_stream_state **edp_streams, 1921 int *edp_stream_num) 1922 { 1923 uint8_t i; 1924 1925 *edp_stream_num = 0; 1926 for (i = 0; i < context->stream_count; i++) { 1927 if (context->streams[i]->signal == SIGNAL_TYPE_EDP) { 1928 edp_streams[*edp_stream_num] = context->streams[i]; 1929 if (++(*edp_stream_num) == MAX_NUM_EDP) 1930 return; 1931 } 1932 } 1933 } 1934 1935 static void get_edp_links_with_sink( 1936 struct dc *dc, 1937 struct dc_link **edp_links_with_sink, 1938 int *edp_with_sink_num) 1939 { 1940 int i; 1941 1942 /* check if there is an eDP panel not in use */ 1943 *edp_with_sink_num = 0; 1944 for (i = 0; i < dc->link_count; i++) { 1945 if (dc->links[i]->local_sink && 1946 dc->links[i]->local_sink->sink_signal == SIGNAL_TYPE_EDP) { 1947 edp_links_with_sink[*edp_with_sink_num] = dc->links[i]; 1948 if (++(*edp_with_sink_num) == MAX_NUM_EDP) 1949 return; 1950 } 1951 } 1952 } 1953 1954 static void clean_up_dsc_blocks(struct dc *dc) 1955 { 1956 struct display_stream_compressor *dsc = NULL; 1957 struct timing_generator *tg = NULL; 1958 struct stream_encoder *se = NULL; 1959 struct dccg *dccg = dc->res_pool->dccg; 1960 struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl; 1961 unsigned int i; 1962 1963 if (!dc->caps.is_apu || 1964 dc->ctx->dce_version < DCN_VERSION_3_15) 1965 return; 1966 /*VBIOS supports dsc starts from dcn315*/ 1967 for (i = 0; i < (unsigned int)dc->res_pool->res_cap->num_dsc; i++) { 1968 struct dcn_dsc_state s = {0}; 1969 1970 dsc = dc->res_pool->dscs[i]; 1971 dsc->funcs->dsc_read_state(dsc, &s); 1972 if (s.dsc_fw_en) { 1973 /* disable DSC in OPTC */ 1974 if (i < dc->res_pool->timing_generator_count) { 1975 tg = dc->res_pool->timing_generators[i]; 1976 if (tg->funcs->set_dsc_config) 1977 tg->funcs->set_dsc_config(tg, OPTC_DSC_DISABLED, 0, 0); 1978 } 1979 /* disable DSC in stream encoder */ 1980 if (i < dc->res_pool->stream_enc_count) { 1981 se = dc->res_pool->stream_enc[i]; 1982 if (se->funcs->dp_set_dsc_config) 1983 se->funcs->dp_set_dsc_config(se, OPTC_DSC_DISABLED, 0, 0); 1984 if (se->funcs->dp_set_dsc_pps_info_packet) 1985 se->funcs->dp_set_dsc_pps_info_packet(se, false, NULL, true); 1986 } 1987 /* disable DSC block */ 1988 if (dccg->funcs->set_ref_dscclk) 1989 dccg->funcs->set_ref_dscclk(dccg, dsc->inst); 1990 dsc->funcs->dsc_disable(dsc); 1991 1992 /* power down DSC */ 1993 if (pg_cntl != NULL) 1994 pg_cntl->funcs->dsc_pg_control(pg_cntl, dsc->inst, false); 1995 } 1996 } 1997 } 1998 1999 static void dc_hwss_enable_otg_pwa( 2000 struct dc *dc, 2001 struct pipe_ctx *pipe_ctx) 2002 { 2003 struct timing_generator *tg = NULL; 2004 2005 if (dc->debug.enable_otg_frame_sync_pwa == 0) 2006 return; 2007 2008 if (pipe_ctx == NULL || pipe_ctx->stream_res.tg == NULL) 2009 return; 2010 tg = pipe_ctx->stream_res.tg; 2011 2012 /*only enable this if one active*/ 2013 if (tg->funcs->enable_otg_pwa) { 2014 struct otc_pwa_frame_sync pwa_param = {0}; 2015 2016 DC_LOGGER_INIT(dc->ctx); 2017 /* mode 1 to choose generate pwa sync signal on line 0 counting 2018 * from vstartup at very beginning of the frame 2019 */ 2020 pwa_param.pwa_frame_sync_line_offset = 0; 2021 pwa_param.pwa_sync_mode = DC_OTG_PWA_FRAME_SYNC_MODE_VSTARTUP; 2022 /*frame sync line for generating high frame sync*/ 2023 tg->funcs->enable_otg_pwa(tg, &pwa_param); 2024 DC_LOG_DC("Enable OTG PWA frame sync on TG %d\n", tg->inst); 2025 } 2026 } 2027 2028 /* 2029 * When ASIC goes from VBIOS/VGA mode to driver/accelerated mode we need: 2030 * 1. Power down all DC HW blocks 2031 * 2. Disable VGA engine on all controllers 2032 * 3. Enable power gating for controller 2033 * 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS) 2034 */ 2035 void dce110_enable_accelerated_mode(struct dc *dc, struct dc_state *context) 2036 { 2037 struct dc_link *edp_links_with_sink[MAX_NUM_EDP]; 2038 struct dc_link *edp_links[MAX_NUM_EDP]; 2039 struct dc_stream_state *edp_streams[MAX_NUM_EDP]; 2040 struct dc_link *edp_link_with_sink = NULL; 2041 struct dc_link *edp_link = NULL; 2042 struct pipe_ctx *pipe_ctx = NULL; 2043 struct dce_hwseq *hws = dc->hwseq; 2044 int edp_with_sink_num; 2045 unsigned int j, edp_num; 2046 int edp_stream_num; 2047 int i; 2048 bool can_apply_edp_fast_boot = false; 2049 bool can_apply_seamless_boot = false; 2050 bool keep_edp_vdd_on = false; 2051 bool should_clean_dsc_block = true; 2052 struct dc_bios *dcb = dc->ctx->dc_bios; 2053 DC_LOGGER_INIT(dc->ctx); 2054 2055 get_edp_links_with_sink(dc, edp_links_with_sink, &edp_with_sink_num); 2056 dc_get_edp_links(dc, edp_links, &edp_num); 2057 2058 if (hws->funcs.init_pipes) 2059 hws->funcs.init_pipes(dc, context); 2060 2061 get_edp_streams(context, edp_streams, &edp_stream_num); 2062 2063 /* Check fastboot support, disable on DCE 6-8-10 because of blank screens */ 2064 if (edp_num && edp_stream_num && dc->ctx->dce_version > DCE_VERSION_10_0) { 2065 for (j = 0; j < edp_num; j++) { 2066 edp_link = edp_links[j]; 2067 if (edp_link != edp_streams[0]->link) 2068 continue; 2069 // enable fastboot if backend is enabled on eDP 2070 if (edp_link->link_enc->funcs->is_dig_enabled && 2071 edp_link->link_enc->funcs->is_dig_enabled(edp_link->link_enc) && 2072 edp_link->link_status.link_active) { 2073 struct dc_stream_state *edp_stream = edp_streams[0]; 2074 2075 can_apply_edp_fast_boot = dc_validate_boot_timing(dc, 2076 edp_stream->sink, &edp_stream->timing); 2077 2078 // For Mux-platform, the default value is false. 2079 // Disable fast boot during mux switching. 2080 // The flag would be clean after switching done. 2081 if (dc->is_switch_in_progress_dest && edp_link->is_dds) 2082 can_apply_edp_fast_boot = false; 2083 2084 edp_stream->apply_edp_fast_boot_optimization = can_apply_edp_fast_boot; 2085 if (can_apply_edp_fast_boot) { 2086 DC_LOG_EVENT_LINK_TRAINING("eDP fast boot Enable\n"); 2087 2088 // Vbios & Driver support different pixel rate div policy. 2089 pipe_ctx = resource_get_otg_master_for_stream(&context->res_ctx, edp_stream); 2090 if (pipe_ctx && 2091 hws->funcs.is_dp_dig_pixel_rate_div_policy && 2092 hws->funcs.is_dp_dig_pixel_rate_div_policy(pipe_ctx)) { 2093 // Get Vbios div factor from register 2094 dc->res_pool->dccg->funcs->get_pixel_rate_div( 2095 dc->res_pool->dccg, 2096 pipe_ctx->stream_res.tg->inst, 2097 &pipe_ctx->pixel_rate_divider.div_factor1, 2098 &pipe_ctx->pixel_rate_divider.div_factor2); 2099 2100 // VBios doesn't support pixel rate div, so force it. 2101 // If VBios supports it, we check it from reigster or other flags. 2102 pipe_ctx->stream_res.pix_clk_params.dio_se_pix_per_cycle = 1; 2103 } 2104 dc_hwss_enable_otg_pwa(dc, pipe_ctx); 2105 } 2106 break; 2107 } 2108 } 2109 // We are trying to enable eDP, don't power down VDD 2110 if (can_apply_edp_fast_boot) 2111 keep_edp_vdd_on = true; 2112 } 2113 2114 // Check seamless boot support 2115 for (i = 0; i < context->stream_count; i++) { 2116 if (context->streams[i]->apply_seamless_boot_optimization) { 2117 can_apply_seamless_boot = true; 2118 break; 2119 } 2120 } 2121 2122 /* eDP should not have stream in resume from S4 and so even with VBios post 2123 * it should get turned off 2124 */ 2125 if (edp_with_sink_num) 2126 edp_link_with_sink = edp_links_with_sink[0]; 2127 2128 // During a mux switch, powering down the HW blocks and then enabling 2129 // the link via a DPCD SET_POWER write causes a brief flash 2130 keep_edp_vdd_on |= dc->is_switch_in_progress_dest; 2131 2132 if (!can_apply_edp_fast_boot && !can_apply_seamless_boot) { 2133 if (edp_link_with_sink && !keep_edp_vdd_on) { 2134 /*turn off backlight before DP_blank and encoder powered down*/ 2135 hws->funcs.edp_backlight_control(edp_link_with_sink, false); 2136 } 2137 /*resume from S3, no vbios posting, no need to power down again*/ 2138 if (dcb && dcb->funcs && !dcb->funcs->is_accelerated_mode(dcb)) 2139 clk_mgr_exit_optimized_pwr_state(dc, dc->clk_mgr); 2140 2141 power_down_all_hw_blocks(dc); 2142 2143 /* DSC could be enabled on eDP during VBIOS post. 2144 * To clean up dsc blocks if all eDP dpms_off is true. 2145 */ 2146 for (i = 0; i < edp_stream_num; i++) { 2147 if (!edp_streams[i]->dpms_off) { 2148 should_clean_dsc_block = false; 2149 } 2150 } 2151 2152 if (should_clean_dsc_block) 2153 clean_up_dsc_blocks(dc); 2154 2155 disable_vga_and_power_gate_all_controllers(dc); 2156 if (edp_link_with_sink && !keep_edp_vdd_on) 2157 dc->hwss.edp_power_control(edp_link_with_sink, false); 2158 if (dcb && dcb->funcs && !dcb->funcs->is_accelerated_mode(dcb)) 2159 clk_mgr_optimize_pwr_state(dc, dc->clk_mgr); 2160 } 2161 bios_set_scratch_acc_mode_change(dc->ctx->dc_bios, 1); 2162 } 2163 2164 static uint32_t compute_pstate_blackout_duration( 2165 struct bw_fixed blackout_duration, 2166 const struct dc_stream_state *stream) 2167 { 2168 uint32_t total_dest_line_time_ns; 2169 int64_t pstate_blackout_duration_ns64; 2170 uint32_t pstate_blackout_duration_ns; 2171 2172 pstate_blackout_duration_ns64 = (1000 * blackout_duration.value) >> 24; 2173 pstate_blackout_duration_ns = (uint32_t)pstate_blackout_duration_ns64; 2174 2175 total_dest_line_time_ns = 1000000UL * 2176 (stream->timing.h_total * 10) / 2177 stream->timing.pix_clk_100hz + 2178 pstate_blackout_duration_ns; 2179 2180 return total_dest_line_time_ns; 2181 } 2182 2183 static void dce110_set_displaymarks( 2184 const struct dc *dc, 2185 struct dc_state *context) 2186 { 2187 uint8_t i, num_pipes; 2188 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 2189 2190 for (i = 0, num_pipes = 0; i < MAX_PIPES; i++) { 2191 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2192 uint32_t total_dest_line_time_ns; 2193 2194 if (pipe_ctx->stream == NULL) 2195 continue; 2196 2197 total_dest_line_time_ns = compute_pstate_blackout_duration( 2198 dc->bw_vbios->blackout_duration, pipe_ctx->stream); 2199 pipe_ctx->plane_res.mi->funcs->mem_input_program_display_marks( 2200 pipe_ctx->plane_res.mi, 2201 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 2202 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 2203 context->bw_ctx.bw.dce.stutter_entry_wm_ns[num_pipes], 2204 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 2205 total_dest_line_time_ns); 2206 if (i == underlay_idx) { 2207 num_pipes++; 2208 pipe_ctx->plane_res.mi->funcs->mem_input_program_chroma_display_marks( 2209 pipe_ctx->plane_res.mi, 2210 context->bw_ctx.bw.dce.nbp_state_change_wm_ns[num_pipes], 2211 context->bw_ctx.bw.dce.stutter_exit_wm_ns[num_pipes], 2212 context->bw_ctx.bw.dce.urgent_wm_ns[num_pipes], 2213 total_dest_line_time_ns); 2214 } 2215 num_pipes++; 2216 } 2217 } 2218 2219 void dce110_set_safe_displaymarks( 2220 struct resource_context *res_ctx, 2221 const struct resource_pool *pool) 2222 { 2223 int i; 2224 int underlay_idx = pool->underlay_pipe_index; 2225 struct dce_watermarks max_marks = { 2226 MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK, MAX_WATERMARK }; 2227 struct dce_watermarks nbp_marks = { 2228 SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK, SAFE_NBP_MARK }; 2229 struct dce_watermarks min_marks = { 0, 0, 0, 0}; 2230 2231 for (i = 0; i < MAX_PIPES; i++) { 2232 if (res_ctx->pipe_ctx[i].stream == NULL || res_ctx->pipe_ctx[i].plane_res.mi == NULL) 2233 continue; 2234 2235 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_display_marks( 2236 res_ctx->pipe_ctx[i].plane_res.mi, 2237 nbp_marks, 2238 max_marks, 2239 min_marks, 2240 max_marks, 2241 MAX_WATERMARK); 2242 2243 if (i == underlay_idx) 2244 res_ctx->pipe_ctx[i].plane_res.mi->funcs->mem_input_program_chroma_display_marks( 2245 res_ctx->pipe_ctx[i].plane_res.mi, 2246 nbp_marks, 2247 max_marks, 2248 max_marks, 2249 MAX_WATERMARK); 2250 2251 } 2252 } 2253 2254 /******************************************************************************* 2255 * Public functions 2256 ******************************************************************************/ 2257 2258 static void set_drr(struct pipe_ctx **pipe_ctx, 2259 int num_pipes, struct dc_crtc_timing_adjust adjust) 2260 { 2261 int i = 0; 2262 struct drr_params params = {0}; 2263 // DRR should set trigger event to monitor surface update event 2264 unsigned int event_triggers = 0x80; 2265 // Note DRR trigger events are generated regardless of whether num frames met. 2266 unsigned int num_frames = 2; 2267 2268 params.vertical_total_max = adjust.v_total_max; 2269 params.vertical_total_min = adjust.v_total_min; 2270 2271 /* TODO: If multiple pipes are to be supported, you need 2272 * some GSL stuff. Static screen triggers may be programmed differently 2273 * as well. 2274 */ 2275 for (i = 0; i < num_pipes; i++) { 2276 /* dc_state_destruct() might null the stream resources, so fetch tg 2277 * here first to avoid a race condition. The lifetime of the pointee 2278 * itself (the timing_generator object) is not a problem here. 2279 */ 2280 struct timing_generator *tg = pipe_ctx[i]->stream_res.tg; 2281 2282 if ((tg != NULL) && tg->funcs) { 2283 set_drr_and_clear_adjust_pending(pipe_ctx[i], pipe_ctx[i]->stream, ¶ms); 2284 if (adjust.v_total_max != 0 && adjust.v_total_min != 0) 2285 if (tg->funcs->set_static_screen_control) 2286 tg->funcs->set_static_screen_control( 2287 tg, event_triggers, num_frames); 2288 } 2289 } 2290 } 2291 2292 static void get_position(struct pipe_ctx **pipe_ctx, 2293 int num_pipes, 2294 struct crtc_position *position) 2295 { 2296 int i = 0; 2297 2298 /* TODO: handle pipes > 1 2299 */ 2300 for (i = 0; i < num_pipes; i++) 2301 pipe_ctx[i]->stream_res.tg->funcs->get_position(pipe_ctx[i]->stream_res.tg, position); 2302 } 2303 2304 static void set_static_screen_control(struct pipe_ctx **pipe_ctx, 2305 int num_pipes, const struct dc_static_screen_params *params) 2306 { 2307 int i; 2308 unsigned int triggers = 0; 2309 2310 if (params->triggers.overlay_update) 2311 triggers |= 0x100; 2312 if (params->triggers.surface_update) 2313 triggers |= 0x80; 2314 if (params->triggers.cursor_update) 2315 triggers |= 0x2; 2316 if (params->triggers.force_trigger) 2317 triggers |= 0x1; 2318 2319 if (num_pipes) { 2320 struct dc *dc = pipe_ctx[0]->stream->ctx->dc; 2321 2322 if (dc->fbc_compressor) 2323 triggers |= 0x84; 2324 } 2325 2326 for (i = 0; i < num_pipes; i++) 2327 pipe_ctx[i]->stream_res.tg->funcs-> 2328 set_static_screen_control(pipe_ctx[i]->stream_res.tg, 2329 triggers, params->num_frames); 2330 } 2331 2332 /* 2333 * Check if FBC can be enabled 2334 */ 2335 static bool should_enable_fbc(struct dc *dc, 2336 struct dc_state *context, 2337 uint32_t *pipe_idx) 2338 { 2339 uint32_t i; 2340 struct pipe_ctx *pipe_ctx = NULL; 2341 struct resource_context *res_ctx = &context->res_ctx; 2342 unsigned int underlay_idx = dc->res_pool->underlay_pipe_index; 2343 2344 2345 ASSERT(dc->fbc_compressor); 2346 2347 /* FBC memory should be allocated */ 2348 if (!dc->ctx->fbc_gpu_addr) 2349 return false; 2350 2351 /* Only supports single display */ 2352 if (context->stream_count != 1) 2353 return false; 2354 2355 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2356 if (res_ctx->pipe_ctx[i].stream) { 2357 2358 pipe_ctx = &res_ctx->pipe_ctx[i]; 2359 2360 /* fbc not applicable on underlay pipe */ 2361 if (pipe_ctx->pipe_idx != underlay_idx) { 2362 *pipe_idx = i; 2363 break; 2364 } 2365 } 2366 } 2367 2368 if (i == dc->res_pool->pipe_count) 2369 return false; 2370 2371 if (!pipe_ctx->stream->link) 2372 return false; 2373 2374 /* Only supports eDP */ 2375 if (pipe_ctx->stream->link->connector_signal != SIGNAL_TYPE_EDP) 2376 return false; 2377 2378 /* PSR should not be enabled */ 2379 if (pipe_ctx->stream->link->psr_settings.psr_feature_enabled) 2380 return false; 2381 2382 /* Replay should not be enabled */ 2383 if (pipe_ctx->stream->link->replay_settings.replay_feature_enabled) 2384 return false; 2385 2386 /* Nothing to compress */ 2387 if (!pipe_ctx->plane_state) 2388 return false; 2389 2390 /* Only for non-linear tiling */ 2391 if (pipe_ctx->plane_state->tiling_info.gfx8.array_mode == DC_ARRAY_LINEAR_GENERAL) 2392 return false; 2393 2394 return true; 2395 } 2396 2397 /* 2398 * Enable FBC 2399 */ 2400 void enable_fbc( 2401 struct dc *dc, 2402 struct dc_state *context) 2403 { 2404 uint32_t pipe_idx = 0; 2405 2406 if (should_enable_fbc(dc, context, &pipe_idx)) { 2407 /* Program GRPH COMPRESSED ADDRESS and PITCH */ 2408 struct compr_addr_and_pitch_params params = {0, 0, 0}; 2409 struct compressor *compr = dc->fbc_compressor; 2410 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx]; 2411 2412 params.source_view_width = pipe_ctx->stream->timing.h_addressable; 2413 params.source_view_height = pipe_ctx->stream->timing.v_addressable; 2414 params.inst = pipe_ctx->stream_res.tg->inst; 2415 compr->compr_surface_address.quad_part = dc->ctx->fbc_gpu_addr; 2416 2417 compr->funcs->surface_address_and_pitch(compr, ¶ms); 2418 compr->funcs->set_fbc_invalidation_triggers(compr, 1); 2419 2420 compr->funcs->enable_fbc(compr, ¶ms); 2421 } 2422 } 2423 2424 static void dce110_reset_hw_ctx_wrap( 2425 struct dc *dc, 2426 struct dc_state *context) 2427 { 2428 int i; 2429 2430 /* Reset old context */ 2431 /* look up the targets that have been removed since last commit */ 2432 for (i = 0; i < MAX_PIPES; i++) { 2433 struct pipe_ctx *pipe_ctx_old = 2434 &dc->current_state->res_ctx.pipe_ctx[i]; 2435 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2436 2437 /* Note: We need to disable output if clock sources change, 2438 * since bios does optimization and doesn't apply if changing 2439 * PHY when not already disabled. 2440 */ 2441 2442 /* Skip underlay pipe since it will be handled in commit surface*/ 2443 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) 2444 continue; 2445 2446 if (!pipe_ctx->stream || 2447 pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) { 2448 struct clock_source *old_clk = pipe_ctx_old->clock_source; 2449 2450 /* Disable if new stream is null. O/w, if stream is 2451 * disabled already, no need to disable again. 2452 */ 2453 if (!pipe_ctx->stream || !pipe_ctx->stream->dpms_off) { 2454 dc->link_srv->set_dpms_off(pipe_ctx_old); 2455 2456 /* free acquired resources*/ 2457 if (pipe_ctx_old->stream_res.audio) { 2458 /*disable az_endpoint*/ 2459 pipe_ctx_old->stream_res.audio->funcs-> 2460 az_disable(pipe_ctx_old->stream_res.audio); 2461 2462 /*free audio*/ 2463 if (dc->caps.dynamic_audio == true) { 2464 /*we have to dynamic arbitrate the audio endpoints*/ 2465 /*we free the resource, need reset is_audio_acquired*/ 2466 update_audio_usage(&dc->current_state->res_ctx, dc->res_pool, 2467 pipe_ctx_old->stream_res.audio, false); 2468 pipe_ctx_old->stream_res.audio = NULL; 2469 } 2470 } 2471 } 2472 2473 pipe_ctx_old->stream_res.tg->funcs->set_blank(pipe_ctx_old->stream_res.tg, true); 2474 if (!hwss_wait_for_blank_complete(pipe_ctx_old->stream_res.tg)) { 2475 dm_error("DC: failed to blank crtc!\n"); 2476 BREAK_TO_DEBUGGER(); 2477 } 2478 pipe_ctx_old->stream_res.tg->funcs->disable_crtc(pipe_ctx_old->stream_res.tg); 2479 if (dc_is_tmds_signal(pipe_ctx_old->stream->signal)) 2480 pipe_ctx_old->stream->link->phy_state.symclk_ref_cnts.otg = 0; 2481 pipe_ctx_old->plane_res.mi->funcs->free_mem_input( 2482 pipe_ctx_old->plane_res.mi, dc->current_state->stream_count); 2483 2484 if (old_clk && 0 == resource_get_clock_source_reference(&context->res_ctx, 2485 dc->res_pool, 2486 old_clk)) 2487 old_clk->funcs->cs_power_down(old_clk); 2488 2489 dc->hwss.disable_plane(dc, dc->current_state, pipe_ctx_old); 2490 2491 pipe_ctx_old->stream = NULL; 2492 } 2493 } 2494 } 2495 2496 static void dce110_setup_audio_dto( 2497 struct dc *dc, 2498 struct dc_state *context) 2499 { 2500 unsigned int i; 2501 2502 /* program audio wall clock. use HDMI as clock source if HDMI 2503 * audio active. Otherwise, use DP as clock source 2504 * first, loop to find any HDMI audio, if not, loop find DP audio 2505 */ 2506 /* Setup audio rate clock source */ 2507 /* Issue: 2508 * Audio lag happened on DP monitor when unplug a HDMI monitor 2509 * 2510 * Cause: 2511 * In case of DP and HDMI connected or HDMI only, DCCG_AUDIO_DTO_SEL 2512 * is set to either dto0 or dto1, audio should work fine. 2513 * In case of DP connected only, DCCG_AUDIO_DTO_SEL should be dto1, 2514 * set to dto0 will cause audio lag. 2515 * 2516 * Solution: 2517 * Not optimized audio wall dto setup. When mode set, iterate pipe_ctx, 2518 * find first available pipe with audio, setup audio wall DTO per topology 2519 * instead of per pipe. 2520 */ 2521 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2522 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2523 2524 if (pipe_ctx->stream == NULL) 2525 continue; 2526 2527 if (pipe_ctx->top_pipe) 2528 continue; 2529 if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A && 2530 pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_FRL) 2531 continue; 2532 if (pipe_ctx->stream_res.audio != NULL) { 2533 struct audio_output audio_output; 2534 2535 build_audio_output(context, pipe_ctx, &audio_output); 2536 2537 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { 2538 struct dtbclk_dto_params dto_params = {0}; 2539 dto_params.ref_dtbclk_khz = dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); 2540 2541 if (pipe_ctx->stream->signal == SIGNAL_TYPE_HDMI_FRL) { 2542 /* For DCN3.1, audio to HPO FRL encoder is using audio DTBCLK DTO */ 2543 /* set audio DTBCLK DTO to 24MHz */ 2544 dto_params.req_audio_dtbclk_khz = 24000; 2545 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( 2546 dc->res_pool->dccg, 2547 &dto_params); 2548 } else { 2549 /* Audio DTBCLK params default to disabled */ 2550 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( 2551 dc->res_pool->dccg, 2552 &dto_params); 2553 2554 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2555 pipe_ctx->stream_res.audio, 2556 pipe_ctx->stream->signal, 2557 &audio_output.crtc_info, 2558 &audio_output.pll_info); 2559 } 2560 } else 2561 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2562 pipe_ctx->stream_res.audio, 2563 pipe_ctx->stream->signal, 2564 &audio_output.crtc_info, 2565 &audio_output.pll_info); 2566 break; 2567 } 2568 } 2569 2570 /* no HDMI audio is found, try DP audio */ 2571 if (i == dc->res_pool->pipe_count) { 2572 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2573 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2574 2575 if (pipe_ctx->stream == NULL) 2576 continue; 2577 2578 if (pipe_ctx->top_pipe) 2579 continue; 2580 2581 if (!dc_is_dp_signal(pipe_ctx->stream->signal)) 2582 continue; 2583 2584 if (pipe_ctx->stream_res.audio != NULL) { 2585 struct audio_output audio_output = {0}; 2586 2587 build_audio_output(context, pipe_ctx, &audio_output); 2588 2589 /* Audio to HPO DP encoder is using audio DTBCLK DTO */ 2590 if (dc->res_pool->dccg && dc->res_pool->dccg->funcs->set_audio_dtbclk_dto) { 2591 struct dtbclk_dto_params dto_params = {0}; 2592 dto_params.ref_dtbclk_khz = 2593 dc->clk_mgr->funcs->get_dtb_ref_clk_frequency(dc->clk_mgr); 2594 2595 if (dc->link_srv->dp_is_128b_132b_signal(pipe_ctx)) { 2596 /* set audio DTBCLK DTO to 24MHz */ 2597 dto_params.req_audio_dtbclk_khz = 24000; 2598 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( 2599 dc->res_pool->dccg, 2600 &dto_params); 2601 } else { 2602 /* Audio DTBCLK params default to disabled */ 2603 dc->res_pool->dccg->funcs->set_audio_dtbclk_dto( 2604 dc->res_pool->dccg, 2605 &dto_params); 2606 2607 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2608 pipe_ctx->stream_res.audio, 2609 pipe_ctx->stream->signal, 2610 &audio_output.crtc_info, 2611 &audio_output.pll_info); 2612 } 2613 } else { 2614 pipe_ctx->stream_res.audio->funcs->wall_dto_setup( 2615 pipe_ctx->stream_res.audio, 2616 pipe_ctx->stream->signal, 2617 &audio_output.crtc_info, 2618 &audio_output.pll_info); 2619 } 2620 break; 2621 } 2622 } 2623 } 2624 } 2625 2626 enum dc_status dce110_apply_ctx_to_hw( 2627 struct dc *dc, 2628 struct dc_state *context) 2629 { 2630 struct dce_hwseq *hws = dc->hwseq; 2631 struct dc_bios *dcb = dc->ctx->dc_bios; 2632 enum dc_status status; 2633 unsigned int i; 2634 bool was_hpo_acquired = resource_is_hpo_acquired(dc->current_state); 2635 bool is_hpo_acquired = resource_is_hpo_acquired(context); 2636 2637 /* reset syncd pipes from disabled pipes */ 2638 if (dc->config.use_pipe_ctx_sync_logic) 2639 reset_syncd_pipes_from_disabled_pipes(dc, context); 2640 2641 /* Reset old context */ 2642 /* look up the targets that have been removed since last commit */ 2643 hws->funcs.reset_hw_ctx_wrap(dc, context); 2644 2645 /* Skip applying if no targets */ 2646 if (context->stream_count <= 0) 2647 return DC_OK; 2648 2649 /* Apply new context */ 2650 dcb->funcs->set_scratch_critical_state(dcb, true); 2651 2652 /* below is for real asic only */ 2653 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2654 struct pipe_ctx *pipe_ctx_old = 2655 &dc->current_state->res_ctx.pipe_ctx[i]; 2656 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2657 2658 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) 2659 continue; 2660 2661 if (pipe_ctx->stream == pipe_ctx_old->stream) { 2662 if (pipe_ctx_old->clock_source != pipe_ctx->clock_source) 2663 dce_crtc_switch_to_clk_src(dc->hwseq, 2664 pipe_ctx->clock_source, i); 2665 continue; 2666 } 2667 2668 hws->funcs.enable_display_power_gating( 2669 dc, (uint8_t)i, dc->ctx->dc_bios, 2670 PIPE_GATING_CONTROL_DISABLE); 2671 } 2672 2673 if (dc->fbc_compressor) 2674 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 2675 2676 dce110_setup_audio_dto(dc, context); 2677 2678 if (dc->hwseq->funcs.setup_hpo_hw_control && was_hpo_acquired != is_hpo_acquired) { 2679 dc->hwseq->funcs.setup_hpo_hw_control(dc->hwseq, is_hpo_acquired); 2680 } 2681 2682 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2683 struct pipe_ctx *pipe_ctx_old = 2684 &dc->current_state->res_ctx.pipe_ctx[i]; 2685 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2686 2687 if (pipe_ctx->stream == NULL) 2688 continue; 2689 2690 if (pipe_ctx->stream == pipe_ctx_old->stream && 2691 pipe_ctx->stream->link->link_state_valid) { 2692 continue; 2693 } 2694 2695 if (pipe_ctx_old->stream && !pipe_need_reprogram(pipe_ctx_old, pipe_ctx)) 2696 continue; 2697 2698 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) 2699 continue; 2700 2701 status = dce110_apply_single_controller_ctx_to_hw( 2702 pipe_ctx, 2703 context, 2704 dc); 2705 2706 if (DC_OK != status) 2707 return status; 2708 2709 #ifdef CONFIG_DRM_AMD_DC_FP 2710 if (hws->funcs.resync_fifo_dccg_dio) 2711 hws->funcs.resync_fifo_dccg_dio(hws, dc, context, i); 2712 #endif 2713 } 2714 2715 2716 if (dc->debug.enable_otg_frame_sync_pwa && context->stream_count == 1) { 2717 /* only enable this on one OTG*/ 2718 for (i = 0; i < dc->res_pool->pipe_count; i++) { 2719 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 2720 2721 if (pipe_ctx && pipe_ctx->stream != NULL) { 2722 dc_hwss_enable_otg_pwa(dc, pipe_ctx); 2723 break; 2724 } 2725 } 2726 } 2727 if (dc->fbc_compressor) 2728 enable_fbc(dc, dc->current_state); 2729 2730 dcb->funcs->set_scratch_critical_state(dcb, false); 2731 2732 return DC_OK; 2733 } 2734 2735 /******************************************************************************* 2736 * Front End programming 2737 ******************************************************************************/ 2738 static void set_default_colors(struct pipe_ctx *pipe_ctx) 2739 { 2740 struct default_adjustment default_adjust = { 0 }; 2741 2742 default_adjust.force_hw_default = false; 2743 default_adjust.in_color_space = pipe_ctx->plane_state->color_space; 2744 default_adjust.out_color_space = pipe_ctx->stream->output_color_space; 2745 default_adjust.csc_adjust_type = GRAPHICS_CSC_ADJUST_TYPE_SW; 2746 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; 2747 2748 /* display color depth */ 2749 default_adjust.color_depth = 2750 pipe_ctx->stream->timing.display_color_depth; 2751 2752 /* Lb color depth */ 2753 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; 2754 2755 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_default( 2756 pipe_ctx->plane_res.xfm, &default_adjust); 2757 } 2758 2759 2760 /******************************************************************************* 2761 * In order to turn on/off specific surface we will program 2762 * Blender + CRTC 2763 * 2764 * In case that we have two surfaces and they have a different visibility 2765 * we can't turn off the CRTC since it will turn off the entire display 2766 * 2767 * |----------------------------------------------- | 2768 * |bottom pipe|curr pipe | | | 2769 * |Surface |Surface | Blender | CRCT | 2770 * |visibility |visibility | Configuration| | 2771 * |------------------------------------------------| 2772 * | off | off | CURRENT_PIPE | blank | 2773 * | off | on | CURRENT_PIPE | unblank | 2774 * | on | off | OTHER_PIPE | unblank | 2775 * | on | on | BLENDING | unblank | 2776 * -------------------------------------------------| 2777 * 2778 ******************************************************************************/ 2779 static void program_surface_visibility(const struct dc *dc, 2780 struct pipe_ctx *pipe_ctx) 2781 { 2782 enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE; 2783 bool blank_target = false; 2784 2785 if (pipe_ctx->bottom_pipe) { 2786 2787 /* For now we are supporting only two pipes */ 2788 ASSERT(pipe_ctx->bottom_pipe->bottom_pipe == NULL); 2789 2790 if (pipe_ctx->bottom_pipe->plane_state->visible) { 2791 if (pipe_ctx->plane_state->visible) 2792 blender_mode = BLND_MODE_BLENDING; 2793 else 2794 blender_mode = BLND_MODE_OTHER_PIPE; 2795 2796 } else if (!pipe_ctx->plane_state->visible) 2797 blank_target = true; 2798 2799 } else if (!pipe_ctx->plane_state->visible) 2800 blank_target = true; 2801 2802 dce_set_blender_mode(dc->hwseq, pipe_ctx->stream_res.tg->inst, blender_mode); 2803 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, blank_target); 2804 2805 } 2806 2807 static void program_gamut_remap(struct pipe_ctx *pipe_ctx) 2808 { 2809 int i = 0; 2810 struct xfm_grph_csc_adjustment adjust; 2811 memset(&adjust, 0, sizeof(adjust)); 2812 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 2813 2814 2815 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 2816 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 2817 2818 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 2819 adjust.temperature_matrix[i] = 2820 pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 2821 } 2822 2823 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 2824 } 2825 static void update_plane_addr(const struct dc *dc, 2826 struct pipe_ctx *pipe_ctx) 2827 { 2828 (void)dc; 2829 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2830 2831 if (plane_state == NULL) 2832 return; 2833 2834 pipe_ctx->plane_res.mi->funcs->mem_input_program_surface_flip_and_addr( 2835 pipe_ctx->plane_res.mi, 2836 &plane_state->address, 2837 plane_state->flip_immediate); 2838 2839 plane_state->status.requested_address = plane_state->address; 2840 } 2841 2842 static void dce110_update_pending_status(struct pipe_ctx *pipe_ctx) 2843 { 2844 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 2845 2846 if (plane_state == NULL) 2847 return; 2848 2849 plane_state->status.is_flip_pending = 2850 pipe_ctx->plane_res.mi->funcs->mem_input_is_flip_pending( 2851 pipe_ctx->plane_res.mi); 2852 2853 if (plane_state->status.is_flip_pending && !plane_state->visible) 2854 pipe_ctx->plane_res.mi->current_address = pipe_ctx->plane_res.mi->request_address; 2855 2856 plane_state->status.current_address = pipe_ctx->plane_res.mi->current_address; 2857 if (pipe_ctx->plane_res.mi->current_address.type == PLN_ADDR_TYPE_GRPH_STEREO && 2858 pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye) { 2859 plane_state->status.is_right_eye =\ 2860 !pipe_ctx->stream_res.tg->funcs->is_stereo_left_eye(pipe_ctx->stream_res.tg); 2861 } 2862 } 2863 2864 void dce110_power_down(struct dc *dc) 2865 { 2866 power_down_all_hw_blocks(dc); 2867 disable_vga_and_power_gate_all_controllers(dc); 2868 } 2869 2870 static bool wait_for_reset_trigger_to_occur( 2871 struct dc_context *dc_ctx, 2872 struct timing_generator *tg) 2873 { 2874 bool rc = false; 2875 2876 /* To avoid endless loop we wait at most 2877 * frames_to_wait_on_triggered_reset frames for the reset to occur. */ 2878 const uint32_t frames_to_wait_on_triggered_reset = 10; 2879 uint32_t i; 2880 2881 for (i = 0; i < frames_to_wait_on_triggered_reset; i++) { 2882 2883 if (!tg->funcs->is_counter_moving(tg)) { 2884 DC_ERROR("TG counter is not moving!\n"); 2885 break; 2886 } 2887 2888 if (tg->funcs->did_triggered_reset_occur(tg)) { 2889 rc = true; 2890 /* usually occurs at i=1 */ 2891 DC_SYNC_INFO("GSL: reset occurred at wait count: %d\n", 2892 i); 2893 break; 2894 } 2895 2896 /* Wait for one frame. */ 2897 tg->funcs->wait_for_state(tg, CRTC_STATE_VACTIVE); 2898 tg->funcs->wait_for_state(tg, CRTC_STATE_VBLANK); 2899 } 2900 2901 if (false == rc) 2902 DC_ERROR("GSL: Timeout on reset trigger!\n"); 2903 2904 return rc; 2905 } 2906 2907 /* Enable timing synchronization for a group of Timing Generators. */ 2908 static void dce110_enable_timing_synchronization( 2909 struct dc *dc, 2910 struct dc_state *state, 2911 int group_index, 2912 int group_size, 2913 struct pipe_ctx *grouped_pipes[]) 2914 { 2915 (void)state; 2916 (void)group_index; 2917 struct dcp_gsl_params gsl_params = { 0 }; 2918 int i; 2919 DC_LOGGER_INIT(dc->ctx); 2920 2921 DC_SYNC_INFO("GSL: Setting-up...\n"); 2922 2923 /* Designate a single TG in the group as a master. 2924 * Since HW doesn't care which one, we always assign 2925 * the 1st one in the group. */ 2926 gsl_params.gsl_group = 0; 2927 gsl_params.gsl_master = grouped_pipes[0]->stream_res.tg->inst; 2928 2929 for (i = 0; i < group_size; i++) 2930 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2931 grouped_pipes[i]->stream_res.tg, &gsl_params); 2932 2933 /* Reset slave controllers on master VSync */ 2934 DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2935 2936 for (i = 1 /* skip the master */; i < group_size; i++) 2937 grouped_pipes[i]->stream_res.tg->funcs->enable_reset_trigger( 2938 grouped_pipes[i]->stream_res.tg, 2939 gsl_params.gsl_group); 2940 2941 for (i = 1 /* skip the master */; i < group_size; i++) { 2942 DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2943 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2944 grouped_pipes[i]->stream_res.tg->funcs->disable_reset_trigger( 2945 grouped_pipes[i]->stream_res.tg); 2946 } 2947 2948 /* GSL Vblank synchronization is a one time sync mechanism, assumption 2949 * is that the sync'ed displays will not drift out of sync over time*/ 2950 DC_SYNC_INFO("GSL: Restoring register states.\n"); 2951 for (i = 0; i < group_size; i++) 2952 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2953 2954 DC_SYNC_INFO("GSL: Set-up complete.\n"); 2955 } 2956 2957 static void dce110_enable_per_frame_crtc_position_reset( 2958 struct dc *dc, 2959 int group_size, 2960 struct pipe_ctx *grouped_pipes[]) 2961 { 2962 struct dcp_gsl_params gsl_params = { 0 }; 2963 int i; 2964 DC_LOGGER_INIT(dc->ctx); 2965 2966 gsl_params.gsl_group = 0; 2967 gsl_params.gsl_master = 0; 2968 2969 for (i = 0; i < group_size; i++) 2970 grouped_pipes[i]->stream_res.tg->funcs->setup_global_swap_lock( 2971 grouped_pipes[i]->stream_res.tg, &gsl_params); 2972 2973 DC_SYNC_INFO("GSL: enabling trigger-reset\n"); 2974 2975 for (i = 1; i < group_size; i++) 2976 grouped_pipes[i]->stream_res.tg->funcs->enable_crtc_reset( 2977 grouped_pipes[i]->stream_res.tg, 2978 gsl_params.gsl_master, 2979 &grouped_pipes[i]->stream->triggered_crtc_reset); 2980 2981 DC_SYNC_INFO("GSL: waiting for reset to occur.\n"); 2982 for (i = 1; i < group_size; i++) 2983 wait_for_reset_trigger_to_occur(dc_ctx, grouped_pipes[i]->stream_res.tg); 2984 2985 for (i = 0; i < group_size; i++) 2986 grouped_pipes[i]->stream_res.tg->funcs->tear_down_global_swap_lock(grouped_pipes[i]->stream_res.tg); 2987 2988 } 2989 2990 static void dce110_init_pipes(struct dc *dc, struct dc_state *context) 2991 { 2992 (void)context; 2993 (void)dc; 2994 // Do nothing 2995 } 2996 2997 static void dce110_init_hw(struct dc *dc) 2998 { 2999 unsigned int i; 3000 struct dc_bios *bp; 3001 struct transform *xfm; 3002 struct abm *abm; 3003 struct dmcu *dmcu; 3004 struct dce_hwseq *hws = dc->hwseq; 3005 uint32_t backlight = MAX_BACKLIGHT_LEVEL; 3006 uint32_t user_level = MAX_BACKLIGHT_LEVEL; 3007 3008 bp = dc->ctx->dc_bios; 3009 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3010 xfm = dc->res_pool->transforms[i]; 3011 xfm->funcs->transform_reset(xfm); 3012 3013 hws->funcs.enable_display_power_gating( 3014 dc, (uint8_t)i, bp, 3015 PIPE_GATING_CONTROL_INIT); 3016 hws->funcs.enable_display_power_gating( 3017 dc, (uint8_t)i, bp, 3018 PIPE_GATING_CONTROL_DISABLE); 3019 hws->funcs.enable_display_pipe_clock_gating( 3020 dc->ctx, 3021 true); 3022 } 3023 3024 dce_clock_gating_power_up(dc->hwseq, false); 3025 /***************************************/ 3026 3027 for (i = 0; i < dc->link_count; i++) { 3028 /****************************************/ 3029 /* Power up AND update implementation according to the 3030 * required signal (which may be different from the 3031 * default signal on connector). */ 3032 struct dc_link *link = dc->links[i]; 3033 3034 link->link_enc->funcs->hw_init(link->link_enc); 3035 } 3036 3037 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3038 struct timing_generator *tg = dc->res_pool->timing_generators[i]; 3039 3040 tg->funcs->disable_vga(tg); 3041 3042 /* Blank controller using driver code instead of 3043 * command table. */ 3044 tg->funcs->set_blank(tg, true); 3045 hwss_wait_for_blank_complete(tg); 3046 } 3047 3048 for (i = 0; i < dc->res_pool->audio_count; i++) { 3049 struct audio *audio = dc->res_pool->audios[i]; 3050 audio->funcs->hw_init(audio); 3051 } 3052 3053 for (i = 0; i < dc->link_count; i++) { 3054 struct dc_link *link = dc->links[i]; 3055 3056 if (link->panel_cntl) { 3057 backlight = link->panel_cntl->funcs->hw_init(link->panel_cntl); 3058 user_level = link->panel_cntl->stored_backlight_registers.USER_LEVEL; 3059 } 3060 } 3061 3062 abm = dc->res_pool->abm; 3063 if (abm != NULL) 3064 abm->funcs->abm_init(abm, backlight, user_level); 3065 3066 dmcu = dc->res_pool->dmcu; 3067 if (dmcu != NULL && abm != NULL) 3068 abm->dmcu_is_running = dmcu->funcs->is_dmcu_initialized(dmcu); 3069 3070 if (dc->fbc_compressor) 3071 dc->fbc_compressor->funcs->power_up_fbc(dc->fbc_compressor); 3072 3073 } 3074 3075 3076 void dce110_prepare_bandwidth( 3077 struct dc *dc, 3078 struct dc_state *context) 3079 { 3080 struct clk_mgr *dccg = dc->clk_mgr; 3081 3082 dce110_set_safe_displaymarks(&context->res_ctx, dc->res_pool); 3083 if (dccg) 3084 dccg->funcs->update_clocks( 3085 dccg, 3086 context, 3087 false); 3088 } 3089 3090 void dce110_optimize_bandwidth( 3091 struct dc *dc, 3092 struct dc_state *context) 3093 { 3094 struct clk_mgr *dccg = dc->clk_mgr; 3095 3096 dce110_set_displaymarks(dc, context); 3097 3098 if (dccg) 3099 dccg->funcs->update_clocks( 3100 dccg, 3101 context, 3102 true); 3103 } 3104 3105 static void dce110_program_front_end_for_pipe( 3106 struct dc *dc, struct pipe_ctx *pipe_ctx) 3107 { 3108 struct mem_input *mi = pipe_ctx->plane_res.mi; 3109 struct dc_plane_state *plane_state = pipe_ctx->plane_state; 3110 struct xfm_grph_csc_adjustment adjust; 3111 struct out_csc_color_matrix tbl_entry; 3112 unsigned int i; 3113 struct dce_hwseq *hws = dc->hwseq; 3114 3115 memset(&tbl_entry, 0, sizeof(tbl_entry)); 3116 3117 memset(&adjust, 0, sizeof(adjust)); 3118 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_BYPASS; 3119 3120 dce_enable_fe_clock(dc->hwseq, mi->inst, true); 3121 3122 set_default_colors(pipe_ctx); 3123 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment 3124 == true) { 3125 tbl_entry.color_space = 3126 pipe_ctx->stream->output_color_space; 3127 3128 for (i = 0; i < 12; i++) 3129 tbl_entry.regval[i] = 3130 pipe_ctx->stream->csc_color_matrix.matrix[i]; 3131 3132 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment 3133 (pipe_ctx->plane_res.xfm, &tbl_entry); 3134 } 3135 3136 if (pipe_ctx->stream->gamut_remap_matrix.enable_remap == true) { 3137 adjust.gamut_adjust_type = GRAPHICS_GAMUT_ADJUST_TYPE_SW; 3138 3139 for (i = 0; i < CSC_TEMPERATURE_MATRIX_SIZE; i++) 3140 adjust.temperature_matrix[i] = 3141 pipe_ctx->stream->gamut_remap_matrix.matrix[i]; 3142 } 3143 3144 pipe_ctx->plane_res.xfm->funcs->transform_set_gamut_remap(pipe_ctx->plane_res.xfm, &adjust); 3145 3146 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != NULL; 3147 3148 program_scaler(dc, pipe_ctx); 3149 3150 mi->funcs->mem_input_program_surface_config( 3151 mi, 3152 plane_state->format, 3153 &plane_state->tiling_info, 3154 &plane_state->plane_size, 3155 plane_state->rotation, 3156 NULL, 3157 false); 3158 if (mi->funcs->set_blank) 3159 mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible); 3160 3161 if (dc->config.gpu_vm_support) 3162 mi->funcs->mem_input_program_pte_vm( 3163 pipe_ctx->plane_res.mi, 3164 plane_state->format, 3165 &plane_state->tiling_info, 3166 plane_state->rotation); 3167 3168 /* Moved programming gamma from dc to hwss */ 3169 if (pipe_ctx->plane_state->update_flags.bits.full_update || 3170 pipe_ctx->plane_state->update_flags.bits.in_transfer_func_change || 3171 pipe_ctx->plane_state->update_flags.bits.gamma_change) 3172 hws->funcs.set_input_transfer_func(dc, pipe_ctx, pipe_ctx->plane_state); 3173 3174 if (pipe_ctx->plane_state->update_flags.bits.full_update) 3175 hws->funcs.set_output_transfer_func(dc, pipe_ctx, pipe_ctx->stream); 3176 3177 DC_LOG_SURFACE( 3178 "Pipe:%d %p: addr hi:0x%x, " 3179 "addr low:0x%x, " 3180 "src: %d, %d, %d," 3181 " %d; dst: %d, %d, %d, %d;" 3182 "clip: %d, %d, %d, %d\n", 3183 pipe_ctx->pipe_idx, 3184 (void *) pipe_ctx->plane_state, 3185 pipe_ctx->plane_state->address.grph.addr.high_part, 3186 pipe_ctx->plane_state->address.grph.addr.low_part, 3187 pipe_ctx->plane_state->src_rect.x, 3188 pipe_ctx->plane_state->src_rect.y, 3189 pipe_ctx->plane_state->src_rect.width, 3190 pipe_ctx->plane_state->src_rect.height, 3191 pipe_ctx->plane_state->dst_rect.x, 3192 pipe_ctx->plane_state->dst_rect.y, 3193 pipe_ctx->plane_state->dst_rect.width, 3194 pipe_ctx->plane_state->dst_rect.height, 3195 pipe_ctx->plane_state->clip_rect.x, 3196 pipe_ctx->plane_state->clip_rect.y, 3197 pipe_ctx->plane_state->clip_rect.width, 3198 pipe_ctx->plane_state->clip_rect.height); 3199 3200 DC_LOG_SURFACE( 3201 "Pipe %d: width, height, x, y\n" 3202 "viewport:%d, %d, %d, %d\n" 3203 "recout: %d, %d, %d, %d\n", 3204 pipe_ctx->pipe_idx, 3205 pipe_ctx->plane_res.scl_data.viewport.width, 3206 pipe_ctx->plane_res.scl_data.viewport.height, 3207 pipe_ctx->plane_res.scl_data.viewport.x, 3208 pipe_ctx->plane_res.scl_data.viewport.y, 3209 pipe_ctx->plane_res.scl_data.recout.width, 3210 pipe_ctx->plane_res.scl_data.recout.height, 3211 pipe_ctx->plane_res.scl_data.recout.x, 3212 pipe_ctx->plane_res.scl_data.recout.y); 3213 } 3214 3215 static void dce110_apply_ctx_for_surface( 3216 struct dc *dc, 3217 const struct dc_stream_state *stream, 3218 int num_planes, 3219 struct dc_state *context) 3220 { 3221 unsigned int i; 3222 3223 if (num_planes == 0) 3224 return; 3225 3226 if (dc->fbc_compressor) 3227 dc->fbc_compressor->funcs->disable_fbc(dc->fbc_compressor); 3228 3229 for (i = 0; i < dc->res_pool->pipe_count; i++) { 3230 struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[i]; 3231 3232 if (pipe_ctx->stream != stream) 3233 continue; 3234 3235 /* Need to allocate mem before program front end for Fiji */ 3236 pipe_ctx->plane_res.mi->funcs->allocate_mem_input( 3237 pipe_ctx->plane_res.mi, 3238 pipe_ctx->stream->timing.h_total, 3239 pipe_ctx->stream->timing.v_total, 3240 pipe_ctx->stream->timing.pix_clk_100hz / 10, 3241 context->stream_count); 3242 3243 dce110_program_front_end_for_pipe(dc, pipe_ctx); 3244 3245 dc->hwss.update_plane_addr(dc, pipe_ctx); 3246 3247 program_surface_visibility(dc, pipe_ctx); 3248 3249 } 3250 3251 if (dc->fbc_compressor) 3252 enable_fbc(dc, context); 3253 } 3254 3255 static void dce110_post_unlock_program_front_end( 3256 struct dc *dc, 3257 struct dc_state *context) 3258 { 3259 (void)dc; 3260 (void)context; 3261 } 3262 3263 static void dce110_power_down_fe(struct dc *dc, struct dc_state *state, struct pipe_ctx *pipe_ctx) 3264 { 3265 (void)state; 3266 struct dce_hwseq *hws = dc->hwseq; 3267 int fe_idx = pipe_ctx->plane_res.mi ? 3268 pipe_ctx->plane_res.mi->inst : pipe_ctx->pipe_idx; 3269 3270 /* Do not power down fe when stream is active on dce*/ 3271 if (dc->current_state->res_ctx.pipe_ctx[fe_idx].stream) 3272 return; 3273 3274 hws->funcs.enable_display_power_gating( 3275 dc, (uint8_t)fe_idx, dc->ctx->dc_bios, PIPE_GATING_CONTROL_ENABLE); 3276 3277 dc->res_pool->transforms[fe_idx]->funcs->transform_reset( 3278 dc->res_pool->transforms[fe_idx]); 3279 } 3280 3281 static void dce110_wait_for_mpcc_disconnect( 3282 struct dc *dc, 3283 struct resource_pool *res_pool, 3284 struct pipe_ctx *pipe_ctx) 3285 { 3286 (void)dc; 3287 (void)res_pool; 3288 (void)pipe_ctx; 3289 /* do nothing*/ 3290 } 3291 3292 static void program_output_csc(struct dc *dc, 3293 struct pipe_ctx *pipe_ctx, 3294 enum dc_color_space colorspace, 3295 uint16_t *matrix, 3296 int opp_id) 3297 { 3298 (void)dc; 3299 (void)colorspace; 3300 (void)matrix; 3301 (void)opp_id; 3302 int i; 3303 struct out_csc_color_matrix tbl_entry; 3304 3305 if (pipe_ctx->stream->csc_color_matrix.enable_adjustment == true) { 3306 enum dc_color_space color_space = pipe_ctx->stream->output_color_space; 3307 3308 for (i = 0; i < 12; i++) 3309 tbl_entry.regval[i] = pipe_ctx->stream->csc_color_matrix.matrix[i]; 3310 3311 tbl_entry.color_space = color_space; 3312 3313 pipe_ctx->plane_res.xfm->funcs->opp_set_csc_adjustment( 3314 pipe_ctx->plane_res.xfm, &tbl_entry); 3315 } 3316 } 3317 3318 static void dce110_set_cursor_position(struct pipe_ctx *pipe_ctx) 3319 { 3320 struct dc_cursor_position pos_cpy = pipe_ctx->stream->cursor_position; 3321 struct input_pixel_processor *ipp = pipe_ctx->plane_res.ipp; 3322 struct mem_input *mi = pipe_ctx->plane_res.mi; 3323 struct dc_cursor_mi_param param = { 3324 .pixel_clk_khz = pipe_ctx->stream->timing.pix_clk_100hz / 10, 3325 .ref_clk_khz = pipe_ctx->stream->ctx->dc->res_pool->ref_clocks.xtalin_clock_inKhz, 3326 .viewport = pipe_ctx->plane_res.scl_data.viewport, 3327 .h_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.horz, 3328 .v_scale_ratio = pipe_ctx->plane_res.scl_data.ratios.vert, 3329 .rotation = pipe_ctx->plane_state->rotation, 3330 .mirror = pipe_ctx->plane_state->horizontal_mirror 3331 }; 3332 3333 /** 3334 * If the cursor's source viewport is clipped then we need to 3335 * translate the cursor to appear in the correct position on 3336 * the screen. 3337 * 3338 * This translation isn't affected by scaling so it needs to be 3339 * done *after* we adjust the position for the scale factor. 3340 * 3341 * This is only done by opt-in for now since there are still 3342 * some usecases like tiled display that might enable the 3343 * cursor on both streams while expecting dc to clip it. 3344 */ 3345 if (pos_cpy.translate_by_source) { 3346 pos_cpy.x += pipe_ctx->plane_state->src_rect.x; 3347 pos_cpy.y += pipe_ctx->plane_state->src_rect.y; 3348 } 3349 3350 if (pipe_ctx->plane_state->address.type 3351 == PLN_ADDR_TYPE_VIDEO_PROGRESSIVE) 3352 pos_cpy.enable = false; 3353 3354 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) 3355 pos_cpy.enable = false; 3356 3357 if (ipp->funcs->ipp_cursor_set_position) 3358 ipp->funcs->ipp_cursor_set_position(ipp, &pos_cpy, ¶m); 3359 if (mi->funcs->set_cursor_position) 3360 mi->funcs->set_cursor_position(mi, &pos_cpy, ¶m); 3361 } 3362 3363 static void dce110_set_cursor_attribute(struct pipe_ctx *pipe_ctx) 3364 { 3365 struct dc_cursor_attributes *attributes = &pipe_ctx->stream->cursor_attributes; 3366 3367 if (pipe_ctx->plane_res.ipp && 3368 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes) 3369 pipe_ctx->plane_res.ipp->funcs->ipp_cursor_set_attributes( 3370 pipe_ctx->plane_res.ipp, attributes); 3371 3372 if (pipe_ctx->plane_res.mi && 3373 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes) 3374 pipe_ctx->plane_res.mi->funcs->set_cursor_attributes( 3375 pipe_ctx->plane_res.mi, attributes); 3376 3377 if (pipe_ctx->plane_res.xfm && 3378 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes) 3379 pipe_ctx->plane_res.xfm->funcs->set_cursor_attributes( 3380 pipe_ctx->plane_res.xfm, attributes); 3381 } 3382 3383 bool dce110_set_backlight_level(struct pipe_ctx *pipe_ctx, 3384 struct set_backlight_level_params *backlight_level_params) 3385 { 3386 uint32_t backlight_pwm_u16_16 = backlight_level_params->backlight_pwm_u16_16; 3387 uint32_t frame_ramp = backlight_level_params->frame_ramp; 3388 struct dc_link *link = pipe_ctx->stream->link; 3389 struct dc *dc = link->ctx->dc; 3390 struct abm *abm = pipe_ctx->stream_res.abm; 3391 struct panel_cntl *panel_cntl = link->panel_cntl; 3392 struct dmcu *dmcu = dc->res_pool->dmcu; 3393 bool fw_set_brightness = true; 3394 /* DMCU -1 for all controller id values, 3395 * therefore +1 here 3396 */ 3397 uint32_t controller_id = pipe_ctx->stream_res.tg->inst + 1; 3398 3399 if (abm == NULL || panel_cntl == NULL || (abm->funcs->set_backlight_level_pwm == NULL)) 3400 return false; 3401 3402 if (dmcu) 3403 fw_set_brightness = dmcu->funcs->is_dmcu_initialized(dmcu); 3404 3405 if (!fw_set_brightness && panel_cntl->funcs->driver_set_backlight) 3406 panel_cntl->funcs->driver_set_backlight(panel_cntl, backlight_pwm_u16_16); 3407 else 3408 abm->funcs->set_backlight_level_pwm( 3409 abm, 3410 backlight_pwm_u16_16, 3411 frame_ramp, 3412 controller_id, 3413 link->panel_cntl->inst); 3414 3415 return true; 3416 } 3417 3418 void dce110_set_abm_immediate_disable(struct pipe_ctx *pipe_ctx) 3419 { 3420 struct abm *abm = pipe_ctx->stream_res.abm; 3421 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 3422 3423 if (abm) 3424 abm->funcs->set_abm_immediate_disable(abm, 3425 pipe_ctx->stream->link->panel_cntl->inst); 3426 3427 if (panel_cntl) 3428 panel_cntl->funcs->store_backlight_level(panel_cntl); 3429 } 3430 3431 void dce110_set_pipe(struct pipe_ctx *pipe_ctx) 3432 { 3433 struct abm *abm = pipe_ctx->stream_res.abm; 3434 struct panel_cntl *panel_cntl = pipe_ctx->stream->link->panel_cntl; 3435 uint32_t otg_inst = pipe_ctx->stream_res.tg->inst + 1; 3436 3437 if (abm && panel_cntl) 3438 abm->funcs->set_pipe(abm, otg_inst, panel_cntl->inst); 3439 } 3440 3441 void dce110_enable_lvds_link_output(struct dc_link *link, 3442 const struct link_resource *link_res, 3443 enum clock_source_id clock_source, 3444 uint32_t pixel_clock) 3445 { 3446 (void)link_res; 3447 link->link_enc->funcs->enable_lvds_output( 3448 link->link_enc, 3449 clock_source, 3450 pixel_clock); 3451 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 3452 } 3453 3454 void dce110_enable_tmds_link_output(struct dc_link *link, 3455 const struct link_resource *link_res, 3456 enum signal_type signal, 3457 enum clock_source_id clock_source, 3458 enum dc_color_depth color_depth, 3459 uint32_t pixel_clock) 3460 { 3461 (void)link_res; 3462 link->link_enc->funcs->enable_tmds_output( 3463 link->link_enc, 3464 clock_source, 3465 color_depth, 3466 signal, 3467 pixel_clock); 3468 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 3469 } 3470 3471 static void dce110_enable_analog_link_output( 3472 struct dc_link *link, 3473 uint32_t pix_clk_100hz) 3474 { 3475 link->link_enc->funcs->enable_analog_output( 3476 link->link_enc, 3477 pix_clk_100hz); 3478 } 3479 3480 void dce110_enable_dp_link_output( 3481 struct dc_link *link, 3482 const struct link_resource *link_res, 3483 enum signal_type signal, 3484 enum clock_source_id clock_source, 3485 const struct dc_link_settings *link_settings) 3486 { 3487 struct dc *dc = link->ctx->dc; 3488 struct dmcu *dmcu = dc->res_pool->dmcu; 3489 struct pipe_ctx *pipes = 3490 link->dc->current_state->res_ctx.pipe_ctx; 3491 struct clock_source *dp_cs = 3492 link->dc->res_pool->dp_clock_source; 3493 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 3494 unsigned int i; 3495 3496 /* 3497 * Add the logic to extract BOTH power up and power down sequences 3498 * from enable/disable link output and only call edp panel control 3499 * in enable_link_dp and disable_link_dp once. 3500 */ 3501 if (link->connector_signal == SIGNAL_TYPE_EDP) { 3502 link->dc->hwss.edp_wait_for_hpd_ready(link, true); 3503 } 3504 3505 /* If the current pixel clock source is not DTO(happens after 3506 * switching from HDMI passive dongle to DP on the same connector), 3507 * switch the pixel clock source to DTO. 3508 */ 3509 3510 for (i = 0; i < MAX_PIPES; i++) { 3511 if (pipes[i].stream != NULL && 3512 pipes[i].stream->link == link) { 3513 if (pipes[i].clock_source != NULL && 3514 pipes[i].clock_source->id != CLOCK_SOURCE_ID_DP_DTO) { 3515 pipes[i].clock_source = dp_cs; 3516 pipes[i].stream_res.pix_clk_params.requested_pix_clk_100hz = 3517 pipes[i].stream->timing.pix_clk_100hz; 3518 pipes[i].clock_source->funcs->program_pix_clk( 3519 pipes[i].clock_source, 3520 &pipes[i].stream_res.pix_clk_params, 3521 dc->link_srv->dp_get_encoding_format(link_settings), 3522 &pipes[i].pll_settings); 3523 } 3524 } 3525 } 3526 3527 if (link->ext_enc_id.id) { 3528 dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_INIT, link, NULL); 3529 dce110_external_encoder_control(EXTERNAL_ENCODER_CONTROL_SETUP, link, NULL); 3530 } 3531 3532 if (dc->link_srv->dp_get_encoding_format(link_settings) == DP_8b_10b_ENCODING) { 3533 if (dc->clk_mgr->funcs->notify_link_rate_change) 3534 dc->clk_mgr->funcs->notify_link_rate_change(dc->clk_mgr, link); 3535 } 3536 3537 if (dmcu != NULL && dmcu->funcs->lock_phy) 3538 dmcu->funcs->lock_phy(dmcu); 3539 3540 if (link_hwss->ext.enable_dp_link_output) 3541 link_hwss->ext.enable_dp_link_output(link, link_res, signal, 3542 clock_source, link_settings); 3543 3544 link->phy_state.symclk_state = SYMCLK_ON_TX_ON; 3545 3546 if (dmcu != NULL && dmcu->funcs->unlock_phy) 3547 dmcu->funcs->unlock_phy(dmcu); 3548 3549 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_ENABLE_LINK_PHY); 3550 } 3551 3552 void dce110_disable_link_output(struct dc_link *link, 3553 const struct link_resource *link_res, 3554 enum signal_type signal) 3555 { 3556 struct dc *dc = link->ctx->dc; 3557 const struct link_hwss *link_hwss = get_link_hwss(link, link_res); 3558 struct dmcu *dmcu = dc->res_pool->dmcu; 3559 3560 if (signal == SIGNAL_TYPE_EDP && 3561 link->dc->hwss.edp_backlight_control && 3562 !link->skip_implict_edp_power_control) 3563 link->dc->hwss.edp_backlight_control(link, false); 3564 else if (dmcu != NULL && dmcu->funcs->lock_phy) 3565 dmcu->funcs->lock_phy(dmcu); 3566 3567 link_hwss->disable_link_output(link, link_res, signal); 3568 link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF; 3569 /* 3570 * Add the logic to extract BOTH power up and power down sequences 3571 * from enable/disable link output and only call edp panel control 3572 * in enable_link_dp and disable_link_dp once. 3573 */ 3574 if (dmcu != NULL && dmcu->funcs->unlock_phy) 3575 dmcu->funcs->unlock_phy(dmcu); 3576 dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY); 3577 } 3578 3579 static const struct hw_sequencer_funcs dce110_funcs = { 3580 .program_gamut_remap = program_gamut_remap, 3581 .program_output_csc = program_output_csc, 3582 .init_hw = dce110_init_hw, 3583 .apply_ctx_to_hw = dce110_apply_ctx_to_hw, 3584 .apply_ctx_for_surface = dce110_apply_ctx_for_surface, 3585 .post_unlock_program_front_end = dce110_post_unlock_program_front_end, 3586 .update_plane_addr = update_plane_addr, 3587 .update_pending_status = dce110_update_pending_status, 3588 .clear_surface_dcc_and_tiling = dce100_reset_surface_dcc_and_tiling, 3589 .enable_accelerated_mode = dce110_enable_accelerated_mode, 3590 .enable_timing_synchronization = dce110_enable_timing_synchronization, 3591 .enable_per_frame_crtc_position_reset = dce110_enable_per_frame_crtc_position_reset, 3592 .update_info_frame = dce110_update_info_frame, 3593 .enable_stream = dce110_enable_stream, 3594 .disable_stream = dce110_disable_stream, 3595 .unblank_stream = dce110_unblank_stream, 3596 .blank_stream = dce110_blank_stream, 3597 .enable_audio_stream = dce110_enable_audio_stream, 3598 .disable_audio_stream = dce110_disable_audio_stream, 3599 .disable_plane = dce110_power_down_fe, 3600 .pipe_control_lock = dce_pipe_control_lock, 3601 .interdependent_update_lock = NULL, 3602 .cursor_lock = dce_pipe_control_lock, 3603 .prepare_bandwidth = dce110_prepare_bandwidth, 3604 .optimize_bandwidth = dce110_optimize_bandwidth, 3605 .set_drr = set_drr, 3606 .get_position = get_position, 3607 .set_static_screen_control = set_static_screen_control, 3608 .setup_stereo = NULL, 3609 .set_avmute = dce110_set_avmute, 3610 .wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect, 3611 .edp_backlight_control = dce110_edp_backlight_control, 3612 .edp_power_control = dce110_edp_power_control, 3613 .edp_wait_for_hpd_ready = dce110_edp_wait_for_hpd_ready, 3614 .set_cursor_position = dce110_set_cursor_position, 3615 .set_cursor_attribute = dce110_set_cursor_attribute, 3616 .set_backlight_level = dce110_set_backlight_level, 3617 .set_abm_immediate_disable = dce110_set_abm_immediate_disable, 3618 .set_pipe = dce110_set_pipe, 3619 .enable_lvds_link_output = dce110_enable_lvds_link_output, 3620 .enable_tmds_link_output = dce110_enable_tmds_link_output, 3621 .enable_dp_link_output = dce110_enable_dp_link_output, 3622 .enable_analog_link_output = dce110_enable_analog_link_output, 3623 .disable_link_output = dce110_disable_link_output, 3624 .dac_load_detect = dce110_dac_load_detect, 3625 .prepare_ddc = dce110_prepare_ddc, 3626 }; 3627 3628 static const struct hwseq_private_funcs dce110_private_funcs = { 3629 .init_pipes = dce110_init_pipes, 3630 .set_input_transfer_func = dce110_set_input_transfer_func, 3631 .set_output_transfer_func = dce110_set_output_transfer_func, 3632 .power_down = dce110_power_down, 3633 .enable_display_pipe_clock_gating = enable_display_pipe_clock_gating, 3634 .enable_display_power_gating = dce110_enable_display_power_gating, 3635 .reset_hw_ctx_wrap = dce110_reset_hw_ctx_wrap, 3636 .enable_stream_timing = dce110_enable_stream_timing, 3637 .disable_stream_gating = NULL, 3638 .enable_stream_gating = NULL, 3639 .edp_backlight_control = dce110_edp_backlight_control, 3640 }; 3641 3642 void dce110_hw_sequencer_construct(struct dc *dc) 3643 { 3644 dc->hwss = dce110_funcs; 3645 dc->hwseq->funcs = dce110_private_funcs; 3646 } 3647 3648