1 // SPDX-License-Identifier: BSD-3-Clause-Clear
2
3 #include <linux/etherdevice.h>
4 #include <linux/timekeeping.h>
5 #include "mt7603.h"
6 #include "mac.h"
7 #include "../trace.h"
8
9 #define MT_PSE_PAGE_SIZE 128
10
11 static u32
mt7603_ac_queue_mask0(u32 mask)12 mt7603_ac_queue_mask0(u32 mask)
13 {
14 u32 ret = 0;
15
16 ret |= GENMASK(3, 0) * !!(mask & BIT(0));
17 ret |= GENMASK(8, 5) * !!(mask & BIT(1));
18 ret |= GENMASK(13, 10) * !!(mask & BIT(2));
19 ret |= GENMASK(19, 16) * !!(mask & BIT(3));
20 return ret;
21 }
22
23 static void
mt76_stop_tx_ac(struct mt7603_dev * dev,u32 mask)24 mt76_stop_tx_ac(struct mt7603_dev *dev, u32 mask)
25 {
26 mt76_set(dev, MT_WF_ARB_TX_STOP_0, mt7603_ac_queue_mask0(mask));
27 }
28
29 static void
mt76_start_tx_ac(struct mt7603_dev * dev,u32 mask)30 mt76_start_tx_ac(struct mt7603_dev *dev, u32 mask)
31 {
32 mt76_set(dev, MT_WF_ARB_TX_START_0, mt7603_ac_queue_mask0(mask));
33 }
34
mt7603_mac_reset_counters(struct mt7603_dev * dev)35 void mt7603_mac_reset_counters(struct mt7603_dev *dev)
36 {
37 int i;
38
39 for (i = 0; i < 2; i++)
40 mt76_rr(dev, MT_TX_AGG_CNT(i));
41
42 memset(dev->mphy.aggr_stats, 0, sizeof(dev->mphy.aggr_stats));
43 }
44
mt7603_mac_set_timing(struct mt7603_dev * dev)45 void mt7603_mac_set_timing(struct mt7603_dev *dev)
46 {
47 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) |
48 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48);
49 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) |
50 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 24);
51 int offset = 3 * dev->coverage_class;
52 u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) |
53 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset);
54 bool is_5ghz = dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ;
55 int sifs;
56 u32 val;
57
58 if (is_5ghz)
59 sifs = 16;
60 else
61 sifs = 10;
62
63 mt76_set(dev, MT_ARB_SCR,
64 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
65 udelay(1);
66
67 mt76_wr(dev, MT_TIMEOUT_CCK, cck + reg_offset);
68 mt76_wr(dev, MT_TIMEOUT_OFDM, ofdm + reg_offset);
69 mt76_wr(dev, MT_IFS,
70 FIELD_PREP(MT_IFS_EIFS, 360) |
71 FIELD_PREP(MT_IFS_RIFS, 2) |
72 FIELD_PREP(MT_IFS_SIFS, sifs) |
73 FIELD_PREP(MT_IFS_SLOT, dev->slottime));
74
75 if (dev->slottime < 20 || is_5ghz)
76 val = MT7603_CFEND_RATE_DEFAULT;
77 else
78 val = MT7603_CFEND_RATE_11B;
79
80 mt76_rmw_field(dev, MT_AGG_CONTROL, MT_AGG_CONTROL_CFEND_RATE, val);
81
82 mt76_clear(dev, MT_ARB_SCR,
83 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
84 }
85
86 static void
mt7603_wtbl_update(struct mt7603_dev * dev,int idx,u32 mask)87 mt7603_wtbl_update(struct mt7603_dev *dev, int idx, u32 mask)
88 {
89 mt76_rmw(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_WLAN_IDX,
90 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, idx) | mask);
91
92 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
93 }
94
95 static u32
mt7603_wtbl1_addr(int idx)96 mt7603_wtbl1_addr(int idx)
97 {
98 return MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
99 }
100
101 static u32
mt7603_wtbl2_addr(int idx)102 mt7603_wtbl2_addr(int idx)
103 {
104 /* Mapped to WTBL2 */
105 return MT_PCIE_REMAP_BASE_1 + idx * MT_WTBL2_SIZE;
106 }
107
108 static u32
mt7603_wtbl3_addr(int idx)109 mt7603_wtbl3_addr(int idx)
110 {
111 u32 base = mt7603_wtbl2_addr(MT7603_WTBL_SIZE);
112
113 return base + idx * MT_WTBL3_SIZE;
114 }
115
116 static u32
mt7603_wtbl4_addr(int idx)117 mt7603_wtbl4_addr(int idx)
118 {
119 u32 base = mt7603_wtbl3_addr(MT7603_WTBL_SIZE);
120
121 return base + idx * MT_WTBL4_SIZE;
122 }
123
mt7603_wtbl_init(struct mt7603_dev * dev,int idx,int vif,const u8 * mac_addr)124 void mt7603_wtbl_init(struct mt7603_dev *dev, int idx, int vif,
125 const u8 *mac_addr)
126 {
127 const void *_mac = mac_addr;
128 u32 addr = mt7603_wtbl1_addr(idx);
129 u32 w0 = 0, w1 = 0;
130 int i;
131
132 if (_mac) {
133 w0 = FIELD_PREP(MT_WTBL1_W0_ADDR_HI,
134 get_unaligned_le16(_mac + 4));
135 w1 = FIELD_PREP(MT_WTBL1_W1_ADDR_LO,
136 get_unaligned_le32(_mac));
137 }
138
139 if (vif < 0)
140 vif = 0;
141 else
142 w0 |= MT_WTBL1_W0_RX_CHECK_A1;
143 w0 |= FIELD_PREP(MT_WTBL1_W0_MUAR_IDX, vif);
144
145 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
146
147 mt76_set(dev, addr + 0 * 4, w0);
148 mt76_set(dev, addr + 1 * 4, w1);
149 mt76_set(dev, addr + 2 * 4, MT_WTBL1_W2_ADMISSION_CONTROL);
150
151 mt76_stop_tx_ac(dev, GENMASK(3, 0));
152 addr = mt7603_wtbl2_addr(idx);
153 for (i = 0; i < MT_WTBL2_SIZE; i += 4)
154 mt76_wr(dev, addr + i, 0);
155 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2);
156 mt76_start_tx_ac(dev, GENMASK(3, 0));
157
158 addr = mt7603_wtbl3_addr(idx);
159 for (i = 0; i < MT_WTBL3_SIZE; i += 4)
160 mt76_wr(dev, addr + i, 0);
161
162 addr = mt7603_wtbl4_addr(idx);
163 for (i = 0; i < MT_WTBL4_SIZE; i += 4)
164 mt76_wr(dev, addr + i, 0);
165
166 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
167 }
168
169 static void
mt7603_wtbl_set_skip_tx(struct mt7603_dev * dev,int idx,bool enabled)170 mt7603_wtbl_set_skip_tx(struct mt7603_dev *dev, int idx, bool enabled)
171 {
172 u32 addr = mt7603_wtbl1_addr(idx);
173 u32 val = mt76_rr(dev, addr + 3 * 4);
174
175 val &= ~MT_WTBL1_W3_SKIP_TX;
176 val |= enabled * MT_WTBL1_W3_SKIP_TX;
177
178 mt76_wr(dev, addr + 3 * 4, val);
179 }
180
mt7603_filter_tx(struct mt7603_dev * dev,int mac_idx,int idx,bool abort)181 void mt7603_filter_tx(struct mt7603_dev *dev, int mac_idx, int idx, bool abort)
182 {
183 u32 flush_mask;
184 int i, port, queue;
185
186 if (abort) {
187 port = 3; /* PSE */
188 queue = 8; /* free queue */
189 } else {
190 port = 0; /* HIF */
191 queue = 1; /* MCU queue */
192 }
193
194 mt7603_wtbl_set_skip_tx(dev, idx, true);
195
196 mt76_wr(dev, MT_TX_ABORT, MT_TX_ABORT_EN |
197 FIELD_PREP(MT_TX_ABORT_WCID, idx));
198
199 flush_mask = MT_WF_ARB_TX_FLUSH_AC0 |
200 MT_WF_ARB_TX_FLUSH_AC1 |
201 MT_WF_ARB_TX_FLUSH_AC2 |
202 MT_WF_ARB_TX_FLUSH_AC3;
203 flush_mask <<= mac_idx;
204
205 mt76_wr(dev, MT_WF_ARB_TX_FLUSH_0, flush_mask);
206 mt76_poll(dev, MT_WF_ARB_TX_FLUSH_0, flush_mask, 0, 20000);
207 mt76_wr(dev, MT_WF_ARB_TX_START_0, flush_mask);
208
209 mt76_wr(dev, MT_TX_ABORT, 0);
210
211 for (i = 0; i < 4; i++) {
212 mt76_wr(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY |
213 FIELD_PREP(MT_DMA_FQCR0_TARGET_WCID, idx) |
214 FIELD_PREP(MT_DMA_FQCR0_TARGET_QID, i) |
215 FIELD_PREP(MT_DMA_FQCR0_DEST_PORT_ID, port) |
216 FIELD_PREP(MT_DMA_FQCR0_DEST_QUEUE_ID, queue));
217
218 mt76_poll(dev, MT_DMA_FQCR0, MT_DMA_FQCR0_BUSY, 0, 5000);
219 }
220
221 WARN_ON_ONCE(mt76_rr(dev, MT_DMA_FQCR0) & MT_DMA_FQCR0_BUSY);
222
223 mt7603_wtbl_set_skip_tx(dev, idx, false);
224 }
225
mt7603_wtbl_set_smps(struct mt7603_dev * dev,struct mt7603_sta * sta,bool enabled)226 void mt7603_wtbl_set_smps(struct mt7603_dev *dev, struct mt7603_sta *sta,
227 bool enabled)
228 {
229 u32 addr = mt7603_wtbl1_addr(sta->wcid.idx);
230
231 if (sta->smps == enabled)
232 return;
233
234 mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_SMPS, enabled);
235 sta->smps = enabled;
236 }
237
238 static void
__mt7603_wtbl_set_ps(struct mt7603_dev * dev,struct mt7603_sta * sta,bool enabled,bool filter)239 __mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta,
240 bool enabled, bool filter)
241 {
242 int idx = sta->wcid.idx;
243 u32 addr;
244
245 lockdep_assert_held(&dev->ps_lock);
246
247 if (sta->ps == enabled)
248 return;
249
250 mt76_wr(dev, MT_PSE_RTA,
251 FIELD_PREP(MT_PSE_RTA_TAG_ID, idx) |
252 FIELD_PREP(MT_PSE_RTA_PORT_ID, 0) |
253 FIELD_PREP(MT_PSE_RTA_QUEUE_ID, 1) |
254 FIELD_PREP(MT_PSE_RTA_REDIRECT_EN, enabled) |
255 MT_PSE_RTA_WRITE | MT_PSE_RTA_BUSY);
256
257 mt76_poll(dev, MT_PSE_RTA, MT_PSE_RTA_BUSY, 0, 5000);
258
259 if (enabled && filter)
260 mt7603_filter_tx(dev, sta->vif->idx, idx, false);
261
262 addr = mt7603_wtbl1_addr(idx);
263 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
264 mt76_rmw(dev, addr + 3 * 4, MT_WTBL1_W3_POWER_SAVE,
265 enabled * MT_WTBL1_W3_POWER_SAVE);
266 mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
267 sta->ps = enabled;
268 }
269
mt7603_wtbl_set_ps(struct mt7603_dev * dev,struct mt7603_sta * sta,bool enabled)270 void mt7603_wtbl_set_ps(struct mt7603_dev *dev, struct mt7603_sta *sta,
271 bool enabled)
272 {
273 spin_lock_bh(&dev->ps_lock);
274 __mt7603_wtbl_set_ps(dev, sta, enabled, enabled);
275 spin_unlock_bh(&dev->ps_lock);
276 }
277
mt7603_wtbl_sta_ps(struct mt7603_dev * dev,struct mt7603_sta * sta,bool ps)278 void mt7603_wtbl_sta_ps(struct mt7603_dev *dev, struct mt7603_sta *sta, bool ps)
279 {
280 spin_lock_bh(&dev->ps_lock);
281 sta->ps_sleeping = ps;
282 __mt7603_wtbl_set_ps(dev, sta, ps, ps);
283 spin_unlock_bh(&dev->ps_lock);
284 }
285
mt7603_wtbl_restore_ps(struct mt7603_dev * dev,struct mt7603_sta * sta)286 void mt7603_wtbl_restore_ps(struct mt7603_dev *dev, struct mt7603_sta *sta)
287 {
288 spin_lock_bh(&dev->ps_lock);
289 /*
290 * Frames that are already queued for the station belong to the service
291 * period that has just been served, so unlike on a sleep transition
292 * they must not be pulled back into the PS queue.
293 */
294 if (sta->ps_sleeping)
295 __mt7603_wtbl_set_ps(dev, sta, true, false);
296 spin_unlock_bh(&dev->ps_lock);
297 }
298
mt7603_wtbl_clear(struct mt7603_dev * dev,int idx)299 void mt7603_wtbl_clear(struct mt7603_dev *dev, int idx)
300 {
301 int wtbl2_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL2_SIZE;
302 int wtbl2_frame = idx / wtbl2_frame_size;
303 int wtbl2_entry = idx % wtbl2_frame_size;
304
305 int wtbl3_base_frame = MT_WTBL3_OFFSET / MT_PSE_PAGE_SIZE;
306 int wtbl3_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL3_SIZE;
307 int wtbl3_frame = wtbl3_base_frame + idx / wtbl3_frame_size;
308 int wtbl3_entry = (idx % wtbl3_frame_size) * 2;
309
310 int wtbl4_base_frame = MT_WTBL4_OFFSET / MT_PSE_PAGE_SIZE;
311 int wtbl4_frame_size = MT_PSE_PAGE_SIZE / MT_WTBL4_SIZE;
312 int wtbl4_frame = wtbl4_base_frame + idx / wtbl4_frame_size;
313 int wtbl4_entry = idx % wtbl4_frame_size;
314
315 u32 addr = MT_WTBL1_BASE + idx * MT_WTBL1_SIZE;
316 int i;
317
318 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
319
320 mt76_wr(dev, addr + 0 * 4,
321 MT_WTBL1_W0_RX_CHECK_A1 |
322 MT_WTBL1_W0_RX_CHECK_A2 |
323 MT_WTBL1_W0_RX_VALID);
324 mt76_wr(dev, addr + 1 * 4, 0);
325 mt76_wr(dev, addr + 2 * 4, 0);
326
327 mt76_set(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
328
329 mt76_wr(dev, addr + 3 * 4,
330 FIELD_PREP(MT_WTBL1_W3_WTBL2_FRAME_ID, wtbl2_frame) |
331 FIELD_PREP(MT_WTBL1_W3_WTBL2_ENTRY_ID, wtbl2_entry) |
332 FIELD_PREP(MT_WTBL1_W3_WTBL4_FRAME_ID, wtbl4_frame) |
333 MT_WTBL1_W3_I_PSM | MT_WTBL1_W3_KEEP_I_PSM);
334 mt76_wr(dev, addr + 4 * 4,
335 FIELD_PREP(MT_WTBL1_W4_WTBL3_FRAME_ID, wtbl3_frame) |
336 FIELD_PREP(MT_WTBL1_W4_WTBL3_ENTRY_ID, wtbl3_entry) |
337 FIELD_PREP(MT_WTBL1_W4_WTBL4_ENTRY_ID, wtbl4_entry));
338
339 mt76_clear(dev, MT_WTBL1_OR, MT_WTBL1_OR_PSM_WRITE);
340
341 addr = mt7603_wtbl2_addr(idx);
342
343 /* Clear BA information */
344 mt76_wr(dev, addr + (15 * 4), 0);
345
346 mt76_stop_tx_ac(dev, GENMASK(3, 0));
347 for (i = 2; i <= 4; i++)
348 mt76_wr(dev, addr + (i * 4), 0);
349 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_WTBL2);
350 mt76_start_tx_ac(dev, GENMASK(3, 0));
351
352 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_RX_COUNT_CLEAR);
353 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_TX_COUNT_CLEAR);
354 mt7603_wtbl_update(dev, idx, MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
355 }
356
mt7603_wtbl_update_cap(struct mt7603_dev * dev,struct ieee80211_sta * sta)357 void mt7603_wtbl_update_cap(struct mt7603_dev *dev, struct ieee80211_sta *sta)
358 {
359 struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
360 int idx = msta->wcid.idx;
361 u8 ampdu_density;
362 u32 addr;
363 u32 val;
364
365 addr = mt7603_wtbl1_addr(idx);
366
367 ampdu_density = sta->deflink.ht_cap.ampdu_density;
368 if (ampdu_density < IEEE80211_HT_MPDU_DENSITY_4)
369 ampdu_density = IEEE80211_HT_MPDU_DENSITY_4;
370
371 val = mt76_rr(dev, addr + 2 * 4);
372 val &= MT_WTBL1_W2_KEY_TYPE | MT_WTBL1_W2_ADMISSION_CONTROL;
373 val |= FIELD_PREP(MT_WTBL1_W2_AMPDU_FACTOR,
374 sta->deflink.ht_cap.ampdu_factor) |
375 FIELD_PREP(MT_WTBL1_W2_MPDU_DENSITY,
376 sta->deflink.ht_cap.ampdu_density) |
377 MT_WTBL1_W2_TXS_BAF_REPORT;
378
379 if (sta->deflink.ht_cap.cap)
380 val |= MT_WTBL1_W2_HT;
381 if (sta->deflink.vht_cap.cap)
382 val |= MT_WTBL1_W2_VHT;
383
384 mt76_wr(dev, addr + 2 * 4, val);
385
386 addr = mt7603_wtbl2_addr(idx);
387 val = mt76_rr(dev, addr + 9 * 4);
388 val &= ~(MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 |
389 MT_WTBL2_W9_SHORT_GI_80);
390 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_20)
391 val |= MT_WTBL2_W9_SHORT_GI_20;
392 if (sta->deflink.ht_cap.cap & IEEE80211_HT_CAP_SGI_40)
393 val |= MT_WTBL2_W9_SHORT_GI_40;
394 mt76_wr(dev, addr + 9 * 4, val);
395 }
396
mt7603_mac_rx_ba_reset(struct mt7603_dev * dev,void * addr,u8 tid)397 void mt7603_mac_rx_ba_reset(struct mt7603_dev *dev, void *addr, u8 tid)
398 {
399 mt76_wr(dev, MT_BA_CONTROL_0, get_unaligned_le32(addr));
400 mt76_wr(dev, MT_BA_CONTROL_1,
401 (get_unaligned_le16(addr + 4) |
402 FIELD_PREP(MT_BA_CONTROL_1_TID, tid) |
403 MT_BA_CONTROL_1_RESET));
404 }
405
mt7603_mac_tx_ba_reset(struct mt7603_dev * dev,int wcid,int tid,int ba_size)406 void mt7603_mac_tx_ba_reset(struct mt7603_dev *dev, int wcid, int tid,
407 int ba_size)
408 {
409 u32 addr = mt7603_wtbl2_addr(wcid);
410 u32 tid_mask = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) |
411 (MT_WTBL2_W15_BA_WIN_SIZE <<
412 (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT));
413 u32 tid_val;
414 int i;
415
416 if (ba_size < 0) {
417 /* disable */
418 mt76_clear(dev, addr + (15 * 4), tid_mask);
419 return;
420 }
421
422 for (i = 7; i > 0; i--) {
423 if (ba_size >= MT_AGG_SIZE_LIMIT(i))
424 break;
425 }
426
427 tid_val = FIELD_PREP(MT_WTBL2_W15_BA_EN_TIDS, BIT(tid)) |
428 i << (tid * MT_WTBL2_W15_BA_WIN_SIZE_SHIFT);
429
430 mt76_rmw(dev, addr + (15 * 4), tid_mask, tid_val);
431 }
432
mt7603_mac_sta_poll(struct mt7603_dev * dev)433 void mt7603_mac_sta_poll(struct mt7603_dev *dev)
434 {
435 static const u8 ac_to_tid[4] = {
436 [IEEE80211_AC_BE] = 0,
437 [IEEE80211_AC_BK] = 1,
438 [IEEE80211_AC_VI] = 4,
439 [IEEE80211_AC_VO] = 6
440 };
441 struct ieee80211_sta *sta;
442 struct mt7603_sta *msta;
443 u32 total_airtime = 0;
444 u32 airtime[4];
445 u32 addr;
446 int i;
447
448 rcu_read_lock();
449
450 while (1) {
451 bool clear = false;
452
453 spin_lock_bh(&dev->mt76.sta_poll_lock);
454 if (list_empty(&dev->mt76.sta_poll_list)) {
455 spin_unlock_bh(&dev->mt76.sta_poll_lock);
456 break;
457 }
458
459 msta = list_first_entry(&dev->mt76.sta_poll_list,
460 struct mt7603_sta, wcid.poll_list);
461 list_del_init(&msta->wcid.poll_list);
462 spin_unlock_bh(&dev->mt76.sta_poll_lock);
463
464 addr = mt7603_wtbl4_addr(msta->wcid.idx);
465 for (i = 0; i < 4; i++) {
466 u32 airtime_last = msta->tx_airtime_ac[i];
467
468 msta->tx_airtime_ac[i] = mt76_rr(dev, addr + i * 8);
469 airtime[i] = msta->tx_airtime_ac[i] - airtime_last;
470 airtime[i] *= 32;
471 total_airtime += airtime[i];
472
473 if (msta->tx_airtime_ac[i] & BIT(22))
474 clear = true;
475 }
476
477 if (clear) {
478 mt7603_wtbl_update(dev, msta->wcid.idx,
479 MT_WTBL_UPDATE_ADM_COUNT_CLEAR);
480 memset(msta->tx_airtime_ac, 0,
481 sizeof(msta->tx_airtime_ac));
482 }
483
484 if (!msta->wcid.sta)
485 continue;
486
487 sta = container_of((void *)msta, struct ieee80211_sta, drv_priv);
488 for (i = 0; i < 4; i++) {
489 struct mt76_queue *q = dev->mphy.q_tx[i];
490 u8 qidx = q->hw_idx;
491 u8 tid = ac_to_tid[i];
492 u32 txtime = airtime[qidx];
493
494 if (!txtime)
495 continue;
496
497 ieee80211_sta_register_airtime(sta, tid, txtime, 0);
498 }
499 }
500
501 rcu_read_unlock();
502
503 if (!total_airtime)
504 return;
505
506 spin_lock_bh(&dev->mt76.cc_lock);
507 dev->mphy.chan_state->cc_tx += total_airtime;
508 spin_unlock_bh(&dev->mt76.cc_lock);
509 }
510
511 static struct mt76_wcid *
mt7603_rx_get_wcid(struct mt7603_dev * dev,u8 idx,bool unicast)512 mt7603_rx_get_wcid(struct mt7603_dev *dev, u8 idx, bool unicast)
513 {
514 struct mt7603_sta *sta;
515 struct mt76_wcid *wcid;
516
517 wcid = mt76_wcid_ptr(dev, idx);
518 if (unicast || !wcid)
519 return wcid;
520
521 if (!wcid->sta)
522 return NULL;
523
524 sta = container_of(wcid, struct mt7603_sta, wcid);
525 if (!sta->vif)
526 return NULL;
527
528 return &sta->vif->sta.wcid;
529 }
530
531 int
mt7603_mac_fill_rx(struct mt7603_dev * dev,struct sk_buff * skb)532 mt7603_mac_fill_rx(struct mt7603_dev *dev, struct sk_buff *skb)
533 {
534 struct mt76_rx_status *status = (struct mt76_rx_status *)skb->cb;
535 struct ieee80211_supported_band *sband;
536 struct ieee80211_hdr *hdr;
537 __le32 *rxd = (__le32 *)skb->data;
538 u32 rxd0 = le32_to_cpu(rxd[0]);
539 u32 rxd1 = le32_to_cpu(rxd[1]);
540 u32 rxd2 = le32_to_cpu(rxd[2]);
541 bool unicast = rxd1 & MT_RXD1_NORMAL_U2M;
542 bool insert_ccmp_hdr = false;
543 bool remove_pad;
544 int idx;
545 int i;
546
547 memset(status, 0, sizeof(*status));
548
549 i = FIELD_GET(MT_RXD1_NORMAL_CH_FREQ, rxd1);
550 sband = (i & 1) ? &dev->mphy.sband_5g.sband : &dev->mphy.sband_2g.sband;
551 i >>= 1;
552
553 idx = FIELD_GET(MT_RXD2_NORMAL_WLAN_IDX, rxd2);
554 status->wcid = mt7603_rx_get_wcid(dev, idx, unicast);
555
556 status->band = sband->band;
557 if (i < sband->n_channels)
558 status->freq = sband->channels[i].center_freq;
559
560 if (rxd2 & MT_RXD2_NORMAL_FCS_ERR)
561 status->flag |= RX_FLAG_FAILED_FCS_CRC;
562
563 if (rxd2 & MT_RXD2_NORMAL_TKIP_MIC_ERR)
564 status->flag |= RX_FLAG_MMIC_ERROR;
565
566 /* ICV error or CCMP/BIP/WPI MIC error */
567 if (rxd2 & MT_RXD2_NORMAL_ICV_ERR)
568 status->flag |= RX_FLAG_ONLY_MONITOR;
569
570 if (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2) != 0 &&
571 !(rxd2 & (MT_RXD2_NORMAL_CLM | MT_RXD2_NORMAL_CM))) {
572 status->flag |= RX_FLAG_DECRYPTED;
573 status->flag |= RX_FLAG_IV_STRIPPED;
574 status->flag |= RX_FLAG_MMIC_STRIPPED | RX_FLAG_MIC_STRIPPED;
575 }
576
577 remove_pad = rxd1 & MT_RXD1_NORMAL_HDR_OFFSET;
578
579 if (rxd2 & MT_RXD2_NORMAL_MAX_LEN_ERROR)
580 return -EINVAL;
581
582 if (!sband->channels)
583 return -EINVAL;
584
585 rxd += 4;
586 if (rxd0 & MT_RXD0_NORMAL_GROUP_4) {
587 rxd += 4;
588 if ((u8 *)rxd - skb->data >= skb->len)
589 return -EINVAL;
590 }
591 if (rxd0 & MT_RXD0_NORMAL_GROUP_1) {
592 u8 *data = (u8 *)rxd;
593
594 if (status->flag & RX_FLAG_DECRYPTED) {
595 switch (FIELD_GET(MT_RXD2_NORMAL_SEC_MODE, rxd2)) {
596 case MT_CIPHER_AES_CCMP:
597 case MT_CIPHER_CCMP_CCX:
598 case MT_CIPHER_CCMP_256:
599 insert_ccmp_hdr =
600 FIELD_GET(MT_RXD2_NORMAL_FRAG, rxd2);
601 fallthrough;
602 case MT_CIPHER_TKIP:
603 case MT_CIPHER_TKIP_NO_MIC:
604 case MT_CIPHER_GCMP:
605 case MT_CIPHER_GCMP_256:
606 status->iv[0] = data[5];
607 status->iv[1] = data[4];
608 status->iv[2] = data[3];
609 status->iv[3] = data[2];
610 status->iv[4] = data[1];
611 status->iv[5] = data[0];
612 break;
613 default:
614 break;
615 }
616 }
617
618 rxd += 4;
619 if ((u8 *)rxd - skb->data >= skb->len)
620 return -EINVAL;
621 }
622 if (rxd0 & MT_RXD0_NORMAL_GROUP_2) {
623 status->timestamp = le32_to_cpu(rxd[0]);
624 status->flag |= RX_FLAG_MACTIME_START;
625
626 if (!(rxd2 & (MT_RXD2_NORMAL_NON_AMPDU_SUB |
627 MT_RXD2_NORMAL_NON_AMPDU))) {
628 status->flag |= RX_FLAG_AMPDU_DETAILS;
629
630 /* all subframes of an A-MPDU have the same timestamp */
631 if (dev->rx_ampdu_ts != status->timestamp) {
632 if (!++dev->ampdu_ref)
633 dev->ampdu_ref++;
634 }
635 dev->rx_ampdu_ts = status->timestamp;
636
637 status->ampdu_ref = dev->ampdu_ref;
638 }
639
640 rxd += 2;
641 if ((u8 *)rxd - skb->data >= skb->len)
642 return -EINVAL;
643 }
644 if (rxd0 & MT_RXD0_NORMAL_GROUP_3) {
645 u32 rxdg0 = le32_to_cpu(rxd[0]);
646 u32 rxdg3 = le32_to_cpu(rxd[3]);
647 bool cck = false;
648
649 i = FIELD_GET(MT_RXV1_TX_RATE, rxdg0);
650 switch (FIELD_GET(MT_RXV1_TX_MODE, rxdg0)) {
651 case MT_PHY_TYPE_CCK:
652 cck = true;
653 fallthrough;
654 case MT_PHY_TYPE_OFDM:
655 i = mt76_get_rate(&dev->mt76, sband, i, cck);
656 break;
657 case MT_PHY_TYPE_HT_GF:
658 case MT_PHY_TYPE_HT:
659 status->encoding = RX_ENC_HT;
660 if (i > 15)
661 return -EINVAL;
662 break;
663 default:
664 return -EINVAL;
665 }
666
667 if (rxdg0 & MT_RXV1_HT_SHORT_GI)
668 status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
669 if (rxdg0 & MT_RXV1_HT_AD_CODE)
670 status->enc_flags |= RX_ENC_FLAG_LDPC;
671
672 status->enc_flags |= RX_ENC_FLAG_STBC_MASK *
673 FIELD_GET(MT_RXV1_HT_STBC, rxdg0);
674
675 status->rate_idx = i;
676
677 status->chains = dev->mphy.antenna_mask;
678 status->chain_signal[0] = FIELD_GET(MT_RXV4_IB_RSSI0, rxdg3) +
679 dev->rssi_offset[0];
680 status->chain_signal[1] = FIELD_GET(MT_RXV4_IB_RSSI1, rxdg3) +
681 dev->rssi_offset[1];
682
683 if (FIELD_GET(MT_RXV1_FRAME_MODE, rxdg0) == 1)
684 status->bw = RATE_INFO_BW_40;
685
686 rxd += 6;
687 if ((u8 *)rxd - skb->data >= skb->len)
688 return -EINVAL;
689 } else {
690 return -EINVAL;
691 }
692
693 skb_pull(skb, (u8 *)rxd - skb->data + 2 * remove_pad);
694
695 if (insert_ccmp_hdr) {
696 u8 key_id = FIELD_GET(MT_RXD1_NORMAL_KEY_ID, rxd1);
697
698 mt76_insert_ccmp_hdr(skb, key_id);
699 }
700
701 hdr = (struct ieee80211_hdr *)skb->data;
702 if (!status->wcid || !ieee80211_is_data_qos(hdr->frame_control))
703 return 0;
704
705 status->aggr = unicast &&
706 !ieee80211_is_qos_nullfunc(hdr->frame_control);
707 status->qos_ctl = *ieee80211_get_qos_ctl(hdr);
708 status->seqno = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
709
710 return 0;
711 }
712
713 static u16
mt7603_mac_tx_rate_val(struct mt7603_dev * dev,const struct ieee80211_tx_rate * rate,bool stbc,u8 * bw)714 mt7603_mac_tx_rate_val(struct mt7603_dev *dev,
715 const struct ieee80211_tx_rate *rate, bool stbc, u8 *bw)
716 {
717 u8 phy, nss, rate_idx;
718 u16 rateval;
719
720 *bw = 0;
721 if (rate->flags & IEEE80211_TX_RC_MCS) {
722 rate_idx = rate->idx;
723 nss = 1 + (rate->idx >> 3);
724 phy = MT_PHY_TYPE_HT;
725 if (rate->flags & IEEE80211_TX_RC_GREEN_FIELD)
726 phy = MT_PHY_TYPE_HT_GF;
727 if (rate->flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
728 *bw = 1;
729 } else {
730 const struct ieee80211_rate *r;
731 int band = dev->mphy.chandef.chan->band;
732 u16 val;
733
734 nss = 1;
735 r = &mt76_hw(dev)->wiphy->bands[band]->bitrates[rate->idx];
736 if (rate->flags & IEEE80211_TX_RC_USE_SHORT_PREAMBLE)
737 val = r->hw_value_short;
738 else
739 val = r->hw_value;
740
741 phy = val >> 8;
742 rate_idx = val & 0xff;
743 }
744
745 rateval = (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) |
746 FIELD_PREP(MT_TX_RATE_MODE, phy));
747
748 if (stbc && nss == 1)
749 rateval |= MT_TX_RATE_STBC;
750
751 return rateval;
752 }
753
mt7603_wtbl_set_rates(struct mt7603_dev * dev,struct mt7603_sta * sta,struct ieee80211_tx_rate * probe_rate,struct ieee80211_tx_rate * rates)754 void mt7603_wtbl_set_rates(struct mt7603_dev *dev, struct mt7603_sta *sta,
755 struct ieee80211_tx_rate *probe_rate,
756 struct ieee80211_tx_rate *rates)
757 {
758 struct ieee80211_tx_rate *ref;
759 int wcid = sta->wcid.idx;
760 u32 addr = mt7603_wtbl2_addr(wcid);
761 bool stbc = false;
762 int n_rates = sta->n_rates;
763 u8 bw, bw_prev, bw_idx = 0;
764 u16 val[4];
765 u16 probe_val;
766 u32 w9 = mt76_rr(dev, addr + 9 * 4);
767 bool rateset;
768 int i, k;
769
770 if (!mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000))
771 return;
772
773 for (i = n_rates; i < 4; i++)
774 rates[i] = rates[n_rates - 1];
775
776 rateset = !(sta->rate_set_tsf & BIT(0));
777 memcpy(sta->rateset[rateset].rates, rates,
778 sizeof(sta->rateset[rateset].rates));
779 if (probe_rate) {
780 sta->rateset[rateset].probe_rate = *probe_rate;
781 ref = &sta->rateset[rateset].probe_rate;
782 } else {
783 sta->rateset[rateset].probe_rate.idx = -1;
784 ref = &sta->rateset[rateset].rates[0];
785 }
786
787 rates = sta->rateset[rateset].rates;
788 for (i = 0; i < ARRAY_SIZE(sta->rateset[rateset].rates); i++) {
789 /*
790 * We don't support switching between short and long GI
791 * within the rate set. For accurate tx status reporting, we
792 * need to make sure that flags match.
793 * For improved performance, avoid duplicate entries by
794 * decrementing the MCS index if necessary
795 */
796 if ((ref->flags ^ rates[i].flags) & IEEE80211_TX_RC_SHORT_GI)
797 rates[i].flags ^= IEEE80211_TX_RC_SHORT_GI;
798
799 for (k = 0; k < i; k++) {
800 if (rates[i].idx != rates[k].idx)
801 continue;
802 if ((rates[i].flags ^ rates[k].flags) &
803 IEEE80211_TX_RC_40_MHZ_WIDTH)
804 continue;
805
806 if (!rates[i].idx)
807 continue;
808
809 rates[i].idx--;
810 }
811 }
812
813 w9 &= MT_WTBL2_W9_SHORT_GI_20 | MT_WTBL2_W9_SHORT_GI_40 |
814 MT_WTBL2_W9_SHORT_GI_80;
815
816 val[0] = mt7603_mac_tx_rate_val(dev, &rates[0], stbc, &bw);
817 bw_prev = bw;
818
819 if (probe_rate) {
820 probe_val = mt7603_mac_tx_rate_val(dev, probe_rate, stbc, &bw);
821 if (bw)
822 bw_idx = 1;
823 else
824 bw_prev = 0;
825 } else {
826 probe_val = val[0];
827 }
828
829 w9 |= FIELD_PREP(MT_WTBL2_W9_CC_BW_SEL, bw);
830 w9 |= FIELD_PREP(MT_WTBL2_W9_BW_CAP, bw);
831
832 val[1] = mt7603_mac_tx_rate_val(dev, &rates[1], stbc, &bw);
833 if (bw_prev) {
834 bw_idx = 3;
835 bw_prev = bw;
836 }
837
838 val[2] = mt7603_mac_tx_rate_val(dev, &rates[2], stbc, &bw);
839 if (bw_prev) {
840 bw_idx = 5;
841 bw_prev = bw;
842 }
843
844 val[3] = mt7603_mac_tx_rate_val(dev, &rates[3], stbc, &bw);
845 if (bw_prev)
846 bw_idx = 7;
847
848 w9 |= FIELD_PREP(MT_WTBL2_W9_CHANGE_BW_RATE,
849 bw_idx ? bw_idx - 1 : 7);
850
851 mt76_wr(dev, MT_WTBL_RIUCR0, w9);
852
853 mt76_wr(dev, MT_WTBL_RIUCR1,
854 FIELD_PREP(MT_WTBL_RIUCR1_RATE0, probe_val) |
855 FIELD_PREP(MT_WTBL_RIUCR1_RATE1, val[0]) |
856 FIELD_PREP(MT_WTBL_RIUCR1_RATE2_LO, val[1]));
857
858 mt76_wr(dev, MT_WTBL_RIUCR2,
859 FIELD_PREP(MT_WTBL_RIUCR2_RATE2_HI, val[1] >> 8) |
860 FIELD_PREP(MT_WTBL_RIUCR2_RATE3, val[1]) |
861 FIELD_PREP(MT_WTBL_RIUCR2_RATE4, val[2]) |
862 FIELD_PREP(MT_WTBL_RIUCR2_RATE5_LO, val[2]));
863
864 mt76_wr(dev, MT_WTBL_RIUCR3,
865 FIELD_PREP(MT_WTBL_RIUCR3_RATE5_HI, val[2] >> 4) |
866 FIELD_PREP(MT_WTBL_RIUCR3_RATE6, val[3]) |
867 FIELD_PREP(MT_WTBL_RIUCR3_RATE7, val[3]));
868
869 mt76_set(dev, MT_LPON_T0CR, MT_LPON_T0CR_MODE); /* TSF read */
870 sta->rate_set_tsf = (mt76_rr(dev, MT_LPON_UTTR0) & ~BIT(0)) | rateset;
871
872 mt76_wr(dev, MT_WTBL_UPDATE,
873 FIELD_PREP(MT_WTBL_UPDATE_WLAN_IDX, wcid) |
874 MT_WTBL_UPDATE_RATE_UPDATE |
875 MT_WTBL_UPDATE_TX_COUNT_CLEAR);
876
877 if (!(sta->wcid.tx_info & MT_WCID_TX_INFO_SET))
878 mt76_poll(dev, MT_WTBL_UPDATE, MT_WTBL_UPDATE_BUSY, 0, 5000);
879
880 sta->rate_count = 2 * MT7603_RATE_RETRY * n_rates;
881 sta->wcid.tx_info |= MT_WCID_TX_INFO_SET;
882 }
883
884 static enum mt76_cipher_type
mt7603_mac_get_key_info(struct ieee80211_key_conf * key,u8 * key_data)885 mt7603_mac_get_key_info(struct ieee80211_key_conf *key, u8 *key_data)
886 {
887 memset(key_data, 0, 32);
888 if (!key)
889 return MT_CIPHER_NONE;
890
891 if (key->keylen > 32)
892 return MT_CIPHER_NONE;
893
894 memcpy(key_data, key->key, key->keylen);
895
896 switch (key->cipher) {
897 case WLAN_CIPHER_SUITE_WEP40:
898 return MT_CIPHER_WEP40;
899 case WLAN_CIPHER_SUITE_WEP104:
900 return MT_CIPHER_WEP104;
901 case WLAN_CIPHER_SUITE_TKIP:
902 /* Rx/Tx MIC keys are swapped */
903 memcpy(key_data + 16, key->key + 24, 8);
904 memcpy(key_data + 24, key->key + 16, 8);
905 return MT_CIPHER_TKIP;
906 case WLAN_CIPHER_SUITE_CCMP:
907 return MT_CIPHER_AES_CCMP;
908 default:
909 return MT_CIPHER_NONE;
910 }
911 }
912
mt7603_wtbl_set_key(struct mt7603_dev * dev,int wcid,struct ieee80211_key_conf * key)913 int mt7603_wtbl_set_key(struct mt7603_dev *dev, int wcid,
914 struct ieee80211_key_conf *key)
915 {
916 enum mt76_cipher_type cipher;
917 u32 addr = mt7603_wtbl3_addr(wcid);
918 u8 key_data[32];
919 int key_len = sizeof(key_data);
920
921 cipher = mt7603_mac_get_key_info(key, key_data);
922 if (cipher == MT_CIPHER_NONE && key)
923 return -EOPNOTSUPP;
924
925 if (key && (cipher == MT_CIPHER_WEP40 || cipher == MT_CIPHER_WEP104)) {
926 addr += key->keyidx * 16;
927 key_len = 16;
928 }
929
930 mt76_wr_copy(dev, addr, key_data, key_len);
931
932 addr = mt7603_wtbl1_addr(wcid);
933 mt76_rmw_field(dev, addr + 2 * 4, MT_WTBL1_W2_KEY_TYPE, cipher);
934 if (key)
935 mt76_rmw_field(dev, addr, MT_WTBL1_W0_KEY_IDX, key->keyidx);
936 mt76_rmw_field(dev, addr, MT_WTBL1_W0_RX_KEY_VALID, !!key);
937
938 return 0;
939 }
940
941 static int
mt7603_mac_write_txwi(struct mt7603_dev * dev,__le32 * txwi,struct sk_buff * skb,enum mt76_txq_id qid,struct mt76_wcid * wcid,struct ieee80211_sta * sta,int pid,struct ieee80211_key_conf * key)942 mt7603_mac_write_txwi(struct mt7603_dev *dev, __le32 *txwi,
943 struct sk_buff *skb, enum mt76_txq_id qid,
944 struct mt76_wcid *wcid, struct ieee80211_sta *sta,
945 int pid, struct ieee80211_key_conf *key)
946 {
947 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
948 struct ieee80211_tx_rate *rate = &info->control.rates[0];
949 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
950 struct ieee80211_bar *bar = (struct ieee80211_bar *)skb->data;
951 struct ieee80211_vif *vif = info->control.vif;
952 struct mt76_queue *q = dev->mphy.q_tx[qid];
953 struct mt7603_vif *mvif;
954 int wlan_idx;
955 int hdr_len = ieee80211_get_hdrlen_from_skb(skb);
956 int tx_count = 8;
957 u8 frame_type, frame_subtype;
958 u16 fc = le16_to_cpu(hdr->frame_control);
959 u16 seqno = 0;
960 u8 vif_idx = 0;
961 u32 val;
962 u8 bw;
963
964 if (vif) {
965 mvif = (struct mt7603_vif *)vif->drv_priv;
966 vif_idx = mvif->idx;
967 if (vif_idx && qid >= MT_TXQ_BEACON)
968 vif_idx += 0x10;
969 }
970
971 if (sta) {
972 struct mt7603_sta *msta = (struct mt7603_sta *)sta->drv_priv;
973
974 tx_count = msta->rate_count;
975 }
976
977 if (wcid)
978 wlan_idx = wcid->idx;
979 else
980 wlan_idx = MT7603_WTBL_RESERVED;
981
982 frame_type = (fc & IEEE80211_FCTL_FTYPE) >> 2;
983 frame_subtype = (fc & IEEE80211_FCTL_STYPE) >> 4;
984
985 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) |
986 FIELD_PREP(MT_TXD0_Q_IDX, q->hw_idx);
987 txwi[0] = cpu_to_le32(val);
988
989 val = MT_TXD1_LONG_FORMAT |
990 FIELD_PREP(MT_TXD1_OWN_MAC, vif_idx) |
991 FIELD_PREP(MT_TXD1_TID,
992 skb->priority & IEEE80211_QOS_CTL_TID_MASK) |
993 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) |
994 FIELD_PREP(MT_TXD1_HDR_INFO, hdr_len / 2) |
995 FIELD_PREP(MT_TXD1_WLAN_IDX, wlan_idx) |
996 FIELD_PREP(MT_TXD1_PROTECTED, !!key);
997 txwi[1] = cpu_to_le32(val);
998
999 if (info->flags & IEEE80211_TX_CTL_NO_ACK)
1000 txwi[1] |= cpu_to_le32(MT_TXD1_NO_ACK);
1001
1002 val = FIELD_PREP(MT_TXD2_FRAME_TYPE, frame_type) |
1003 FIELD_PREP(MT_TXD2_SUB_TYPE, frame_subtype) |
1004 FIELD_PREP(MT_TXD2_MULTICAST,
1005 is_multicast_ether_addr(hdr->addr1));
1006 txwi[2] = cpu_to_le32(val);
1007
1008 if (!(info->flags & IEEE80211_TX_CTL_AMPDU))
1009 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
1010
1011 txwi[4] = 0;
1012
1013 val = MT_TXD5_TX_STATUS_HOST | MT_TXD5_SW_POWER_MGMT |
1014 FIELD_PREP(MT_TXD5_PID, pid);
1015 txwi[5] = cpu_to_le32(val);
1016
1017 txwi[6] = 0;
1018
1019 if (rate->idx >= 0 && rate->count &&
1020 !(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE)) {
1021 bool stbc = info->flags & IEEE80211_TX_CTL_STBC;
1022 u16 rateval = mt7603_mac_tx_rate_val(dev, rate, stbc, &bw);
1023
1024 txwi[2] |= cpu_to_le32(MT_TXD2_FIX_RATE);
1025
1026 val = MT_TXD6_FIXED_BW |
1027 FIELD_PREP(MT_TXD6_BW, bw) |
1028 FIELD_PREP(MT_TXD6_TX_RATE, rateval);
1029 txwi[6] |= cpu_to_le32(val);
1030
1031 if (rate->flags & IEEE80211_TX_RC_SHORT_GI)
1032 txwi[6] |= cpu_to_le32(MT_TXD6_SGI);
1033
1034 if (!(rate->flags & IEEE80211_TX_RC_MCS))
1035 txwi[2] |= cpu_to_le32(MT_TXD2_BA_DISABLE);
1036
1037 tx_count = rate->count;
1038 }
1039
1040 /* use maximum tx count for beacons and buffered multicast */
1041 if (qid >= MT_TXQ_BEACON)
1042 tx_count = 0x1f;
1043
1044 val = FIELD_PREP(MT_TXD3_REM_TX_COUNT, tx_count) |
1045 MT_TXD3_SN_VALID;
1046
1047 if (ieee80211_is_data_qos(hdr->frame_control))
1048 seqno = le16_to_cpu(hdr->seq_ctrl);
1049 else if (ieee80211_is_back_req(hdr->frame_control))
1050 seqno = le16_to_cpu(bar->start_seq_num);
1051 else
1052 val &= ~MT_TXD3_SN_VALID;
1053
1054 val |= FIELD_PREP(MT_TXD3_SEQ, seqno >> 4);
1055
1056 txwi[3] = cpu_to_le32(val);
1057
1058 if (key) {
1059 u64 pn = atomic64_inc_return(&key->tx_pn);
1060
1061 txwi[3] |= cpu_to_le32(MT_TXD3_PN_VALID);
1062 txwi[4] = cpu_to_le32(pn & GENMASK(31, 0));
1063 txwi[5] |= cpu_to_le32(FIELD_PREP(MT_TXD5_PN_HIGH, pn >> 32));
1064 }
1065
1066 txwi[7] = 0;
1067
1068 return 0;
1069 }
1070
mt7603_tx_prepare_skb(struct mt76_dev * mdev,void * txwi_ptr,enum mt76_txq_id qid,struct mt76_wcid * wcid,struct ieee80211_sta * sta,struct mt76_tx_info * tx_info)1071 int mt7603_tx_prepare_skb(struct mt76_dev *mdev, void *txwi_ptr,
1072 enum mt76_txq_id qid, struct mt76_wcid *wcid,
1073 struct ieee80211_sta *sta,
1074 struct mt76_tx_info *tx_info)
1075 {
1076 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
1077 struct mt7603_sta *msta = container_of(wcid, struct mt7603_sta, wcid);
1078 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(tx_info->skb);
1079 struct ieee80211_key_conf *key = info->control.hw_key;
1080 int pid;
1081
1082 if (!wcid)
1083 wcid = &dev->global_sta.wcid;
1084
1085 if (sta) {
1086 msta = (struct mt7603_sta *)sta->drv_priv;
1087
1088 if ((info->flags & (IEEE80211_TX_CTL_NO_PS_BUFFER |
1089 IEEE80211_TX_CTL_CLEAR_PS_FILT)) ||
1090 (info->control.flags & IEEE80211_TX_CTRL_PS_RESPONSE))
1091 mt7603_wtbl_set_ps(dev, msta, false);
1092
1093 mt76_tx_check_agg_ssn(sta, tx_info->skb);
1094 }
1095
1096 pid = mt76_tx_status_skb_add(mdev, wcid, tx_info->skb);
1097
1098 if (info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE) {
1099 spin_lock_bh(&dev->mt76.lock);
1100 mt7603_wtbl_set_rates(dev, msta, &info->control.rates[0],
1101 msta->rates);
1102 msta->rate_probe = true;
1103 spin_unlock_bh(&dev->mt76.lock);
1104 }
1105
1106 mt7603_mac_write_txwi(dev, txwi_ptr, tx_info->skb, qid, wcid,
1107 sta, pid, key);
1108
1109 return 0;
1110 }
1111
1112 static bool
mt7603_fill_txs(struct mt7603_dev * dev,struct mt7603_sta * sta,struct ieee80211_tx_info * info,__le32 * txs_data)1113 mt7603_fill_txs(struct mt7603_dev *dev, struct mt7603_sta *sta,
1114 struct ieee80211_tx_info *info, __le32 *txs_data)
1115 {
1116 struct ieee80211_supported_band *sband;
1117 struct mt7603_rate_set *rs;
1118 int first_idx = 0, last_idx;
1119 u32 rate_set_tsf;
1120 u32 final_rate;
1121 u32 final_rate_flags;
1122 bool rs_idx;
1123 bool ack_timeout;
1124 bool fixed_rate;
1125 bool probe;
1126 bool ampdu;
1127 bool cck = false;
1128 int count;
1129 u32 txs;
1130 int idx;
1131 int i;
1132
1133 fixed_rate = info->status.rates[0].count;
1134 probe = !!(info->flags & IEEE80211_TX_CTL_RATE_CTRL_PROBE);
1135
1136 txs = le32_to_cpu(txs_data[4]);
1137 ampdu = !fixed_rate && (txs & MT_TXS4_AMPDU);
1138 count = FIELD_GET(MT_TXS4_TX_COUNT, txs);
1139 last_idx = FIELD_GET(MT_TXS4_LAST_TX_RATE, txs);
1140
1141 txs = le32_to_cpu(txs_data[0]);
1142 final_rate = FIELD_GET(MT_TXS0_TX_RATE, txs);
1143 ack_timeout = txs & MT_TXS0_ACK_TIMEOUT;
1144
1145 if (!ampdu && (txs & MT_TXS0_RTS_TIMEOUT))
1146 return false;
1147
1148 if (txs & MT_TXS0_QUEUE_TIMEOUT)
1149 return false;
1150
1151 if (!ack_timeout)
1152 info->flags |= IEEE80211_TX_STAT_ACK;
1153
1154 info->status.ampdu_len = 1;
1155 info->status.ampdu_ack_len = !!(info->flags &
1156 IEEE80211_TX_STAT_ACK);
1157
1158 if (ampdu || (info->flags & IEEE80211_TX_CTL_AMPDU))
1159 info->flags |= IEEE80211_TX_STAT_AMPDU | IEEE80211_TX_CTL_AMPDU;
1160
1161 first_idx = max_t(int, 0, last_idx - (count - 1) / MT7603_RATE_RETRY);
1162
1163 if (fixed_rate && !probe) {
1164 info->status.rates[0].count = count;
1165 i = 0;
1166 goto out;
1167 }
1168
1169 rate_set_tsf = READ_ONCE(sta->rate_set_tsf);
1170 rs_idx = !((u32)(le32_get_bits(txs_data[1], MT_TXS1_F0_TIMESTAMP) -
1171 rate_set_tsf) < 1000000);
1172 rs_idx ^= rate_set_tsf & BIT(0);
1173 rs = &sta->rateset[rs_idx];
1174
1175 if (!first_idx && rs->probe_rate.idx >= 0) {
1176 info->status.rates[0] = rs->probe_rate;
1177
1178 spin_lock_bh(&dev->mt76.lock);
1179 if (sta->rate_probe) {
1180 mt7603_wtbl_set_rates(dev, sta, NULL,
1181 sta->rates);
1182 sta->rate_probe = false;
1183 }
1184 spin_unlock_bh(&dev->mt76.lock);
1185 } else {
1186 info->status.rates[0] = rs->rates[first_idx / 2];
1187 }
1188 info->status.rates[0].count = 0;
1189
1190 for (i = 0, idx = first_idx; count && idx <= last_idx; idx++) {
1191 struct ieee80211_tx_rate *cur_rate;
1192 int cur_count;
1193
1194 cur_rate = &rs->rates[idx / 2];
1195 cur_count = min_t(int, MT7603_RATE_RETRY, count);
1196 count -= cur_count;
1197
1198 if (idx && (cur_rate->idx != info->status.rates[i].idx ||
1199 cur_rate->flags != info->status.rates[i].flags)) {
1200 i++;
1201 if (i == ARRAY_SIZE(info->status.rates)) {
1202 i--;
1203 break;
1204 }
1205
1206 info->status.rates[i] = *cur_rate;
1207 info->status.rates[i].count = 0;
1208 }
1209
1210 info->status.rates[i].count += cur_count;
1211 }
1212
1213 out:
1214 final_rate_flags = info->status.rates[i].flags;
1215
1216 switch (FIELD_GET(MT_TX_RATE_MODE, final_rate)) {
1217 case MT_PHY_TYPE_CCK:
1218 cck = true;
1219 fallthrough;
1220 case MT_PHY_TYPE_OFDM:
1221 if (dev->mphy.chandef.chan->band == NL80211_BAND_5GHZ)
1222 sband = &dev->mphy.sband_5g.sband;
1223 else
1224 sband = &dev->mphy.sband_2g.sband;
1225 final_rate &= GENMASK(5, 0);
1226 final_rate = mt76_get_rate(&dev->mt76, sband, final_rate,
1227 cck);
1228 final_rate_flags = 0;
1229 break;
1230 case MT_PHY_TYPE_HT_GF:
1231 case MT_PHY_TYPE_HT:
1232 final_rate_flags |= IEEE80211_TX_RC_MCS;
1233 final_rate &= GENMASK(5, 0);
1234 if (final_rate > 15)
1235 return false;
1236 break;
1237 default:
1238 return false;
1239 }
1240
1241 info->status.rates[i].idx = final_rate;
1242 info->status.rates[i].flags = final_rate_flags;
1243
1244 return true;
1245 }
1246
1247 static bool
mt7603_mac_add_txs_skb(struct mt7603_dev * dev,struct mt7603_sta * sta,int pid,__le32 * txs_data)1248 mt7603_mac_add_txs_skb(struct mt7603_dev *dev, struct mt7603_sta *sta, int pid,
1249 __le32 *txs_data)
1250 {
1251 struct mt76_dev *mdev = &dev->mt76;
1252 struct sk_buff_head list;
1253 struct sk_buff *skb;
1254
1255 if (pid < MT_PACKET_ID_FIRST)
1256 return false;
1257
1258 trace_mac_txdone(mdev, sta->wcid.idx, pid);
1259
1260 mt76_tx_status_lock(mdev, &list);
1261 skb = mt76_tx_status_skb_get(mdev, &sta->wcid, pid, &list);
1262 if (skb) {
1263 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1264
1265 if (!mt7603_fill_txs(dev, sta, info, txs_data)) {
1266 info->status.rates[0].count = 0;
1267 info->status.rates[0].idx = -1;
1268 }
1269
1270 mt76_tx_status_skb_done(mdev, skb, &list);
1271 }
1272 mt76_tx_status_unlock(mdev, &list);
1273
1274 return !!skb;
1275 }
1276
mt7603_mac_add_txs(struct mt7603_dev * dev,void * data)1277 void mt7603_mac_add_txs(struct mt7603_dev *dev, void *data)
1278 {
1279 struct ieee80211_tx_info info = {};
1280 struct ieee80211_sta *sta = NULL;
1281 struct mt7603_sta *msta = NULL;
1282 struct mt76_wcid *wcid;
1283 __le32 *txs_data = data;
1284 u8 wcidx;
1285 u8 pid;
1286
1287 pid = le32_get_bits(txs_data[4], MT_TXS4_PID);
1288 wcidx = le32_get_bits(txs_data[3], MT_TXS3_WCID);
1289
1290 if (pid == MT_PACKET_ID_NO_ACK)
1291 return;
1292
1293 rcu_read_lock();
1294
1295 wcid = mt76_wcid_ptr(dev, wcidx);
1296 if (!wcid)
1297 goto out;
1298
1299 msta = container_of(wcid, struct mt7603_sta, wcid);
1300 sta = wcid_to_sta(wcid);
1301 mt76_wcid_add_poll(&dev->mt76, &msta->wcid);
1302
1303 if (mt7603_mac_add_txs_skb(dev, msta, pid, txs_data))
1304 goto out;
1305
1306 if (wcidx >= MT7603_WTBL_STA || !sta)
1307 goto out;
1308
1309 if (mt7603_fill_txs(dev, msta, &info, txs_data)) {
1310 spin_lock_bh(&dev->mt76.rx_lock);
1311 ieee80211_tx_status_noskb(mt76_hw(dev), sta, &info);
1312 spin_unlock_bh(&dev->mt76.rx_lock);
1313 }
1314
1315 out:
1316 rcu_read_unlock();
1317 }
1318
mt7603_tx_complete_skb(struct mt76_dev * mdev,struct mt76_queue_entry * e)1319 void mt7603_tx_complete_skb(struct mt76_dev *mdev, struct mt76_queue_entry *e)
1320 {
1321 struct mt7603_dev *dev = container_of(mdev, struct mt7603_dev, mt76);
1322 struct sk_buff *skb = e->skb;
1323
1324 if (!e->txwi) {
1325 dev_kfree_skb_any(skb);
1326 return;
1327 }
1328
1329 dev->tx_hang_check = 0;
1330 mt76_tx_complete_skb(mdev, e->wcid, skb);
1331 }
1332
1333 static bool
wait_for_wpdma(struct mt7603_dev * dev)1334 wait_for_wpdma(struct mt7603_dev *dev)
1335 {
1336 return mt76_poll(dev, MT_WPDMA_GLO_CFG,
1337 MT_WPDMA_GLO_CFG_TX_DMA_BUSY |
1338 MT_WPDMA_GLO_CFG_RX_DMA_BUSY,
1339 0, 1000);
1340 }
1341
mt7603_pse_reset(struct mt7603_dev * dev)1342 static void mt7603_pse_reset(struct mt7603_dev *dev)
1343 {
1344 /* Clear previous reset result */
1345 if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED])
1346 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE_S);
1347
1348 /* Reset PSE */
1349 mt76_set(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE);
1350
1351 if (!mt76_poll_msec(dev, MT_MCU_DEBUG_RESET,
1352 MT_MCU_DEBUG_RESET_PSE_S,
1353 MT_MCU_DEBUG_RESET_PSE_S, 500)) {
1354 dev->reset_cause[RESET_CAUSE_RESET_FAILED]++;
1355 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_PSE);
1356 } else {
1357 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0;
1358 mt76_clear(dev, MT_MCU_DEBUG_RESET, MT_MCU_DEBUG_RESET_QUEUES);
1359 }
1360
1361 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] >= 3)
1362 dev->reset_cause[RESET_CAUSE_RESET_FAILED] = 0;
1363 }
1364
mt7603_mac_dma_start(struct mt7603_dev * dev)1365 void mt7603_mac_dma_start(struct mt7603_dev *dev)
1366 {
1367 mt7603_mac_start(dev);
1368
1369 wait_for_wpdma(dev);
1370 usleep_range(50, 100);
1371
1372 mt76_set(dev, MT_WPDMA_GLO_CFG,
1373 (MT_WPDMA_GLO_CFG_TX_DMA_EN |
1374 MT_WPDMA_GLO_CFG_RX_DMA_EN |
1375 FIELD_PREP(MT_WPDMA_GLO_CFG_DMA_BURST_SIZE, 3) |
1376 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE));
1377
1378 mt7603_irq_enable(dev, MT_INT_RX_DONE_ALL | MT_INT_TX_DONE_ALL);
1379 }
1380
mt7603_mac_start(struct mt7603_dev * dev)1381 void mt7603_mac_start(struct mt7603_dev *dev)
1382 {
1383 mt76_clear(dev, MT_ARB_SCR,
1384 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1385 mt76_wr(dev, MT_WF_ARB_TX_START_0, ~0);
1386 mt76_set(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);
1387 }
1388
mt7603_mac_stop(struct mt7603_dev * dev)1389 void mt7603_mac_stop(struct mt7603_dev *dev)
1390 {
1391 mt76_set(dev, MT_ARB_SCR,
1392 MT_ARB_SCR_TX_DISABLE | MT_ARB_SCR_RX_DISABLE);
1393 mt76_wr(dev, MT_WF_ARB_TX_START_0, 0);
1394 mt76_clear(dev, MT_WF_ARB_RQCR, MT_WF_ARB_RQCR_RX_START);
1395 }
1396
mt7603_pse_client_reset(struct mt7603_dev * dev)1397 void mt7603_pse_client_reset(struct mt7603_dev *dev)
1398 {
1399 u32 addr;
1400
1401 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR +
1402 MT_CLIENT_RESET_TX);
1403
1404 /* Clear previous reset state */
1405 mt76_clear(dev, addr,
1406 MT_CLIENT_RESET_TX_R_E_1 |
1407 MT_CLIENT_RESET_TX_R_E_2 |
1408 MT_CLIENT_RESET_TX_R_E_1_S |
1409 MT_CLIENT_RESET_TX_R_E_2_S);
1410
1411 /* Start PSE client TX abort */
1412 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_FORCE_TX_EOF);
1413 mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_1);
1414 mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_1_S,
1415 MT_CLIENT_RESET_TX_R_E_1_S, 500);
1416
1417 mt76_set(dev, addr, MT_CLIENT_RESET_TX_R_E_2);
1418 mt76_set(dev, MT_WPDMA_GLO_CFG, MT_WPDMA_GLO_CFG_SW_RESET);
1419
1420 /* Wait for PSE client to clear TX FIFO */
1421 mt76_poll_msec(dev, addr, MT_CLIENT_RESET_TX_R_E_2_S,
1422 MT_CLIENT_RESET_TX_R_E_2_S, 500);
1423
1424 /* Clear PSE client TX abort state */
1425 mt76_clear(dev, addr,
1426 MT_CLIENT_RESET_TX_R_E_1 |
1427 MT_CLIENT_RESET_TX_R_E_2);
1428 }
1429
mt7603_dma_sched_reset(struct mt7603_dev * dev)1430 static void mt7603_dma_sched_reset(struct mt7603_dev *dev)
1431 {
1432 if (!is_mt7628(dev))
1433 return;
1434
1435 mt76_set(dev, MT_SCH_4, MT_SCH_4_RESET);
1436 mt76_clear(dev, MT_SCH_4, MT_SCH_4_RESET);
1437 }
1438
mt7603_mac_watchdog_reset(struct mt7603_dev * dev)1439 static void mt7603_mac_watchdog_reset(struct mt7603_dev *dev)
1440 {
1441 int beacon_int = dev->mt76.beacon_int;
1442 u32 mask = dev->mt76.mmio.irqmask;
1443 int i;
1444
1445 ieee80211_stop_queues(dev->mt76.hw);
1446 set_bit(MT76_RESET, &dev->mphy.state);
1447
1448 /* lock/unlock all queues to ensure that no tx is pending */
1449 mt76_txq_schedule_all(&dev->mphy);
1450
1451 mt76_worker_disable(&dev->mt76.tx_worker);
1452 tasklet_disable(&dev->mt76.pre_tbtt_tasklet);
1453 napi_disable(&dev->mt76.napi[0]);
1454 napi_disable(&dev->mt76.napi[1]);
1455 napi_disable(&dev->mt76.tx_napi);
1456
1457 mutex_lock(&dev->mt76.mutex);
1458
1459 mt7603_beacon_set_timer(dev, -1, 0);
1460
1461 mt7603_mac_stop(dev);
1462
1463 mt76_clear(dev, MT_WPDMA_GLO_CFG,
1464 MT_WPDMA_GLO_CFG_RX_DMA_EN | MT_WPDMA_GLO_CFG_TX_DMA_EN |
1465 MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE);
1466 usleep_range(1000, 2000);
1467
1468 mt7603_irq_disable(dev, mask);
1469
1470 mt7603_pse_client_reset(dev);
1471
1472 mt76_queue_tx_cleanup(dev, dev->mt76.q_mcu[MT_MCUQ_WM], true);
1473 for (i = 0; i < __MT_TXQ_MAX; i++)
1474 mt76_queue_tx_cleanup(dev, dev->mphy.q_tx[i], true);
1475
1476 mt7603_dma_sched_reset(dev);
1477
1478 mt76_tx_status_check(&dev->mt76, true);
1479
1480 mt76_for_each_q_rx(&dev->mt76, i) {
1481 mt76_queue_rx_reset(dev, i);
1482 }
1483
1484 if (dev->reset_cause[RESET_CAUSE_RESET_FAILED] ||
1485 dev->cur_reset_cause == RESET_CAUSE_RX_PSE_BUSY)
1486 mt7603_pse_reset(dev);
1487
1488 if (!dev->reset_cause[RESET_CAUSE_RESET_FAILED]) {
1489 mt7603_mac_dma_start(dev);
1490
1491 mt7603_irq_enable(dev, mask);
1492
1493 clear_bit(MT76_RESET, &dev->mphy.state);
1494 }
1495
1496 mutex_unlock(&dev->mt76.mutex);
1497
1498 mt76_worker_enable(&dev->mt76.tx_worker);
1499
1500 tasklet_enable(&dev->mt76.pre_tbtt_tasklet);
1501 mt7603_beacon_set_timer(dev, -1, beacon_int);
1502
1503 napi_enable(&dev->mt76.tx_napi);
1504 napi_enable(&dev->mt76.napi[0]);
1505 napi_enable(&dev->mt76.napi[1]);
1506
1507 local_bh_disable();
1508 napi_schedule(&dev->mt76.tx_napi);
1509 napi_schedule(&dev->mt76.napi[0]);
1510 napi_schedule(&dev->mt76.napi[1]);
1511 local_bh_enable();
1512
1513 ieee80211_wake_queues(dev->mt76.hw);
1514 mt76_txq_schedule_all(&dev->mphy);
1515 }
1516
mt7603_dma_debug(struct mt7603_dev * dev,u8 index)1517 static u32 mt7603_dma_debug(struct mt7603_dev *dev, u8 index)
1518 {
1519 u32 val;
1520
1521 mt76_wr(dev, MT_WPDMA_DEBUG,
1522 FIELD_PREP(MT_WPDMA_DEBUG_IDX, index) |
1523 MT_WPDMA_DEBUG_SEL);
1524
1525 val = mt76_rr(dev, MT_WPDMA_DEBUG);
1526 return FIELD_GET(MT_WPDMA_DEBUG_VALUE, val);
1527 }
1528
mt7603_rx_fifo_busy(struct mt7603_dev * dev)1529 static bool mt7603_rx_fifo_busy(struct mt7603_dev *dev)
1530 {
1531 if (is_mt7628(dev))
1532 return mt7603_dma_debug(dev, 9) & BIT(9);
1533
1534 return mt7603_dma_debug(dev, 2) & BIT(8);
1535 }
1536
mt7603_rx_dma_busy(struct mt7603_dev * dev)1537 static bool mt7603_rx_dma_busy(struct mt7603_dev *dev)
1538 {
1539 if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_RX_DMA_BUSY))
1540 return false;
1541
1542 return mt7603_rx_fifo_busy(dev);
1543 }
1544
mt7603_tx_dma_busy(struct mt7603_dev * dev)1545 static bool mt7603_tx_dma_busy(struct mt7603_dev *dev)
1546 {
1547 u32 val;
1548
1549 if (!(mt76_rr(dev, MT_WPDMA_GLO_CFG) & MT_WPDMA_GLO_CFG_TX_DMA_BUSY))
1550 return false;
1551
1552 val = mt7603_dma_debug(dev, 9);
1553 return (val & BIT(8)) && (val & 0xf) != 0xf;
1554 }
1555
mt7603_tx_hang(struct mt7603_dev * dev)1556 static bool mt7603_tx_hang(struct mt7603_dev *dev)
1557 {
1558 struct mt76_queue *q;
1559 u32 dma_idx, prev_dma_idx;
1560 int i;
1561
1562 for (i = 0; i < 4; i++) {
1563 q = dev->mphy.q_tx[i];
1564
1565 if (!q->queued)
1566 continue;
1567
1568 prev_dma_idx = dev->tx_dma_idx[i];
1569 dma_idx = readl(&q->regs->dma_idx);
1570 dev->tx_dma_idx[i] = dma_idx;
1571
1572 if (dma_idx == prev_dma_idx &&
1573 dma_idx != readl(&q->regs->cpu_idx))
1574 break;
1575 }
1576
1577 return i < 4;
1578 }
1579
mt7603_rx_pse_busy(struct mt7603_dev * dev)1580 static bool mt7603_rx_pse_busy(struct mt7603_dev *dev)
1581 {
1582 u32 addr, val;
1583
1584 if (mt7603_rx_fifo_busy(dev))
1585 goto out;
1586
1587 addr = mt7603_reg_map(dev, MT_CLIENT_BASE_PHYS_ADDR + MT_CLIENT_STATUS);
1588 mt76_wr(dev, addr, 3);
1589 val = mt76_rr(dev, addr) >> 16;
1590
1591 if (!(val & BIT(0)))
1592 return false;
1593
1594 if (is_mt7628(dev))
1595 val &= 0xa000;
1596 else
1597 val &= 0x8000;
1598 if (!val)
1599 return false;
1600
1601 out:
1602 if (mt76_rr(dev, MT_INT_SOURCE_CSR) &
1603 (MT_INT_RX_DONE(0) | MT_INT_RX_DONE(1)))
1604 return false;
1605
1606 return true;
1607 }
1608
1609 static bool
mt7603_watchdog_check(struct mt7603_dev * dev,u8 * counter,enum mt7603_reset_cause cause,bool (* check)(struct mt7603_dev * dev))1610 mt7603_watchdog_check(struct mt7603_dev *dev, u8 *counter,
1611 enum mt7603_reset_cause cause,
1612 bool (*check)(struct mt7603_dev *dev))
1613 {
1614 if (dev->reset_test == cause + 1) {
1615 dev->reset_test = 0;
1616 goto trigger;
1617 }
1618
1619 if (check) {
1620 if (!check(dev) && *counter < MT7603_WATCHDOG_TIMEOUT) {
1621 *counter = 0;
1622 return false;
1623 }
1624
1625 (*counter)++;
1626 }
1627
1628 if (*counter < MT7603_WATCHDOG_TIMEOUT)
1629 return false;
1630 trigger:
1631 dev->cur_reset_cause = cause;
1632 dev->reset_cause[cause]++;
1633 return true;
1634 }
1635
mt7603_update_channel(struct mt76_phy * mphy)1636 void mt7603_update_channel(struct mt76_phy *mphy)
1637 {
1638 struct mt7603_dev *dev = container_of(mphy->dev, struct mt7603_dev, mt76);
1639 struct mt76_channel_state *state;
1640
1641 state = mphy->chan_state;
1642 state->cc_busy += mt76_rr(dev, MT_MIB_STAT_CCA);
1643 }
1644
1645 void
mt7603_edcca_set_strict(struct mt7603_dev * dev,bool val)1646 mt7603_edcca_set_strict(struct mt7603_dev *dev, bool val)
1647 {
1648 u32 rxtd_6 = 0xd7c80000;
1649
1650 if (val == dev->ed_strict_mode)
1651 return;
1652
1653 dev->ed_strict_mode = val;
1654
1655 /* Ensure that ED/CCA does not trigger if disabled */
1656 if (!dev->ed_monitor)
1657 rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x34);
1658 else
1659 rxtd_6 |= FIELD_PREP(MT_RXTD_6_CCAED_TH, 0x7d);
1660
1661 if (dev->ed_monitor && !dev->ed_strict_mode)
1662 rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x0f);
1663 else
1664 rxtd_6 |= FIELD_PREP(MT_RXTD_6_ACI_TH, 0x10);
1665
1666 mt76_wr(dev, MT_RXTD(6), rxtd_6);
1667
1668 mt76_rmw_field(dev, MT_RXTD(13), MT_RXTD_13_ACI_TH_EN,
1669 dev->ed_monitor && !dev->ed_strict_mode);
1670 }
1671
1672 static void
mt7603_edcca_check(struct mt7603_dev * dev)1673 mt7603_edcca_check(struct mt7603_dev *dev)
1674 {
1675 u32 val = mt76_rr(dev, MT_AGC(41));
1676 ktime_t cur_time;
1677 int rssi0, rssi1;
1678 u32 active;
1679 u32 ed_busy;
1680
1681 if (!dev->ed_monitor)
1682 return;
1683
1684 rssi0 = FIELD_GET(MT_AGC_41_RSSI_0, val);
1685 if (rssi0 > 128)
1686 rssi0 -= 256;
1687
1688 if (dev->mphy.antenna_mask & BIT(1)) {
1689 rssi1 = FIELD_GET(MT_AGC_41_RSSI_1, val);
1690 if (rssi1 > 128)
1691 rssi1 -= 256;
1692 } else {
1693 rssi1 = rssi0;
1694 }
1695
1696 if (max(rssi0, rssi1) >= -40 &&
1697 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH)
1698 dev->ed_strong_signal++;
1699 else if (dev->ed_strong_signal > 0)
1700 dev->ed_strong_signal--;
1701
1702 cur_time = ktime_get_boottime();
1703 ed_busy = mt76_rr(dev, MT_MIB_STAT_ED) & MT_MIB_STAT_ED_MASK;
1704
1705 active = ktime_to_us(ktime_sub(cur_time, dev->ed_time));
1706 dev->ed_time = cur_time;
1707
1708 if (!active)
1709 return;
1710
1711 if (100 * ed_busy / active > 90) {
1712 if (dev->ed_trigger < 0)
1713 dev->ed_trigger = 0;
1714 dev->ed_trigger++;
1715 } else {
1716 if (dev->ed_trigger > 0)
1717 dev->ed_trigger = 0;
1718 dev->ed_trigger--;
1719 }
1720
1721 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH ||
1722 dev->ed_strong_signal < MT7603_EDCCA_BLOCK_TH / 2) {
1723 mt7603_edcca_set_strict(dev, true);
1724 } else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH) {
1725 mt7603_edcca_set_strict(dev, false);
1726 }
1727
1728 if (dev->ed_trigger > MT7603_EDCCA_BLOCK_TH)
1729 dev->ed_trigger = MT7603_EDCCA_BLOCK_TH;
1730 else if (dev->ed_trigger < -MT7603_EDCCA_BLOCK_TH)
1731 dev->ed_trigger = -MT7603_EDCCA_BLOCK_TH;
1732 }
1733
mt7603_cca_stats_reset(struct mt7603_dev * dev)1734 void mt7603_cca_stats_reset(struct mt7603_dev *dev)
1735 {
1736 mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET);
1737 mt76_clear(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_RESET);
1738 mt76_set(dev, MT_PHYCTRL(2), MT_PHYCTRL_2_STATUS_EN);
1739 }
1740
1741 static void
mt7603_adjust_sensitivity(struct mt7603_dev * dev)1742 mt7603_adjust_sensitivity(struct mt7603_dev *dev)
1743 {
1744 u32 agc0 = dev->agc0, agc3 = dev->agc3;
1745 u32 adj;
1746
1747 if (!dev->sensitivity || dev->sensitivity < -100) {
1748 dev->sensitivity = 0;
1749 } else if (dev->sensitivity <= -84) {
1750 adj = 7 + (dev->sensitivity + 92) / 2;
1751
1752 agc0 = 0x56f0076f;
1753 agc0 |= adj << 12;
1754 agc0 |= adj << 16;
1755 agc3 = 0x81d0d5e3;
1756 } else if (dev->sensitivity <= -72) {
1757 adj = 7 + (dev->sensitivity + 80) / 2;
1758
1759 agc0 = 0x6af0006f;
1760 agc0 |= adj << 8;
1761 agc0 |= adj << 12;
1762 agc0 |= adj << 16;
1763
1764 agc3 = 0x8181d5e3;
1765 } else {
1766 if (dev->sensitivity > -54)
1767 dev->sensitivity = -54;
1768
1769 adj = 7 + (dev->sensitivity + 80) / 2;
1770
1771 agc0 = 0x7ff0000f;
1772 agc0 |= adj << 4;
1773 agc0 |= adj << 8;
1774 agc0 |= adj << 12;
1775 agc0 |= adj << 16;
1776
1777 agc3 = 0x818181e3;
1778 }
1779
1780 mt76_wr(dev, MT_AGC(0), agc0);
1781 mt76_wr(dev, MT_AGC1(0), agc0);
1782
1783 mt76_wr(dev, MT_AGC(3), agc3);
1784 mt76_wr(dev, MT_AGC1(3), agc3);
1785 }
1786
1787 static void
mt7603_false_cca_check(struct mt7603_dev * dev)1788 mt7603_false_cca_check(struct mt7603_dev *dev)
1789 {
1790 int pd_cck, pd_ofdm, mdrdy_cck, mdrdy_ofdm;
1791 int false_cca;
1792 int min_signal;
1793 u32 val;
1794
1795 if (!dev->dynamic_sensitivity)
1796 return;
1797
1798 val = mt76_rr(dev, MT_PHYCTRL_STAT_PD);
1799 pd_cck = FIELD_GET(MT_PHYCTRL_STAT_PD_CCK, val);
1800 pd_ofdm = FIELD_GET(MT_PHYCTRL_STAT_PD_OFDM, val);
1801
1802 val = mt76_rr(dev, MT_PHYCTRL_STAT_MDRDY);
1803 mdrdy_cck = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_CCK, val);
1804 mdrdy_ofdm = FIELD_GET(MT_PHYCTRL_STAT_MDRDY_OFDM, val);
1805
1806 dev->false_cca_ofdm = pd_ofdm - mdrdy_ofdm;
1807 dev->false_cca_cck = pd_cck - mdrdy_cck;
1808
1809 mt7603_cca_stats_reset(dev);
1810
1811 min_signal = mt76_get_min_avg_rssi(&dev->mt76, 0);
1812 if (!min_signal) {
1813 dev->sensitivity = 0;
1814 dev->last_cca_adj = jiffies;
1815 goto out;
1816 }
1817
1818 min_signal -= 15;
1819
1820 false_cca = dev->false_cca_ofdm + dev->false_cca_cck;
1821 if (false_cca > 600 &&
1822 dev->sensitivity < -100 + dev->sensitivity_limit) {
1823 if (!dev->sensitivity)
1824 dev->sensitivity = -92;
1825 else
1826 dev->sensitivity += 2;
1827 dev->last_cca_adj = jiffies;
1828 } else if (false_cca < 100 ||
1829 time_after(jiffies, dev->last_cca_adj + 10 * HZ)) {
1830 dev->last_cca_adj = jiffies;
1831 if (!dev->sensitivity)
1832 goto out;
1833
1834 dev->sensitivity -= 2;
1835 }
1836
1837 if (dev->sensitivity && dev->sensitivity > min_signal) {
1838 dev->sensitivity = min_signal;
1839 dev->last_cca_adj = jiffies;
1840 }
1841
1842 out:
1843 mt7603_adjust_sensitivity(dev);
1844 }
1845
1846 /*
1847 * Releasing buffered frames turns off the PSE redirect for a station, since
1848 * the released frames would otherwise be looped back into the driver PS queue
1849 * again. mac80211 never tells us when the service period is over, so hardware
1850 * buffering has to be re-armed here for every station that is still known to
1851 * be asleep. Waiting for the PSD queue to drain makes sure that the released
1852 * frames have already passed the redirect stage.
1853 */
1854 static void
mt7603_mac_ps_check(struct mt7603_dev * dev)1855 mt7603_mac_ps_check(struct mt7603_dev *dev)
1856 {
1857 int i;
1858
1859 if (dev->mphy.q_tx[MT_TXQ_PSD]->queued)
1860 return;
1861
1862 rcu_read_lock();
1863 for (i = 0; i < MT7603_WTBL_STA; i++) {
1864 struct mt76_wcid *wcid = mt76_wcid_ptr(dev, i);
1865 struct mt7603_sta *msta;
1866
1867 if (!wcid || !wcid->sta)
1868 continue;
1869
1870 msta = container_of(wcid, struct mt7603_sta, wcid);
1871 if (msta->ps || !msta->ps_sleeping)
1872 continue;
1873
1874 mt7603_wtbl_restore_ps(dev, msta);
1875 }
1876 rcu_read_unlock();
1877 }
1878
mt7603_mac_work(struct work_struct * work)1879 void mt7603_mac_work(struct work_struct *work)
1880 {
1881 struct mt7603_dev *dev = container_of(work, struct mt7603_dev,
1882 mphy.mac_work.work);
1883 bool reset = false;
1884 int i, idx;
1885
1886 mt76_tx_status_check(&dev->mt76, false);
1887
1888 mutex_lock(&dev->mt76.mutex);
1889
1890 dev->mphy.mac_work_count++;
1891 mt76_update_survey(&dev->mphy);
1892 mt7603_edcca_check(dev);
1893 mt7603_mac_ps_check(dev);
1894
1895 for (i = 0, idx = 0; i < 2; i++) {
1896 u32 val = mt76_rr(dev, MT_TX_AGG_CNT(i));
1897
1898 dev->mphy.aggr_stats[idx++] += val & 0xffff;
1899 dev->mphy.aggr_stats[idx++] += val >> 16;
1900 }
1901
1902 if (dev->mphy.mac_work_count == 10)
1903 mt7603_false_cca_check(dev);
1904
1905 if (mt7603_watchdog_check(dev, &dev->rx_pse_check,
1906 RESET_CAUSE_RX_PSE_BUSY,
1907 mt7603_rx_pse_busy) ||
1908 mt7603_watchdog_check(dev, &dev->beacon_check,
1909 RESET_CAUSE_BEACON_STUCK,
1910 NULL) ||
1911 mt7603_watchdog_check(dev, &dev->tx_hang_check,
1912 RESET_CAUSE_TX_HANG,
1913 mt7603_tx_hang) ||
1914 mt7603_watchdog_check(dev, &dev->tx_dma_check,
1915 RESET_CAUSE_TX_BUSY,
1916 mt7603_tx_dma_busy) ||
1917 mt7603_watchdog_check(dev, &dev->rx_dma_check,
1918 RESET_CAUSE_RX_BUSY,
1919 mt7603_rx_dma_busy) ||
1920 mt7603_watchdog_check(dev, &dev->mcu_hang,
1921 RESET_CAUSE_MCU_HANG,
1922 NULL) ||
1923 dev->reset_cause[RESET_CAUSE_RESET_FAILED]) {
1924 dev->beacon_check = 0;
1925 dev->tx_dma_check = 0;
1926 dev->tx_hang_check = 0;
1927 dev->rx_dma_check = 0;
1928 dev->rx_pse_check = 0;
1929 dev->mcu_hang = 0;
1930 dev->rx_dma_idx = ~0;
1931 memset(dev->tx_dma_idx, 0xff, sizeof(dev->tx_dma_idx));
1932 reset = true;
1933 dev->mphy.mac_work_count = 0;
1934 }
1935
1936 if (dev->mphy.mac_work_count >= 10)
1937 dev->mphy.mac_work_count = 0;
1938
1939 mutex_unlock(&dev->mt76.mutex);
1940
1941 if (reset)
1942 mt7603_mac_watchdog_reset(dev);
1943
1944 ieee80211_queue_delayed_work(mt76_hw(dev), &dev->mphy.mac_work,
1945 msecs_to_jiffies(MT7603_WATCHDOG_TIME));
1946 }
1947