1 // SPDX-License-Identifier: GPL-2.0 2 /* Marvell RVU Physical Function ethernet driver 3 * 4 * Copyright (C) 2020 Marvell. 5 * 6 */ 7 8 #include <linux/module.h> 9 #include <linux/interrupt.h> 10 #include <linux/pci.h> 11 #include <linux/etherdevice.h> 12 #include <linux/of.h> 13 #include <linux/if_vlan.h> 14 #include <linux/iommu.h> 15 #include <net/ip.h> 16 #include <linux/bpf.h> 17 #include <linux/bpf_trace.h> 18 #include <linux/bitfield.h> 19 #include <net/page_pool/types.h> 20 21 #include "otx2_reg.h" 22 #include "otx2_common.h" 23 #include "otx2_txrx.h" 24 #include "otx2_struct.h" 25 #include "otx2_ptp.h" 26 #include "cn10k.h" 27 #include "qos.h" 28 #include <rvu_trace.h> 29 #include "cn10k_ipsec.h" 30 #include "otx2_xsk.h" 31 32 #define DRV_NAME "rvu_nicpf" 33 #define DRV_STRING "Marvell RVU NIC Physical Function Driver" 34 35 /* Supported devices */ 36 static const struct pci_device_id otx2_pf_id_table[] = { 37 { PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_PF) }, 38 { 0, } /* end of table */ 39 }; 40 41 MODULE_AUTHOR("Sunil Goutham <sgoutham@marvell.com>"); 42 MODULE_DESCRIPTION(DRV_STRING); 43 MODULE_LICENSE("GPL v2"); 44 MODULE_DEVICE_TABLE(pci, otx2_pf_id_table); 45 46 static void otx2_vf_link_event_task(struct work_struct *work); 47 48 enum { 49 TYPE_PFAF, 50 TYPE_PFVF, 51 }; 52 53 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable); 54 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable); 55 56 static int otx2_change_mtu(struct net_device *netdev, int new_mtu) 57 { 58 struct otx2_nic *pf = netdev_priv(netdev); 59 bool if_up = netif_running(netdev); 60 int err = 0; 61 62 if (pf->xdp_prog && new_mtu > MAX_XDP_MTU) { 63 netdev_warn(netdev, "Jumbo frames not yet supported with XDP, current MTU %d.\n", 64 netdev->mtu); 65 return -EINVAL; 66 } 67 if (if_up) 68 otx2_stop(netdev); 69 70 netdev_info(netdev, "Changing MTU from %d to %d\n", 71 netdev->mtu, new_mtu); 72 WRITE_ONCE(netdev->mtu, new_mtu); 73 74 if (if_up) 75 err = otx2_open(netdev); 76 77 return err; 78 } 79 80 static void otx2_disable_flr_me_intr(struct otx2_nic *pf) 81 { 82 int irq, vfs = pf->total_vfs; 83 84 /* Disable VFs ME interrupts */ 85 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(0), INTR_MASK(vfs)); 86 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0); 87 free_irq(irq, pf); 88 89 /* Disable VFs FLR interrupts */ 90 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(0), INTR_MASK(vfs)); 91 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0); 92 free_irq(irq, pf); 93 94 if (vfs <= 64) 95 return; 96 97 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 98 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME1); 99 free_irq(irq, pf); 100 101 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(1), INTR_MASK(vfs - 64)); 102 irq = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR1); 103 free_irq(irq, pf); 104 } 105 106 static void otx2_flr_wq_destroy(struct otx2_nic *pf) 107 { 108 if (!pf->flr_wq) 109 return; 110 destroy_workqueue(pf->flr_wq); 111 pf->flr_wq = NULL; 112 devm_kfree(pf->dev, pf->flr_wrk); 113 } 114 115 static void otx2_flr_handler(struct work_struct *work) 116 { 117 struct flr_work *flrwork = container_of(work, struct flr_work, work); 118 struct otx2_nic *pf = flrwork->pf; 119 struct mbox *mbox = &pf->mbox; 120 struct msg_req *req; 121 int vf, reg = 0; 122 123 vf = flrwork - pf->flr_wrk; 124 125 mutex_lock(&mbox->lock); 126 req = otx2_mbox_alloc_msg_vf_flr(mbox); 127 if (!req) { 128 mutex_unlock(&mbox->lock); 129 return; 130 } 131 req->hdr.pcifunc &= RVU_PFVF_FUNC_MASK; 132 req->hdr.pcifunc |= (vf + 1) & RVU_PFVF_FUNC_MASK; 133 134 if (!otx2_sync_mbox_msg(&pf->mbox)) { 135 if (vf >= 64) { 136 reg = 1; 137 vf = vf - 64; 138 } 139 /* clear transcation pending bit */ 140 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 141 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(reg), BIT_ULL(vf)); 142 } 143 144 mutex_unlock(&mbox->lock); 145 } 146 147 static irqreturn_t otx2_pf_flr_intr_handler(int irq, void *pf_irq) 148 { 149 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 150 int reg, dev, vf, start_vf, num_reg = 1; 151 u64 intr; 152 153 if (pf->total_vfs > 64) 154 num_reg = 2; 155 156 for (reg = 0; reg < num_reg; reg++) { 157 intr = otx2_read64(pf, RVU_PF_VFFLR_INTX(reg)); 158 if (!intr) 159 continue; 160 start_vf = 64 * reg; 161 for (vf = 0; vf < 64; vf++) { 162 if (!(intr & BIT_ULL(vf))) 163 continue; 164 dev = vf + start_vf; 165 queue_work(pf->flr_wq, &pf->flr_wrk[dev].work); 166 /* Clear interrupt */ 167 otx2_write64(pf, RVU_PF_VFFLR_INTX(reg), BIT_ULL(vf)); 168 /* Disable the interrupt */ 169 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1CX(reg), 170 BIT_ULL(vf)); 171 } 172 } 173 return IRQ_HANDLED; 174 } 175 176 static irqreturn_t otx2_pf_me_intr_handler(int irq, void *pf_irq) 177 { 178 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 179 int vf, reg, num_reg = 1; 180 u64 intr; 181 182 if (pf->total_vfs > 64) 183 num_reg = 2; 184 185 for (reg = 0; reg < num_reg; reg++) { 186 intr = otx2_read64(pf, RVU_PF_VFME_INTX(reg)); 187 if (!intr) 188 continue; 189 for (vf = 0; vf < 64; vf++) { 190 if (!(intr & BIT_ULL(vf))) 191 continue; 192 /* clear trpend bit */ 193 otx2_write64(pf, RVU_PF_VFTRPENDX(reg), BIT_ULL(vf)); 194 /* clear interrupt */ 195 otx2_write64(pf, RVU_PF_VFME_INTX(reg), BIT_ULL(vf)); 196 } 197 } 198 return IRQ_HANDLED; 199 } 200 201 static int otx2_register_flr_me_intr(struct otx2_nic *pf, int numvfs) 202 { 203 struct otx2_hw *hw = &pf->hw; 204 char *irq_name; 205 int ret; 206 207 /* Register ME interrupt handler*/ 208 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME0 * NAME_SIZE]; 209 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME0", 210 rvu_get_pf(pf->pdev, pf->pcifunc)); 211 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFME0), 212 otx2_pf_me_intr_handler, 0, irq_name, pf); 213 if (ret) { 214 dev_err(pf->dev, 215 "RVUPF: IRQ registration failed for ME0\n"); 216 } 217 218 /* Register FLR interrupt handler */ 219 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR0 * NAME_SIZE]; 220 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR0", 221 rvu_get_pf(pf->pdev, pf->pcifunc)); 222 ret = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFFLR0), 223 otx2_pf_flr_intr_handler, 0, irq_name, pf); 224 if (ret) { 225 dev_err(pf->dev, 226 "RVUPF: IRQ registration failed for FLR0\n"); 227 return ret; 228 } 229 230 if (numvfs > 64) { 231 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFME1 * NAME_SIZE]; 232 snprintf(irq_name, NAME_SIZE, "RVUPF%d_ME1", 233 rvu_get_pf(pf->pdev, pf->pcifunc)); 234 ret = request_irq(pci_irq_vector 235 (pf->pdev, RVU_PF_INT_VEC_VFME1), 236 otx2_pf_me_intr_handler, 0, irq_name, pf); 237 if (ret) { 238 dev_err(pf->dev, 239 "RVUPF: IRQ registration failed for ME1\n"); 240 } 241 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFFLR1 * NAME_SIZE]; 242 snprintf(irq_name, NAME_SIZE, "RVUPF%d_FLR1", 243 rvu_get_pf(pf->pdev, pf->pcifunc)); 244 ret = request_irq(pci_irq_vector 245 (pf->pdev, RVU_PF_INT_VEC_VFFLR1), 246 otx2_pf_flr_intr_handler, 0, irq_name, pf); 247 if (ret) { 248 dev_err(pf->dev, 249 "RVUPF: IRQ registration failed for FLR1\n"); 250 return ret; 251 } 252 } 253 254 /* Enable ME interrupt for all VFs*/ 255 otx2_write64(pf, RVU_PF_VFME_INTX(0), INTR_MASK(numvfs)); 256 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 257 258 /* Enable FLR interrupt for all VFs*/ 259 otx2_write64(pf, RVU_PF_VFFLR_INTX(0), INTR_MASK(numvfs)); 260 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 261 262 if (numvfs > 64) { 263 numvfs -= 64; 264 265 otx2_write64(pf, RVU_PF_VFME_INTX(1), INTR_MASK(numvfs)); 266 otx2_write64(pf, RVU_PF_VFME_INT_ENA_W1SX(1), 267 INTR_MASK(numvfs)); 268 269 otx2_write64(pf, RVU_PF_VFFLR_INTX(1), INTR_MASK(numvfs)); 270 otx2_write64(pf, RVU_PF_VFFLR_INT_ENA_W1SX(1), 271 INTR_MASK(numvfs)); 272 } 273 return 0; 274 } 275 276 static int otx2_pf_flr_init(struct otx2_nic *pf, int num_vfs) 277 { 278 int vf; 279 280 pf->flr_wq = alloc_ordered_workqueue("otx2_pf_flr_wq", WQ_HIGHPRI); 281 if (!pf->flr_wq) 282 return -ENOMEM; 283 284 pf->flr_wrk = devm_kcalloc(pf->dev, num_vfs, 285 sizeof(struct flr_work), GFP_KERNEL); 286 if (!pf->flr_wrk) { 287 destroy_workqueue(pf->flr_wq); 288 return -ENOMEM; 289 } 290 291 for (vf = 0; vf < num_vfs; vf++) { 292 pf->flr_wrk[vf].pf = pf; 293 INIT_WORK(&pf->flr_wrk[vf].work, otx2_flr_handler); 294 } 295 296 return 0; 297 } 298 299 void otx2_queue_vf_work(struct mbox *mw, struct workqueue_struct *mbox_wq, 300 int first, int mdevs, u64 intr) 301 { 302 struct otx2_mbox_dev *mdev; 303 struct otx2_mbox *mbox; 304 struct mbox_hdr *hdr; 305 int i; 306 307 for (i = first; i < mdevs; i++) { 308 /* start from 0 */ 309 if (!(intr & BIT_ULL(i - first))) 310 continue; 311 312 mbox = &mw->mbox; 313 mdev = &mbox->dev[i]; 314 hdr = mdev->mbase + mbox->rx_start; 315 /* The hdr->num_msgs is set to zero immediately in the interrupt 316 * handler to ensure that it holds a correct value next time 317 * when the interrupt handler is called. pf->mw[i].num_msgs 318 * holds the data for use in otx2_pfvf_mbox_handler and 319 * pf->mw[i].up_num_msgs holds the data for use in 320 * otx2_pfvf_mbox_up_handler. 321 */ 322 if (hdr->num_msgs) { 323 mw[i].num_msgs = hdr->num_msgs; 324 hdr->num_msgs = 0; 325 queue_work(mbox_wq, &mw[i].mbox_wrk); 326 } 327 328 mbox = &mw->mbox_up; 329 mdev = &mbox->dev[i]; 330 hdr = mdev->mbase + mbox->rx_start; 331 if (hdr->num_msgs) { 332 mw[i].up_num_msgs = hdr->num_msgs; 333 hdr->num_msgs = 0; 334 queue_work(mbox_wq, &mw[i].mbox_up_wrk); 335 } 336 } 337 } 338 339 static void otx2_forward_msg_pfvf(struct otx2_mbox_dev *mdev, 340 struct otx2_mbox *pfvf_mbox, void *bbuf_base, 341 int devid) 342 { 343 struct otx2_mbox_dev *src_mdev = mdev; 344 int offset; 345 346 /* Msgs are already copied, trigger VF's mbox irq */ 347 smp_wmb(); 348 349 otx2_mbox_wait_for_zero(pfvf_mbox, devid); 350 351 offset = pfvf_mbox->trigger | (devid << pfvf_mbox->tr_shift); 352 writeq(MBOX_DOWN_MSG, (void __iomem *)pfvf_mbox->reg_base + offset); 353 354 /* Restore VF's mbox bounce buffer region address */ 355 src_mdev->mbase = bbuf_base; 356 } 357 358 static int otx2_forward_vf_mbox_msgs(struct otx2_nic *pf, 359 struct otx2_mbox *src_mbox, 360 int dir, int vf, int num_msgs) 361 { 362 struct otx2_mbox_dev *src_mdev, *dst_mdev; 363 struct mbox_hdr *mbox_hdr; 364 struct mbox_hdr *req_hdr; 365 struct mbox *dst_mbox; 366 int dst_size, err; 367 368 if (dir == MBOX_DIR_PFAF) { 369 /* Set VF's mailbox memory as PF's bounce buffer memory, so 370 * that explicit copying of VF's msgs to PF=>AF mbox region 371 * and AF=>PF responses to VF's mbox region can be avoided. 372 */ 373 src_mdev = &src_mbox->dev[vf]; 374 mbox_hdr = src_mbox->hwbase + 375 src_mbox->rx_start + (vf * MBOX_SIZE); 376 377 dst_mbox = &pf->mbox; 378 dst_size = dst_mbox->mbox.tx_size - 379 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 380 /* Check if msgs fit into destination area and has valid size */ 381 if (mbox_hdr->msg_size > dst_size || !mbox_hdr->msg_size) 382 return -EINVAL; 383 384 dst_mdev = &dst_mbox->mbox.dev[0]; 385 386 mutex_lock(&pf->mbox.lock); 387 dst_mdev->mbase = src_mdev->mbase; 388 dst_mdev->msg_size = mbox_hdr->msg_size; 389 dst_mdev->num_msgs = num_msgs; 390 err = otx2_sync_mbox_msg(dst_mbox); 391 /* Error code -EIO indicate there is a communication failure 392 * to the AF. Rest of the error codes indicate that AF processed 393 * VF messages and set the error codes in response messages 394 * (if any) so simply forward responses to VF. 395 */ 396 if (err == -EIO) { 397 dev_warn(pf->dev, 398 "AF not responding to VF%d messages\n", vf); 399 /* restore PF mbase and exit */ 400 dst_mdev->mbase = pf->mbox.bbuf_base; 401 mutex_unlock(&pf->mbox.lock); 402 return err; 403 } 404 /* At this point, all the VF messages sent to AF are acked 405 * with proper responses and responses are copied to VF 406 * mailbox hence raise interrupt to VF. 407 */ 408 req_hdr = (struct mbox_hdr *)(dst_mdev->mbase + 409 dst_mbox->mbox.rx_start); 410 req_hdr->num_msgs = num_msgs; 411 412 otx2_forward_msg_pfvf(dst_mdev, &pf->mbox_pfvf[0].mbox, 413 pf->mbox.bbuf_base, vf); 414 mutex_unlock(&pf->mbox.lock); 415 } else if (dir == MBOX_DIR_PFVF_UP) { 416 src_mdev = &src_mbox->dev[0]; 417 mbox_hdr = src_mbox->hwbase + src_mbox->rx_start; 418 req_hdr = (struct mbox_hdr *)(src_mdev->mbase + 419 src_mbox->rx_start); 420 req_hdr->num_msgs = num_msgs; 421 422 dst_mbox = &pf->mbox_pfvf[0]; 423 dst_size = dst_mbox->mbox_up.tx_size - 424 ALIGN(sizeof(*mbox_hdr), MBOX_MSG_ALIGN); 425 /* Check if msgs fit into destination area */ 426 if (mbox_hdr->msg_size > dst_size) 427 return -EINVAL; 428 429 dst_mdev = &dst_mbox->mbox_up.dev[vf]; 430 dst_mdev->mbase = src_mdev->mbase; 431 dst_mdev->msg_size = mbox_hdr->msg_size; 432 dst_mdev->num_msgs = mbox_hdr->num_msgs; 433 err = otx2_sync_mbox_up_msg(dst_mbox, vf); 434 if (err) { 435 dev_warn(pf->dev, 436 "VF%d is not responding to mailbox\n", vf); 437 return err; 438 } 439 } else if (dir == MBOX_DIR_VFPF_UP) { 440 req_hdr = (struct mbox_hdr *)(src_mbox->dev[0].mbase + 441 src_mbox->rx_start); 442 req_hdr->num_msgs = num_msgs; 443 otx2_forward_msg_pfvf(&pf->mbox_pfvf->mbox_up.dev[vf], 444 &pf->mbox.mbox_up, 445 pf->mbox_pfvf[vf].bbuf_base, 446 0); 447 } 448 449 return 0; 450 } 451 452 static void otx2_pfvf_mbox_handler(struct work_struct *work) 453 { 454 struct mbox_msghdr *msg = NULL; 455 int offset, vf_idx, id, err; 456 struct otx2_mbox_dev *mdev; 457 struct otx2_mbox *mbox; 458 struct mbox *vf_mbox; 459 struct otx2_nic *pf; 460 461 vf_mbox = container_of(work, struct mbox, mbox_wrk); 462 pf = vf_mbox->pfvf; 463 vf_idx = vf_mbox - pf->mbox_pfvf; 464 465 mbox = &pf->mbox_pfvf[0].mbox; 466 mdev = &mbox->dev[vf_idx]; 467 468 offset = ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 469 470 trace_otx2_msg_status(pf->pdev, "PF-VF down queue handler(forwarding)", 471 vf_mbox->num_msgs); 472 473 for (id = 0; id < vf_mbox->num_msgs; id++) { 474 msg = (struct mbox_msghdr *)(mdev->mbase + mbox->rx_start + 475 offset); 476 477 if (msg->sig != OTX2_MBOX_REQ_SIG) 478 goto inval_msg; 479 480 /* Set VF's number in each of the msg */ 481 msg->pcifunc &= ~RVU_PFVF_FUNC_MASK; 482 msg->pcifunc |= (vf_idx + 1) & RVU_PFVF_FUNC_MASK; 483 offset = msg->next_msgoff; 484 } 485 err = otx2_forward_vf_mbox_msgs(pf, mbox, MBOX_DIR_PFAF, vf_idx, 486 vf_mbox->num_msgs); 487 if (err) 488 goto inval_msg; 489 return; 490 491 inval_msg: 492 otx2_reply_invalid_msg(mbox, vf_idx, 0, msg->id); 493 otx2_mbox_msg_send(mbox, vf_idx); 494 } 495 496 static void otx2_pfvf_mbox_up_handler(struct work_struct *work) 497 { 498 struct mbox *vf_mbox = container_of(work, struct mbox, mbox_up_wrk); 499 struct otx2_nic *pf = vf_mbox->pfvf; 500 struct otx2_mbox_dev *mdev; 501 int offset, id, vf_idx = 0; 502 struct mbox_msghdr *msg; 503 struct otx2_mbox *mbox; 504 505 vf_idx = vf_mbox - pf->mbox_pfvf; 506 mbox = &pf->mbox_pfvf[0].mbox_up; 507 mdev = &mbox->dev[vf_idx]; 508 509 offset = mbox->rx_start + ALIGN(sizeof(struct mbox_hdr), MBOX_MSG_ALIGN); 510 511 trace_otx2_msg_status(pf->pdev, "PF-VF up queue handler(response)", 512 vf_mbox->up_num_msgs); 513 514 for (id = 0; id < vf_mbox->up_num_msgs; id++) { 515 msg = mdev->mbase + offset; 516 517 if (msg->id >= MBOX_MSG_MAX) { 518 dev_err(pf->dev, 519 "Mbox msg with unknown ID 0x%x\n", msg->id); 520 goto end; 521 } 522 523 if (msg->sig != OTX2_MBOX_RSP_SIG) { 524 dev_err(pf->dev, 525 "Mbox msg with wrong signature %x, ID 0x%x\n", 526 msg->sig, msg->id); 527 goto end; 528 } 529 530 switch (msg->id) { 531 case MBOX_MSG_CGX_LINK_EVENT: 532 case MBOX_MSG_REP_EVENT_UP_NOTIFY: 533 break; 534 default: 535 if (msg->rc) 536 dev_err(pf->dev, 537 "Mbox msg response has err %d, ID 0x%x\n", 538 msg->rc, msg->id); 539 break; 540 } 541 542 end: 543 offset = mbox->rx_start + msg->next_msgoff; 544 if (mdev->msgs_acked == (vf_mbox->up_num_msgs - 1)) 545 __otx2_mbox_reset(mbox, vf_idx); 546 mdev->msgs_acked++; 547 } 548 } 549 550 irqreturn_t otx2_pfvf_mbox_intr_handler(int irq, void *pf_irq) 551 { 552 struct otx2_nic *pf = (struct otx2_nic *)(pf_irq); 553 int vfs = pf->total_vfs; 554 struct mbox *mbox; 555 u64 intr; 556 557 mbox = pf->mbox_pfvf; 558 /* Handle VF interrupts */ 559 if (vfs > 64) { 560 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(1)); 561 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), intr); 562 otx2_queue_vf_work(mbox, pf->mbox_pfvf_wq, 64, vfs, intr); 563 if (intr) 564 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 565 vfs = 64; 566 } 567 568 intr = otx2_read64(pf, RVU_PF_VFPF_MBOX_INTX(0)); 569 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), intr); 570 571 otx2_queue_vf_work(mbox, pf->mbox_pfvf_wq, 0, vfs, intr); 572 573 if (intr) 574 trace_otx2_msg_interrupt(mbox->mbox.pdev, "VF(s) to PF", intr); 575 576 return IRQ_HANDLED; 577 } 578 579 static void *cn20k_pfvf_mbox_alloc(struct otx2_nic *pf, int numvfs) 580 { 581 struct qmem *mbox_addr; 582 int err; 583 584 err = qmem_alloc(&pf->pdev->dev, &mbox_addr, numvfs, MBOX_SIZE); 585 if (err) { 586 dev_err(pf->dev, "qmem alloc fail\n"); 587 return ERR_PTR(-ENOMEM); 588 } 589 590 otx2_write64(pf, RVU_PF_VF_MBOX_ADDR, (u64)mbox_addr->iova); 591 pf->pfvf_mbox_addr = mbox_addr; 592 593 return mbox_addr->base; 594 } 595 596 static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs) 597 { 598 void __iomem *hwbase; 599 struct mbox *mbox; 600 int err, vf; 601 u64 base; 602 603 if (!numvfs) 604 return -EINVAL; 605 606 pf->mbox_pfvf = devm_kcalloc(&pf->pdev->dev, numvfs, 607 sizeof(struct mbox), GFP_KERNEL); 608 if (!pf->mbox_pfvf) 609 return -ENOMEM; 610 611 pf->mbox_pfvf_wq = alloc_workqueue("otx2_pfvf_mailbox", 612 WQ_UNBOUND | WQ_HIGHPRI | 613 WQ_MEM_RECLAIM, 0); 614 if (!pf->mbox_pfvf_wq) 615 return -ENOMEM; 616 617 /* For CN20K, PF allocates mbox memory in DRAM and writes PF/VF 618 * regions/offsets in RVU_PF_VF_MBOX_ADDR, the RVU_PFX_FUNC_PFAF_MBOX 619 * gives the aliased address to access PF/VF mailbox regions. 620 */ 621 if (is_cn20k(pf->pdev)) { 622 hwbase = (void __iomem *)cn20k_pfvf_mbox_alloc(pf, numvfs); 623 } else { 624 /* On CN10K platform, PF <-> VF mailbox region follows after 625 * PF <-> AF mailbox region. 626 */ 627 if (test_bit(CN10K_MBOX, &pf->hw.cap_flag)) 628 base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) + 629 MBOX_SIZE; 630 else 631 base = readq(pf->reg_base + RVU_PF_VF_BAR4_ADDR); 632 633 hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs); 634 if (!hwbase) { 635 err = -ENOMEM; 636 goto free_wq; 637 } 638 } 639 640 mbox = &pf->mbox_pfvf[0]; 641 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 642 MBOX_DIR_PFVF, numvfs); 643 if (err) 644 goto free_iomem; 645 646 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 647 MBOX_DIR_PFVF_UP, numvfs); 648 if (err) 649 goto free_iomem; 650 651 for (vf = 0; vf < numvfs; vf++) { 652 mbox->pfvf = pf; 653 INIT_WORK(&mbox->mbox_wrk, otx2_pfvf_mbox_handler); 654 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfvf_mbox_up_handler); 655 mbox++; 656 } 657 658 return 0; 659 660 free_iomem: 661 if (hwbase && !(is_cn20k(pf->pdev))) 662 iounmap(hwbase); 663 free_wq: 664 destroy_workqueue(pf->mbox_pfvf_wq); 665 return err; 666 } 667 668 static void otx2_pfvf_mbox_destroy(struct otx2_nic *pf) 669 { 670 struct mbox *mbox = &pf->mbox_pfvf[0]; 671 672 if (!mbox) 673 return; 674 675 if (pf->mbox_pfvf_wq) { 676 destroy_workqueue(pf->mbox_pfvf_wq); 677 pf->mbox_pfvf_wq = NULL; 678 } 679 680 if (mbox->mbox.hwbase && !is_cn20k(pf->pdev)) 681 iounmap(mbox->mbox.hwbase); 682 else 683 qmem_free(&pf->pdev->dev, pf->pfvf_mbox_addr); 684 685 otx2_mbox_destroy(&mbox->mbox); 686 } 687 688 static void otx2_enable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 689 { 690 /* Clear PF <=> VF mailbox IRQ */ 691 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 692 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 693 694 /* Enable PF <=> VF mailbox IRQ */ 695 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(0), INTR_MASK(numvfs)); 696 if (numvfs > 64) { 697 numvfs -= 64; 698 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1SX(1), 699 INTR_MASK(numvfs)); 700 } 701 } 702 703 static void otx2_disable_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 704 { 705 int vector; 706 707 if (is_cn20k(pf->pdev)) 708 return cn20k_disable_pfvf_mbox_intr(pf, numvfs); 709 710 /* Disable PF <=> VF mailbox IRQ */ 711 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(0), ~0ull); 712 otx2_write64(pf, RVU_PF_VFPF_MBOX_INT_ENA_W1CX(1), ~0ull); 713 714 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(0), ~0ull); 715 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0); 716 free_irq(vector, pf); 717 718 if (numvfs > 64) { 719 otx2_write64(pf, RVU_PF_VFPF_MBOX_INTX(1), ~0ull); 720 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX1); 721 free_irq(vector, pf); 722 } 723 } 724 725 static int otx2_register_pfvf_mbox_intr(struct otx2_nic *pf, int numvfs) 726 { 727 struct otx2_hw *hw = &pf->hw; 728 char *irq_name; 729 int err; 730 731 if (is_cn20k(pf->pdev)) 732 return cn20k_register_pfvf_mbox_intr(pf, numvfs); 733 734 /* Register MBOX0 interrupt handler */ 735 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX0 * NAME_SIZE]; 736 if (pf->pcifunc) 737 snprintf(irq_name, NAME_SIZE, 738 "RVUPF%d_VF Mbox0", rvu_get_pf(pf->pdev, pf->pcifunc)); 739 else 740 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox0"); 741 err = request_irq(pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_VFPF_MBOX0), 742 otx2_pfvf_mbox_intr_handler, 0, irq_name, pf); 743 if (err) { 744 dev_err(pf->dev, 745 "RVUPF: IRQ registration failed for PFVF mbox0 irq\n"); 746 return err; 747 } 748 749 if (numvfs > 64) { 750 /* Register MBOX1 interrupt handler */ 751 irq_name = &hw->irq_name[RVU_PF_INT_VEC_VFPF_MBOX1 * NAME_SIZE]; 752 if (pf->pcifunc) 753 snprintf(irq_name, NAME_SIZE, 754 "RVUPF%d_VF Mbox1", 755 rvu_get_pf(pf->pdev, pf->pcifunc)); 756 else 757 snprintf(irq_name, NAME_SIZE, "RVUPF_VF Mbox1"); 758 err = request_irq(pci_irq_vector(pf->pdev, 759 RVU_PF_INT_VEC_VFPF_MBOX1), 760 otx2_pfvf_mbox_intr_handler, 761 0, irq_name, pf); 762 if (err) { 763 dev_err(pf->dev, 764 "RVUPF: IRQ registration failed for PFVF mbox1 irq\n"); 765 return err; 766 } 767 } 768 769 otx2_enable_pfvf_mbox_intr(pf, numvfs); 770 771 return 0; 772 } 773 774 static void otx2_process_pfaf_mbox_msg(struct otx2_nic *pf, 775 struct mbox_msghdr *msg) 776 { 777 int devid; 778 779 if (msg->id >= MBOX_MSG_MAX) { 780 dev_err(pf->dev, 781 "Mbox msg with unknown ID 0x%x\n", msg->id); 782 return; 783 } 784 785 if (msg->sig != OTX2_MBOX_RSP_SIG) { 786 dev_err(pf->dev, 787 "Mbox msg with wrong signature %x, ID 0x%x\n", 788 msg->sig, msg->id); 789 return; 790 } 791 792 /* message response heading VF */ 793 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 794 if (devid) { 795 struct otx2_vf_config *config = &pf->vf_configs[devid - 1]; 796 struct delayed_work *dwork; 797 798 switch (msg->id) { 799 case MBOX_MSG_NIX_LF_START_RX: 800 config->intf_down = false; 801 dwork = &config->link_event_work; 802 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 803 break; 804 case MBOX_MSG_NIX_LF_STOP_RX: 805 config->intf_down = true; 806 break; 807 } 808 809 return; 810 } 811 812 switch (msg->id) { 813 case MBOX_MSG_READY: 814 pf->pcifunc = msg->pcifunc; 815 break; 816 case MBOX_MSG_MSIX_OFFSET: 817 mbox_handler_msix_offset(pf, (struct msix_offset_rsp *)msg); 818 break; 819 case MBOX_MSG_NPA_LF_ALLOC: 820 mbox_handler_npa_lf_alloc(pf, (struct npa_lf_alloc_rsp *)msg); 821 break; 822 case MBOX_MSG_NIX_LF_ALLOC: 823 mbox_handler_nix_lf_alloc(pf, (struct nix_lf_alloc_rsp *)msg); 824 break; 825 case MBOX_MSG_NIX_BP_ENABLE: 826 mbox_handler_nix_bp_enable(pf, (struct nix_bp_cfg_rsp *)msg); 827 break; 828 case MBOX_MSG_CGX_STATS: 829 mbox_handler_cgx_stats(pf, (struct cgx_stats_rsp *)msg); 830 break; 831 case MBOX_MSG_CGX_FEC_STATS: 832 mbox_handler_cgx_fec_stats(pf, (struct cgx_fec_stats_rsp *)msg); 833 break; 834 default: 835 if (msg->rc) 836 dev_err(pf->dev, 837 "Mbox msg response has err %d, ID 0x%x\n", 838 msg->rc, msg->id); 839 break; 840 } 841 } 842 843 static void otx2_pfaf_mbox_handler(struct work_struct *work) 844 { 845 struct otx2_mbox_dev *mdev; 846 struct mbox_hdr *rsp_hdr; 847 struct mbox_msghdr *msg; 848 struct otx2_mbox *mbox; 849 struct mbox *af_mbox; 850 struct otx2_nic *pf; 851 int offset, id; 852 u16 num_msgs; 853 854 af_mbox = container_of(work, struct mbox, mbox_wrk); 855 mbox = &af_mbox->mbox; 856 mdev = &mbox->dev[0]; 857 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 858 num_msgs = rsp_hdr->num_msgs; 859 860 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 861 pf = af_mbox->pfvf; 862 863 trace_otx2_msg_status(pf->pdev, "PF-AF down queue handler(response)", 864 num_msgs); 865 866 for (id = 0; id < num_msgs; id++) { 867 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 868 otx2_process_pfaf_mbox_msg(pf, msg); 869 offset = mbox->rx_start + msg->next_msgoff; 870 if (mdev->msgs_acked == (num_msgs - 1)) 871 __otx2_mbox_reset(mbox, 0); 872 mdev->msgs_acked++; 873 } 874 875 } 876 877 static void otx2_handle_link_event(struct otx2_nic *pf) 878 { 879 struct cgx_link_user_info *linfo = &pf->linfo; 880 struct net_device *netdev = pf->netdev; 881 882 if (pf->flags & OTX2_FLAG_PORT_UP) 883 return; 884 885 pr_info("%s NIC Link is %s %d Mbps %s duplex\n", netdev->name, 886 linfo->link_up ? "UP" : "DOWN", linfo->speed, 887 linfo->full_duplex ? "Full" : "Half"); 888 if (linfo->link_up) { 889 netif_carrier_on(netdev); 890 netif_tx_start_all_queues(netdev); 891 } else { 892 netif_carrier_off(netdev); 893 netif_tx_stop_all_queues(netdev); 894 } 895 } 896 897 static int otx2_mbox_up_handler_rep_event_up_notify(struct otx2_nic *pf, 898 struct rep_event *info, 899 struct msg_rsp *rsp) 900 { 901 struct net_device *netdev = pf->netdev; 902 903 if (info->event == RVU_EVENT_MTU_CHANGE) { 904 netdev->mtu = info->evt_data.mtu; 905 return 0; 906 } 907 908 if (info->event == RVU_EVENT_PORT_STATE) { 909 if (info->evt_data.port_state) { 910 pf->flags |= OTX2_FLAG_PORT_UP; 911 netif_carrier_on(netdev); 912 netif_tx_start_all_queues(netdev); 913 } else { 914 pf->flags &= ~OTX2_FLAG_PORT_UP; 915 netif_tx_stop_all_queues(netdev); 916 netif_carrier_off(netdev); 917 } 918 return 0; 919 } 920 #ifdef CONFIG_RVU_ESWITCH 921 rvu_event_up_notify(pf, info); 922 #endif 923 return 0; 924 } 925 926 int otx2_mbox_up_handler_mcs_intr_notify(struct otx2_nic *pf, 927 struct mcs_intr_info *event, 928 struct msg_rsp *rsp) 929 { 930 cn10k_handle_mcs_event(pf, event); 931 932 return 0; 933 } 934 935 int otx2_mbox_up_handler_cgx_link_event(struct otx2_nic *pf, 936 struct cgx_link_info_msg *msg, 937 struct msg_rsp *rsp) 938 { 939 int i; 940 941 /* Copy the link info sent by AF */ 942 pf->linfo = msg->link_info; 943 944 /* notify VFs about link event */ 945 for (i = 0; i < pci_num_vf(pf->pdev); i++) { 946 struct otx2_vf_config *config = &pf->vf_configs[i]; 947 struct delayed_work *dwork = &config->link_event_work; 948 949 if (config->intf_down) 950 continue; 951 952 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 953 } 954 955 /* interface has not been fully configured yet */ 956 if (pf->flags & OTX2_FLAG_INTF_DOWN) 957 return 0; 958 959 otx2_handle_link_event(pf); 960 return 0; 961 } 962 EXPORT_SYMBOL(otx2_mbox_up_handler_cgx_link_event); 963 964 static int otx2_process_mbox_msg_up(struct otx2_nic *pf, 965 struct mbox_msghdr *req) 966 { 967 /* Check if valid, if not reply with a invalid msg */ 968 if (req->sig != OTX2_MBOX_REQ_SIG) { 969 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 970 return -ENODEV; 971 } 972 973 switch (req->id) { 974 #define M(_name, _id, _fn_name, _req_type, _rsp_type) \ 975 case _id: { \ 976 struct _rsp_type *rsp; \ 977 int err; \ 978 \ 979 rsp = (struct _rsp_type *)otx2_mbox_alloc_msg( \ 980 &pf->mbox.mbox_up, 0, \ 981 sizeof(struct _rsp_type)); \ 982 if (!rsp) \ 983 return -ENOMEM; \ 984 \ 985 rsp->hdr.id = _id; \ 986 rsp->hdr.sig = OTX2_MBOX_RSP_SIG; \ 987 rsp->hdr.pcifunc = 0; \ 988 rsp->hdr.rc = 0; \ 989 \ 990 err = otx2_mbox_up_handler_ ## _fn_name( \ 991 pf, (struct _req_type *)req, rsp); \ 992 return err; \ 993 } 994 MBOX_UP_CGX_MESSAGES 995 MBOX_UP_MCS_MESSAGES 996 MBOX_UP_REP_MESSAGES 997 #undef M 998 break; 999 default: 1000 otx2_reply_invalid_msg(&pf->mbox.mbox_up, 0, 0, req->id); 1001 return -ENODEV; 1002 } 1003 return 0; 1004 } 1005 1006 static void otx2_pfaf_mbox_up_handler(struct work_struct *work) 1007 { 1008 struct mbox *af_mbox = container_of(work, struct mbox, mbox_up_wrk); 1009 struct otx2_mbox *mbox = &af_mbox->mbox_up; 1010 struct otx2_mbox_dev *mdev = &mbox->dev[0]; 1011 struct otx2_nic *pf = af_mbox->pfvf; 1012 int offset, id, devid = 0; 1013 struct mbox_hdr *rsp_hdr; 1014 struct mbox_msghdr *msg; 1015 u16 num_msgs; 1016 1017 rsp_hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 1018 num_msgs = rsp_hdr->num_msgs; 1019 1020 offset = mbox->rx_start + ALIGN(sizeof(*rsp_hdr), MBOX_MSG_ALIGN); 1021 1022 trace_otx2_msg_status(pf->pdev, "PF-AF up queue handler(notification)", 1023 num_msgs); 1024 1025 for (id = 0; id < num_msgs; id++) { 1026 msg = (struct mbox_msghdr *)(mdev->mbase + offset); 1027 1028 devid = msg->pcifunc & RVU_PFVF_FUNC_MASK; 1029 /* Skip processing VF's messages */ 1030 if (!devid) 1031 otx2_process_mbox_msg_up(pf, msg); 1032 offset = mbox->rx_start + msg->next_msgoff; 1033 } 1034 /* Forward to VF iff VFs are really present */ 1035 if (devid && pci_num_vf(pf->pdev)) { 1036 otx2_forward_vf_mbox_msgs(pf, &pf->mbox.mbox_up, 1037 MBOX_DIR_PFVF_UP, devid - 1, 1038 num_msgs); 1039 return; 1040 } 1041 1042 otx2_mbox_msg_send(mbox, 0); 1043 } 1044 1045 irqreturn_t otx2_pfaf_mbox_intr_handler(int irq, void *pf_irq) 1046 { 1047 struct otx2_nic *pf = (struct otx2_nic *)pf_irq; 1048 struct mbox *mw = &pf->mbox; 1049 struct otx2_mbox_dev *mdev; 1050 struct otx2_mbox *mbox; 1051 struct mbox_hdr *hdr; 1052 u64 mbox_data; 1053 1054 /* Clear the IRQ */ 1055 otx2_write64(pf, RVU_PF_INT, BIT_ULL(0)); 1056 1057 mbox_data = otx2_read64(pf, RVU_PF_PFAF_MBOX0); 1058 1059 if (mbox_data & MBOX_UP_MSG) { 1060 mbox_data &= ~MBOX_UP_MSG; 1061 otx2_write64(pf, RVU_PF_PFAF_MBOX0, mbox_data); 1062 1063 mbox = &mw->mbox_up; 1064 mdev = &mbox->dev[0]; 1065 otx2_sync_mbox_bbuf(mbox, 0); 1066 1067 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 1068 if (hdr->num_msgs) 1069 queue_work(pf->mbox_wq, &mw->mbox_up_wrk); 1070 1071 trace_otx2_msg_interrupt(pf->pdev, "UP message from AF to PF", 1072 BIT_ULL(0)); 1073 1074 trace_otx2_msg_status(pf->pdev, "PF-AF up work queued(interrupt)", 1075 hdr->num_msgs); 1076 } 1077 1078 if (mbox_data & MBOX_DOWN_MSG) { 1079 mbox_data &= ~MBOX_DOWN_MSG; 1080 otx2_write64(pf, RVU_PF_PFAF_MBOX0, mbox_data); 1081 1082 mbox = &mw->mbox; 1083 mdev = &mbox->dev[0]; 1084 otx2_sync_mbox_bbuf(mbox, 0); 1085 1086 hdr = (struct mbox_hdr *)(mdev->mbase + mbox->rx_start); 1087 if (hdr->num_msgs) 1088 queue_work(pf->mbox_wq, &mw->mbox_wrk); 1089 1090 trace_otx2_msg_interrupt(pf->pdev, "DOWN reply from AF to PF", 1091 BIT_ULL(0)); 1092 1093 trace_otx2_msg_status(pf->pdev, "PF-AF down work queued(interrupt)", 1094 hdr->num_msgs); 1095 } 1096 1097 return IRQ_HANDLED; 1098 } 1099 1100 void otx2_disable_mbox_intr(struct otx2_nic *pf) 1101 { 1102 int vector; 1103 1104 /* Disable AF => PF mailbox IRQ */ 1105 if (!is_cn20k(pf->pdev)) { 1106 vector = pci_irq_vector(pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX); 1107 otx2_write64(pf, RVU_PF_INT_ENA_W1C, BIT_ULL(0)); 1108 } else { 1109 vector = pci_irq_vector(pf->pdev, 1110 RVU_MBOX_PF_INT_VEC_AFPF_MBOX); 1111 otx2_write64(pf, RVU_PF_INT_ENA_W1C, 1112 BIT_ULL(0) | BIT_ULL(1)); 1113 } 1114 free_irq(vector, pf); 1115 } 1116 EXPORT_SYMBOL(otx2_disable_mbox_intr); 1117 1118 int otx2_register_mbox_intr(struct otx2_nic *pf, bool probe_af) 1119 { 1120 struct otx2_hw *hw = &pf->hw; 1121 struct msg_req *req; 1122 u64 mbox_int_mask; 1123 char *irq_name; 1124 int err; 1125 1126 mbox_int_mask = !is_cn20k(pf->pdev) ? BIT_ULL(0) : 1127 BIT_ULL(0) | BIT_ULL(1); 1128 1129 /* Clear stale mailbox interrupt state before installing the handler. */ 1130 otx2_write64(pf, RVU_PF_INT, mbox_int_mask); 1131 1132 /* Register mailbox interrupt handler */ 1133 if (!is_cn20k(pf->pdev)) { 1134 irq_name = &hw->irq_name[RVU_PF_INT_VEC_AFPF_MBOX * NAME_SIZE]; 1135 snprintf(irq_name, NAME_SIZE, "RVUPF%d AFPF Mbox", 1136 rvu_get_pf(pf->pdev, pf->pcifunc)); 1137 err = request_irq(pci_irq_vector 1138 (pf->pdev, RVU_PF_INT_VEC_AFPF_MBOX), 1139 pf->hw_ops->pfaf_mbox_intr_handler, 1140 0, irq_name, pf); 1141 } else { 1142 irq_name = &hw->irq_name[RVU_MBOX_PF_INT_VEC_AFPF_MBOX * 1143 NAME_SIZE]; 1144 snprintf(irq_name, NAME_SIZE, "RVUPF%d AFPF Mbox", 1145 rvu_get_pf(pf->pdev, pf->pcifunc)); 1146 err = request_irq(pci_irq_vector 1147 (pf->pdev, RVU_MBOX_PF_INT_VEC_AFPF_MBOX), 1148 pf->hw_ops->pfaf_mbox_intr_handler, 1149 0, irq_name, pf); 1150 } 1151 if (err) { 1152 dev_err(pf->dev, 1153 "RVUPF: IRQ registration failed for PFAF mbox irq\n"); 1154 return err; 1155 } 1156 1157 /* Enable mailbox interrupt for msgs coming from AF. */ 1158 otx2_write64(pf, RVU_PF_INT_ENA_W1S, mbox_int_mask); 1159 1160 if (!probe_af) 1161 return 0; 1162 1163 /* Check mailbox communication with AF */ 1164 req = otx2_mbox_alloc_msg_ready(&pf->mbox); 1165 if (!req) { 1166 otx2_disable_mbox_intr(pf); 1167 return -ENOMEM; 1168 } 1169 err = otx2_sync_mbox_msg(&pf->mbox); 1170 if (err) { 1171 otx2_disable_mbox_intr(pf); 1172 return dev_err_probe(pf->dev, -EPROBE_DEFER, 1173 "AF not responding to mailbox, deferring probe\n"); 1174 } 1175 1176 return 0; 1177 } 1178 1179 void otx2_pfaf_mbox_destroy(struct otx2_nic *pf) 1180 { 1181 struct mbox *mbox = &pf->mbox; 1182 1183 if (pf->mbox_wq) { 1184 destroy_workqueue(pf->mbox_wq); 1185 pf->mbox_wq = NULL; 1186 } 1187 1188 if (mbox->mbox.hwbase && !is_cn20k(pf->pdev)) 1189 iounmap((void __iomem *)mbox->mbox.hwbase); 1190 1191 otx2_mbox_destroy(&mbox->mbox); 1192 otx2_mbox_destroy(&mbox->mbox_up); 1193 } 1194 EXPORT_SYMBOL(otx2_pfaf_mbox_destroy); 1195 1196 int otx2_pfaf_mbox_init(struct otx2_nic *pf) 1197 { 1198 struct mbox *mbox = &pf->mbox; 1199 void __iomem *hwbase; 1200 int err; 1201 1202 mbox->pfvf = pf; 1203 pf->mbox_wq = alloc_ordered_workqueue("otx2_pfaf_mailbox", 1204 WQ_HIGHPRI | WQ_MEM_RECLAIM); 1205 if (!pf->mbox_wq) 1206 return -ENOMEM; 1207 1208 /* For CN20K, AF allocates mbox memory in DRAM and writes PF 1209 * regions/offsets in RVU_MBOX_AF_PFX_ADDR, the RVU_PFX_FUNC_PFAF_MBOX 1210 * gives the aliased address to access AF/PF mailbox regions. 1211 */ 1212 if (is_cn20k(pf->pdev)) 1213 hwbase = pf->reg_base + RVU_PFX_FUNC_PFAF_MBOX + 1214 ((u64)BLKADDR_MBOX << RVU_FUNC_BLKADDR_SHIFT); 1215 else 1216 /* Mailbox is a reserved memory (in RAM) region shared between 1217 * admin function (i.e AF) and this PF, shouldn't be mapped as 1218 * device memory to allow unaligned accesses. 1219 */ 1220 hwbase = ioremap_wc(pci_resource_start 1221 (pf->pdev, PCI_MBOX_BAR_NUM), MBOX_SIZE); 1222 if (!hwbase) { 1223 dev_err(pf->dev, "Unable to map PFAF mailbox region\n"); 1224 err = -ENOMEM; 1225 goto exit; 1226 } 1227 1228 err = otx2_mbox_init(&mbox->mbox, hwbase, pf->pdev, pf->reg_base, 1229 MBOX_DIR_PFAF, 1); 1230 if (err) 1231 goto exit; 1232 1233 err = otx2_mbox_init(&mbox->mbox_up, hwbase, pf->pdev, pf->reg_base, 1234 MBOX_DIR_PFAF_UP, 1); 1235 if (err) 1236 goto exit; 1237 1238 err = otx2_mbox_bbuf_init(mbox, pf->pdev); 1239 if (err) 1240 goto exit; 1241 1242 INIT_WORK(&mbox->mbox_wrk, otx2_pfaf_mbox_handler); 1243 INIT_WORK(&mbox->mbox_up_wrk, otx2_pfaf_mbox_up_handler); 1244 mutex_init(&mbox->lock); 1245 1246 return 0; 1247 exit: 1248 otx2_pfaf_mbox_destroy(pf); 1249 return err; 1250 } 1251 1252 static int otx2_cgx_config_linkevents(struct otx2_nic *pf, bool enable) 1253 { 1254 struct msg_req *msg; 1255 int err; 1256 1257 mutex_lock(&pf->mbox.lock); 1258 if (enable) 1259 msg = otx2_mbox_alloc_msg_cgx_start_linkevents(&pf->mbox); 1260 else 1261 msg = otx2_mbox_alloc_msg_cgx_stop_linkevents(&pf->mbox); 1262 1263 if (!msg) { 1264 mutex_unlock(&pf->mbox.lock); 1265 return -ENOMEM; 1266 } 1267 1268 err = otx2_sync_mbox_msg(&pf->mbox); 1269 mutex_unlock(&pf->mbox.lock); 1270 return err; 1271 } 1272 1273 int otx2_reset_mac_stats(struct otx2_nic *pfvf) 1274 { 1275 struct msg_req *req; 1276 int err; 1277 1278 mutex_lock(&pfvf->mbox.lock); 1279 req = otx2_mbox_alloc_msg_cgx_stats_rst(&pfvf->mbox); 1280 if (!req) { 1281 mutex_unlock(&pfvf->mbox.lock); 1282 return -ENOMEM; 1283 } 1284 1285 err = otx2_sync_mbox_msg(&pfvf->mbox); 1286 mutex_unlock(&pfvf->mbox.lock); 1287 return err; 1288 } 1289 1290 static int otx2_cgx_config_loopback(struct otx2_nic *pf, bool enable) 1291 { 1292 struct msg_req *msg; 1293 int err; 1294 1295 if (enable && !bitmap_empty(pf->flow_cfg->dmacflt_bmap, 1296 pf->flow_cfg->dmacflt_max_flows)) 1297 netdev_warn(pf->netdev, 1298 "CGX/RPM internal loopback might not work as DMAC filters are active\n"); 1299 1300 mutex_lock(&pf->mbox.lock); 1301 if (enable) 1302 msg = otx2_mbox_alloc_msg_cgx_intlbk_enable(&pf->mbox); 1303 else 1304 msg = otx2_mbox_alloc_msg_cgx_intlbk_disable(&pf->mbox); 1305 1306 if (!msg) { 1307 mutex_unlock(&pf->mbox.lock); 1308 return -ENOMEM; 1309 } 1310 1311 err = otx2_sync_mbox_msg(&pf->mbox); 1312 mutex_unlock(&pf->mbox.lock); 1313 return err; 1314 } 1315 1316 int otx2_set_real_num_queues(struct net_device *netdev, 1317 int tx_queues, int rx_queues) 1318 { 1319 int err; 1320 1321 err = netif_set_real_num_tx_queues(netdev, tx_queues); 1322 if (err) { 1323 netdev_err(netdev, 1324 "Failed to set no of Tx queues: %d\n", tx_queues); 1325 return err; 1326 } 1327 1328 err = netif_set_real_num_rx_queues(netdev, rx_queues); 1329 if (err) 1330 netdev_err(netdev, 1331 "Failed to set no of Rx queues: %d\n", rx_queues); 1332 return err; 1333 } 1334 EXPORT_SYMBOL(otx2_set_real_num_queues); 1335 1336 static char *nix_sqoperr_e_str[NIX_SQOPERR_MAX] = { 1337 "NIX_SQOPERR_OOR", 1338 "NIX_SQOPERR_CTX_FAULT", 1339 "NIX_SQOPERR_CTX_POISON", 1340 "NIX_SQOPERR_DISABLED", 1341 "NIX_SQOPERR_SIZE_ERR", 1342 "NIX_SQOPERR_OFLOW", 1343 "NIX_SQOPERR_SQB_NULL", 1344 "NIX_SQOPERR_SQB_FAULT", 1345 "NIX_SQOPERR_SQE_SZ_ZERO", 1346 }; 1347 1348 static char *nix_mnqerr_e_str[NIX_MNQERR_MAX] = { 1349 "NIX_MNQERR_SQ_CTX_FAULT", 1350 "NIX_MNQERR_SQ_CTX_POISON", 1351 "NIX_MNQERR_SQB_FAULT", 1352 "NIX_MNQERR_SQB_POISON", 1353 "NIX_MNQERR_TOTAL_ERR", 1354 "NIX_MNQERR_LSO_ERR", 1355 "NIX_MNQERR_CQ_QUERY_ERR", 1356 "NIX_MNQERR_MAX_SQE_SIZE_ERR", 1357 "NIX_MNQERR_MAXLEN_ERR", 1358 "NIX_MNQERR_SQE_SIZEM1_ZERO", 1359 }; 1360 1361 static char *nix_snd_status_e_str[NIX_SND_STATUS_MAX] = { 1362 [NIX_SND_STATUS_GOOD] = "NIX_SND_STATUS_GOOD", 1363 [NIX_SND_STATUS_SQ_CTX_FAULT] = "NIX_SND_STATUS_SQ_CTX_FAULT", 1364 [NIX_SND_STATUS_SQ_CTX_POISON] = "NIX_SND_STATUS_SQ_CTX_POISON", 1365 [NIX_SND_STATUS_SQB_FAULT] = "NIX_SND_STATUS_SQB_FAULT", 1366 [NIX_SND_STATUS_SQB_POISON] = "NIX_SND_STATUS_SQB_POISON", 1367 [NIX_SND_STATUS_HDR_ERR] = "NIX_SND_STATUS_HDR_ERR", 1368 [NIX_SND_STATUS_EXT_ERR] = "NIX_SND_STATUS_EXT_ERR", 1369 [NIX_SND_STATUS_JUMP_FAULT] = "NIX_SND_STATUS_JUMP_FAULT", 1370 [NIX_SND_STATUS_JUMP_POISON] = "NIX_SND_STATUS_JUMP_POISON", 1371 [NIX_SND_STATUS_CRC_ERR] = "NIX_SND_STATUS_CRC_ERR", 1372 [NIX_SND_STATUS_IMM_ERR] = "NIX_SND_STATUS_IMM_ERR", 1373 [NIX_SND_STATUS_SG_ERR] = "NIX_SND_STATUS_SG_ERR", 1374 [NIX_SND_STATUS_MEM_ERR] = "NIX_SND_STATUS_MEM_ERR", 1375 [NIX_SND_STATUS_INVALID_SUBDC] = "NIX_SND_STATUS_INVALID_SUBDC", 1376 [NIX_SND_STATUS_SUBDC_ORDER_ERR] = "NIX_SND_STATUS_SUBDC_ORDER_ERR", 1377 [NIX_SND_STATUS_DATA_FAULT] = "NIX_SND_STATUS_DATA_FAULT", 1378 [NIX_SND_STATUS_DATA_POISON] = "NIX_SND_STATUS_DATA_POISON", 1379 [NIX_SND_STATUS_NPC_DROP_ACTION] = "NIX_SND_STATUS_NPC_DROP_ACTION", 1380 [NIX_SND_STATUS_LOCK_VIOL] = "NIX_SND_STATUS_LOCK_VIOL", 1381 [NIX_SND_STATUS_NPC_UCAST_CHAN_ERR] = "NIX_SND_STAT_NPC_UCAST_CHAN_ERR", 1382 [NIX_SND_STATUS_NPC_MCAST_CHAN_ERR] = "NIX_SND_STAT_NPC_MCAST_CHAN_ERR", 1383 [NIX_SND_STATUS_NPC_MCAST_ABORT] = "NIX_SND_STATUS_NPC_MCAST_ABORT", 1384 [NIX_SND_STATUS_NPC_VTAG_PTR_ERR] = "NIX_SND_STATUS_NPC_VTAG_PTR_ERR", 1385 [NIX_SND_STATUS_NPC_VTAG_SIZE_ERR] = "NIX_SND_STATUS_NPC_VTAG_SIZE_ERR", 1386 [NIX_SND_STATUS_SEND_MEM_FAULT] = "NIX_SND_STATUS_SEND_MEM_FAULT", 1387 [NIX_SND_STATUS_SEND_STATS_ERR] = "NIX_SND_STATUS_SEND_STATS_ERR", 1388 }; 1389 1390 static irqreturn_t otx2_q_intr_handler(int irq, void *data) 1391 { 1392 struct otx2_nic *pf = data; 1393 struct otx2_snd_queue *sq; 1394 void __iomem *ptr; 1395 u64 val, qidx = 0; 1396 1397 /* CQ */ 1398 for (qidx = 0; qidx < pf->qset.cq_cnt; qidx++) { 1399 ptr = otx2_get_regaddr(pf, NIX_LF_CQ_OP_INT); 1400 val = otx2_atomic64_add((qidx << 44), ptr); 1401 1402 otx2_write64(pf, NIX_LF_CQ_OP_INT, (qidx << 44) | 1403 (val & NIX_CQERRINT_BITS)); 1404 if (!(val & (NIX_CQERRINT_BITS | BIT_ULL(42)))) 1405 continue; 1406 1407 if (val & BIT_ULL(42)) { 1408 netdev_err(pf->netdev, 1409 "CQ%lld: error reading NIX_LF_CQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1410 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1411 } else { 1412 if (val & BIT_ULL(NIX_CQERRINT_DOOR_ERR)) 1413 netdev_err(pf->netdev, "CQ%lld: Doorbell error", 1414 qidx); 1415 if (val & BIT_ULL(NIX_CQERRINT_CQE_FAULT)) 1416 netdev_err(pf->netdev, 1417 "CQ%lld: Memory fault on CQE write to LLC/DRAM", 1418 qidx); 1419 } 1420 1421 schedule_work(&pf->reset_task); 1422 } 1423 1424 /* SQ */ 1425 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1426 u64 sq_op_err_dbg, mnq_err_dbg, snd_err_dbg; 1427 u8 sq_op_err_code, mnq_err_code, snd_err_code; 1428 1429 sq = &pf->qset.sq[qidx]; 1430 if (!sq->sqb_ptrs) 1431 continue; 1432 1433 /* Below debug registers captures first errors corresponding to 1434 * those registers. We don't have to check against SQ qid as 1435 * these are fatal errors. 1436 */ 1437 1438 ptr = otx2_get_regaddr(pf, NIX_LF_SQ_OP_INT); 1439 val = otx2_atomic64_add((qidx << 44), ptr); 1440 otx2_write64(pf, NIX_LF_SQ_OP_INT, (qidx << 44) | 1441 (val & NIX_SQINT_BITS)); 1442 1443 if (val & BIT_ULL(42)) { 1444 netdev_err(pf->netdev, 1445 "SQ%lld: error reading NIX_LF_SQ_OP_INT, NIX_LF_ERR_INT 0x%llx\n", 1446 qidx, otx2_read64(pf, NIX_LF_ERR_INT)); 1447 goto done; 1448 } 1449 1450 sq_op_err_dbg = otx2_read64(pf, NIX_LF_SQ_OP_ERR_DBG); 1451 if (!(sq_op_err_dbg & BIT(44))) 1452 goto chk_mnq_err_dbg; 1453 1454 sq_op_err_code = FIELD_GET(GENMASK(7, 0), sq_op_err_dbg); 1455 netdev_err(pf->netdev, 1456 "SQ%lld: NIX_LF_SQ_OP_ERR_DBG(0x%llx) err=%s(%#x)\n", 1457 qidx, sq_op_err_dbg, 1458 nix_sqoperr_e_str[sq_op_err_code], 1459 sq_op_err_code); 1460 1461 otx2_write64(pf, NIX_LF_SQ_OP_ERR_DBG, BIT_ULL(44)); 1462 1463 if (sq_op_err_code == NIX_SQOPERR_SQB_NULL) 1464 goto chk_mnq_err_dbg; 1465 1466 /* Err is not NIX_SQOPERR_SQB_NULL, call aq function to read SQ structure. 1467 * TODO: But we are in irq context. How to call mbox functions which does sleep 1468 */ 1469 1470 chk_mnq_err_dbg: 1471 mnq_err_dbg = otx2_read64(pf, NIX_LF_MNQ_ERR_DBG); 1472 if (!(mnq_err_dbg & BIT(44))) 1473 goto chk_snd_err_dbg; 1474 1475 mnq_err_code = FIELD_GET(GENMASK(7, 0), mnq_err_dbg); 1476 netdev_err(pf->netdev, 1477 "SQ%lld: NIX_LF_MNQ_ERR_DBG(0x%llx) err=%s(%#x)\n", 1478 qidx, mnq_err_dbg, nix_mnqerr_e_str[mnq_err_code], 1479 mnq_err_code); 1480 otx2_write64(pf, NIX_LF_MNQ_ERR_DBG, BIT_ULL(44)); 1481 1482 chk_snd_err_dbg: 1483 snd_err_dbg = otx2_read64(pf, NIX_LF_SEND_ERR_DBG); 1484 if (snd_err_dbg & BIT(44)) { 1485 snd_err_code = FIELD_GET(GENMASK(7, 0), snd_err_dbg); 1486 netdev_err(pf->netdev, 1487 "SQ%lld: NIX_LF_SND_ERR_DBG:0x%llx err=%s(%#x)\n", 1488 qidx, snd_err_dbg, 1489 nix_snd_status_e_str[snd_err_code], 1490 snd_err_code); 1491 otx2_write64(pf, NIX_LF_SEND_ERR_DBG, BIT_ULL(44)); 1492 } 1493 1494 done: 1495 /* Print values and reset */ 1496 if (val & BIT_ULL(NIX_SQINT_SQB_ALLOC_FAIL)) 1497 netdev_err(pf->netdev, "SQ%lld: SQB allocation failed", 1498 qidx); 1499 1500 schedule_work(&pf->reset_task); 1501 } 1502 1503 return IRQ_HANDLED; 1504 } 1505 1506 irqreturn_t otx2_cq_intr_handler(int irq, void *cq_irq) 1507 { 1508 struct otx2_cq_poll *cq_poll = (struct otx2_cq_poll *)cq_irq; 1509 struct otx2_nic *pf = (struct otx2_nic *)cq_poll->dev; 1510 int qidx = cq_poll->cint_idx; 1511 1512 /* Disable interrupts. 1513 * 1514 * Completion interrupts behave in a level-triggered interrupt 1515 * fashion, and hence have to be cleared only after it is serviced. 1516 */ 1517 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 1518 1519 /* Schedule NAPI */ 1520 pf->napi_events++; 1521 napi_schedule_irqoff(&cq_poll->napi); 1522 1523 return IRQ_HANDLED; 1524 } 1525 EXPORT_SYMBOL(otx2_cq_intr_handler); 1526 1527 static irqreturn_t otx2_nixlf_err_intr_handler(int irq, void *data) 1528 { 1529 struct otx2_nic *pf = data; 1530 u64 regval; 1531 1532 /* Clear interrupt */ 1533 regval = otx2_read64(pf, NIX_LF_ERR_INT); 1534 otx2_write64(pf, NIX_LF_ERR_INT, regval); 1535 1536 dev_err_ratelimited(pf->dev, "NIXLF Error Interrupt: 0x%llx\n", regval); 1537 1538 return IRQ_HANDLED; 1539 } 1540 1541 static irqreturn_t otx2_nixlf_poison_intr_handler(int irq, void *data) 1542 { 1543 struct otx2_nic *pf = data; 1544 u64 regval; 1545 1546 /* Clear interrupt */ 1547 regval = otx2_read64(pf, NIX_LF_RAS); 1548 otx2_write64(pf, NIX_LF_RAS, regval); 1549 1550 dev_err_ratelimited(pf->dev, "NIXLF Poison Interrupt: 0x%llx\n", regval); 1551 1552 return IRQ_HANDLED; 1553 } 1554 1555 void otx2_disable_napi(struct otx2_nic *pf) 1556 { 1557 struct otx2_qset *qset = &pf->qset; 1558 struct otx2_cq_poll *cq_poll; 1559 struct work_struct *work; 1560 int qidx; 1561 1562 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 1563 cq_poll = &qset->napi[qidx]; 1564 work = &cq_poll->dim.work; 1565 if (work->func) 1566 cancel_work_sync(work); 1567 napi_disable(&cq_poll->napi); 1568 netif_napi_del(&cq_poll->napi); 1569 } 1570 } 1571 EXPORT_SYMBOL(otx2_disable_napi); 1572 1573 static void otx2_free_cq_res(struct otx2_nic *pf) 1574 { 1575 struct otx2_qset *qset = &pf->qset; 1576 struct otx2_cq_queue *cq; 1577 int qidx; 1578 1579 /* Disable CQs */ 1580 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_CQ, false); 1581 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1582 cq = &qset->cq[qidx]; 1583 qmem_free(pf->dev, cq->cqe); 1584 } 1585 } 1586 1587 static void otx2_free_sq_res(struct otx2_nic *pf) 1588 { 1589 struct otx2_qset *qset = &pf->qset; 1590 struct otx2_snd_queue *sq; 1591 int qidx; 1592 1593 /* Disable SQs */ 1594 otx2_ctx_disable(&pf->mbox, NIX_AQ_CTYPE_SQ, false); 1595 /* Free SQB pointers */ 1596 otx2_sq_free_sqbs(pf); 1597 for (qidx = 0; qidx < otx2_get_total_tx_queues(pf); qidx++) { 1598 sq = &qset->sq[qidx]; 1599 /* sq->sqe is not initialized for unused QoS queues */ 1600 if (sq->sqe) { 1601 qmem_free(pf->dev, sq->sqe); 1602 qmem_free(pf->dev, sq->sqe_ring); 1603 qmem_free(pf->dev, sq->cpt_resp); 1604 qmem_free(pf->dev, sq->tso_hdrs); 1605 qmem_free(pf->dev, sq->timestamps); 1606 kfree(sq->sg); 1607 } 1608 kfree(sq->sqb_ptrs); 1609 } 1610 } 1611 1612 static int otx2_get_rbuf_size(struct otx2_nic *pf, int mtu) 1613 { 1614 int frame_size; 1615 int total_size; 1616 int rbuf_size; 1617 1618 if (pf->hw.rbuf_len) 1619 return ALIGN(pf->hw.rbuf_len, OTX2_ALIGN) + OTX2_HEAD_ROOM; 1620 1621 /* The data transferred by NIX to memory consists of actual packet 1622 * plus additional data which has timestamp and/or EDSA/HIGIG2 1623 * headers if interface is configured in corresponding modes. 1624 * NIX transfers entire data using 6 segments/buffers and writes 1625 * a CQE_RX descriptor with those segment addresses. First segment 1626 * has additional data prepended to packet. Also software omits a 1627 * headroom of 128 bytes in each segment. Hence the total size of 1628 * memory needed to receive a packet with 'mtu' is: 1629 * frame size = mtu + additional data; 1630 * memory = frame_size + headroom * 6; 1631 * each receive buffer size = memory / 6; 1632 */ 1633 frame_size = mtu + OTX2_ETH_HLEN + OTX2_HW_TIMESTAMP_LEN; 1634 total_size = frame_size + OTX2_HEAD_ROOM * 6; 1635 rbuf_size = total_size / 6; 1636 1637 return ALIGN(rbuf_size, 2048); 1638 } 1639 1640 int otx2_init_hw_resources(struct otx2_nic *pf) 1641 { 1642 struct nix_lf_free_req *free_req; 1643 struct mbox *mbox = &pf->mbox; 1644 struct otx2_hw *hw = &pf->hw; 1645 struct msg_req *req; 1646 int err = 0, lvl; 1647 1648 /* Set required NPA LF's pool counts 1649 * Auras and Pools are used in a 1:1 mapping, 1650 * so, aura count = pool count. 1651 */ 1652 hw->rqpool_cnt = hw->rx_queues; 1653 hw->sqpool_cnt = otx2_get_total_tx_queues(pf); 1654 hw->pool_cnt = hw->rqpool_cnt + hw->sqpool_cnt; 1655 1656 if (!otx2_rep_dev(pf->pdev)) { 1657 /* Maximum hardware supported transmit length */ 1658 pf->tx_max_pktlen = pf->netdev->max_mtu + OTX2_ETH_HLEN; 1659 pf->rbsize = otx2_get_rbuf_size(pf, pf->netdev->mtu); 1660 } 1661 1662 mutex_lock(&mbox->lock); 1663 /* NPA init */ 1664 err = otx2_config_npa(pf); 1665 if (err) 1666 goto exit; 1667 1668 /* NIX init */ 1669 err = otx2_config_nix(pf); 1670 if (err) 1671 goto err_free_npa_lf; 1672 1673 /* Default disable backpressure on NIX-CPT */ 1674 otx2_nix_cpt_config_bp(pf, false); 1675 1676 /* Enable backpressure for CGX mapped PF/VFs */ 1677 if (!is_otx2_lbkvf(pf->pdev)) 1678 otx2_nix_config_bp(pf, true); 1679 1680 /* Init Auras and pools used by NIX RQ, for free buffer ptrs */ 1681 err = otx2_rq_aura_pool_init(pf); 1682 if (err) { 1683 mutex_unlock(&mbox->lock); 1684 goto err_free_nix_lf; 1685 } 1686 /* Init Auras and pools used by NIX SQ, for queueing SQEs */ 1687 err = otx2_sq_aura_pool_init(pf); 1688 if (err) { 1689 mutex_unlock(&mbox->lock); 1690 goto err_free_rq_ptrs; 1691 } 1692 1693 err = otx2_txsch_alloc(pf); 1694 if (err) { 1695 mutex_unlock(&mbox->lock); 1696 goto err_free_sq_ptrs; 1697 } 1698 1699 #ifdef CONFIG_DCB 1700 if (pf->pfc_en) { 1701 err = otx2_pfc_txschq_alloc(pf); 1702 if (err) { 1703 mutex_unlock(&mbox->lock); 1704 goto err_free_sq_ptrs; 1705 } 1706 } 1707 #endif 1708 1709 err = otx2_config_nix_queues(pf); 1710 if (err) { 1711 mutex_unlock(&mbox->lock); 1712 goto err_free_txsch; 1713 } 1714 1715 for (lvl = 0; lvl < NIX_TXSCH_LVL_CNT; lvl++) { 1716 int idx; 1717 1718 for (idx = 0; idx < pf->hw.txschq_cnt[lvl]; idx++) { 1719 err = otx2_txschq_config(pf, lvl, idx, false); 1720 if (err) { 1721 dev_err(pf->dev, "Failed to config TXSCH\n"); 1722 mutex_unlock(&mbox->lock); 1723 goto err_free_nix_queues; 1724 } 1725 } 1726 } 1727 1728 #ifdef CONFIG_DCB 1729 if (pf->pfc_en) { 1730 err = otx2_pfc_txschq_config(pf); 1731 if (err) { 1732 mutex_unlock(&mbox->lock); 1733 goto err_free_nix_queues; 1734 } 1735 } 1736 #endif 1737 1738 mutex_unlock(&mbox->lock); 1739 return err; 1740 1741 err_free_nix_queues: 1742 otx2_free_cq_res(pf); 1743 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1744 err_free_txsch: 1745 otx2_txschq_stop(pf); 1746 err_free_sq_ptrs: 1747 otx2_free_sq_res(pf); 1748 err_free_rq_ptrs: 1749 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1750 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1751 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1752 otx2_aura_pool_free(pf); 1753 err_free_nix_lf: 1754 mutex_lock(&mbox->lock); 1755 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1756 if (free_req) { 1757 free_req->flags = NIX_LF_DISABLE_FLOWS | NIX_LF_DONT_FREE_DFT_IDXS; 1758 if (otx2_sync_mbox_msg(mbox)) 1759 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1760 } 1761 err_free_npa_lf: 1762 /* Reset NPA LF */ 1763 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1764 if (req) { 1765 if (otx2_sync_mbox_msg(mbox)) 1766 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1767 } 1768 exit: 1769 mutex_unlock(&mbox->lock); 1770 return err; 1771 } 1772 EXPORT_SYMBOL(otx2_init_hw_resources); 1773 1774 void otx2_free_hw_resources(struct otx2_nic *pf) 1775 { 1776 struct otx2_qset *qset = &pf->qset; 1777 struct nix_lf_free_req *free_req; 1778 struct mbox *mbox = &pf->mbox; 1779 struct otx2_cq_queue *cq; 1780 struct msg_req *req; 1781 int qidx; 1782 1783 /* Ensure all SQE are processed */ 1784 otx2_sqb_flush(pf); 1785 1786 /* Stop transmission */ 1787 otx2_txschq_stop(pf); 1788 1789 #ifdef CONFIG_DCB 1790 if (pf->pfc_en) 1791 otx2_pfc_txschq_stop(pf); 1792 #endif 1793 1794 if (!otx2_rep_dev(pf->pdev)) 1795 otx2_clean_qos_queues(pf); 1796 1797 mutex_lock(&mbox->lock); 1798 /* Disable backpressure */ 1799 if (!is_otx2_lbkvf(pf->pdev)) 1800 otx2_nix_config_bp(pf, false); 1801 mutex_unlock(&mbox->lock); 1802 1803 /* Disable RQs */ 1804 otx2_ctx_disable(mbox, NIX_AQ_CTYPE_RQ, false); 1805 1806 /*Dequeue all CQEs */ 1807 for (qidx = 0; qidx < qset->cq_cnt; qidx++) { 1808 cq = &qset->cq[qidx]; 1809 if (cq->cq_type == CQ_RX) 1810 otx2_cleanup_rx_cqes(pf, cq, qidx); 1811 else 1812 otx2_cleanup_tx_cqes(pf, cq); 1813 } 1814 otx2_free_pending_sqe(pf); 1815 1816 otx2_free_sq_res(pf); 1817 1818 /* Free RQ buffer pointers*/ 1819 otx2_free_aura_ptr(pf, AURA_NIX_RQ); 1820 1821 otx2_free_cq_res(pf); 1822 1823 /* Free all ingress bandwidth profiles allocated */ 1824 if (!otx2_rep_dev(pf->pdev)) 1825 cn10k_free_all_ipolicers(pf); 1826 1827 mutex_lock(&mbox->lock); 1828 /* Reset NIX LF */ 1829 free_req = otx2_mbox_alloc_msg_nix_lf_free(mbox); 1830 if (free_req) { 1831 free_req->flags = NIX_LF_DISABLE_FLOWS | NIX_LF_DONT_FREE_DFT_IDXS; 1832 if (!(pf->flags & OTX2_FLAG_PF_SHUTDOWN)) 1833 free_req->flags |= NIX_LF_DONT_FREE_TX_VTAG; 1834 if (otx2_sync_mbox_msg(mbox)) 1835 dev_err(pf->dev, "%s failed to free nixlf\n", __func__); 1836 } 1837 mutex_unlock(&mbox->lock); 1838 1839 /* Disable NPA Pool and Aura hw context */ 1840 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_POOL, true); 1841 otx2_ctx_disable(mbox, NPA_AQ_CTYPE_AURA, true); 1842 otx2_aura_pool_free(pf); 1843 1844 mutex_lock(&mbox->lock); 1845 /* Reset NPA LF */ 1846 req = otx2_mbox_alloc_msg_npa_lf_free(mbox); 1847 if (req) { 1848 if (otx2_sync_mbox_msg(mbox)) 1849 dev_err(pf->dev, "%s failed to free npalf\n", __func__); 1850 } 1851 mutex_unlock(&mbox->lock); 1852 } 1853 EXPORT_SYMBOL(otx2_free_hw_resources); 1854 1855 static bool otx2_promisc_use_mce_list(struct otx2_nic *pfvf) 1856 { 1857 int vf; 1858 1859 /* The AF driver will determine whether to allow the VF netdev or not */ 1860 if (is_otx2_vf(pfvf->pcifunc)) 1861 return true; 1862 1863 /* check if there are any trusted VFs associated with the PF netdev */ 1864 for (vf = 0; vf < pci_num_vf(pfvf->pdev); vf++) 1865 if (pfvf->vf_configs[vf].trusted) 1866 return true; 1867 return false; 1868 } 1869 1870 static void otx2_do_set_rx_mode(struct otx2_nic *pf) 1871 { 1872 struct net_device *netdev = pf->netdev; 1873 struct nix_rx_mode *req; 1874 bool promisc = false; 1875 1876 if (!(netdev->flags & IFF_UP)) 1877 return; 1878 1879 if ((netdev->flags & IFF_PROMISC) || 1880 (netdev_uc_count(netdev) > pf->flow_cfg->ucast_flt_cnt)) { 1881 promisc = true; 1882 } 1883 1884 /* Write unicast address to mcam entries or del from mcam */ 1885 if (!promisc && netdev->priv_flags & IFF_UNICAST_FLT) 1886 __dev_uc_sync(netdev, otx2_add_macfilter, otx2_del_macfilter); 1887 1888 mutex_lock(&pf->mbox.lock); 1889 req = otx2_mbox_alloc_msg_nix_set_rx_mode(&pf->mbox); 1890 if (!req) { 1891 mutex_unlock(&pf->mbox.lock); 1892 return; 1893 } 1894 1895 req->mode = NIX_RX_MODE_UCAST; 1896 1897 if (promisc) 1898 req->mode |= NIX_RX_MODE_PROMISC; 1899 if (netdev->flags & (IFF_ALLMULTI | IFF_MULTICAST)) 1900 req->mode |= NIX_RX_MODE_ALLMULTI; 1901 1902 if (otx2_promisc_use_mce_list(pf)) 1903 req->mode |= NIX_RX_MODE_USE_MCE; 1904 1905 otx2_sync_mbox_msg(&pf->mbox); 1906 mutex_unlock(&pf->mbox.lock); 1907 } 1908 1909 static void otx2_set_irq_coalesce(struct otx2_nic *pfvf) 1910 { 1911 int cint; 1912 1913 for (cint = 0; cint < pfvf->hw.cint_cnt; cint++) 1914 otx2_config_irq_coalescing(pfvf, cint); 1915 } 1916 1917 static void otx2_dim_work(struct work_struct *w) 1918 { 1919 struct dim_cq_moder cur_moder; 1920 struct otx2_cq_poll *cq_poll; 1921 struct otx2_nic *pfvf; 1922 struct dim *dim; 1923 1924 dim = container_of(w, struct dim, work); 1925 cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix); 1926 cq_poll = container_of(dim, struct otx2_cq_poll, dim); 1927 pfvf = (struct otx2_nic *)cq_poll->dev; 1928 pfvf->hw.cq_time_wait = (cur_moder.usec > CQ_TIMER_THRESH_MAX) ? 1929 CQ_TIMER_THRESH_MAX : cur_moder.usec; 1930 pfvf->hw.cq_ecount_wait = (cur_moder.pkts > NAPI_POLL_WEIGHT) ? 1931 NAPI_POLL_WEIGHT : cur_moder.pkts; 1932 otx2_set_irq_coalesce(pfvf); 1933 dim->state = DIM_START_MEASURE; 1934 } 1935 1936 void otx2_free_queue_mem(struct otx2_qset *qset) 1937 { 1938 kfree(qset->sq); 1939 qset->sq = NULL; 1940 kfree(qset->cq); 1941 qset->cq = NULL; 1942 kfree(qset->rq); 1943 qset->rq = NULL; 1944 kfree(qset->napi); 1945 qset->napi = NULL; 1946 } 1947 EXPORT_SYMBOL(otx2_free_queue_mem); 1948 1949 int otx2_alloc_queue_mem(struct otx2_nic *pf) 1950 { 1951 struct otx2_qset *qset = &pf->qset; 1952 struct otx2_cq_poll *cq_poll; 1953 1954 /* RQ and SQs are mapped to different CQs, 1955 * so find out max CQ IRQs (i.e CINTs) needed. 1956 */ 1957 pf->hw.non_qos_queues = pf->hw.tx_queues + pf->hw.xdp_queues; 1958 pf->hw.cint_cnt = max3(pf->hw.rx_queues, pf->hw.tx_queues, 1959 pf->hw.tc_tx_queues); 1960 1961 pf->qset.cq_cnt = pf->hw.rx_queues + otx2_get_total_tx_queues(pf); 1962 1963 qset->napi = kzalloc_objs(*cq_poll, pf->hw.cint_cnt); 1964 if (!qset->napi) 1965 return -ENOMEM; 1966 1967 /* CQ size of RQ */ 1968 qset->rqe_cnt = qset->rqe_cnt ? qset->rqe_cnt : Q_COUNT(Q_SIZE_256); 1969 /* CQ size of SQ */ 1970 qset->sqe_cnt = qset->sqe_cnt ? qset->sqe_cnt : Q_COUNT(Q_SIZE_4K); 1971 1972 qset->cq = kzalloc_objs(struct otx2_cq_queue, pf->qset.cq_cnt); 1973 if (!qset->cq) 1974 goto err_free_mem; 1975 1976 qset->sq = kzalloc_objs(struct otx2_snd_queue, 1977 otx2_get_total_tx_queues(pf)); 1978 if (!qset->sq) 1979 goto err_free_mem; 1980 1981 qset->rq = kzalloc_objs(struct otx2_rcv_queue, pf->hw.rx_queues); 1982 if (!qset->rq) 1983 goto err_free_mem; 1984 1985 return 0; 1986 1987 err_free_mem: 1988 otx2_free_queue_mem(qset); 1989 return -ENOMEM; 1990 } 1991 EXPORT_SYMBOL(otx2_alloc_queue_mem); 1992 1993 int otx2_open(struct net_device *netdev) 1994 { 1995 struct otx2_nic *pf = netdev_priv(netdev); 1996 struct otx2_cq_poll *cq_poll = NULL; 1997 struct otx2_qset *qset = &pf->qset; 1998 int err = 0, qidx, vec; 1999 char *irq_name; 2000 2001 netif_carrier_off(netdev); 2002 2003 err = otx2_alloc_queue_mem(pf); 2004 if (err) 2005 return err; 2006 2007 err = otx2_init_hw_resources(pf); 2008 if (err) 2009 goto err_free_mem; 2010 2011 /* Register NAPI handler */ 2012 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 2013 cq_poll = &qset->napi[qidx]; 2014 cq_poll->cint_idx = qidx; 2015 /* RQ0 & SQ0 are mapped to CINT0 and so on.. 2016 * 'cq_ids[0]' points to RQ's CQ and 2017 * 'cq_ids[1]' points to SQ's CQ and 2018 * 'cq_ids[2]' points to XDP's CQ and 2019 */ 2020 cq_poll->cq_ids[CQ_RX] = 2021 (qidx < pf->hw.rx_queues) ? qidx : CINT_INVALID_CQ; 2022 cq_poll->cq_ids[CQ_TX] = (qidx < pf->hw.tx_queues) ? 2023 qidx + pf->hw.rx_queues : CINT_INVALID_CQ; 2024 if (pf->xdp_prog) 2025 cq_poll->cq_ids[CQ_XDP] = (qidx < pf->hw.xdp_queues) ? 2026 (qidx + pf->hw.rx_queues + 2027 pf->hw.tx_queues) : 2028 CINT_INVALID_CQ; 2029 else 2030 cq_poll->cq_ids[CQ_XDP] = CINT_INVALID_CQ; 2031 2032 cq_poll->cq_ids[CQ_QOS] = (qidx < pf->hw.tc_tx_queues) ? 2033 (qidx + pf->hw.rx_queues + 2034 pf->hw.non_qos_queues) : 2035 CINT_INVALID_CQ; 2036 2037 cq_poll->dev = (void *)pf; 2038 cq_poll->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_CQE; 2039 INIT_WORK(&cq_poll->dim.work, otx2_dim_work); 2040 netif_napi_add(netdev, &cq_poll->napi, otx2_napi_handler); 2041 napi_enable(&cq_poll->napi); 2042 } 2043 2044 /* Set maximum frame size allowed in HW */ 2045 err = otx2_hw_set_mtu(pf, netdev->mtu); 2046 if (err) 2047 goto err_disable_napi; 2048 2049 /* Setup segmentation algorithms, if failed, clear offload capability */ 2050 otx2_setup_segmentation(pf); 2051 2052 /* Initialize RSS */ 2053 err = otx2_rss_init(pf); 2054 if (err) 2055 goto err_disable_napi; 2056 2057 /* Register Queue IRQ handlers */ 2058 vec = pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START; 2059 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 2060 2061 snprintf(irq_name, NAME_SIZE, "%s-qerr", pf->netdev->name); 2062 2063 err = request_irq(pci_irq_vector(pf->pdev, vec), 2064 otx2_q_intr_handler, 0, irq_name, pf); 2065 if (err) { 2066 dev_err(pf->dev, 2067 "RVUPF%d: IRQ registration failed for QERR\n", 2068 rvu_get_pf(pf->pdev, pf->pcifunc)); 2069 goto err_disable_napi; 2070 } 2071 2072 /* Enable QINT IRQ */ 2073 otx2_write64(pf, NIX_LF_QINTX_ENA_W1S(0), BIT_ULL(0)); 2074 2075 /* Register CQ IRQ handlers */ 2076 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 2077 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 2078 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 2079 int name_len; 2080 2081 name_len = snprintf(irq_name, NAME_SIZE, "%s-rxtx-%d", 2082 pf->netdev->name, qidx); 2083 if (name_len >= NAME_SIZE) { 2084 dev_err(pf->dev, 2085 "RVUPF%d: IRQ registration failed for CQ%d, irq name is too long\n", 2086 rvu_get_pf(pf->pdev, pf->pcifunc), qidx); 2087 err = -EINVAL; 2088 goto err_free_cints; 2089 } 2090 2091 err = request_irq(pci_irq_vector(pf->pdev, vec), 2092 otx2_cq_intr_handler, 0, irq_name, 2093 &qset->napi[qidx]); 2094 if (err) { 2095 dev_err(pf->dev, 2096 "RVUPF%d: IRQ registration failed for CQ%d\n", 2097 rvu_get_pf(pf->pdev, pf->pcifunc), qidx); 2098 goto err_free_cints; 2099 } 2100 vec++; 2101 2102 otx2_config_irq_coalescing(pf, qidx); 2103 2104 /* Enable CQ IRQ */ 2105 otx2_write64(pf, NIX_LF_CINTX_INT(qidx), BIT_ULL(0)); 2106 otx2_write64(pf, NIX_LF_CINTX_ENA_W1S(qidx), BIT_ULL(0)); 2107 } 2108 2109 otx2_set_cints_affinity(pf); 2110 2111 /* Register NIXLF error IRQ handler */ 2112 vec = pf->hw.nix_msixoff + NIX_LF_ERR_VEC; 2113 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 2114 snprintf(irq_name, NAME_SIZE, "%s-nixlf-err", pf->netdev->name); 2115 err = request_irq(pci_irq_vector(pf->pdev, vec), 2116 otx2_nixlf_err_intr_handler, 0, irq_name, pf); 2117 if (err) { 2118 dev_err(pf->dev, 2119 "RVUPF%d: IRQ registration failed for NIXLF ERR vector\n", 2120 rvu_get_pf(pf->pdev, pf->pcifunc)); 2121 goto err_free_cints; 2122 } 2123 otx2_write64(pf, NIX_LF_ERR_INT_ENA_W1S, NIX_LF_ERR_INT_MASK); 2124 2125 /* Register NIXLF POISON interrupt handler */ 2126 vec = pf->hw.nix_msixoff + NIX_LF_POISON_VEC; 2127 irq_name = &pf->hw.irq_name[vec * NAME_SIZE]; 2128 snprintf(irq_name, NAME_SIZE, "%s-nixlf-poison", pf->netdev->name); 2129 err = request_irq(pci_irq_vector(pf->pdev, vec), 2130 otx2_nixlf_poison_intr_handler, 0, irq_name, pf); 2131 if (err) { 2132 dev_err(pf->dev, 2133 "RVUPF%d: IRQ registration failed for NIXLF POISON vector\n", 2134 rvu_get_pf(pf->pdev, pf->pcifunc)); 2135 goto err_free_errint; 2136 } 2137 otx2_write64(pf, NIX_LF_RAS_ENA_W1S, NIX_LF_RAS_MASK); 2138 2139 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 2140 otx2_enable_rxvlan(pf, true); 2141 2142 /* When reinitializing enable time stamping if it is enabled before */ 2143 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) { 2144 pf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2145 otx2_config_hw_tx_tstamp(pf, true); 2146 } 2147 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) { 2148 pf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 2149 otx2_config_hw_rx_tstamp(pf, true); 2150 } 2151 2152 pf->flags &= ~OTX2_FLAG_INTF_DOWN; 2153 pf->flags &= ~OTX2_FLAG_PORT_UP; 2154 /* 'intf_down' may be checked on any cpu */ 2155 smp_wmb(); 2156 2157 /* Enable QoS configuration before starting tx queues */ 2158 otx2_qos_config_txschq(pf); 2159 2160 /* we have already received link status notification */ 2161 if (pf->linfo.link_up && !(pf->pcifunc & RVU_PFVF_FUNC_MASK)) 2162 otx2_handle_link_event(pf); 2163 2164 /* Install DMAC Filters */ 2165 if (pf->flags & OTX2_FLAG_DMACFLTR_SUPPORT) 2166 otx2_dmacflt_reinstall_flows(pf); 2167 2168 otx2_tc_apply_ingress_police_rules(pf); 2169 2170 err = otx2_rxtx_enable(pf, true); 2171 /* If a mbox communication error happens at this point then interface 2172 * will end up in a state such that it is in down state but hardware 2173 * mcam entries are enabled to receive the packets. Hence disable the 2174 * packet I/O. 2175 */ 2176 if (err == -EIO) 2177 goto err_disable_rxtx; 2178 else if (err) 2179 goto err_tx_stop_queues; 2180 2181 otx2_do_set_rx_mode(pf); 2182 2183 return 0; 2184 2185 err_disable_rxtx: 2186 otx2_rxtx_enable(pf, false); 2187 err_tx_stop_queues: 2188 netif_tx_stop_all_queues(netdev); 2189 netif_carrier_off(netdev); 2190 pf->flags |= OTX2_FLAG_INTF_DOWN; 2191 /* free NIXLF POISON irq */ 2192 vec = pci_irq_vector(pf->pdev, 2193 pf->hw.nix_msixoff + NIX_LF_POISON_VEC); 2194 otx2_write64(pf, NIX_LF_RAS_ENA_W1C, NIX_LF_RAS_MASK); 2195 free_irq(vec, pf); 2196 err_free_errint: 2197 vec = pci_irq_vector(pf->pdev, 2198 pf->hw.nix_msixoff + NIX_LF_ERR_VEC); 2199 otx2_write64(pf, NIX_LF_ERR_INT_ENA_W1C, NIX_LF_ERR_INT_MASK); 2200 free_irq(vec, pf); 2201 err_free_cints: 2202 otx2_free_cints(pf, qidx); 2203 vec = pci_irq_vector(pf->pdev, 2204 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 2205 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 2206 free_irq(vec, pf); 2207 err_disable_napi: 2208 otx2_disable_napi(pf); 2209 otx2_free_hw_resources(pf); 2210 err_free_mem: 2211 otx2_free_queue_mem(qset); 2212 return err; 2213 } 2214 EXPORT_SYMBOL(otx2_open); 2215 2216 int otx2_stop(struct net_device *netdev) 2217 { 2218 struct otx2_nic *pf = netdev_priv(netdev); 2219 struct otx2_cq_poll *cq_poll = NULL; 2220 struct otx2_qset *qset = &pf->qset; 2221 int qidx, vec, wrk; 2222 2223 /* If the DOWN flag is set resources are already freed */ 2224 if (pf->flags & OTX2_FLAG_INTF_DOWN) 2225 return 0; 2226 2227 netif_carrier_off(netdev); 2228 netif_tx_stop_all_queues(netdev); 2229 2230 pf->flags |= OTX2_FLAG_INTF_DOWN; 2231 /* 'intf_down' may be checked on any cpu */ 2232 smp_wmb(); 2233 2234 /* First stop packet Rx/Tx */ 2235 otx2_rxtx_enable(pf, false); 2236 2237 /* Clear RSS enable flag */ 2238 pf->hw.rss_info.enable = false; 2239 2240 /* Cleanup NIXLF Poison IRQ */ 2241 vec = pci_irq_vector(pf->pdev, 2242 pf->hw.nix_msixoff + NIX_LF_POISON_VEC); 2243 otx2_write64(pf, NIX_LF_RAS_ENA_W1C, NIX_LF_RAS_MASK); 2244 free_irq(vec, pf); 2245 2246 /* Cleanup NIXLF Error IRQ */ 2247 vec = pci_irq_vector(pf->pdev, 2248 pf->hw.nix_msixoff + NIX_LF_ERR_VEC); 2249 otx2_write64(pf, NIX_LF_ERR_INT_ENA_W1C, NIX_LF_ERR_INT_MASK); 2250 free_irq(vec, pf); 2251 2252 /* Cleanup Queue IRQ */ 2253 vec = pci_irq_vector(pf->pdev, 2254 pf->hw.nix_msixoff + NIX_LF_QINT_VEC_START); 2255 otx2_write64(pf, NIX_LF_QINTX_ENA_W1C(0), BIT_ULL(0)); 2256 free_irq(vec, pf); 2257 2258 /* Cleanup CQ NAPI and IRQ */ 2259 vec = pf->hw.nix_msixoff + NIX_LF_CINT_VEC_START; 2260 for (qidx = 0; qidx < pf->hw.cint_cnt; qidx++) { 2261 /* Disable interrupt */ 2262 otx2_write64(pf, NIX_LF_CINTX_ENA_W1C(qidx), BIT_ULL(0)); 2263 2264 synchronize_irq(pci_irq_vector(pf->pdev, vec)); 2265 2266 cq_poll = &qset->napi[qidx]; 2267 napi_synchronize(&cq_poll->napi); 2268 vec++; 2269 } 2270 2271 netif_tx_disable(netdev); 2272 2273 for (wrk = 0; wrk < pf->qset.cq_cnt; wrk++) 2274 cancel_delayed_work_sync(&pf->refill_wrk[wrk].pool_refill_work); 2275 devm_kfree(pf->dev, pf->refill_wrk); 2276 2277 otx2_free_hw_resources(pf); 2278 otx2_free_cints(pf, pf->hw.cint_cnt); 2279 otx2_disable_napi(pf); 2280 2281 for (qidx = 0; qidx < netdev->num_tx_queues; qidx++) 2282 netdev_tx_reset_queue(netdev_get_tx_queue(netdev, qidx)); 2283 2284 otx2_free_queue_mem(qset); 2285 /* Do not clear RQ/SQ ringsize settings */ 2286 memset_startat(qset, 0, sqe_cnt); 2287 return 0; 2288 } 2289 EXPORT_SYMBOL(otx2_stop); 2290 2291 static netdev_tx_t otx2_xmit(struct sk_buff *skb, struct net_device *netdev) 2292 { 2293 struct otx2_nic *pf = netdev_priv(netdev); 2294 int qidx = skb_get_queue_mapping(skb); 2295 struct otx2_dev_stats *dev_stats; 2296 struct otx2_snd_queue *sq; 2297 struct netdev_queue *txq; 2298 int sq_idx; 2299 2300 /* XDP SQs are not mapped with TXQs 2301 * advance qid to derive correct sq mapped with QOS 2302 */ 2303 sq_idx = (qidx >= pf->hw.tx_queues) ? (qidx + pf->hw.xdp_queues) : qidx; 2304 2305 /* Check for minimum and maximum packet length */ 2306 if (skb->len <= ETH_HLEN || 2307 (!skb_shinfo(skb)->gso_size && skb->len > pf->tx_max_pktlen)) { 2308 dev_stats = &pf->hw.dev_stats; 2309 atomic_long_inc(&dev_stats->tx_discards); 2310 dev_kfree_skb(skb); 2311 return NETDEV_TX_OK; 2312 } 2313 2314 sq = &pf->qset.sq[sq_idx]; 2315 txq = netdev_get_tx_queue(netdev, qidx); 2316 2317 if (!otx2_sq_append_skb(pf, txq, sq, skb, qidx)) { 2318 netif_tx_stop_queue(txq); 2319 2320 /* Check again, incase SQBs got freed up */ 2321 smp_mb(); 2322 if (((sq->num_sqbs - *sq->aura_fc_addr) * sq->sqe_per_sqb) 2323 > sq->sqe_thresh) 2324 netif_tx_wake_queue(txq); 2325 2326 return NETDEV_TX_BUSY; 2327 } 2328 2329 return NETDEV_TX_OK; 2330 } 2331 2332 static int otx2_qos_select_htb_queue(struct otx2_nic *pf, struct sk_buff *skb, 2333 u16 htb_maj_id) 2334 { 2335 u16 classid; 2336 2337 if ((TC_H_MAJ(skb->priority) >> 16) == htb_maj_id) 2338 classid = TC_H_MIN(skb->priority); 2339 else 2340 classid = READ_ONCE(pf->qos.defcls); 2341 2342 if (!classid) 2343 return 0; 2344 2345 return otx2_get_txq_by_classid(pf, classid); 2346 } 2347 2348 u16 otx2_select_queue(struct net_device *netdev, struct sk_buff *skb, 2349 struct net_device *sb_dev) 2350 { 2351 struct otx2_nic *pf = netdev_priv(netdev); 2352 bool qos_enabled; 2353 #ifdef CONFIG_DCB 2354 u8 vlan_prio; 2355 #endif 2356 int txq; 2357 2358 qos_enabled = netdev->real_num_tx_queues > pf->hw.tx_queues; 2359 if (unlikely(qos_enabled)) { 2360 /* This smp_load_acquire() pairs with smp_store_release() in 2361 * otx2_qos_root_add() called from htb offload root creation 2362 */ 2363 u16 htb_maj_id = smp_load_acquire(&pf->qos.maj_id); 2364 2365 if (unlikely(htb_maj_id)) { 2366 txq = otx2_qos_select_htb_queue(pf, skb, htb_maj_id); 2367 if (txq > 0) 2368 return txq; 2369 goto process_pfc; 2370 } 2371 } 2372 2373 process_pfc: 2374 #ifdef CONFIG_DCB 2375 if (!skb_vlan_tag_present(skb)) 2376 goto pick_tx; 2377 2378 vlan_prio = skb->vlan_tci >> 13; 2379 if ((vlan_prio > pf->hw.tx_queues - 1) || 2380 !pf->pfc_alloc_status[vlan_prio]) 2381 goto pick_tx; 2382 2383 return vlan_prio; 2384 2385 pick_tx: 2386 #endif 2387 txq = netdev_pick_tx(netdev, skb, NULL); 2388 if (unlikely(qos_enabled)) 2389 return txq % pf->hw.tx_queues; 2390 2391 return txq; 2392 } 2393 EXPORT_SYMBOL(otx2_select_queue); 2394 2395 static netdev_features_t otx2_fix_features(struct net_device *dev, 2396 netdev_features_t features) 2397 { 2398 if (features & NETIF_F_HW_VLAN_CTAG_RX) 2399 features |= NETIF_F_HW_VLAN_STAG_RX; 2400 else 2401 features &= ~NETIF_F_HW_VLAN_STAG_RX; 2402 2403 return features; 2404 } 2405 2406 static void otx2_set_rx_mode(struct net_device *netdev) 2407 { 2408 struct otx2_nic *pf = netdev_priv(netdev); 2409 2410 queue_work(pf->otx2_wq, &pf->rx_mode_work); 2411 } 2412 2413 static void otx2_rx_mode_wrk_handler(struct work_struct *work) 2414 { 2415 struct otx2_nic *pf = container_of(work, struct otx2_nic, rx_mode_work); 2416 2417 otx2_do_set_rx_mode(pf); 2418 } 2419 2420 static int otx2_set_features(struct net_device *netdev, 2421 netdev_features_t features) 2422 { 2423 netdev_features_t changed = features ^ netdev->features; 2424 struct otx2_nic *pf = netdev_priv(netdev); 2425 2426 if ((changed & NETIF_F_LOOPBACK) && netif_running(netdev)) 2427 return otx2_cgx_config_loopback(pf, 2428 features & NETIF_F_LOOPBACK); 2429 2430 if ((changed & NETIF_F_HW_VLAN_CTAG_RX) && netif_running(netdev)) 2431 return otx2_enable_rxvlan(pf, 2432 features & NETIF_F_HW_VLAN_CTAG_RX); 2433 2434 if (changed & NETIF_F_HW_ESP) 2435 return cn10k_ipsec_ethtool_init(netdev, 2436 features & NETIF_F_HW_ESP); 2437 2438 return otx2_handle_ntuple_tc_features(netdev, features); 2439 } 2440 2441 static void otx2_reset_task(struct work_struct *work) 2442 { 2443 struct otx2_nic *pf = container_of(work, struct otx2_nic, reset_task); 2444 2445 if (!netif_running(pf->netdev)) 2446 return; 2447 2448 rtnl_lock(); 2449 otx2_stop(pf->netdev); 2450 pf->reset_count++; 2451 otx2_open(pf->netdev); 2452 netif_trans_update(pf->netdev); 2453 rtnl_unlock(); 2454 } 2455 2456 static int otx2_config_hw_rx_tstamp(struct otx2_nic *pfvf, bool enable) 2457 { 2458 struct msg_req *req; 2459 int err; 2460 2461 if (pfvf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED && enable) 2462 return 0; 2463 2464 mutex_lock(&pfvf->mbox.lock); 2465 if (enable) 2466 req = otx2_mbox_alloc_msg_cgx_ptp_rx_enable(&pfvf->mbox); 2467 else 2468 req = otx2_mbox_alloc_msg_cgx_ptp_rx_disable(&pfvf->mbox); 2469 if (!req) { 2470 mutex_unlock(&pfvf->mbox.lock); 2471 return -ENOMEM; 2472 } 2473 2474 err = otx2_sync_mbox_msg(&pfvf->mbox); 2475 if (err) { 2476 mutex_unlock(&pfvf->mbox.lock); 2477 return err; 2478 } 2479 2480 mutex_unlock(&pfvf->mbox.lock); 2481 if (enable) 2482 pfvf->flags |= OTX2_FLAG_RX_TSTAMP_ENABLED; 2483 else 2484 pfvf->flags &= ~OTX2_FLAG_RX_TSTAMP_ENABLED; 2485 return 0; 2486 } 2487 2488 static int otx2_config_hw_tx_tstamp(struct otx2_nic *pfvf, bool enable) 2489 { 2490 struct msg_req *req; 2491 int err; 2492 2493 if (pfvf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED && enable) 2494 return 0; 2495 2496 mutex_lock(&pfvf->mbox.lock); 2497 if (enable) 2498 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_enable(&pfvf->mbox); 2499 else 2500 req = otx2_mbox_alloc_msg_nix_lf_ptp_tx_disable(&pfvf->mbox); 2501 if (!req) { 2502 mutex_unlock(&pfvf->mbox.lock); 2503 return -ENOMEM; 2504 } 2505 2506 err = otx2_sync_mbox_msg(&pfvf->mbox); 2507 if (err) { 2508 mutex_unlock(&pfvf->mbox.lock); 2509 return err; 2510 } 2511 2512 mutex_unlock(&pfvf->mbox.lock); 2513 if (enable) 2514 pfvf->flags |= OTX2_FLAG_TX_TSTAMP_ENABLED; 2515 else 2516 pfvf->flags &= ~OTX2_FLAG_TX_TSTAMP_ENABLED; 2517 return 0; 2518 } 2519 2520 int otx2_config_hwtstamp_get(struct net_device *netdev, 2521 struct kernel_hwtstamp_config *config) 2522 { 2523 struct otx2_nic *pfvf = netdev_priv(netdev); 2524 2525 *config = pfvf->tstamp; 2526 return 0; 2527 } 2528 EXPORT_SYMBOL(otx2_config_hwtstamp_get); 2529 2530 int otx2_config_hwtstamp_set(struct net_device *netdev, 2531 struct kernel_hwtstamp_config *config, 2532 struct netlink_ext_ack *extack) 2533 { 2534 struct otx2_nic *pfvf = netdev_priv(netdev); 2535 2536 if (!pfvf->ptp) 2537 return -ENODEV; 2538 2539 switch (config->tx_type) { 2540 case HWTSTAMP_TX_OFF: 2541 if (pfvf->flags & OTX2_FLAG_PTP_ONESTEP_SYNC) 2542 pfvf->flags &= ~OTX2_FLAG_PTP_ONESTEP_SYNC; 2543 2544 cancel_delayed_work(&pfvf->ptp->synctstamp_work); 2545 otx2_config_hw_tx_tstamp(pfvf, false); 2546 break; 2547 case HWTSTAMP_TX_ONESTEP_SYNC: 2548 if (!test_bit(CN10K_PTP_ONESTEP, &pfvf->hw.cap_flag)) { 2549 NL_SET_ERR_MSG_MOD(extack, 2550 "One-step time stamping is not supported"); 2551 return -ERANGE; 2552 } 2553 pfvf->flags |= OTX2_FLAG_PTP_ONESTEP_SYNC; 2554 schedule_delayed_work(&pfvf->ptp->synctstamp_work, 2555 msecs_to_jiffies(500)); 2556 fallthrough; 2557 case HWTSTAMP_TX_ON: 2558 otx2_config_hw_tx_tstamp(pfvf, true); 2559 break; 2560 default: 2561 return -ERANGE; 2562 } 2563 2564 switch (config->rx_filter) { 2565 case HWTSTAMP_FILTER_NONE: 2566 otx2_config_hw_rx_tstamp(pfvf, false); 2567 break; 2568 case HWTSTAMP_FILTER_ALL: 2569 case HWTSTAMP_FILTER_SOME: 2570 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT: 2571 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC: 2572 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ: 2573 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT: 2574 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC: 2575 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ: 2576 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT: 2577 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC: 2578 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ: 2579 case HWTSTAMP_FILTER_PTP_V2_EVENT: 2580 case HWTSTAMP_FILTER_PTP_V2_SYNC: 2581 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ: 2582 otx2_config_hw_rx_tstamp(pfvf, true); 2583 config->rx_filter = HWTSTAMP_FILTER_ALL; 2584 break; 2585 default: 2586 return -ERANGE; 2587 } 2588 2589 pfvf->tstamp = *config; 2590 2591 return 0; 2592 } 2593 EXPORT_SYMBOL(otx2_config_hwtstamp_set); 2594 2595 static int otx2_do_set_vf_mac(struct otx2_nic *pf, int vf, const u8 *mac) 2596 { 2597 struct npc_get_field_status_req *freq; 2598 struct npc_get_field_status_rsp *frsp; 2599 struct npc_install_flow_req *req; 2600 int err; 2601 2602 mutex_lock(&pf->mbox.lock); 2603 2604 /* Skip installing the DMAC filter if the hardware parser profile 2605 * does not support DMAC extraction. 2606 */ 2607 freq = otx2_mbox_alloc_msg_npc_get_field_status(&pf->mbox); 2608 if (!freq) { 2609 err = -ENOMEM; 2610 goto out; 2611 } 2612 2613 freq->field = NPC_DMAC; 2614 err = otx2_sync_mbox_msg(&pf->mbox); 2615 if (err) 2616 goto out; 2617 2618 frsp = (struct npc_get_field_status_rsp *)otx2_mbox_get_rsp 2619 (&pf->mbox.mbox, 0, &freq->hdr); 2620 if (IS_ERR(frsp)) { 2621 err = PTR_ERR(frsp); 2622 goto out; 2623 } 2624 2625 if (!frsp->enable) { 2626 netdev_warn(pf->netdev, 2627 "VF %d MAC filter not installed: DMAC extraction not supported by parser profile\n", 2628 vf); 2629 err = -EOPNOTSUPP; 2630 goto out; 2631 } 2632 2633 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2634 if (!req) { 2635 err = -ENOMEM; 2636 goto out; 2637 } 2638 2639 ether_addr_copy(req->packet.dmac, mac); 2640 eth_broadcast_addr((u8 *)&req->mask.dmac); 2641 req->features = BIT_ULL(NPC_DMAC); 2642 req->channel = pf->hw.rx_chan_base; 2643 req->intf = NIX_INTF_RX; 2644 req->default_rule = 1; 2645 req->append = 1; 2646 req->vf = vf + 1; 2647 req->op = NIX_RX_ACTION_DEFAULT; 2648 2649 err = otx2_sync_mbox_msg(&pf->mbox); 2650 out: 2651 mutex_unlock(&pf->mbox.lock); 2652 return err; 2653 } 2654 2655 static int otx2_set_vf_mac(struct net_device *netdev, int vf, u8 *mac) 2656 { 2657 struct otx2_nic *pf = netdev_priv(netdev); 2658 struct pci_dev *pdev = pf->pdev; 2659 struct otx2_vf_config *config; 2660 int ret; 2661 2662 if (!netif_running(netdev)) 2663 return -EAGAIN; 2664 2665 if (vf >= pf->total_vfs) 2666 return -EINVAL; 2667 2668 if (!is_valid_ether_addr(mac)) 2669 return -EINVAL; 2670 2671 ret = otx2_do_set_vf_mac(pf, vf, mac); 2672 if (ret == 0) { 2673 config = &pf->vf_configs[vf]; 2674 ether_addr_copy(config->mac, mac); 2675 dev_info(&pdev->dev, "Load/Reload VF driver\n"); 2676 } 2677 2678 return ret; 2679 } 2680 2681 static int otx2_do_set_vf_vlan(struct otx2_nic *pf, int vf, u16 vlan, u8 qos, 2682 __be16 proto) 2683 { 2684 struct otx2_flow_config *flow_cfg = pf->flow_cfg; 2685 struct nix_vtag_config_rsp *vtag_rsp; 2686 struct npc_delete_flow_req *del_req; 2687 struct nix_vtag_config *vtag_req; 2688 struct npc_install_flow_req *req; 2689 struct otx2_vf_config *config; 2690 int err = 0; 2691 u32 idx; 2692 2693 config = &pf->vf_configs[vf]; 2694 2695 if (!vlan && !config->vlan) 2696 goto out; 2697 2698 mutex_lock(&pf->mbox.lock); 2699 2700 /* free old tx vtag entry */ 2701 if (config->vlan) { 2702 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2703 if (!vtag_req) { 2704 err = -ENOMEM; 2705 goto out; 2706 } 2707 vtag_req->cfg_type = 0; 2708 vtag_req->tx.free_vtag0 = 1; 2709 vtag_req->tx.vtag0_idx = config->tx_vtag_idx; 2710 2711 err = otx2_sync_mbox_msg(&pf->mbox); 2712 if (err) 2713 goto out; 2714 } 2715 2716 if (!vlan && config->vlan) { 2717 /* rx */ 2718 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2719 if (!del_req) { 2720 err = -ENOMEM; 2721 goto out; 2722 } 2723 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2724 del_req->entry = 2725 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2726 err = otx2_sync_mbox_msg(&pf->mbox); 2727 if (err) 2728 goto out; 2729 2730 /* tx */ 2731 del_req = otx2_mbox_alloc_msg_npc_delete_flow(&pf->mbox); 2732 if (!del_req) { 2733 err = -ENOMEM; 2734 goto out; 2735 } 2736 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2737 del_req->entry = 2738 flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2739 err = otx2_sync_mbox_msg(&pf->mbox); 2740 2741 goto out; 2742 } 2743 2744 /* rx */ 2745 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2746 if (!req) { 2747 err = -ENOMEM; 2748 goto out; 2749 } 2750 2751 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_RX_INDEX); 2752 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2753 req->packet.vlan_tci = htons(vlan); 2754 req->mask.vlan_tci = htons(VLAN_VID_MASK); 2755 /* af fills the destination mac addr */ 2756 eth_broadcast_addr((u8 *)&req->mask.dmac); 2757 req->features = BIT_ULL(NPC_OUTER_VID) | BIT_ULL(NPC_DMAC); 2758 req->channel = pf->hw.rx_chan_base; 2759 req->intf = NIX_INTF_RX; 2760 req->vf = vf + 1; 2761 req->op = NIX_RX_ACTION_DEFAULT; 2762 req->vtag0_valid = true; 2763 req->vtag0_type = NIX_AF_LFX_RX_VTAG_TYPE7; 2764 req->set_cntr = 1; 2765 2766 err = otx2_sync_mbox_msg(&pf->mbox); 2767 if (err) 2768 goto out; 2769 2770 /* tx */ 2771 vtag_req = otx2_mbox_alloc_msg_nix_vtag_cfg(&pf->mbox); 2772 if (!vtag_req) { 2773 err = -ENOMEM; 2774 goto out; 2775 } 2776 2777 /* configure tx vtag params */ 2778 vtag_req->vtag_size = VTAGSIZE_T4; 2779 vtag_req->cfg_type = 0; /* tx vlan cfg */ 2780 vtag_req->tx.cfg_vtag0 = 1; 2781 vtag_req->tx.vtag0 = ((u64)ntohs(proto) << 16) | vlan; 2782 2783 err = otx2_sync_mbox_msg(&pf->mbox); 2784 if (err) 2785 goto out; 2786 2787 vtag_rsp = (struct nix_vtag_config_rsp *)otx2_mbox_get_rsp 2788 (&pf->mbox.mbox, 0, &vtag_req->hdr); 2789 if (IS_ERR(vtag_rsp)) { 2790 err = PTR_ERR(vtag_rsp); 2791 goto out; 2792 } 2793 config->tx_vtag_idx = vtag_rsp->vtag0_idx; 2794 2795 req = otx2_mbox_alloc_msg_npc_install_flow(&pf->mbox); 2796 if (!req) { 2797 err = -ENOMEM; 2798 goto out; 2799 } 2800 2801 eth_zero_addr((u8 *)&req->mask.dmac); 2802 idx = ((vf * OTX2_PER_VF_VLAN_FLOWS) + OTX2_VF_VLAN_TX_INDEX); 2803 req->entry = flow_cfg->def_ent[flow_cfg->vf_vlan_offset + idx]; 2804 req->features = BIT_ULL(NPC_DMAC); 2805 req->channel = pf->hw.tx_chan_base; 2806 req->intf = NIX_INTF_TX; 2807 req->vf = vf + 1; 2808 req->op = NIX_TX_ACTIONOP_UCAST_DEFAULT; 2809 req->vtag0_def = vtag_rsp->vtag0_idx; 2810 req->vtag0_op = VTAG_INSERT; 2811 req->set_cntr = 1; 2812 2813 err = otx2_sync_mbox_msg(&pf->mbox); 2814 out: 2815 config->vlan = vlan; 2816 mutex_unlock(&pf->mbox.lock); 2817 return err; 2818 } 2819 2820 static int otx2_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, u8 qos, 2821 __be16 proto) 2822 { 2823 struct otx2_nic *pf = netdev_priv(netdev); 2824 struct pci_dev *pdev = pf->pdev; 2825 2826 if (!netif_running(netdev)) 2827 return -EAGAIN; 2828 2829 if (vf >= pci_num_vf(pdev)) 2830 return -EINVAL; 2831 2832 /* qos is currently unsupported */ 2833 if (vlan >= VLAN_N_VID || qos) 2834 return -EINVAL; 2835 2836 if (proto != htons(ETH_P_8021Q)) 2837 return -EPROTONOSUPPORT; 2838 2839 if (!(pf->flags & OTX2_FLAG_VF_VLAN_SUPPORT)) 2840 return -EOPNOTSUPP; 2841 2842 return otx2_do_set_vf_vlan(pf, vf, vlan, qos, proto); 2843 } 2844 2845 static int otx2_get_vf_config(struct net_device *netdev, int vf, 2846 struct ifla_vf_info *ivi) 2847 { 2848 struct otx2_nic *pf = netdev_priv(netdev); 2849 struct pci_dev *pdev = pf->pdev; 2850 struct otx2_vf_config *config; 2851 2852 if (!netif_running(netdev)) 2853 return -EAGAIN; 2854 2855 if (vf >= pci_num_vf(pdev)) 2856 return -EINVAL; 2857 2858 config = &pf->vf_configs[vf]; 2859 ivi->vf = vf; 2860 ether_addr_copy(ivi->mac, config->mac); 2861 ivi->vlan = config->vlan; 2862 ivi->trusted = config->trusted; 2863 2864 return 0; 2865 } 2866 2867 static int otx2_xdp_xmit_tx(struct otx2_nic *pf, struct xdp_frame *xdpf, 2868 int qidx) 2869 { 2870 u64 dma_addr; 2871 int err = 0; 2872 2873 dma_addr = otx2_dma_map_page(pf, virt_to_page(xdpf->data), 2874 offset_in_page(xdpf->data), xdpf->len, 2875 DMA_TO_DEVICE); 2876 if (dma_mapping_error(pf->dev, dma_addr)) 2877 return -ENOMEM; 2878 2879 err = otx2_xdp_sq_append_pkt(pf, xdpf, dma_addr, xdpf->len, 2880 qidx, OTX2_XDP_REDIRECT); 2881 if (!err) { 2882 otx2_dma_unmap_page(pf, dma_addr, xdpf->len, DMA_TO_DEVICE); 2883 xdp_return_frame(xdpf); 2884 return -ENOMEM; 2885 } 2886 return 0; 2887 } 2888 2889 static int otx2_xdp_xmit(struct net_device *netdev, int n, 2890 struct xdp_frame **frames, u32 flags) 2891 { 2892 struct otx2_nic *pf = netdev_priv(netdev); 2893 int qidx = smp_processor_id(); 2894 struct otx2_snd_queue *sq; 2895 int drops = 0, i; 2896 2897 if (!netif_running(netdev)) 2898 return -ENETDOWN; 2899 2900 qidx += pf->hw.tx_queues; 2901 sq = pf->xdp_prog ? &pf->qset.sq[qidx] : NULL; 2902 2903 /* Abort xmit if xdp queue is not */ 2904 if (unlikely(!sq)) 2905 return -ENXIO; 2906 2907 if (unlikely(flags & ~XDP_XMIT_FLAGS_MASK)) 2908 return -EINVAL; 2909 2910 for (i = 0; i < n; i++) { 2911 struct xdp_frame *xdpf = frames[i]; 2912 int err; 2913 2914 err = otx2_xdp_xmit_tx(pf, xdpf, qidx); 2915 if (err) 2916 drops++; 2917 } 2918 return n - drops; 2919 } 2920 2921 static int otx2_xdp_setup(struct otx2_nic *pf, struct bpf_prog *prog) 2922 { 2923 struct net_device *dev = pf->netdev; 2924 bool if_up = netif_running(pf->netdev); 2925 struct bpf_prog *old_prog; 2926 2927 if (prog && dev->mtu > MAX_XDP_MTU) { 2928 netdev_warn(dev, "Jumbo frames not yet supported with XDP\n"); 2929 return -EOPNOTSUPP; 2930 } 2931 2932 if (if_up) 2933 otx2_stop(pf->netdev); 2934 2935 old_prog = xchg(&pf->xdp_prog, prog); 2936 2937 if (old_prog) 2938 bpf_prog_put(old_prog); 2939 2940 if (pf->xdp_prog) 2941 bpf_prog_add(pf->xdp_prog, pf->hw.rx_queues - 1); 2942 2943 /* Network stack and XDP shared same rx queues. 2944 * Use separate tx queues for XDP and network stack. 2945 */ 2946 if (pf->xdp_prog) { 2947 pf->hw.xdp_queues = pf->hw.rx_queues; 2948 xdp_features_set_redirect_target(dev, false); 2949 } else { 2950 pf->hw.xdp_queues = 0; 2951 xdp_features_clear_redirect_target(dev); 2952 } 2953 2954 if (if_up) 2955 otx2_open(pf->netdev); 2956 2957 return 0; 2958 } 2959 2960 static int otx2_xdp(struct net_device *netdev, struct netdev_bpf *xdp) 2961 { 2962 struct otx2_nic *pf = netdev_priv(netdev); 2963 2964 switch (xdp->command) { 2965 case XDP_SETUP_PROG: 2966 return otx2_xdp_setup(pf, xdp->prog); 2967 case XDP_SETUP_XSK_POOL: 2968 return otx2_xsk_pool_setup(pf, xdp->xsk.pool, xdp->xsk.queue_id); 2969 default: 2970 return -EINVAL; 2971 } 2972 } 2973 2974 static int otx2_set_vf_permissions(struct otx2_nic *pf, int vf, 2975 int req_perm) 2976 { 2977 struct set_vf_perm *req; 2978 int rc; 2979 2980 mutex_lock(&pf->mbox.lock); 2981 req = otx2_mbox_alloc_msg_set_vf_perm(&pf->mbox); 2982 if (!req) { 2983 rc = -ENOMEM; 2984 goto out; 2985 } 2986 2987 /* Let AF reset VF permissions as sriov is disabled */ 2988 if (req_perm == OTX2_RESET_VF_PERM) { 2989 req->flags |= RESET_VF_PERM; 2990 } else if (req_perm == OTX2_TRUSTED_VF) { 2991 if (pf->vf_configs[vf].trusted) 2992 req->flags |= VF_TRUSTED; 2993 } 2994 2995 req->vf = vf; 2996 rc = otx2_sync_mbox_msg(&pf->mbox); 2997 out: 2998 mutex_unlock(&pf->mbox.lock); 2999 return rc; 3000 } 3001 3002 static int otx2_ndo_set_vf_trust(struct net_device *netdev, int vf, 3003 bool enable) 3004 { 3005 struct otx2_nic *pf = netdev_priv(netdev); 3006 struct pci_dev *pdev = pf->pdev; 3007 int rc; 3008 3009 if (vf >= pci_num_vf(pdev)) 3010 return -EINVAL; 3011 3012 if (pf->vf_configs[vf].trusted == enable) 3013 return 0; 3014 3015 pf->vf_configs[vf].trusted = enable; 3016 rc = otx2_set_vf_permissions(pf, vf, OTX2_TRUSTED_VF); 3017 3018 if (rc) { 3019 pf->vf_configs[vf].trusted = !enable; 3020 } else { 3021 netdev_info(pf->netdev, "VF %d is %strusted\n", 3022 vf, enable ? "" : "not "); 3023 otx2_set_rx_mode(netdev); 3024 } 3025 3026 return rc; 3027 } 3028 3029 static const struct net_device_ops otx2_netdev_ops = { 3030 .ndo_open = otx2_open, 3031 .ndo_stop = otx2_stop, 3032 .ndo_start_xmit = otx2_xmit, 3033 .ndo_select_queue = otx2_select_queue, 3034 .ndo_fix_features = otx2_fix_features, 3035 .ndo_set_mac_address = otx2_set_mac_address, 3036 .ndo_change_mtu = otx2_change_mtu, 3037 .ndo_set_rx_mode = otx2_set_rx_mode, 3038 .ndo_set_features = otx2_set_features, 3039 .ndo_tx_timeout = otx2_tx_timeout, 3040 .ndo_get_stats64 = otx2_get_stats64, 3041 .ndo_set_vf_mac = otx2_set_vf_mac, 3042 .ndo_set_vf_vlan = otx2_set_vf_vlan, 3043 .ndo_get_vf_config = otx2_get_vf_config, 3044 .ndo_bpf = otx2_xdp, 3045 .ndo_xsk_wakeup = otx2_xsk_wakeup, 3046 .ndo_xdp_xmit = otx2_xdp_xmit, 3047 .ndo_setup_tc = otx2_setup_tc, 3048 .ndo_set_vf_trust = otx2_ndo_set_vf_trust, 3049 .ndo_hwtstamp_get = otx2_config_hwtstamp_get, 3050 .ndo_hwtstamp_set = otx2_config_hwtstamp_set, 3051 }; 3052 3053 int otx2_wq_init(struct otx2_nic *pf) 3054 { 3055 pf->otx2_wq = create_singlethread_workqueue("otx2_wq"); 3056 if (!pf->otx2_wq) 3057 return -ENOMEM; 3058 3059 INIT_WORK(&pf->rx_mode_work, otx2_rx_mode_wrk_handler); 3060 INIT_WORK(&pf->reset_task, otx2_reset_task); 3061 return 0; 3062 } 3063 3064 int otx2_check_pf_usable(struct otx2_nic *nic) 3065 { 3066 u64 rev; 3067 3068 rev = otx2_read64(nic, RVU_PF_BLOCK_ADDRX_DISC(BLKADDR_RVUM)); 3069 rev = (rev >> 12) & 0xFF; 3070 /* Check if AF has setup revision for RVUM block, 3071 * otherwise this driver probe should be deferred 3072 * until AF driver comes up. 3073 */ 3074 if (!rev) 3075 return dev_err_probe(nic->dev, -EPROBE_DEFER, 3076 "AF is not initialized, deferring probe\n"); 3077 return 0; 3078 } 3079 3080 int otx2_realloc_msix_vectors(struct otx2_nic *pf) 3081 { 3082 struct otx2_hw *hw = &pf->hw; 3083 int num_vec, err; 3084 3085 /* Skip NPA vectors. Representors only use CINT vectors, so limit 3086 * the budget to that range. For PF/VF, allocate the full NIX LF 3087 * interrupt range (QINT, CINT, GINT, ERR and POISON vectors). 3088 */ 3089 num_vec = hw->nix_msixoff; 3090 if (pf->flags & OTX2_FLAG_REP_MODE_ENABLED) 3091 num_vec += NIX_LF_CINT_VEC_START + hw->max_queues; 3092 else 3093 num_vec += NIX_LF_POISON_VEC + 1; 3094 3095 otx2_disable_mbox_intr(pf); 3096 pci_free_irq_vectors(hw->pdev); 3097 err = pci_alloc_irq_vectors(hw->pdev, num_vec, num_vec, PCI_IRQ_MSIX); 3098 if (err < 0) { 3099 dev_err(pf->dev, "%s: Failed to realloc %d IRQ vectors\n", 3100 __func__, num_vec); 3101 return err; 3102 } 3103 3104 return otx2_register_mbox_intr(pf, false); 3105 } 3106 3107 static int otx2_sriov_vfcfg_init(struct otx2_nic *pf) 3108 { 3109 int i; 3110 3111 pf->vf_configs = devm_kcalloc(pf->dev, pf->total_vfs, 3112 sizeof(struct otx2_vf_config), 3113 GFP_KERNEL); 3114 if (!pf->vf_configs) 3115 return -ENOMEM; 3116 3117 for (i = 0; i < pf->total_vfs; i++) { 3118 pf->vf_configs[i].pf = pf; 3119 pf->vf_configs[i].intf_down = true; 3120 pf->vf_configs[i].trusted = false; 3121 INIT_DELAYED_WORK(&pf->vf_configs[i].link_event_work, 3122 otx2_vf_link_event_task); 3123 } 3124 3125 return 0; 3126 } 3127 3128 static void otx2_sriov_vfcfg_cleanup(struct otx2_nic *pf) 3129 { 3130 int i; 3131 3132 if (!pf->vf_configs) 3133 return; 3134 3135 for (i = 0; i < pf->total_vfs; i++) { 3136 cancel_delayed_work_sync(&pf->vf_configs[i].link_event_work); 3137 otx2_set_vf_permissions(pf, i, OTX2_RESET_VF_PERM); 3138 } 3139 } 3140 3141 int otx2_init_rsrc(struct pci_dev *pdev, struct otx2_nic *pf) 3142 { 3143 struct device *dev = &pdev->dev; 3144 struct otx2_hw *hw = &pf->hw; 3145 int num_vec, err; 3146 3147 num_vec = pci_msix_vec_count(pdev); 3148 hw->irq_name = devm_kmalloc_array(&hw->pdev->dev, num_vec, NAME_SIZE, 3149 GFP_KERNEL); 3150 if (!hw->irq_name) 3151 return -ENOMEM; 3152 3153 hw->affinity_mask = devm_kcalloc(&hw->pdev->dev, num_vec, 3154 sizeof(cpumask_var_t), GFP_KERNEL); 3155 if (!hw->affinity_mask) 3156 return -ENOMEM; 3157 3158 /* Map CSRs */ 3159 pf->reg_base = pcim_iomap(pdev, PCI_CFG_REG_BAR_NUM, 0); 3160 if (!pf->reg_base) { 3161 dev_err(dev, "Unable to map physical function CSRs, aborting\n"); 3162 return -ENOMEM; 3163 } 3164 3165 err = otx2_check_pf_usable(pf); 3166 if (err) 3167 return err; 3168 3169 if (!is_cn20k(pf->pdev)) 3170 err = pci_alloc_irq_vectors(hw->pdev, RVU_PF_INT_VEC_CNT, 3171 RVU_PF_INT_VEC_CNT, PCI_IRQ_MSIX); 3172 else 3173 err = pci_alloc_irq_vectors(hw->pdev, RVU_MBOX_PF_INT_VEC_CNT, 3174 RVU_MBOX_PF_INT_VEC_CNT, 3175 PCI_IRQ_MSIX); 3176 if (err < 0) { 3177 dev_err(dev, "%s: Failed to alloc %d IRQ vectors\n", 3178 __func__, num_vec); 3179 return err; 3180 } 3181 3182 otx2_setup_dev_hw_settings(pf); 3183 3184 if (is_cn20k(pf->pdev)) 3185 cn20k_init(pf); 3186 else 3187 otx2_init_hw_ops(pf); 3188 3189 /* Init PF <=> AF mailbox stuff */ 3190 err = otx2_pfaf_mbox_init(pf); 3191 if (err) 3192 goto err_free_irq_vectors; 3193 3194 /* Register mailbox interrupt */ 3195 err = otx2_register_mbox_intr(pf, true); 3196 if (err) 3197 goto err_mbox_destroy; 3198 3199 /* Request AF to attach NPA and NIX LFs to this PF. 3200 * NIX and NPA LFs are needed for this PF to function as a NIC. 3201 */ 3202 err = otx2_attach_npa_nix(pf); 3203 if (err) 3204 goto err_disable_mbox_intr; 3205 3206 err = otx2_realloc_msix_vectors(pf); 3207 if (err) 3208 goto err_detach_rsrc; 3209 3210 err = cn10k_lmtst_init(pf); 3211 if (err) 3212 goto err_detach_rsrc; 3213 3214 return 0; 3215 3216 err_detach_rsrc: 3217 if (pf->hw.lmt_info) 3218 free_percpu(pf->hw.lmt_info); 3219 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3220 qmem_free(pf->dev, pf->dync_lmt); 3221 otx2_detach_resources(&pf->mbox); 3222 err_disable_mbox_intr: 3223 otx2_disable_mbox_intr(pf); 3224 err_mbox_destroy: 3225 otx2_pfaf_mbox_destroy(pf); 3226 err_free_irq_vectors: 3227 pci_free_irq_vectors(hw->pdev); 3228 3229 return err; 3230 } 3231 EXPORT_SYMBOL(otx2_init_rsrc); 3232 3233 static int otx2_probe(struct pci_dev *pdev, const struct pci_device_id *id) 3234 { 3235 struct device *dev = &pdev->dev; 3236 int err, qcount, qos_txqs; 3237 struct net_device *netdev; 3238 struct otx2_nic *pf; 3239 struct otx2_hw *hw; 3240 3241 err = pcim_enable_device(pdev); 3242 if (err) { 3243 dev_err(dev, "Failed to enable PCI device\n"); 3244 return err; 3245 } 3246 3247 err = pcim_request_all_regions(pdev, DRV_NAME); 3248 if (err) { 3249 dev_err(dev, "PCI request regions failed 0x%x\n", err); 3250 return err; 3251 } 3252 3253 err = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(48)); 3254 if (err) { 3255 dev_err(dev, "DMA mask config failed, abort\n"); 3256 return err; 3257 } 3258 3259 pci_set_master(pdev); 3260 3261 /* Set number of queues */ 3262 qcount = min_t(int, num_online_cpus(), OTX2_MAX_CQ_CNT); 3263 qos_txqs = min_t(int, qcount, OTX2_QOS_MAX_LEAF_NODES); 3264 3265 netdev = alloc_etherdev_mqs(sizeof(*pf), qcount + qos_txqs, qcount); 3266 if (!netdev) 3267 return -ENOMEM; 3268 3269 pci_set_drvdata(pdev, netdev); 3270 SET_NETDEV_DEV(netdev, &pdev->dev); 3271 pf = netdev_priv(netdev); 3272 pf->netdev = netdev; 3273 pf->pdev = pdev; 3274 pf->dev = dev; 3275 pf->total_vfs = pci_sriov_get_totalvfs(pdev); 3276 pf->flags |= OTX2_FLAG_INTF_DOWN; 3277 3278 hw = &pf->hw; 3279 hw->pdev = pdev; 3280 hw->rx_queues = qcount; 3281 hw->tx_queues = qcount; 3282 hw->non_qos_queues = qcount; 3283 hw->max_queues = qcount; 3284 hw->rbuf_len = OTX2_DEFAULT_RBUF_LEN; 3285 /* Use CQE of 128 byte descriptor size by default */ 3286 hw->xqe_size = 128; 3287 3288 err = otx2_init_rsrc(pdev, pf); 3289 if (err) 3290 goto err_free_netdev; 3291 3292 err = otx2_set_real_num_queues(netdev, hw->tx_queues, hw->rx_queues); 3293 if (err) 3294 goto err_detach_rsrc; 3295 3296 /* Assign default mac address */ 3297 otx2_get_mac_from_af(netdev); 3298 3299 /* Don't check for error. Proceed without ptp */ 3300 otx2_ptp_init(pf); 3301 3302 /* NPA's pool is a stack to which SW frees buffer pointers via Aura. 3303 * HW allocates buffer pointer from stack and uses it for DMA'ing 3304 * ingress packet. In some scenarios HW can free back allocated buffer 3305 * pointers to pool. This makes it impossible for SW to maintain a 3306 * parallel list where physical addresses of buffer pointers (IOVAs) 3307 * given to HW can be saved for later reference. 3308 * 3309 * So the only way to convert Rx packet's buffer address is to use 3310 * IOMMU's iova_to_phys() handler which translates the address by 3311 * walking through the translation tables. 3312 */ 3313 pf->iommu_domain = iommu_get_domain_for_dev(dev); 3314 3315 netdev->hw_features = (NETIF_F_RXCSUM | NETIF_F_IP_CSUM | 3316 NETIF_F_IPV6_CSUM | NETIF_F_RXHASH | 3317 NETIF_F_SG | NETIF_F_TSO | NETIF_F_TSO6 | 3318 NETIF_F_GSO_UDP_L4); 3319 netdev->features |= netdev->hw_features; 3320 3321 err = otx2_mcam_flow_init(pf); 3322 if (err) 3323 goto err_ptp_destroy; 3324 3325 otx2_set_hw_capabilities(pf); 3326 3327 err = cn10k_mcs_init(pf); 3328 if (err) 3329 goto err_del_mcam_entries; 3330 3331 if (pf->flags & OTX2_FLAG_NTUPLE_SUPPORT) 3332 netdev->hw_features |= NETIF_F_NTUPLE; 3333 3334 if (pf->flags & OTX2_FLAG_UCAST_FLTR_SUPPORT) 3335 netdev->priv_flags |= IFF_UNICAST_FLT; 3336 3337 /* Support TSO on tag interface */ 3338 netdev->vlan_features |= netdev->features; 3339 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX | 3340 NETIF_F_HW_VLAN_STAG_TX; 3341 if (pf->flags & OTX2_FLAG_RX_VLAN_SUPPORT) 3342 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX | 3343 NETIF_F_HW_VLAN_STAG_RX; 3344 netdev->features |= netdev->hw_features; 3345 3346 /* HW supports tc offload but mutually exclusive with n-tuple filters */ 3347 if (pf->flags & OTX2_FLAG_TC_FLOWER_SUPPORT) 3348 netdev->hw_features |= NETIF_F_HW_TC; 3349 3350 netdev->hw_features |= NETIF_F_LOOPBACK | NETIF_F_RXALL; 3351 3352 netif_set_tso_max_segs(netdev, OTX2_MAX_GSO_SEGS); 3353 netdev->watchdog_timeo = OTX2_TX_TIMEOUT; 3354 3355 netdev->netdev_ops = &otx2_netdev_ops; 3356 netdev->xdp_features = NETDEV_XDP_ACT_BASIC | NETDEV_XDP_ACT_REDIRECT | 3357 NETDEV_XDP_ACT_NDO_XMIT | 3358 NETDEV_XDP_ACT_XSK_ZEROCOPY; 3359 3360 netdev->min_mtu = OTX2_MIN_MTU; 3361 netdev->max_mtu = otx2_get_max_mtu(pf); 3362 hw->max_mtu = netdev->max_mtu; 3363 3364 /* reset CGX/RPM MAC stats */ 3365 otx2_reset_mac_stats(pf); 3366 3367 err = cn10k_ipsec_init(netdev); 3368 if (err) 3369 goto err_mcs_free; 3370 3371 err = register_netdev(netdev); 3372 if (err) { 3373 dev_err(dev, "Failed to register netdevice\n"); 3374 goto err_ipsec_clean; 3375 } 3376 3377 err = otx2_wq_init(pf); 3378 if (err) 3379 goto err_unreg_netdev; 3380 3381 otx2_set_ethtool_ops(netdev); 3382 3383 err = otx2_init_tc(pf); 3384 if (err) 3385 goto err_mcam_flow_del; 3386 3387 err = otx2_register_dl(pf); 3388 if (err) 3389 goto err_mcam_flow_del; 3390 3391 /* Initialize SR-IOV resources */ 3392 err = otx2_sriov_vfcfg_init(pf); 3393 if (err) 3394 goto err_pf_sriov_init; 3395 3396 /* Enable link notifications */ 3397 otx2_cgx_config_linkevents(pf, true); 3398 3399 pf->af_xdp_zc_qidx = bitmap_zalloc(qcount, GFP_KERNEL); 3400 if (!pf->af_xdp_zc_qidx) { 3401 err = -ENOMEM; 3402 goto err_sriov_cleannup; 3403 } 3404 3405 #ifdef CONFIG_DCB 3406 err = otx2_dcbnl_set_ops(netdev); 3407 if (err) 3408 goto err_free_zc_bmap; 3409 #endif 3410 3411 otx2_qos_init(pf, qos_txqs); 3412 3413 return 0; 3414 3415 #ifdef CONFIG_DCB 3416 err_free_zc_bmap: 3417 bitmap_free(pf->af_xdp_zc_qidx); 3418 #endif 3419 err_sriov_cleannup: 3420 otx2_sriov_vfcfg_cleanup(pf); 3421 err_pf_sriov_init: 3422 otx2_unregister_dl(pf); 3423 otx2_shutdown_tc(pf); 3424 err_mcam_flow_del: 3425 otx2_mcam_flow_del(pf); 3426 err_unreg_netdev: 3427 unregister_netdev(netdev); 3428 err_ipsec_clean: 3429 cn10k_ipsec_clean(pf); 3430 err_mcs_free: 3431 cn10k_mcs_free(pf); 3432 err_del_mcam_entries: 3433 otx2_mcam_flow_del(pf); 3434 err_ptp_destroy: 3435 otx2_ptp_destroy(pf); 3436 err_detach_rsrc: 3437 if (pf->hw.lmt_info) 3438 free_percpu(pf->hw.lmt_info); 3439 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3440 qmem_free(pf->dev, pf->dync_lmt); 3441 otx2_detach_resources(&pf->mbox); 3442 otx2_disable_mbox_intr(pf); 3443 otx2_pfaf_mbox_destroy(pf); 3444 pci_free_irq_vectors(hw->pdev); 3445 err_free_netdev: 3446 pci_set_drvdata(pdev, NULL); 3447 free_netdev(netdev); 3448 return err; 3449 } 3450 3451 static void otx2_vf_link_event_task(struct work_struct *work) 3452 { 3453 struct otx2_vf_config *config; 3454 struct cgx_link_info_msg *req; 3455 struct mbox_msghdr *msghdr; 3456 struct delayed_work *dwork; 3457 struct otx2_nic *pf; 3458 int vf_idx; 3459 3460 config = container_of(work, struct otx2_vf_config, 3461 link_event_work.work); 3462 vf_idx = config - config->pf->vf_configs; 3463 pf = config->pf; 3464 3465 if (config->intf_down) 3466 return; 3467 3468 mutex_lock(&pf->mbox.lock); 3469 3470 dwork = &config->link_event_work; 3471 3472 if (!otx2_mbox_wait_for_zero(&pf->mbox_pfvf[0].mbox_up, vf_idx)) { 3473 schedule_delayed_work(dwork, msecs_to_jiffies(100)); 3474 mutex_unlock(&pf->mbox.lock); 3475 return; 3476 } 3477 3478 msghdr = otx2_mbox_alloc_msg_rsp(&pf->mbox_pfvf[0].mbox_up, vf_idx, 3479 sizeof(*req), sizeof(struct msg_rsp)); 3480 if (!msghdr) { 3481 dev_err(pf->dev, "Failed to create VF%d link event\n", vf_idx); 3482 mutex_unlock(&pf->mbox.lock); 3483 return; 3484 } 3485 3486 req = (struct cgx_link_info_msg *)msghdr; 3487 req->hdr.id = MBOX_MSG_CGX_LINK_EVENT; 3488 req->hdr.sig = OTX2_MBOX_REQ_SIG; 3489 req->hdr.pcifunc = pf->pcifunc; 3490 memcpy(&req->link_info, &pf->linfo, sizeof(req->link_info)); 3491 3492 otx2_mbox_wait_for_zero(&pf->mbox_pfvf[0].mbox_up, vf_idx); 3493 3494 otx2_sync_mbox_up_msg(&pf->mbox_pfvf[0], vf_idx); 3495 3496 mutex_unlock(&pf->mbox.lock); 3497 } 3498 3499 static int otx2_sriov_enable(struct pci_dev *pdev, int numvfs) 3500 { 3501 struct net_device *netdev = pci_get_drvdata(pdev); 3502 struct otx2_nic *pf = netdev_priv(netdev); 3503 int ret; 3504 3505 /* Init PF <=> VF mailbox stuff */ 3506 ret = otx2_pfvf_mbox_init(pf, numvfs); 3507 if (ret) 3508 return ret; 3509 3510 ret = otx2_register_pfvf_mbox_intr(pf, numvfs); 3511 if (ret) 3512 goto free_mbox; 3513 3514 ret = otx2_pf_flr_init(pf, numvfs); 3515 if (ret) 3516 goto free_intr; 3517 3518 ret = otx2_register_flr_me_intr(pf, numvfs); 3519 if (ret) 3520 goto free_flr; 3521 3522 ret = pci_enable_sriov(pdev, numvfs); 3523 if (ret) 3524 goto free_flr_intr; 3525 3526 return numvfs; 3527 free_flr_intr: 3528 otx2_disable_flr_me_intr(pf); 3529 free_flr: 3530 otx2_flr_wq_destroy(pf); 3531 free_intr: 3532 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3533 free_mbox: 3534 otx2_pfvf_mbox_destroy(pf); 3535 return ret; 3536 } 3537 3538 static int otx2_sriov_disable(struct pci_dev *pdev) 3539 { 3540 struct net_device *netdev = pci_get_drvdata(pdev); 3541 struct otx2_nic *pf = netdev_priv(netdev); 3542 int numvfs = pci_num_vf(pdev); 3543 3544 if (!numvfs) 3545 return 0; 3546 3547 pci_disable_sriov(pdev); 3548 3549 otx2_disable_flr_me_intr(pf); 3550 otx2_flr_wq_destroy(pf); 3551 otx2_disable_pfvf_mbox_intr(pf, numvfs); 3552 otx2_pfvf_mbox_destroy(pf); 3553 3554 return 0; 3555 } 3556 3557 static int otx2_sriov_configure(struct pci_dev *pdev, int numvfs) 3558 { 3559 if (numvfs == 0) 3560 return otx2_sriov_disable(pdev); 3561 else 3562 return otx2_sriov_enable(pdev, numvfs); 3563 } 3564 3565 static void otx2_ndc_sync(struct otx2_nic *pf) 3566 { 3567 struct mbox *mbox = &pf->mbox; 3568 struct ndc_sync_op *req; 3569 3570 mutex_lock(&mbox->lock); 3571 3572 req = otx2_mbox_alloc_msg_ndc_sync_op(mbox); 3573 if (!req) { 3574 mutex_unlock(&mbox->lock); 3575 return; 3576 } 3577 3578 req->nix_lf_tx_sync = 1; 3579 req->nix_lf_rx_sync = 1; 3580 req->npa_lf_sync = 1; 3581 3582 if (otx2_sync_mbox_msg(mbox)) 3583 dev_err(pf->dev, "NDC sync operation failed\n"); 3584 3585 mutex_unlock(&mbox->lock); 3586 } 3587 3588 static void otx2_remove(struct pci_dev *pdev) 3589 { 3590 struct net_device *netdev = pci_get_drvdata(pdev); 3591 struct otx2_nic *pf; 3592 3593 if (!netdev) 3594 return; 3595 3596 pf = netdev_priv(netdev); 3597 3598 pf->flags |= OTX2_FLAG_PF_SHUTDOWN; 3599 3600 if (pf->flags & OTX2_FLAG_TX_TSTAMP_ENABLED) 3601 otx2_config_hw_tx_tstamp(pf, false); 3602 if (pf->flags & OTX2_FLAG_RX_TSTAMP_ENABLED) 3603 otx2_config_hw_rx_tstamp(pf, false); 3604 3605 /* Disable 802.3x pause frames */ 3606 if (pf->flags & OTX2_FLAG_RX_PAUSE_ENABLED || 3607 (pf->flags & OTX2_FLAG_TX_PAUSE_ENABLED)) { 3608 pf->flags &= ~OTX2_FLAG_RX_PAUSE_ENABLED; 3609 pf->flags &= ~OTX2_FLAG_TX_PAUSE_ENABLED; 3610 otx2_config_pause_frm(pf); 3611 } 3612 3613 #ifdef CONFIG_DCB 3614 /* Disable PFC config */ 3615 if (pf->pfc_en) { 3616 pf->pfc_en = 0; 3617 otx2_config_priority_flow_ctrl(pf); 3618 } 3619 #endif 3620 cancel_work_sync(&pf->reset_task); 3621 /* Disable link notifications */ 3622 otx2_cgx_config_linkevents(pf, false); 3623 3624 otx2_unregister_dl(pf); 3625 unregister_netdev(netdev); 3626 cn10k_ipsec_clean(pf); 3627 cn10k_mcs_free(pf); 3628 otx2_sriov_disable(pf->pdev); 3629 otx2_sriov_vfcfg_cleanup(pf); 3630 if (pf->otx2_wq) 3631 destroy_workqueue(pf->otx2_wq); 3632 3633 otx2_ptp_destroy(pf); 3634 otx2_mcam_flow_del(pf); 3635 otx2_shutdown_tc(pf); 3636 otx2_shutdown_qos(pf); 3637 otx2_ndc_sync(pf); 3638 otx2_detach_resources(&pf->mbox); 3639 if (pf->hw.lmt_info) 3640 free_percpu(pf->hw.lmt_info); 3641 if (test_bit(CN10K_LMTST, &pf->hw.cap_flag)) 3642 qmem_free(pf->dev, pf->dync_lmt); 3643 otx2_disable_mbox_intr(pf); 3644 otx2_pfaf_mbox_destroy(pf); 3645 pci_free_irq_vectors(pf->pdev); 3646 bitmap_free(pf->af_xdp_zc_qidx); 3647 pci_set_drvdata(pdev, NULL); 3648 free_netdev(netdev); 3649 } 3650 3651 static struct pci_driver otx2_pf_driver = { 3652 .name = DRV_NAME, 3653 .id_table = otx2_pf_id_table, 3654 .probe = otx2_probe, 3655 .shutdown = otx2_remove, 3656 .remove = otx2_remove, 3657 .sriov_configure = otx2_sriov_configure 3658 }; 3659 3660 static int __init otx2_rvupf_init_module(void) 3661 { 3662 pr_info("%s: %s\n", DRV_NAME, DRV_STRING); 3663 3664 return pci_register_driver(&otx2_pf_driver); 3665 } 3666 3667 static void __exit otx2_rvupf_cleanup_module(void) 3668 { 3669 pci_unregister_driver(&otx2_pf_driver); 3670 } 3671 3672 module_init(otx2_rvupf_init_module); 3673 module_exit(otx2_rvupf_cleanup_module); 3674