1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4 #include <linux/ip.h>
5 #include <linux/sort.h>
6 #include <linux/udp.h>
7
8 #include "cam.h"
9 #include "chan.h"
10 #include "coex.h"
11 #include "core.h"
12 #include "efuse.h"
13 #include "fw.h"
14 #include "mac.h"
15 #include "phy.h"
16 #include "ps.h"
17 #include "reg.h"
18 #include "sar.h"
19 #include "ser.h"
20 #include "txrx.h"
21 #include "util.h"
22 #include "wow.h"
23
24 static bool rtw89_disable_ps_mode;
25 module_param_named(disable_ps_mode, rtw89_disable_ps_mode, bool, 0644);
26 MODULE_PARM_DESC(disable_ps_mode, "Set Y to disable low power mode");
27
28 #define RTW89_DEF_CHAN(_freq, _hw_val, _flags, _band) \
29 { .center_freq = _freq, .hw_value = _hw_val, .flags = _flags, .band = _band, }
30 #define RTW89_DEF_CHAN_2G(_freq, _hw_val) \
31 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_2GHZ)
32 #define RTW89_DEF_CHAN_5G(_freq, _hw_val) \
33 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_5GHZ)
34 #define RTW89_DEF_CHAN_5G_NO_HT40MINUS(_freq, _hw_val) \
35 RTW89_DEF_CHAN(_freq, _hw_val, IEEE80211_CHAN_NO_HT40MINUS, NL80211_BAND_5GHZ)
36 #define RTW89_DEF_CHAN_6G(_freq, _hw_val) \
37 RTW89_DEF_CHAN(_freq, _hw_val, 0, NL80211_BAND_6GHZ)
38
39 static struct ieee80211_channel rtw89_channels_2ghz[] = {
40 RTW89_DEF_CHAN_2G(2412, 1),
41 RTW89_DEF_CHAN_2G(2417, 2),
42 RTW89_DEF_CHAN_2G(2422, 3),
43 RTW89_DEF_CHAN_2G(2427, 4),
44 RTW89_DEF_CHAN_2G(2432, 5),
45 RTW89_DEF_CHAN_2G(2437, 6),
46 RTW89_DEF_CHAN_2G(2442, 7),
47 RTW89_DEF_CHAN_2G(2447, 8),
48 RTW89_DEF_CHAN_2G(2452, 9),
49 RTW89_DEF_CHAN_2G(2457, 10),
50 RTW89_DEF_CHAN_2G(2462, 11),
51 RTW89_DEF_CHAN_2G(2467, 12),
52 RTW89_DEF_CHAN_2G(2472, 13),
53 RTW89_DEF_CHAN_2G(2484, 14),
54 };
55
56 static struct ieee80211_channel rtw89_channels_5ghz[] = {
57 RTW89_DEF_CHAN_5G(5180, 36),
58 RTW89_DEF_CHAN_5G(5200, 40),
59 RTW89_DEF_CHAN_5G(5220, 44),
60 RTW89_DEF_CHAN_5G(5240, 48),
61 RTW89_DEF_CHAN_5G(5260, 52),
62 RTW89_DEF_CHAN_5G(5280, 56),
63 RTW89_DEF_CHAN_5G(5300, 60),
64 RTW89_DEF_CHAN_5G(5320, 64),
65 RTW89_DEF_CHAN_5G(5500, 100),
66 RTW89_DEF_CHAN_5G(5520, 104),
67 RTW89_DEF_CHAN_5G(5540, 108),
68 RTW89_DEF_CHAN_5G(5560, 112),
69 RTW89_DEF_CHAN_5G(5580, 116),
70 RTW89_DEF_CHAN_5G(5600, 120),
71 RTW89_DEF_CHAN_5G(5620, 124),
72 RTW89_DEF_CHAN_5G(5640, 128),
73 RTW89_DEF_CHAN_5G(5660, 132),
74 RTW89_DEF_CHAN_5G(5680, 136),
75 RTW89_DEF_CHAN_5G(5700, 140),
76 RTW89_DEF_CHAN_5G(5720, 144),
77 RTW89_DEF_CHAN_5G(5745, 149),
78 RTW89_DEF_CHAN_5G(5765, 153),
79 RTW89_DEF_CHAN_5G(5785, 157),
80 RTW89_DEF_CHAN_5G(5805, 161),
81 RTW89_DEF_CHAN_5G_NO_HT40MINUS(5825, 165),
82 RTW89_DEF_CHAN_5G(5845, 169),
83 RTW89_DEF_CHAN_5G(5865, 173),
84 RTW89_DEF_CHAN_5G(5885, 177),
85 };
86
87 static_assert(RTW89_5GHZ_UNII4_START_INDEX + RTW89_5GHZ_UNII4_CHANNEL_NUM ==
88 ARRAY_SIZE(rtw89_channels_5ghz));
89
90 static struct ieee80211_channel rtw89_channels_6ghz[] = {
91 RTW89_DEF_CHAN_6G(5955, 1),
92 RTW89_DEF_CHAN_6G(5975, 5),
93 RTW89_DEF_CHAN_6G(5995, 9),
94 RTW89_DEF_CHAN_6G(6015, 13),
95 RTW89_DEF_CHAN_6G(6035, 17),
96 RTW89_DEF_CHAN_6G(6055, 21),
97 RTW89_DEF_CHAN_6G(6075, 25),
98 RTW89_DEF_CHAN_6G(6095, 29),
99 RTW89_DEF_CHAN_6G(6115, 33),
100 RTW89_DEF_CHAN_6G(6135, 37),
101 RTW89_DEF_CHAN_6G(6155, 41),
102 RTW89_DEF_CHAN_6G(6175, 45),
103 RTW89_DEF_CHAN_6G(6195, 49),
104 RTW89_DEF_CHAN_6G(6215, 53),
105 RTW89_DEF_CHAN_6G(6235, 57),
106 RTW89_DEF_CHAN_6G(6255, 61),
107 RTW89_DEF_CHAN_6G(6275, 65),
108 RTW89_DEF_CHAN_6G(6295, 69),
109 RTW89_DEF_CHAN_6G(6315, 73),
110 RTW89_DEF_CHAN_6G(6335, 77),
111 RTW89_DEF_CHAN_6G(6355, 81),
112 RTW89_DEF_CHAN_6G(6375, 85),
113 RTW89_DEF_CHAN_6G(6395, 89),
114 RTW89_DEF_CHAN_6G(6415, 93),
115 RTW89_DEF_CHAN_6G(6435, 97),
116 RTW89_DEF_CHAN_6G(6455, 101),
117 RTW89_DEF_CHAN_6G(6475, 105),
118 RTW89_DEF_CHAN_6G(6495, 109),
119 RTW89_DEF_CHAN_6G(6515, 113),
120 RTW89_DEF_CHAN_6G(6535, 117),
121 RTW89_DEF_CHAN_6G(6555, 121),
122 RTW89_DEF_CHAN_6G(6575, 125),
123 RTW89_DEF_CHAN_6G(6595, 129),
124 RTW89_DEF_CHAN_6G(6615, 133),
125 RTW89_DEF_CHAN_6G(6635, 137),
126 RTW89_DEF_CHAN_6G(6655, 141),
127 RTW89_DEF_CHAN_6G(6675, 145),
128 RTW89_DEF_CHAN_6G(6695, 149),
129 RTW89_DEF_CHAN_6G(6715, 153),
130 RTW89_DEF_CHAN_6G(6735, 157),
131 RTW89_DEF_CHAN_6G(6755, 161),
132 RTW89_DEF_CHAN_6G(6775, 165),
133 RTW89_DEF_CHAN_6G(6795, 169),
134 RTW89_DEF_CHAN_6G(6815, 173),
135 RTW89_DEF_CHAN_6G(6835, 177),
136 RTW89_DEF_CHAN_6G(6855, 181),
137 RTW89_DEF_CHAN_6G(6875, 185),
138 RTW89_DEF_CHAN_6G(6895, 189),
139 RTW89_DEF_CHAN_6G(6915, 193),
140 RTW89_DEF_CHAN_6G(6935, 197),
141 RTW89_DEF_CHAN_6G(6955, 201),
142 RTW89_DEF_CHAN_6G(6975, 205),
143 RTW89_DEF_CHAN_6G(6995, 209),
144 RTW89_DEF_CHAN_6G(7015, 213),
145 RTW89_DEF_CHAN_6G(7035, 217),
146 RTW89_DEF_CHAN_6G(7055, 221),
147 RTW89_DEF_CHAN_6G(7075, 225),
148 RTW89_DEF_CHAN_6G(7095, 229),
149 RTW89_DEF_CHAN_6G(7115, 233),
150 };
151
152 static struct ieee80211_rate rtw89_bitrates[] = {
153 { .bitrate = 10, .hw_value = 0x00, },
154 { .bitrate = 20, .hw_value = 0x01, },
155 { .bitrate = 55, .hw_value = 0x02, },
156 { .bitrate = 110, .hw_value = 0x03, },
157 { .bitrate = 60, .hw_value = 0x04, },
158 { .bitrate = 90, .hw_value = 0x05, },
159 { .bitrate = 120, .hw_value = 0x06, },
160 { .bitrate = 180, .hw_value = 0x07, },
161 { .bitrate = 240, .hw_value = 0x08, },
162 { .bitrate = 360, .hw_value = 0x09, },
163 { .bitrate = 480, .hw_value = 0x0a, },
164 { .bitrate = 540, .hw_value = 0x0b, },
165 };
166
167 static const struct ieee80211_iface_limit rtw89_iface_limits[] = {
168 {
169 .max = 1,
170 .types = BIT(NL80211_IFTYPE_STATION),
171 },
172 {
173 .max = 1,
174 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
175 BIT(NL80211_IFTYPE_P2P_GO) |
176 BIT(NL80211_IFTYPE_AP),
177 },
178 };
179
180 static const struct ieee80211_iface_limit rtw89_iface_limits_mcc[] = {
181 {
182 .max = 1,
183 .types = BIT(NL80211_IFTYPE_STATION),
184 },
185 {
186 .max = 1,
187 .types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
188 BIT(NL80211_IFTYPE_P2P_GO),
189 },
190 };
191
192 static const struct ieee80211_iface_combination rtw89_iface_combs[] = {
193 {
194 .limits = rtw89_iface_limits,
195 .n_limits = ARRAY_SIZE(rtw89_iface_limits),
196 .max_interfaces = RTW89_MAX_INTERFACE_NUM,
197 .num_different_channels = 1,
198 },
199 {
200 .limits = rtw89_iface_limits_mcc,
201 .n_limits = ARRAY_SIZE(rtw89_iface_limits_mcc),
202 .max_interfaces = RTW89_MAX_INTERFACE_NUM,
203 .num_different_channels = 2,
204 },
205 };
206
207 static const u8 rtw89_ext_capa_sta[] = {
208 [0] = WLAN_EXT_CAPA1_EXT_CHANNEL_SWITCHING,
209 [2] = WLAN_EXT_CAPA3_MULTI_BSSID_SUPPORT,
210 [7] = WLAN_EXT_CAPA8_OPMODE_NOTIF,
211 };
212
213 static const struct wiphy_iftype_ext_capab rtw89_iftypes_ext_capa[] = {
214 {
215 .iftype = NL80211_IFTYPE_STATION,
216 .extended_capabilities = rtw89_ext_capa_sta,
217 .extended_capabilities_mask = rtw89_ext_capa_sta,
218 .extended_capabilities_len = sizeof(rtw89_ext_capa_sta),
219 /* relevant only if EHT is supported */
220 .eml_capabilities = 0,
221 .mld_capa_and_ops = 0,
222 },
223 };
224
225 #define RTW89_6GHZ_SPAN_HEAD 6145
226 #define RTW89_6GHZ_SPAN_IDX(center_freq) \
227 ((((int)(center_freq) - RTW89_6GHZ_SPAN_HEAD) / 5) / 2)
228
229 #define RTW89_DECL_6GHZ_SPAN(center_freq, subband_l, subband_h) \
230 [RTW89_6GHZ_SPAN_IDX(center_freq)] = { \
231 .sar_subband_low = RTW89_SAR_6GHZ_ ## subband_l, \
232 .sar_subband_high = RTW89_SAR_6GHZ_ ## subband_h, \
233 .acpi_sar_subband_low = RTW89_ACPI_SAR_6GHZ_ ## subband_l, \
234 .acpi_sar_subband_high = RTW89_ACPI_SAR_6GHZ_ ## subband_h, \
235 .ant_gain_subband_low = RTW89_ANT_GAIN_6GHZ_ ## subband_l, \
236 .ant_gain_subband_high = RTW89_ANT_GAIN_6GHZ_ ## subband_h, \
237 }
238
239 /* Since 6GHz subbands are not edge aligned, some cases span two subbands.
240 * In the following, we describe each of them with rtw89_6ghz_span.
241 */
242 static const struct rtw89_6ghz_span rtw89_overlapping_6ghz[] = {
243 RTW89_DECL_6GHZ_SPAN(6145, SUBBAND_5_L, SUBBAND_5_H),
244 RTW89_DECL_6GHZ_SPAN(6165, SUBBAND_5_L, SUBBAND_5_H),
245 RTW89_DECL_6GHZ_SPAN(6185, SUBBAND_5_L, SUBBAND_5_H),
246 RTW89_DECL_6GHZ_SPAN(6505, SUBBAND_6, SUBBAND_7_L),
247 RTW89_DECL_6GHZ_SPAN(6525, SUBBAND_6, SUBBAND_7_L),
248 RTW89_DECL_6GHZ_SPAN(6545, SUBBAND_6, SUBBAND_7_L),
249 RTW89_DECL_6GHZ_SPAN(6665, SUBBAND_7_L, SUBBAND_7_H),
250 RTW89_DECL_6GHZ_SPAN(6705, SUBBAND_7_L, SUBBAND_7_H),
251 RTW89_DECL_6GHZ_SPAN(6825, SUBBAND_7_H, SUBBAND_8),
252 RTW89_DECL_6GHZ_SPAN(6865, SUBBAND_7_H, SUBBAND_8),
253 RTW89_DECL_6GHZ_SPAN(6875, SUBBAND_7_H, SUBBAND_8),
254 RTW89_DECL_6GHZ_SPAN(6885, SUBBAND_7_H, SUBBAND_8),
255 };
256
257 const struct rtw89_6ghz_span *
rtw89_get_6ghz_span(struct rtw89_dev * rtwdev,u32 center_freq)258 rtw89_get_6ghz_span(struct rtw89_dev *rtwdev, u32 center_freq)
259 {
260 int idx;
261
262 if (center_freq >= RTW89_6GHZ_SPAN_HEAD) {
263 idx = RTW89_6GHZ_SPAN_IDX(center_freq);
264 /* To decrease size of rtw89_overlapping_6ghz[],
265 * RTW89_6GHZ_SPAN_IDX() truncates the leading NULLs
266 * to make first span as index 0 of the table. So, if center
267 * frequency is less than the first one, it will get netative.
268 */
269 if (idx >= 0 && idx < ARRAY_SIZE(rtw89_overlapping_6ghz))
270 return &rtw89_overlapping_6ghz[idx];
271 }
272
273 return NULL;
274 }
275
rtw89_legacy_rate_to_bitrate(struct rtw89_dev * rtwdev,u8 legacy_rate,u16 * bitrate)276 bool rtw89_legacy_rate_to_bitrate(struct rtw89_dev *rtwdev, u8 legacy_rate, u16 *bitrate)
277 {
278 const struct ieee80211_rate *rate;
279
280 if (unlikely(legacy_rate >= ARRAY_SIZE(rtw89_bitrates))) {
281 rtw89_debug(rtwdev, RTW89_DBG_UNEXP,
282 "invalid legacy rate %d\n", legacy_rate);
283 return false;
284 }
285
286 rate = &rtw89_bitrates[legacy_rate];
287 *bitrate = rate->bitrate;
288
289 return true;
290 }
291
292 static const struct ieee80211_supported_band rtw89_sband_2ghz = {
293 .band = NL80211_BAND_2GHZ,
294 .channels = rtw89_channels_2ghz,
295 .n_channels = ARRAY_SIZE(rtw89_channels_2ghz),
296 .bitrates = rtw89_bitrates,
297 .n_bitrates = ARRAY_SIZE(rtw89_bitrates),
298 .ht_cap = {0},
299 .vht_cap = {0},
300 };
301
302 static const struct ieee80211_supported_band rtw89_sband_5ghz = {
303 .band = NL80211_BAND_5GHZ,
304 .channels = rtw89_channels_5ghz,
305 .n_channels = ARRAY_SIZE(rtw89_channels_5ghz),
306
307 /* 5G has no CCK rates, 1M/2M/5.5M/11M */
308 .bitrates = rtw89_bitrates + 4,
309 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
310 .ht_cap = {0},
311 .vht_cap = {0},
312 };
313
314 static const struct ieee80211_supported_band rtw89_sband_6ghz = {
315 .band = NL80211_BAND_6GHZ,
316 .channels = rtw89_channels_6ghz,
317 .n_channels = ARRAY_SIZE(rtw89_channels_6ghz),
318
319 /* 6G has no CCK rates, 1M/2M/5.5M/11M */
320 .bitrates = rtw89_bitrates + 4,
321 .n_bitrates = ARRAY_SIZE(rtw89_bitrates) - 4,
322 };
323
324 static const struct rtw89_hw_rate_def {
325 enum rtw89_hw_rate ht;
326 enum rtw89_hw_rate vht[RTW89_NSS_NUM];
327 } rtw89_hw_rate[RTW89_CHIP_GEN_NUM] = {
328 [RTW89_CHIP_AX] = {
329 .ht = RTW89_HW_RATE_MCS0,
330 .vht = {RTW89_HW_RATE_VHT_NSS1_MCS0,
331 RTW89_HW_RATE_VHT_NSS2_MCS0,
332 RTW89_HW_RATE_VHT_NSS3_MCS0,
333 RTW89_HW_RATE_VHT_NSS4_MCS0},
334 },
335 [RTW89_CHIP_BE] = {
336 .ht = RTW89_HW_RATE_V1_MCS0,
337 .vht = {RTW89_HW_RATE_V1_VHT_NSS1_MCS0,
338 RTW89_HW_RATE_V1_VHT_NSS2_MCS0,
339 RTW89_HW_RATE_V1_VHT_NSS3_MCS0,
340 RTW89_HW_RATE_V1_VHT_NSS4_MCS0},
341 },
342 };
343
__rtw89_traffic_stats_accu(struct rtw89_traffic_stats * stats,struct sk_buff * skb,bool tx)344 static void __rtw89_traffic_stats_accu(struct rtw89_traffic_stats *stats,
345 struct sk_buff *skb, bool tx)
346 {
347 if (tx) {
348 stats->tx_cnt++;
349 stats->tx_unicast += skb->len;
350 } else {
351 stats->rx_cnt++;
352 stats->rx_unicast += skb->len;
353 }
354 }
355
rtw89_traffic_stats_accu(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct sk_buff * skb,bool accu_dev,bool tx)356 static void rtw89_traffic_stats_accu(struct rtw89_dev *rtwdev,
357 struct rtw89_vif *rtwvif,
358 struct sk_buff *skb,
359 bool accu_dev, bool tx)
360 {
361 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
362
363 if (!ieee80211_is_data(hdr->frame_control))
364 return;
365
366 if (is_broadcast_ether_addr(hdr->addr1) ||
367 is_multicast_ether_addr(hdr->addr1))
368 return;
369
370 if (accu_dev)
371 __rtw89_traffic_stats_accu(&rtwdev->stats, skb, tx);
372
373 if (rtwvif) {
374 __rtw89_traffic_stats_accu(&rtwvif->stats, skb, tx);
375 __rtw89_traffic_stats_accu(&rtwvif->stats_ps, skb, tx);
376 }
377 }
378
rtw89_get_default_chandef(struct cfg80211_chan_def * chandef)379 void rtw89_get_default_chandef(struct cfg80211_chan_def *chandef)
380 {
381 cfg80211_chandef_create(chandef, &rtw89_channels_2ghz[0],
382 NL80211_CHAN_NO_HT);
383 }
384
rtw89_get_channel_params(const struct cfg80211_chan_def * chandef,struct rtw89_chan * chan)385 void rtw89_get_channel_params(const struct cfg80211_chan_def *chandef,
386 struct rtw89_chan *chan)
387 {
388 struct ieee80211_channel *channel = chandef->chan;
389 enum nl80211_chan_width width = chandef->width;
390 u32 primary_freq, center_freq;
391 u8 center_chan;
392 u8 bandwidth = RTW89_CHANNEL_WIDTH_20;
393 u32 offset;
394 u8 band;
395
396 center_chan = channel->hw_value;
397 primary_freq = channel->center_freq;
398 center_freq = chandef->center_freq1;
399
400 switch (width) {
401 case NL80211_CHAN_WIDTH_20_NOHT:
402 case NL80211_CHAN_WIDTH_20:
403 bandwidth = RTW89_CHANNEL_WIDTH_20;
404 break;
405 case NL80211_CHAN_WIDTH_40:
406 bandwidth = RTW89_CHANNEL_WIDTH_40;
407 if (primary_freq > center_freq) {
408 center_chan -= 2;
409 } else {
410 center_chan += 2;
411 }
412 break;
413 case NL80211_CHAN_WIDTH_80:
414 case NL80211_CHAN_WIDTH_160:
415 bandwidth = nl_to_rtw89_bandwidth(width);
416 if (primary_freq > center_freq) {
417 offset = (primary_freq - center_freq - 10) / 20;
418 center_chan -= 2 + offset * 4;
419 } else {
420 offset = (center_freq - primary_freq - 10) / 20;
421 center_chan += 2 + offset * 4;
422 }
423 break;
424 default:
425 center_chan = 0;
426 break;
427 }
428
429 switch (channel->band) {
430 default:
431 case NL80211_BAND_2GHZ:
432 band = RTW89_BAND_2G;
433 break;
434 case NL80211_BAND_5GHZ:
435 band = RTW89_BAND_5G;
436 break;
437 case NL80211_BAND_6GHZ:
438 band = RTW89_BAND_6G;
439 break;
440 }
441
442 rtw89_chan_create(chan, center_chan, channel->hw_value, band, bandwidth);
443 }
444
__rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_phy_idx phy_idx)445 static void __rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev,
446 const struct rtw89_chan *chan,
447 enum rtw89_phy_idx phy_idx)
448 {
449 const struct rtw89_chip_info *chip = rtwdev->chip;
450 bool entity_active;
451
452 entity_active = rtw89_get_entity_state(rtwdev, phy_idx);
453 if (!entity_active)
454 return;
455
456 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
457 }
458
rtw89_core_set_chip_txpwr(struct rtw89_dev * rtwdev)459 void rtw89_core_set_chip_txpwr(struct rtw89_dev *rtwdev)
460 {
461 const struct rtw89_chan *chan;
462
463 chan = rtw89_mgnt_chan_get(rtwdev, 0);
464 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_0);
465
466 if (!rtwdev->support_mlo)
467 return;
468
469 chan = rtw89_mgnt_chan_get(rtwdev, 1);
470 __rtw89_core_set_chip_txpwr(rtwdev, chan, RTW89_PHY_1);
471 }
472
rtw89_chip_rfk_channel(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)473 void rtw89_chip_rfk_channel(struct rtw89_dev *rtwdev,
474 struct rtw89_vif_link *rtwvif_link)
475 {
476 const struct rtw89_chip_info *chip = rtwdev->chip;
477 bool mon = !!rtwdev->pure_monitor_mode_vif;
478 bool prehdl_link = false;
479
480 if (chip->chip_gen != RTW89_CHIP_AX &&
481 !RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw) &&
482 !mon && !rtw89_entity_check_hw(rtwdev, rtwvif_link->phy_idx))
483 prehdl_link = true;
484
485 if (prehdl_link) {
486 rtw89_entity_force_hw(rtwdev, rtwvif_link->phy_idx);
487 rtw89_set_channel(rtwdev);
488 }
489
490 if (chip->ops->rfk_channel)
491 chip->ops->rfk_channel(rtwdev, rtwvif_link);
492
493 if (prehdl_link) {
494 rtw89_entity_force_hw(rtwdev, RTW89_PHY_NUM);
495 rtw89_set_channel(rtwdev);
496 }
497 }
498
rtw89_chip_rfk_channel_for_pure_mon_vif(struct rtw89_dev * rtwdev,enum rtw89_phy_idx phy_idx)499 static void rtw89_chip_rfk_channel_for_pure_mon_vif(struct rtw89_dev *rtwdev,
500 enum rtw89_phy_idx phy_idx)
501 {
502 struct rtw89_vif *rtwvif = rtwdev->pure_monitor_mode_vif;
503 struct rtw89_vif_link *rtwvif_link;
504
505 if (!rtwvif)
506 return;
507
508 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, phy_idx);
509 if (!rtwvif_link)
510 return;
511
512 rtw89_chip_rfk_channel(rtwdev, rtwvif_link);
513 }
514
__rtw89_set_channel(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan,enum rtw89_mac_idx mac_idx,enum rtw89_phy_idx phy_idx)515 static void __rtw89_set_channel(struct rtw89_dev *rtwdev,
516 const struct rtw89_chan *chan,
517 enum rtw89_mac_idx mac_idx,
518 enum rtw89_phy_idx phy_idx)
519 {
520 const struct rtw89_chip_info *chip = rtwdev->chip;
521 const struct rtw89_chan_rcd *chan_rcd;
522 struct rtw89_channel_help_params bak;
523 bool entity_active;
524
525 entity_active = rtw89_get_entity_state(rtwdev, phy_idx);
526
527 chan_rcd = rtw89_chan_rcd_get_by_chan(chan);
528
529 rtw89_chip_set_channel_prepare(rtwdev, &bak, chan, mac_idx, phy_idx);
530
531 chip->ops->set_channel(rtwdev, chan, mac_idx, phy_idx);
532
533 chip->ops->set_txpwr(rtwdev, chan, phy_idx);
534
535 rtw89_chip_set_channel_done(rtwdev, &bak, chan, mac_idx, phy_idx);
536
537 if (!entity_active || chan_rcd->band_changed) {
538 rtw89_btc_ntfy_switch_band(rtwdev, phy_idx, chan->band_type);
539 rtw89_chip_rfk_band_changed(rtwdev, phy_idx, chan);
540 }
541
542 rtw89_set_entity_state(rtwdev, phy_idx, true);
543
544 rtw89_chip_rfk_channel_for_pure_mon_vif(rtwdev, phy_idx);
545 }
546
rtw89_set_channel(struct rtw89_dev * rtwdev)547 int rtw89_set_channel(struct rtw89_dev *rtwdev)
548 {
549 const struct rtw89_chan *chan;
550 enum rtw89_entity_mode mode;
551
552 mode = rtw89_entity_recalc(rtwdev);
553 if (mode < 0 || mode >= NUM_OF_RTW89_ENTITY_MODE) {
554 WARN(1, "Invalid ent mode: %d\n", mode);
555 return -EINVAL;
556 }
557
558 chan = rtw89_mgnt_chan_get(rtwdev, 0);
559 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_0, RTW89_PHY_0);
560
561 if (!rtwdev->support_mlo)
562 return 0;
563
564 chan = rtw89_mgnt_chan_get(rtwdev, 1);
565 __rtw89_set_channel(rtwdev, chan, RTW89_MAC_1, RTW89_PHY_1);
566
567 return 0;
568 }
569
570 static enum rtw89_core_tx_type
rtw89_core_get_tx_type(struct rtw89_dev * rtwdev,struct sk_buff * skb)571 rtw89_core_get_tx_type(struct rtw89_dev *rtwdev,
572 struct sk_buff *skb)
573 {
574 struct ieee80211_hdr *hdr = (void *)skb->data;
575 __le16 fc = hdr->frame_control;
576
577 if (ieee80211_is_mgmt(fc) || ieee80211_is_any_nullfunc(fc))
578 return RTW89_CORE_TX_TYPE_MGMT;
579
580 return RTW89_CORE_TX_TYPE_DATA;
581 }
582
583 static void
rtw89_core_tx_update_ampdu_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)584 rtw89_core_tx_update_ampdu_info(struct rtw89_dev *rtwdev,
585 struct rtw89_core_tx_request *tx_req,
586 enum btc_pkt_type pkt_type)
587 {
588 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
589 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
590 struct ieee80211_link_sta *link_sta;
591 struct sk_buff *skb = tx_req->skb;
592 struct rtw89_sta *rtwsta;
593 u8 ampdu_num;
594 u8 tid;
595
596 if (pkt_type == PACKET_EAPOL) {
597 desc_info->bk = true;
598 return;
599 }
600
601 if (!(IEEE80211_SKB_CB(skb)->flags & IEEE80211_TX_CTL_AMPDU))
602 return;
603
604 if (!rtwsta_link) {
605 rtw89_warn(rtwdev, "cannot set ampdu info without sta\n");
606 return;
607 }
608
609 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
610 rtwsta = rtwsta_link->rtwsta;
611
612 rcu_read_lock();
613
614 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
615 ampdu_num = (u8)((rtwsta->ampdu_params[tid].agg_num ?
616 rtwsta->ampdu_params[tid].agg_num :
617 4 << link_sta->ht_cap.ampdu_factor) - 1);
618
619 desc_info->agg_en = true;
620 desc_info->ampdu_density = link_sta->ht_cap.ampdu_density;
621 desc_info->ampdu_num = ampdu_num;
622
623 rcu_read_unlock();
624 }
625
626 static void
rtw89_core_tx_update_sec_key(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)627 rtw89_core_tx_update_sec_key(struct rtw89_dev *rtwdev,
628 struct rtw89_core_tx_request *tx_req)
629 {
630 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
631 const struct rtw89_chip_info *chip = rtwdev->chip;
632 const struct rtw89_sec_cam_entry *sec_cam;
633 struct ieee80211_tx_info *info;
634 struct ieee80211_key_conf *key;
635 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
636 struct sk_buff *skb = tx_req->skb;
637 u8 sec_type = RTW89_SEC_KEY_TYPE_NONE;
638 u8 sec_cam_idx;
639 u64 pn64;
640
641 info = IEEE80211_SKB_CB(skb);
642 key = info->control.hw_key;
643 sec_cam_idx = key->hw_key_idx;
644 sec_cam = cam_info->sec_entries[sec_cam_idx];
645 if (!sec_cam) {
646 rtw89_warn(rtwdev, "sec cam entry is empty\n");
647 return;
648 }
649
650 switch (key->cipher) {
651 case WLAN_CIPHER_SUITE_WEP40:
652 sec_type = RTW89_SEC_KEY_TYPE_WEP40;
653 break;
654 case WLAN_CIPHER_SUITE_WEP104:
655 sec_type = RTW89_SEC_KEY_TYPE_WEP104;
656 break;
657 case WLAN_CIPHER_SUITE_TKIP:
658 sec_type = RTW89_SEC_KEY_TYPE_TKIP;
659 break;
660 case WLAN_CIPHER_SUITE_CCMP:
661 sec_type = RTW89_SEC_KEY_TYPE_CCMP128;
662 break;
663 case WLAN_CIPHER_SUITE_CCMP_256:
664 sec_type = RTW89_SEC_KEY_TYPE_CCMP256;
665 break;
666 case WLAN_CIPHER_SUITE_GCMP:
667 sec_type = RTW89_SEC_KEY_TYPE_GCMP128;
668 break;
669 case WLAN_CIPHER_SUITE_GCMP_256:
670 sec_type = RTW89_SEC_KEY_TYPE_GCMP256;
671 break;
672 default:
673 rtw89_warn(rtwdev, "key cipher not supported %d\n", key->cipher);
674 return;
675 }
676
677 desc_info->sec_en = true;
678 desc_info->sec_keyid = key->keyidx;
679 desc_info->sec_type = sec_type;
680 desc_info->sec_cam_idx = sec_cam->sec_cam_idx;
681
682 if (!chip->hw_sec_hdr)
683 return;
684
685 pn64 = atomic64_inc_return(&key->tx_pn);
686 desc_info->sec_seq[0] = pn64;
687 desc_info->sec_seq[1] = pn64 >> 8;
688 desc_info->sec_seq[2] = pn64 >> 16;
689 desc_info->sec_seq[3] = pn64 >> 24;
690 desc_info->sec_seq[4] = pn64 >> 32;
691 desc_info->sec_seq[5] = pn64 >> 40;
692 desc_info->wp_offset = 1; /* in unit of 8 bytes for security header */
693 }
694
rtw89_core_get_mgmt_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,const struct rtw89_chan * chan)695 static u16 rtw89_core_get_mgmt_rate(struct rtw89_dev *rtwdev,
696 struct rtw89_core_tx_request *tx_req,
697 const struct rtw89_chan *chan)
698 {
699 struct sk_buff *skb = tx_req->skb;
700 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
701 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
702 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
703 struct ieee80211_vif *vif = tx_info->control.vif;
704 struct ieee80211_bss_conf *bss_conf;
705 u16 lowest_rate;
706 u16 rate;
707
708 if (tx_info->flags & IEEE80211_TX_CTL_NO_CCK_RATE ||
709 (vif && vif->p2p))
710 lowest_rate = RTW89_HW_RATE_OFDM6;
711 else if (chan->band_type == RTW89_BAND_2G)
712 lowest_rate = RTW89_HW_RATE_CCK1;
713 else
714 lowest_rate = RTW89_HW_RATE_OFDM6;
715
716 if (!rtwvif_link)
717 return lowest_rate;
718
719 rcu_read_lock();
720
721 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
722 if (!bss_conf->basic_rates || !rtwsta_link) {
723 rate = lowest_rate;
724 goto out;
725 }
726
727 rate = __ffs(bss_conf->basic_rates) + lowest_rate;
728
729 out:
730 rcu_read_unlock();
731
732 return rate;
733 }
734
rtw89_core_tx_get_mac_id(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)735 static u8 rtw89_core_tx_get_mac_id(struct rtw89_dev *rtwdev,
736 struct rtw89_core_tx_request *tx_req)
737 {
738 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
739 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
740 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
741
742 if (desc_info->mlo && !desc_info->sw_mld) {
743 if (rtwsta_link)
744 return rtw89_sta_get_main_macid(rtwsta_link->rtwsta);
745 else
746 return rtw89_vif_get_main_macid(rtwvif_link->rtwvif);
747 }
748
749 if (!rtwsta_link)
750 return rtwvif_link->mac_id;
751
752 return rtwsta_link->mac_id;
753 }
754
rtw89_core_tx_update_llc_hdr(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,struct sk_buff * skb)755 static void rtw89_core_tx_update_llc_hdr(struct rtw89_dev *rtwdev,
756 struct rtw89_tx_desc_info *desc_info,
757 struct sk_buff *skb)
758 {
759 struct ieee80211_hdr *hdr = (void *)skb->data;
760 __le16 fc = hdr->frame_control;
761
762 desc_info->hdr_llc_len = ieee80211_hdrlen(fc);
763 desc_info->hdr_llc_len >>= 1; /* in unit of 2 bytes */
764 }
765
rtw89_core_get_ch_dma(struct rtw89_dev * rtwdev,u8 qsel)766 u8 rtw89_core_get_ch_dma(struct rtw89_dev *rtwdev, u8 qsel)
767 {
768 switch (qsel) {
769 default:
770 rtw89_warn(rtwdev, "Cannot map qsel to dma: %d\n", qsel);
771 fallthrough;
772 case RTW89_TX_QSEL_BE_0:
773 case RTW89_TX_QSEL_BE_1:
774 case RTW89_TX_QSEL_BE_2:
775 case RTW89_TX_QSEL_BE_3:
776 return RTW89_TXCH_ACH0;
777 case RTW89_TX_QSEL_BK_0:
778 case RTW89_TX_QSEL_BK_1:
779 case RTW89_TX_QSEL_BK_2:
780 case RTW89_TX_QSEL_BK_3:
781 return RTW89_TXCH_ACH1;
782 case RTW89_TX_QSEL_VI_0:
783 case RTW89_TX_QSEL_VI_1:
784 case RTW89_TX_QSEL_VI_2:
785 case RTW89_TX_QSEL_VI_3:
786 return RTW89_TXCH_ACH2;
787 case RTW89_TX_QSEL_VO_0:
788 case RTW89_TX_QSEL_VO_1:
789 case RTW89_TX_QSEL_VO_2:
790 case RTW89_TX_QSEL_VO_3:
791 return RTW89_TXCH_ACH3;
792 case RTW89_TX_QSEL_B0_MGMT:
793 return RTW89_TXCH_CH8;
794 case RTW89_TX_QSEL_B0_HI:
795 return RTW89_TXCH_CH9;
796 case RTW89_TX_QSEL_B1_MGMT:
797 return RTW89_TXCH_CH10;
798 case RTW89_TX_QSEL_B1_HI:
799 return RTW89_TXCH_CH11;
800 }
801 }
802 EXPORT_SYMBOL(rtw89_core_get_ch_dma);
803
rtw89_core_get_ch_dma_v1(struct rtw89_dev * rtwdev,u8 qsel)804 u8 rtw89_core_get_ch_dma_v1(struct rtw89_dev *rtwdev, u8 qsel)
805 {
806 switch (qsel) {
807 default:
808 rtw89_warn(rtwdev, "Cannot map qsel to dma v1: %d\n", qsel);
809 fallthrough;
810 case RTW89_TX_QSEL_BE_0:
811 case RTW89_TX_QSEL_BK_0:
812 return RTW89_TXCH_ACH0;
813 case RTW89_TX_QSEL_VI_0:
814 case RTW89_TX_QSEL_VO_0:
815 return RTW89_TXCH_ACH2;
816 case RTW89_TX_QSEL_B0_MGMT:
817 case RTW89_TX_QSEL_B0_HI:
818 return RTW89_TXCH_CH8;
819 case RTW89_TX_QSEL_B1_MGMT:
820 case RTW89_TX_QSEL_B1_HI:
821 return RTW89_TXCH_CH10;
822 }
823 }
824 EXPORT_SYMBOL(rtw89_core_get_ch_dma_v1);
825
rtw89_core_get_ch_dma_v2(struct rtw89_dev * rtwdev,u8 qsel)826 u8 rtw89_core_get_ch_dma_v2(struct rtw89_dev *rtwdev, u8 qsel)
827 {
828 switch (qsel) {
829 default:
830 rtw89_warn(rtwdev, "Cannot map qsel to dma v2: %d\n", qsel);
831 fallthrough;
832 case RTW89_TX_QSEL_BE_0:
833 case RTW89_TX_QSEL_VO_0:
834 return RTW89_TXCH_ACH0;
835 case RTW89_TX_QSEL_BK_0:
836 case RTW89_TX_QSEL_VI_0:
837 return RTW89_TXCH_ACH2;
838 case RTW89_TX_QSEL_B0_MGMT:
839 case RTW89_TX_QSEL_B0_HI:
840 return RTW89_TXCH_CH8;
841 }
842 }
843 EXPORT_SYMBOL(rtw89_core_get_ch_dma_v2);
844
845 static void
rtw89_core_tx_update_mgmt_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)846 rtw89_core_tx_update_mgmt_info(struct rtw89_dev *rtwdev,
847 struct rtw89_core_tx_request *tx_req)
848 {
849 const struct rtw89_chip_info *chip = rtwdev->chip;
850 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
851 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
852 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
853 rtwvif_link->chanctx_idx);
854 struct sk_buff *skb = tx_req->skb;
855 u8 qsel, ch_dma;
856
857 qsel = rtw89_core_get_qsel_mgmt(rtwdev, tx_req);
858 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel);
859
860 desc_info->qsel = qsel;
861 desc_info->ch_dma = ch_dma;
862 desc_info->sw_mld = true;
863 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
864 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
865 desc_info->hw_ssn_sel = RTW89_MGMT_HW_SSN_SEL;
866 desc_info->hw_seq_mode = RTW89_MGMT_HW_SEQ_MODE;
867
868 /* fixed data rate for mgmt frames */
869 desc_info->en_wd_info = true;
870 desc_info->use_rate = true;
871 desc_info->dis_data_fb = true;
872 desc_info->data_rate = rtw89_core_get_mgmt_rate(rtwdev, tx_req, chan);
873
874 if (chip->hw_mgmt_tx_encrypt && IEEE80211_SKB_CB(skb)->control.hw_key) {
875 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
876 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
877 }
878
879 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
880 "tx mgmt frame with rate 0x%x on channel %d (band %d, bw %d)\n",
881 desc_info->data_rate, chan->channel, chan->band_type,
882 chan->band_width);
883 }
884
885 static void
rtw89_core_tx_update_h2c_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)886 rtw89_core_tx_update_h2c_info(struct rtw89_dev *rtwdev,
887 struct rtw89_core_tx_request *tx_req)
888 {
889 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
890
891 desc_info->is_bmc = false;
892 desc_info->wd_page = false;
893 desc_info->ch_dma = RTW89_DMA_H2C;
894 }
895
rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev * rtwdev,__le32 * htc,const struct rtw89_chan * chan)896 static void rtw89_core_get_no_ul_ofdma_htc(struct rtw89_dev *rtwdev, __le32 *htc,
897 const struct rtw89_chan *chan)
898 {
899 static const u8 rtw89_bandwidth_to_om[] = {
900 [RTW89_CHANNEL_WIDTH_20] = HTC_OM_CHANNEL_WIDTH_20,
901 [RTW89_CHANNEL_WIDTH_40] = HTC_OM_CHANNEL_WIDTH_40,
902 [RTW89_CHANNEL_WIDTH_80] = HTC_OM_CHANNEL_WIDTH_80,
903 [RTW89_CHANNEL_WIDTH_160] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
904 [RTW89_CHANNEL_WIDTH_80_80] = HTC_OM_CHANNEL_WIDTH_160_OR_80_80,
905 };
906 const struct rtw89_chip_info *chip = rtwdev->chip;
907 struct rtw89_hal *hal = &rtwdev->hal;
908 u8 om_bandwidth;
909
910 if (!chip->dis_2g_40m_ul_ofdma ||
911 chan->band_type != RTW89_BAND_2G ||
912 chan->band_width != RTW89_CHANNEL_WIDTH_40)
913 return;
914
915 om_bandwidth = chan->band_width < ARRAY_SIZE(rtw89_bandwidth_to_om) ?
916 rtw89_bandwidth_to_om[chan->band_width] : 0;
917 *htc = le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
918 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_OM, RTW89_HTC_MASK_CTL_ID) |
919 le32_encode_bits(hal->rx_nss - 1, RTW89_HTC_MASK_HTC_OM_RX_NSS) |
920 le32_encode_bits(om_bandwidth, RTW89_HTC_MASK_HTC_OM_CH_WIDTH) |
921 le32_encode_bits(1, RTW89_HTC_MASK_HTC_OM_UL_MU_DIS) |
922 le32_encode_bits(hal->tx_nss - 1, RTW89_HTC_MASK_HTC_OM_TX_NSTS) |
923 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_ER_SU_DIS) |
924 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_DL_MU_MIMO_RR) |
925 le32_encode_bits(0, RTW89_HTC_MASK_HTC_OM_UL_MU_DATA_DIS);
926 }
927
928 static bool
__rtw89_core_tx_check_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)929 __rtw89_core_tx_check_he_qos_htc(struct rtw89_dev *rtwdev,
930 struct rtw89_core_tx_request *tx_req,
931 enum btc_pkt_type pkt_type)
932 {
933 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
934 struct sk_buff *skb = tx_req->skb;
935 struct ieee80211_hdr *hdr = (void *)skb->data;
936 struct ieee80211_link_sta *link_sta;
937 __le16 fc = hdr->frame_control;
938
939 /* AP IOT issue with EAPoL, ARP and DHCP */
940 if (pkt_type < PACKET_MAX)
941 return false;
942
943 if (!rtwsta_link)
944 return false;
945
946 rcu_read_lock();
947
948 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
949 if (!link_sta->he_cap.has_he) {
950 rcu_read_unlock();
951 return false;
952 }
953
954 rcu_read_unlock();
955
956 if (!ieee80211_is_data_qos(fc))
957 return false;
958
959 if (skb_headroom(skb) < IEEE80211_HT_CTL_LEN)
960 return false;
961
962 if (rtwsta_link && rtwsta_link->ra_report.might_fallback_legacy)
963 return false;
964
965 return true;
966 }
967
968 static void
__rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)969 __rtw89_core_tx_adjust_he_qos_htc(struct rtw89_dev *rtwdev,
970 struct rtw89_core_tx_request *tx_req)
971 {
972 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
973 struct sk_buff *skb = tx_req->skb;
974 struct ieee80211_hdr *hdr = (void *)skb->data;
975 __le16 fc = hdr->frame_control;
976 void *data;
977 __le32 *htc;
978 u8 *qc;
979 int hdr_len;
980
981 hdr_len = ieee80211_has_a4(fc) ? 32 : 26;
982 data = skb_push(skb, IEEE80211_HT_CTL_LEN);
983 memmove(data, data + IEEE80211_HT_CTL_LEN, hdr_len);
984
985 hdr = data;
986 htc = data + hdr_len;
987 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_ORDER);
988 *htc = rtwsta_link->htc_template ? rtwsta_link->htc_template :
989 le32_encode_bits(RTW89_HTC_VARIANT_HE, RTW89_HTC_MASK_VARIANT) |
990 le32_encode_bits(RTW89_HTC_VARIANT_HE_CID_CAS, RTW89_HTC_MASK_CTL_ID);
991
992 qc = data + hdr_len - IEEE80211_QOS_CTL_LEN;
993 qc[0] |= IEEE80211_QOS_CTL_EOSP;
994 }
995
996 static void
rtw89_core_tx_update_he_qos_htc(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,enum btc_pkt_type pkt_type)997 rtw89_core_tx_update_he_qos_htc(struct rtw89_dev *rtwdev,
998 struct rtw89_core_tx_request *tx_req,
999 enum btc_pkt_type pkt_type)
1000 {
1001 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1002 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
1003
1004 if (!__rtw89_core_tx_check_he_qos_htc(rtwdev, tx_req, pkt_type))
1005 goto desc_bk;
1006
1007 __rtw89_core_tx_adjust_he_qos_htc(rtwdev, tx_req);
1008
1009 desc_info->pkt_size += IEEE80211_HT_CTL_LEN;
1010 desc_info->a_ctrl_bsr = true;
1011
1012 desc_bk:
1013 if (!rtwvif_link || rtwvif_link->last_a_ctrl == desc_info->a_ctrl_bsr)
1014 return;
1015
1016 rtwvif_link->last_a_ctrl = desc_info->a_ctrl_bsr;
1017 desc_info->bk = true;
1018 }
1019
rtw89_core_get_data_rate(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1020 static u16 rtw89_core_get_data_rate(struct rtw89_dev *rtwdev,
1021 struct rtw89_core_tx_request *tx_req)
1022 {
1023 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
1024 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
1025 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
1026 struct rtw89_phy_rate_pattern *rate_pattern = &rtwvif_link->rate_pattern;
1027 enum rtw89_chanctx_idx idx = rtwvif_link->chanctx_idx;
1028 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, idx);
1029 struct ieee80211_link_sta *link_sta;
1030 u16 lowest_rate;
1031 u16 rate;
1032
1033 if (rate_pattern->enable)
1034 return rate_pattern->rate;
1035
1036 if (vif->p2p)
1037 lowest_rate = RTW89_HW_RATE_OFDM6;
1038 else if (chan->band_type == RTW89_BAND_2G)
1039 lowest_rate = RTW89_HW_RATE_CCK1;
1040 else
1041 lowest_rate = RTW89_HW_RATE_OFDM6;
1042
1043 if (!rtwsta_link)
1044 return lowest_rate;
1045
1046 rcu_read_lock();
1047
1048 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, false);
1049 if (!link_sta->supp_rates[chan->band_type]) {
1050 rate = lowest_rate;
1051 goto out;
1052 }
1053
1054 rate = __ffs(link_sta->supp_rates[chan->band_type]) + lowest_rate;
1055
1056 out:
1057 rcu_read_unlock();
1058
1059 return rate;
1060 }
1061
1062 static void
rtw89_core_tx_update_data_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1063 rtw89_core_tx_update_data_info(struct rtw89_dev *rtwdev,
1064 struct rtw89_core_tx_request *tx_req)
1065 {
1066 struct rtw89_vif_link *rtwvif_link = tx_req->rtwvif_link;
1067 struct rtw89_sta_link *rtwsta_link = tx_req->rtwsta_link;
1068 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1069 struct sk_buff *skb = tx_req->skb;
1070 u8 tid, tid_indicate;
1071 u8 qsel, ch_dma;
1072
1073 tid = skb->priority & IEEE80211_QOS_CTL_TAG1D_MASK;
1074 tid_indicate = rtw89_core_get_tid_indicate(rtwdev, tid);
1075 qsel = desc_info->hiq ? RTW89_TX_QSEL_B0_HI : rtw89_core_get_qsel(rtwdev, tid);
1076 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel);
1077
1078 desc_info->ch_dma = ch_dma;
1079 desc_info->tid_indicate = tid_indicate;
1080 desc_info->qsel = qsel;
1081 desc_info->sw_mld = false;
1082 desc_info->mac_id = rtw89_core_tx_get_mac_id(rtwdev, tx_req);
1083 desc_info->port = desc_info->hiq ? rtwvif_link->port : 0;
1084 desc_info->er_cap = rtwsta_link ? rtwsta_link->er_cap : false;
1085 desc_info->stbc = rtwsta_link ? rtwsta_link->ra.stbc_cap : false;
1086 desc_info->ldpc = rtwsta_link ? rtwsta_link->ra.ldpc_cap : false;
1087
1088 /* enable wd_info for AMPDU */
1089 desc_info->en_wd_info = true;
1090
1091 if (IEEE80211_SKB_CB(skb)->control.hw_key)
1092 rtw89_core_tx_update_sec_key(rtwdev, tx_req);
1093
1094 desc_info->data_retry_lowest_rate = rtw89_core_get_data_rate(rtwdev, tx_req);
1095 }
1096
1097 static enum btc_pkt_type
rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1098 rtw89_core_tx_btc_spec_pkt_notify(struct rtw89_dev *rtwdev,
1099 struct rtw89_core_tx_request *tx_req)
1100 {
1101 struct wiphy *wiphy = rtwdev->hw->wiphy;
1102 struct sk_buff *skb = tx_req->skb;
1103 struct udphdr *udphdr;
1104
1105 if (IEEE80211_SKB_CB(skb)->control.flags & IEEE80211_TX_CTRL_PORT_CTRL_PROTO) {
1106 wiphy_work_queue(wiphy, &rtwdev->btc.eapol_notify_work);
1107 return PACKET_EAPOL;
1108 }
1109
1110 if (skb->protocol == htons(ETH_P_ARP)) {
1111 wiphy_work_queue(wiphy, &rtwdev->btc.arp_notify_work);
1112 return PACKET_ARP;
1113 }
1114
1115 if (skb->protocol == htons(ETH_P_IP) &&
1116 ip_hdr(skb)->protocol == IPPROTO_UDP) {
1117 udphdr = udp_hdr(skb);
1118 if (((udphdr->source == htons(67) && udphdr->dest == htons(68)) ||
1119 (udphdr->source == htons(68) && udphdr->dest == htons(67))) &&
1120 skb->len > 282) {
1121 wiphy_work_queue(wiphy, &rtwdev->btc.dhcp_notify_work);
1122 return PACKET_DHCP;
1123 }
1124 }
1125
1126 if (skb->protocol == htons(ETH_P_IP) &&
1127 ip_hdr(skb)->protocol == IPPROTO_ICMP) {
1128 wiphy_work_queue(wiphy, &rtwdev->btc.icmp_notify_work);
1129 return PACKET_ICMP;
1130 }
1131
1132 return PACKET_MAX;
1133 }
1134
1135 static void
rtw89_core_tx_wake(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1136 rtw89_core_tx_wake(struct rtw89_dev *rtwdev,
1137 struct rtw89_core_tx_request *tx_req)
1138 {
1139 const struct rtw89_chip_info *chip = rtwdev->chip;
1140
1141 if (!RTW89_CHK_FW_FEATURE(TX_WAKE, &rtwdev->fw))
1142 return;
1143
1144 switch (chip->chip_id) {
1145 case RTL8852BT:
1146 if (test_bit(RTW89_FLAG_LEISURE_PS, rtwdev->flags))
1147 goto notify;
1148 break;
1149 case RTL8852C:
1150 if (test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags))
1151 goto notify;
1152 break;
1153 default:
1154 if (test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags) &&
1155 tx_req->tx_type == RTW89_CORE_TX_TYPE_MGMT)
1156 goto notify;
1157 break;
1158 }
1159
1160 return;
1161
1162 notify:
1163 rtw89_mac_notify_wake(rtwdev);
1164 }
1165
rtw89_core_tx_update_injection(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req,struct ieee80211_tx_info * info)1166 static void rtw89_core_tx_update_injection(struct rtw89_dev *rtwdev,
1167 struct rtw89_core_tx_request *tx_req,
1168 struct ieee80211_tx_info *info)
1169 {
1170 const struct rtw89_hw_rate_def *hw_rate = &rtw89_hw_rate[rtwdev->chip->chip_gen];
1171 enum mac80211_rate_control_flags flags = info->control.rates[0].flags;
1172 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1173 const struct rtw89_chan *chan;
1174 u8 idx = info->control.rates[0].idx;
1175 u8 nss, mcs;
1176
1177 desc_info->use_rate = true;
1178 desc_info->dis_data_fb = true;
1179
1180 if (flags & IEEE80211_TX_RC_160_MHZ_WIDTH)
1181 desc_info->data_bw = 3;
1182 else if (flags & IEEE80211_TX_RC_80_MHZ_WIDTH)
1183 desc_info->data_bw = 2;
1184 else if (flags & IEEE80211_TX_RC_40_MHZ_WIDTH)
1185 desc_info->data_bw = 1;
1186
1187 if (flags & IEEE80211_TX_RC_SHORT_GI)
1188 desc_info->gi_ltf = 1;
1189
1190 if (flags & IEEE80211_TX_RC_VHT_MCS) {
1191 nss = umin(idx >> 4, ARRAY_SIZE(hw_rate->vht) - 1);
1192 mcs = idx & 0xf;
1193 desc_info->data_rate = hw_rate->vht[nss] + mcs;
1194 } else if (flags & IEEE80211_TX_RC_MCS) {
1195 desc_info->data_rate = hw_rate->ht + idx;
1196 } else {
1197 chan = rtw89_chan_get(rtwdev, tx_req->rtwvif_link->chanctx_idx);
1198
1199 desc_info->data_rate = idx + (chan->band_type == RTW89_BAND_2G ?
1200 RTW89_HW_RATE_CCK1 : RTW89_HW_RATE_OFDM6);
1201 }
1202 }
1203
1204 static void
rtw89_core_tx_update_desc_info(struct rtw89_dev * rtwdev,struct rtw89_core_tx_request * tx_req)1205 rtw89_core_tx_update_desc_info(struct rtw89_dev *rtwdev,
1206 struct rtw89_core_tx_request *tx_req)
1207 {
1208 struct rtw89_tx_desc_info *desc_info = &tx_req->desc_info;
1209 struct sk_buff *skb = tx_req->skb;
1210 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1211 struct ieee80211_hdr *hdr = (void *)skb->data;
1212 struct rtw89_addr_cam_entry *addr_cam;
1213 enum btc_pkt_type pkt_type;
1214 bool upd_wlan_hdr = false;
1215 bool is_bmc;
1216 u16 seq;
1217
1218 desc_info->pkt_size = skb->len;
1219
1220 if (unlikely(tx_req->tx_type == RTW89_CORE_TX_TYPE_FWCMD)) {
1221 rtw89_core_tx_update_h2c_info(rtwdev, tx_req);
1222 return;
1223 }
1224
1225 tx_req->tx_type = rtw89_core_get_tx_type(rtwdev, skb);
1226
1227 if (tx_req->sta)
1228 desc_info->mlo = tx_req->sta->mlo;
1229 else if (tx_req->vif)
1230 desc_info->mlo = ieee80211_vif_is_mld(tx_req->vif);
1231
1232 seq = (le16_to_cpu(hdr->seq_ctrl) & IEEE80211_SCTL_SEQ) >> 4;
1233 addr_cam = rtw89_get_addr_cam_of(tx_req->rtwvif_link,
1234 tx_req->rtwsta_link);
1235 if (addr_cam->valid && desc_info->mlo)
1236 upd_wlan_hdr = true;
1237
1238 if (info->flags & IEEE80211_TX_CTL_REQ_TX_STATUS || tx_req->with_wait)
1239 rtw89_tx_rpt_init(rtwdev, tx_req);
1240
1241 is_bmc = (is_broadcast_ether_addr(hdr->addr1) ||
1242 is_multicast_ether_addr(hdr->addr1));
1243
1244 desc_info->seq = seq;
1245 desc_info->is_bmc = is_bmc;
1246 desc_info->wd_page = true;
1247 desc_info->hiq = info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM;
1248 desc_info->upd_wlan_hdr = upd_wlan_hdr;
1249
1250 switch (tx_req->tx_type) {
1251 case RTW89_CORE_TX_TYPE_MGMT:
1252 rtw89_core_tx_update_mgmt_info(rtwdev, tx_req);
1253 break;
1254 case RTW89_CORE_TX_TYPE_DATA:
1255 rtw89_core_tx_update_data_info(rtwdev, tx_req);
1256 pkt_type = rtw89_core_tx_btc_spec_pkt_notify(rtwdev, tx_req);
1257 rtw89_core_tx_update_he_qos_htc(rtwdev, tx_req, pkt_type);
1258 rtw89_core_tx_update_ampdu_info(rtwdev, tx_req, pkt_type);
1259 rtw89_core_tx_update_llc_hdr(rtwdev, desc_info, skb);
1260 break;
1261 default:
1262 break;
1263 }
1264
1265 if (unlikely(info->flags & IEEE80211_TX_CTL_INJECTED))
1266 rtw89_core_tx_update_injection(rtwdev, tx_req, info);
1267 }
1268
rtw89_tx_wait_work(struct wiphy * wiphy,struct wiphy_work * work)1269 static void rtw89_tx_wait_work(struct wiphy *wiphy, struct wiphy_work *work)
1270 {
1271 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
1272 tx_wait_work.work);
1273
1274 rtw89_tx_wait_list_clear(rtwdev);
1275 }
1276
rtw89_core_tx_kick_off(struct rtw89_dev * rtwdev,u8 qsel)1277 void rtw89_core_tx_kick_off(struct rtw89_dev *rtwdev, u8 qsel)
1278 {
1279 u8 ch_dma;
1280
1281 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel);
1282
1283 rtw89_hci_tx_kick_off(rtwdev, ch_dma);
1284 }
1285
rtw89_core_tx_kick_off_and_wait(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_tx_wait_info * wait,int qsel,unsigned int timeout)1286 int rtw89_core_tx_kick_off_and_wait(struct rtw89_dev *rtwdev, struct sk_buff *skb,
1287 struct rtw89_tx_wait_info *wait, int qsel,
1288 unsigned int timeout)
1289 {
1290 unsigned long time_left;
1291 int ret = 0;
1292
1293 lockdep_assert_wiphy(rtwdev->hw->wiphy);
1294
1295 rtw89_core_tx_kick_off(rtwdev, qsel);
1296 time_left = wait_for_completion_timeout(&wait->completion,
1297 msecs_to_jiffies(timeout));
1298
1299 if (time_left == 0) {
1300 ret = -ETIMEDOUT;
1301 list_add_tail(&wait->list, &rtwdev->tx_waits);
1302 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->tx_wait_work,
1303 RTW89_TX_WAIT_WORK_TIMEOUT);
1304 } else {
1305 if (!wait->tx_done)
1306 ret = -EAGAIN;
1307 rtw89_tx_wait_release(wait);
1308 }
1309
1310 return ret;
1311 }
1312
rtw89_h2c_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb,bool fwdl)1313 int rtw89_h2c_tx(struct rtw89_dev *rtwdev,
1314 struct sk_buff *skb, bool fwdl)
1315 {
1316 struct rtw89_core_tx_request tx_req = {0};
1317 u32 cnt;
1318 int ret;
1319
1320 if (!test_bit(RTW89_FLAG_POWERON, rtwdev->flags)) {
1321 rtw89_debug(rtwdev, RTW89_DBG_FW,
1322 "ignore h2c due to power is off with firmware state=%d\n",
1323 test_bit(RTW89_FLAG_FW_RDY, rtwdev->flags));
1324 dev_kfree_skb(skb);
1325 return 0;
1326 }
1327
1328 tx_req.skb = skb;
1329 tx_req.tx_type = RTW89_CORE_TX_TYPE_FWCMD;
1330 if (fwdl)
1331 tx_req.desc_info.fw_dl = true;
1332
1333 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1334
1335 if (!fwdl)
1336 rtw89_hex_dump(rtwdev, RTW89_DBG_FW, "H2C: ", skb->data, skb->len);
1337
1338 cnt = rtw89_hci_check_and_reclaim_tx_resource(rtwdev, RTW89_TXCH_CH12);
1339 if (cnt == 0) {
1340 rtw89_err(rtwdev, "no tx fwcmd resource\n");
1341 return -ENOSPC;
1342 }
1343
1344 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1345 if (ret) {
1346 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1347 return ret;
1348 }
1349 rtw89_hci_tx_kick_off(rtwdev, RTW89_TXCH_CH12);
1350
1351 return 0;
1352 }
1353
rtw89_core_tx_write_link(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link,struct sk_buff * skb,int * qsel,struct rtw89_tx_wait_info * wait)1354 static int rtw89_core_tx_write_link(struct rtw89_dev *rtwdev,
1355 struct rtw89_vif_link *rtwvif_link,
1356 struct rtw89_sta_link *rtwsta_link,
1357 struct sk_buff *skb, int *qsel,
1358 struct rtw89_tx_wait_info *wait)
1359 {
1360 struct ieee80211_sta *sta = rtwsta_link_to_sta_safe(rtwsta_link);
1361 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
1362 struct rtw89_tx_skb_data *skb_data = RTW89_TX_SKB_CB(skb);
1363 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
1364 struct rtw89_core_tx_request tx_req = {};
1365 int ret;
1366
1367 tx_req.skb = skb;
1368 tx_req.vif = vif;
1369 tx_req.sta = sta;
1370 tx_req.rtwvif_link = rtwvif_link;
1371 tx_req.rtwsta_link = rtwsta_link;
1372 tx_req.with_wait = !!wait;
1373
1374 rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, true, true);
1375 rtw89_wow_parse_akm(rtwdev, skb);
1376 rtw89_core_tx_update_desc_info(rtwdev, &tx_req);
1377 rtw89_core_tx_wake(rtwdev, &tx_req);
1378
1379 rcu_assign_pointer(skb_data->wait, wait);
1380
1381 ret = rtw89_hci_tx_write(rtwdev, &tx_req);
1382 if (ret) {
1383 rtw89_err(rtwdev, "failed to transmit skb to HCI\n");
1384 return ret;
1385 }
1386
1387 if (qsel)
1388 *qsel = tx_req.desc_info.qsel;
1389
1390 return 0;
1391 }
1392
rtw89_core_tx_write(struct rtw89_dev * rtwdev,struct ieee80211_vif * vif,struct ieee80211_sta * sta,struct sk_buff * skb,int * qsel)1393 int rtw89_core_tx_write(struct rtw89_dev *rtwdev, struct ieee80211_vif *vif,
1394 struct ieee80211_sta *sta, struct sk_buff *skb, int *qsel)
1395 {
1396 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
1397 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
1398 struct rtw89_sta_link *rtwsta_link = NULL;
1399 struct rtw89_vif_link *rtwvif_link;
1400
1401 if (rtwsta) {
1402 rtwsta_link = rtw89_get_designated_link(rtwsta);
1403 if (unlikely(!rtwsta_link)) {
1404 rtw89_err(rtwdev, "tx: find no sta designated link\n");
1405 return -ENOLINK;
1406 }
1407
1408 rtwvif_link = rtwsta_link->rtwvif_link;
1409 } else {
1410 rtwvif_link = rtw89_get_designated_link(rtwvif);
1411 if (unlikely(!rtwvif_link)) {
1412 rtw89_err(rtwdev, "tx: find no vif designated link\n");
1413 return -ENOLINK;
1414 }
1415 }
1416
1417 return rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, qsel, NULL);
1418 }
1419
rtw89_build_txwd_body0(struct rtw89_tx_desc_info * desc_info)1420 static __le32 rtw89_build_txwd_body0(struct rtw89_tx_desc_info *desc_info)
1421 {
1422 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET, desc_info->wp_offset) |
1423 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1424 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1425 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1426 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1427 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl) |
1428 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_SEL, desc_info->hw_ssn_sel) |
1429 FIELD_PREP(RTW89_TXWD_BODY0_HW_SSN_MODE, desc_info->hw_seq_mode);
1430
1431 return cpu_to_le32(dword);
1432 }
1433
rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info * desc_info)1434 static __le32 rtw89_build_txwd_body0_v1(struct rtw89_tx_desc_info *desc_info)
1435 {
1436 u32 dword = FIELD_PREP(RTW89_TXWD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1437 FIELD_PREP(RTW89_TXWD_BODY0_WD_INFO_EN, desc_info->en_wd_info) |
1438 FIELD_PREP(RTW89_TXWD_BODY0_CHANNEL_DMA, desc_info->ch_dma) |
1439 FIELD_PREP(RTW89_TXWD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1440 FIELD_PREP(RTW89_TXWD_BODY0_WD_PAGE, desc_info->wd_page) |
1441 FIELD_PREP(RTW89_TXWD_BODY0_FW_DL, desc_info->fw_dl);
1442
1443 return cpu_to_le32(dword);
1444 }
1445
rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info * desc_info)1446 static __le32 rtw89_build_txwd_body1_v1(struct rtw89_tx_desc_info *desc_info)
1447 {
1448 u32 dword = FIELD_PREP(RTW89_TXWD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1449 FIELD_PREP(RTW89_TXWD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1450 FIELD_PREP(RTW89_TXWD_BODY1_SEC_TYPE, desc_info->sec_type);
1451
1452 return cpu_to_le32(dword);
1453 }
1454
rtw89_build_txwd_body2(struct rtw89_tx_desc_info * desc_info)1455 static __le32 rtw89_build_txwd_body2(struct rtw89_tx_desc_info *desc_info)
1456 {
1457 u32 dword = FIELD_PREP(RTW89_TXWD_BODY2_TID_INDICATE, desc_info->tid_indicate) |
1458 FIELD_PREP(RTW89_TXWD_BODY2_QSEL, desc_info->qsel) |
1459 FIELD_PREP(RTW89_TXWD_BODY2_TXPKT_SIZE, desc_info->pkt_size) |
1460 FIELD_PREP(RTW89_TXWD_BODY2_MACID, desc_info->mac_id);
1461
1462 return cpu_to_le32(dword);
1463 }
1464
rtw89_build_txwd_body3(struct rtw89_tx_desc_info * desc_info)1465 static __le32 rtw89_build_txwd_body3(struct rtw89_tx_desc_info *desc_info)
1466 {
1467 u32 dword = FIELD_PREP(RTW89_TXWD_BODY3_SW_SEQ, desc_info->seq) |
1468 FIELD_PREP(RTW89_TXWD_BODY3_AGG_EN, desc_info->agg_en) |
1469 FIELD_PREP(RTW89_TXWD_BODY3_BK, desc_info->bk);
1470
1471 return cpu_to_le32(dword);
1472 }
1473
rtw89_build_txwd_body4(struct rtw89_tx_desc_info * desc_info)1474 static __le32 rtw89_build_txwd_body4(struct rtw89_tx_desc_info *desc_info)
1475 {
1476 u32 dword = FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1477 FIELD_PREP(RTW89_TXWD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1478
1479 return cpu_to_le32(dword);
1480 }
1481
rtw89_build_txwd_body5(struct rtw89_tx_desc_info * desc_info)1482 static __le32 rtw89_build_txwd_body5(struct rtw89_tx_desc_info *desc_info)
1483 {
1484 u32 dword = FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1485 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1486 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1487 FIELD_PREP(RTW89_TXWD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1488
1489 return cpu_to_le32(dword);
1490 }
1491
rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info * desc_info)1492 static __le32 rtw89_build_txwd_body7_v1(struct rtw89_tx_desc_info *desc_info)
1493 {
1494 u32 dword = FIELD_PREP(RTW89_TXWD_BODY7_USE_RATE_V1, desc_info->use_rate) |
1495 FIELD_PREP(RTW89_TXWD_BODY7_DATA_BW, desc_info->data_bw) |
1496 FIELD_PREP(RTW89_TXWD_BODY7_GI_LTF, desc_info->gi_ltf) |
1497 FIELD_PREP(RTW89_TXWD_BODY7_DATA_RATE, desc_info->data_rate);
1498
1499 return cpu_to_le32(dword);
1500 }
1501
rtw89_build_txwd_info0(struct rtw89_tx_desc_info * desc_info)1502 static __le32 rtw89_build_txwd_info0(struct rtw89_tx_desc_info *desc_info)
1503 {
1504 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_USE_RATE, desc_info->use_rate) |
1505 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW, desc_info->data_bw) |
1506 FIELD_PREP(RTW89_TXWD_INFO0_GI_LTF, desc_info->gi_ltf) |
1507 FIELD_PREP(RTW89_TXWD_INFO0_DATA_RATE, desc_info->data_rate) |
1508 FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1509 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1510 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1511 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port);
1512
1513 return cpu_to_le32(dword);
1514 }
1515
rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info * desc_info)1516 static __le32 rtw89_build_txwd_info0_v1(struct rtw89_tx_desc_info *desc_info)
1517 {
1518 u32 dword = FIELD_PREP(RTW89_TXWD_INFO0_DATA_STBC, desc_info->stbc) |
1519 FIELD_PREP(RTW89_TXWD_INFO0_DATA_LDPC, desc_info->ldpc) |
1520 FIELD_PREP(RTW89_TXWD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1521 FIELD_PREP(RTW89_TXWD_INFO0_MULTIPORT_ID, desc_info->port) |
1522 FIELD_PREP(RTW89_TXWD_INFO0_DATA_ER, desc_info->er_cap) |
1523 FIELD_PREP(RTW89_TXWD_INFO0_DATA_BW_ER, 0);
1524
1525 return cpu_to_le32(dword);
1526 }
1527
rtw89_build_txwd_info1(struct rtw89_tx_desc_info * desc_info)1528 static __le32 rtw89_build_txwd_info1(struct rtw89_tx_desc_info *desc_info)
1529 {
1530 u32 dword = FIELD_PREP(RTW89_TXWD_INFO1_MAX_AGGNUM, desc_info->ampdu_num) |
1531 FIELD_PREP(RTW89_TXWD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1532 FIELD_PREP(RTW89_TXWD_INFO1_DATA_RTY_LOWEST_RATE,
1533 desc_info->data_retry_lowest_rate) |
1534 FIELD_PREP(RTW89_TXWD_INFO1_DATA_TXCNT_LMT_SEL,
1535 desc_info->tx_cnt_lmt_en) |
1536 FIELD_PREP(RTW89_TXWD_INFO1_DATA_TXCNT_LMT, desc_info->tx_cnt_lmt);
1537
1538 return cpu_to_le32(dword);
1539 }
1540
rtw89_build_txwd_info2(struct rtw89_tx_desc_info * desc_info)1541 static __le32 rtw89_build_txwd_info2(struct rtw89_tx_desc_info *desc_info)
1542 {
1543 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1544 FIELD_PREP(RTW89_TXWD_INFO2_SEC_TYPE, desc_info->sec_type) |
1545 FIELD_PREP(RTW89_TXWD_INFO2_SEC_HW_ENC, desc_info->sec_en) |
1546 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1547
1548 return cpu_to_le32(dword);
1549 }
1550
rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info * desc_info)1551 static __le32 rtw89_build_txwd_info2_v1(struct rtw89_tx_desc_info *desc_info)
1552 {
1553 u32 dword = FIELD_PREP(RTW89_TXWD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1554 FIELD_PREP(RTW89_TXWD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1555 FIELD_PREP(RTW89_TXWD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx);
1556
1557 return cpu_to_le32(dword);
1558 }
1559
rtw89_build_txwd_info3(struct rtw89_tx_desc_info * desc_info)1560 static __le32 rtw89_build_txwd_info3(struct rtw89_tx_desc_info *desc_info)
1561 {
1562 u32 dword = FIELD_PREP(RTW89_TXWD_INFO3_SPE_RPT, desc_info->report);
1563
1564 return cpu_to_le32(dword);
1565 }
1566
rtw89_build_txwd_info4(struct rtw89_tx_desc_info * desc_info)1567 static __le32 rtw89_build_txwd_info4(struct rtw89_tx_desc_info *desc_info)
1568 {
1569 bool rts_en = !desc_info->is_bmc;
1570 u32 dword = FIELD_PREP(RTW89_TXWD_INFO4_RTS_EN, rts_en) |
1571 FIELD_PREP(RTW89_TXWD_INFO4_HW_RTS_EN, 1) |
1572 FIELD_PREP(RTW89_TXWD_INFO4_SW_DEFINE, desc_info->sn);
1573
1574 return cpu_to_le32(dword);
1575 }
1576
rtw89_core_fill_txdesc(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1577 void rtw89_core_fill_txdesc(struct rtw89_dev *rtwdev,
1578 struct rtw89_tx_desc_info *desc_info,
1579 void *txdesc)
1580 {
1581 struct rtw89_txwd_body *txwd_body = (struct rtw89_txwd_body *)txdesc;
1582 struct rtw89_txwd_info *txwd_info;
1583
1584 txwd_body->dword0 = rtw89_build_txwd_body0(desc_info);
1585 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1586 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1587
1588 if (!desc_info->en_wd_info)
1589 return;
1590
1591 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1592 txwd_info->dword0 = rtw89_build_txwd_info0(desc_info);
1593 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1594 txwd_info->dword2 = rtw89_build_txwd_info2(desc_info);
1595 txwd_info->dword3 = rtw89_build_txwd_info3(desc_info);
1596 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1597
1598 }
1599 EXPORT_SYMBOL(rtw89_core_fill_txdesc);
1600
rtw89_core_fill_txdesc_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1601 void rtw89_core_fill_txdesc_v1(struct rtw89_dev *rtwdev,
1602 struct rtw89_tx_desc_info *desc_info,
1603 void *txdesc)
1604 {
1605 struct rtw89_txwd_body_v1 *txwd_body = (struct rtw89_txwd_body_v1 *)txdesc;
1606 struct rtw89_txwd_info *txwd_info;
1607
1608 txwd_body->dword0 = rtw89_build_txwd_body0_v1(desc_info);
1609 txwd_body->dword1 = rtw89_build_txwd_body1_v1(desc_info);
1610 txwd_body->dword2 = rtw89_build_txwd_body2(desc_info);
1611 txwd_body->dword3 = rtw89_build_txwd_body3(desc_info);
1612 if (desc_info->sec_en) {
1613 txwd_body->dword4 = rtw89_build_txwd_body4(desc_info);
1614 txwd_body->dword5 = rtw89_build_txwd_body5(desc_info);
1615 }
1616 txwd_body->dword7 = rtw89_build_txwd_body7_v1(desc_info);
1617
1618 if (!desc_info->en_wd_info)
1619 return;
1620
1621 txwd_info = (struct rtw89_txwd_info *)(txwd_body + 1);
1622 txwd_info->dword0 = rtw89_build_txwd_info0_v1(desc_info);
1623 txwd_info->dword1 = rtw89_build_txwd_info1(desc_info);
1624 txwd_info->dword2 = rtw89_build_txwd_info2_v1(desc_info);
1625 txwd_info->dword3 = rtw89_build_txwd_info3(desc_info);
1626 txwd_info->dword4 = rtw89_build_txwd_info4(desc_info);
1627 }
1628 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v1);
1629
rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info * desc_info)1630 static __le32 rtw89_build_txwd_body0_v2(struct rtw89_tx_desc_info *desc_info)
1631 {
1632 u32 dword = FIELD_PREP(BE_TXD_BODY0_WP_OFFSET_V1, desc_info->wp_offset) |
1633 FIELD_PREP(BE_TXD_BODY0_WDINFO_EN, desc_info->en_wd_info) |
1634 FIELD_PREP(BE_TXD_BODY0_CH_DMA, desc_info->ch_dma) |
1635 FIELD_PREP(BE_TXD_BODY0_HDR_LLC_LEN, desc_info->hdr_llc_len) |
1636 FIELD_PREP(BE_TXD_BODY0_WD_PAGE, desc_info->wd_page);
1637
1638 return cpu_to_le32(dword);
1639 }
1640
rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info * desc_info)1641 static __le32 rtw89_build_txwd_body1_v2(struct rtw89_tx_desc_info *desc_info)
1642 {
1643 u32 dword = FIELD_PREP(BE_TXD_BODY1_ADDR_INFO_NUM, desc_info->addr_info_nr) |
1644 FIELD_PREP(BE_TXD_BODY1_SEC_KEYID, desc_info->sec_keyid) |
1645 FIELD_PREP(BE_TXD_BODY1_SEC_TYPE, desc_info->sec_type);
1646
1647 return cpu_to_le32(dword);
1648 }
1649
rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info * desc_info)1650 static __le32 rtw89_build_txwd_body2_v2(struct rtw89_tx_desc_info *desc_info)
1651 {
1652 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND, desc_info->tid_indicate) |
1653 FIELD_PREP(BE_TXD_BODY2_QSEL, desc_info->qsel) |
1654 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) |
1655 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) |
1656 FIELD_PREP(BE_TXD_BODY2_BK, desc_info->bk) |
1657 FIELD_PREP(BE_TXD_BODY2_MACID, desc_info->mac_id);
1658
1659 return cpu_to_le32(dword);
1660 }
1661
rtw89_build_txwd_body2_v3(struct rtw89_tx_desc_info * desc_info)1662 static __le32 rtw89_build_txwd_body2_v3(struct rtw89_tx_desc_info *desc_info)
1663 {
1664 u32 dword = FIELD_PREP(BE_TXD_BODY2_TID_IND_V1, desc_info->tid_indicate) |
1665 FIELD_PREP(BE_TXD_BODY2_QSEL_V1, desc_info->qsel) |
1666 FIELD_PREP(BE_TXD_BODY2_TXPKTSIZE, desc_info->pkt_size) |
1667 FIELD_PREP(BE_TXD_BODY2_AGG_EN, desc_info->agg_en) |
1668 FIELD_PREP(BE_TXD_BODY2_MACID_V1, desc_info->mac_id);
1669
1670 return cpu_to_le32(dword);
1671 }
1672
rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info * desc_info)1673 static __le32 rtw89_build_txwd_body3_v2(struct rtw89_tx_desc_info *desc_info)
1674 {
1675 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) |
1676 FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) |
1677 FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld);
1678
1679 return cpu_to_le32(dword);
1680 }
1681
rtw89_build_txwd_body3_v3(struct rtw89_tx_desc_info * desc_info)1682 static __le32 rtw89_build_txwd_body3_v3(struct rtw89_tx_desc_info *desc_info)
1683 {
1684 u32 dword = FIELD_PREP(BE_TXD_BODY3_WIFI_SEQ, desc_info->seq) |
1685 FIELD_PREP(BE_TXD_BODY3_MLO_FLAG, desc_info->mlo) |
1686 FIELD_PREP(BE_TXD_BODY3_IS_MLD_SW_EN, desc_info->sw_mld) |
1687 FIELD_PREP(BE_TXD_BODY3_BK_V1, desc_info->bk);
1688
1689 return cpu_to_le32(dword);
1690 }
1691
rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info * desc_info)1692 static __le32 rtw89_build_txwd_body4_v2(struct rtw89_tx_desc_info *desc_info)
1693 {
1694 u32 dword = FIELD_PREP(BE_TXD_BODY4_SEC_IV_L0, desc_info->sec_seq[0]) |
1695 FIELD_PREP(BE_TXD_BODY4_SEC_IV_L1, desc_info->sec_seq[1]);
1696
1697 return cpu_to_le32(dword);
1698 }
1699
rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info * desc_info)1700 static __le32 rtw89_build_txwd_body5_v2(struct rtw89_tx_desc_info *desc_info)
1701 {
1702 u32 dword = FIELD_PREP(BE_TXD_BODY5_SEC_IV_H2, desc_info->sec_seq[2]) |
1703 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H3, desc_info->sec_seq[3]) |
1704 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H4, desc_info->sec_seq[4]) |
1705 FIELD_PREP(BE_TXD_BODY5_SEC_IV_H5, desc_info->sec_seq[5]);
1706
1707 return cpu_to_le32(dword);
1708 }
1709
rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info * desc_info)1710 static __le32 rtw89_build_txwd_body6_v2(struct rtw89_tx_desc_info *desc_info)
1711 {
1712 u32 dword = FIELD_PREP(BE_TXD_BODY6_UPD_WLAN_HDR, desc_info->upd_wlan_hdr);
1713
1714 return cpu_to_le32(dword);
1715 }
1716
rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info * desc_info)1717 static __le32 rtw89_build_txwd_body7_v2(struct rtw89_tx_desc_info *desc_info)
1718 {
1719 u32 dword = FIELD_PREP(BE_TXD_BODY7_USERATE_SEL, desc_info->use_rate) |
1720 FIELD_PREP(BE_TXD_BODY7_DATA_BW, desc_info->data_bw) |
1721 FIELD_PREP(BE_TXD_BODY7_GI_LTF, desc_info->gi_ltf) |
1722 FIELD_PREP(BE_TXD_BODY7_DATA_ER, desc_info->er_cap) |
1723 FIELD_PREP(BE_TXD_BODY7_DATA_BW_ER, 0) |
1724 FIELD_PREP(BE_TXD_BODY7_DATARATE, desc_info->data_rate);
1725
1726 return cpu_to_le32(dword);
1727 }
1728
rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info * desc_info)1729 static __le32 rtw89_build_txwd_info0_v2(struct rtw89_tx_desc_info *desc_info)
1730 {
1731 u32 dword = FIELD_PREP(BE_TXD_INFO0_DATA_STBC, desc_info->stbc) |
1732 FIELD_PREP(BE_TXD_INFO0_DATA_LDPC, desc_info->ldpc) |
1733 FIELD_PREP(BE_TXD_INFO0_DISDATAFB, desc_info->dis_data_fb) |
1734 FIELD_PREP(BE_TXD_INFO0_MULTIPORT_ID, desc_info->port) |
1735 FIELD_PREP(BE_TXD_INFO0_DATA_TXCNT_LMT_SEL,
1736 desc_info->tx_cnt_lmt_en) |
1737 FIELD_PREP(BE_TXD_INFO0_DATA_TXCNT_LMT, desc_info->tx_cnt_lmt);
1738
1739 return cpu_to_le32(dword);
1740 }
1741
rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info * desc_info)1742 static __le32 rtw89_build_txwd_info1_v2(struct rtw89_tx_desc_info *desc_info)
1743 {
1744 u32 dword = FIELD_PREP(BE_TXD_INFO1_MAX_AGG_NUM, desc_info->ampdu_num) |
1745 FIELD_PREP(BE_TXD_INFO1_A_CTRL_BSR, desc_info->a_ctrl_bsr) |
1746 FIELD_PREP(BE_TXD_INFO1_DATA_RTY_LOWEST_RATE,
1747 desc_info->data_retry_lowest_rate) |
1748 FIELD_PREP(BE_TXD_INFO1_SW_DEFINE, desc_info->sn);
1749
1750 return cpu_to_le32(dword);
1751 }
1752
rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info * desc_info)1753 static __le32 rtw89_build_txwd_info2_v2(struct rtw89_tx_desc_info *desc_info)
1754 {
1755 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1756 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN, desc_info->sec_en) |
1757 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX, desc_info->sec_cam_idx) |
1758 FIELD_PREP(BE_TXD_INFO2_SPE_RPT_V1, desc_info->report);
1759
1760 return cpu_to_le32(dword);
1761 }
1762
rtw89_build_txwd_info2_v3(struct rtw89_tx_desc_info * desc_info)1763 static __le32 rtw89_build_txwd_info2_v3(struct rtw89_tx_desc_info *desc_info)
1764 {
1765 u32 dword = FIELD_PREP(BE_TXD_INFO2_AMPDU_DENSITY, desc_info->ampdu_density) |
1766 FIELD_PREP(BE_TXD_INFO2_FORCE_KEY_EN_V1, desc_info->sec_en) |
1767 FIELD_PREP(BE_TXD_INFO2_SEC_CAM_IDX_V1, desc_info->sec_cam_idx);
1768
1769 return cpu_to_le32(dword);
1770 }
1771
rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info * desc_info)1772 static __le32 rtw89_build_txwd_info4_v2(struct rtw89_tx_desc_info *desc_info)
1773 {
1774 bool rts_en = !desc_info->is_bmc;
1775 u32 dword = FIELD_PREP(BE_TXD_INFO4_RTS_EN, rts_en) |
1776 FIELD_PREP(BE_TXD_INFO4_HW_RTS_EN, 1);
1777
1778 return cpu_to_le32(dword);
1779 }
1780
rtw89_core_fill_txdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1781 void rtw89_core_fill_txdesc_v2(struct rtw89_dev *rtwdev,
1782 struct rtw89_tx_desc_info *desc_info,
1783 void *txdesc)
1784 {
1785 struct rtw89_txwd_body_v2 *txwd_body = txdesc;
1786 struct rtw89_txwd_info_v2 *txwd_info;
1787
1788 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info);
1789 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info);
1790 txwd_body->dword2 = rtw89_build_txwd_body2_v2(desc_info);
1791 txwd_body->dword3 = rtw89_build_txwd_body3_v2(desc_info);
1792 if (desc_info->sec_en) {
1793 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info);
1794 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info);
1795 }
1796 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info);
1797 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info);
1798
1799 if (!desc_info->en_wd_info)
1800 return;
1801
1802 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1);
1803 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info);
1804 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info);
1805 txwd_info->dword2 = rtw89_build_txwd_info2_v2(desc_info);
1806 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info);
1807 }
1808 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v2);
1809
rtw89_core_fill_txdesc_v3(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1810 void rtw89_core_fill_txdesc_v3(struct rtw89_dev *rtwdev,
1811 struct rtw89_tx_desc_info *desc_info,
1812 void *txdesc)
1813 {
1814 struct rtw89_txwd_body_v2 *txwd_body = txdesc;
1815 struct rtw89_txwd_info_v2 *txwd_info;
1816
1817 txwd_body->dword0 = rtw89_build_txwd_body0_v2(desc_info);
1818 txwd_body->dword1 = rtw89_build_txwd_body1_v2(desc_info);
1819 txwd_body->dword2 = rtw89_build_txwd_body2_v3(desc_info);
1820 txwd_body->dword3 = rtw89_build_txwd_body3_v3(desc_info);
1821 if (desc_info->sec_en) {
1822 txwd_body->dword4 = rtw89_build_txwd_body4_v2(desc_info);
1823 txwd_body->dword5 = rtw89_build_txwd_body5_v2(desc_info);
1824 }
1825 txwd_body->dword6 = rtw89_build_txwd_body6_v2(desc_info);
1826 txwd_body->dword7 = rtw89_build_txwd_body7_v2(desc_info);
1827
1828 if (!desc_info->en_wd_info)
1829 return;
1830
1831 txwd_info = (struct rtw89_txwd_info_v2 *)(txwd_body + 1);
1832 txwd_info->dword0 = rtw89_build_txwd_info0_v2(desc_info);
1833 txwd_info->dword1 = rtw89_build_txwd_info1_v2(desc_info);
1834 txwd_info->dword2 = rtw89_build_txwd_info2_v3(desc_info);
1835 txwd_info->dword4 = rtw89_build_txwd_info4_v2(desc_info);
1836 }
1837 EXPORT_SYMBOL(rtw89_core_fill_txdesc_v3);
1838
rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info * desc_info)1839 static __le32 rtw89_build_txwd_fwcmd0_v1(struct rtw89_tx_desc_info *desc_info)
1840 {
1841 u32 dword = FIELD_PREP(AX_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1842 FIELD_PREP(AX_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1843 RTW89_CORE_RX_TYPE_FWDL :
1844 RTW89_CORE_RX_TYPE_H2C);
1845
1846 return cpu_to_le32(dword);
1847 }
1848
rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1849 void rtw89_core_fill_txdesc_fwcmd_v1(struct rtw89_dev *rtwdev,
1850 struct rtw89_tx_desc_info *desc_info,
1851 void *txdesc)
1852 {
1853 struct rtw89_rxdesc_short *txwd_v1 = (struct rtw89_rxdesc_short *)txdesc;
1854
1855 txwd_v1->dword0 = rtw89_build_txwd_fwcmd0_v1(desc_info);
1856 }
1857 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v1);
1858
rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info * desc_info)1859 static __le32 rtw89_build_txwd_fwcmd0_v2(struct rtw89_tx_desc_info *desc_info)
1860 {
1861 u32 dword = FIELD_PREP(BE_RXD_RPKT_LEN_MASK, desc_info->pkt_size) |
1862 FIELD_PREP(BE_RXD_RPKT_TYPE_MASK, desc_info->fw_dl ?
1863 RTW89_CORE_RX_TYPE_FWDL :
1864 RTW89_CORE_RX_TYPE_H2C);
1865
1866 return cpu_to_le32(dword);
1867 }
1868
rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev * rtwdev,struct rtw89_tx_desc_info * desc_info,void * txdesc)1869 void rtw89_core_fill_txdesc_fwcmd_v2(struct rtw89_dev *rtwdev,
1870 struct rtw89_tx_desc_info *desc_info,
1871 void *txdesc)
1872 {
1873 struct rtw89_rxdesc_short_v2 *txwd_v2 = (struct rtw89_rxdesc_short_v2 *)txdesc;
1874
1875 txwd_v2->dword0 = rtw89_build_txwd_fwcmd0_v2(desc_info);
1876 }
1877 EXPORT_SYMBOL(rtw89_core_fill_txdesc_fwcmd_v2);
1878
rtw89_core_rx_process_mac_ppdu(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_rx_phy_ppdu * phy_ppdu)1879 static int rtw89_core_rx_process_mac_ppdu(struct rtw89_dev *rtwdev,
1880 struct sk_buff *skb,
1881 struct rtw89_rx_phy_ppdu *phy_ppdu)
1882 {
1883 const struct rtw89_chip_info *chip = rtwdev->chip;
1884 const struct rtw89_rxinfo *rxinfo = (const struct rtw89_rxinfo *)skb->data;
1885 const struct rtw89_rxinfo_user *user;
1886 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
1887 int rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE;
1888 bool rx_cnt_valid = false;
1889 bool invalid = false;
1890 u8 plcp_size = 0;
1891 u8 *phy_sts;
1892 u8 usr_num;
1893 int i;
1894
1895 if (chip_gen == RTW89_CHIP_BE) {
1896 invalid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_INVALID_V1);
1897 rx_cnt_size = RTW89_PPDU_MAC_RX_CNT_SIZE_V1;
1898 }
1899
1900 if (invalid)
1901 return -EINVAL;
1902
1903 rx_cnt_valid = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_RX_CNT_VLD);
1904 if (chip_gen == RTW89_CHIP_BE) {
1905 plcp_size = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_PLCP_LEN_V1) << 3;
1906 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM_V1);
1907 } else {
1908 plcp_size = le32_get_bits(rxinfo->w1, RTW89_RXINFO_W1_PLCP_LEN) << 3;
1909 usr_num = le32_get_bits(rxinfo->w0, RTW89_RXINFO_W0_USR_NUM);
1910 }
1911 if (usr_num > chip->ppdu_max_usr) {
1912 rtw89_warn(rtwdev, "Invalid user number (%d) in mac info\n",
1913 usr_num);
1914 return -EINVAL;
1915 }
1916
1917 for (i = 0; i < usr_num; i++) {
1918 user = &rxinfo->user[i];
1919 if (!le32_get_bits(user->w0, RTW89_RXINFO_USER_MAC_ID_VALID))
1920 continue;
1921 /* For WiFi 7 chips, RXWD.mac_id of PPDU status is not set
1922 * by hardware, so update mac_id by rxinfo_user[].mac_id.
1923 */
1924 if (chip->chip_id == RTL8922A)
1925 phy_ppdu->mac_id =
1926 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID);
1927 else if (chip->chip_id == RTL8922D)
1928 phy_ppdu->mac_id =
1929 le32_get_bits(user->w0, RTW89_RXINFO_USER_MACID_V1);
1930
1931 phy_ppdu->has_data =
1932 le32_get_bits(user->w0, RTW89_RXINFO_USER_DATA);
1933 phy_ppdu->has_bcn =
1934 le32_get_bits(user->w0, RTW89_RXINFO_USER_BCN);
1935 break;
1936 }
1937
1938 phy_sts = skb->data + RTW89_PPDU_MAC_INFO_SIZE;
1939 phy_sts += usr_num * RTW89_PPDU_MAC_INFO_USR_SIZE;
1940 /* 8-byte alignment */
1941 if (usr_num & BIT(0))
1942 phy_sts += RTW89_PPDU_MAC_INFO_USR_SIZE;
1943 if (rx_cnt_valid)
1944 phy_sts += rx_cnt_size;
1945 phy_sts += plcp_size;
1946
1947 if (phy_sts > skb->data + skb->len)
1948 return -EINVAL;
1949
1950 phy_ppdu->buf = phy_sts;
1951 phy_ppdu->len = skb->data + skb->len - phy_sts;
1952
1953 return 0;
1954 }
1955
rtw89_get_data_rate_nss(struct rtw89_dev * rtwdev,u16 data_rate)1956 static u8 rtw89_get_data_rate_nss(struct rtw89_dev *rtwdev, u16 data_rate)
1957 {
1958 u8 data_rate_mode;
1959
1960 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
1961 switch (data_rate_mode) {
1962 case DATA_RATE_MODE_NON_HT:
1963 return 1;
1964 case DATA_RATE_MODE_HT:
1965 return rtw89_get_data_ht_nss(rtwdev, data_rate) + 1;
1966 case DATA_RATE_MODE_VHT:
1967 case DATA_RATE_MODE_HE:
1968 case DATA_RATE_MODE_EHT:
1969 return rtw89_get_data_nss(rtwdev, data_rate) + 1;
1970 default:
1971 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
1972 return 0;
1973 }
1974 }
1975
rtw89_core_rx_process_phy_ppdu_iter(void * data,struct ieee80211_sta * sta)1976 static void rtw89_core_rx_process_phy_ppdu_iter(void *data,
1977 struct ieee80211_sta *sta)
1978 {
1979 struct rtw89_rx_phy_ppdu *phy_ppdu = (struct rtw89_rx_phy_ppdu *)data;
1980 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
1981 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
1982 struct rtw89_hal *hal = &rtwdev->hal;
1983 struct rtw89_sta_link *rtwsta_link;
1984 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
1985 u8 ant_pos = U8_MAX;
1986 u8 evm_pos = 0;
1987 int i;
1988
1989 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, phy_ppdu->phy_idx);
1990 if (unlikely(!rtwsta_link))
1991 return;
1992
1993 if (rtwsta_link->mac_id != phy_ppdu->mac_id || !phy_ppdu->to_self)
1994 return;
1995
1996 if (hal->ant_diversity && hal->antenna_rx) {
1997 ant_pos = __ffs(hal->antenna_rx);
1998 evm_pos = ant_pos;
1999 }
2000
2001 ewma_rssi_add(&rtwsta_link->avg_rssi, phy_ppdu->rssi_avg);
2002
2003 if (ant_pos < ant_num) {
2004 ewma_rssi_add(&rtwsta_link->rssi[ant_pos], phy_ppdu->rssi[0]);
2005 } else {
2006 for (i = 0; i < rtwdev->chip->rf_path_num; i++)
2007 ewma_rssi_add(&rtwsta_link->rssi[i], phy_ppdu->rssi[i]);
2008 }
2009
2010 if (phy_ppdu->ofdm.has && (phy_ppdu->has_data || phy_ppdu->has_bcn)) {
2011 ewma_snr_add(&rtwsta_link->avg_snr, phy_ppdu->ofdm.avg_snr);
2012 if (rtw89_get_data_rate_nss(rtwdev, phy_ppdu->rate) == 1) {
2013 ewma_evm_add(&rtwsta_link->evm_1ss, phy_ppdu->ofdm.evm_min);
2014 } else {
2015 ewma_evm_add(&rtwsta_link->evm_min[evm_pos],
2016 phy_ppdu->ofdm.evm_min);
2017 ewma_evm_add(&rtwsta_link->evm_max[evm_pos],
2018 phy_ppdu->ofdm.evm_max);
2019 }
2020 }
2021 }
2022
2023 #define VAR_LEN 0xff
2024 #define VAR_LEN_UNIT 8
rtw89_core_get_phy_status_ie_len(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr)2025 static u16 rtw89_core_get_phy_status_ie_len(struct rtw89_dev *rtwdev,
2026 const struct rtw89_phy_sts_iehdr *iehdr)
2027 {
2028 static const u8 physts_ie_len_tabs[RTW89_CHIP_GEN_NUM][32] = {
2029 [RTW89_CHIP_AX] = {
2030 16, 32, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
2031 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 16, 24, VAR_LEN,
2032 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
2033 },
2034 [RTW89_CHIP_BE] = {
2035 32, 40, 24, 24, 8, 8, 8, 8, VAR_LEN, 8, VAR_LEN, 176, VAR_LEN,
2036 VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, VAR_LEN, 88, 56, VAR_LEN,
2037 VAR_LEN, VAR_LEN, 0, 24, 24, 24, 24, 32, 32, 32, 32
2038 },
2039 };
2040 const u8 *physts_ie_len_tab;
2041 u16 ie_len;
2042 u8 ie;
2043
2044 physts_ie_len_tab = physts_ie_len_tabs[rtwdev->chip->chip_gen];
2045
2046 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
2047 if (physts_ie_len_tab[ie] != VAR_LEN)
2048 ie_len = physts_ie_len_tab[ie];
2049 else
2050 ie_len = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_LEN) * VAR_LEN_UNIT;
2051
2052 return ie_len;
2053 }
2054
rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2055 static void rtw89_core_parse_phy_status_ie01_v2(struct rtw89_dev *rtwdev,
2056 const struct rtw89_phy_sts_iehdr *iehdr,
2057 struct rtw89_rx_phy_ppdu *phy_ppdu)
2058 {
2059 const struct rtw89_phy_sts_ie01_v2 *ie;
2060 u8 *rpl_fd = phy_ppdu->rpl_fd;
2061
2062 ie = (const struct rtw89_phy_sts_ie01_v2 *)iehdr;
2063 rpl_fd[RF_PATH_A] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_A);
2064 rpl_fd[RF_PATH_B] = le32_get_bits(ie->w8, RTW89_PHY_STS_IE01_V2_W8_RPL_FD_B);
2065 rpl_fd[RF_PATH_C] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_C);
2066 rpl_fd[RF_PATH_D] = le32_get_bits(ie->w9, RTW89_PHY_STS_IE01_V2_W9_RPL_FD_D);
2067
2068 phy_ppdu->bw_idx = le32_get_bits(ie->w5, RTW89_PHY_STS_IE01_V2_W5_BW_IDX);
2069 }
2070
rtw89_core_parse_phy_status_ie01(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2071 static void rtw89_core_parse_phy_status_ie01(struct rtw89_dev *rtwdev,
2072 const struct rtw89_phy_sts_iehdr *iehdr,
2073 struct rtw89_rx_phy_ppdu *phy_ppdu)
2074 {
2075 const struct rtw89_phy_sts_ie01 *ie = (const struct rtw89_phy_sts_ie01 *)iehdr;
2076 s16 cfo;
2077 u32 t;
2078
2079 phy_ppdu->chan_idx = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_CH_IDX);
2080
2081 if (rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR) {
2082 phy_ppdu->ldpc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_LDPC);
2083 phy_ppdu->stbc = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_STBC);
2084 }
2085
2086 if (!phy_ppdu->hdr_2_en)
2087 phy_ppdu->rx_path_en =
2088 le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RX_PATH_EN);
2089
2090 if (phy_ppdu->rate < RTW89_HW_RATE_OFDM6)
2091 return;
2092
2093 if (!phy_ppdu->to_self)
2094 return;
2095
2096 phy_ppdu->rpl_avg = le32_get_bits(ie->w0, RTW89_PHY_STS_IE01_W0_RSSI_AVG_FD);
2097 phy_ppdu->ofdm.avg_snr = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_AVG_SNR);
2098 phy_ppdu->ofdm.evm_max = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MAX);
2099 phy_ppdu->ofdm.evm_min = le32_get_bits(ie->w2, RTW89_PHY_STS_IE01_W2_EVM_MIN);
2100 phy_ppdu->ofdm.has = true;
2101
2102 /* sign conversion for S(12,2) */
2103 if (rtwdev->chip->cfo_src_fd) {
2104 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_FD_CFO);
2105 cfo = sign_extend32(t, 11);
2106 } else {
2107 t = le32_get_bits(ie->w1, RTW89_PHY_STS_IE01_W1_PREMB_CFO);
2108 cfo = sign_extend32(t, 11);
2109 }
2110
2111 rtw89_phy_cfo_parse(rtwdev, cfo, phy_ppdu);
2112
2113 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
2114 rtw89_core_parse_phy_status_ie01_v2(rtwdev, iehdr, phy_ppdu);
2115 }
2116
rtw89_core_parse_phy_status_ie00(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2117 static void rtw89_core_parse_phy_status_ie00(struct rtw89_dev *rtwdev,
2118 const struct rtw89_phy_sts_iehdr *iehdr,
2119 struct rtw89_rx_phy_ppdu *phy_ppdu)
2120 {
2121 const struct rtw89_phy_sts_ie00 *ie = (const struct rtw89_phy_sts_ie00 *)iehdr;
2122 u16 tmp_rpl;
2123
2124 tmp_rpl = le32_get_bits(ie->w0, RTW89_PHY_STS_IE00_W0_RPL);
2125 phy_ppdu->rpl_avg = tmp_rpl >> 1;
2126
2127 if (!phy_ppdu->hdr_2_en)
2128 phy_ppdu->rx_path_en =
2129 le32_get_bits(ie->w3, RTW89_PHY_STS_IE00_W3_RX_PATH_EN);
2130 }
2131
rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2132 static void rtw89_core_parse_phy_status_ie00_v2(struct rtw89_dev *rtwdev,
2133 const struct rtw89_phy_sts_iehdr *iehdr,
2134 struct rtw89_rx_phy_ppdu *phy_ppdu)
2135 {
2136 const struct rtw89_phy_sts_ie00_v2 *ie;
2137 u8 *rpl_path = phy_ppdu->rpl_path;
2138 u16 tmp_rpl[RF_PATH_MAX];
2139 u8 i;
2140
2141 ie = (const struct rtw89_phy_sts_ie00_v2 *)iehdr;
2142 tmp_rpl[RF_PATH_A] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_A);
2143 tmp_rpl[RF_PATH_B] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_B);
2144 tmp_rpl[RF_PATH_C] = le32_get_bits(ie->w4, RTW89_PHY_STS_IE00_V2_W4_RPL_TD_C);
2145 tmp_rpl[RF_PATH_D] = le32_get_bits(ie->w5, RTW89_PHY_STS_IE00_V2_W5_RPL_TD_D);
2146
2147 for (i = 0; i < RF_PATH_MAX; i++)
2148 rpl_path[i] = tmp_rpl[i] >> 1;
2149 }
2150
rtw89_core_process_phy_status_ie(struct rtw89_dev * rtwdev,const struct rtw89_phy_sts_iehdr * iehdr,struct rtw89_rx_phy_ppdu * phy_ppdu)2151 static int rtw89_core_process_phy_status_ie(struct rtw89_dev *rtwdev,
2152 const struct rtw89_phy_sts_iehdr *iehdr,
2153 struct rtw89_rx_phy_ppdu *phy_ppdu)
2154 {
2155 u8 ie;
2156
2157 ie = le32_get_bits(iehdr->w0, RTW89_PHY_STS_IEHDR_TYPE);
2158
2159 switch (ie) {
2160 case RTW89_PHYSTS_IE00_CMN_CCK:
2161 rtw89_core_parse_phy_status_ie00(rtwdev, iehdr, phy_ppdu);
2162 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
2163 rtw89_core_parse_phy_status_ie00_v2(rtwdev, iehdr, phy_ppdu);
2164 break;
2165 case RTW89_PHYSTS_IE01_CMN_OFDM:
2166 rtw89_core_parse_phy_status_ie01(rtwdev, iehdr, phy_ppdu);
2167 break;
2168 default:
2169 break;
2170 }
2171
2172 return 0;
2173 }
2174
rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu * phy_ppdu)2175 static void rtw89_core_update_phy_ppdu_hdr_v2(struct rtw89_rx_phy_ppdu *phy_ppdu)
2176 {
2177 const struct rtw89_phy_sts_hdr_v2 *hdr = phy_ppdu->buf + PHY_STS_HDR_LEN;
2178
2179 phy_ppdu->rx_path_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_V2_W0_PATH_EN);
2180 }
2181
rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu * phy_ppdu)2182 static void rtw89_core_update_phy_ppdu(struct rtw89_rx_phy_ppdu *phy_ppdu)
2183 {
2184 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
2185 u8 *rssi = phy_ppdu->rssi;
2186
2187 phy_ppdu->ie = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_IE_MAP);
2188 phy_ppdu->rssi_avg = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_RSSI_AVG);
2189 rssi[RF_PATH_A] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_A);
2190 rssi[RF_PATH_B] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_B);
2191 rssi[RF_PATH_C] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_C);
2192 rssi[RF_PATH_D] = le32_get_bits(hdr->w1, RTW89_PHY_STS_HDR_W1_RSSI_D);
2193
2194 phy_ppdu->hdr_2_en = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_HDR_2_EN);
2195 if (phy_ppdu->hdr_2_en)
2196 rtw89_core_update_phy_ppdu_hdr_v2(phy_ppdu);
2197 }
2198
rtw89_core_rx_process_phy_ppdu(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)2199 static int rtw89_core_rx_process_phy_ppdu(struct rtw89_dev *rtwdev,
2200 struct rtw89_rx_phy_ppdu *phy_ppdu)
2201 {
2202 const struct rtw89_phy_sts_hdr *hdr = phy_ppdu->buf;
2203 u32 len_from_header;
2204 bool physts_valid;
2205
2206 physts_valid = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_VALID);
2207 if (!physts_valid)
2208 return -EINVAL;
2209
2210 len_from_header = le32_get_bits(hdr->w0, RTW89_PHY_STS_HDR_W0_LEN) << 3;
2211
2212 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE)
2213 len_from_header += PHY_STS_HDR_LEN;
2214
2215 if (len_from_header != phy_ppdu->len) {
2216 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "phy ppdu len mismatch\n");
2217 return -EINVAL;
2218 }
2219 rtw89_core_update_phy_ppdu(phy_ppdu);
2220
2221 return 0;
2222 }
2223
rtw89_core_rx_parse_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)2224 static int rtw89_core_rx_parse_phy_sts(struct rtw89_dev *rtwdev,
2225 struct rtw89_rx_phy_ppdu *phy_ppdu)
2226 {
2227 u16 ie_len;
2228 void *pos, *end;
2229
2230 /* mark invalid reports and bypass them */
2231 if (phy_ppdu->ie < RTW89_CCK_PKT)
2232 return -EINVAL;
2233
2234 pos = phy_ppdu->buf + PHY_STS_HDR_LEN;
2235 if (phy_ppdu->hdr_2_en)
2236 pos += PHY_STS_HDR_LEN;
2237 end = phy_ppdu->buf + phy_ppdu->len;
2238 while (pos < end) {
2239 const struct rtw89_phy_sts_iehdr *iehdr = pos;
2240
2241 ie_len = rtw89_core_get_phy_status_ie_len(rtwdev, iehdr);
2242 rtw89_core_process_phy_status_ie(rtwdev, iehdr, phy_ppdu);
2243 pos += ie_len;
2244 if (pos > end || ie_len == 0) {
2245 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2246 "phy status parse failed\n");
2247 return -EINVAL;
2248 }
2249 }
2250
2251 rtw89_chip_convert_rpl_to_rssi(rtwdev, phy_ppdu);
2252 rtw89_phy_antdiv_parse(rtwdev, phy_ppdu);
2253
2254 return 0;
2255 }
2256
rtw89_core_rx_process_phy_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu)2257 static void rtw89_core_rx_process_phy_sts(struct rtw89_dev *rtwdev,
2258 struct rtw89_rx_phy_ppdu *phy_ppdu)
2259 {
2260 int ret;
2261
2262 ret = rtw89_core_rx_parse_phy_sts(rtwdev, phy_ppdu);
2263 if (ret)
2264 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "parse phy sts failed\n");
2265 else
2266 phy_ppdu->valid = true;
2267
2268 ieee80211_iterate_stations_atomic(rtwdev->hw,
2269 rtw89_core_rx_process_phy_ppdu_iter,
2270 phy_ppdu);
2271 }
2272
rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status)2273 static u8 rtw89_rxdesc_to_nl_he_gi(struct rtw89_dev *rtwdev,
2274 u8 desc_info_gi,
2275 bool rx_status)
2276 {
2277 switch (desc_info_gi) {
2278 case RTW89_GILTF_SGI_4XHE08:
2279 case RTW89_GILTF_2XHE08:
2280 case RTW89_GILTF_1XHE08:
2281 return NL80211_RATE_INFO_HE_GI_0_8;
2282 case RTW89_GILTF_2XHE16:
2283 case RTW89_GILTF_1XHE16:
2284 return NL80211_RATE_INFO_HE_GI_1_6;
2285 case RTW89_GILTF_LGI_4XHE32:
2286 return NL80211_RATE_INFO_HE_GI_3_2;
2287 default:
2288 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi);
2289 if (rx_status)
2290 return NL80211_RATE_INFO_HE_GI_3_2;
2291 return U8_MAX;
2292 }
2293 }
2294
rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status)2295 static u8 rtw89_rxdesc_to_nl_eht_gi(struct rtw89_dev *rtwdev,
2296 u8 desc_info_gi,
2297 bool rx_status)
2298 {
2299 switch (desc_info_gi) {
2300 case RTW89_GILTF_SGI_4XHE08:
2301 case RTW89_GILTF_2XHE08:
2302 case RTW89_GILTF_1XHE08:
2303 return NL80211_RATE_INFO_EHT_GI_0_8;
2304 case RTW89_GILTF_2XHE16:
2305 case RTW89_GILTF_1XHE16:
2306 return NL80211_RATE_INFO_EHT_GI_1_6;
2307 case RTW89_GILTF_LGI_4XHE32:
2308 return NL80211_RATE_INFO_EHT_GI_3_2;
2309 default:
2310 rtw89_warn(rtwdev, "invalid gi_ltf=%d", desc_info_gi);
2311 if (rx_status)
2312 return NL80211_RATE_INFO_EHT_GI_3_2;
2313 return U8_MAX;
2314 }
2315 }
2316
rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev * rtwdev,u8 desc_info_gi,bool rx_status,bool eht)2317 static u8 rtw89_rxdesc_to_nl_he_eht_gi(struct rtw89_dev *rtwdev,
2318 u8 desc_info_gi,
2319 bool rx_status, bool eht)
2320 {
2321 return eht ? rtw89_rxdesc_to_nl_eht_gi(rtwdev, desc_info_gi, rx_status) :
2322 rtw89_rxdesc_to_nl_he_gi(rtwdev, desc_info_gi, rx_status);
2323 }
2324
2325 static
rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status * status,u8 gi_ltf,bool eht)2326 bool rtw89_check_rx_statu_gi_match(struct ieee80211_rx_status *status, u8 gi_ltf,
2327 bool eht)
2328 {
2329 if (eht)
2330 return status->eht.gi == gi_ltf;
2331
2332 return status->he_gi == gi_ltf;
2333 }
2334
rtw89_core_rx_ppdu_match(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * status)2335 static bool rtw89_core_rx_ppdu_match(struct rtw89_dev *rtwdev,
2336 struct rtw89_rx_desc_info *desc_info,
2337 struct ieee80211_rx_status *status)
2338 {
2339 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
2340 u8 data_rate_mode, bw, rate_idx = MASKBYTE0, gi_ltf;
2341 bool eht = false;
2342 u16 data_rate;
2343 bool ret;
2344
2345 data_rate = desc_info->data_rate;
2346 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
2347 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
2348 rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
2349 /* rate_idx is still hardware value here */
2350 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
2351 rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
2352 } else if (data_rate_mode == DATA_RATE_MODE_VHT ||
2353 data_rate_mode == DATA_RATE_MODE_HE ||
2354 data_rate_mode == DATA_RATE_MODE_EHT) {
2355 rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
2356 } else {
2357 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
2358 }
2359
2360 eht = data_rate_mode == DATA_RATE_MODE_EHT;
2361 bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
2362 gi_ltf = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, false, eht);
2363 ret = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band] == desc_info->ppdu_cnt &&
2364 status->rate_idx == rate_idx &&
2365 rtw89_check_rx_statu_gi_match(status, gi_ltf, eht) &&
2366 status->bw == bw;
2367
2368 return ret;
2369 }
2370
2371 struct rtw89_vif_rx_stats_iter_data {
2372 struct rtw89_dev *rtwdev;
2373 struct rtw89_rx_phy_ppdu *phy_ppdu;
2374 struct rtw89_rx_desc_info *desc_info;
2375 struct sk_buff *skb;
2376 const u8 *bssid;
2377 };
2378
rtw89_stats_trigger_frame(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct ieee80211_bss_conf * bss_conf,struct sk_buff * skb)2379 static void rtw89_stats_trigger_frame(struct rtw89_dev *rtwdev,
2380 struct rtw89_vif_link *rtwvif_link,
2381 struct ieee80211_bss_conf *bss_conf,
2382 struct sk_buff *skb)
2383 {
2384 struct ieee80211_trigger *tf = (struct ieee80211_trigger *)skb->data;
2385 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
2386 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
2387 u8 *pos, *end, type, tf_bw;
2388 u16 aid, tf_rua;
2389
2390 if (!ether_addr_equal(bss_conf->bssid, tf->ta) ||
2391 rtwvif_link->wifi_role != RTW89_WIFI_ROLE_STATION ||
2392 rtwvif_link->net_type == RTW89_NET_TYPE_NO_LINK)
2393 return;
2394
2395 type = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_TYPE_MASK);
2396 if (type != IEEE80211_TRIGGER_TYPE_BASIC && type != IEEE80211_TRIGGER_TYPE_MU_BAR)
2397 return;
2398
2399 end = (u8 *)tf + skb->len;
2400 pos = tf->variable;
2401
2402 while (end - pos >= RTW89_TF_BASIC_USER_INFO_SZ) {
2403 aid = RTW89_GET_TF_USER_INFO_AID12(pos);
2404 tf_rua = RTW89_GET_TF_USER_INFO_RUA(pos);
2405 tf_bw = le64_get_bits(tf->common_info, IEEE80211_TRIGGER_ULBW_MASK);
2406 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
2407 "[TF] aid: %d, ul_mcs: %d, rua: %d, bw: %d\n",
2408 aid, RTW89_GET_TF_USER_INFO_UL_MCS(pos),
2409 tf_rua, tf_bw);
2410
2411 if (aid == RTW89_TF_PAD)
2412 break;
2413
2414 if (aid == vif->cfg.aid) {
2415 enum nl80211_he_ru_alloc rua;
2416
2417 rtwvif->stats.rx_tf_acc++;
2418 rtwdev->stats.rx_tf_acc++;
2419
2420 /* The following only required for HE trigger frame, but we
2421 * cannot use UL HE-SIG-A2 reserved subfield to identify it
2422 * since some 11ax APs will fill it with all 0s, which will
2423 * be misunderstood as EHT trigger frame.
2424 */
2425 if (bss_conf->eht_support)
2426 break;
2427
2428 rua = rtw89_he_rua_to_ru_alloc(tf_rua >> 1);
2429
2430 if (tf_bw == IEEE80211_TRIGGER_ULBW_160_80P80MHZ &&
2431 rua <= NL80211_RATE_INFO_HE_RU_ALLOC_106)
2432 rtwvif_link->pwr_diff_en = true;
2433 break;
2434 }
2435
2436 pos += RTW89_TF_BASIC_USER_INFO_SZ;
2437 }
2438 }
2439
rtw89_cancel_6ghz_probe_work(struct wiphy * wiphy,struct wiphy_work * work)2440 static void rtw89_cancel_6ghz_probe_work(struct wiphy *wiphy, struct wiphy_work *work)
2441 {
2442 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
2443 cancel_6ghz_probe_work);
2444 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
2445 struct rtw89_pktofld_info *info;
2446
2447 lockdep_assert_wiphy(wiphy);
2448
2449 if (!rtwdev->scanning)
2450 return;
2451
2452 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
2453 if (!info->cancel || !test_bit(info->id, rtwdev->pkt_offload))
2454 continue;
2455
2456 rtw89_fw_h2c_del_pkt_offload(rtwdev, info->id);
2457
2458 /* Don't delete/free info from pkt_list at this moment. Let it
2459 * be deleted/freed in rtw89_release_pkt_list() after scanning,
2460 * since if during scanning, pkt_list is accessed in bottom half.
2461 */
2462 }
2463 }
2464
rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev * rtwdev,struct sk_buff * skb)2465 static void rtw89_core_cancel_6ghz_probe_tx(struct rtw89_dev *rtwdev,
2466 struct sk_buff *skb)
2467 {
2468 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
2469 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
2470 struct list_head *pkt_list = rtwdev->scan_info.pkt_list;
2471 struct rtw89_pktofld_info *info;
2472 const u8 *ies = mgmt->u.beacon.variable, *ssid_ie;
2473 bool queue_work = false;
2474
2475 if (rx_status->band != NL80211_BAND_6GHZ)
2476 return;
2477
2478 if (unlikely(!(rtwdev->chip->support_bands & BIT(NL80211_BAND_6GHZ)))) {
2479 rtw89_debug(rtwdev, RTW89_DBG_UNEXP, "invalid rx on unsupported 6 GHz\n");
2480 return;
2481 }
2482
2483 ssid_ie = cfg80211_find_ie(WLAN_EID_SSID, ies, skb->len);
2484
2485 list_for_each_entry(info, &pkt_list[NL80211_BAND_6GHZ], list) {
2486 if (ether_addr_equal(info->bssid, mgmt->bssid)) {
2487 info->cancel = true;
2488 queue_work = true;
2489 continue;
2490 }
2491
2492 if (!ssid_ie || ssid_ie[1] != info->ssid_len || info->ssid_len == 0)
2493 continue;
2494
2495 if (memcmp(&ssid_ie[2], info->ssid, info->ssid_len) == 0) {
2496 info->cancel = true;
2497 queue_work = true;
2498 }
2499 }
2500
2501 if (queue_work)
2502 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->cancel_6ghz_probe_work);
2503 }
2504
rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link * rtwvif_link,struct ieee80211_hdr * hdr,size_t len)2505 static void rtw89_vif_sync_bcn_tsf(struct rtw89_vif_link *rtwvif_link,
2506 struct ieee80211_hdr *hdr, size_t len)
2507 {
2508 struct ieee80211_mgmt *mgmt = (typeof(mgmt))hdr;
2509
2510 if (len < offsetof(typeof(*mgmt), u.beacon.variable))
2511 return;
2512
2513 WRITE_ONCE(rtwvif_link->sync_bcn_tsf, le64_to_cpu(mgmt->u.beacon.timestamp));
2514 }
2515
rtw89_bcn_calc_min_tbtt(struct rtw89_dev * rtwdev,u32 tbtt1,u32 tbtt2)2516 static u32 rtw89_bcn_calc_min_tbtt(struct rtw89_dev *rtwdev, u32 tbtt1, u32 tbtt2)
2517 {
2518 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2519 u32 close_bcn_intvl_th = bcn_track->close_bcn_intvl_th;
2520 u32 tbtt_diff_th = bcn_track->tbtt_diff_th;
2521
2522 if (tbtt2 > tbtt1)
2523 swap(tbtt1, tbtt2);
2524
2525 if (tbtt1 - tbtt2 > tbtt_diff_th)
2526 return tbtt1;
2527 else if (tbtt2 > close_bcn_intvl_th)
2528 return tbtt2;
2529 else if (tbtt1 > close_bcn_intvl_th)
2530 return tbtt1;
2531 else
2532 return tbtt2;
2533 }
2534
rtw89_bcn_cfg_tbtt_offset(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2535 static void rtw89_bcn_cfg_tbtt_offset(struct rtw89_dev *rtwdev,
2536 struct rtw89_vif_link *rtwvif_link)
2537 {
2538 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2539 enum rtw89_core_chip_id chip_id = rtwdev->chip->chip_id;
2540 u32 offset = bcn_track->tbtt_offset;
2541
2542 if (chip_id == RTL8852A || rtw89_is_rtl885xb(rtwdev)) {
2543 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
2544 const struct rtw89_port_reg *p = mac->port_base;
2545 u32 bcnspc, val;
2546
2547 bcnspc = rtw89_read32_port_mask(rtwdev, rtwvif_link,
2548 p->bcn_space, B_AX_BCN_SPACE_MASK);
2549 val = bcnspc - (offset / 1024);
2550 val = u32_encode_bits(val, B_AX_TBTT_SHIFT_OFST_MAG) |
2551 B_AX_TBTT_SHIFT_OFST_SIGN;
2552
2553 rtw89_write16_port_mask(rtwdev, rtwvif_link, p->tbtt_shift,
2554 B_AX_TBTT_SHIFT_OFST_MASK, val);
2555
2556 return;
2557 }
2558
2559 rtw89_fw_h2c_tbtt_tuning(rtwdev, rtwvif_link, offset);
2560 }
2561
rtw89_bcn_update_tbtt_offset(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2562 static void rtw89_bcn_update_tbtt_offset(struct rtw89_dev *rtwdev,
2563 struct rtw89_vif_link *rtwvif_link)
2564 {
2565 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2566 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2567 u32 *tbtt_us = bcn_stat->tbtt_us;
2568 u32 offset = tbtt_us[0];
2569 u8 i;
2570
2571 for (i = 1; i < RTW89_BCN_TRACK_STAT_NR; i++)
2572 offset = rtw89_bcn_calc_min_tbtt(rtwdev, tbtt_us[i], offset);
2573
2574 if (bcn_track->tbtt_offset == offset)
2575 return;
2576
2577 bcn_track->tbtt_offset = offset;
2578 rtw89_bcn_cfg_tbtt_offset(rtwdev, rtwvif_link);
2579 }
2580
cmp_u16(const void * a,const void * b)2581 static int cmp_u16(const void *a, const void *b)
2582 {
2583 return *(const u16 *)a - *(const u16 *)b;
2584 }
2585
_rtw89_bcn_calc_drift(u16 tbtt,u16 offset,u16 beacon_int)2586 static u16 _rtw89_bcn_calc_drift(u16 tbtt, u16 offset, u16 beacon_int)
2587 {
2588 if (tbtt < offset)
2589 return beacon_int - offset + tbtt;
2590
2591 return tbtt - offset;
2592 }
2593
rtw89_bcn_calc_drift(struct rtw89_dev * rtwdev)2594 static void rtw89_bcn_calc_drift(struct rtw89_dev *rtwdev)
2595 {
2596 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2597 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2598 u16 offset_tu = bcn_track->tbtt_offset / 1024;
2599 u16 *tbtt_tu = bcn_stat->tbtt_tu;
2600 u16 *drift = bcn_stat->drift;
2601 u8 i;
2602
2603 bcn_stat->tbtt_tu_min = U16_MAX;
2604 bcn_stat->tbtt_tu_max = 0;
2605 for (i = 0; i < RTW89_BCN_TRACK_STAT_NR; i++) {
2606 drift[i] = _rtw89_bcn_calc_drift(tbtt_tu[i], offset_tu,
2607 bcn_track->beacon_int);
2608
2609 bcn_stat->tbtt_tu_min = min(bcn_stat->tbtt_tu_min, tbtt_tu[i]);
2610 bcn_stat->tbtt_tu_max = max(bcn_stat->tbtt_tu_max, tbtt_tu[i]);
2611 }
2612
2613 sort(drift, RTW89_BCN_TRACK_STAT_NR, sizeof(*drift), cmp_u16, NULL);
2614 }
2615
rtw89_bcn_calc_distribution(struct rtw89_dev * rtwdev)2616 static void rtw89_bcn_calc_distribution(struct rtw89_dev *rtwdev)
2617 {
2618 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2619 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist;
2620 u16 lower_bound, upper_bound, outlier_count = 0;
2621 u16 *drift = bcn_stat->drift;
2622 u16 *bins = bcn_dist->bins;
2623 u16 q1, q3, iqr, tmp;
2624 u8 i;
2625
2626 BUILD_BUG_ON(RTW89_BCN_TRACK_STAT_NR % 4 != 0);
2627
2628 memset(bcn_dist, 0, sizeof(*bcn_dist));
2629
2630 bcn_dist->min = drift[0];
2631 bcn_dist->max = drift[RTW89_BCN_TRACK_STAT_NR - 1];
2632
2633 tmp = RTW89_BCN_TRACK_STAT_NR / 4;
2634 q1 = ((drift[tmp] + drift[tmp - 1]) * RTW89_BCN_TRACK_SCALE_FACTOR) / 2;
2635
2636 tmp = (RTW89_BCN_TRACK_STAT_NR * 3) / 4;
2637 q3 = ((drift[tmp] + drift[tmp - 1]) * RTW89_BCN_TRACK_SCALE_FACTOR) / 2;
2638
2639 iqr = q3 - q1;
2640 tmp = (3 * iqr) / 2;
2641
2642 if (bcn_dist->min <= 5)
2643 lower_bound = bcn_dist->min;
2644 else if (q1 > tmp)
2645 lower_bound = (q1 - tmp) / RTW89_BCN_TRACK_SCALE_FACTOR;
2646 else
2647 lower_bound = 0;
2648
2649 upper_bound = (q3 + tmp) / RTW89_BCN_TRACK_SCALE_FACTOR;
2650
2651 for (i = 0; i < RTW89_BCN_TRACK_STAT_NR; i++) {
2652 u16 tbtt = bcn_stat->tbtt_tu[i];
2653 u16 min = bcn_stat->tbtt_tu_min;
2654 u8 bin_idx;
2655
2656 /* histogram */
2657 bin_idx = min((tbtt - min) / RTW89_BCN_TRACK_BIN_WIDTH,
2658 RTW89_BCN_TRACK_MAX_BIN_NUM - 1);
2659 bins[bin_idx]++;
2660
2661 /* boxplot outlier */
2662 if (drift[i] < lower_bound || drift[i] > upper_bound)
2663 outlier_count++;
2664 }
2665
2666 bcn_dist->outlier_count = outlier_count;
2667 bcn_dist->lower_bound = lower_bound;
2668 bcn_dist->upper_bound = upper_bound;
2669 }
2670
rtw89_bcn_get_coverage(struct rtw89_dev * rtwdev,u16 threshold)2671 static u8 rtw89_bcn_get_coverage(struct rtw89_dev *rtwdev, u16 threshold)
2672 {
2673 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2674 int l = 0, r = RTW89_BCN_TRACK_STAT_NR - 1, m;
2675 u16 *drift = bcn_stat->drift;
2676 int index = -1;
2677 u8 count = 0;
2678
2679 while (l <= r) {
2680 m = l + (r - l) / 2;
2681
2682 if (drift[m] <= threshold) {
2683 index = m;
2684 l = m + 1;
2685 } else {
2686 r = m - 1;
2687 }
2688 }
2689
2690 count = (index == -1) ? 0 : (index + 1);
2691
2692 return (count * PERCENT) / RTW89_BCN_TRACK_STAT_NR;
2693 }
2694
rtw89_bcn_get_histogram_bound(struct rtw89_dev * rtwdev,u8 target)2695 static u16 rtw89_bcn_get_histogram_bound(struct rtw89_dev *rtwdev, u8 target)
2696 {
2697 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2698 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist;
2699 u16 tbtt_tu_max = bcn_stat->tbtt_tu_max;
2700 u16 upper, lower = bcn_stat->tbtt_tu_min;
2701 u8 i, count = 0;
2702
2703 for (i = 0; i < RTW89_BCN_TRACK_MAX_BIN_NUM; i++) {
2704 upper = lower + RTW89_BCN_TRACK_BIN_WIDTH - 1;
2705 if (i == RTW89_BCN_TRACK_MAX_BIN_NUM - 1)
2706 upper = max(upper, tbtt_tu_max);
2707
2708 count += bcn_dist->bins[i];
2709 if (count > target)
2710 break;
2711
2712 lower = upper + 1;
2713 }
2714
2715 return upper;
2716 }
2717
rtw89_bcn_get_rx_time(struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)2718 static u16 rtw89_bcn_get_rx_time(struct rtw89_dev *rtwdev,
2719 const struct rtw89_chan *chan)
2720 {
2721 #define RTW89_SYMBOL_TIME_2GHZ 192
2722 #define RTW89_SYMBOL_TIME_5GHZ 20
2723 #define RTW89_SYMBOL_TIME_6GHZ 20
2724 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
2725 u16 bitrate, val;
2726
2727 if (!rtw89_legacy_rate_to_bitrate(rtwdev, pkt_stat->beacon_rate, &bitrate))
2728 return 0;
2729
2730 val = (pkt_stat->beacon_len * 8 * RTW89_BCN_TRACK_SCALE_FACTOR) / bitrate;
2731
2732 switch (chan->band_type) {
2733 default:
2734 case RTW89_BAND_2G:
2735 val += RTW89_SYMBOL_TIME_2GHZ;
2736 break;
2737 case RTW89_BAND_5G:
2738 val += RTW89_SYMBOL_TIME_5GHZ;
2739 break;
2740 case RTW89_BAND_6G:
2741 val += RTW89_SYMBOL_TIME_6GHZ;
2742 break;
2743 }
2744
2745 /* convert to millisecond */
2746 return DIV_ROUND_UP(val, 1000);
2747 }
2748
rtw89_bcn_calc_timeout(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2749 static void rtw89_bcn_calc_timeout(struct rtw89_dev *rtwdev,
2750 struct rtw89_vif_link *rtwvif_link)
2751 {
2752 #define RTW89_BCN_TRACK_EXTEND_TIMEOUT 5
2753 #define RTW89_BCN_TRACK_COVERAGE_TH 0 /* unit: TU */
2754 #define RTW89_BCN_TRACK_STRONG_RSSI 80
2755 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
2756 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
2757 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2758 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2759 struct rtw89_beacon_dist *bcn_dist = &bcn_stat->bcn_dist;
2760 u16 outlier_high_bcn_th = bcn_track->outlier_high_bcn_th;
2761 u16 outlier_low_bcn_th = bcn_track->outlier_low_bcn_th;
2762 u8 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi);
2763 u16 target_bcn_th = bcn_track->target_bcn_th;
2764 u16 low_bcn_th = bcn_track->low_bcn_th;
2765 u16 med_bcn_th = bcn_track->med_bcn_th;
2766 u16 beacon_int = bcn_track->beacon_int;
2767 u16 bcn_timeout;
2768
2769 if (pkt_stat->beacon_nr < low_bcn_th) {
2770 bcn_timeout = (RTW89_BCN_TRACK_TARGET_BCN * beacon_int) / PERCENT;
2771 goto out;
2772 }
2773
2774 if (bcn_dist->outlier_count >= outlier_high_bcn_th) {
2775 bcn_timeout = bcn_dist->max;
2776 goto out;
2777 }
2778
2779 if (pkt_stat->beacon_nr < med_bcn_th) {
2780 if (bcn_dist->outlier_count > outlier_low_bcn_th)
2781 bcn_timeout = (bcn_dist->max + bcn_dist->upper_bound) / 2;
2782 else
2783 bcn_timeout = bcn_dist->upper_bound +
2784 RTW89_BCN_TRACK_EXTEND_TIMEOUT;
2785
2786 goto out;
2787 }
2788
2789 if (rssi >= RTW89_BCN_TRACK_STRONG_RSSI) {
2790 if (rtw89_bcn_get_coverage(rtwdev, RTW89_BCN_TRACK_COVERAGE_TH) >= 90) {
2791 /* ideal case */
2792 bcn_timeout = 0;
2793 } else {
2794 u16 offset_tu = bcn_track->tbtt_offset / 1024;
2795 u16 upper_bound;
2796
2797 upper_bound =
2798 rtw89_bcn_get_histogram_bound(rtwdev, target_bcn_th);
2799 bcn_timeout =
2800 _rtw89_bcn_calc_drift(upper_bound, offset_tu, beacon_int);
2801 }
2802
2803 goto out;
2804 }
2805
2806 bcn_timeout = bcn_stat->drift[target_bcn_th];
2807
2808 out:
2809 bcn_track->bcn_timeout = bcn_timeout + rtw89_bcn_get_rx_time(rtwdev, chan);
2810 }
2811
rtw89_bcn_update_timeout(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2812 static void rtw89_bcn_update_timeout(struct rtw89_dev *rtwdev,
2813 struct rtw89_vif_link *rtwvif_link)
2814 {
2815 rtw89_bcn_calc_drift(rtwdev);
2816 rtw89_bcn_calc_distribution(rtwdev);
2817 rtw89_bcn_calc_timeout(rtwdev, rtwvif_link);
2818 }
2819
rtw89_core_bcn_track(struct rtw89_dev * rtwdev)2820 static void rtw89_core_bcn_track(struct rtw89_dev *rtwdev)
2821 {
2822 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2823 struct rtw89_vif_link *rtwvif_link;
2824 struct rtw89_vif *rtwvif;
2825 unsigned int link_id;
2826
2827 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw))
2828 return;
2829
2830 if (!rtwdev->lps_enabled)
2831 return;
2832
2833 if (!bcn_track->is_data_ready)
2834 return;
2835
2836 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
2837 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id) {
2838 if (!(rtwvif_link->wifi_role == RTW89_WIFI_ROLE_STATION ||
2839 rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT))
2840 continue;
2841
2842 rtw89_bcn_update_tbtt_offset(rtwdev, rtwvif_link);
2843 rtw89_bcn_update_timeout(rtwdev, rtwvif_link);
2844 }
2845 }
2846 }
2847
rtw89_core_bcn_track_can_lps(struct rtw89_dev * rtwdev)2848 static bool rtw89_core_bcn_track_can_lps(struct rtw89_dev *rtwdev)
2849 {
2850 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2851
2852 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw))
2853 return true;
2854
2855 return bcn_track->is_data_ready;
2856 }
2857
rtw89_core_bcn_track_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)2858 static void rtw89_core_bcn_track_assoc(struct rtw89_dev *rtwdev,
2859 struct rtw89_vif_link *rtwvif_link)
2860 {
2861 #define RTW89_BCN_TRACK_MED_BCN 70
2862 #define RTW89_BCN_TRACK_LOW_BCN 30
2863 #define RTW89_BCN_TRACK_OUTLIER_HIGH_BCN 30
2864 #define RTW89_BCN_TRACK_OUTLIER_LOW_BCN 20
2865 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2866 u32 period = jiffies_to_msecs(RTW89_TRACK_WORK_PERIOD);
2867 struct ieee80211_bss_conf *bss_conf;
2868 u32 beacons_in_period;
2869 u32 bcn_intvl_us;
2870 u16 beacon_int;
2871 u8 dtim;
2872
2873 rcu_read_lock();
2874 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
2875 beacon_int = bss_conf->beacon_int ?: 100;
2876 dtim = bss_conf->dtim_period;
2877 rcu_read_unlock();
2878
2879 beacons_in_period = period / beacon_int / dtim;
2880 bcn_intvl_us = ieee80211_tu_to_usec(beacon_int);
2881
2882 bcn_track->low_bcn_th =
2883 (beacons_in_period * RTW89_BCN_TRACK_LOW_BCN) / PERCENT;
2884 bcn_track->med_bcn_th =
2885 (beacons_in_period * RTW89_BCN_TRACK_MED_BCN) / PERCENT;
2886 bcn_track->outlier_low_bcn_th =
2887 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_OUTLIER_LOW_BCN) / PERCENT;
2888 bcn_track->outlier_high_bcn_th =
2889 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_OUTLIER_HIGH_BCN) / PERCENT;
2890 bcn_track->target_bcn_th =
2891 (RTW89_BCN_TRACK_STAT_NR * RTW89_BCN_TRACK_TARGET_BCN) / PERCENT;
2892
2893 bcn_track->close_bcn_intvl_th = ieee80211_tu_to_usec(beacon_int - 3);
2894 bcn_track->tbtt_diff_th = (bcn_intvl_us * 85) / PERCENT;
2895 bcn_track->beacon_int = beacon_int;
2896 bcn_track->dtim = dtim;
2897 }
2898
rtw89_core_bcn_track_reset(struct rtw89_dev * rtwdev)2899 static void rtw89_core_bcn_track_reset(struct rtw89_dev *rtwdev)
2900 {
2901 memset(&rtwdev->phystat.bcn_stat, 0, sizeof(rtwdev->phystat.bcn_stat));
2902 memset(&rtwdev->bcn_track, 0, sizeof(rtwdev->bcn_track));
2903 }
2904
rtw89_vif_rx_bcn_stat(struct rtw89_dev * rtwdev,struct sk_buff * skb)2905 static void rtw89_vif_rx_bcn_stat(struct rtw89_dev *rtwdev, struct sk_buff *skb)
2906 {
2907 #define RTW89_APPEND_TSF_2GHZ 384
2908 #define RTW89_APPEND_TSF_5GHZ 52
2909 #define RTW89_APPEND_TSF_6GHZ 52
2910 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
2911 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
2912 struct rtw89_beacon_stat *bcn_stat = &rtwdev->phystat.bcn_stat;
2913 struct rtw89_beacon_track_info *bcn_track = &rtwdev->bcn_track;
2914 u32 bcn_intvl_us = ieee80211_tu_to_usec(bcn_track->beacon_int);
2915 u64 tsf = le64_to_cpu(mgmt->u.beacon.timestamp);
2916 u8 wp, num = bcn_stat->num;
2917 u16 append;
2918
2919 if (!RTW89_CHK_FW_FEATURE(BEACON_TRACKING, &rtwdev->fw))
2920 return;
2921
2922 /* Skip if not yet associated */
2923 if (!bcn_intvl_us)
2924 return;
2925
2926 switch (rx_status->band) {
2927 default:
2928 case NL80211_BAND_2GHZ:
2929 append = RTW89_APPEND_TSF_2GHZ;
2930 break;
2931 case NL80211_BAND_5GHZ:
2932 append = RTW89_APPEND_TSF_5GHZ;
2933 break;
2934 case NL80211_BAND_6GHZ:
2935 append = RTW89_APPEND_TSF_6GHZ;
2936 break;
2937 }
2938
2939 wp = bcn_stat->wp;
2940 div_u64_rem(tsf - append, bcn_intvl_us, &bcn_stat->tbtt_us[wp]);
2941 bcn_stat->tbtt_tu[wp] = bcn_stat->tbtt_us[wp] / 1024;
2942 bcn_stat->wp = (wp + 1) % RTW89_BCN_TRACK_STAT_NR;
2943 bcn_stat->num = umin(num + 1, RTW89_BCN_TRACK_STAT_NR);
2944 bcn_track->is_data_ready = bcn_stat->num == RTW89_BCN_TRACK_STAT_NR;
2945 }
2946
rtw89_vif_rx_stats_iter(void * data,u8 * mac,struct ieee80211_vif * vif)2947 static void rtw89_vif_rx_stats_iter(void *data, u8 *mac,
2948 struct ieee80211_vif *vif)
2949 {
2950 struct rtw89_vif_rx_stats_iter_data *iter_data = data;
2951 struct rtw89_dev *rtwdev = iter_data->rtwdev;
2952 struct rtw89_vif *rtwvif = vif_to_rtwvif(vif);
2953 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.cur_pkt_stat;
2954 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
2955 struct sk_buff *skb = iter_data->skb;
2956 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
2957 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
2958 struct rtw89_rx_phy_ppdu *phy_ppdu = iter_data->phy_ppdu;
2959 bool is_mld = ieee80211_vif_is_mld(vif);
2960 struct ieee80211_bss_conf *bss_conf;
2961 struct rtw89_vif_link *rtwvif_link;
2962 const u8 *bssid = iter_data->bssid;
2963 const u8 *target_bssid;
2964
2965 if (rtwdev->scanning &&
2966 (ieee80211_is_beacon(hdr->frame_control) ||
2967 ieee80211_is_probe_resp(hdr->frame_control)))
2968 rtw89_core_cancel_6ghz_probe_tx(rtwdev, skb);
2969
2970 rcu_read_lock();
2971
2972 rtwvif_link = rtw89_vif_get_link_inst(rtwvif, desc_info->bb_sel);
2973 if (unlikely(!rtwvif_link))
2974 goto out;
2975
2976 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
2977 if (!bss_conf->bssid)
2978 goto out;
2979
2980 if (ieee80211_is_trigger(hdr->frame_control)) {
2981 rtw89_stats_trigger_frame(rtwdev, rtwvif_link, bss_conf, skb);
2982 goto out;
2983 }
2984
2985 target_bssid = ieee80211_is_beacon(hdr->frame_control) &&
2986 bss_conf->nontransmitted ?
2987 bss_conf->transmitter_bssid : bss_conf->bssid;
2988 if (!ether_addr_equal(target_bssid, bssid))
2989 goto out;
2990
2991 if (is_mld) {
2992 rx_status->link_valid = true;
2993 rx_status->link_id = rtwvif_link->link_id;
2994 }
2995
2996 if (ieee80211_is_beacon(hdr->frame_control)) {
2997 if (vif->type == NL80211_IFTYPE_STATION &&
2998 !test_bit(RTW89_FLAG_WOWLAN, rtwdev->flags)) {
2999 rtw89_vif_sync_bcn_tsf(rtwvif_link, hdr, skb->len);
3000 rtw89_fw_h2c_rssi_offload(rtwdev, phy_ppdu);
3001 }
3002
3003 if (phy_ppdu) {
3004 ewma_rssi_add(&rtwdev->phystat.bcn_rssi, phy_ppdu->rssi_avg);
3005 if (!test_bit(RTW89_FLAG_LOW_POWER_MODE, rtwdev->flags))
3006 rtwvif_link->bcn_bw_idx = phy_ppdu->bw_idx;
3007 }
3008
3009 pkt_stat->beacon_nr++;
3010 pkt_stat->beacon_rate = desc_info->data_rate;
3011 pkt_stat->beacon_len = skb->len;
3012
3013 rtw89_vif_rx_bcn_stat(rtwdev, skb);
3014 }
3015
3016 if (!ether_addr_equal(bss_conf->addr, hdr->addr1))
3017 goto out;
3018
3019 if (desc_info->data_rate < RTW89_HW_RATE_NR)
3020 pkt_stat->rx_rate_cnt[desc_info->data_rate]++;
3021
3022 rtw89_traffic_stats_accu(rtwdev, rtwvif, skb, false, false);
3023
3024 out:
3025 rcu_read_unlock();
3026 }
3027
rtw89_core_rx_stats(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)3028 static void rtw89_core_rx_stats(struct rtw89_dev *rtwdev,
3029 struct rtw89_rx_phy_ppdu *phy_ppdu,
3030 struct rtw89_rx_desc_info *desc_info,
3031 struct sk_buff *skb)
3032 {
3033 struct rtw89_vif_rx_stats_iter_data iter_data;
3034
3035 rtw89_traffic_stats_accu(rtwdev, NULL, skb, true, false);
3036
3037 iter_data.rtwdev = rtwdev;
3038 iter_data.phy_ppdu = phy_ppdu;
3039 iter_data.desc_info = desc_info;
3040 iter_data.skb = skb;
3041 iter_data.bssid = get_hdr_bssid((struct ieee80211_hdr *)skb->data);
3042 rtw89_iterate_vifs_bh(rtwdev, rtw89_vif_rx_stats_iter, &iter_data);
3043 }
3044
rtw89_correct_cck_chan(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * status)3045 static void rtw89_correct_cck_chan(struct rtw89_dev *rtwdev,
3046 struct ieee80211_rx_status *status)
3047 {
3048 const struct rtw89_chan_rcd *rcd =
3049 rtw89_chan_rcd_get(rtwdev, RTW89_CHANCTX_0);
3050 u16 chan = rcd->prev_primary_channel;
3051 u8 band = rtw89_hw_to_nl80211_band(rcd->prev_band_type);
3052
3053 if (status->band != NL80211_BAND_2GHZ &&
3054 status->encoding == RX_ENC_LEGACY &&
3055 status->rate_idx < RTW89_HW_RATE_OFDM6) {
3056 status->freq = ieee80211_channel_to_frequency(chan, band);
3057 status->band = band;
3058 }
3059 }
3060
rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status * rx_status)3061 static void rtw89_core_hw_to_sband_rate(struct ieee80211_rx_status *rx_status)
3062 {
3063 if (rx_status->band == NL80211_BAND_2GHZ ||
3064 rx_status->encoding != RX_ENC_LEGACY)
3065 return;
3066
3067 /* Some control frames' freq(ACKs in this case) are reported wrong due
3068 * to FW notify timing, set to lowest rate to prevent overflow.
3069 */
3070 if (rx_status->rate_idx < RTW89_HW_RATE_OFDM6) {
3071 rx_status->rate_idx = 0;
3072 return;
3073 }
3074
3075 /* No 4 CCK rates for non-2G */
3076 rx_status->rate_idx -= 4;
3077 }
3078
3079 static
rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev * rtwdev,struct ieee80211_rx_status * rx_status,struct rtw89_rx_phy_ppdu * phy_ppdu)3080 void rtw89_core_update_rx_status_by_ppdu(struct rtw89_dev *rtwdev,
3081 struct ieee80211_rx_status *rx_status,
3082 struct rtw89_rx_phy_ppdu *phy_ppdu)
3083 {
3084 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
3085 return;
3086
3087 if (!phy_ppdu)
3088 return;
3089
3090 if (phy_ppdu->ldpc)
3091 rx_status->enc_flags |= RX_ENC_FLAG_LDPC;
3092 if (phy_ppdu->stbc)
3093 rx_status->enc_flags |= u8_encode_bits(1, RX_ENC_FLAG_STBC_MASK);
3094 }
3095
3096 static const u8 rx_status_bw_to_radiotap_eht_usig[] = {
3097 [RATE_INFO_BW_20] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_20MHZ,
3098 [RATE_INFO_BW_5] = U8_MAX,
3099 [RATE_INFO_BW_10] = U8_MAX,
3100 [RATE_INFO_BW_40] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_40MHZ,
3101 [RATE_INFO_BW_80] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_80MHZ,
3102 [RATE_INFO_BW_160] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_160MHZ,
3103 [RATE_INFO_BW_HE_RU] = U8_MAX,
3104 [RATE_INFO_BW_320] = IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_320MHZ_1,
3105 [RATE_INFO_BW_EHT_RU] = U8_MAX,
3106 };
3107
rtw89_core_update_radiotap_eht(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)3108 static void rtw89_core_update_radiotap_eht(struct rtw89_dev *rtwdev,
3109 struct sk_buff *skb,
3110 struct ieee80211_rx_status *rx_status)
3111 {
3112 struct ieee80211_radiotap_eht_usig *usig;
3113 struct ieee80211_radiotap_eht *eht;
3114 struct ieee80211_radiotap_tlv *tlv;
3115 int eht_len = struct_size(eht, user_info, 1);
3116 int usig_len = sizeof(*usig);
3117 int len;
3118 u8 bw;
3119
3120 len = sizeof(*tlv) + ALIGN(eht_len, 4) +
3121 sizeof(*tlv) + ALIGN(usig_len, 4);
3122
3123 rx_status->flag |= RX_FLAG_RADIOTAP_TLV_AT_END;
3124 skb_reset_mac_header(skb);
3125
3126 /* EHT */
3127 tlv = skb_push(skb, len);
3128 memset(tlv, 0, len);
3129 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT);
3130 tlv->len = cpu_to_le16(eht_len);
3131
3132 eht = (struct ieee80211_radiotap_eht *)tlv->data;
3133 eht->known = cpu_to_le32(IEEE80211_RADIOTAP_EHT_KNOWN_GI);
3134 eht->data[0] =
3135 le32_encode_bits(rx_status->eht.gi, IEEE80211_RADIOTAP_EHT_DATA0_GI);
3136
3137 eht->user_info[0] =
3138 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_MCS_KNOWN |
3139 IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_KNOWN_O |
3140 IEEE80211_RADIOTAP_EHT_USER_INFO_CODING_KNOWN);
3141 eht->user_info[0] |=
3142 le32_encode_bits(rx_status->rate_idx, IEEE80211_RADIOTAP_EHT_USER_INFO_MCS) |
3143 le32_encode_bits(rx_status->nss, IEEE80211_RADIOTAP_EHT_USER_INFO_NSS_O);
3144 if (rx_status->enc_flags & RX_ENC_FLAG_LDPC)
3145 eht->user_info[0] |=
3146 cpu_to_le32(IEEE80211_RADIOTAP_EHT_USER_INFO_CODING);
3147
3148 /* U-SIG */
3149 tlv = (void *)tlv + sizeof(*tlv) + ALIGN(eht_len, 4);
3150 tlv->type = cpu_to_le16(IEEE80211_RADIOTAP_EHT_USIG);
3151 tlv->len = cpu_to_le16(usig_len);
3152
3153 if (rx_status->bw >= ARRAY_SIZE(rx_status_bw_to_radiotap_eht_usig))
3154 return;
3155
3156 bw = rx_status_bw_to_radiotap_eht_usig[rx_status->bw];
3157 if (bw == U8_MAX)
3158 return;
3159
3160 usig = (struct ieee80211_radiotap_eht_usig *)tlv->data;
3161 usig->common =
3162 le32_encode_bits(1, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW_KNOWN) |
3163 le32_encode_bits(bw, IEEE80211_RADIOTAP_EHT_USIG_COMMON_BW);
3164 }
3165
rtw89_core_update_radiotap(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)3166 static void rtw89_core_update_radiotap(struct rtw89_dev *rtwdev,
3167 struct sk_buff *skb,
3168 struct ieee80211_rx_status *rx_status)
3169 {
3170 static const struct ieee80211_radiotap_he known_he = {
3171 .data1 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA1_DATA_MCS_KNOWN |
3172 IEEE80211_RADIOTAP_HE_DATA1_CODING_KNOWN |
3173 IEEE80211_RADIOTAP_HE_DATA1_STBC_KNOWN |
3174 IEEE80211_RADIOTAP_HE_DATA1_BW_RU_ALLOC_KNOWN),
3175 .data2 = cpu_to_le16(IEEE80211_RADIOTAP_HE_DATA2_GI_KNOWN),
3176 };
3177 struct ieee80211_radiotap_he *he;
3178
3179 if (!(rtwdev->hw->conf.flags & IEEE80211_CONF_MONITOR))
3180 return;
3181
3182 if (rx_status->encoding == RX_ENC_HE) {
3183 rx_status->flag |= RX_FLAG_RADIOTAP_HE;
3184 he = skb_push(skb, sizeof(*he));
3185 *he = known_he;
3186 } else if (rx_status->encoding == RX_ENC_EHT) {
3187 rtw89_core_update_radiotap_eht(rtwdev, skb, rx_status);
3188 }
3189 }
3190
rtw89_core_validate_rx_signal(struct ieee80211_rx_status * rx_status)3191 static void rtw89_core_validate_rx_signal(struct ieee80211_rx_status *rx_status)
3192 {
3193 if (!rx_status->signal)
3194 rx_status->flag |= RX_FLAG_NO_SIGNAL_VAL;
3195 }
3196
rtw89_core_update_rx_freq_from_ie(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct ieee80211_rx_status * rx_status)3197 static void rtw89_core_update_rx_freq_from_ie(struct rtw89_dev *rtwdev,
3198 struct sk_buff *skb,
3199 struct ieee80211_rx_status *rx_status)
3200 {
3201 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)skb->data;
3202 size_t hdr_len, ielen;
3203 u8 *variable;
3204 int chan;
3205
3206 if (!rtwdev->chip->rx_freq_frome_ie)
3207 return;
3208
3209 if (!rtwdev->scanning)
3210 return;
3211
3212 if (ieee80211_is_beacon(mgmt->frame_control)) {
3213 variable = mgmt->u.beacon.variable;
3214 hdr_len = offsetof(struct ieee80211_mgmt,
3215 u.beacon.variable);
3216 } else if (ieee80211_is_probe_resp(mgmt->frame_control)) {
3217 variable = mgmt->u.probe_resp.variable;
3218 hdr_len = offsetof(struct ieee80211_mgmt,
3219 u.probe_resp.variable);
3220 } else {
3221 return;
3222 }
3223
3224 if (skb->len > hdr_len)
3225 ielen = skb->len - hdr_len;
3226 else
3227 return;
3228
3229 /* The parsing code for both 2GHz and 5GHz bands is the same in this
3230 * function.
3231 */
3232 chan = cfg80211_get_ies_channel_number(variable, ielen, NL80211_BAND_2GHZ);
3233 if (chan == -1)
3234 return;
3235
3236 rx_status->band = chan > 14 ? RTW89_BAND_5G : RTW89_BAND_2G;
3237 rx_status->freq = ieee80211_channel_to_frequency(chan, rx_status->band);
3238 }
3239
rtw89_core_correct_mcc_chan(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status,struct rtw89_rx_phy_ppdu * phy_ppdu)3240 static void rtw89_core_correct_mcc_chan(struct rtw89_dev *rtwdev,
3241 struct rtw89_rx_desc_info *desc_info,
3242 struct ieee80211_rx_status *rx_status,
3243 struct rtw89_rx_phy_ppdu *phy_ppdu)
3244 {
3245 enum rtw89_chip_gen chip_gen = rtwdev->chip->chip_gen;
3246 struct rtw89_vif_link *rtwvif_link;
3247 struct rtw89_sta_link *rtwsta_link;
3248 const struct rtw89_chan *chan;
3249 u8 mac_id = desc_info->mac_id;
3250 enum rtw89_entity_mode mode;
3251 enum nl80211_band band;
3252
3253 mode = rtw89_get_entity_mode(rtwdev);
3254 if (likely(mode != RTW89_ENTITY_MODE_MCC))
3255 return;
3256
3257 if (chip_gen == RTW89_CHIP_BE && phy_ppdu)
3258 mac_id = phy_ppdu->mac_id;
3259
3260 rcu_read_lock();
3261
3262 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, mac_id);
3263 if (!rtwsta_link)
3264 goto out;
3265
3266 rtwvif_link = rtwsta_link->rtwvif_link;
3267 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
3268 band = rtw89_hw_to_nl80211_band(chan->band_type);
3269 rx_status->freq = ieee80211_channel_to_frequency(chan->primary_channel, band);
3270
3271 out:
3272 rcu_read_unlock();
3273 }
3274
rtw89_core_rx_to_mac80211(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb_ppdu,struct ieee80211_rx_status * rx_status)3275 static void rtw89_core_rx_to_mac80211(struct rtw89_dev *rtwdev,
3276 struct rtw89_rx_phy_ppdu *phy_ppdu,
3277 struct rtw89_rx_desc_info *desc_info,
3278 struct sk_buff *skb_ppdu,
3279 struct ieee80211_rx_status *rx_status)
3280 {
3281 struct napi_struct *napi = &rtwdev->napi;
3282
3283 /* In low power mode, napi isn't scheduled. Receive it to netif. */
3284 if (unlikely(!napi_is_scheduled(napi)))
3285 napi = NULL;
3286
3287 rtw89_core_hw_to_sband_rate(rx_status);
3288 rtw89_core_rx_stats(rtwdev, phy_ppdu, desc_info, skb_ppdu);
3289 rtw89_core_update_rx_status_by_ppdu(rtwdev, rx_status, phy_ppdu);
3290 rtw89_core_update_radiotap(rtwdev, skb_ppdu, rx_status);
3291 rtw89_core_validate_rx_signal(rx_status);
3292 rtw89_core_update_rx_freq_from_ie(rtwdev, skb_ppdu, rx_status);
3293 rtw89_core_correct_mcc_chan(rtwdev, desc_info, rx_status, phy_ppdu);
3294
3295 /* In low power mode, it does RX in thread context. */
3296 local_bh_disable();
3297 ieee80211_rx_napi(rtwdev->hw, NULL, skb_ppdu, napi);
3298 local_bh_enable();
3299 rtwdev->napi_budget_countdown--;
3300 }
3301
rtw89_core_rx_pending_skb(struct rtw89_dev * rtwdev,struct rtw89_rx_phy_ppdu * phy_ppdu,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)3302 static void rtw89_core_rx_pending_skb(struct rtw89_dev *rtwdev,
3303 struct rtw89_rx_phy_ppdu *phy_ppdu,
3304 struct rtw89_rx_desc_info *desc_info,
3305 struct sk_buff *skb)
3306 {
3307 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
3308 int curr = rtwdev->ppdu_sts.curr_rx_ppdu_cnt[band];
3309 struct sk_buff *skb_ppdu = NULL, *tmp;
3310 struct ieee80211_rx_status *rx_status;
3311
3312 if (curr > RTW89_MAX_PPDU_CNT)
3313 return;
3314
3315 skb_queue_walk_safe(&rtwdev->ppdu_sts.rx_queue[band], skb_ppdu, tmp) {
3316 skb_unlink(skb_ppdu, &rtwdev->ppdu_sts.rx_queue[band]);
3317 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
3318 if (rtw89_core_rx_ppdu_match(rtwdev, desc_info, rx_status))
3319 rtw89_chip_query_ppdu(rtwdev, phy_ppdu, rx_status);
3320 rtw89_correct_cck_chan(rtwdev, rx_status);
3321 rtw89_core_rx_to_mac80211(rtwdev, phy_ppdu, desc_info, skb_ppdu, rx_status);
3322 }
3323 }
3324
rtw89_core_rx_process_ppdu_sts(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)3325 static void rtw89_core_rx_process_ppdu_sts(struct rtw89_dev *rtwdev,
3326 struct rtw89_rx_desc_info *desc_info,
3327 struct sk_buff *skb)
3328 {
3329 struct rtw89_rx_phy_ppdu phy_ppdu = {.buf = skb->data, .valid = false,
3330 .len = skb->len,
3331 .to_self = desc_info->addr1_match,
3332 .rate = desc_info->data_rate,
3333 .mac_id = desc_info->mac_id,
3334 .phy_idx = desc_info->bb_sel};
3335 int ret;
3336
3337 if (desc_info->mac_info_valid) {
3338 ret = rtw89_core_rx_process_mac_ppdu(rtwdev, skb, &phy_ppdu);
3339 if (ret)
3340 goto out;
3341 }
3342
3343 ret = rtw89_core_rx_process_phy_ppdu(rtwdev, &phy_ppdu);
3344 if (ret)
3345 goto out;
3346
3347 rtw89_core_rx_process_phy_sts(rtwdev, &phy_ppdu);
3348
3349 out:
3350 rtw89_core_rx_pending_skb(rtwdev, &phy_ppdu, desc_info, skb);
3351 dev_kfree_skb_any(skb);
3352 }
3353
rtw89_core_rx_process_report(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)3354 static void rtw89_core_rx_process_report(struct rtw89_dev *rtwdev,
3355 struct rtw89_rx_desc_info *desc_info,
3356 struct sk_buff *skb)
3357 {
3358 switch (desc_info->pkt_type) {
3359 case RTW89_CORE_RX_TYPE_C2H:
3360 rtw89_fw_c2h_irqsafe(rtwdev, skb);
3361 break;
3362 case RTW89_CORE_RX_TYPE_PPDU_STAT:
3363 rtw89_core_rx_process_ppdu_sts(rtwdev, desc_info, skb);
3364 break;
3365 default:
3366 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "unhandled pkt_type=%d\n",
3367 desc_info->pkt_type);
3368 dev_kfree_skb_any(skb);
3369 break;
3370 }
3371 }
3372
rtw89_core_query_rxdesc(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)3373 void rtw89_core_query_rxdesc(struct rtw89_dev *rtwdev,
3374 struct rtw89_rx_desc_info *desc_info,
3375 u8 *data, u32 data_offset)
3376 {
3377 const struct rtw89_chip_info *chip = rtwdev->chip;
3378 struct rtw89_rxdesc_short *rxd_s;
3379 struct rtw89_rxdesc_long *rxd_l;
3380 u8 shift_len, drv_info_len;
3381
3382 rxd_s = (struct rtw89_rxdesc_short *)(data + data_offset);
3383 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_LEN_MASK);
3384 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, AX_RXD_DRV_INFO_SIZE_MASK);
3385 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, AX_RXD_LONG_RXD);
3386 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, AX_RXD_RPKT_TYPE_MASK);
3387 desc_info->mac_info_valid = le32_get_bits(rxd_s->dword0, AX_RXD_MAC_INFO_VLD);
3388 if (chip->chip_id == RTL8852C)
3389 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_v1_MASK);
3390 else
3391 desc_info->bw = le32_get_bits(rxd_s->dword1, AX_RXD_BW_MASK);
3392 desc_info->data_rate = le32_get_bits(rxd_s->dword1, AX_RXD_RX_DATARATE_MASK);
3393 desc_info->gi_ltf = le32_get_bits(rxd_s->dword1, AX_RXD_RX_GI_LTF_MASK);
3394 desc_info->user_id = le32_get_bits(rxd_s->dword1, AX_RXD_USER_ID_MASK);
3395 desc_info->sr_en = le32_get_bits(rxd_s->dword1, AX_RXD_SR_EN);
3396 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_CNT_MASK);
3397 desc_info->ppdu_type = le32_get_bits(rxd_s->dword1, AX_RXD_PPDU_TYPE_MASK);
3398 desc_info->free_run_cnt = le32_get_bits(rxd_s->dword2, AX_RXD_FREERUN_CNT_MASK);
3399 desc_info->icv_err = le32_get_bits(rxd_s->dword3, AX_RXD_ICV_ERR);
3400 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, AX_RXD_CRC32_ERR);
3401 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_HW_DEC);
3402 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, AX_RXD_SW_DEC);
3403 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, AX_RXD_A1_MATCH);
3404
3405 shift_len = desc_info->shift << 1; /* 2-byte unit */
3406 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
3407 desc_info->offset = data_offset + shift_len + drv_info_len;
3408 if (desc_info->long_rxdesc)
3409 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long);
3410 else
3411 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short);
3412 desc_info->ready = true;
3413
3414 if (!desc_info->long_rxdesc)
3415 return;
3416
3417 rxd_l = (struct rtw89_rxdesc_long *)(data + data_offset);
3418 desc_info->frame_type = le32_get_bits(rxd_l->dword4, AX_RXD_TYPE_MASK);
3419 desc_info->addr_cam_valid = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_VLD);
3420 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_ADDR_CAM_MASK);
3421 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword5, AX_RXD_SEC_CAM_IDX_MASK);
3422 desc_info->mac_id = le32_get_bits(rxd_l->dword5, AX_RXD_MAC_ID_MASK);
3423 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword5, AX_RXD_RX_PL_ID_MASK);
3424 }
3425 EXPORT_SYMBOL(rtw89_core_query_rxdesc);
3426
rtw89_core_query_rxdesc_v2(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)3427 void rtw89_core_query_rxdesc_v2(struct rtw89_dev *rtwdev,
3428 struct rtw89_rx_desc_info *desc_info,
3429 u8 *data, u32 data_offset)
3430 {
3431 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt;
3432 struct rtw89_rxdesc_short_v2 *rxd_s;
3433 struct rtw89_rxdesc_long_v2 *rxd_l;
3434 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len;
3435
3436 rxd_s = (struct rtw89_rxdesc_short_v2 *)(data + data_offset);
3437
3438 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK);
3439 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK);
3440 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK);
3441 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK);
3442 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK);
3443 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD);
3444 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK);
3445 desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL);
3446 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT)
3447 desc_info->mac_info_valid = true;
3448
3449 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK);
3450 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_MASK);
3451 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
3452
3453 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
3454 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
3455 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
3456 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC);
3457 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH);
3458
3459 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK);
3460 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK);
3461 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK);
3462 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK);
3463 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK);
3464
3465 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5);
3466
3467 shift_len = desc_info->shift << 1; /* 2-byte unit */
3468 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
3469 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */
3470 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */
3471 desc_info->offset = data_offset + shift_len + drv_info_len +
3472 phy_rtp_len + hdr_cnv_len;
3473
3474 if (desc_info->long_rxdesc)
3475 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v2);
3476 else
3477 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v2);
3478 desc_info->ready = true;
3479
3480 if (phy_rtp_len == sizeof(*rxd_rpt)) {
3481 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset +
3482 desc_info->rxd_len);
3483 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI);
3484 }
3485
3486 if (!desc_info->long_rxdesc)
3487 return;
3488
3489 rxd_l = (struct rtw89_rxdesc_long_v2 *)(data + data_offset);
3490
3491 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN);
3492 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK);
3493 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_MASK);
3494 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_MASK);
3495
3496 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK);
3497 }
3498 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v2);
3499
rtw89_core_query_rxdesc_v3(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,u8 * data,u32 data_offset)3500 void rtw89_core_query_rxdesc_v3(struct rtw89_dev *rtwdev,
3501 struct rtw89_rx_desc_info *desc_info,
3502 u8 *data, u32 data_offset)
3503 {
3504 struct rtw89_rxdesc_phy_rpt_v2 *rxd_rpt;
3505 struct rtw89_rxdesc_short_v3 *rxd_s;
3506 struct rtw89_rxdesc_long_v3 *rxd_l;
3507 u16 shift_len, drv_info_len, phy_rtp_len, hdr_cnv_len;
3508
3509 rxd_s = (struct rtw89_rxdesc_short_v3 *)(data + data_offset);
3510
3511 desc_info->pkt_size = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_LEN_MASK);
3512 desc_info->drv_info_size = le32_get_bits(rxd_s->dword0, BE_RXD_DRV_INFO_SZ_MASK);
3513 desc_info->phy_rpt_size = le32_get_bits(rxd_s->dword0, BE_RXD_PHY_RPT_SZ_MASK);
3514 desc_info->hdr_cnv_size = le32_get_bits(rxd_s->dword0, BE_RXD_HDR_CNV_SZ_MASK);
3515 desc_info->shift = le32_get_bits(rxd_s->dword0, BE_RXD_SHIFT_MASK);
3516 desc_info->long_rxdesc = le32_get_bits(rxd_s->dword0, BE_RXD_LONG_RXD);
3517 desc_info->pkt_type = le32_get_bits(rxd_s->dword0, BE_RXD_RPKT_TYPE_MASK);
3518 desc_info->bb_sel = le32_get_bits(rxd_s->dword0, BE_RXD_BB_SEL);
3519 if (desc_info->pkt_type == RTW89_CORE_RX_TYPE_PPDU_STAT)
3520 desc_info->mac_info_valid = true;
3521
3522 desc_info->frame_type = le32_get_bits(rxd_s->dword2, BE_RXD_TYPE_MASK);
3523 desc_info->mac_id = le32_get_bits(rxd_s->dword2, BE_RXD_MAC_ID_V1);
3524 desc_info->addr_cam_valid = le32_get_bits(rxd_s->dword2, BE_RXD_ADDR_CAM_VLD);
3525
3526 desc_info->icv_err = le32_get_bits(rxd_s->dword3, BE_RXD_ICV_ERR);
3527 desc_info->crc32_err = le32_get_bits(rxd_s->dword3, BE_RXD_CRC32_ERR);
3528 desc_info->hw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_HW_DEC);
3529 desc_info->sw_dec = le32_get_bits(rxd_s->dword3, BE_RXD_SW_DEC);
3530 desc_info->addr1_match = le32_get_bits(rxd_s->dword3, BE_RXD_A1_MATCH);
3531
3532 desc_info->bw = le32_get_bits(rxd_s->dword4, BE_RXD_BW_MASK);
3533 desc_info->data_rate = le32_get_bits(rxd_s->dword4, BE_RXD_RX_DATARATE_MASK);
3534 desc_info->gi_ltf = le32_get_bits(rxd_s->dword4, BE_RXD_RX_GI_LTF_MASK);
3535 desc_info->ppdu_cnt = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_CNT_MASK);
3536 desc_info->ppdu_type = le32_get_bits(rxd_s->dword4, BE_RXD_PPDU_TYPE_MASK);
3537
3538 desc_info->free_run_cnt = le32_to_cpu(rxd_s->dword5);
3539
3540 shift_len = desc_info->shift << 1; /* 2-byte unit */
3541 drv_info_len = desc_info->drv_info_size << 3; /* 8-byte unit */
3542 phy_rtp_len = desc_info->phy_rpt_size << 3; /* 8-byte unit */
3543 hdr_cnv_len = desc_info->hdr_cnv_size << 4; /* 16-byte unit */
3544 desc_info->offset = data_offset + shift_len + drv_info_len +
3545 phy_rtp_len + hdr_cnv_len;
3546
3547 if (desc_info->long_rxdesc)
3548 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_long_v3);
3549 else
3550 desc_info->rxd_len = sizeof(struct rtw89_rxdesc_short_v3);
3551 desc_info->ready = true;
3552
3553 if (phy_rtp_len == sizeof(*rxd_rpt)) {
3554 rxd_rpt = (struct rtw89_rxdesc_phy_rpt_v2 *)(data + data_offset +
3555 desc_info->rxd_len);
3556 desc_info->rssi = le32_get_bits(rxd_rpt->dword0, BE_RXD_PHY_RSSI);
3557 }
3558
3559 if (!desc_info->long_rxdesc)
3560 return;
3561
3562 rxd_l = (struct rtw89_rxdesc_long_v3 *)(data + data_offset);
3563
3564 desc_info->sr_en = le32_get_bits(rxd_l->dword6, BE_RXD_SR_EN);
3565 desc_info->user_id = le32_get_bits(rxd_l->dword6, BE_RXD_USER_ID_MASK);
3566 desc_info->addr_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_ADDR_CAM_V1);
3567 desc_info->sec_cam_id = le32_get_bits(rxd_l->dword6, BE_RXD_SEC_CAM_IDX_V1);
3568
3569 desc_info->rx_pl_id = le32_get_bits(rxd_l->dword7, BE_RXD_RX_PL_ID_MASK);
3570 }
3571 EXPORT_SYMBOL(rtw89_core_query_rxdesc_v3);
3572
3573 struct rtw89_core_iter_rx_status {
3574 struct rtw89_dev *rtwdev;
3575 struct ieee80211_rx_status *rx_status;
3576 struct rtw89_rx_desc_info *desc_info;
3577 u8 mac_id;
3578 };
3579
3580 static
rtw89_core_stats_sta_rx_status_iter(void * data,struct ieee80211_sta * sta)3581 void rtw89_core_stats_sta_rx_status_iter(void *data, struct ieee80211_sta *sta)
3582 {
3583 struct rtw89_core_iter_rx_status *iter_data =
3584 (struct rtw89_core_iter_rx_status *)data;
3585 struct ieee80211_rx_status *rx_status = iter_data->rx_status;
3586 struct rtw89_rx_desc_info *desc_info = iter_data->desc_info;
3587 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
3588 struct rtw89_sta_link *rtwsta_link;
3589 u8 mac_id = iter_data->mac_id;
3590
3591 rtwsta_link = rtw89_sta_get_link_inst(rtwsta, desc_info->bb_sel);
3592 if (unlikely(!rtwsta_link))
3593 return;
3594
3595 if (mac_id != rtwsta_link->mac_id)
3596 return;
3597
3598 rtwsta_link->rx_status = *rx_status;
3599 rtwsta_link->rx_hw_rate = desc_info->data_rate;
3600 }
3601
rtw89_core_stats_sta_rx_status(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)3602 static void rtw89_core_stats_sta_rx_status(struct rtw89_dev *rtwdev,
3603 struct rtw89_rx_desc_info *desc_info,
3604 struct ieee80211_rx_status *rx_status)
3605 {
3606 struct rtw89_core_iter_rx_status iter_data;
3607
3608 if (!desc_info->addr1_match || !desc_info->long_rxdesc)
3609 return;
3610
3611 if (desc_info->frame_type != RTW89_RX_TYPE_DATA)
3612 return;
3613
3614 iter_data.rtwdev = rtwdev;
3615 iter_data.rx_status = rx_status;
3616 iter_data.desc_info = desc_info;
3617 iter_data.mac_id = desc_info->mac_id;
3618 ieee80211_iterate_stations_atomic(rtwdev->hw,
3619 rtw89_core_stats_sta_rx_status_iter,
3620 &iter_data);
3621 }
3622
rtw89_core_update_rx_status(struct rtw89_dev * rtwdev,struct sk_buff * skb,struct rtw89_rx_desc_info * desc_info,struct ieee80211_rx_status * rx_status)3623 static void rtw89_core_update_rx_status(struct rtw89_dev *rtwdev,
3624 struct sk_buff *skb,
3625 struct rtw89_rx_desc_info *desc_info,
3626 struct ieee80211_rx_status *rx_status)
3627 {
3628 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
3629 const struct cfg80211_chan_def *chandef =
3630 rtw89_chandef_get(rtwdev, RTW89_CHANCTX_0);
3631 u16 data_rate;
3632 u8 data_rate_mode;
3633 bool eht = false;
3634 u8 gi;
3635
3636 /* currently using single PHY */
3637 rx_status->freq = chandef->chan->center_freq;
3638 rx_status->band = chandef->chan->band;
3639
3640 if (ieee80211_is_beacon(hdr->frame_control) ||
3641 ieee80211_is_probe_resp(hdr->frame_control))
3642 rx_status->boottime_ns = ktime_get_boottime_ns();
3643
3644 if (rtwdev->scanning &&
3645 RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &rtwdev->fw)) {
3646 const struct rtw89_chan *cur = rtw89_scan_chan_get(rtwdev);
3647 u8 chan = cur->primary_channel;
3648 u8 band = cur->band_type;
3649 enum nl80211_band nl_band;
3650
3651 nl_band = rtw89_hw_to_nl80211_band(band);
3652 rx_status->freq = ieee80211_channel_to_frequency(chan, nl_band);
3653 rx_status->band = nl_band;
3654 }
3655
3656 if (desc_info->icv_err || desc_info->crc32_err)
3657 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
3658
3659 if (desc_info->hw_dec &&
3660 !(desc_info->sw_dec || desc_info->icv_err))
3661 rx_status->flag |= RX_FLAG_DECRYPTED;
3662
3663 rx_status->bw = rtw89_hw_to_rate_info_bw(desc_info->bw);
3664
3665 data_rate = desc_info->data_rate;
3666 data_rate_mode = rtw89_get_data_rate_mode(rtwdev, data_rate);
3667 if (data_rate_mode == DATA_RATE_MODE_NON_HT) {
3668 rx_status->encoding = RX_ENC_LEGACY;
3669 rx_status->rate_idx = rtw89_get_data_not_ht_idx(rtwdev, data_rate);
3670 /* convert rate_idx after we get the correct band */
3671 } else if (data_rate_mode == DATA_RATE_MODE_HT) {
3672 rx_status->encoding = RX_ENC_HT;
3673 rx_status->rate_idx = rtw89_get_data_ht_mcs(rtwdev, data_rate);
3674 if (desc_info->gi_ltf)
3675 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
3676 } else if (data_rate_mode == DATA_RATE_MODE_VHT) {
3677 rx_status->encoding = RX_ENC_VHT;
3678 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
3679 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
3680 if (desc_info->gi_ltf)
3681 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
3682 } else if (data_rate_mode == DATA_RATE_MODE_HE) {
3683 rx_status->encoding = RX_ENC_HE;
3684 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
3685 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
3686 } else if (data_rate_mode == DATA_RATE_MODE_EHT) {
3687 rx_status->encoding = RX_ENC_EHT;
3688 rx_status->rate_idx = rtw89_get_data_mcs(rtwdev, data_rate);
3689 rx_status->nss = rtw89_get_data_nss(rtwdev, data_rate) + 1;
3690 eht = true;
3691 } else {
3692 rtw89_warn(rtwdev, "invalid RX rate mode %d\n", data_rate_mode);
3693 }
3694
3695 /* he_gi is used to match ppdu, so we always fill it. */
3696 gi = rtw89_rxdesc_to_nl_he_eht_gi(rtwdev, desc_info->gi_ltf, true, eht);
3697 if (eht)
3698 rx_status->eht.gi = gi;
3699 else
3700 rx_status->he_gi = gi;
3701 rx_status->flag |= RX_FLAG_MACTIME_START;
3702 rx_status->mactime = desc_info->free_run_cnt;
3703
3704 rtw89_chip_phy_rpt_to_rssi(rtwdev, desc_info, rx_status);
3705 rtw89_core_stats_sta_rx_status(rtwdev, desc_info, rx_status);
3706 }
3707
rtw89_update_ps_mode(struct rtw89_dev * rtwdev)3708 static enum rtw89_ps_mode rtw89_update_ps_mode(struct rtw89_dev *rtwdev)
3709 {
3710 const struct rtw89_chip_info *chip = rtwdev->chip;
3711
3712 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE)
3713 return RTW89_PS_MODE_NONE;
3714
3715 if (rtw89_disable_ps_mode || !chip->ps_mode_supported ||
3716 RTW89_CHK_FW_FEATURE(NO_DEEP_PS, &rtwdev->fw))
3717 return RTW89_PS_MODE_NONE;
3718
3719 if ((chip->ps_mode_supported & BIT(RTW89_PS_MODE_PWR_GATED)) &&
3720 !RTW89_CHK_FW_FEATURE(NO_LPS_PG, &rtwdev->fw))
3721 return RTW89_PS_MODE_PWR_GATED;
3722
3723 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_CLK_GATED))
3724 return RTW89_PS_MODE_CLK_GATED;
3725
3726 if (chip->ps_mode_supported & BIT(RTW89_PS_MODE_RFOFF))
3727 return RTW89_PS_MODE_RFOFF;
3728
3729 return RTW89_PS_MODE_NONE;
3730 }
3731
rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info)3732 static void rtw89_core_flush_ppdu_rx_queue(struct rtw89_dev *rtwdev,
3733 struct rtw89_rx_desc_info *desc_info)
3734 {
3735 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
3736 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
3737 struct ieee80211_rx_status *rx_status;
3738 struct sk_buff *skb_ppdu, *tmp;
3739
3740 skb_queue_walk_safe(&ppdu_sts->rx_queue[band], skb_ppdu, tmp) {
3741 skb_unlink(skb_ppdu, &ppdu_sts->rx_queue[band]);
3742 rx_status = IEEE80211_SKB_RXCB(skb_ppdu);
3743 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb_ppdu, rx_status);
3744 }
3745 }
3746
3747 static
rtw89_core_rx_pkt_hdl(struct rtw89_dev * rtwdev,const struct sk_buff * skb,const struct rtw89_rx_desc_info * desc)3748 void rtw89_core_rx_pkt_hdl(struct rtw89_dev *rtwdev, const struct sk_buff *skb,
3749 const struct rtw89_rx_desc_info *desc)
3750 {
3751 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
3752 struct rtw89_sta_link *rtwsta_link;
3753 struct ieee80211_sta *sta;
3754 struct rtw89_sta *rtwsta;
3755 u8 macid = desc->mac_id;
3756
3757 if (!refcount_read(&rtwdev->refcount_ap_info))
3758 return;
3759
3760 rcu_read_lock();
3761
3762 rtwsta_link = rtw89_assoc_link_rcu_dereference(rtwdev, macid);
3763 if (!rtwsta_link)
3764 goto out;
3765
3766 rtwsta = rtwsta_link->rtwsta;
3767 if (!test_bit(RTW89_REMOTE_STA_IN_PS, rtwsta->flags))
3768 goto out;
3769
3770 sta = rtwsta_to_sta(rtwsta);
3771 if (ieee80211_is_pspoll(hdr->frame_control))
3772 ieee80211_sta_pspoll(sta);
3773 else if (ieee80211_has_pm(hdr->frame_control) &&
3774 (ieee80211_is_data_qos(hdr->frame_control) ||
3775 ieee80211_is_qos_nullfunc(hdr->frame_control)))
3776 ieee80211_sta_uapsd_trigger(sta, ieee80211_get_tid(hdr));
3777
3778 out:
3779 rcu_read_unlock();
3780 }
3781
rtw89_core_rx(struct rtw89_dev * rtwdev,struct rtw89_rx_desc_info * desc_info,struct sk_buff * skb)3782 void rtw89_core_rx(struct rtw89_dev *rtwdev,
3783 struct rtw89_rx_desc_info *desc_info,
3784 struct sk_buff *skb)
3785 {
3786 struct ieee80211_rx_status *rx_status;
3787 struct rtw89_ppdu_sts_info *ppdu_sts = &rtwdev->ppdu_sts;
3788 u8 ppdu_cnt = desc_info->ppdu_cnt;
3789 u8 band = desc_info->bb_sel ? RTW89_PHY_1 : RTW89_PHY_0;
3790
3791 if (desc_info->pkt_type != RTW89_CORE_RX_TYPE_WIFI) {
3792 rtw89_core_rx_process_report(rtwdev, desc_info, skb);
3793 return;
3794 }
3795
3796 if (ppdu_sts->curr_rx_ppdu_cnt[band] != ppdu_cnt) {
3797 rtw89_core_flush_ppdu_rx_queue(rtwdev, desc_info);
3798 ppdu_sts->curr_rx_ppdu_cnt[band] = ppdu_cnt;
3799 }
3800
3801 rx_status = IEEE80211_SKB_RXCB(skb);
3802 memset(rx_status, 0, sizeof(*rx_status));
3803 rtw89_core_update_rx_status(rtwdev, skb, desc_info, rx_status);
3804 rtw89_core_rx_pkt_hdl(rtwdev, skb, desc_info);
3805 if (desc_info->long_rxdesc &&
3806 BIT(desc_info->frame_type) & PPDU_FILTER_BITMAP)
3807 skb_queue_tail(&ppdu_sts->rx_queue[band], skb);
3808 else
3809 rtw89_core_rx_to_mac80211(rtwdev, NULL, desc_info, skb, rx_status);
3810 }
3811 EXPORT_SYMBOL(rtw89_core_rx);
3812
rtw89_core_napi_start(struct rtw89_dev * rtwdev)3813 void rtw89_core_napi_start(struct rtw89_dev *rtwdev)
3814 {
3815 if (test_and_set_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
3816 return;
3817
3818 napi_enable(&rtwdev->napi);
3819 }
3820 EXPORT_SYMBOL(rtw89_core_napi_start);
3821
rtw89_core_napi_stop(struct rtw89_dev * rtwdev)3822 void rtw89_core_napi_stop(struct rtw89_dev *rtwdev)
3823 {
3824 if (!test_and_clear_bit(RTW89_FLAG_NAPI_RUNNING, rtwdev->flags))
3825 return;
3826
3827 napi_synchronize(&rtwdev->napi);
3828 napi_disable(&rtwdev->napi);
3829 }
3830 EXPORT_SYMBOL(rtw89_core_napi_stop);
3831
rtw89_core_napi_init(struct rtw89_dev * rtwdev)3832 int rtw89_core_napi_init(struct rtw89_dev *rtwdev)
3833 {
3834 rtwdev->netdev = alloc_netdev_dummy(0);
3835 if (!rtwdev->netdev)
3836 return -ENOMEM;
3837
3838 netif_napi_add(rtwdev->netdev, &rtwdev->napi,
3839 rtwdev->hci.ops->napi_poll);
3840 return 0;
3841 }
3842 EXPORT_SYMBOL(rtw89_core_napi_init);
3843
rtw89_core_napi_deinit(struct rtw89_dev * rtwdev)3844 void rtw89_core_napi_deinit(struct rtw89_dev *rtwdev)
3845 {
3846 rtw89_core_napi_stop(rtwdev);
3847 netif_napi_del(&rtwdev->napi);
3848 free_netdev(rtwdev->netdev);
3849 }
3850 EXPORT_SYMBOL(rtw89_core_napi_deinit);
3851
rtw89_core_ba_work(struct work_struct * work)3852 static void rtw89_core_ba_work(struct work_struct *work)
3853 {
3854 struct rtw89_dev *rtwdev =
3855 container_of(work, struct rtw89_dev, ba_work);
3856 struct rtw89_txq *rtwtxq, *tmp;
3857 int ret;
3858
3859 spin_lock_bh(&rtwdev->ba_lock);
3860 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
3861 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
3862 struct ieee80211_sta *sta = txq->sta;
3863 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
3864 u8 tid = txq->tid;
3865
3866 if (!sta) {
3867 rtw89_warn(rtwdev, "cannot start BA without sta\n");
3868 goto skip_ba_work;
3869 }
3870
3871 if (rtwsta->disassoc) {
3872 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
3873 "cannot start BA with disassoc sta\n");
3874 goto skip_ba_work;
3875 }
3876
3877 ret = ieee80211_start_tx_ba_session(sta, tid, 0);
3878 if (ret) {
3879 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
3880 "failed to setup BA session for %pM:%2d: %d\n",
3881 sta->addr, tid, ret);
3882 if (ret == -EINVAL)
3883 set_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags);
3884 }
3885 skip_ba_work:
3886 list_del_init(&rtwtxq->list);
3887 }
3888 spin_unlock_bh(&rtwdev->ba_lock);
3889 }
3890
rtw89_core_free_sta_pending_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)3891 void rtw89_core_free_sta_pending_ba(struct rtw89_dev *rtwdev,
3892 struct ieee80211_sta *sta)
3893 {
3894 struct rtw89_txq *rtwtxq, *tmp;
3895
3896 spin_lock_bh(&rtwdev->ba_lock);
3897 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->ba_list, list) {
3898 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
3899
3900 if (sta == txq->sta)
3901 list_del_init(&rtwtxq->list);
3902 }
3903 spin_unlock_bh(&rtwdev->ba_lock);
3904 }
3905
rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)3906 void rtw89_core_free_sta_pending_forbid_ba(struct rtw89_dev *rtwdev,
3907 struct ieee80211_sta *sta)
3908 {
3909 struct rtw89_txq *rtwtxq, *tmp;
3910
3911 spin_lock_bh(&rtwdev->ba_lock);
3912 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
3913 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
3914
3915 if (sta == txq->sta) {
3916 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
3917 list_del_init(&rtwtxq->list);
3918 }
3919 }
3920 spin_unlock_bh(&rtwdev->ba_lock);
3921 }
3922
rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta)3923 void rtw89_core_free_sta_pending_roc_tx(struct rtw89_dev *rtwdev,
3924 struct ieee80211_sta *sta)
3925 {
3926 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
3927 struct sk_buff *skb;
3928
3929 while ((skb = skb_dequeue(&rtwsta->roc_queue)))
3930 dev_kfree_skb_any(skb);
3931 }
3932
rtw89_core_stop_tx_ba_session(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq)3933 static void rtw89_core_stop_tx_ba_session(struct rtw89_dev *rtwdev,
3934 struct rtw89_txq *rtwtxq)
3935 {
3936 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
3937 struct ieee80211_sta *sta = txq->sta;
3938 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
3939
3940 if (unlikely(!rtwsta) || unlikely(rtwsta->disassoc))
3941 return;
3942
3943 if (!test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags) ||
3944 test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
3945 return;
3946
3947 spin_lock_bh(&rtwdev->ba_lock);
3948 if (!test_and_set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
3949 list_add_tail(&rtwtxq->list, &rtwdev->forbid_ba_list);
3950 spin_unlock_bh(&rtwdev->ba_lock);
3951
3952 ieee80211_stop_tx_ba_session(sta, txq->tid);
3953 cancel_delayed_work(&rtwdev->forbid_ba_work);
3954 ieee80211_queue_delayed_work(rtwdev->hw, &rtwdev->forbid_ba_work,
3955 RTW89_FORBID_BA_TIMER);
3956 }
3957
rtw89_core_txq_check_agg(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,struct sk_buff * skb)3958 static void rtw89_core_txq_check_agg(struct rtw89_dev *rtwdev,
3959 struct rtw89_txq *rtwtxq,
3960 struct sk_buff *skb)
3961 {
3962 struct ieee80211_hw *hw = rtwdev->hw;
3963 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
3964 struct ieee80211_sta *sta = txq->sta;
3965 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(sta);
3966
3967 if (test_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags))
3968 return;
3969
3970 if (unlikely(skb->protocol == cpu_to_be16(ETH_P_PAE))) {
3971 rtw89_core_stop_tx_ba_session(rtwdev, rtwtxq);
3972 return;
3973 }
3974
3975 if (unlikely(!sta))
3976 return;
3977
3978 if (unlikely(test_bit(RTW89_TXQ_F_BLOCK_BA, &rtwtxq->flags)))
3979 return;
3980
3981 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags)) {
3982 IEEE80211_SKB_CB(skb)->flags |= IEEE80211_TX_CTL_AMPDU;
3983 return;
3984 }
3985
3986 spin_lock_bh(&rtwdev->ba_lock);
3987 if (!rtwsta->disassoc && list_empty(&rtwtxq->list)) {
3988 list_add_tail(&rtwtxq->list, &rtwdev->ba_list);
3989 ieee80211_queue_work(hw, &rtwdev->ba_work);
3990 }
3991 spin_unlock_bh(&rtwdev->ba_lock);
3992 }
3993
rtw89_core_txq_push(struct rtw89_dev * rtwdev,struct rtw89_txq * rtwtxq,unsigned long frame_cnt,unsigned long byte_cnt)3994 static void rtw89_core_txq_push(struct rtw89_dev *rtwdev,
3995 struct rtw89_txq *rtwtxq,
3996 unsigned long frame_cnt,
3997 unsigned long byte_cnt)
3998 {
3999 struct ieee80211_txq *txq = rtw89_txq_to_txq(rtwtxq);
4000 struct ieee80211_vif *vif = txq->vif;
4001 struct ieee80211_sta *sta = txq->sta;
4002 struct sk_buff *skb;
4003 unsigned long i;
4004 int ret;
4005
4006 rcu_read_lock();
4007 for (i = 0; i < frame_cnt; i++) {
4008 skb = ieee80211_tx_dequeue_ni(rtwdev->hw, txq);
4009 if (!skb) {
4010 rtw89_debug(rtwdev, RTW89_DBG_TXRX, "dequeue a NULL skb\n");
4011 goto out;
4012 }
4013 rtw89_core_txq_check_agg(rtwdev, rtwtxq, skb);
4014 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, NULL);
4015 if (ret) {
4016 rtw89_err(rtwdev, "failed to push txq: %d\n", ret);
4017 ieee80211_free_txskb(rtwdev->hw, skb);
4018 break;
4019 }
4020 }
4021 out:
4022 rcu_read_unlock();
4023 }
4024
rtw89_check_and_reclaim_tx_resource(struct rtw89_dev * rtwdev,u8 tid)4025 static u32 rtw89_check_and_reclaim_tx_resource(struct rtw89_dev *rtwdev, u8 tid)
4026 {
4027 u8 qsel, ch_dma;
4028
4029 qsel = rtw89_core_get_qsel(rtwdev, tid);
4030 ch_dma = rtw89_chip_get_ch_dma(rtwdev, qsel);
4031
4032 return rtw89_hci_check_and_reclaim_tx_resource(rtwdev, ch_dma);
4033 }
4034
rtw89_core_txq_agg_wait(struct rtw89_dev * rtwdev,struct ieee80211_txq * txq,unsigned long * frame_cnt,bool * sched_txq,bool * reinvoke)4035 static bool rtw89_core_txq_agg_wait(struct rtw89_dev *rtwdev,
4036 struct ieee80211_txq *txq,
4037 unsigned long *frame_cnt,
4038 bool *sched_txq, bool *reinvoke)
4039 {
4040 struct rtw89_txq *rtwtxq = (struct rtw89_txq *)txq->drv_priv;
4041 struct rtw89_sta *rtwsta = sta_to_rtwsta_safe(txq->sta);
4042 struct rtw89_sta_link *rtwsta_link;
4043
4044 if (!rtwsta)
4045 return false;
4046
4047 rtwsta_link = rtw89_get_designated_link(rtwsta);
4048 if (unlikely(!rtwsta_link)) {
4049 rtw89_err(rtwdev, "agg wait: find no designated link\n");
4050 return false;
4051 }
4052
4053 if (rtwsta_link->max_agg_wait <= 0)
4054 return false;
4055
4056 if (rtwdev->stats.tx_tfc_lv <= RTW89_TFC_MID)
4057 return false;
4058
4059 if (*frame_cnt > 1) {
4060 *frame_cnt -= 1;
4061 *sched_txq = true;
4062 *reinvoke = true;
4063 rtwtxq->wait_cnt = 1;
4064 return false;
4065 }
4066
4067 if (*frame_cnt == 1 && rtwtxq->wait_cnt < rtwsta_link->max_agg_wait) {
4068 *reinvoke = true;
4069 rtwtxq->wait_cnt++;
4070 return true;
4071 }
4072
4073 rtwtxq->wait_cnt = 0;
4074 return false;
4075 }
4076
rtw89_core_txq_schedule(struct rtw89_dev * rtwdev,u8 ac,bool * reinvoke)4077 static void rtw89_core_txq_schedule(struct rtw89_dev *rtwdev, u8 ac, bool *reinvoke)
4078 {
4079 struct ieee80211_hw *hw = rtwdev->hw;
4080 struct ieee80211_txq *txq;
4081 struct rtw89_vif *rtwvif;
4082 struct rtw89_txq *rtwtxq;
4083 unsigned long frame_cnt;
4084 unsigned long byte_cnt;
4085 u32 tx_resource;
4086 bool sched_txq;
4087
4088 ieee80211_txq_schedule_start(hw, ac);
4089 while ((txq = ieee80211_next_txq(hw, ac))) {
4090 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
4091 rtwvif = vif_to_rtwvif(txq->vif);
4092
4093 if (rtwvif->offchan) {
4094 ieee80211_return_txq(hw, txq, true);
4095 continue;
4096 }
4097 tx_resource = rtw89_check_and_reclaim_tx_resource(rtwdev, txq->tid);
4098 sched_txq = false;
4099
4100 ieee80211_txq_get_depth(txq, &frame_cnt, &byte_cnt);
4101 if (rtw89_core_txq_agg_wait(rtwdev, txq, &frame_cnt, &sched_txq, reinvoke)) {
4102 ieee80211_return_txq(hw, txq, true);
4103 continue;
4104 }
4105 frame_cnt = min_t(unsigned long, frame_cnt, tx_resource);
4106 rtw89_core_txq_push(rtwdev, rtwtxq, frame_cnt, byte_cnt);
4107 ieee80211_return_txq(hw, txq, sched_txq);
4108 if (frame_cnt != 0)
4109 rtw89_core_tx_kick_off(rtwdev, rtw89_core_get_qsel(rtwdev, txq->tid));
4110
4111 /* bound of tx_resource could get stuck due to burst traffic */
4112 if (frame_cnt == tx_resource)
4113 *reinvoke = true;
4114 }
4115 ieee80211_txq_schedule_end(hw, ac);
4116 }
4117
rtw89_ips_work(struct wiphy * wiphy,struct wiphy_work * work)4118 static void rtw89_ips_work(struct wiphy *wiphy, struct wiphy_work *work)
4119 {
4120 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
4121 ips_work);
4122
4123 lockdep_assert_wiphy(wiphy);
4124
4125 rtw89_enter_ips_by_hwflags(rtwdev);
4126 }
4127
rtw89_core_txq_work(struct work_struct * w)4128 static void rtw89_core_txq_work(struct work_struct *w)
4129 {
4130 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev, txq_work);
4131 bool reinvoke = false;
4132 u8 ac;
4133
4134 for (ac = 0; ac < IEEE80211_NUM_ACS; ac++)
4135 rtw89_core_txq_schedule(rtwdev, ac, &reinvoke);
4136
4137 if (reinvoke) {
4138 /* reinvoke to process the last frame */
4139 mod_delayed_work(rtwdev->txq_wq, &rtwdev->txq_reinvoke_work, 1);
4140 }
4141 }
4142
rtw89_core_txq_reinvoke_work(struct work_struct * w)4143 static void rtw89_core_txq_reinvoke_work(struct work_struct *w)
4144 {
4145 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
4146 txq_reinvoke_work.work);
4147
4148 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
4149 }
4150
rtw89_forbid_ba_work(struct work_struct * w)4151 static void rtw89_forbid_ba_work(struct work_struct *w)
4152 {
4153 struct rtw89_dev *rtwdev = container_of(w, struct rtw89_dev,
4154 forbid_ba_work.work);
4155 struct rtw89_txq *rtwtxq, *tmp;
4156
4157 spin_lock_bh(&rtwdev->ba_lock);
4158 list_for_each_entry_safe(rtwtxq, tmp, &rtwdev->forbid_ba_list, list) {
4159 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
4160 list_del_init(&rtwtxq->list);
4161 }
4162 spin_unlock_bh(&rtwdev->ba_lock);
4163 }
4164
rtw89_core_sta_pending_tx_iter(void * data,struct ieee80211_sta * sta)4165 static void rtw89_core_sta_pending_tx_iter(void *data,
4166 struct ieee80211_sta *sta)
4167 {
4168 struct rtw89_sta *rtwsta = sta_to_rtwsta(sta);
4169 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
4170 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
4171 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
4172 struct rtw89_vif_link *target = data;
4173 struct rtw89_vif_link *rtwvif_link;
4174 unsigned int link_id;
4175 struct sk_buff *skb;
4176 int qsel, ret;
4177
4178 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
4179 if (rtwvif_link->chanctx_idx == target->chanctx_idx)
4180 goto bottom;
4181
4182 return;
4183
4184 bottom:
4185 if (skb_queue_len(&rtwsta->roc_queue) == 0)
4186 return;
4187
4188 while ((skb = skb_dequeue(&rtwsta->roc_queue))) {
4189 ret = rtw89_core_tx_write(rtwdev, vif, sta, skb, &qsel);
4190 if (ret) {
4191 rtw89_warn(rtwdev, "pending tx failed with %d\n", ret);
4192 dev_kfree_skb_any(skb);
4193 } else {
4194 rtw89_core_tx_kick_off(rtwdev, qsel);
4195 }
4196 }
4197 }
4198
rtw89_core_handle_sta_pending_tx(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)4199 static void rtw89_core_handle_sta_pending_tx(struct rtw89_dev *rtwdev,
4200 struct rtw89_vif_link *rtwvif_link)
4201 {
4202 ieee80211_iterate_stations_atomic(rtwdev->hw,
4203 rtw89_core_sta_pending_tx_iter,
4204 rtwvif_link);
4205 }
4206
rtw89_core_send_nullfunc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool qos,bool ps,int timeout)4207 int rtw89_core_send_nullfunc(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
4208 bool qos, bool ps, int timeout)
4209 {
4210 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4211 int link_id = ieee80211_vif_is_mld(vif) ? rtwvif_link->link_id : -1;
4212 struct rtw89_sta_link *rtwsta_link;
4213 struct rtw89_tx_wait_info *wait;
4214 struct ieee80211_sta *sta;
4215 struct ieee80211_hdr *hdr;
4216 struct rtw89_sta *rtwsta;
4217 struct sk_buff *skb;
4218 int ret, qsel;
4219
4220 if (vif->type != NL80211_IFTYPE_STATION || !vif->cfg.assoc)
4221 return 0;
4222
4223 wait = kzalloc_obj(*wait);
4224 if (!wait)
4225 return -ENOMEM;
4226
4227 init_completion(&wait->completion);
4228
4229 rcu_read_lock();
4230 sta = ieee80211_find_sta(vif, vif->cfg.ap_addr);
4231 if (!sta) {
4232 ret = -EINVAL;
4233 goto out;
4234 }
4235 rtwsta = sta_to_rtwsta(sta);
4236
4237 skb = ieee80211_nullfunc_get(rtwdev->hw, vif, link_id, qos);
4238 if (!skb) {
4239 ret = -ENOMEM;
4240 goto out;
4241 }
4242
4243 wait->skb = skb;
4244
4245 hdr = (struct ieee80211_hdr *)skb->data;
4246 if (ps)
4247 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
4248
4249 rtwsta_link = rtwsta->links[rtwvif_link->link_id];
4250 if (unlikely(!rtwsta_link)) {
4251 ret = -ENOLINK;
4252 dev_kfree_skb_any(skb);
4253 goto out;
4254 }
4255
4256 ret = rtw89_core_tx_write_link(rtwdev, rtwvif_link, rtwsta_link, skb, &qsel, wait);
4257 if (ret) {
4258 rtw89_warn(rtwdev, "nullfunc transmit failed: %d\n", ret);
4259 dev_kfree_skb_any(skb);
4260 goto out;
4261 }
4262
4263 rcu_read_unlock();
4264
4265 return rtw89_core_tx_kick_off_and_wait(rtwdev, skb, wait, qsel,
4266 timeout);
4267 out:
4268 rcu_read_unlock();
4269 kfree(wait);
4270
4271 return ret;
4272 }
4273
rtw89_roc_start(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4274 void rtw89_roc_start(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4275 {
4276 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
4277 struct rtw89_chanctx_pause_parm pause_parm = {
4278 .rsn = RTW89_CHANCTX_PAUSE_REASON_ROC,
4279 };
4280 struct ieee80211_hw *hw = rtwdev->hw;
4281 struct rtw89_roc *roc = &rtwvif->roc;
4282 struct rtw89_vif_link *rtwvif_link;
4283 struct cfg80211_chan_def roc_chan;
4284 struct rtw89_vif *tmp_vif;
4285 u32 reg;
4286 int ret;
4287
4288 lockdep_assert_wiphy(hw->wiphy);
4289
4290 rtw89_leave_ips_by_hwflags(rtwdev);
4291 rtw89_leave_lps(rtwdev);
4292
4293 rtwvif_link = rtw89_get_designated_link(rtwvif);
4294 if (unlikely(!rtwvif_link)) {
4295 rtw89_err(rtwdev, "roc start: find no designated link\n");
4296 return;
4297 }
4298
4299 roc->link_id = rtwvif_link->link_id;
4300
4301 pause_parm.trigger = rtwvif_link;
4302 rtw89_chanctx_pause(rtwdev, &pause_parm);
4303
4304 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, true,
4305 RTW89_ROC_TX_TIMEOUT);
4306 if (ret)
4307 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
4308 "roc send null-1 failed: %d\n", ret);
4309
4310 rtw89_for_each_rtwvif(rtwdev, tmp_vif) {
4311 struct rtw89_vif_link *tmp_link;
4312 unsigned int link_id;
4313
4314 rtw89_vif_for_each_link(tmp_vif, tmp_link, link_id) {
4315 if (tmp_link->chanctx_idx == rtwvif_link->chanctx_idx) {
4316 tmp_vif->offchan = true;
4317 break;
4318 }
4319 }
4320 }
4321
4322 cfg80211_chandef_create(&roc_chan, &roc->chan, NL80211_CHAN_NO_HT);
4323 rtw89_config_roc_chandef(rtwdev, rtwvif_link, &roc_chan);
4324 rtw89_set_channel(rtwdev);
4325
4326 reg = rtw89_mac_reg_by_idx(rtwdev, mac->rx_fltr, rtwvif_link->mac_idx);
4327 rtw89_write32_clr(rtwdev, reg, B_AX_A_UC_CAM_MATCH | B_AX_A_BC_CAM_MATCH);
4328
4329 ieee80211_ready_on_channel(hw);
4330 wiphy_delayed_work_cancel(hw->wiphy, &rtwvif->roc.roc_work);
4331 wiphy_delayed_work_queue(hw->wiphy, &rtwvif->roc.roc_work,
4332 msecs_to_jiffies(rtwvif->roc.duration));
4333 }
4334
rtw89_roc_end(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4335 void rtw89_roc_end(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif)
4336 {
4337 struct ieee80211_hw *hw = rtwdev->hw;
4338 struct rtw89_roc *roc = &rtwvif->roc;
4339 struct rtw89_vif_link *rtwvif_link;
4340 struct rtw89_vif *tmp_vif;
4341 int ret;
4342
4343 lockdep_assert_wiphy(hw->wiphy);
4344
4345 ieee80211_remain_on_channel_expired(hw);
4346
4347 rtw89_leave_ips_by_hwflags(rtwdev);
4348 rtw89_leave_lps(rtwdev);
4349
4350 rtwvif_link = rtwvif->links[roc->link_id];
4351 if (unlikely(!rtwvif_link)) {
4352 rtw89_err(rtwdev, "roc end: find no link (link id %u)\n",
4353 roc->link_id);
4354 return;
4355 }
4356
4357 rtw89_mac_set_rx_fltr(rtwdev, rtwvif_link->mac_idx, rtwdev->hal.rx_fltr);
4358
4359 roc->state = RTW89_ROC_IDLE;
4360 rtw89_config_roc_chandef(rtwdev, rtwvif_link, NULL);
4361 rtw89_chanctx_proceed(rtwdev, NULL);
4362 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, true, false,
4363 RTW89_ROC_TX_TIMEOUT);
4364 if (ret)
4365 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
4366 "roc send null-0 failed: %d\n", ret);
4367
4368 rtw89_for_each_rtwvif(rtwdev, tmp_vif)
4369 tmp_vif->offchan = false;
4370
4371 rtw89_core_handle_sta_pending_tx(rtwdev, rtwvif_link);
4372 queue_work(rtwdev->txq_wq, &rtwdev->txq_work);
4373
4374 if (hw->conf.flags & IEEE80211_CONF_IDLE)
4375 wiphy_delayed_work_queue(hw->wiphy, &roc->roc_work,
4376 msecs_to_jiffies(RTW89_ROC_IDLE_TIMEOUT));
4377 }
4378
rtw89_roc_work(struct wiphy * wiphy,struct wiphy_work * work)4379 void rtw89_roc_work(struct wiphy *wiphy, struct wiphy_work *work)
4380 {
4381 struct rtw89_vif *rtwvif = container_of(work, struct rtw89_vif,
4382 roc.roc_work.work);
4383 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
4384 struct rtw89_roc *roc = &rtwvif->roc;
4385
4386 lockdep_assert_wiphy(wiphy);
4387
4388 switch (roc->state) {
4389 case RTW89_ROC_IDLE:
4390 rtw89_enter_ips_by_hwflags(rtwdev);
4391 break;
4392 case RTW89_ROC_MGMT:
4393 case RTW89_ROC_NORMAL:
4394 rtw89_roc_end(rtwdev, rtwvif);
4395 break;
4396 default:
4397 break;
4398 }
4399 }
4400
rtw89_get_traffic_level(struct rtw89_dev * rtwdev,u32 throughput,u64 cnt,enum rtw89_tfc_interval interval)4401 static enum rtw89_tfc_lv rtw89_get_traffic_level(struct rtw89_dev *rtwdev,
4402 u32 throughput, u64 cnt,
4403 enum rtw89_tfc_interval interval)
4404 {
4405 u64 cnt_level;
4406
4407 switch (interval) {
4408 default:
4409 case RTW89_TFC_INTERVAL_100MS:
4410 cnt_level = 5;
4411 break;
4412 case RTW89_TFC_INTERVAL_2SEC:
4413 cnt_level = 100;
4414 break;
4415 }
4416
4417 if (cnt < cnt_level)
4418 return RTW89_TFC_IDLE;
4419 if (throughput > 50)
4420 return RTW89_TFC_HIGH;
4421 if (throughput > 10)
4422 return RTW89_TFC_MID;
4423 if (throughput > 2)
4424 return RTW89_TFC_LOW;
4425 return RTW89_TFC_ULTRA_LOW;
4426 }
4427
rtw89_traffic_stats_calc(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats,enum rtw89_tfc_interval interval)4428 static bool rtw89_traffic_stats_calc(struct rtw89_dev *rtwdev,
4429 struct rtw89_traffic_stats *stats,
4430 enum rtw89_tfc_interval interval)
4431 {
4432 enum rtw89_tfc_lv tx_tfc_lv = stats->tx_tfc_lv;
4433 enum rtw89_tfc_lv rx_tfc_lv = stats->rx_tfc_lv;
4434
4435 stats->tx_throughput_raw = rtw89_bytes_to_mbps(stats->tx_unicast, interval);
4436 stats->rx_throughput_raw = rtw89_bytes_to_mbps(stats->rx_unicast, interval);
4437
4438 ewma_tp_add(&stats->tx_ewma_tp, stats->tx_throughput_raw);
4439 ewma_tp_add(&stats->rx_ewma_tp, stats->rx_throughput_raw);
4440
4441 stats->tx_throughput = ewma_tp_read(&stats->tx_ewma_tp);
4442 stats->rx_throughput = ewma_tp_read(&stats->rx_ewma_tp);
4443 stats->tx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->tx_throughput,
4444 stats->tx_cnt, interval);
4445 stats->rx_tfc_lv = rtw89_get_traffic_level(rtwdev, stats->rx_throughput,
4446 stats->rx_cnt, interval);
4447 stats->tx_avg_len = stats->tx_cnt ?
4448 DIV_ROUND_DOWN_ULL(stats->tx_unicast, stats->tx_cnt) : 0;
4449 stats->rx_avg_len = stats->rx_cnt ?
4450 DIV_ROUND_DOWN_ULL(stats->rx_unicast, stats->rx_cnt) : 0;
4451
4452 stats->tx_unicast = 0;
4453 stats->rx_unicast = 0;
4454 stats->tx_cnt = 0;
4455 stats->rx_cnt = 0;
4456 stats->rx_tf_periodic = stats->rx_tf_acc;
4457 stats->rx_tf_acc = 0;
4458
4459 if (tx_tfc_lv != stats->tx_tfc_lv || rx_tfc_lv != stats->rx_tfc_lv)
4460 return true;
4461
4462 return false;
4463 }
4464
rtw89_traffic_stats_track(struct rtw89_dev * rtwdev)4465 static bool rtw89_traffic_stats_track(struct rtw89_dev *rtwdev)
4466 {
4467 struct rtw89_vif_link *rtwvif_link;
4468 struct rtw89_vif *rtwvif;
4469 unsigned int link_id;
4470 bool tfc_changed;
4471
4472 tfc_changed = rtw89_traffic_stats_calc(rtwdev, &rtwdev->stats,
4473 RTW89_TFC_INTERVAL_2SEC);
4474
4475 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
4476 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats,
4477 RTW89_TFC_INTERVAL_2SEC);
4478
4479 rtw89_vif_for_each_link(rtwvif, rtwvif_link, link_id)
4480 rtw89_fw_h2c_tp_offload(rtwdev, rtwvif_link);
4481 }
4482
4483 return tfc_changed;
4484 }
4485
rtw89_enter_lps_track(struct rtw89_dev * rtwdev)4486 static void rtw89_enter_lps_track(struct rtw89_dev *rtwdev)
4487 {
4488 struct ieee80211_vif *vif;
4489 struct rtw89_vif *rtwvif;
4490
4491 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
4492 if (rtwvif->tdls_peer)
4493 continue;
4494 if (rtwvif->offchan)
4495 continue;
4496
4497 if (rtwvif->stats_ps.tx_tfc_lv >= RTW89_TFC_MID ||
4498 rtwvif->stats_ps.rx_tfc_lv >= RTW89_TFC_MID)
4499 continue;
4500
4501 vif = rtwvif_to_vif(rtwvif);
4502
4503 if (!(vif->type == NL80211_IFTYPE_STATION ||
4504 vif->type == NL80211_IFTYPE_P2P_CLIENT))
4505 continue;
4506
4507 if (!rtw89_core_bcn_track_can_lps(rtwdev))
4508 continue;
4509
4510 rtw89_enter_lps(rtwdev, rtwvif, true);
4511 }
4512 }
4513
rtw89_core_rfk_track(struct rtw89_dev * rtwdev)4514 static void rtw89_core_rfk_track(struct rtw89_dev *rtwdev)
4515 {
4516 enum rtw89_entity_mode mode;
4517
4518 mode = rtw89_get_entity_mode(rtwdev);
4519 if (mode == RTW89_ENTITY_MODE_MCC)
4520 return;
4521
4522 rtw89_chip_rfk_track(rtwdev);
4523 }
4524
rtw89_core_update_p2p_ps(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct ieee80211_bss_conf * bss_conf)4525 void rtw89_core_update_p2p_ps(struct rtw89_dev *rtwdev,
4526 struct rtw89_vif_link *rtwvif_link,
4527 struct ieee80211_bss_conf *bss_conf)
4528 {
4529 enum rtw89_entity_mode mode = rtw89_get_entity_mode(rtwdev);
4530
4531 if (mode == RTW89_ENTITY_MODE_MCC)
4532 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_P2P_PS_CHANGE);
4533 else
4534 rtw89_process_p2p_ps(rtwdev, rtwvif_link, bss_conf);
4535 }
4536
rtw89_traffic_stats_init(struct rtw89_dev * rtwdev,struct rtw89_traffic_stats * stats)4537 void rtw89_traffic_stats_init(struct rtw89_dev *rtwdev,
4538 struct rtw89_traffic_stats *stats)
4539 {
4540 stats->tx_unicast = 0;
4541 stats->rx_unicast = 0;
4542 stats->tx_cnt = 0;
4543 stats->rx_cnt = 0;
4544 ewma_tp_init(&stats->tx_ewma_tp);
4545 ewma_tp_init(&stats->rx_ewma_tp);
4546 }
4547
4548 #define RTW89_MLSR_GOTO_2GHZ_THRESHOLD -53
4549 #define RTW89_MLSR_EXIT_2GHZ_THRESHOLD -38
rtw89_core_mlsr_link_decision(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif)4550 static void rtw89_core_mlsr_link_decision(struct rtw89_dev *rtwdev,
4551 struct rtw89_vif *rtwvif)
4552 {
4553 unsigned int sel_link_id = IEEE80211_MLD_MAX_NUM_LINKS;
4554 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
4555 struct rtw89_vif_link *rtwvif_link;
4556 const struct rtw89_chan *chan;
4557 unsigned long usable_links;
4558 unsigned int link_id;
4559 u8 decided_bands;
4560 u8 rssi;
4561
4562 rssi = ewma_rssi_read(&rtwdev->phystat.bcn_rssi);
4563 if (unlikely(!rssi))
4564 return;
4565
4566 if (RTW89_RSSI_RAW_TO_DBM(rssi) >= RTW89_MLSR_EXIT_2GHZ_THRESHOLD)
4567 decided_bands = BIT(RTW89_BAND_5G) | BIT(RTW89_BAND_6G);
4568 else if (RTW89_RSSI_RAW_TO_DBM(rssi) <= RTW89_MLSR_GOTO_2GHZ_THRESHOLD)
4569 decided_bands = BIT(RTW89_BAND_2G);
4570 else
4571 return;
4572
4573 usable_links = ieee80211_vif_usable_links(vif);
4574
4575 rtwvif_link = rtw89_get_designated_link(rtwvif);
4576 if (unlikely(!rtwvif_link))
4577 goto select;
4578
4579 chan = rtw89_chan_get(rtwdev, rtwvif_link->chanctx_idx);
4580 if (decided_bands & BIT(chan->band_type))
4581 return;
4582
4583 usable_links &= ~BIT(rtwvif_link->link_id);
4584
4585 select:
4586 rcu_read_lock();
4587
4588 for_each_set_bit(link_id, &usable_links, IEEE80211_MLD_MAX_NUM_LINKS) {
4589 struct ieee80211_bss_conf *link_conf;
4590 struct ieee80211_channel *channel;
4591 enum rtw89_band band;
4592
4593 link_conf = rcu_dereference(vif->link_conf[link_id]);
4594 if (unlikely(!link_conf))
4595 continue;
4596
4597 channel = link_conf->chanreq.oper.chan;
4598 if (unlikely(!channel))
4599 continue;
4600
4601 band = rtw89_nl80211_to_hw_band(channel->band);
4602 if (decided_bands & BIT(band)) {
4603 sel_link_id = link_id;
4604 break;
4605 }
4606 }
4607
4608 rcu_read_unlock();
4609
4610 if (sel_link_id == IEEE80211_MLD_MAX_NUM_LINKS)
4611 return;
4612
4613 rtw89_core_mlsr_switch(rtwdev, rtwvif, sel_link_id);
4614 }
4615
rtw89_core_mlo_track(struct rtw89_dev * rtwdev)4616 static void rtw89_core_mlo_track(struct rtw89_dev *rtwdev)
4617 {
4618 struct rtw89_hal *hal = &rtwdev->hal;
4619 struct ieee80211_vif *vif;
4620 struct rtw89_vif *rtwvif;
4621
4622 if (hal->disabled_dm_bitmap & BIT(RTW89_DM_MLO))
4623 return;
4624
4625 rtw89_for_each_rtwvif(rtwdev, rtwvif) {
4626 vif = rtwvif_to_vif(rtwvif);
4627 if (!vif->cfg.assoc || !ieee80211_vif_is_mld(vif))
4628 continue;
4629
4630 switch (rtwvif->mlo_mode) {
4631 case RTW89_MLO_MODE_MLSR:
4632 rtw89_core_mlsr_link_decision(rtwdev, rtwvif);
4633 break;
4634 default:
4635 break;
4636 }
4637 }
4638 }
4639
rtw89_track_ps_work(struct wiphy * wiphy,struct wiphy_work * work)4640 static void rtw89_track_ps_work(struct wiphy *wiphy, struct wiphy_work *work)
4641 {
4642 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
4643 track_ps_work.work);
4644 struct rtw89_vif *rtwvif;
4645
4646 lockdep_assert_wiphy(wiphy);
4647
4648 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags))
4649 return;
4650
4651 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
4652 return;
4653
4654 wiphy_delayed_work_queue(wiphy, &rtwdev->track_ps_work,
4655 RTW89_TRACK_PS_WORK_PERIOD);
4656
4657 rtw89_for_each_rtwvif(rtwdev, rtwvif)
4658 rtw89_traffic_stats_calc(rtwdev, &rtwvif->stats_ps,
4659 RTW89_TFC_INTERVAL_100MS);
4660
4661 if (rtwdev->scanning)
4662 return;
4663
4664 if (rtwdev->lps_enabled && !rtwdev->btc.lps)
4665 rtw89_enter_lps_track(rtwdev);
4666 }
4667
rtw89_track_work(struct wiphy * wiphy,struct wiphy_work * work)4668 static void rtw89_track_work(struct wiphy *wiphy, struct wiphy_work *work)
4669 {
4670 struct rtw89_dev *rtwdev = container_of(work, struct rtw89_dev,
4671 track_work.work);
4672 bool tfc_changed;
4673
4674 lockdep_assert_wiphy(wiphy);
4675
4676 if (test_bit(RTW89_FLAG_FORBIDDEN_TRACK_WORK, rtwdev->flags))
4677 return;
4678
4679 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
4680 return;
4681
4682 wiphy_delayed_work_queue(wiphy, &rtwdev->track_work,
4683 RTW89_TRACK_WORK_PERIOD);
4684
4685 tfc_changed = rtw89_traffic_stats_track(rtwdev);
4686 if (rtwdev->scanning)
4687 return;
4688
4689 rtw89_leave_lps(rtwdev);
4690
4691 if (tfc_changed) {
4692 rtw89_hci_recalc_int_mit(rtwdev);
4693 rtw89_btc_ntfy_wl_sta(rtwdev);
4694 }
4695 rtw89_mac_bf_monitor_track(rtwdev);
4696 rtw89_core_bcn_track(rtwdev);
4697 rtw89_phy_stat_track(rtwdev);
4698 rtw89_phy_env_monitor_track(rtwdev);
4699 rtw89_phy_dig(rtwdev);
4700 rtw89_core_rfk_track(rtwdev);
4701 rtw89_phy_ra_update(rtwdev);
4702 rtw89_phy_cfo_track(rtwdev);
4703 rtw89_phy_tx_path_div_track(rtwdev);
4704 rtw89_phy_antdiv_track(rtwdev);
4705 rtw89_phy_ul_tb_ctrl_track(rtwdev);
4706 rtw89_phy_edcca_track(rtwdev);
4707 rtw89_sar_track(rtwdev);
4708 rtw89_chanctx_track(rtwdev);
4709 rtw89_core_rfkill_poll(rtwdev, false);
4710 rtw89_core_mlo_track(rtwdev);
4711
4712 if (rtwdev->lps_enabled && !rtwdev->btc.lps)
4713 rtw89_enter_lps_track(rtwdev);
4714 }
4715
rtw89_core_acquire_bit_map(unsigned long * addr,unsigned long size)4716 u8 rtw89_core_acquire_bit_map(unsigned long *addr, unsigned long size)
4717 {
4718 unsigned long bit;
4719
4720 bit = find_first_zero_bit(addr, size);
4721 if (bit < size)
4722 set_bit(bit, addr);
4723
4724 return bit;
4725 }
4726
rtw89_core_release_bit_map(unsigned long * addr,u8 bit)4727 void rtw89_core_release_bit_map(unsigned long *addr, u8 bit)
4728 {
4729 clear_bit(bit, addr);
4730 }
4731
rtw89_core_release_all_bits_map(unsigned long * addr,unsigned int nbits)4732 void rtw89_core_release_all_bits_map(unsigned long *addr, unsigned int nbits)
4733 {
4734 bitmap_zero(addr, nbits);
4735 }
4736
rtw89_core_acquire_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u8 tid,u8 * cam_idx)4737 int rtw89_core_acquire_sta_ba_entry(struct rtw89_dev *rtwdev,
4738 struct rtw89_sta_link *rtwsta_link, u8 tid,
4739 u8 *cam_idx)
4740 {
4741 const struct rtw89_chip_info *chip = rtwdev->chip;
4742 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
4743 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
4744 u8 idx;
4745 int i;
4746
4747 lockdep_assert_wiphy(rtwdev->hw->wiphy);
4748
4749 idx = rtw89_core_acquire_bit_map(cam_info->ba_cam_map, chip->bacam_num);
4750 if (idx == chip->bacam_num) {
4751 /* allocate a static BA CAM to tid=0/5, so replace the existing
4752 * one if BA CAM is full. Hardware will process the original tid
4753 * automatically.
4754 */
4755 if (tid != 0 && tid != 5)
4756 return -ENOSPC;
4757
4758 for_each_set_bit(i, cam_info->ba_cam_map, chip->bacam_num) {
4759 tmp = &cam_info->ba_cam_entry[i];
4760 if (tmp->tid == 0 || tmp->tid == 5)
4761 continue;
4762
4763 idx = i;
4764 entry = tmp;
4765 list_del(&entry->list);
4766 break;
4767 }
4768
4769 if (!entry)
4770 return -ENOSPC;
4771 } else {
4772 entry = &cam_info->ba_cam_entry[idx];
4773 }
4774
4775 entry->tid = tid;
4776 list_add_tail(&entry->list, &rtwsta_link->ba_cam_list);
4777
4778 *cam_idx = idx;
4779
4780 return 0;
4781 }
4782
rtw89_core_release_sta_ba_entry(struct rtw89_dev * rtwdev,struct rtw89_sta_link * rtwsta_link,u8 tid,u8 * cam_idx)4783 int rtw89_core_release_sta_ba_entry(struct rtw89_dev *rtwdev,
4784 struct rtw89_sta_link *rtwsta_link, u8 tid,
4785 u8 *cam_idx)
4786 {
4787 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
4788 struct rtw89_ba_cam_entry *entry = NULL, *tmp;
4789 u8 idx;
4790
4791 lockdep_assert_wiphy(rtwdev->hw->wiphy);
4792
4793 list_for_each_entry_safe(entry, tmp, &rtwsta_link->ba_cam_list, list) {
4794 if (entry->tid != tid)
4795 continue;
4796
4797 idx = entry - cam_info->ba_cam_entry;
4798 list_del(&entry->list);
4799
4800 rtw89_core_release_bit_map(cam_info->ba_cam_map, idx);
4801 *cam_idx = idx;
4802 return 0;
4803 }
4804
4805 return -ENOENT;
4806 }
4807
4808 #define RTW89_TYPE_MAPPING(_type) \
4809 case NL80211_IFTYPE_ ## _type: \
4810 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_ ## _type; \
4811 break
rtw89_vif_type_mapping(struct rtw89_vif_link * rtwvif_link,bool assoc)4812 void rtw89_vif_type_mapping(struct rtw89_vif_link *rtwvif_link, bool assoc)
4813 {
4814 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4815 const struct ieee80211_bss_conf *bss_conf;
4816
4817 switch (vif->type) {
4818 case NL80211_IFTYPE_STATION:
4819 if (vif->p2p)
4820 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_CLIENT;
4821 else
4822 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_STATION;
4823 break;
4824 case NL80211_IFTYPE_AP:
4825 if (vif->p2p)
4826 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_P2P_GO;
4827 else
4828 rtwvif_link->wifi_role = RTW89_WIFI_ROLE_AP;
4829 break;
4830 RTW89_TYPE_MAPPING(ADHOC);
4831 RTW89_TYPE_MAPPING(MONITOR);
4832 RTW89_TYPE_MAPPING(MESH_POINT);
4833 default:
4834 WARN_ON(1);
4835 break;
4836 }
4837
4838 switch (vif->type) {
4839 case NL80211_IFTYPE_AP:
4840 case NL80211_IFTYPE_MESH_POINT:
4841 rtwvif_link->net_type = RTW89_NET_TYPE_AP_MODE;
4842 rtwvif_link->self_role = RTW89_SELF_ROLE_AP;
4843 break;
4844 case NL80211_IFTYPE_ADHOC:
4845 rtwvif_link->net_type = RTW89_NET_TYPE_AD_HOC;
4846 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT;
4847 break;
4848 case NL80211_IFTYPE_STATION:
4849 if (assoc) {
4850 rtwvif_link->net_type = RTW89_NET_TYPE_INFRA;
4851
4852 rcu_read_lock();
4853 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
4854 rtwvif_link->trigger = bss_conf->he_support;
4855 rcu_read_unlock();
4856 } else {
4857 rtwvif_link->net_type = RTW89_NET_TYPE_NO_LINK;
4858 rtwvif_link->trigger = false;
4859 }
4860 rtwvif_link->self_role = RTW89_SELF_ROLE_CLIENT;
4861 rtwvif_link->addr_cam.sec_ent_mode = RTW89_ADDR_CAM_SEC_NORMAL;
4862 break;
4863 case NL80211_IFTYPE_MONITOR:
4864 break;
4865 default:
4866 WARN_ON(1);
4867 break;
4868 }
4869 }
4870
rtw89_core_sta_link_add(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4871 int rtw89_core_sta_link_add(struct rtw89_dev *rtwdev,
4872 struct rtw89_vif_link *rtwvif_link,
4873 struct rtw89_sta_link *rtwsta_link)
4874 {
4875 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4876 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
4877 struct rtw89_hal *hal = &rtwdev->hal;
4878 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
4879 int i;
4880 int ret;
4881
4882 rtwsta_link->prev_rssi = 0;
4883 INIT_LIST_HEAD(&rtwsta_link->ba_cam_list);
4884 ewma_rssi_init(&rtwsta_link->avg_rssi);
4885 ewma_snr_init(&rtwsta_link->avg_snr);
4886 ewma_evm_init(&rtwsta_link->evm_1ss);
4887 for (i = 0; i < ant_num; i++) {
4888 ewma_rssi_init(&rtwsta_link->rssi[i]);
4889 ewma_evm_init(&rtwsta_link->evm_min[i]);
4890 ewma_evm_init(&rtwsta_link->evm_max[i]);
4891 }
4892
4893 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
4894 /* must do rtw89_reg_6ghz_recalc() before rfk channel */
4895 ret = rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, true);
4896 if (ret)
4897 return ret;
4898
4899 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
4900 BTC_ROLE_MSTS_STA_CONN_START);
4901 rtw89_chip_rfk_channel(rtwdev, rtwvif_link);
4902
4903 if (vif->p2p) {
4904 rtw89_mac_get_tx_retry_limit(rtwdev, rtwsta_link,
4905 &rtwsta_link->tx_retry);
4906 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false, 60);
4907 }
4908 rtw89_phy_dig_suspend(rtwdev);
4909 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
4910 ret = rtw89_mac_set_macid_pause(rtwdev, rtwsta_link->mac_id, false);
4911 if (ret) {
4912 rtw89_warn(rtwdev, "failed to send h2c macid pause\n");
4913 return ret;
4914 }
4915
4916 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link,
4917 RTW89_ROLE_CREATE);
4918 if (ret) {
4919 rtw89_warn(rtwdev, "failed to send h2c role info\n");
4920 return ret;
4921 }
4922
4923 ret = rtw89_chip_h2c_default_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4924 if (ret)
4925 return ret;
4926
4927 ret = rtw89_chip_h2c_default_dmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4928 if (ret)
4929 return ret;
4930 }
4931
4932 return 0;
4933 }
4934
rtw89_core_sta_link_disassoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4935 int rtw89_core_sta_link_disassoc(struct rtw89_dev *rtwdev,
4936 struct rtw89_vif_link *rtwvif_link,
4937 struct rtw89_sta_link *rtwsta_link)
4938 {
4939 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4940
4941 rtw89_assoc_link_clr(rtwsta_link);
4942
4943 if (vif->type == NL80211_IFTYPE_STATION) {
4944 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, false);
4945 rtw89_core_bcn_track_reset(rtwdev);
4946 }
4947
4948 if (rtwvif_link->wifi_role == RTW89_WIFI_ROLE_P2P_CLIENT)
4949 rtw89_p2p_noa_once_deinit(rtwvif_link);
4950
4951 return 0;
4952 }
4953
rtw89_core_sta_link_disconnect(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)4954 int rtw89_core_sta_link_disconnect(struct rtw89_dev *rtwdev,
4955 struct rtw89_vif_link *rtwvif_link,
4956 struct rtw89_sta_link *rtwsta_link)
4957 {
4958 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
4959 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
4960 int ret;
4961
4962 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, true);
4963 rtw89_mac_bf_disassoc(rtwdev, rtwvif_link, rtwsta_link);
4964
4965 if (vif->type == NL80211_IFTYPE_AP || sta->tdls)
4966 rtw89_cam_deinit_addr_cam(rtwdev, &rtwsta_link->addr_cam);
4967 if (sta->tdls)
4968 rtw89_cam_deinit_bssid_cam(rtwdev, &rtwsta_link->bssid_cam);
4969
4970 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
4971 rtw89_vif_type_mapping(rtwvif_link, false);
4972 rtw89_fw_release_general_pkt_list_vif(rtwdev, rtwvif_link, true);
4973 }
4974
4975 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
4976 if (ret) {
4977 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
4978 return ret;
4979 }
4980
4981 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, true);
4982 if (ret) {
4983 rtw89_warn(rtwdev, "failed to send h2c join info\n");
4984 return ret;
4985 }
4986
4987 /* update cam aid mac_id net_type */
4988 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL,
4989 RTW89_ROLE_CON_DISCONN);
4990 if (ret) {
4991 rtw89_warn(rtwdev, "failed to send h2c cam\n");
4992 return ret;
4993 }
4994
4995 return ret;
4996 }
4997
rtw89_sta_link_can_er(struct rtw89_dev * rtwdev,struct ieee80211_bss_conf * bss_conf,struct ieee80211_link_sta * link_sta)4998 static bool rtw89_sta_link_can_er(struct rtw89_dev *rtwdev,
4999 struct ieee80211_bss_conf *bss_conf,
5000 struct ieee80211_link_sta *link_sta)
5001 {
5002 if (!bss_conf->he_support ||
5003 bss_conf->he_oper.params & IEEE80211_HE_OPERATION_ER_SU_DISABLE)
5004 return false;
5005
5006 if (rtwdev->chip->chip_id == RTL8852C &&
5007 rtw89_sta_link_has_su_mu_4xhe08(link_sta) &&
5008 !rtw89_sta_link_has_er_su_4xhe08(link_sta))
5009 return false;
5010
5011 return true;
5012 }
5013
rtw89_core_sta_link_assoc(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5014 int rtw89_core_sta_link_assoc(struct rtw89_dev *rtwdev,
5015 struct rtw89_vif_link *rtwvif_link,
5016 struct rtw89_sta_link *rtwsta_link)
5017 {
5018 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5019 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
5020 struct rtw89_bssid_cam_entry *bssid_cam = rtw89_get_bssid_cam_of(rtwvif_link,
5021 rtwsta_link);
5022 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
5023 rtwvif_link->chanctx_idx);
5024 struct ieee80211_link_sta *link_sta;
5025 int ret;
5026
5027 if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
5028 if (sta->tdls) {
5029 rcu_read_lock();
5030
5031 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
5032 ret = rtw89_cam_init_bssid_cam(rtwdev, rtwvif_link, bssid_cam,
5033 link_sta->addr);
5034 if (ret) {
5035 rtw89_warn(rtwdev, "failed to send h2c init bssid cam for TDLS\n");
5036 rcu_read_unlock();
5037 return ret;
5038 }
5039
5040 rcu_read_unlock();
5041 }
5042
5043 ret = rtw89_cam_init_addr_cam(rtwdev, &rtwsta_link->addr_cam, bssid_cam);
5044 if (ret) {
5045 rtw89_warn(rtwdev, "failed to send h2c init addr cam\n");
5046 return ret;
5047 }
5048 }
5049
5050 ret = rtw89_chip_h2c_assoc_cmac_tbl(rtwdev, rtwvif_link, rtwsta_link);
5051 if (ret) {
5052 rtw89_warn(rtwdev, "failed to send h2c cmac table\n");
5053 return ret;
5054 }
5055
5056 ret = rtw89_fw_h2c_join_info(rtwdev, rtwvif_link, rtwsta_link, false);
5057 if (ret) {
5058 rtw89_warn(rtwdev, "failed to send h2c join info\n");
5059 return ret;
5060 }
5061
5062 /* update cam aid mac_id net_type */
5063 ret = rtw89_fw_h2c_cam(rtwdev, rtwvif_link, rtwsta_link, NULL,
5064 RTW89_ROLE_CON_DISCONN);
5065 if (ret) {
5066 rtw89_warn(rtwdev, "failed to send h2c cam\n");
5067 return ret;
5068 }
5069
5070 rtw89_phy_ra_assoc(rtwdev, rtwsta_link);
5071 rtw89_mac_bf_assoc(rtwdev, rtwvif_link, rtwsta_link);
5072 rtw89_mac_bf_monitor_calc(rtwdev, rtwsta_link, false);
5073
5074 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
5075 struct ieee80211_bss_conf *bss_conf;
5076
5077 rcu_read_lock();
5078
5079 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
5080 link_sta = rtw89_sta_rcu_dereference_link(rtwsta_link, true);
5081 rtwsta_link->er_cap = rtw89_sta_link_can_er(rtwdev, bss_conf, link_sta);
5082
5083 rcu_read_unlock();
5084
5085 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
5086 BTC_ROLE_MSTS_STA_CONN_END);
5087 rtw89_core_get_no_ul_ofdma_htc(rtwdev, &rtwsta_link->htc_template, chan);
5088 rtw89_phy_ul_tb_assoc(rtwdev, rtwvif_link);
5089 rtw89_core_bcn_track_assoc(rtwdev, rtwvif_link);
5090
5091 ret = rtw89_fw_h2c_general_pkt(rtwdev, rtwvif_link, rtwsta_link->mac_id);
5092 if (ret) {
5093 rtw89_warn(rtwdev, "failed to send h2c general packet\n");
5094 return ret;
5095 }
5096
5097 rtw89_fw_h2c_set_bcn_fltr_cfg(rtwdev, rtwvif_link, true);
5098
5099 if (vif->p2p)
5100 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false,
5101 rtwsta_link->tx_retry);
5102 rtw89_phy_dig_resume(rtwdev, false);
5103 }
5104
5105 rtw89_assoc_link_set(rtwsta_link);
5106 return ret;
5107 }
5108
rtw89_core_sta_link_remove(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,struct rtw89_sta_link * rtwsta_link)5109 int rtw89_core_sta_link_remove(struct rtw89_dev *rtwdev,
5110 struct rtw89_vif_link *rtwvif_link,
5111 struct rtw89_sta_link *rtwsta_link)
5112 {
5113 const struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
5114 const struct ieee80211_sta *sta = rtwsta_link_to_sta(rtwsta_link);
5115 int ret;
5116
5117 if (vif->type == NL80211_IFTYPE_STATION && !sta->tdls) {
5118 rtw89_reg_6ghz_recalc(rtwdev, rtwvif_link, false);
5119 rtw89_btc_ntfy_role_info(rtwdev, rtwvif_link, rtwsta_link,
5120 BTC_ROLE_MSTS_STA_DIS_CONN);
5121
5122 if (vif->p2p)
5123 rtw89_mac_set_tx_retry_limit(rtwdev, rtwsta_link, false,
5124 rtwsta_link->tx_retry);
5125 } else if (vif->type == NL80211_IFTYPE_AP || sta->tdls) {
5126 ret = rtw89_fw_h2c_role_maintain(rtwdev, rtwvif_link, rtwsta_link,
5127 RTW89_ROLE_REMOVE);
5128 if (ret) {
5129 rtw89_warn(rtwdev, "failed to send h2c role info\n");
5130 return ret;
5131 }
5132 }
5133
5134 return 0;
5135 }
5136
_rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_cfg * tid_conf)5137 static void _rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
5138 struct ieee80211_sta *sta,
5139 struct cfg80211_tid_cfg *tid_conf)
5140 {
5141 struct ieee80211_txq *txq;
5142 struct rtw89_txq *rtwtxq;
5143 u32 mask = tid_conf->mask;
5144 u8 tids = tid_conf->tids;
5145 int tids_nbit = BITS_PER_BYTE;
5146 int i;
5147
5148 for (i = 0; i < tids_nbit; i++, tids >>= 1) {
5149 if (!tids)
5150 break;
5151
5152 if (!(tids & BIT(0)))
5153 continue;
5154
5155 txq = sta->txq[i];
5156 rtwtxq = (struct rtw89_txq *)txq->drv_priv;
5157
5158 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL)) {
5159 if (tid_conf->ampdu == NL80211_TID_CONFIG_ENABLE) {
5160 clear_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
5161 } else {
5162 if (test_bit(RTW89_TXQ_F_AMPDU, &rtwtxq->flags))
5163 ieee80211_stop_tx_ba_session(sta, txq->tid);
5164 spin_lock_bh(&rtwdev->ba_lock);
5165 list_del_init(&rtwtxq->list);
5166 set_bit(RTW89_TXQ_F_FORBID_BA, &rtwtxq->flags);
5167 spin_unlock_bh(&rtwdev->ba_lock);
5168 }
5169 }
5170
5171 if (mask & BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL) && tids == 0xff) {
5172 if (tid_conf->amsdu == NL80211_TID_CONFIG_ENABLE)
5173 sta->max_amsdu_subframes = 0;
5174 else
5175 sta->max_amsdu_subframes = 1;
5176 }
5177 }
5178 }
5179
rtw89_core_set_tid_config(struct rtw89_dev * rtwdev,struct ieee80211_sta * sta,struct cfg80211_tid_config * tid_config)5180 void rtw89_core_set_tid_config(struct rtw89_dev *rtwdev,
5181 struct ieee80211_sta *sta,
5182 struct cfg80211_tid_config *tid_config)
5183 {
5184 int i;
5185
5186 for (i = 0; i < tid_config->n_tid_conf; i++)
5187 _rtw89_core_set_tid_config(rtwdev, sta,
5188 &tid_config->tid_conf[i]);
5189 }
5190
rtw89_init_ht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_ht_cap * ht_cap)5191 static void rtw89_init_ht_cap(struct rtw89_dev *rtwdev,
5192 struct ieee80211_sta_ht_cap *ht_cap)
5193 {
5194 static const __le16 highest[RF_PATH_MAX] = {
5195 cpu_to_le16(150), cpu_to_le16(300), cpu_to_le16(450), cpu_to_le16(600),
5196 };
5197 struct rtw89_hal *hal = &rtwdev->hal;
5198 u8 nss = hal->rx_nss;
5199 int i;
5200
5201 ht_cap->ht_supported = true;
5202 ht_cap->cap = 0;
5203 ht_cap->cap |= IEEE80211_HT_CAP_SGI_20 |
5204 IEEE80211_HT_CAP_MAX_AMSDU |
5205 IEEE80211_HT_CAP_TX_STBC |
5206 (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT);
5207 ht_cap->cap |= IEEE80211_HT_CAP_LDPC_CODING;
5208 ht_cap->cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
5209 IEEE80211_HT_CAP_DSSSCCK40 |
5210 IEEE80211_HT_CAP_SGI_40;
5211 ht_cap->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
5212 ht_cap->ampdu_density = IEEE80211_HT_MPDU_DENSITY_NONE;
5213 ht_cap->mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
5214 for (i = 0; i < nss; i++)
5215 ht_cap->mcs.rx_mask[i] = 0xFF;
5216 ht_cap->mcs.rx_mask[4] = 0x01;
5217 ht_cap->mcs.rx_highest = highest[nss - 1];
5218 }
5219
rtw89_init_vht_cap(struct rtw89_dev * rtwdev,struct ieee80211_sta_vht_cap * vht_cap)5220 static void rtw89_init_vht_cap(struct rtw89_dev *rtwdev,
5221 struct ieee80211_sta_vht_cap *vht_cap)
5222 {
5223 static const __le16 highest_bw80[RF_PATH_MAX] = {
5224 cpu_to_le16(433), cpu_to_le16(867), cpu_to_le16(1300), cpu_to_le16(1733),
5225 };
5226 static const __le16 highest_bw160[RF_PATH_MAX] = {
5227 cpu_to_le16(867), cpu_to_le16(1733), cpu_to_le16(2600), cpu_to_le16(3467),
5228 };
5229 const struct rtw89_chip_info *chip = rtwdev->chip;
5230 const __le16 *highest = chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160) ?
5231 highest_bw160 : highest_bw80;
5232 struct rtw89_hal *hal = &rtwdev->hal;
5233 u16 tx_mcs_map = 0, rx_mcs_map = 0;
5234 u8 sts_cap = 3;
5235 int i;
5236
5237 for (i = 0; i < 8; i++) {
5238 if (i < hal->tx_nss)
5239 tx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
5240 else
5241 tx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
5242 if (i < hal->rx_nss)
5243 rx_mcs_map |= IEEE80211_VHT_MCS_SUPPORT_0_9 << (i * 2);
5244 else
5245 rx_mcs_map |= IEEE80211_VHT_MCS_NOT_SUPPORTED << (i * 2);
5246 }
5247
5248 vht_cap->vht_supported = true;
5249 vht_cap->cap = chip->max_vht_mpdu_cap |
5250 IEEE80211_VHT_CAP_SHORT_GI_80 |
5251 IEEE80211_VHT_CAP_RXSTBC_1 |
5252 IEEE80211_VHT_CAP_HTC_VHT |
5253 IEEE80211_VHT_CAP_MAX_A_MPDU_LENGTH_EXPONENT_MASK |
5254 0;
5255 vht_cap->cap |= IEEE80211_VHT_CAP_TXSTBC;
5256 vht_cap->cap |= IEEE80211_VHT_CAP_RXLDPC;
5257 vht_cap->cap |= IEEE80211_VHT_CAP_MU_BEAMFORMEE_CAPABLE |
5258 IEEE80211_VHT_CAP_SU_BEAMFORMEE_CAPABLE;
5259 vht_cap->cap |= sts_cap << IEEE80211_VHT_CAP_BEAMFORMEE_STS_SHIFT;
5260 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
5261 vht_cap->cap |= IEEE80211_VHT_CAP_SUPP_CHAN_WIDTH_160MHZ |
5262 IEEE80211_VHT_CAP_SHORT_GI_160;
5263 vht_cap->vht_mcs.rx_mcs_map = cpu_to_le16(rx_mcs_map);
5264 vht_cap->vht_mcs.tx_mcs_map = cpu_to_le16(tx_mcs_map);
5265 vht_cap->vht_mcs.rx_highest = highest[hal->rx_nss - 1];
5266 vht_cap->vht_mcs.tx_highest = highest[hal->tx_nss - 1];
5267
5268 if (ieee80211_hw_check(rtwdev->hw, SUPPORTS_VHT_EXT_NSS_BW))
5269 vht_cap->vht_mcs.tx_highest |=
5270 cpu_to_le16(IEEE80211_VHT_EXT_NSS_BW_CAPABLE);
5271 }
5272
rtw89_init_he_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)5273 static void rtw89_init_he_cap(struct rtw89_dev *rtwdev,
5274 enum nl80211_band band,
5275 enum nl80211_iftype iftype,
5276 struct ieee80211_sband_iftype_data *iftype_data)
5277 {
5278 const struct rtw89_chip_info *chip = rtwdev->chip;
5279 struct rtw89_hal *hal = &rtwdev->hal;
5280 bool no_ng16 = (chip->chip_id == RTL8852A && hal->cv == CHIP_CBV) ||
5281 (chip->chip_id == RTL8852B && hal->cv == CHIP_CAV);
5282 struct ieee80211_sta_he_cap *he_cap;
5283 int nss = hal->rx_nss;
5284 u8 *mac_cap_info;
5285 u8 *phy_cap_info;
5286 u16 mcs_map = 0;
5287 int i;
5288
5289 for (i = 0; i < 8; i++) {
5290 if (i < nss)
5291 mcs_map |= IEEE80211_HE_MCS_SUPPORT_0_11 << (i * 2);
5292 else
5293 mcs_map |= IEEE80211_HE_MCS_NOT_SUPPORTED << (i * 2);
5294 }
5295
5296 he_cap = &iftype_data->he_cap;
5297 mac_cap_info = he_cap->he_cap_elem.mac_cap_info;
5298 phy_cap_info = he_cap->he_cap_elem.phy_cap_info;
5299
5300 he_cap->has_he = true;
5301 mac_cap_info[0] = IEEE80211_HE_MAC_CAP0_HTC_HE;
5302 if (iftype == NL80211_IFTYPE_STATION)
5303 mac_cap_info[1] = IEEE80211_HE_MAC_CAP1_TF_MAC_PAD_DUR_16US;
5304 mac_cap_info[2] = IEEE80211_HE_MAC_CAP2_ALL_ACK |
5305 IEEE80211_HE_MAC_CAP2_BSR;
5306 mac_cap_info[3] = IEEE80211_HE_MAC_CAP3_MAX_AMPDU_LEN_EXP_EXT_2;
5307 if (iftype == NL80211_IFTYPE_AP)
5308 mac_cap_info[3] |= IEEE80211_HE_MAC_CAP3_OMI_CONTROL;
5309 mac_cap_info[4] = IEEE80211_HE_MAC_CAP4_OPS |
5310 IEEE80211_HE_MAC_CAP4_AMSDU_IN_AMPDU;
5311 if (iftype == NL80211_IFTYPE_STATION)
5312 mac_cap_info[5] = IEEE80211_HE_MAC_CAP5_HT_VHT_TRIG_FRAME_RX;
5313 if (band == NL80211_BAND_2GHZ) {
5314 phy_cap_info[0] =
5315 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_IN_2G;
5316 } else {
5317 phy_cap_info[0] =
5318 IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_40MHZ_80MHZ_IN_5G;
5319 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
5320 phy_cap_info[0] |= IEEE80211_HE_PHY_CAP0_CHANNEL_WIDTH_SET_160MHZ_IN_5G;
5321 }
5322 phy_cap_info[1] = IEEE80211_HE_PHY_CAP1_DEVICE_CLASS_A |
5323 IEEE80211_HE_PHY_CAP1_LDPC_CODING_IN_PAYLOAD |
5324 IEEE80211_HE_PHY_CAP1_HE_LTF_AND_GI_FOR_HE_PPDUS_0_8US;
5325 phy_cap_info[2] = IEEE80211_HE_PHY_CAP2_NDP_4x_LTF_AND_3_2US |
5326 IEEE80211_HE_PHY_CAP2_STBC_TX_UNDER_80MHZ |
5327 IEEE80211_HE_PHY_CAP2_STBC_RX_UNDER_80MHZ |
5328 IEEE80211_HE_PHY_CAP2_DOPPLER_TX;
5329 phy_cap_info[3] = IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_RX_16_QAM;
5330 if (iftype == NL80211_IFTYPE_STATION)
5331 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_DCM_MAX_CONST_TX_16_QAM |
5332 IEEE80211_HE_PHY_CAP3_DCM_MAX_TX_NSS_2;
5333 if (iftype == NL80211_IFTYPE_AP)
5334 phy_cap_info[3] |= IEEE80211_HE_PHY_CAP3_RX_PARTIAL_BW_SU_IN_20MHZ_MU;
5335 phy_cap_info[4] = IEEE80211_HE_PHY_CAP4_SU_BEAMFORMEE |
5336 IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_UNDER_80MHZ_4;
5337 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
5338 phy_cap_info[4] |= IEEE80211_HE_PHY_CAP4_BEAMFORMEE_MAX_STS_ABOVE_80MHZ_4;
5339 phy_cap_info[5] = no_ng16 ? 0 :
5340 IEEE80211_HE_PHY_CAP5_NG16_SU_FEEDBACK |
5341 IEEE80211_HE_PHY_CAP5_NG16_MU_FEEDBACK;
5342 phy_cap_info[6] = IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_42_SU |
5343 IEEE80211_HE_PHY_CAP6_CODEBOOK_SIZE_75_MU |
5344 IEEE80211_HE_PHY_CAP6_TRIG_SU_BEAMFORMING_FB |
5345 IEEE80211_HE_PHY_CAP6_PARTIAL_BW_EXT_RANGE;
5346 phy_cap_info[7] = IEEE80211_HE_PHY_CAP7_POWER_BOOST_FACTOR_SUPP |
5347 IEEE80211_HE_PHY_CAP7_HE_SU_MU_PPDU_4XLTF_AND_08_US_GI |
5348 IEEE80211_HE_PHY_CAP7_MAX_NC_1;
5349 phy_cap_info[8] = IEEE80211_HE_PHY_CAP8_HE_ER_SU_PPDU_4XLTF_AND_08_US_GI |
5350 IEEE80211_HE_PHY_CAP8_HE_ER_SU_1XLTF_AND_08_US_GI |
5351 IEEE80211_HE_PHY_CAP8_DCM_MAX_RU_996;
5352 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
5353 phy_cap_info[8] |= IEEE80211_HE_PHY_CAP8_20MHZ_IN_160MHZ_HE_PPDU |
5354 IEEE80211_HE_PHY_CAP8_80MHZ_IN_160MHZ_HE_PPDU;
5355 phy_cap_info[9] = IEEE80211_HE_PHY_CAP9_LONGER_THAN_16_SIGB_OFDM_SYM |
5356 IEEE80211_HE_PHY_CAP9_RX_1024_QAM_LESS_THAN_242_TONE_RU |
5357 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_COMP_SIGB |
5358 IEEE80211_HE_PHY_CAP9_RX_FULL_BW_SU_USING_MU_WITH_NON_COMP_SIGB |
5359 u8_encode_bits(IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_16US,
5360 IEEE80211_HE_PHY_CAP9_NOMINAL_PKT_PADDING_MASK);
5361 if (iftype == NL80211_IFTYPE_STATION)
5362 phy_cap_info[9] |= IEEE80211_HE_PHY_CAP9_TX_1024_QAM_LESS_THAN_242_TONE_RU;
5363 he_cap->he_mcs_nss_supp.rx_mcs_80 = cpu_to_le16(mcs_map);
5364 he_cap->he_mcs_nss_supp.tx_mcs_80 = cpu_to_le16(mcs_map);
5365 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160)) {
5366 he_cap->he_mcs_nss_supp.rx_mcs_160 = cpu_to_le16(mcs_map);
5367 he_cap->he_mcs_nss_supp.tx_mcs_160 = cpu_to_le16(mcs_map);
5368 }
5369
5370 if (band == NL80211_BAND_6GHZ) {
5371 __le16 capa;
5372
5373 capa = le16_encode_bits(IEEE80211_HT_MPDU_DENSITY_NONE,
5374 IEEE80211_HE_6GHZ_CAP_MIN_MPDU_START) |
5375 le16_encode_bits(IEEE80211_VHT_MAX_AMPDU_1024K,
5376 IEEE80211_HE_6GHZ_CAP_MAX_AMPDU_LEN_EXP) |
5377 le16_encode_bits(chip->max_vht_mpdu_cap,
5378 IEEE80211_HE_6GHZ_CAP_MAX_MPDU_LEN);
5379 iftype_data->he_6ghz_capa.capa = capa;
5380 }
5381 }
5382
rtw89_init_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,enum nl80211_iftype iftype,struct ieee80211_sband_iftype_data * iftype_data)5383 static void rtw89_init_eht_cap(struct rtw89_dev *rtwdev,
5384 enum nl80211_band band,
5385 enum nl80211_iftype iftype,
5386 struct ieee80211_sband_iftype_data *iftype_data)
5387 {
5388 const struct rtw89_chip_info *chip = rtwdev->chip;
5389 struct ieee80211_eht_cap_elem_fixed *eht_cap_elem;
5390 struct ieee80211_eht_mcs_nss_supp *eht_nss;
5391 struct ieee80211_sta_eht_cap *eht_cap;
5392 struct rtw89_hal *hal = &rtwdev->hal;
5393 bool support_mcs_12_13 = true;
5394 bool support_320mhz = false;
5395 u8 val, val_mcs13;
5396 int sts = 8;
5397
5398 if (chip->chip_gen == RTW89_CHIP_AX || hal->no_eht)
5399 return;
5400
5401 if (hal->no_mcs_12_13)
5402 support_mcs_12_13 = false;
5403
5404 if (band == NL80211_BAND_6GHZ &&
5405 chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_320))
5406 support_320mhz = true;
5407
5408 eht_cap = &iftype_data->eht_cap;
5409 eht_cap_elem = &eht_cap->eht_cap_elem;
5410 eht_nss = &eht_cap->eht_mcs_nss_supp;
5411
5412 eht_cap->has_eht = true;
5413
5414 eht_cap_elem->mac_cap_info[0] =
5415 u8_encode_bits(chip->max_eht_mpdu_cap,
5416 IEEE80211_EHT_MAC_CAP0_MAX_MPDU_LEN_MASK);
5417 eht_cap_elem->mac_cap_info[1] = 0;
5418
5419 eht_cap_elem->phy_cap_info[0] =
5420 IEEE80211_EHT_PHY_CAP0_NDP_4_EHT_LFT_32_GI |
5421 IEEE80211_EHT_PHY_CAP0_SU_BEAMFORMEE;
5422 if (support_320mhz)
5423 eht_cap_elem->phy_cap_info[0] |=
5424 IEEE80211_EHT_PHY_CAP0_320MHZ_IN_6GHZ;
5425
5426 eht_cap_elem->phy_cap_info[0] |=
5427 u8_encode_bits(u8_get_bits(sts - 1, BIT(0)),
5428 IEEE80211_EHT_PHY_CAP0_BEAMFORMEE_SS_80MHZ_MASK);
5429 eht_cap_elem->phy_cap_info[1] =
5430 u8_encode_bits(u8_get_bits(sts - 1, GENMASK(2, 1)),
5431 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_80MHZ_MASK) |
5432 u8_encode_bits(sts - 1,
5433 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_160MHZ_MASK);
5434 if (support_320mhz)
5435 eht_cap_elem->phy_cap_info[1] |=
5436 u8_encode_bits(sts - 1,
5437 IEEE80211_EHT_PHY_CAP1_BEAMFORMEE_SS_320MHZ_MASK);
5438
5439 eht_cap_elem->phy_cap_info[2] = 0;
5440
5441 eht_cap_elem->phy_cap_info[3] =
5442 IEEE80211_EHT_PHY_CAP3_CODEBOOK_4_2_SU_FDBK |
5443 IEEE80211_EHT_PHY_CAP3_CODEBOOK_7_5_MU_FDBK |
5444 IEEE80211_EHT_PHY_CAP3_TRIG_SU_BF_FDBK |
5445 IEEE80211_EHT_PHY_CAP3_TRIG_MU_BF_PART_BW_FDBK;
5446
5447 eht_cap_elem->phy_cap_info[4] =
5448 IEEE80211_EHT_PHY_CAP4_POWER_BOOST_FACT_SUPP |
5449 u8_encode_bits(1, IEEE80211_EHT_PHY_CAP4_MAX_NC_MASK);
5450
5451 eht_cap_elem->phy_cap_info[5] =
5452 u8_encode_bits(IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_20US,
5453 IEEE80211_EHT_PHY_CAP5_COMMON_NOMINAL_PKT_PAD_MASK);
5454
5455 eht_cap_elem->phy_cap_info[6] = 0;
5456 eht_cap_elem->phy_cap_info[7] = 0;
5457 eht_cap_elem->phy_cap_info[8] = 0;
5458
5459 val = u8_encode_bits(hal->rx_nss, IEEE80211_EHT_MCS_NSS_RX) |
5460 u8_encode_bits(hal->tx_nss, IEEE80211_EHT_MCS_NSS_TX);
5461 val_mcs13 = support_mcs_12_13 ? val : 0;
5462
5463 eht_nss->bw._80.rx_tx_mcs9_max_nss = val;
5464 eht_nss->bw._80.rx_tx_mcs11_max_nss = val;
5465 eht_nss->bw._80.rx_tx_mcs13_max_nss = val_mcs13;
5466 eht_nss->bw._160.rx_tx_mcs9_max_nss = val;
5467 eht_nss->bw._160.rx_tx_mcs11_max_nss = val;
5468 eht_nss->bw._160.rx_tx_mcs13_max_nss = val_mcs13;
5469 if (support_320mhz) {
5470 eht_nss->bw._320.rx_tx_mcs9_max_nss = val;
5471 eht_nss->bw._320.rx_tx_mcs11_max_nss = val;
5472 eht_nss->bw._320.rx_tx_mcs13_max_nss = val_mcs13;
5473 }
5474 }
5475
5476 #define RTW89_SBAND_IFTYPES_NR 2
5477
rtw89_init_he_eht_cap(struct rtw89_dev * rtwdev,enum nl80211_band band,struct ieee80211_supported_band * sband)5478 static int rtw89_init_he_eht_cap(struct rtw89_dev *rtwdev,
5479 enum nl80211_band band,
5480 struct ieee80211_supported_band *sband)
5481 {
5482 struct ieee80211_sband_iftype_data *iftype_data;
5483 enum nl80211_iftype iftype;
5484 int idx = 0;
5485
5486 iftype_data = devm_kcalloc(rtwdev->dev, RTW89_SBAND_IFTYPES_NR,
5487 sizeof(*iftype_data), GFP_KERNEL);
5488 if (!iftype_data)
5489 return -ENOMEM;
5490
5491 for (iftype = 0; iftype < NUM_NL80211_IFTYPES; iftype++) {
5492 switch (iftype) {
5493 case NL80211_IFTYPE_STATION:
5494 case NL80211_IFTYPE_AP:
5495 break;
5496 default:
5497 continue;
5498 }
5499
5500 if (idx >= RTW89_SBAND_IFTYPES_NR) {
5501 rtw89_warn(rtwdev, "run out of iftype_data\n");
5502 break;
5503 }
5504
5505 iftype_data[idx].types_mask = BIT(iftype);
5506
5507 rtw89_init_he_cap(rtwdev, band, iftype, &iftype_data[idx]);
5508 rtw89_init_eht_cap(rtwdev, band, iftype, &iftype_data[idx]);
5509
5510 idx++;
5511 }
5512
5513 _ieee80211_set_sband_iftype_data(sband, iftype_data, idx);
5514 return 0;
5515 }
5516
5517 static struct ieee80211_supported_band *
rtw89_core_sband_dup(struct rtw89_dev * rtwdev,const struct ieee80211_supported_band * sband)5518 rtw89_core_sband_dup(struct rtw89_dev *rtwdev,
5519 const struct ieee80211_supported_band *sband)
5520 {
5521 struct ieee80211_supported_band *dup;
5522
5523 dup = devm_kmemdup(rtwdev->dev, sband, sizeof(*sband), GFP_KERNEL);
5524 if (!dup)
5525 return NULL;
5526
5527 dup->channels = devm_kmemdup(rtwdev->dev, sband->channels,
5528 sizeof(*sband->channels) * sband->n_channels,
5529 GFP_KERNEL);
5530 if (!dup->channels)
5531 return NULL;
5532
5533 dup->bitrates = devm_kmemdup(rtwdev->dev, sband->bitrates,
5534 sizeof(*sband->bitrates) * sband->n_bitrates,
5535 GFP_KERNEL);
5536 if (!dup->bitrates)
5537 return NULL;
5538
5539 return dup;
5540 }
5541
rtw89_core_set_supported_band(struct rtw89_dev * rtwdev)5542 static int rtw89_core_set_supported_band(struct rtw89_dev *rtwdev)
5543 {
5544 struct ieee80211_hw *hw = rtwdev->hw;
5545 struct ieee80211_supported_band *sband;
5546 u8 support_bands = rtwdev->chip->support_bands;
5547 int ret;
5548
5549 if (support_bands & BIT(NL80211_BAND_2GHZ)) {
5550 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_2ghz);
5551 if (!sband)
5552 return -ENOMEM;
5553 rtw89_init_ht_cap(rtwdev, &sband->ht_cap);
5554 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_2GHZ, sband);
5555 if (ret)
5556 return ret;
5557 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
5558 }
5559
5560 if (support_bands & BIT(NL80211_BAND_5GHZ)) {
5561 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_5ghz);
5562 if (!sband)
5563 return -ENOMEM;
5564 rtw89_init_ht_cap(rtwdev, &sband->ht_cap);
5565 rtw89_init_vht_cap(rtwdev, &sband->vht_cap);
5566 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_5GHZ, sband);
5567 if (ret)
5568 return ret;
5569 hw->wiphy->bands[NL80211_BAND_5GHZ] = sband;
5570 }
5571
5572 if (support_bands & BIT(NL80211_BAND_6GHZ)) {
5573 sband = rtw89_core_sband_dup(rtwdev, &rtw89_sband_6ghz);
5574 if (!sband)
5575 return -ENOMEM;
5576 ret = rtw89_init_he_eht_cap(rtwdev, NL80211_BAND_6GHZ, sband);
5577 if (ret)
5578 return ret;
5579 hw->wiphy->bands[NL80211_BAND_6GHZ] = sband;
5580 }
5581
5582 return 0;
5583 }
5584
rtw89_core_ppdu_sts_init(struct rtw89_dev * rtwdev)5585 static void rtw89_core_ppdu_sts_init(struct rtw89_dev *rtwdev)
5586 {
5587 int i;
5588
5589 for (i = 0; i < RTW89_PHY_NUM; i++)
5590 skb_queue_head_init(&rtwdev->ppdu_sts.rx_queue[i]);
5591 for (i = 0; i < RTW89_PHY_NUM; i++)
5592 rtwdev->ppdu_sts.curr_rx_ppdu_cnt[i] = U8_MAX;
5593 }
5594
rtw89_core_update_beacon_work(struct wiphy * wiphy,struct wiphy_work * work)5595 void rtw89_core_update_beacon_work(struct wiphy *wiphy, struct wiphy_work *work)
5596 {
5597 struct rtw89_dev *rtwdev;
5598 struct rtw89_vif_link *rtwvif_link = container_of(work, struct rtw89_vif_link,
5599 update_beacon_work);
5600
5601 lockdep_assert_wiphy(wiphy);
5602
5603 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE)
5604 return;
5605
5606 rtwdev = rtwvif_link->rtwvif->rtwdev;
5607
5608 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link);
5609 }
5610
rtw89_core_csa_beacon_work(struct wiphy * wiphy,struct wiphy_work * work)5611 void rtw89_core_csa_beacon_work(struct wiphy *wiphy, struct wiphy_work *work)
5612 {
5613 struct rtw89_vif_link *rtwvif_link =
5614 container_of(work, struct rtw89_vif_link, csa_beacon_work.work);
5615 struct rtw89_vif *rtwvif = rtwvif_link->rtwvif;
5616 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
5617 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
5618 struct ieee80211_bss_conf *bss_conf;
5619 unsigned int delay;
5620
5621 lockdep_assert_wiphy(wiphy);
5622
5623 if (rtwvif_link->net_type != RTW89_NET_TYPE_AP_MODE)
5624 return;
5625
5626 rcu_read_lock();
5627
5628 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
5629 if (!bss_conf->csa_active) {
5630 rcu_read_unlock();
5631 return;
5632 }
5633
5634 delay = ieee80211_tu_to_usec(bss_conf->beacon_int);
5635
5636 rcu_read_unlock();
5637
5638 if (!ieee80211_beacon_cntdwn_is_complete(vif, rtwvif_link->link_id)) {
5639 rtw89_chip_h2c_update_beacon(rtwdev, rtwvif_link);
5640
5641 wiphy_delayed_work_queue(wiphy, &rtwvif_link->csa_beacon_work,
5642 usecs_to_jiffies(delay));
5643 } else {
5644 ieee80211_csa_finish(vif, rtwvif_link->link_id);
5645 }
5646 }
5647
5648 struct rtw89_wait_response *
rtw89_wait_for_cond_prep(struct rtw89_wait_info * wait,unsigned int cond)5649 rtw89_wait_for_cond_prep(struct rtw89_wait_info *wait, unsigned int cond)
5650 {
5651 struct rtw89_wait_response *prep;
5652 unsigned int cur;
5653
5654 /* use -EPERM _iff_ telling eval side not to make any changes */
5655
5656 cur = atomic_cmpxchg(&wait->cond, RTW89_WAIT_COND_IDLE, cond);
5657 if (cur != RTW89_WAIT_COND_IDLE)
5658 return ERR_PTR(-EPERM);
5659
5660 prep = kzalloc_obj(*prep);
5661 if (!prep)
5662 return ERR_PTR(-ENOMEM);
5663
5664 init_completion(&prep->completion);
5665
5666 rcu_assign_pointer(wait->resp, prep);
5667
5668 return prep;
5669 }
5670
rtw89_wait_for_cond_eval(struct rtw89_wait_info * wait,struct rtw89_wait_response * prep,int err)5671 int rtw89_wait_for_cond_eval(struct rtw89_wait_info *wait,
5672 struct rtw89_wait_response *prep, int err)
5673 {
5674 unsigned long time_left;
5675
5676 if (IS_ERR(prep)) {
5677 err = err ?: PTR_ERR(prep);
5678
5679 /* special error case: no permission to reset anything */
5680 if (PTR_ERR(prep) == -EPERM)
5681 return err;
5682
5683 goto reset;
5684 }
5685
5686 if (err)
5687 goto cleanup;
5688
5689 time_left = wait_for_completion_timeout(&prep->completion,
5690 RTW89_WAIT_FOR_COND_TIMEOUT);
5691 if (time_left == 0) {
5692 err = -ETIMEDOUT;
5693 goto cleanup;
5694 }
5695
5696 wait->data = prep->data;
5697
5698 cleanup:
5699 rcu_assign_pointer(wait->resp, NULL);
5700 kfree_rcu(prep, rcu_head);
5701
5702 reset:
5703 atomic_set(&wait->cond, RTW89_WAIT_COND_IDLE);
5704
5705 if (err)
5706 return err;
5707
5708 if (wait->data.err)
5709 return -EFAULT;
5710
5711 return 0;
5712 }
5713
rtw89_complete_cond_resp(struct rtw89_wait_response * resp,const struct rtw89_completion_data * data)5714 static void rtw89_complete_cond_resp(struct rtw89_wait_response *resp,
5715 const struct rtw89_completion_data *data)
5716 {
5717 resp->data = *data;
5718 complete(&resp->completion);
5719 }
5720
rtw89_complete_cond(struct rtw89_wait_info * wait,unsigned int cond,const struct rtw89_completion_data * data)5721 void rtw89_complete_cond(struct rtw89_wait_info *wait, unsigned int cond,
5722 const struct rtw89_completion_data *data)
5723 {
5724 struct rtw89_wait_response *resp;
5725 unsigned int cur;
5726
5727 guard(rcu)();
5728
5729 resp = rcu_dereference(wait->resp);
5730 if (!resp)
5731 return;
5732
5733 cur = atomic_cmpxchg(&wait->cond, cond, RTW89_WAIT_COND_IDLE);
5734 if (cur != cond)
5735 return;
5736
5737 rtw89_complete_cond_resp(resp, data);
5738 }
5739
rtw89_core_ntfy_btc_event(struct rtw89_dev * rtwdev,enum rtw89_btc_hmsg event)5740 void rtw89_core_ntfy_btc_event(struct rtw89_dev *rtwdev, enum rtw89_btc_hmsg event)
5741 {
5742 u16 bt_req_len;
5743
5744 switch (event) {
5745 case RTW89_BTC_HMSG_SET_BT_REQ_SLOT:
5746 bt_req_len = rtw89_coex_query_bt_req_len(rtwdev, RTW89_PHY_0);
5747 rtw89_debug(rtwdev, RTW89_DBG_BTC,
5748 "coex updates BT req len to %d TU\n", bt_req_len);
5749 rtw89_queue_chanctx_change(rtwdev, RTW89_CHANCTX_BT_SLOT_CHANGE);
5750 break;
5751 default:
5752 if (event < NUM_OF_RTW89_BTC_HMSG)
5753 rtw89_debug(rtwdev, RTW89_DBG_BTC,
5754 "unhandled BTC HMSG event: %d\n", event);
5755 else
5756 rtw89_warn(rtwdev,
5757 "unrecognized BTC HMSG event: %d\n", event);
5758 break;
5759 }
5760 }
5761
rtw89_check_quirks(struct rtw89_dev * rtwdev,const struct dmi_system_id * quirks)5762 void rtw89_check_quirks(struct rtw89_dev *rtwdev, const struct dmi_system_id *quirks)
5763 {
5764 const struct dmi_system_id *match;
5765 enum rtw89_quirks quirk;
5766
5767 if (!quirks)
5768 return;
5769
5770 for (match = dmi_first_match(quirks); match; match = dmi_first_match(match + 1)) {
5771 quirk = (uintptr_t)match->driver_data;
5772 if (quirk >= NUM_OF_RTW89_QUIRKS)
5773 continue;
5774
5775 set_bit(quirk, rtwdev->quirks);
5776 }
5777 }
5778 EXPORT_SYMBOL(rtw89_check_quirks);
5779
rtw89_core_start(struct rtw89_dev * rtwdev)5780 int rtw89_core_start(struct rtw89_dev *rtwdev)
5781 {
5782 bool no_bbmcu = !rtwdev->chip->bbmcu_nr;
5783 int ret;
5784
5785 ret = rtw89_mac_preinit(rtwdev);
5786 if (ret) {
5787 rtw89_err(rtwdev, "mac preinit fail, ret: %d\n", ret);
5788 return ret;
5789 }
5790
5791 if (no_bbmcu)
5792 rtw89_chip_bb_preinit(rtwdev);
5793
5794 rtw89_phy_init_bb_afe(rtwdev);
5795
5796 /* above do preinit before downloading firmware */
5797
5798 ret = rtw89_mac_init(rtwdev);
5799 if (ret) {
5800 rtw89_err(rtwdev, "mac init fail, ret:%d\n", ret);
5801 return ret;
5802 }
5803
5804 rtw89_btc_ntfy_poweron(rtwdev);
5805
5806 /* efuse process */
5807
5808 /* pre-config BB/RF, BB reset/RFC reset */
5809 ret = rtw89_chip_reset_bb_rf(rtwdev);
5810 if (ret)
5811 return ret;
5812
5813 rtw89_phy_init_bb_reg(rtwdev);
5814 rtw89_chip_bb_postinit(rtwdev);
5815 rtw89_phy_init_rf_reg(rtwdev, false);
5816
5817 rtw89_btc_ntfy_init(rtwdev, BTC_MODE_NORMAL);
5818
5819 rtw89_phy_dm_init(rtwdev);
5820
5821 rtw89_mac_set_edcca_mode_bands(rtwdev, true);
5822 rtw89_mac_cfg_ppdu_status_bands(rtwdev, true);
5823 rtw89_mac_cfg_phy_rpt_bands(rtwdev, true);
5824 rtw89_mac_update_rts_threshold(rtwdev);
5825
5826 ret = rtw89_hci_start(rtwdev);
5827 if (ret) {
5828 rtw89_err(rtwdev, "failed to start hci\n");
5829 return ret;
5830 }
5831
5832 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_work,
5833 RTW89_TRACK_WORK_PERIOD);
5834 wiphy_delayed_work_queue(rtwdev->hw->wiphy, &rtwdev->track_ps_work,
5835 RTW89_TRACK_PS_WORK_PERIOD);
5836
5837 set_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
5838
5839 rtw89_chip_rfk_init_late(rtwdev);
5840 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_ON);
5841 rtw89_fw_h2c_fw_log(rtwdev, rtwdev->fw.log.enable);
5842 rtw89_fw_h2c_init_ba_cam(rtwdev);
5843 rtw89_tas_fw_timer_enable(rtwdev, true);
5844 rtwdev->ps_hang_cnt = 0;
5845
5846 return 0;
5847 }
5848
rtw89_core_stop(struct rtw89_dev * rtwdev)5849 void rtw89_core_stop(struct rtw89_dev *rtwdev)
5850 {
5851 struct wiphy *wiphy = rtwdev->hw->wiphy;
5852 struct rtw89_btc *btc = &rtwdev->btc;
5853
5854 lockdep_assert_wiphy(wiphy);
5855
5856 /* Prvent to stop twice; enter_ips and ops_stop */
5857 if (!test_bit(RTW89_FLAG_RUNNING, rtwdev->flags))
5858 return;
5859
5860 rtw89_tas_fw_timer_enable(rtwdev, false);
5861 rtw89_btc_ntfy_radio_state(rtwdev, BTC_RFCTRL_WL_OFF);
5862
5863 clear_bit(RTW89_FLAG_RUNNING, rtwdev->flags);
5864
5865 wiphy_work_cancel(wiphy, &rtwdev->c2h_work);
5866 wiphy_work_cancel(wiphy, &rtwdev->cancel_6ghz_probe_work);
5867 wiphy_work_cancel(wiphy, &btc->eapol_notify_work);
5868 wiphy_work_cancel(wiphy, &btc->arp_notify_work);
5869 wiphy_work_cancel(wiphy, &btc->dhcp_notify_work);
5870 wiphy_work_cancel(wiphy, &btc->icmp_notify_work);
5871 cancel_delayed_work_sync(&rtwdev->txq_reinvoke_work);
5872 wiphy_delayed_work_cancel(wiphy, &rtwdev->tx_wait_work);
5873 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_work);
5874 wiphy_delayed_work_cancel(wiphy, &rtwdev->track_ps_work);
5875 wiphy_delayed_work_cancel(wiphy, &rtwdev->chanctx_work);
5876 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_act1_work);
5877 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_bt_devinfo_work);
5878 wiphy_delayed_work_cancel(wiphy, &rtwdev->coex_rfk_chk_work);
5879 wiphy_delayed_work_cancel(wiphy, &rtwdev->cfo_track_work);
5880 wiphy_delayed_work_cancel(wiphy, &rtwdev->mcc_prepare_done_work);
5881 cancel_delayed_work_sync(&rtwdev->forbid_ba_work);
5882 wiphy_delayed_work_cancel(wiphy, &rtwdev->antdiv_work);
5883
5884 rtw89_btc_ntfy_poweroff(rtwdev);
5885 rtw89_hci_flush_queues(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
5886 rtw89_mac_flush_txq(rtwdev, BIT(rtwdev->hw->queues) - 1, true);
5887 rtw89_hci_stop(rtwdev);
5888 rtw89_hci_deinit(rtwdev);
5889 rtw89_mac_pwr_off(rtwdev);
5890 rtw89_hci_reset(rtwdev);
5891 }
5892
rtw89_acquire_mac_id(struct rtw89_dev * rtwdev)5893 u8 rtw89_acquire_mac_id(struct rtw89_dev *rtwdev)
5894 {
5895 const struct rtw89_chip_info *chip = rtwdev->chip;
5896 u8 mac_id_num;
5897 u8 mac_id;
5898
5899 if (rtwdev->support_mlo)
5900 mac_id_num = chip->support_macid_num / chip->support_link_num;
5901 else
5902 mac_id_num = chip->support_macid_num;
5903
5904 mac_id = find_first_zero_bit(rtwdev->mac_id_map, mac_id_num);
5905 if (mac_id == mac_id_num)
5906 return RTW89_MAX_MAC_ID_NUM;
5907
5908 set_bit(mac_id, rtwdev->mac_id_map);
5909 return mac_id;
5910 }
5911
rtw89_release_mac_id(struct rtw89_dev * rtwdev,u8 mac_id)5912 void rtw89_release_mac_id(struct rtw89_dev *rtwdev, u8 mac_id)
5913 {
5914 clear_bit(mac_id, rtwdev->mac_id_map);
5915 }
5916
rtw89_init_vif(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,u8 mac_id,u8 port)5917 void rtw89_init_vif(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
5918 u8 mac_id, u8 port)
5919 {
5920 const struct rtw89_chip_info *chip = rtwdev->chip;
5921 u8 support_link_num = chip->support_link_num;
5922 u8 support_mld_num = 0;
5923 unsigned int link_id;
5924 u8 index;
5925
5926 bitmap_zero(rtwvif->links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
5927 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++)
5928 rtwvif->links[link_id] = NULL;
5929
5930 rtwvif->rtwdev = rtwdev;
5931
5932 if (rtwdev->support_mlo) {
5933 rtwvif->links_inst_valid_num = support_link_num;
5934 support_mld_num = chip->support_macid_num / support_link_num;
5935 } else {
5936 rtwvif->links_inst_valid_num = 1;
5937 }
5938
5939 for (index = 0; index < rtwvif->links_inst_valid_num; index++) {
5940 struct rtw89_vif_link *inst = &rtwvif->links_inst[index];
5941
5942 inst->rtwvif = rtwvif;
5943 inst->mac_id = mac_id + index * support_mld_num;
5944 inst->mac_idx = RTW89_MAC_0 + index;
5945 inst->phy_idx = RTW89_PHY_0 + index;
5946
5947 /* multi-link use the same port id on different HW bands */
5948 inst->port = port;
5949 }
5950 }
5951
rtw89_init_sta(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,struct rtw89_sta * rtwsta,u8 mac_id)5952 void rtw89_init_sta(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
5953 struct rtw89_sta *rtwsta, u8 mac_id)
5954 {
5955 const struct rtw89_chip_info *chip = rtwdev->chip;
5956 u8 support_link_num = chip->support_link_num;
5957 u8 support_mld_num = 0;
5958 unsigned int link_id;
5959 u8 index;
5960
5961 bitmap_zero(rtwsta->links_inst_map, __RTW89_MLD_MAX_LINK_NUM);
5962 for (link_id = 0; link_id < IEEE80211_MLD_MAX_NUM_LINKS; link_id++)
5963 rtwsta->links[link_id] = NULL;
5964
5965 rtwsta->rtwdev = rtwdev;
5966 rtwsta->rtwvif = rtwvif;
5967
5968 if (rtwdev->support_mlo) {
5969 rtwsta->links_inst_valid_num = support_link_num;
5970 support_mld_num = chip->support_macid_num / support_link_num;
5971 } else {
5972 rtwsta->links_inst_valid_num = 1;
5973 }
5974
5975 for (index = 0; index < rtwsta->links_inst_valid_num; index++) {
5976 struct rtw89_sta_link *inst = &rtwsta->links_inst[index];
5977
5978 inst->rtwvif_link = &rtwvif->links_inst[index];
5979
5980 inst->rtwsta = rtwsta;
5981 inst->mac_id = mac_id + index * support_mld_num;
5982 }
5983 }
5984
rtw89_vif_set_link(struct rtw89_vif * rtwvif,unsigned int link_id)5985 struct rtw89_vif_link *rtw89_vif_set_link(struct rtw89_vif *rtwvif,
5986 unsigned int link_id)
5987 {
5988 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id];
5989 u8 index;
5990 int ret;
5991
5992 if (rtwvif_link)
5993 return rtwvif_link;
5994
5995 index = find_first_zero_bit(rtwvif->links_inst_map,
5996 rtwvif->links_inst_valid_num);
5997 if (index == rtwvif->links_inst_valid_num) {
5998 ret = -EBUSY;
5999 goto err;
6000 }
6001
6002 rtwvif_link = &rtwvif->links_inst[index];
6003 rtwvif_link->link_id = link_id;
6004
6005 set_bit(index, rtwvif->links_inst_map);
6006 rtwvif->links[link_id] = rtwvif_link;
6007 list_add_tail(&rtwvif_link->dlink_schd, &rtwvif->dlink_pool);
6008 return rtwvif_link;
6009
6010 err:
6011 rtw89_err(rtwvif->rtwdev, "vif (link_id %u) failed to set link: %d\n",
6012 link_id, ret);
6013 return NULL;
6014 }
6015
rtw89_vif_unset_link(struct rtw89_vif * rtwvif,unsigned int link_id)6016 void rtw89_vif_unset_link(struct rtw89_vif *rtwvif, unsigned int link_id)
6017 {
6018 struct rtw89_vif_link **container = &rtwvif->links[link_id];
6019 struct rtw89_vif_link *link = *container;
6020 u8 index;
6021
6022 if (!link)
6023 return;
6024
6025 index = rtw89_vif_link_inst_get_index(link);
6026 clear_bit(index, rtwvif->links_inst_map);
6027 *container = NULL;
6028 list_del(&link->dlink_schd);
6029 }
6030
rtw89_sta_set_link(struct rtw89_sta * rtwsta,unsigned int link_id)6031 struct rtw89_sta_link *rtw89_sta_set_link(struct rtw89_sta *rtwsta,
6032 unsigned int link_id)
6033 {
6034 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
6035 struct rtw89_vif_link *rtwvif_link = rtwvif->links[link_id];
6036 struct rtw89_sta_link *rtwsta_link = rtwsta->links[link_id];
6037 u8 index;
6038 int ret;
6039
6040 if (rtwsta_link)
6041 return rtwsta_link;
6042
6043 if (!rtwvif_link) {
6044 ret = -ENOLINK;
6045 goto err;
6046 }
6047
6048 index = rtw89_vif_link_inst_get_index(rtwvif_link);
6049 if (test_bit(index, rtwsta->links_inst_map)) {
6050 ret = -EBUSY;
6051 goto err;
6052 }
6053
6054 rtwsta_link = &rtwsta->links_inst[index];
6055 rtwsta_link->link_id = link_id;
6056
6057 set_bit(index, rtwsta->links_inst_map);
6058 rtwsta->links[link_id] = rtwsta_link;
6059 list_add_tail(&rtwsta_link->dlink_schd, &rtwsta->dlink_pool);
6060 return rtwsta_link;
6061
6062 err:
6063 rtw89_err(rtwsta->rtwdev, "sta (link_id %u) failed to set link: %d\n",
6064 link_id, ret);
6065 return NULL;
6066 }
6067
rtw89_sta_unset_link(struct rtw89_sta * rtwsta,unsigned int link_id)6068 void rtw89_sta_unset_link(struct rtw89_sta *rtwsta, unsigned int link_id)
6069 {
6070 struct rtw89_sta_link **container = &rtwsta->links[link_id];
6071 struct rtw89_sta_link *link = *container;
6072 u8 index;
6073
6074 if (!link)
6075 return;
6076
6077 index = rtw89_sta_link_inst_get_index(link);
6078 clear_bit(index, rtwsta->links_inst_map);
6079 *container = NULL;
6080 list_del(&link->dlink_schd);
6081 }
6082
rtw89_core_init(struct rtw89_dev * rtwdev)6083 int rtw89_core_init(struct rtw89_dev *rtwdev)
6084 {
6085 struct rtw89_btc *btc = &rtwdev->btc;
6086 u8 band;
6087
6088 bitmap_or(rtwdev->quirks, rtwdev->quirks, &rtwdev->chip->default_quirks,
6089 NUM_OF_RTW89_QUIRKS);
6090
6091 INIT_LIST_HEAD(&rtwdev->ba_list);
6092 INIT_LIST_HEAD(&rtwdev->forbid_ba_list);
6093 INIT_LIST_HEAD(&rtwdev->rtwvifs_list);
6094 INIT_LIST_HEAD(&rtwdev->early_h2c_list);
6095 for (band = NL80211_BAND_2GHZ; band < NUM_NL80211_BANDS; band++) {
6096 if (!(rtwdev->chip->support_bands & BIT(band)))
6097 continue;
6098 INIT_LIST_HEAD(&rtwdev->scan_info.pkt_list[band]);
6099 }
6100 INIT_LIST_HEAD(&rtwdev->scan_info.chan_list);
6101 INIT_LIST_HEAD(&rtwdev->tx_waits);
6102 INIT_WORK(&rtwdev->ba_work, rtw89_core_ba_work);
6103 INIT_WORK(&rtwdev->txq_work, rtw89_core_txq_work);
6104 INIT_DELAYED_WORK(&rtwdev->txq_reinvoke_work, rtw89_core_txq_reinvoke_work);
6105 wiphy_delayed_work_init(&rtwdev->track_work, rtw89_track_work);
6106 wiphy_delayed_work_init(&rtwdev->track_ps_work, rtw89_track_ps_work);
6107 wiphy_delayed_work_init(&rtwdev->chanctx_work, rtw89_chanctx_work);
6108 wiphy_delayed_work_init(&rtwdev->coex_act1_work, rtw89_coex_act1_work);
6109 wiphy_delayed_work_init(&rtwdev->coex_bt_devinfo_work, rtw89_coex_bt_devinfo_work);
6110 wiphy_delayed_work_init(&rtwdev->coex_rfk_chk_work, rtw89_coex_rfk_chk_work);
6111 wiphy_delayed_work_init(&rtwdev->cfo_track_work, rtw89_phy_cfo_track_work);
6112 wiphy_delayed_work_init(&rtwdev->mcc_prepare_done_work, rtw89_mcc_prepare_done_work);
6113 wiphy_delayed_work_init(&rtwdev->tx_wait_work, rtw89_tx_wait_work);
6114 INIT_DELAYED_WORK(&rtwdev->forbid_ba_work, rtw89_forbid_ba_work);
6115 wiphy_delayed_work_init(&rtwdev->antdiv_work, rtw89_phy_antdiv_work);
6116 rtwdev->txq_wq = alloc_workqueue("rtw89_tx_wq", WQ_UNBOUND | WQ_HIGHPRI, 0);
6117 if (!rtwdev->txq_wq)
6118 return -ENOMEM;
6119 spin_lock_init(&rtwdev->ba_lock);
6120 spin_lock_init(&rtwdev->rpwm_lock);
6121 mutex_init(&rtwdev->rf_mutex);
6122 rtwdev->total_sta_assoc = 0;
6123
6124 rtw89_init_wait(&rtwdev->mcc.wait);
6125 rtw89_init_wait(&rtwdev->mlo.wait);
6126 rtw89_init_wait(&rtwdev->mac.fw_ofld_wait);
6127 rtw89_init_wait(&rtwdev->wow.wait);
6128 rtw89_init_wait(&rtwdev->mac.ps_wait);
6129
6130 wiphy_work_init(&rtwdev->c2h_work, rtw89_fw_c2h_work);
6131 wiphy_work_init(&rtwdev->ips_work, rtw89_ips_work);
6132 wiphy_work_init(&rtwdev->cancel_6ghz_probe_work, rtw89_cancel_6ghz_probe_work);
6133 INIT_WORK(&rtwdev->load_firmware_work, rtw89_load_firmware_work);
6134
6135 spin_lock_init(&rtwdev->tx_rpt.skb_lock);
6136 skb_queue_head_init(&rtwdev->c2h_queue);
6137 rtw89_core_ppdu_sts_init(rtwdev);
6138 rtw89_traffic_stats_init(rtwdev, &rtwdev->stats);
6139
6140 rtwdev->hal.rx_fltr = DEFAULT_AX_RX_FLTR;
6141 rtwdev->dbcc_en = false;
6142 rtwdev->mlo_dbcc_mode = MLO_DBCC_NOT_SUPPORT;
6143 rtwdev->mac.qta_mode = RTW89_QTA_SCC;
6144
6145 if (rtwdev->chip->chip_gen == RTW89_CHIP_BE) {
6146 rtwdev->dbcc_en = true;
6147 rtwdev->mac.qta_mode = RTW89_QTA_DBCC;
6148 rtwdev->mlo_dbcc_mode = MLO_1_PLUS_1_1RF;
6149 }
6150
6151 rtwdev->bbs[RTW89_PHY_0].phy_idx = RTW89_PHY_0;
6152 rtwdev->bbs[RTW89_PHY_1].phy_idx = RTW89_PHY_1;
6153
6154 wiphy_work_init(&btc->eapol_notify_work, rtw89_btc_ntfy_eapol_packet_work);
6155 wiphy_work_init(&btc->arp_notify_work, rtw89_btc_ntfy_arp_packet_work);
6156 wiphy_work_init(&btc->dhcp_notify_work, rtw89_btc_ntfy_dhcp_packet_work);
6157 wiphy_work_init(&btc->icmp_notify_work, rtw89_btc_ntfy_icmp_packet_work);
6158
6159 init_completion(&rtwdev->fw.req.completion);
6160 init_completion(&rtwdev->rfk_wait.completion);
6161
6162 schedule_work(&rtwdev->load_firmware_work);
6163
6164 rtw89_ser_init(rtwdev);
6165 rtw89_entity_init(rtwdev);
6166 rtw89_sar_init(rtwdev);
6167 rtw89_phy_ant_gain_init(rtwdev);
6168
6169 return 0;
6170 }
6171 EXPORT_SYMBOL(rtw89_core_init);
6172
rtw89_core_deinit(struct rtw89_dev * rtwdev)6173 void rtw89_core_deinit(struct rtw89_dev *rtwdev)
6174 {
6175 rtw89_ser_deinit(rtwdev);
6176 rtw89_unload_firmware(rtwdev);
6177 __rtw89_fw_free_all_early_h2c(rtwdev);
6178
6179 destroy_workqueue(rtwdev->txq_wq);
6180 mutex_destroy(&rtwdev->rf_mutex);
6181 }
6182 EXPORT_SYMBOL(rtw89_core_deinit);
6183
rtw89_core_scan_start(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,const u8 * mac_addr,bool hw_scan)6184 void rtw89_core_scan_start(struct rtw89_dev *rtwdev, struct rtw89_vif_link *rtwvif_link,
6185 const u8 *mac_addr, bool hw_scan)
6186 {
6187 const struct rtw89_chan *chan = rtw89_chan_get(rtwdev,
6188 rtwvif_link->chanctx_idx);
6189 struct rtw89_bb_ctx *bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
6190
6191 rtwdev->scanning = true;
6192
6193 ether_addr_copy(rtwvif_link->mac_addr, mac_addr);
6194 rtw89_btc_ntfy_scan_start(rtwdev, rtwvif_link->phy_idx, chan->band_type);
6195 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, true);
6196 rtw89_hci_recalc_int_mit(rtwdev);
6197 rtw89_phy_config_edcca(rtwdev, bb, true);
6198 rtw89_tas_scan(rtwdev, true);
6199
6200 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, mac_addr,
6201 RTW89_ROLE_INFO_CHANGE);
6202 }
6203
rtw89_core_scan_complete(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link,bool hw_scan)6204 void rtw89_core_scan_complete(struct rtw89_dev *rtwdev,
6205 struct rtw89_vif_link *rtwvif_link, bool hw_scan)
6206 {
6207 struct ieee80211_bss_conf *bss_conf;
6208 struct rtw89_bb_ctx *bb;
6209 int ret;
6210
6211 if (!rtwvif_link)
6212 return;
6213
6214 rcu_read_lock();
6215
6216 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, true);
6217 ether_addr_copy(rtwvif_link->mac_addr, bss_conf->addr);
6218
6219 rcu_read_unlock();
6220
6221 rtw89_fw_h2c_cam(rtwdev, rtwvif_link, NULL, NULL,
6222 RTW89_ROLE_INFO_CHANGE);
6223
6224 rtw89_chip_rfk_scan(rtwdev, rtwvif_link, false);
6225 rtw89_btc_ntfy_scan_finish(rtwdev, rtwvif_link->phy_idx);
6226 bb = rtw89_get_bb_ctx(rtwdev, rtwvif_link->phy_idx);
6227 rtw89_phy_config_edcca(rtwdev, bb, false);
6228 rtw89_tas_scan(rtwdev, false);
6229
6230 if (hw_scan) {
6231 ret = rtw89_core_send_nullfunc(rtwdev, rtwvif_link, false, false,
6232 RTW89_SCAN_NULL_TIMEOUT);
6233 if (ret)
6234 rtw89_debug(rtwdev, RTW89_DBG_TXRX,
6235 "scan send null-0 failed: %d\n", ret);
6236 }
6237
6238 rtwdev->scanning = false;
6239 rtw89_for_each_active_bb(rtwdev, bb)
6240 bb->dig.bypass_dig = true;
6241 if (hw_scan && (rtwdev->hw->conf.flags & IEEE80211_CONF_IDLE))
6242 wiphy_work_queue(rtwdev->hw->wiphy, &rtwdev->ips_work);
6243 }
6244
rtw89_read_chip_ver(struct rtw89_dev * rtwdev)6245 static void rtw89_read_chip_ver(struct rtw89_dev *rtwdev)
6246 {
6247 const struct rtw89_chip_info *chip = rtwdev->chip;
6248 struct rtw89_hal *hal = &rtwdev->hal;
6249 int ret;
6250 u8 val2;
6251 u8 val;
6252 u8 cv;
6253
6254 cv = rtw89_read32_mask(rtwdev, R_AX_SYS_CFG1, B_AX_CHIP_VER_MASK);
6255 if (chip->chip_id == RTL8852A && cv <= CHIP_CBV) {
6256 if (rtw89_read32(rtwdev, R_AX_GPIO0_7_FUNC_SEL) == RTW89_R32_DEAD)
6257 cv = CHIP_CAV;
6258 else
6259 cv = CHIP_CBV;
6260 }
6261
6262 hal->cv = cv;
6263
6264 if (rtw89_is_rtl885xb(rtwdev) || chip->chip_gen >= RTW89_CHIP_BE) {
6265 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CV, &val);
6266 if (ret)
6267 return;
6268
6269 hal->acv = u8_get_bits(val, XTAL_SI_ACV_MASK);
6270 }
6271
6272 if (chip->chip_gen >= RTW89_CHIP_BE) {
6273 hal->cid =
6274 rtw89_read32_mask(rtwdev, R_BE_SYS_CHIPINFO, B_BE_HW_ID_MASK);
6275
6276 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CHIP_ID_L, &val);
6277 if (ret)
6278 return;
6279 ret = rtw89_mac_read_xtal_si(rtwdev, XTAL_SI_CHIP_ID_H, &val2);
6280 if (ret)
6281 return;
6282
6283 hal->aid = val | val2 << 8;
6284 }
6285 }
6286
rtw89_core_setup_phycap(struct rtw89_dev * rtwdev)6287 static void rtw89_core_setup_phycap(struct rtw89_dev *rtwdev)
6288 {
6289 const struct rtw89_chip_info *chip = rtwdev->chip;
6290
6291 rtwdev->hal.support_cckpd =
6292 !(rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV) &&
6293 !(rtwdev->chip->chip_id == RTL8852B && rtwdev->hal.cv <= CHIP_CAV);
6294 rtwdev->hal.support_igi =
6295 rtwdev->chip->chip_id == RTL8852A && rtwdev->hal.cv <= CHIP_CBV;
6296
6297 if (test_bit(RTW89_QUIRK_THERMAL_PROT_120C, rtwdev->quirks))
6298 rtwdev->hal.thermal_prot_th = chip->thermal_th[1];
6299 else if (test_bit(RTW89_QUIRK_THERMAL_PROT_110C, rtwdev->quirks))
6300 rtwdev->hal.thermal_prot_th = chip->thermal_th[0];
6301 else
6302 rtwdev->hal.thermal_prot_th = 0;
6303 }
6304
rtw89_core_setup_rfe_parms(struct rtw89_dev * rtwdev)6305 static void rtw89_core_setup_rfe_parms(struct rtw89_dev *rtwdev)
6306 {
6307 const struct rtw89_chip_info *chip = rtwdev->chip;
6308 const struct rtw89_rfe_parms_conf *conf = chip->rfe_parms_conf;
6309 struct rtw89_efuse *efuse = &rtwdev->efuse;
6310 const struct rtw89_rfe_parms *sel;
6311 u8 rfe_type = efuse->rfe_type;
6312
6313 if (!conf) {
6314 sel = chip->dflt_parms;
6315 goto out;
6316 }
6317
6318 while (conf->rfe_parms) {
6319 if (rfe_type == conf->rfe_type) {
6320 sel = conf->rfe_parms;
6321 goto out;
6322 }
6323 conf++;
6324 }
6325
6326 sel = chip->dflt_parms;
6327
6328 out:
6329 rtwdev->rfe_parms = rtw89_load_rfe_data_from_fw(rtwdev, sel);
6330 rtw89_load_txpwr_table(rtwdev, rtwdev->rfe_parms->byr_tbl);
6331 }
6332
rtw89_core_mlsr_switch(struct rtw89_dev * rtwdev,struct rtw89_vif * rtwvif,unsigned int link_id)6333 int rtw89_core_mlsr_switch(struct rtw89_dev *rtwdev, struct rtw89_vif *rtwvif,
6334 unsigned int link_id)
6335 {
6336 struct ieee80211_vif *vif = rtwvif_to_vif(rtwvif);
6337 u16 usable_links = ieee80211_vif_usable_links(vif);
6338 u16 active_links = vif->active_links;
6339 struct rtw89_vif_link *target;
6340 int ret;
6341
6342 lockdep_assert_wiphy(rtwdev->hw->wiphy);
6343
6344 if (unlikely(!ieee80211_vif_is_mld(vif)))
6345 return -EOPNOTSUPP;
6346
6347 if (unlikely(link_id >= IEEE80211_MLD_MAX_NUM_LINKS ||
6348 !(usable_links & BIT(link_id)))) {
6349 rtw89_warn(rtwdev, "%s: link id %u is not usable\n", __func__,
6350 link_id);
6351 return -ENOLINK;
6352 }
6353
6354 if (active_links == BIT(link_id))
6355 return 0;
6356
6357 rtw89_debug(rtwdev, RTW89_DBG_STATE, "%s: switch to link id %u MLSR\n",
6358 __func__, link_id);
6359
6360 rtw89_leave_lps(rtwdev);
6361
6362 ieee80211_stop_queues(rtwdev->hw);
6363 flush_work(&rtwdev->txq_work);
6364
6365 ret = ieee80211_set_active_links(vif, BIT(link_id));
6366 if (ret) {
6367 rtw89_err(rtwdev, "%s: failed to work on link id %u\n",
6368 __func__, link_id);
6369 goto wake_queue;
6370 }
6371
6372 target = rtwvif->links[link_id];
6373 if (unlikely(!target)) {
6374 rtw89_err(rtwdev, "%s: failed to confirm link id %u\n",
6375 __func__, link_id);
6376
6377 ieee80211_set_active_links(vif, active_links);
6378 ret = -EFAULT;
6379 goto wake_queue;
6380 }
6381
6382 if (RTW89_CHK_FW_FEATURE_GROUP(WITH_RFK_PRE_NOTIFY, &rtwdev->fw))
6383 rtw89_chip_rfk_channel(rtwdev, target);
6384
6385 rtwvif->mlo_mode = RTW89_MLO_MODE_MLSR;
6386
6387 wake_queue:
6388 ieee80211_wake_queues(rtwdev->hw);
6389
6390 return ret;
6391 }
6392
rtw89_chip_efuse_info_setup(struct rtw89_dev * rtwdev)6393 static int rtw89_chip_efuse_info_setup(struct rtw89_dev *rtwdev)
6394 {
6395 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
6396 int ret;
6397
6398 ret = rtw89_mac_partial_init(rtwdev, false);
6399 if (ret)
6400 return ret;
6401
6402 ret = mac->parse_efuse_map(rtwdev);
6403 if (ret)
6404 return ret;
6405
6406 ret = mac->parse_phycap_map(rtwdev);
6407 if (ret)
6408 return ret;
6409
6410 ret = rtw89_mac_setup_phycap(rtwdev);
6411 if (ret)
6412 return ret;
6413
6414 rtw89_core_setup_phycap(rtwdev);
6415
6416 rtw89_hci_mac_pre_deinit(rtwdev);
6417
6418 return 0;
6419 }
6420
rtw89_chip_board_info_setup(struct rtw89_dev * rtwdev)6421 static int rtw89_chip_board_info_setup(struct rtw89_dev *rtwdev)
6422 {
6423 rtw89_chip_fem_setup(rtwdev);
6424
6425 return 0;
6426 }
6427
rtw89_chip_has_rfkill(struct rtw89_dev * rtwdev)6428 static bool rtw89_chip_has_rfkill(struct rtw89_dev *rtwdev)
6429 {
6430 return !!rtwdev->chip->rfkill_init;
6431 }
6432
rtw89_core_rfkill_init(struct rtw89_dev * rtwdev)6433 static void rtw89_core_rfkill_init(struct rtw89_dev *rtwdev)
6434 {
6435 const struct rtw89_rfkill_regs *regs = rtwdev->chip->rfkill_init;
6436
6437 rtw89_write16_mask(rtwdev, regs->pinmux.addr,
6438 regs->pinmux.mask, regs->pinmux.data);
6439 rtw89_write16_mask(rtwdev, regs->mode.addr,
6440 regs->mode.mask, regs->mode.data);
6441 }
6442
rtw89_core_rfkill_get(struct rtw89_dev * rtwdev)6443 static bool rtw89_core_rfkill_get(struct rtw89_dev *rtwdev)
6444 {
6445 const struct rtw89_reg_def *reg = &rtwdev->chip->rfkill_get;
6446
6447 return !rtw89_read8_mask(rtwdev, reg->addr, reg->mask);
6448 }
6449
rtw89_rfkill_polling_init(struct rtw89_dev * rtwdev)6450 static void rtw89_rfkill_polling_init(struct rtw89_dev *rtwdev)
6451 {
6452 if (!rtw89_chip_has_rfkill(rtwdev))
6453 return;
6454
6455 rtw89_core_rfkill_init(rtwdev);
6456 rtw89_core_rfkill_poll(rtwdev, true);
6457 wiphy_rfkill_start_polling(rtwdev->hw->wiphy);
6458 }
6459
rtw89_rfkill_polling_deinit(struct rtw89_dev * rtwdev)6460 static void rtw89_rfkill_polling_deinit(struct rtw89_dev *rtwdev)
6461 {
6462 if (!rtw89_chip_has_rfkill(rtwdev))
6463 return;
6464
6465 wiphy_rfkill_stop_polling(rtwdev->hw->wiphy);
6466 }
6467
rtw89_core_rfkill_poll(struct rtw89_dev * rtwdev,bool force)6468 void rtw89_core_rfkill_poll(struct rtw89_dev *rtwdev, bool force)
6469 {
6470 bool prev, blocked;
6471
6472 if (!rtw89_chip_has_rfkill(rtwdev))
6473 return;
6474
6475 prev = test_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
6476 blocked = rtw89_core_rfkill_get(rtwdev);
6477
6478 if (!force && prev == blocked)
6479 return;
6480
6481 rtw89_info(rtwdev, "rfkill hardware state changed to %s\n",
6482 blocked ? "disable" : "enable");
6483
6484 if (blocked)
6485 set_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
6486 else
6487 clear_bit(RTW89_FLAG_HW_RFKILL_STATE, rtwdev->flags);
6488
6489 wiphy_rfkill_set_hw_state(rtwdev->hw->wiphy, blocked);
6490 }
6491
rtw89_chip_info_setup(struct rtw89_dev * rtwdev)6492 int rtw89_chip_info_setup(struct rtw89_dev *rtwdev)
6493 {
6494 struct rtw89_efuse *efuse = &rtwdev->efuse;
6495 struct rtw89_hal *hal = &rtwdev->hal;
6496 int ret;
6497
6498 rtw89_read_chip_ver(rtwdev);
6499
6500 ret = rtw89_mac_pwr_on(rtwdev);
6501 if (ret) {
6502 rtw89_err(rtwdev, "failed to power on\n");
6503 return ret;
6504 }
6505
6506 ret = rtw89_wait_firmware_completion(rtwdev);
6507 if (ret) {
6508 rtw89_err(rtwdev, "failed to wait firmware completion\n");
6509 goto out;
6510 }
6511
6512 ret = rtw89_fw_recognize(rtwdev);
6513 if (ret) {
6514 rtw89_err(rtwdev, "failed to recognize firmware\n");
6515 goto out;
6516 }
6517
6518 ret = rtw89_chip_efuse_info_setup(rtwdev);
6519 if (ret)
6520 goto out;
6521
6522 ret = rtw89_fw_recognize_elements(rtwdev);
6523 if (ret) {
6524 rtw89_err(rtwdev, "failed to recognize firmware elements\n");
6525 goto out;
6526 }
6527
6528 ret = rtw89_chip_board_info_setup(rtwdev);
6529 if (ret)
6530 goto out;
6531
6532 rtw89_core_setup_rfe_parms(rtwdev);
6533 rtwdev->ps_mode = rtw89_update_ps_mode(rtwdev);
6534
6535 rtw89_info(rtwdev, "chip info CID: %x, CV: %x, AID: %x, ACV: %x, RFE: %d\n",
6536 hal->cid, hal->cv, hal->aid, hal->acv, efuse->rfe_type);
6537
6538 out:
6539 rtw89_mac_pwr_off(rtwdev);
6540
6541 return ret;
6542 }
6543 EXPORT_SYMBOL(rtw89_chip_info_setup);
6544
rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev * rtwdev,struct rtw89_vif_link * rtwvif_link)6545 void rtw89_chip_cfg_txpwr_ul_tb_offset(struct rtw89_dev *rtwdev,
6546 struct rtw89_vif_link *rtwvif_link)
6547 {
6548 struct ieee80211_vif *vif = rtwvif_link_to_vif(rtwvif_link);
6549 const struct rtw89_chip_info *chip = rtwdev->chip;
6550 struct ieee80211_bss_conf *bss_conf;
6551
6552 rcu_read_lock();
6553
6554 bss_conf = rtw89_vif_rcu_dereference_link(rtwvif_link, false);
6555 if (!bss_conf->he_support || !vif->cfg.assoc) {
6556 rcu_read_unlock();
6557 return;
6558 }
6559
6560 rcu_read_unlock();
6561
6562 if (chip->ops->set_txpwr_ul_tb_offset)
6563 chip->ops->set_txpwr_ul_tb_offset(rtwdev, 0, rtwvif_link->mac_idx);
6564 }
6565
rtw89_core_register_hw(struct rtw89_dev * rtwdev)6566 static int rtw89_core_register_hw(struct rtw89_dev *rtwdev)
6567 {
6568 const struct rtw89_chip_info *chip = rtwdev->chip;
6569 u8 n = rtwdev->support_mlo ? chip->support_link_num : 1;
6570 struct ieee80211_hw *hw = rtwdev->hw;
6571 struct rtw89_efuse *efuse = &rtwdev->efuse;
6572 struct rtw89_hal *hal = &rtwdev->hal;
6573 int ret;
6574 int tx_headroom = IEEE80211_HT_CTL_LEN;
6575
6576 if (rtwdev->hci.type == RTW89_HCI_TYPE_USB)
6577 tx_headroom += chip->txwd_body_size + chip->txwd_info_size;
6578
6579 hw->vif_data_size = struct_size_t(struct rtw89_vif, links_inst, n);
6580 hw->sta_data_size = struct_size_t(struct rtw89_sta, links_inst, n);
6581 hw->txq_data_size = sizeof(struct rtw89_txq);
6582 hw->chanctx_data_size = sizeof(struct rtw89_chanctx_cfg);
6583
6584 SET_IEEE80211_PERM_ADDR(hw, efuse->addr);
6585
6586 hw->extra_tx_headroom = tx_headroom;
6587 hw->queues = IEEE80211_NUM_ACS;
6588 hw->max_rx_aggregation_subframes = chip->max_rx_agg_num;
6589 hw->max_tx_aggregation_subframes = chip->max_tx_agg_num;
6590 hw->uapsd_max_sp_len = IEEE80211_WMM_IE_STA_QOSINFO_SP_ALL;
6591
6592 hw->radiotap_mcs_details |= IEEE80211_RADIOTAP_MCS_HAVE_FEC |
6593 IEEE80211_RADIOTAP_MCS_HAVE_STBC;
6594 hw->radiotap_vht_details |= IEEE80211_RADIOTAP_VHT_KNOWN_STBC;
6595
6596 ieee80211_hw_set(hw, SIGNAL_DBM);
6597 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6598 ieee80211_hw_set(hw, MFP_CAPABLE);
6599 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
6600 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
6601 ieee80211_hw_set(hw, RX_INCLUDES_FCS);
6602 ieee80211_hw_set(hw, TX_AMSDU);
6603 ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
6604 ieee80211_hw_set(hw, SUPPORTS_AMSDU_IN_AMPDU);
6605 ieee80211_hw_set(hw, SUPPORTS_PS);
6606 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS);
6607 ieee80211_hw_set(hw, SINGLE_SCAN_ON_ALL_BANDS);
6608 ieee80211_hw_set(hw, SUPPORTS_MULTI_BSSID);
6609 ieee80211_hw_set(hw, WANT_MONITOR_VIF);
6610 ieee80211_hw_set(hw, CHANCTX_STA_CSA);
6611
6612 if (chip->support_bandwidths & BIT(NL80211_CHAN_WIDTH_160))
6613 ieee80211_hw_set(hw, SUPPORTS_VHT_EXT_NSS_BW);
6614
6615 if (RTW89_CHK_FW_FEATURE(BEACON_FILTER, &rtwdev->fw))
6616 ieee80211_hw_set(hw, CONNECTION_MONITOR);
6617
6618 if (RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &rtwdev->fw))
6619 ieee80211_hw_set(hw, AP_LINK_PS);
6620
6621 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
6622 BIT(NL80211_IFTYPE_AP) |
6623 BIT(NL80211_IFTYPE_P2P_CLIENT) |
6624 BIT(NL80211_IFTYPE_P2P_GO);
6625
6626 if (hal->ant_diversity) {
6627 hw->wiphy->available_antennas_tx = 0x3;
6628 hw->wiphy->available_antennas_rx = 0x3;
6629 } else {
6630 hw->wiphy->available_antennas_tx = BIT(rtwdev->chip->rf_path_num) - 1;
6631 hw->wiphy->available_antennas_rx = BIT(rtwdev->chip->rf_path_num) - 1;
6632 }
6633
6634 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS |
6635 WIPHY_FLAG_TDLS_EXTERNAL_SETUP |
6636 WIPHY_FLAG_AP_UAPSD |
6637 WIPHY_FLAG_HAS_CHANNEL_SWITCH |
6638 WIPHY_FLAG_SUPPORTS_EXT_KEK_KCK;
6639
6640 if (!chip->support_rnr)
6641 hw->wiphy->flags |= WIPHY_FLAG_SPLIT_SCAN_6GHZ;
6642
6643 if (chip->chip_gen == RTW89_CHIP_BE)
6644 hw->wiphy->flags |= WIPHY_FLAG_DISABLE_WEXT;
6645
6646 if (rtwdev->support_mlo) {
6647 hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_MLO;
6648 hw->wiphy->iftype_ext_capab = rtw89_iftypes_ext_capa;
6649 hw->wiphy->num_iftype_ext_capab = ARRAY_SIZE(rtw89_iftypes_ext_capa);
6650 }
6651
6652 hw->wiphy->features |= NL80211_FEATURE_SCAN_RANDOM_MAC_ADDR;
6653
6654 hw->wiphy->max_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
6655 hw->wiphy->max_scan_ie_len = RTW89_SCANOFLD_MAX_IE_LEN;
6656
6657 #ifdef CONFIG_PM
6658 hw->wiphy->wowlan = rtwdev->chip->wowlan_stub;
6659 hw->wiphy->max_sched_scan_ssids = RTW89_SCANOFLD_MAX_SSID;
6660 #endif
6661
6662 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
6663 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMPDU_CTRL);
6664 hw->wiphy->tid_config_support.vif |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
6665 hw->wiphy->tid_config_support.peer |= BIT(NL80211_TID_CONFIG_ATTR_AMSDU_CTRL);
6666 hw->wiphy->max_remain_on_channel_duration = 1000;
6667
6668 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
6669 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SCAN_RANDOM_SN);
6670 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_SET_SCAN_DWELL);
6671
6672 ret = rtw89_core_set_supported_band(rtwdev);
6673 if (ret) {
6674 rtw89_err(rtwdev, "failed to set supported band\n");
6675 return ret;
6676 }
6677
6678 ret = rtw89_regd_setup(rtwdev);
6679 if (ret) {
6680 rtw89_err(rtwdev, "failed to set up regd\n");
6681 return ret;
6682 }
6683
6684 hw->wiphy->sar_capa = &rtw89_sar_capa;
6685
6686 ret = ieee80211_register_hw(hw);
6687 if (ret) {
6688 rtw89_err(rtwdev, "failed to register hw\n");
6689 return ret;
6690 }
6691
6692 ret = rtw89_regd_init_hint(rtwdev);
6693 if (ret) {
6694 rtw89_err(rtwdev, "failed to init regd\n");
6695 goto err_unregister_hw;
6696 }
6697
6698 rtw89_rfkill_polling_init(rtwdev);
6699
6700 return 0;
6701
6702 err_unregister_hw:
6703 ieee80211_unregister_hw(hw);
6704
6705 return ret;
6706 }
6707
rtw89_core_unregister_hw(struct rtw89_dev * rtwdev)6708 static void rtw89_core_unregister_hw(struct rtw89_dev *rtwdev)
6709 {
6710 struct ieee80211_hw *hw = rtwdev->hw;
6711
6712 rtw89_rfkill_polling_deinit(rtwdev);
6713 ieee80211_unregister_hw(hw);
6714 }
6715
rtw89_core_register(struct rtw89_dev * rtwdev)6716 int rtw89_core_register(struct rtw89_dev *rtwdev)
6717 {
6718 int ret;
6719
6720 ret = rtw89_core_register_hw(rtwdev);
6721 if (ret) {
6722 rtw89_err(rtwdev, "failed to register core hw\n");
6723 return ret;
6724 }
6725
6726 rtw89_phy_dm_init_data(rtwdev);
6727 rtw89_debugfs_init(rtwdev);
6728
6729 return 0;
6730 }
6731 EXPORT_SYMBOL(rtw89_core_register);
6732
rtw89_core_unregister(struct rtw89_dev * rtwdev)6733 void rtw89_core_unregister(struct rtw89_dev *rtwdev)
6734 {
6735 rtw89_core_unregister_hw(rtwdev);
6736
6737 rtw89_debugfs_deinit(rtwdev);
6738 }
6739 EXPORT_SYMBOL(rtw89_core_unregister);
6740
rtw89_alloc_ieee80211_hw(struct device * device,u32 bus_data_size,const struct rtw89_chip_info * chip,const struct rtw89_chip_variant * variant)6741 struct rtw89_dev *rtw89_alloc_ieee80211_hw(struct device *device,
6742 u32 bus_data_size,
6743 const struct rtw89_chip_info *chip,
6744 const struct rtw89_chip_variant *variant)
6745 {
6746 struct rtw89_fw_info early_fw = {};
6747 const struct firmware *firmware;
6748 struct ieee80211_hw *hw;
6749 struct rtw89_dev *rtwdev;
6750 struct ieee80211_ops *ops;
6751 u32 driver_data_size;
6752 int fw_format = -1;
6753 bool support_mlo;
6754 bool no_chanctx;
6755
6756 firmware = rtw89_early_fw_feature_recognize(device, chip, &early_fw, &fw_format);
6757
6758 ops = kmemdup(&rtw89_ops, sizeof(rtw89_ops), GFP_KERNEL);
6759 if (!ops)
6760 goto err;
6761
6762 no_chanctx = chip->support_chanctx_num == 0 ||
6763 !RTW89_CHK_FW_FEATURE(SCAN_OFFLOAD, &early_fw) ||
6764 !RTW89_CHK_FW_FEATURE(BEACON_FILTER, &early_fw);
6765
6766 if (no_chanctx) {
6767 ops->add_chanctx = ieee80211_emulate_add_chanctx;
6768 ops->remove_chanctx = ieee80211_emulate_remove_chanctx;
6769 ops->change_chanctx = ieee80211_emulate_change_chanctx;
6770 ops->switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx;
6771 ops->assign_vif_chanctx = NULL;
6772 ops->unassign_vif_chanctx = NULL;
6773 ops->remain_on_channel = NULL;
6774 ops->cancel_remain_on_channel = NULL;
6775 }
6776
6777 if (!chip->support_noise)
6778 ops->get_survey = NULL;
6779
6780 driver_data_size = sizeof(struct rtw89_dev) + bus_data_size;
6781 hw = ieee80211_alloc_hw(driver_data_size, ops);
6782 if (!hw)
6783 goto err;
6784
6785 /* Currently, our AP_LINK_PS handling only works for non-MLD softap
6786 * or MLD-single-link softap. If RTW89_MLD_NON_STA_LINK_NUM enlarges,
6787 * please tweak entire AP_LINKS_PS handling before supporting MLO.
6788 */
6789 support_mlo = !no_chanctx && chip->support_link_num &&
6790 RTW89_CHK_FW_FEATURE(NOTIFY_AP_INFO, &early_fw) &&
6791 RTW89_MLD_NON_STA_LINK_NUM == 1;
6792
6793 hw->wiphy->iface_combinations = rtw89_iface_combs;
6794
6795 if (no_chanctx || chip->support_chanctx_num == 1)
6796 hw->wiphy->n_iface_combinations = 1;
6797 else
6798 hw->wiphy->n_iface_combinations = ARRAY_SIZE(rtw89_iface_combs);
6799
6800 rtwdev = hw->priv;
6801 rtwdev->hw = hw;
6802 rtwdev->dev = device;
6803 rtwdev->ops = ops;
6804 rtwdev->chip = chip;
6805 rtwdev->variant = variant;
6806 rtwdev->fw.req.firmware = firmware;
6807 rtwdev->fw.fw_format = fw_format;
6808 rtwdev->support_mlo = support_mlo;
6809
6810 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s chanctx\n",
6811 no_chanctx ? "without" : "with");
6812 rtw89_debug(rtwdev, RTW89_DBG_CHAN, "probe driver %s MLO cap\n",
6813 support_mlo ? "with" : "without");
6814
6815 return rtwdev;
6816
6817 err:
6818 kfree(ops);
6819 release_firmware(firmware);
6820 return NULL;
6821 }
6822 EXPORT_SYMBOL(rtw89_alloc_ieee80211_hw);
6823
rtw89_free_ieee80211_hw(struct rtw89_dev * rtwdev)6824 void rtw89_free_ieee80211_hw(struct rtw89_dev *rtwdev)
6825 {
6826 kfree(rtwdev->ops);
6827 kfree(rtwdev->rfe_data);
6828 release_firmware(rtwdev->fw.req.firmware);
6829 ieee80211_free_hw(rtwdev->hw);
6830 }
6831 EXPORT_SYMBOL(rtw89_free_ieee80211_hw);
6832
6833 MODULE_AUTHOR("Realtek Corporation");
6834 MODULE_DESCRIPTION("Realtek 802.11ax wireless core module");
6835 MODULE_LICENSE("Dual BSD/GPL");
6836