1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Thunderbolt driver - NHI driver 4 * 5 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> 6 * Copyright (C) 2018, Intel Corporation 7 */ 8 9 #ifndef DSL3510_H_ 10 #define DSL3510_H_ 11 12 #include <linux/thunderbolt.h> 13 14 enum nhi_fw_mode { 15 NHI_FW_SAFE_MODE, 16 NHI_FW_AUTH_MODE, 17 NHI_FW_EP_MODE, 18 NHI_FW_CM_MODE, 19 }; 20 21 enum nhi_mailbox_cmd { 22 NHI_MAILBOX_SAVE_DEVS = 0x05, 23 NHI_MAILBOX_DISCONNECT_PCIE_PATHS = 0x06, 24 NHI_MAILBOX_DRV_UNLOADS = 0x07, 25 NHI_MAILBOX_DISCONNECT_PA = 0x10, 26 NHI_MAILBOX_DISCONNECT_PB = 0x11, 27 NHI_MAILBOX_ALLOW_ALL_DEVS = 0x23, 28 }; 29 30 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data); 31 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi); 32 void nhi_enable_int_throttling(struct tb_nhi *nhi); 33 void nhi_disable_interrupts(struct tb_nhi *nhi); 34 void nhi_interrupt_work(struct work_struct *work); 35 irqreturn_t nhi_msi(int irq, void *data); 36 irqreturn_t ring_msix(int irq, void *data); 37 int nhi_probe(struct tb_nhi *nhi); 38 void nhi_shutdown(struct tb_nhi *nhi); 39 extern const struct dev_pm_ops nhi_pm_ops; 40 41 /** 42 * struct tb_nhi_ops - NHI specific optional operations 43 * @init: NHI specific initialization 44 * @add_links: Setup device links for tunneling native protocols 45 * @suspend_noirq: NHI specific suspend_noirq hook 46 * @resume_noirq: NHI specific resume_noirq hook 47 * @runtime_suspend: NHI specific runtime_suspend hook 48 * @runtime_resume: NHI specific runtime_resume hook 49 * @shutdown: NHI specific shutdown 50 * @pre_nvm_auth: hook to run before Thunderbolt 3 NVM authentication 51 * @post_nvm_auth: hook to run after Thunderbolt 3 NVM authentication 52 * @request_ring_irq: NHI specific interrupt retrieval hook 53 * @release_ring_irq: NHI specific interrupt release hook 54 * @is_present: Whether the device is currently present on the parent bus 55 * @init_interrupts: NHI specific interrupt initialization hook 56 */ 57 struct tb_nhi_ops { 58 int (*init)(struct tb_nhi *nhi); 59 bool (*add_links)(struct tb_nhi *nhi); 60 int (*suspend_noirq)(struct tb_nhi *nhi, bool wakeup); 61 int (*resume_noirq)(struct tb_nhi *nhi); 62 int (*runtime_suspend)(struct tb_nhi *nhi); 63 int (*runtime_resume)(struct tb_nhi *nhi); 64 void (*shutdown)(struct tb_nhi *nhi); 65 void (*pre_nvm_auth)(struct tb_nhi *nhi); 66 void (*post_nvm_auth)(struct tb_nhi *nhi); 67 int (*request_ring_irq)(struct tb_ring *ring, bool no_suspend); 68 void (*release_ring_irq)(struct tb_ring *ring); 69 bool (*is_present)(struct tb_nhi *nhi); 70 int (*init_interrupts)(struct tb_nhi *nhi); 71 }; 72 73 /* 74 * PCI IDs used in this driver from Win Ridge forward. There is no 75 * need for the PCI quirk anymore as we will use ICM also on Apple 76 * hardware. 77 */ 78 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_2C_NHI 0x1134 79 #define PCI_DEVICE_ID_INTEL_MAPLE_RIDGE_4C_NHI 0x1137 80 #define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_NHI 0x157d 81 #define PCI_DEVICE_ID_INTEL_WIN_RIDGE_2C_BRIDGE 0x157e 82 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI 0x15bf 83 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_BRIDGE 0x15c0 84 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI 0x15d2 85 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_BRIDGE 0x15d3 86 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI 0x15d9 87 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_BRIDGE 0x15da 88 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI 0x15dc 89 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI 0x15dd 90 #define PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI 0x15de 91 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_BRIDGE 0x15e7 92 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI 0x15e8 93 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_BRIDGE 0x15ea 94 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI 0x15eb 95 #define PCI_DEVICE_ID_INTEL_TITAN_RIDGE_DD_BRIDGE 0x15ef 96 #define PCI_DEVICE_ID_INTEL_ADL_NHI0 0x463e 97 #define PCI_DEVICE_ID_INTEL_ADL_NHI1 0x466d 98 #define PCI_DEVICE_ID_INTEL_WCL_NHI0 0x4d33 99 #define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI 0x5781 100 #define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI 0x5784 101 #define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_80G_BRIDGE 0x5786 102 #define PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_40G_BRIDGE 0x57a4 103 #define PCI_DEVICE_ID_INTEL_MTL_M_NHI0 0x7eb2 104 #define PCI_DEVICE_ID_INTEL_MTL_P_NHI0 0x7ec2 105 #define PCI_DEVICE_ID_INTEL_MTL_P_NHI1 0x7ec3 106 #define PCI_DEVICE_ID_INTEL_ICL_NHI1 0x8a0d 107 #define PCI_DEVICE_ID_INTEL_ICL_NHI0 0x8a17 108 #define PCI_DEVICE_ID_INTEL_TGL_NHI0 0x9a1b 109 #define PCI_DEVICE_ID_INTEL_TGL_NHI1 0x9a1d 110 #define PCI_DEVICE_ID_INTEL_TGL_H_NHI0 0x9a1f 111 #define PCI_DEVICE_ID_INTEL_TGL_H_NHI1 0x9a21 112 #define PCI_DEVICE_ID_INTEL_RPL_NHI0 0xa73e 113 #define PCI_DEVICE_ID_INTEL_RPL_NHI1 0xa76d 114 #define PCI_DEVICE_ID_INTEL_LNL_NHI0 0xa833 115 #define PCI_DEVICE_ID_INTEL_LNL_NHI1 0xa834 116 #define PCI_DEVICE_ID_INTEL_PTL_M_NHI0 0xe333 117 #define PCI_DEVICE_ID_INTEL_PTL_M_NHI1 0xe334 118 #define PCI_DEVICE_ID_INTEL_PTL_P_NHI0 0xe433 119 #define PCI_DEVICE_ID_INTEL_PTL_P_NHI1 0xe434 120 121 #define PCI_CLASS_SERIAL_USB_USB4 0x0c0340 122 123 /* Host interface quirks */ 124 #define QUIRK_AUTO_CLEAR_INT BIT(0) 125 #define QUIRK_E2E BIT(1) 126 127 /* 128 * Minimal number of vectors when we use MSI-X. Two for control channel 129 * Rx/Tx and the rest four are for cross domain DMA paths. 130 */ 131 #define MSIX_MIN_VECS 6 132 #define MSIX_MAX_VECS 16 133 134 #endif 135