1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4 */
5
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
21 #include <linux/usb/typec.h>
22 #include <linux/usb/typec_dp.h>
23 #include <linux/usb/typec_mux.h>
24
25 #include <drm/bridge/aux-bridge.h>
26
27 #include <dt-bindings/phy/phy-qcom-qmp.h>
28
29 #include "phy-qcom-qmp-common.h"
30
31 #include "phy-qcom-qmp.h"
32 #include "phy-qcom-qmp-pcs-misc-v3.h"
33 #include "phy-qcom-qmp-pcs-usb-v4.h"
34 #include "phy-qcom-qmp-pcs-usb-v5.h"
35 #include "phy-qcom-qmp-pcs-usb-v6.h"
36 #include "phy-qcom-qmp-pcs-usb-v8.h"
37
38 #include "phy-qcom-qmp-dp-com-v3.h"
39
40 #include "phy-qcom-qmp-dp-phy.h"
41 #include "phy-qcom-qmp-dp-phy-v3.h"
42 #include "phy-qcom-qmp-dp-phy-v4.h"
43 #include "phy-qcom-qmp-dp-phy-v5.h"
44 #include "phy-qcom-qmp-dp-phy-v6.h"
45
46 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
47 /* DP PHY soft reset */
48 #define SW_DPPHY_RESET BIT(0)
49 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
50 #define SW_DPPHY_RESET_MUX BIT(1)
51 /* USB3 PHY soft reset */
52 #define SW_USB3PHY_RESET BIT(2)
53 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
54 #define SW_USB3PHY_RESET_MUX BIT(3)
55
56 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
57 #define USB3_MODE BIT(0) /* enables USB3 mode */
58 #define DP_MODE BIT(1) /* enables DP mode */
59
60 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */
61 #define SW_PORTSELECT_VAL BIT(0)
62 #define SW_PORTSELECT_MUX BIT(1)
63
64 #define PHY_INIT_COMPLETE_TIMEOUT 10000
65
66 enum qmpphy_mode {
67 QMPPHY_MODE_USB3DP = 0,
68 QMPPHY_MODE_DP_ONLY,
69 QMPPHY_MODE_USB3_ONLY,
70 };
71
72 /* set of registers with offsets different per-PHY */
73 enum qphy_reg_layout {
74 /* PCS registers */
75 QPHY_SW_RESET,
76 QPHY_START_CTRL,
77 QPHY_PCS_STATUS,
78 QPHY_PCS_AUTONOMOUS_MODE_CTRL,
79 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
80 QPHY_PCS_POWER_DOWN_CONTROL,
81
82 QPHY_COM_RESETSM_CNTRL,
83 QPHY_COM_C_READY_STATUS,
84 QPHY_COM_CMN_STATUS,
85 QPHY_COM_BIAS_EN_CLKBUFLR_EN,
86
87 QPHY_DP_PHY_STATUS,
88 QPHY_DP_PHY_VCO_DIV,
89
90 QPHY_TX_TX_POL_INV,
91 QPHY_TX_TX_DRV_LVL,
92 QPHY_TX_TX_EMP_POST1_LVL,
93 QPHY_TX_HIGHZ_DRVR_EN,
94 QPHY_TX_TRANSCEIVER_BIAS_EN,
95
96 /* Keep last to ensure regs_layout arrays are properly initialized */
97 QPHY_LAYOUT_SIZE
98 };
99
100 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
101 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET,
102 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL,
103 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS,
104 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL,
105 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
106 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
107
108 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V3_COM_RESETSM_CNTRL,
109 [QPHY_COM_C_READY_STATUS] = QSERDES_V3_COM_C_READY_STATUS,
110 [QPHY_COM_CMN_STATUS] = QSERDES_V3_COM_CMN_STATUS,
111 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN,
112
113 [QPHY_DP_PHY_STATUS] = QSERDES_V3_DP_PHY_STATUS,
114 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V3_DP_PHY_VCO_DIV,
115
116 [QPHY_TX_TX_POL_INV] = QSERDES_V3_TX_TX_POL_INV,
117 [QPHY_TX_TX_DRV_LVL] = QSERDES_V3_TX_TX_DRV_LVL,
118 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V3_TX_TX_EMP_POST1_LVL,
119 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V3_TX_HIGHZ_DRVR_EN,
120 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V3_TX_TRANSCEIVER_BIAS_EN,
121 };
122
123 static const unsigned int qmp_v45_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
124 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET,
125 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL,
126 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1,
127 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL,
128
129 /* In PCS_USB */
130 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
131 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
132
133 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V4_COM_RESETSM_CNTRL,
134 [QPHY_COM_C_READY_STATUS] = QSERDES_V4_COM_C_READY_STATUS,
135 [QPHY_COM_CMN_STATUS] = QSERDES_V4_COM_CMN_STATUS,
136 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN,
137
138 [QPHY_DP_PHY_STATUS] = QSERDES_V4_DP_PHY_STATUS,
139 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V4_DP_PHY_VCO_DIV,
140
141 [QPHY_TX_TX_POL_INV] = QSERDES_V4_TX_TX_POL_INV,
142 [QPHY_TX_TX_DRV_LVL] = QSERDES_V4_TX_TX_DRV_LVL,
143 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V4_TX_TX_EMP_POST1_LVL,
144 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V4_TX_HIGHZ_DRVR_EN,
145 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V4_TX_TRANSCEIVER_BIAS_EN,
146 };
147
148 static const unsigned int qmp_v5_5nm_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
149 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET,
150 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL,
151 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1,
152 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL,
153
154 /* In PCS_USB */
155 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
156 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
157
158 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V5_COM_RESETSM_CNTRL,
159 [QPHY_COM_C_READY_STATUS] = QSERDES_V5_COM_C_READY_STATUS,
160 [QPHY_COM_CMN_STATUS] = QSERDES_V5_COM_CMN_STATUS,
161 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN,
162
163 [QPHY_DP_PHY_STATUS] = QSERDES_V5_DP_PHY_STATUS,
164 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V5_DP_PHY_VCO_DIV,
165
166 [QPHY_TX_TX_POL_INV] = QSERDES_V5_5NM_TX_TX_POL_INV,
167 [QPHY_TX_TX_DRV_LVL] = QSERDES_V5_5NM_TX_TX_DRV_LVL,
168 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V5_5NM_TX_TX_EMP_POST1_LVL,
169 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V5_5NM_TX_HIGHZ_DRVR_EN,
170 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN,
171 };
172
173 static const unsigned int qmp_v6_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
174 [QPHY_SW_RESET] = QPHY_V6_PCS_SW_RESET,
175 [QPHY_START_CTRL] = QPHY_V6_PCS_START_CONTROL,
176 [QPHY_PCS_STATUS] = QPHY_V6_PCS_PCS_STATUS1,
177 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_PCS_POWER_DOWN_CONTROL,
178
179 /* In PCS_USB */
180 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
181 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
182
183 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL,
184 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS,
185 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS,
186 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN,
187
188 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS,
189 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV,
190
191 [QPHY_TX_TX_POL_INV] = QSERDES_V6_TX_TX_POL_INV,
192 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_TX_TX_DRV_LVL,
193 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_TX_TX_EMP_POST1_LVL,
194 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_TX_HIGHZ_DRVR_EN,
195 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_TX_TRANSCEIVER_BIAS_EN,
196 };
197
198 static const unsigned int qmp_v6_n4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
199 [QPHY_SW_RESET] = QPHY_V6_N4_PCS_SW_RESET,
200 [QPHY_START_CTRL] = QPHY_V6_N4_PCS_START_CONTROL,
201 [QPHY_PCS_STATUS] = QPHY_V6_N4_PCS_PCS_STATUS1,
202 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V6_N4_PCS_POWER_DOWN_CONTROL,
203
204 /* In PCS_USB */
205 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V6_PCS_USB3_AUTONOMOUS_MODE_CTRL,
206 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V6_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
207
208 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V6_COM_RESETSM_CNTRL,
209 [QPHY_COM_C_READY_STATUS] = QSERDES_V6_COM_C_READY_STATUS,
210 [QPHY_COM_CMN_STATUS] = QSERDES_V6_COM_CMN_STATUS,
211 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN,
212
213 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS,
214 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV,
215
216 [QPHY_TX_TX_POL_INV] = QSERDES_V6_N4_TX_TX_POL_INV,
217 [QPHY_TX_TX_DRV_LVL] = QSERDES_V6_N4_TX_TX_DRV_LVL,
218 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V6_N4_TX_TX_EMP_POST1_LVL,
219 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V6_N4_TX_HIGHZ_DRVR_EN,
220 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V6_N4_TX_TRANSCEIVER_BIAS_EN,
221 };
222
223 static const unsigned int qmp_v8_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
224 [QPHY_SW_RESET] = QPHY_V8_PCS_SW_RESET,
225 [QPHY_START_CTRL] = QPHY_V8_PCS_START_CONTROL,
226 [QPHY_PCS_STATUS] = QPHY_V8_PCS_PCS_STATUS1,
227 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V8_PCS_POWER_DOWN_CONTROL,
228
229 /* In PCS_USB */
230 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V8_PCS_USB_AUTONOMOUS_MODE_CTRL,
231 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V8_PCS_USB_LFPS_RXTERM_IRQ_CLEAR,
232
233 [QPHY_COM_RESETSM_CNTRL] = QSERDES_V8_COM_RESETSM_CNTRL,
234 [QPHY_COM_C_READY_STATUS] = QSERDES_V8_COM_C_READY_STATUS,
235 [QPHY_COM_CMN_STATUS] = QSERDES_V8_COM_CMN_STATUS,
236 [QPHY_COM_BIAS_EN_CLKBUFLR_EN] = QSERDES_V8_COM_BIAS_EN_CLKBUFLR_EN,
237
238 [QPHY_DP_PHY_STATUS] = QSERDES_V6_DP_PHY_STATUS,
239 [QPHY_DP_PHY_VCO_DIV] = QSERDES_V6_DP_PHY_VCO_DIV,
240
241 [QPHY_TX_TX_POL_INV] = QSERDES_V8_TX_TX_POL_INV,
242 [QPHY_TX_TX_DRV_LVL] = QSERDES_V8_TX_TX_DRV_LVL,
243 [QPHY_TX_TX_EMP_POST1_LVL] = QSERDES_V8_TX_TX_EMP_POST1_LVL,
244 [QPHY_TX_HIGHZ_DRVR_EN] = QSERDES_V8_TX_HIGHZ_DRVR_EN,
245 [QPHY_TX_TRANSCEIVER_BIAS_EN] = QSERDES_V8_TX_TRANSCEIVER_BIAS_EN,
246 };
247
248 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
249 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
250 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
251 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
252 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
253 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
254 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
255 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
256 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
257 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
258 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
259 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
260 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
261 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
262 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
263 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
264 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
265 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
266 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
267 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
268 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
269 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
270 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
271 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
272 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
273 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
274 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
275 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
276 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
277 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
278 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
279 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
280 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
281 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
282 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
283 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
284 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
285 };
286
287 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
288 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
289 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
290 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
291 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
292 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
293 };
294
295 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl[] = {
296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x37),
298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
299 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_ENABLE1, 0x0e),
300 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x06),
301 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x02),
303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0x00),
304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
310 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_CTRL, 0x00),
311 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x3f),
312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x1f),
313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
317 };
318
319 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_rbr[] = {
320 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x0c),
321 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
322 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
323 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
324 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x6f),
325 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x08),
326 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
327 };
328
329 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr[] = {
330 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x04),
331 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
332 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
333 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
334 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x0f),
335 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x0e),
336 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
337 };
338
339 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr2[] = {
340 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x00),
341 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x8c),
342 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x00),
343 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x0a),
344 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x1f),
345 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x1c),
346 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x00),
347 };
348
349 static const struct qmp_phy_init_tbl qmp_v3_dp_serdes_tbl_hbr3[] = {
350 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x03),
351 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x69),
352 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0x80),
353 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x07),
354 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x2f),
355 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x2a),
356 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x08),
357 };
358
359 static const struct qmp_phy_init_tbl qmp_v3_dp_tx_tbl[] = {
360 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRANSCEIVER_BIAS_EN, 0x1a),
361 QMP_PHY_INIT_CFG(QSERDES_V3_TX_VMODE_CTRL1, 0x40),
362 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
363 QMP_PHY_INIT_CFG(QSERDES_V3_TX_INTERFACE_SELECT, 0x3d),
364 QMP_PHY_INIT_CFG(QSERDES_V3_TX_CLKBUF_ENABLE, 0x0f),
365 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RESET_TSYNC_EN, 0x03),
366 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TRAN_DRVR_EMP_EN, 0x03),
367 QMP_PHY_INIT_CFG(QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
368 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_INTERFACE_MODE, 0x00),
369 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_BAND, 0x4),
370 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_POL_INV, 0x0a),
371 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_DRV_LVL, 0x38),
372 QMP_PHY_INIT_CFG(QSERDES_V3_TX_TX_EMP_POST1_LVL, 0x20),
373 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
374 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
375 };
376
377 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
378 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
379 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
380 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
381 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
382 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
383 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
384 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
385 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
386 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
387 };
388
389 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
390 /* FLL settings */
391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
392 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
393 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
394 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
395 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
396
397 /* Lock Det settings */
398 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
399 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
400 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
401 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
402
403 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
404 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
405 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
406 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
407 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
408 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
409 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
410 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
411 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
412 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
413 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
414 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
415 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
416 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
417 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
418 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
419 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
420 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
421 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
422
423 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
424 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
425 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
426 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
427 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
428 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
429 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
430 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
431 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
432 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
434 };
435
436 static const struct qmp_phy_init_tbl sar2130p_usb3_serdes_tbl[] = {
437 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0x55),
438 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x0e),
439 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
440 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
441 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
442 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
443 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x2e),
444 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x82),
445 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x04),
446 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x01),
447 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
448 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0xd5),
449 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x05),
450 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
451 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
452 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
453 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xb7),
454 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
455 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xb7),
456 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
457 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x55),
458 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x0e),
459 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
460 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
461 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
462 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x12),
463 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x34),
464 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x04),
465 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x01),
466 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
467 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xd5),
468 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
469 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
470 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
471 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0e),
472 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
473 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x31),
474 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x01),
475 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c),
476 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
477 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
478 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
479 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
480 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x04),
481 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
482 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
483 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
484 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
485 };
486
487 static const struct qmp_phy_init_tbl sm6350_usb3_rx_tbl[] = {
488 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
489 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
490 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
491 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
492 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
493 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
494 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
495 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
496 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
497 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
498 };
499
500 static const struct qmp_phy_init_tbl sm6350_usb3_pcs_tbl[] = {
501 /* FLL settings */
502 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
503 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
504 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
505 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
506 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
507
508 /* Lock Det settings */
509 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
510 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
511 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
512 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
513
514 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xcc),
515 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
516 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
517 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
518 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
519 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
520 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
521 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
522 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
523 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
524 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
525 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
526 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
527 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
528 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
529 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
530 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
531 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
532 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
533
534 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
535 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
536 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
537 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
538 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
539 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
540 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
541 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
542 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
543 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
544 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
545 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_DET_HIGH_COUNT_VAL, 0x04),
546
547 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
548 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
549 };
550
551 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
552 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
553 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
554 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
555 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
556 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
557 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
558 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
559 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
560 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
561 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
562 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
563 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
564 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
565 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
566 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
567 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
568 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
569 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
570 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
571 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
572 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
573 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
574 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
575 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
576 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
577 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
578 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
579 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
580 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
581 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
582 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
583 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
584 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
585 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
586 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
587 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
588 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
589 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
590 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
591 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
592 };
593
594 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
595 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
596 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
597 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
598 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
599 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
600 };
601
602 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
603 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
604 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
605 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
606 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
607 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
608 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
609 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
610 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
611 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
612 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
613 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
614 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
615 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
616 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
617 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
618 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
619 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
620 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
621 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
622 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
623 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
624 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
625 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
626 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
627 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
628 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
629 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
630 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
631 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
632 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
633 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
634 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
635 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
636 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
637 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
638 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
639 };
640
641 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
642 /* Lock Det settings */
643 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
644 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
645 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
646
647 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
648 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
649 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
650 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
651 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
652 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
653 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
654 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
655 };
656
657 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
658 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
659 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
660 };
661
662 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
663 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
664 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
665 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
666 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
667 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
668 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
669 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
670 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
671 };
672
673 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
694 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
695 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
696 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
697 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
702 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
703 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
704 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
705 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
706 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
707 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
708 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
709 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
710 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
711 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
712 };
713
714 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
715 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
718 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
719 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
720 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
721 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
722 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
723 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
724 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
725 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
726 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
727 };
728
729 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
730 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
731 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
732 };
733
734 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
735 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
736 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
737 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
738 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
739 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
740 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
741 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
742 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
743 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
744 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
745 };
746
747 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
748 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
749 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
750 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
751 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
752 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
753 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
754 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
755 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
756 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
757 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
758 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
759 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
760 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
761 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
762 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
763 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
764 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
765 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
766 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
767 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
768 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
769 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
770 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
771 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
772 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
773 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
774 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
775 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
776 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
777 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
778 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
779 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
780 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
781 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
782 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
783 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
784 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
785 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
786 };
787
788 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
789 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
790 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
791 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
792 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
793 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
794 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
795 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
796 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
797 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
798 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
799 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
800 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
801 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
802 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
803 };
804
805 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
806 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
807 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
808 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
809 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
810 };
811
812 static const struct qmp_phy_init_tbl sm8550_usb3_serdes_tbl[] = {
813 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
814 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x01),
815 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
816 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
817 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
818 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
819 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
820 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
821 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x41),
822 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
823 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
824 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x75),
825 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x01),
826 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
827 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0x25),
828 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x02),
829 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
830 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
831 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
832 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
833 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
834 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
835 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
836 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
837 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
838 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
839 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
840 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x41),
841 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
842 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
843 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x75),
844 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x01),
845 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0x25),
846 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x02),
847 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
848 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
849 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
850 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
851 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0c),
852 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
853 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x14),
854 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x04),
855 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x20),
856 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x16),
857 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
858 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4b),
859 QMP_PHY_INIT_CFG(QSERDES_V6_COM_AUTO_GAIN_ADJ_CTRL_3, 0x37),
860 QMP_PHY_INIT_CFG(QSERDES_V6_COM_ADDITIONAL_MISC, 0x0c),
861 };
862
863 static const struct qmp_phy_init_tbl sm8550_usb3_tx_tbl[] = {
864 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_TX, 0x00),
865 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_RX, 0x00),
866 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
867 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
868 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_1, 0xf5),
869 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_3, 0x3f),
870 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_4, 0x3f),
871 QMP_PHY_INIT_CFG(QSERDES_V6_TX_LANE_MODE_5, 0x5f),
872 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RCV_DETECT_LVL_2, 0x12),
873 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x21, 1),
874 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_TX_PI_QEC_CTRL, 0x05, 2),
875 };
876
877 static const struct qmp_phy_init_tbl sm8550_usb3_rx_tbl[] = {
878 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FO_GAIN, 0x0a),
879 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_GAIN, 0x06),
880 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
881 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
882 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
883 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
884 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_PI_CONTROLS, 0x99),
885 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH1, 0x08),
886 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_THRESH2, 0x08),
887 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN1, 0x00),
888 QMP_PHY_INIT_CFG(QSERDES_V6_RX_UCDR_SB2_GAIN2, 0x0a),
889 QMP_PHY_INIT_CFG(QSERDES_V6_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
890 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL1, 0x54),
891 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VGA_CAL_CNTRL2, 0x0f),
892 QMP_PHY_INIT_CFG(QSERDES_V6_RX_GM_CAL, 0x13),
893 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
894 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
895 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
896 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_LOW, 0x07),
897 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
898 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
899 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CNTRL, 0x04),
900 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
901 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_LOW, 0xdc),
902 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH, 0x5c),
903 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH2, 0x9c),
904 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH3, 0x1d),
905 QMP_PHY_INIT_CFG(QSERDES_V6_RX_RX_MODE_01_HIGH4, 0x09),
906 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_EN_TIMER, 0x04),
907 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
908 QMP_PHY_INIT_CFG(QSERDES_V6_RX_DCC_CTRL1, 0x0c),
909 QMP_PHY_INIT_CFG(QSERDES_V6_RX_VTH_CODE, 0x10),
910 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_CTRL1, 0x14),
911 QMP_PHY_INIT_CFG(QSERDES_V6_RX_SIGDET_CAL_TRIM, 0x08),
912
913 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0x3f, 1),
914 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 1),
915 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xff, 1),
916 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 1),
917 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xed, 1),
918
919 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_LOW, 0xbf, 2),
920 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH, 0xbf, 2),
921 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH2, 0xbf, 2),
922 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH3, 0xdf, 2),
923 QMP_PHY_INIT_CFG_LANE(QSERDES_V6_RX_RX_MODE_00_HIGH4, 0xfd, 2),
924 };
925
926 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_tbl[] = {
927 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG1, 0xc4),
928 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG2, 0x89),
929 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG3, 0x20),
930 QMP_PHY_INIT_CFG(QPHY_V6_PCS_LOCK_DETECT_CONFIG6, 0x13),
931 QMP_PHY_INIT_CFG(QPHY_V6_PCS_REFGEN_REQ_CONFIG1, 0x21),
932 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RX_SIGDET_LVL, 0x99),
933 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
934 QMP_PHY_INIT_CFG(QPHY_V6_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
935 QMP_PHY_INIT_CFG(QPHY_V6_PCS_CDR_RESET_TIME, 0x0a),
936 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG1, 0x88),
937 QMP_PHY_INIT_CFG(QPHY_V6_PCS_ALIGN_DETECT_CONFIG2, 0x13),
938 QMP_PHY_INIT_CFG(QPHY_V6_PCS_PCS_TX_RX_CONFIG, 0x0c),
939 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG1, 0x4b),
940 QMP_PHY_INIT_CFG(QPHY_V6_PCS_EQ_CONFIG5, 0x10),
941 };
942
943 static const struct qmp_phy_init_tbl sm8550_usb3_pcs_usb_tbl[] = {
944 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
945 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
946 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
947 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
948 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_POWER_STATE_CONFIG1, 0x68),
949 };
950
951 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl[] = {
952 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
953 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
954 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
955 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
956 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
957 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
958 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
959 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
960 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
961 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
962 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
963 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
964 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
965 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x00),
966 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
967 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
968 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
969 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
970 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
971 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
972 };
973
974 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_rbr[] = {
975 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x05),
976 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
977 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
978 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
979 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x6f),
980 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x08),
981 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
982 };
983
984 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr[] = {
985 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x03),
986 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
987 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
988 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
989 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x0f),
990 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x0e),
991 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
992 };
993
994 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr2[] = {
995 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
996 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x8c),
997 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x00),
998 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x0a),
999 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x1f),
1000 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x1c),
1001 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
1002 };
1003
1004 static const struct qmp_phy_init_tbl qmp_v4_dp_serdes_tbl_hbr3[] = {
1005 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x00),
1006 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x69),
1007 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0x80),
1008 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x07),
1009 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x2f),
1010 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x2a),
1011 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x08),
1012 };
1013
1014 static const struct qmp_phy_init_tbl qmp_v4_dp_tx_tbl[] = {
1015 QMP_PHY_INIT_CFG(QSERDES_V4_TX_VMODE_CTRL1, 0x40),
1016 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1017 QMP_PHY_INIT_CFG(QSERDES_V4_TX_INTERFACE_SELECT, 0x3b),
1018 QMP_PHY_INIT_CFG(QSERDES_V4_TX_CLKBUF_ENABLE, 0x0f),
1019 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RESET_TSYNC_EN, 0x03),
1020 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0f),
1021 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1022 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_INTERFACE_MODE, 0x00),
1023 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1024 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
1025 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_BAND, 0x4),
1026 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_POL_INV, 0x0a),
1027 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_DRV_LVL, 0x2a),
1028 QMP_PHY_INIT_CFG(QSERDES_V4_TX_TX_EMP_POST1_LVL, 0x20),
1029 };
1030
1031 static const struct qmp_phy_init_tbl qmp_v5_dp_serdes_tbl[] = {
1032 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SVS_MODE_CLK_SEL, 0x05),
1033 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x3b),
1034 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYS_CLK_CTRL, 0x02),
1035 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_ENABLE1, 0x0c),
1036 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x06),
1037 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CLK_SELECT, 0x30),
1038 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_IVCO, 0x0f),
1039 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
1040 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
1041 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
1042 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
1043 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
1044 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
1045 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_CONFIG, 0x02),
1046 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1047 QMP_PHY_INIT_CFG(QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1048 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
1049 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0x00),
1050 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BG_TIMER, 0x0a),
1051 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE0, 0x0a),
1052 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_CTRL, 0x00),
1053 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN, 0x17),
1054 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORE_CLK_EN, 0x1f),
1055 };
1056
1057 static const struct qmp_phy_init_tbl qmp_v5_dp_tx_tbl[] = {
1058 QMP_PHY_INIT_CFG(QSERDES_V5_TX_VMODE_CTRL1, 0x40),
1059 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1060 QMP_PHY_INIT_CFG(QSERDES_V5_TX_INTERFACE_SELECT, 0x3b),
1061 QMP_PHY_INIT_CFG(QSERDES_V5_TX_CLKBUF_ENABLE, 0x0f),
1062 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RESET_TSYNC_EN, 0x03),
1063 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0f),
1064 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1065 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_INTERFACE_MODE, 0x00),
1066 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1067 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
1068 QMP_PHY_INIT_CFG(QSERDES_V5_TX_TX_BAND, 0x04),
1069 };
1070
1071 static const struct qmp_phy_init_tbl qmp_v5_5nm_dp_tx_tbl[] = {
1072 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x51),
1073 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRANSCEIVER_BIAS_EN, 0x1a),
1074 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_VMODE_CTRL1, 0x40),
1075 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PRE_STALL_LDO_BOOST_EN, 0x0),
1076 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_INTERFACE_SELECT, 0xff),
1077 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_CLKBUF_ENABLE, 0x0f),
1078 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RESET_TSYNC_EN, 0x03),
1079 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TRAN_DRVR_EMP_EN, 0xf),
1080 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1081 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1082 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
1083 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_TX_BAND, 0x01),
1084 };
1085
1086 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl[] = {
1087 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15),
1088 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b),
1089 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02),
1090 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c),
1091 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06),
1092 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30),
1093 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1094 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1095 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1096 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1097 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00),
1098 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12),
1099 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1100 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1101 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00),
1102 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1103 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14),
1104 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00),
1105 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17),
1106 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),
1107 };
1108
1109 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl[] = {
1110 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x15),
1111 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x3b),
1112 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYS_CLK_CTRL, 0x02),
1113 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_ENABLE1, 0x0c),
1114 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x06),
1115 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CLK_SELECT, 0x30),
1116 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x07),
1117 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1118 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1119 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x06),
1120 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1121 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x00),
1122 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1123 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x12),
1124 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
1125 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1126 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x00),
1127 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1128 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x14),
1129 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_CTRL, 0x00),
1130 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_BIAS_EN_CLK_BUFLR_EN, 0x17),
1131 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0x0f),
1132 };
1133
1134 static const struct qmp_phy_init_tbl qmp_v6_dp_tx_tbl[] = {
1135 QMP_PHY_INIT_CFG(QSERDES_V6_TX_VMODE_CTRL1, 0x40),
1136 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PRE_STALL_LDO_BOOST_EN, 0x30),
1137 QMP_PHY_INIT_CFG(QSERDES_V6_TX_INTERFACE_SELECT, 0x3b),
1138 QMP_PHY_INIT_CFG(QSERDES_V6_TX_CLKBUF_ENABLE, 0x0f),
1139 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RESET_TSYNC_EN, 0x03),
1140 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TRAN_DRVR_EMP_EN, 0x0f),
1141 QMP_PHY_INIT_CFG(QSERDES_V6_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1142 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_INTERFACE_MODE, 0x00),
1143 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_TX, 0x0c),
1144 QMP_PHY_INIT_CFG(QSERDES_V6_TX_RES_CODE_LANE_OFFSET_RX, 0x0c),
1145 QMP_PHY_INIT_CFG(QSERDES_V6_TX_TX_BAND, 0x4),
1146 };
1147
1148 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_tx_tbl[] = {
1149 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_VMODE_CTRL1, 0x40),
1150 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PRE_STALL_LDO_BOOST_EN, 0x00),
1151 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_INTERFACE_SELECT, 0xff),
1152 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_CLKBUF_ENABLE, 0x0f),
1153 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RESET_TSYNC_EN, 0x03),
1154 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TRAN_DRVR_EMP_EN, 0x0f),
1155 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_PARRATE_REC_DETECT_IDLE_EN, 0x00),
1156 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
1157 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x11),
1158 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_TX_BAND, 0x1),
1159 };
1160
1161 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_rbr[] = {
1162 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),
1163 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1164 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1165 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1166 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37),
1167 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
1168 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
1169 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1170 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1171 };
1172
1173 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr[] = {
1174 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03),
1175 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1176 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1177 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1178 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07),
1179 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
1180 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1181 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1182 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1183 };
1184
1185 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr2[] = {
1186 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
1187 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46),
1188 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x00),
1189 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
1190 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f),
1191 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e),
1192 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1193 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97),
1194 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10),
1195 };
1196
1197 static const struct qmp_phy_init_tbl qmp_v6_dp_serdes_tbl_hbr3[] = {
1198 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00),
1199 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1200 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0xc0),
1201 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1202 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17),
1203 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15),
1204 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1205 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1206 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1207 };
1208
1209 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_rbr[] = {
1210 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x05),
1211 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1212 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
1213 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1214 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x37),
1215 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x04),
1216 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1217 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1218 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1219 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),
1220 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),
1221 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1222 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92),
1223 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1224 };
1225
1226 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr[] = {
1227 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x03),
1228 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1229 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1230 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1231 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x07),
1232 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x07),
1233 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1234 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1235 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1236 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),
1237 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),
1238 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1239 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92),
1240 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1241 };
1242
1243 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr2[] = {
1244 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x01),
1245 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x46),
1246 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1247 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x05),
1248 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x0f),
1249 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x0e),
1250 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x97),
1251 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x10),
1252 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1253 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),
1254 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),
1255 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1256 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x18),
1257 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x02),
1258 };
1259
1260 static const struct qmp_phy_init_tbl qmp_v6_n4_dp_serdes_tbl_hbr3[] = {
1261 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x00),
1262 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x34),
1263 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x08),
1264 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x0b),
1265 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x17),
1266 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x15),
1267 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x71),
1268 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0c),
1269 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1270 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_ADJ_PER1, 0x00),
1271 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x6b),
1272 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1273 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0x92),
1274 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1275 };
1276
1277 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_serdes_tbl[] = {
1278 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1279 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1280 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1281 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xfd),
1282 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x0d),
1283 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xfd),
1284 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x0d),
1285 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1286 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x02),
1287 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x02),
1288 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1289 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1290 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1291 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1292 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1293 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1294 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1295 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1296 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1297 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1298 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x04),
1299 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE0, 0x01),
1300 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x04),
1301 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MSB_MODE1, 0x01),
1302 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0x55),
1303 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xd5),
1304 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x05),
1305 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0x55),
1306 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xd5),
1307 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x05),
1308 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1309 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0xd4),
1310 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE0, 0x00),
1311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0xd4),
1312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x00),
1313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x13),
1314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
1315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE0, 0x0a),
1316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x04),
1317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORE_CLK_EN, 0x60),
1318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CMN_CONFIG, 0x76),
1319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_IVCO, 0xff),
1320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE0, 0x20),
1321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_INTEGLOOP_GAIN0_MODE1, 0x20),
1322 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_INITVAL2, 0x00),
1323 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAXVAL2, 0x01),
1324 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SVS_MODE_CLK_SEL, 0x0a),
1325 };
1326
1327 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_tx_tbl[] = {
1328 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_1, 0x05),
1329 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_2, 0xc2),
1330 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_LANE_MODE_3, 0x10),
1331 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1332 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_TX_RES_CODE_LANE_OFFSET_RX, 0x0a),
1333 };
1334
1335 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_rx_tbl[] = {
1336 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_CNTRL, 0x04),
1337 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1338 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_SIGDET_ENABLES, 0x00),
1339 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B0, 0xd2),
1340 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B1, 0xd2),
1341 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B2, 0xdb),
1342 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B3, 0x21),
1343 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B4, 0x3f),
1344 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B5, 0x80),
1345 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B6, 0x45),
1346 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE_0_1_B7, 0x00),
1347 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B0, 0x6b),
1348 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B1, 0x63),
1349 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B2, 0xb6),
1350 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B3, 0x23),
1351 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B4, 0x35),
1352 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B5, 0x30),
1353 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B6, 0x8e),
1354 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_MODE_RATE2_B7, 0x00),
1355 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CODE_OVERRIDE, 0x00),
1356 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_CAL_CTRL2, 0x80),
1357 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_SUMMER_CAL_SPD_MODE, 0x1b),
1358 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1359 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_PI_CONTROLS, 0x15),
1360 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SB2_GAIN2_RATE2, 0x0a),
1361 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1362 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_CNTRL1, 0x00),
1363 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_VGA_CAL_MAN_VAL, 0x0d),
1364 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_DAC_ENABLE1, 0x00),
1365 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_DFE_3, 0x45),
1366 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_GM_CAL, 0x09),
1367 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_FO_GAIN_RATE2, 0x09),
1368 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_UCDR_SO_GAIN_RATE2, 0x05),
1369 QMP_PHY_INIT_CFG(QSERDES_V5_5NM_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x3f),
1370 };
1371
1372 static const struct qmp_phy_init_tbl sc8280xp_usb43dp_pcs_tbl[] = {
1373 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1374 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1375 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1376 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1377 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1378 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1379 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1380 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1381 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_CONFIG, 0x0a),
1382 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1383 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1384 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1385 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1386 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1387 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1388 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1389 };
1390
1391 static const struct qmp_phy_init_tbl x1e80100_usb43dp_serdes_tbl[] = {
1392 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_EN_CENTER, 0x01),
1393 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER1, 0x62),
1394 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_PER2, 0x02),
1395 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE0, 0xc2),
1396 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE0, 0x03),
1397 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE1_MODE1, 0xc2),
1398 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SSC_STEP_SIZE2_MODE1, 0x03),
1399 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_BUF_ENABLE, 0x0a),
1400 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE0, 0x02),
1401 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CP_CTRL_MODE1, 0x02),
1402 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE0, 0x16),
1403 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_RCTRL_MODE1, 0x16),
1404 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE0, 0x36),
1405 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CCTRL_MODE1, 0x36),
1406 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SYSCLK_EN_SEL, 0x1a),
1407 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_EN, 0x04),
1408 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP_CFG, 0x04),
1409 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE0, 0x08),
1410 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE0, 0x1a),
1411 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP1_MODE1, 0x16),
1412 QMP_PHY_INIT_CFG(QSERDES_V6_COM_LOCK_CMP2_MODE1, 0x41),
1413 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE0, 0x82),
1414 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE0, 0x00),
1415 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MODE1, 0x82),
1416 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DEC_START_MSB_MODE1, 0x00),
1417 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE0, 0x55),
1418 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE0, 0x55),
1419 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE0, 0x03),
1420 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START1_MODE1, 0x55),
1421 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START2_MODE1, 0x55),
1422 QMP_PHY_INIT_CFG(QSERDES_V6_COM_DIV_FRAC_START3_MODE1, 0x03),
1423 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAP, 0x14),
1424 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE0, 0xba),
1425 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE0, 0x00),
1426 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE1_MODE1, 0xba),
1427 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE2_MODE1, 0x00),
1428 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_SEL_1, 0x13),
1429 QMP_PHY_INIT_CFG(QSERDES_V6_COM_HSCLK_HS_SWITCH_SEL_1, 0x00),
1430 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_CORE_CLK_DIV_MODE0, 0x0a),
1431 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORECLK_DIV_MODE1, 0x04),
1432 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CORE_CLK_EN, 0xa0),
1433 QMP_PHY_INIT_CFG(QSERDES_V6_COM_CMN_CONFIG_1, 0x76),
1434 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO, 0x0f),
1435 QMP_PHY_INIT_CFG(QSERDES_V6_COM_PLL_IVCO_MODE1, 0x0f),
1436 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE0, 0x20),
1437 QMP_PHY_INIT_CFG(QSERDES_V6_COM_INTEGLOOP_GAIN0_MODE1, 0x20),
1438 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_INITVAL2, 0x00),
1439 QMP_PHY_INIT_CFG(QSERDES_V6_COM_VCO_TUNE_MAXVAL2, 0x01),
1440 QMP_PHY_INIT_CFG(QSERDES_V6_COM_SVS_MODE_CLK_SEL, 0x0a),
1441 QMP_PHY_INIT_CFG(QSERDES_V6_COM_BG_TIMER, 0x0a),
1442 };
1443
1444 static const struct qmp_phy_init_tbl x1e80100_usb43dp_tx_tbl[] = {
1445 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_1, 0x05),
1446 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_2, 0x50),
1447 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_LANE_MODE_3, 0x50),
1448 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1449 QMP_PHY_INIT_CFG(QSERDES_V6_N4_TX_RES_CODE_LANE_OFFSET_RX, 0x0a),
1450 };
1451
1452 static const struct qmp_phy_init_tbl x1e80100_usb43dp_rx_tbl[] = {
1453 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_CNTRL, 0x04),
1454 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1455 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_SIGDET_ENABLES, 0x00),
1456 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B0, 0xc3),
1457 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B1, 0xc3),
1458 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B2, 0xd8),
1459 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B3, 0x9e),
1460 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B4, 0x36),
1461 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B5, 0xb6),
1462 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE_0_1_B6, 0x64),
1463 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B0, 0xd6),
1464 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B1, 0xee),
1465 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B2, 0x18),
1466 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B3, 0x9a),
1467 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B4, 0x04),
1468 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B5, 0x36),
1469 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_MODE_RATE2_B6, 0xe3),
1470 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_IVCM_CAL_CODE_OVERRIDE, 0x00),
1471 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_CAL_CTRL2, 0x80),
1472 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_SUMMER_CAL_SPD_MODE, 0x2f),
1473 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x08),
1474 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CONTROLS, 0x15),
1475 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL1, 0xd0),
1476 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_PI_CTRL2, 0x48),
1477 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SB2_GAIN2_RATE2, 0x0a),
1478 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_IVCM_POSTCAL_OFFSET, 0x7c),
1479 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_CNTRL1, 0x00),
1480 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_VGA_CAL_MAN_VAL, 0x04),
1481 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_DAC_ENABLE1, 0x88),
1482 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_DFE_3, 0x45),
1483 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_GM_CAL, 0x0d),
1484 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_FO_GAIN_RATE2, 0x09),
1485 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_UCDR_SO_GAIN_RATE2, 0x05),
1486 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_Q_PI_INTRINSIC_BIAS_RATE32, 0x2f),
1487 QMP_PHY_INIT_CFG(QSERDES_V6_N4_RX_RX_BKUP_CTRL1, 0x14),
1488 };
1489
1490 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_tbl[] = {
1491 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1492 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1493 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1494 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG2, 0x89),
1495 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1496 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1497 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1498 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_SIGDET_LVL, 0x55),
1499 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_RX_CONFIG, 0x0a),
1500 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG1, 0xd4),
1501 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_ALIGN_DETECT_CONFIG2, 0x30),
1502 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1503 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG1, 0x4b),
1504 QMP_PHY_INIT_CFG(QPHY_V6_N4_PCS_EQ_CONFIG5, 0x10),
1505 };
1506
1507 static const struct qmp_phy_init_tbl sm8750_usb3_serdes_tbl[] = {
1508 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE1, 0xc0),
1509 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE1, 0x01),
1510 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE1, 0x02),
1511 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE1, 0x16),
1512 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE1, 0x36),
1513 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORECLK_DIV_MODE1, 0x04),
1514 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE1, 0x16),
1515 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE1, 0x41),
1516 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE1, 0x41),
1517 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE1, 0x00),
1518 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE1, 0x55),
1519 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE1, 0x75),
1520 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE1, 0x01),
1521 QMP_PHY_INIT_CFG(QSERDES_V8_COM_HSCLK_SEL_1, 0x01),
1522 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE1, 0x25),
1523 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE1, 0x02),
1524 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0x5c),
1525 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x0f),
1526 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0x5c),
1527 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x0f),
1528 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE1_MODE0, 0xc0),
1529 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_STEP_SIZE2_MODE0, 0x01),
1530 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CP_CTRL_MODE0, 0x02),
1531 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_RCTRL_MODE0, 0x16),
1532 QMP_PHY_INIT_CFG(QSERDES_V8_COM_PLL_CCTRL_MODE0, 0x36),
1533 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP1_MODE0, 0x08),
1534 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP2_MODE0, 0x1a),
1535 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MODE0, 0x41),
1536 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DEC_START_MSB_MODE0, 0x00),
1537 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START1_MODE0, 0x55),
1538 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START2_MODE0, 0x75),
1539 QMP_PHY_INIT_CFG(QSERDES_V8_COM_DIV_FRAC_START3_MODE0, 0x01),
1540 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE1_MODE0, 0x25),
1541 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE2_MODE0, 0x02),
1542 QMP_PHY_INIT_CFG(QSERDES_V8_COM_BG_TIMER, 0x0a),
1543 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_EN_CENTER, 0x01),
1544 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER1, 0x62),
1545 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SSC_PER2, 0x02),
1546 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_BUF_ENABLE, 0x0c),
1547 QMP_PHY_INIT_CFG(QSERDES_V8_COM_SYSCLK_EN_SEL, 0x1a),
1548 QMP_PHY_INIT_CFG(QSERDES_V8_COM_LOCK_CMP_CFG, 0x14),
1549 QMP_PHY_INIT_CFG(QSERDES_V8_COM_VCO_TUNE_MAP, 0x04),
1550 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CORE_CLK_EN, 0x20),
1551 QMP_PHY_INIT_CFG(QSERDES_V8_COM_CMN_CONFIG_1, 0x16),
1552 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_1, 0xb6),
1553 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_2, 0x4a),
1554 QMP_PHY_INIT_CFG(QSERDES_V8_COM_AUTO_GAIN_ADJ_CTRL_3, 0x36),
1555 QMP_PHY_INIT_CFG(QSERDES_V8_COM_ADDITIONAL_MISC, 0x0c),
1556 };
1557
1558 static const struct qmp_phy_init_tbl sm8750_usb3_tx_tbl[] = {
1559 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_TX, 0x00),
1560 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_RX, 0x00),
1561 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1562 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
1563 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_1, 0xf5),
1564 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_3, 0x11),
1565 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_4, 0x31),
1566 QMP_PHY_INIT_CFG(QSERDES_V8_TX_LANE_MODE_5, 0x5f),
1567 QMP_PHY_INIT_CFG(QSERDES_V8_TX_RCV_DETECT_LVL_2, 0x12),
1568 QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x21, 1),
1569 QMP_PHY_INIT_CFG_LANE(QSERDES_V8_TX_PI_QEC_CTRL, 0x05, 2),
1570 };
1571
1572 static const struct qmp_phy_init_tbl sm8750_usb3_rx_tbl[] = {
1573 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FO_GAIN, 0x0a),
1574 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_GAIN, 0x06),
1575 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1576 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1577 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1578 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1579 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_PI_CONTROLS, 0x99),
1580 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH1, 0x08),
1581 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_THRESH2, 0x08),
1582 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN1, 0x00),
1583 QMP_PHY_INIT_CFG(QSERDES_V8_RX_UCDR_SB2_GAIN2, 0x0a),
1584 QMP_PHY_INIT_CFG(QSERDES_V8_RX_AUX_DATA_TCOARSE_TFINE, 0x20),
1585 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL1, 0x54),
1586 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VGA_CAL_CNTRL2, 0x0f),
1587 QMP_PHY_INIT_CFG(QSERDES_V8_RX_GM_CAL, 0x13),
1588 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
1589 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1590 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1591 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_LOW, 0x07),
1592 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1593 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x27),
1594
1595 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_ENABLES, 0x0c),
1596 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CNTRL, 0x04),
1597 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1598 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_LOW, 0x3f),
1599 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH, 0xbf),
1600 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH2, 0xff),
1601 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH3, 0xdf),
1602 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_00_HIGH4, 0xed),
1603 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_LOW, 0x19),
1604 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH, 0x09),
1605 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH2, 0x91),
1606 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH3, 0xb7),
1607 QMP_PHY_INIT_CFG(QSERDES_V8_RX_RX_MODE_01_HIGH4, 0xaa),
1608 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_EN_TIMER, 0x04),
1609 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1610 QMP_PHY_INIT_CFG(QSERDES_V8_RX_DCC_CTRL1, 0x0c),
1611 QMP_PHY_INIT_CFG(QSERDES_V8_RX_VTH_CODE, 0x10),
1612 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_CTRL1, 0x14),
1613 QMP_PHY_INIT_CFG(QSERDES_V8_RX_SIGDET_CAL_TRIM, 0x08),
1614 };
1615
1616 static const struct qmp_phy_init_tbl sm8750_usb3_pcs_tbl[] = {
1617 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1618 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG2, 0x89),
1619 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG3, 0x20),
1620 QMP_PHY_INIT_CFG(QPHY_V8_PCS_LOCK_DETECT_CONFIG6, 0x13),
1621 QMP_PHY_INIT_CFG(QPHY_V8_PCS_REFGEN_REQ_CONFIG1, 0x21),
1622 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RX_SIGDET_LVL, 0x55),
1623 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1624 QMP_PHY_INIT_CFG(QPHY_V8_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1625 QMP_PHY_INIT_CFG(QPHY_V8_PCS_CDR_RESET_TIME, 0x0a),
1626 QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1627 QMP_PHY_INIT_CFG(QPHY_V8_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1628 QMP_PHY_INIT_CFG(QPHY_V8_PCS_PCS_TX_RX_CONFIG, 0x0c),
1629 QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG1, 0x4b),
1630 QMP_PHY_INIT_CFG(QPHY_V8_PCS_EQ_CONFIG5, 0x10),
1631 };
1632
1633 static const struct qmp_phy_init_tbl sm8750_usb3_pcs_usb_tbl[] = {
1634 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1635 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RXEQTRAINING_DFE_TIME_S2, 0x07),
1636 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_L, 0x40),
1637 QMP_PHY_INIT_CFG(QPHY_V8_PCS_USB_RCVR_DTCT_DLY_U3_H, 0x00),
1638 };
1639
1640 static const struct qmp_phy_init_tbl x1e80100_usb43dp_pcs_usb_tbl[] = {
1641 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1642 QMP_PHY_INIT_CFG(QPHY_V6_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1643 };
1644
1645 /* list of regulators */
1646 struct qmp_regulator_data {
1647 const char *name;
1648 unsigned int enable_load;
1649 };
1650
1651 static struct qmp_regulator_data qmp_phy_vreg_l[] = {
1652 { .name = "vdda-phy", .enable_load = 21800 },
1653 { .name = "vdda-pll", .enable_load = 36000 },
1654 };
1655
1656 static const u8 qmp_dp_v3_pre_emphasis_hbr3_hbr2[4][4] = {
1657 { 0x00, 0x0c, 0x15, 0x1a },
1658 { 0x02, 0x0e, 0x16, 0xff },
1659 { 0x02, 0x11, 0xff, 0xff },
1660 { 0x04, 0xff, 0xff, 0xff }
1661 };
1662
1663 static const u8 qmp_dp_v3_voltage_swing_hbr3_hbr2[4][4] = {
1664 { 0x02, 0x12, 0x16, 0x1a },
1665 { 0x09, 0x19, 0x1f, 0xff },
1666 { 0x10, 0x1f, 0xff, 0xff },
1667 { 0x1f, 0xff, 0xff, 0xff }
1668 };
1669
1670 static const u8 qmp_dp_v3_pre_emphasis_hbr_rbr[4][4] = {
1671 { 0x00, 0x0c, 0x14, 0x19 },
1672 { 0x00, 0x0b, 0x12, 0xff },
1673 { 0x00, 0x0b, 0xff, 0xff },
1674 { 0x04, 0xff, 0xff, 0xff }
1675 };
1676
1677 static const u8 qmp_dp_v3_voltage_swing_hbr_rbr[4][4] = {
1678 { 0x08, 0x0f, 0x16, 0x1f },
1679 { 0x11, 0x1e, 0x1f, 0xff },
1680 { 0x19, 0x1f, 0xff, 0xff },
1681 { 0x1f, 0xff, 0xff, 0xff }
1682 };
1683
1684 static const u8 qmp_dp_v4_pre_emphasis_hbr3_hbr2[4][4] = {
1685 { 0x00, 0x0c, 0x15, 0x1b },
1686 { 0x02, 0x0e, 0x16, 0xff },
1687 { 0x02, 0x11, 0xff, 0xff },
1688 { 0x04, 0xff, 0xff, 0xff }
1689 };
1690
1691 static const u8 qmp_dp_v4_pre_emphasis_hbr_rbr[4][4] = {
1692 { 0x00, 0x0d, 0x14, 0x1a },
1693 { 0x00, 0x0e, 0x15, 0xff },
1694 { 0x00, 0x0d, 0xff, 0xff },
1695 { 0x03, 0xff, 0xff, 0xff }
1696 };
1697
1698 static const u8 qmp_dp_v4_voltage_swing_hbr_rbr[4][4] = {
1699 { 0x08, 0x0f, 0x16, 0x1f },
1700 { 0x11, 0x1e, 0x1f, 0xff },
1701 { 0x16, 0x1f, 0xff, 0xff },
1702 { 0x1f, 0xff, 0xff, 0xff }
1703 };
1704
1705 static const u8 qmp_dp_v5_pre_emphasis_hbr3_hbr2[4][4] = {
1706 { 0x20, 0x2c, 0x35, 0x3b },
1707 { 0x22, 0x2e, 0x36, 0xff },
1708 { 0x22, 0x31, 0xff, 0xff },
1709 { 0x24, 0xff, 0xff, 0xff }
1710 };
1711
1712 static const u8 qmp_dp_v5_voltage_swing_hbr3_hbr2[4][4] = {
1713 { 0x22, 0x32, 0x36, 0x3a },
1714 { 0x29, 0x39, 0x3f, 0xff },
1715 { 0x30, 0x3f, 0xff, 0xff },
1716 { 0x3f, 0xff, 0xff, 0xff }
1717 };
1718
1719 static const u8 qmp_dp_v5_pre_emphasis_hbr_rbr[4][4] = {
1720 { 0x20, 0x2d, 0x34, 0x3a },
1721 { 0x20, 0x2e, 0x35, 0xff },
1722 { 0x20, 0x2e, 0xff, 0xff },
1723 { 0x24, 0xff, 0xff, 0xff }
1724 };
1725
1726 static const u8 qmp_dp_v5_voltage_swing_hbr_rbr[4][4] = {
1727 { 0x28, 0x2f, 0x36, 0x3f },
1728 { 0x31, 0x3e, 0x3f, 0xff },
1729 { 0x36, 0x3f, 0xff, 0xff },
1730 { 0x3f, 0xff, 0xff, 0xff }
1731 };
1732
1733 static const u8 qmp_dp_v6_voltage_swing_hbr_rbr[4][4] = {
1734 { 0x27, 0x2f, 0x36, 0x3f },
1735 { 0x31, 0x3e, 0x3f, 0xff },
1736 { 0x36, 0x3f, 0xff, 0xff },
1737 { 0x3f, 0xff, 0xff, 0xff }
1738 };
1739
1740 static const u8 qmp_dp_v6_pre_emphasis_hbr_rbr[4][4] = {
1741 { 0x20, 0x2d, 0x34, 0x3a },
1742 { 0x20, 0x2e, 0x35, 0xff },
1743 { 0x20, 0x2e, 0xff, 0xff },
1744 { 0x22, 0xff, 0xff, 0xff }
1745 };
1746
1747 struct qmp_combo;
1748
1749 struct qmp_combo_offsets {
1750 u16 com;
1751 u16 txa;
1752 u16 rxa;
1753 u16 txb;
1754 u16 rxb;
1755 u16 usb3_serdes;
1756 u16 usb3_pcs_misc;
1757 u16 usb3_pcs;
1758 u16 usb3_pcs_usb;
1759 u16 dp_serdes;
1760 u16 dp_txa;
1761 u16 dp_txb;
1762 u16 dp_dp_phy;
1763 };
1764
1765 struct qmp_phy_cfg {
1766 const struct qmp_combo_offsets *offsets;
1767
1768 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1769 const struct qmp_phy_init_tbl *serdes_tbl;
1770 int serdes_tbl_num;
1771 const struct qmp_phy_init_tbl *tx_tbl;
1772 int tx_tbl_num;
1773 const struct qmp_phy_init_tbl *rx_tbl;
1774 int rx_tbl_num;
1775 const struct qmp_phy_init_tbl *pcs_tbl;
1776 int pcs_tbl_num;
1777 const struct qmp_phy_init_tbl *pcs_usb_tbl;
1778 int pcs_usb_tbl_num;
1779
1780 const struct qmp_phy_init_tbl *dp_serdes_tbl;
1781 int dp_serdes_tbl_num;
1782 const struct qmp_phy_init_tbl *dp_tx_tbl;
1783 int dp_tx_tbl_num;
1784
1785 /* Init sequence for DP PHY block link rates */
1786 const struct qmp_phy_init_tbl *serdes_tbl_rbr;
1787 int serdes_tbl_rbr_num;
1788 const struct qmp_phy_init_tbl *serdes_tbl_hbr;
1789 int serdes_tbl_hbr_num;
1790 const struct qmp_phy_init_tbl *serdes_tbl_hbr2;
1791 int serdes_tbl_hbr2_num;
1792 const struct qmp_phy_init_tbl *serdes_tbl_hbr3;
1793 int serdes_tbl_hbr3_num;
1794
1795 /* DP PHY swing and pre_emphasis tables */
1796 const u8 (*swing_hbr_rbr)[4][4];
1797 const u8 (*swing_hbr3_hbr2)[4][4];
1798 const u8 (*pre_emphasis_hbr_rbr)[4][4];
1799 const u8 (*pre_emphasis_hbr3_hbr2)[4][4];
1800
1801 /* DP PHY callbacks */
1802 int (*configure_dp_phy)(struct qmp_combo *qmp);
1803 void (*configure_dp_tx)(struct qmp_combo *qmp);
1804 int (*calibrate_dp_phy)(struct qmp_combo *qmp);
1805 void (*dp_aux_init)(struct qmp_combo *qmp);
1806
1807 /* resets to be requested */
1808 const char * const *reset_list;
1809 int num_resets;
1810 /* regulators to be requested */
1811 const struct qmp_regulator_data *vreg_list;
1812 int num_vregs;
1813
1814 /* array of registers with different offsets */
1815 const unsigned int *regs;
1816
1817 /* true, if PHY needs delay after POWER_DOWN */
1818 bool has_pwrdn_delay;
1819
1820 /* Offset from PCS to PCS_USB region */
1821 unsigned int pcs_usb_offset;
1822
1823 };
1824
1825 struct qmp_combo {
1826 struct device *dev;
1827
1828 const struct qmp_phy_cfg *cfg;
1829
1830 void __iomem *com;
1831
1832 void __iomem *serdes;
1833 void __iomem *tx;
1834 void __iomem *rx;
1835 void __iomem *pcs;
1836 void __iomem *tx2;
1837 void __iomem *rx2;
1838 void __iomem *pcs_misc;
1839 void __iomem *pcs_usb;
1840
1841 void __iomem *dp_serdes;
1842 void __iomem *dp_tx;
1843 void __iomem *dp_tx2;
1844 void __iomem *dp_dp_phy;
1845
1846 struct clk *pipe_clk;
1847 struct clk_bulk_data *clks;
1848 int num_clks;
1849 struct reset_control_bulk_data *resets;
1850 struct regulator_bulk_data *vregs;
1851
1852 struct mutex phy_mutex;
1853 int init_count;
1854 enum qmpphy_mode qmpphy_mode;
1855
1856 struct phy *usb_phy;
1857 enum phy_mode phy_mode;
1858 unsigned int usb_init_count;
1859
1860 struct phy *dp_phy;
1861 unsigned int dp_aux_cfg;
1862 struct phy_configure_opts_dp dp_opts;
1863 unsigned int dp_init_count;
1864 bool dp_powered_on;
1865
1866 struct clk_fixed_rate pipe_clk_fixed;
1867 struct clk_hw dp_link_hw;
1868 struct clk_hw dp_pixel_hw;
1869
1870 struct typec_switch_dev *sw;
1871 enum typec_orientation orientation;
1872
1873 struct typec_mux_dev *mux;
1874 };
1875
1876 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp);
1877 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp);
1878 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp);
1879 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp);
1880
1881 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp);
1882 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp);
1883 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp);
1884 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp);
1885
qphy_setbits(void __iomem * base,u32 offset,u32 val)1886 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1887 {
1888 u32 reg;
1889
1890 reg = readl(base + offset);
1891 reg |= val;
1892 writel(reg, base + offset);
1893
1894 /* ensure that above write is through */
1895 readl(base + offset);
1896 }
1897
qphy_clrbits(void __iomem * base,u32 offset,u32 val)1898 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1899 {
1900 u32 reg;
1901
1902 reg = readl(base + offset);
1903 reg &= ~val;
1904 writel(reg, base + offset);
1905
1906 /* ensure that above write is through */
1907 readl(base + offset);
1908 }
1909
1910 /* list of clocks required by phy */
1911 static const char * const qmp_combo_phy_clk_l[] = {
1912 "aux", "cfg_ahb", "ref", "com_aux",
1913 };
1914
1915 /* list of resets */
1916 static const char * const msm8996_usb3phy_reset_l[] = {
1917 "phy", "common",
1918 };
1919
1920 static const char * const sc7180_usb3phy_reset_l[] = {
1921 "phy",
1922 };
1923
1924 static const struct qmp_combo_offsets qmp_combo_offsets_v3 = {
1925 .com = 0x0000,
1926 .txa = 0x1200,
1927 .rxa = 0x1400,
1928 .txb = 0x1600,
1929 .rxb = 0x1800,
1930 .usb3_serdes = 0x1000,
1931 .usb3_pcs_misc = 0x1a00,
1932 .usb3_pcs = 0x1c00,
1933 .usb3_pcs_usb = 0x1f00,
1934 .dp_serdes = 0x2000,
1935 .dp_txa = 0x2200,
1936 .dp_txb = 0x2600,
1937 .dp_dp_phy = 0x2a00,
1938 };
1939
1940 static const struct qmp_combo_offsets qmp_combo_offsets_v5 = {
1941 .com = 0x0000,
1942 .txa = 0x0400,
1943 .rxa = 0x0600,
1944 .txb = 0x0a00,
1945 .rxb = 0x0c00,
1946 .usb3_serdes = 0x1000,
1947 .usb3_pcs_misc = 0x1200,
1948 .usb3_pcs = 0x1400,
1949 .usb3_pcs_usb = 0x1700,
1950 .dp_serdes = 0x2000,
1951 .dp_dp_phy = 0x2200,
1952 };
1953
1954 static const struct qmp_combo_offsets qmp_combo_offsets_v8 = {
1955 .com = 0x0000,
1956 .txa = 0x1400,
1957 .rxa = 0x1600,
1958 .txb = 0x1800,
1959 .rxb = 0x1a00,
1960 .usb3_serdes = 0x1000,
1961 .usb3_pcs_misc = 0x1c00,
1962 .usb3_pcs = 0x1e00,
1963 .usb3_pcs_usb = 0x2100,
1964 .dp_serdes = 0x3000,
1965 .dp_txa = 0x3400,
1966 .dp_txb = 0x3800,
1967 .dp_dp_phy = 0x3c00,
1968 };
1969
1970 static const struct qmp_phy_cfg sar2130p_usb3dpphy_cfg = {
1971 .offsets = &qmp_combo_offsets_v3,
1972
1973 .serdes_tbl = sar2130p_usb3_serdes_tbl,
1974 .serdes_tbl_num = ARRAY_SIZE(sar2130p_usb3_serdes_tbl),
1975 .tx_tbl = sm8550_usb3_tx_tbl,
1976 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl),
1977 .rx_tbl = sm8550_usb3_rx_tbl,
1978 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl),
1979 .pcs_tbl = sm8550_usb3_pcs_tbl,
1980 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl),
1981 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl,
1982 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl),
1983
1984 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
1985 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
1986 .dp_tx_tbl = qmp_v6_dp_tx_tbl,
1987 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
1988
1989 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
1990 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
1991 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
1992 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
1993 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
1994 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
1995 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
1996 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
1997
1998 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr,
1999 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
2000 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
2001 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
2002
2003 .dp_aux_init = qmp_v4_dp_aux_init,
2004 .configure_dp_tx = qmp_v4_configure_dp_tx,
2005 .configure_dp_phy = qmp_v4_configure_dp_phy,
2006 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
2007
2008 .regs = qmp_v6_usb3phy_regs_layout,
2009 .reset_list = msm8996_usb3phy_reset_l,
2010 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2011 .vreg_list = qmp_phy_vreg_l,
2012 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2013 };
2014
2015 static const struct qmp_phy_cfg sc7180_usb3dpphy_cfg = {
2016 .offsets = &qmp_combo_offsets_v3,
2017
2018 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
2019 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
2020 .tx_tbl = qmp_v3_usb3_tx_tbl,
2021 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
2022 .rx_tbl = qmp_v3_usb3_rx_tbl,
2023 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
2024 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
2025 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
2026
2027 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl,
2028 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
2029 .dp_tx_tbl = qmp_v3_dp_tx_tbl,
2030 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
2031
2032 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
2033 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
2034 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
2035 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
2036 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
2037 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
2038 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
2039 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
2040
2041 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
2042 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
2043 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
2044 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
2045
2046 .dp_aux_init = qmp_v3_dp_aux_init,
2047 .configure_dp_tx = qmp_v3_configure_dp_tx,
2048 .configure_dp_phy = qmp_v3_configure_dp_phy,
2049 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy,
2050
2051 .reset_list = sc7180_usb3phy_reset_l,
2052 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
2053 .vreg_list = qmp_phy_vreg_l,
2054 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2055 .regs = qmp_v3_usb3phy_regs_layout,
2056
2057 .has_pwrdn_delay = true,
2058 };
2059
2060 static const struct qmp_phy_cfg sdm845_usb3dpphy_cfg = {
2061 .offsets = &qmp_combo_offsets_v3,
2062
2063 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
2064 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
2065 .tx_tbl = qmp_v3_usb3_tx_tbl,
2066 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
2067 .rx_tbl = qmp_v3_usb3_rx_tbl,
2068 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
2069 .pcs_tbl = qmp_v3_usb3_pcs_tbl,
2070 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
2071
2072 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl,
2073 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
2074 .dp_tx_tbl = qmp_v3_dp_tx_tbl,
2075 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
2076
2077 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
2078 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
2079 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
2080 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
2081 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
2082 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
2083 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
2084 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
2085
2086 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
2087 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
2088 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
2089 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
2090
2091 .dp_aux_init = qmp_v3_dp_aux_init,
2092 .configure_dp_tx = qmp_v3_configure_dp_tx,
2093 .configure_dp_phy = qmp_v3_configure_dp_phy,
2094 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy,
2095
2096 .reset_list = msm8996_usb3phy_reset_l,
2097 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2098 .vreg_list = qmp_phy_vreg_l,
2099 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2100 .regs = qmp_v3_usb3phy_regs_layout,
2101
2102 .has_pwrdn_delay = true,
2103 };
2104
2105 static const struct qmp_phy_cfg sc8180x_usb3dpphy_cfg = {
2106 .offsets = &qmp_combo_offsets_v3,
2107
2108 .serdes_tbl = sm8150_usb3_serdes_tbl,
2109 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
2110 .tx_tbl = sm8150_usb3_tx_tbl,
2111 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl),
2112 .rx_tbl = sm8150_usb3_rx_tbl,
2113 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl),
2114 .pcs_tbl = sm8150_usb3_pcs_tbl,
2115 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
2116 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl,
2117 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
2118
2119 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl,
2120 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
2121 .dp_tx_tbl = qmp_v4_dp_tx_tbl,
2122 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
2123
2124 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
2125 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
2126 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
2127 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
2128 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
2129 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
2130 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
2131 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
2132
2133 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
2134 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
2135 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
2136 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
2137
2138 .dp_aux_init = qmp_v4_dp_aux_init,
2139 .configure_dp_tx = qmp_v4_configure_dp_tx,
2140 .configure_dp_phy = qmp_v4_configure_dp_phy,
2141 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
2142
2143 .reset_list = msm8996_usb3phy_reset_l,
2144 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2145 .vreg_list = qmp_phy_vreg_l,
2146 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2147 .regs = qmp_v45_usb3phy_regs_layout,
2148 .pcs_usb_offset = 0x300,
2149
2150 .has_pwrdn_delay = true,
2151 };
2152
2153 static const struct qmp_phy_cfg sc8280xp_usb43dpphy_cfg = {
2154 .offsets = &qmp_combo_offsets_v5,
2155
2156 .serdes_tbl = sc8280xp_usb43dp_serdes_tbl,
2157 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_serdes_tbl),
2158 .tx_tbl = sc8280xp_usb43dp_tx_tbl,
2159 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_tx_tbl),
2160 .rx_tbl = sc8280xp_usb43dp_rx_tbl,
2161 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_rx_tbl),
2162 .pcs_tbl = sc8280xp_usb43dp_pcs_tbl,
2163 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb43dp_pcs_tbl),
2164
2165 .dp_serdes_tbl = qmp_v5_dp_serdes_tbl,
2166 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v5_dp_serdes_tbl),
2167 .dp_tx_tbl = qmp_v5_5nm_dp_tx_tbl,
2168 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_5nm_dp_tx_tbl),
2169
2170 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
2171 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
2172 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
2173 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
2174 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
2175 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
2176 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
2177 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
2178
2179 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr,
2180 .pre_emphasis_hbr_rbr = &qmp_dp_v5_pre_emphasis_hbr_rbr,
2181 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
2182 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
2183
2184 .dp_aux_init = qmp_v4_dp_aux_init,
2185 .configure_dp_tx = qmp_v4_configure_dp_tx,
2186 .configure_dp_phy = qmp_v4_configure_dp_phy,
2187 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
2188
2189 .reset_list = msm8996_usb3phy_reset_l,
2190 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2191 .vreg_list = qmp_phy_vreg_l,
2192 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2193 .regs = qmp_v5_5nm_usb3phy_regs_layout,
2194 };
2195
2196 static const struct qmp_phy_cfg x1e80100_usb3dpphy_cfg = {
2197 .offsets = &qmp_combo_offsets_v5,
2198
2199 .serdes_tbl = x1e80100_usb43dp_serdes_tbl,
2200 .serdes_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_serdes_tbl),
2201 .tx_tbl = x1e80100_usb43dp_tx_tbl,
2202 .tx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_tx_tbl),
2203 .rx_tbl = x1e80100_usb43dp_rx_tbl,
2204 .rx_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_rx_tbl),
2205 .pcs_tbl = x1e80100_usb43dp_pcs_tbl,
2206 .pcs_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_tbl),
2207 .pcs_usb_tbl = x1e80100_usb43dp_pcs_usb_tbl,
2208 .pcs_usb_tbl_num = ARRAY_SIZE(x1e80100_usb43dp_pcs_usb_tbl),
2209
2210 .dp_serdes_tbl = qmp_v6_n4_dp_serdes_tbl,
2211 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl),
2212 .dp_tx_tbl = qmp_v6_n4_dp_tx_tbl,
2213 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_n4_dp_tx_tbl),
2214
2215 .serdes_tbl_rbr = qmp_v6_n4_dp_serdes_tbl_rbr,
2216 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_rbr),
2217 .serdes_tbl_hbr = qmp_v6_n4_dp_serdes_tbl_hbr,
2218 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr),
2219 .serdes_tbl_hbr2 = qmp_v6_n4_dp_serdes_tbl_hbr2,
2220 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr2),
2221 .serdes_tbl_hbr3 = qmp_v6_n4_dp_serdes_tbl_hbr3,
2222 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_n4_dp_serdes_tbl_hbr3),
2223
2224 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr,
2225 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
2226 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
2227 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
2228
2229 .dp_aux_init = qmp_v4_dp_aux_init,
2230 .configure_dp_tx = qmp_v4_configure_dp_tx,
2231 .configure_dp_phy = qmp_v4_configure_dp_phy,
2232 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
2233
2234 .reset_list = msm8996_usb3phy_reset_l,
2235 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2236 .vreg_list = qmp_phy_vreg_l,
2237 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2238 .regs = qmp_v6_n4_usb3phy_regs_layout,
2239 };
2240
2241 static const struct qmp_phy_cfg sm6350_usb3dpphy_cfg = {
2242 .offsets = &qmp_combo_offsets_v3,
2243
2244 .serdes_tbl = qmp_v3_usb3_serdes_tbl,
2245 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
2246 .tx_tbl = qmp_v3_usb3_tx_tbl,
2247 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
2248 .rx_tbl = sm6350_usb3_rx_tbl,
2249 .rx_tbl_num = ARRAY_SIZE(sm6350_usb3_rx_tbl),
2250 .pcs_tbl = sm6350_usb3_pcs_tbl,
2251 .pcs_tbl_num = ARRAY_SIZE(sm6350_usb3_pcs_tbl),
2252
2253 .dp_serdes_tbl = qmp_v3_dp_serdes_tbl,
2254 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl),
2255 .dp_tx_tbl = qmp_v3_dp_tx_tbl,
2256 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v3_dp_tx_tbl),
2257
2258 .serdes_tbl_rbr = qmp_v3_dp_serdes_tbl_rbr,
2259 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_rbr),
2260 .serdes_tbl_hbr = qmp_v3_dp_serdes_tbl_hbr,
2261 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr),
2262 .serdes_tbl_hbr2 = qmp_v3_dp_serdes_tbl_hbr2,
2263 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr2),
2264 .serdes_tbl_hbr3 = qmp_v3_dp_serdes_tbl_hbr3,
2265 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v3_dp_serdes_tbl_hbr3),
2266
2267 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
2268 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
2269 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
2270 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
2271
2272 .dp_aux_init = qmp_v3_dp_aux_init,
2273 .configure_dp_tx = qmp_v3_configure_dp_tx,
2274 .configure_dp_phy = qmp_v3_configure_dp_phy,
2275 .calibrate_dp_phy = qmp_v3_calibrate_dp_phy,
2276
2277 .reset_list = msm8996_usb3phy_reset_l,
2278 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2279 .vreg_list = qmp_phy_vreg_l,
2280 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2281 .regs = qmp_v3_usb3phy_regs_layout,
2282 };
2283
2284 static const struct qmp_phy_cfg sm8250_usb3dpphy_cfg = {
2285 .offsets = &qmp_combo_offsets_v3,
2286
2287 .serdes_tbl = sm8150_usb3_serdes_tbl,
2288 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
2289 .tx_tbl = sm8250_usb3_tx_tbl,
2290 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl),
2291 .rx_tbl = sm8250_usb3_rx_tbl,
2292 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl),
2293 .pcs_tbl = sm8250_usb3_pcs_tbl,
2294 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
2295 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl,
2296 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
2297
2298 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl,
2299 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
2300 .dp_tx_tbl = qmp_v4_dp_tx_tbl,
2301 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v4_dp_tx_tbl),
2302
2303 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
2304 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
2305 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
2306 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
2307 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
2308 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
2309 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
2310 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
2311
2312 .swing_hbr_rbr = &qmp_dp_v3_voltage_swing_hbr_rbr,
2313 .pre_emphasis_hbr_rbr = &qmp_dp_v3_pre_emphasis_hbr_rbr,
2314 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
2315 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v3_pre_emphasis_hbr3_hbr2,
2316
2317 .dp_aux_init = qmp_v4_dp_aux_init,
2318 .configure_dp_tx = qmp_v4_configure_dp_tx,
2319 .configure_dp_phy = qmp_v4_configure_dp_phy,
2320 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
2321
2322 .reset_list = msm8996_usb3phy_reset_l,
2323 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2324 .vreg_list = qmp_phy_vreg_l,
2325 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2326 .regs = qmp_v45_usb3phy_regs_layout,
2327 .pcs_usb_offset = 0x300,
2328
2329 .has_pwrdn_delay = true,
2330 };
2331
2332 static const struct qmp_phy_cfg sm8350_usb3dpphy_cfg = {
2333 .offsets = &qmp_combo_offsets_v3,
2334
2335 .serdes_tbl = sm8150_usb3_serdes_tbl,
2336 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
2337 .tx_tbl = sm8350_usb3_tx_tbl,
2338 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl),
2339 .rx_tbl = sm8350_usb3_rx_tbl,
2340 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl),
2341 .pcs_tbl = sm8350_usb3_pcs_tbl,
2342 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
2343 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl,
2344 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
2345
2346 .dp_serdes_tbl = qmp_v4_dp_serdes_tbl,
2347 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl),
2348 .dp_tx_tbl = qmp_v5_dp_tx_tbl,
2349 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v5_dp_tx_tbl),
2350
2351 .serdes_tbl_rbr = qmp_v4_dp_serdes_tbl_rbr,
2352 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_rbr),
2353 .serdes_tbl_hbr = qmp_v4_dp_serdes_tbl_hbr,
2354 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr),
2355 .serdes_tbl_hbr2 = qmp_v4_dp_serdes_tbl_hbr2,
2356 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr2),
2357 .serdes_tbl_hbr3 = qmp_v4_dp_serdes_tbl_hbr3,
2358 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v4_dp_serdes_tbl_hbr3),
2359
2360 .swing_hbr_rbr = &qmp_dp_v4_voltage_swing_hbr_rbr,
2361 .pre_emphasis_hbr_rbr = &qmp_dp_v4_pre_emphasis_hbr_rbr,
2362 .swing_hbr3_hbr2 = &qmp_dp_v3_voltage_swing_hbr3_hbr2,
2363 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v4_pre_emphasis_hbr3_hbr2,
2364
2365 .dp_aux_init = qmp_v4_dp_aux_init,
2366 .configure_dp_tx = qmp_v4_configure_dp_tx,
2367 .configure_dp_phy = qmp_v4_configure_dp_phy,
2368 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
2369
2370 .reset_list = msm8996_usb3phy_reset_l,
2371 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2372 .vreg_list = qmp_phy_vreg_l,
2373 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2374 .regs = qmp_v45_usb3phy_regs_layout,
2375
2376 .has_pwrdn_delay = true,
2377 };
2378
2379 static const struct qmp_phy_cfg sm8550_usb3dpphy_cfg = {
2380 .offsets = &qmp_combo_offsets_v3,
2381
2382 .serdes_tbl = sm8550_usb3_serdes_tbl,
2383 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl),
2384 .tx_tbl = sm8550_usb3_tx_tbl,
2385 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl),
2386 .rx_tbl = sm8550_usb3_rx_tbl,
2387 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl),
2388 .pcs_tbl = sm8550_usb3_pcs_tbl,
2389 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl),
2390 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl,
2391 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl),
2392
2393 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
2394 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
2395 .dp_tx_tbl = qmp_v6_dp_tx_tbl,
2396 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
2397
2398 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
2399 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
2400 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
2401 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
2402 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
2403 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
2404 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
2405 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
2406
2407 .swing_hbr_rbr = &qmp_dp_v5_voltage_swing_hbr_rbr,
2408 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
2409 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
2410 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
2411
2412 .dp_aux_init = qmp_v4_dp_aux_init,
2413 .configure_dp_tx = qmp_v4_configure_dp_tx,
2414 .configure_dp_phy = qmp_v4_configure_dp_phy,
2415 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
2416
2417 .regs = qmp_v6_usb3phy_regs_layout,
2418 .reset_list = msm8996_usb3phy_reset_l,
2419 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2420 .vreg_list = qmp_phy_vreg_l,
2421 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2422 };
2423
2424 static const struct qmp_phy_cfg sm8650_usb3dpphy_cfg = {
2425 .offsets = &qmp_combo_offsets_v3,
2426
2427 .serdes_tbl = sm8550_usb3_serdes_tbl,
2428 .serdes_tbl_num = ARRAY_SIZE(sm8550_usb3_serdes_tbl),
2429 .tx_tbl = sm8550_usb3_tx_tbl,
2430 .tx_tbl_num = ARRAY_SIZE(sm8550_usb3_tx_tbl),
2431 .rx_tbl = sm8550_usb3_rx_tbl,
2432 .rx_tbl_num = ARRAY_SIZE(sm8550_usb3_rx_tbl),
2433 .pcs_tbl = sm8550_usb3_pcs_tbl,
2434 .pcs_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_tbl),
2435 .pcs_usb_tbl = sm8550_usb3_pcs_usb_tbl,
2436 .pcs_usb_tbl_num = ARRAY_SIZE(sm8550_usb3_pcs_usb_tbl),
2437
2438 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
2439 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
2440 .dp_tx_tbl = qmp_v6_dp_tx_tbl,
2441 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
2442
2443 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
2444 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
2445 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
2446 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
2447 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
2448 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
2449 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
2450 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
2451
2452 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr,
2453 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
2454 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
2455 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
2456
2457 .dp_aux_init = qmp_v4_dp_aux_init,
2458 .configure_dp_tx = qmp_v4_configure_dp_tx,
2459 .configure_dp_phy = qmp_v4_configure_dp_phy,
2460 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
2461
2462 .regs = qmp_v6_usb3phy_regs_layout,
2463 .reset_list = msm8996_usb3phy_reset_l,
2464 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2465 .vreg_list = qmp_phy_vreg_l,
2466 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2467 };
2468
2469 static const struct qmp_phy_cfg sm8750_usb3dpphy_cfg = {
2470 .offsets = &qmp_combo_offsets_v8,
2471
2472 .serdes_tbl = sm8750_usb3_serdes_tbl,
2473 .serdes_tbl_num = ARRAY_SIZE(sm8750_usb3_serdes_tbl),
2474 .tx_tbl = sm8750_usb3_tx_tbl,
2475 .tx_tbl_num = ARRAY_SIZE(sm8750_usb3_tx_tbl),
2476 .rx_tbl = sm8750_usb3_rx_tbl,
2477 .rx_tbl_num = ARRAY_SIZE(sm8750_usb3_rx_tbl),
2478 .pcs_tbl = sm8750_usb3_pcs_tbl,
2479 .pcs_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_tbl),
2480 .pcs_usb_tbl = sm8750_usb3_pcs_usb_tbl,
2481 .pcs_usb_tbl_num = ARRAY_SIZE(sm8750_usb3_pcs_usb_tbl),
2482
2483 .dp_serdes_tbl = qmp_v6_dp_serdes_tbl,
2484 .dp_serdes_tbl_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl),
2485 .dp_tx_tbl = qmp_v6_dp_tx_tbl,
2486 .dp_tx_tbl_num = ARRAY_SIZE(qmp_v6_dp_tx_tbl),
2487
2488 .serdes_tbl_rbr = qmp_v6_dp_serdes_tbl_rbr,
2489 .serdes_tbl_rbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_rbr),
2490 .serdes_tbl_hbr = qmp_v6_dp_serdes_tbl_hbr,
2491 .serdes_tbl_hbr_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr),
2492 .serdes_tbl_hbr2 = qmp_v6_dp_serdes_tbl_hbr2,
2493 .serdes_tbl_hbr2_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr2),
2494 .serdes_tbl_hbr3 = qmp_v6_dp_serdes_tbl_hbr3,
2495 .serdes_tbl_hbr3_num = ARRAY_SIZE(qmp_v6_dp_serdes_tbl_hbr3),
2496
2497 .swing_hbr_rbr = &qmp_dp_v6_voltage_swing_hbr_rbr,
2498 .pre_emphasis_hbr_rbr = &qmp_dp_v6_pre_emphasis_hbr_rbr,
2499 .swing_hbr3_hbr2 = &qmp_dp_v5_voltage_swing_hbr3_hbr2,
2500 .pre_emphasis_hbr3_hbr2 = &qmp_dp_v5_pre_emphasis_hbr3_hbr2,
2501
2502 .dp_aux_init = qmp_v4_dp_aux_init,
2503 .configure_dp_tx = qmp_v4_configure_dp_tx,
2504 .configure_dp_phy = qmp_v4_configure_dp_phy,
2505 .calibrate_dp_phy = qmp_v4_calibrate_dp_phy,
2506
2507 .regs = qmp_v8_usb3phy_regs_layout,
2508 .reset_list = msm8996_usb3phy_reset_l,
2509 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l),
2510 .vreg_list = qmp_phy_vreg_l,
2511 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
2512 };
2513
qmp_combo_dp_serdes_init(struct qmp_combo * qmp)2514 static int qmp_combo_dp_serdes_init(struct qmp_combo *qmp)
2515 {
2516 const struct qmp_phy_cfg *cfg = qmp->cfg;
2517 void __iomem *serdes = qmp->dp_serdes;
2518 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2519
2520 qmp_configure(qmp->dev, serdes, cfg->dp_serdes_tbl,
2521 cfg->dp_serdes_tbl_num);
2522
2523 switch (dp_opts->link_rate) {
2524 case 1620:
2525 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_rbr,
2526 cfg->serdes_tbl_rbr_num);
2527 break;
2528 case 2700:
2529 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr,
2530 cfg->serdes_tbl_hbr_num);
2531 break;
2532 case 5400:
2533 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr2,
2534 cfg->serdes_tbl_hbr2_num);
2535 break;
2536 case 8100:
2537 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl_hbr3,
2538 cfg->serdes_tbl_hbr3_num);
2539 break;
2540 default:
2541 /* Other link rates aren't supported */
2542 return -EINVAL;
2543 }
2544
2545 return 0;
2546 }
2547
qmp_v3_dp_aux_init(struct qmp_combo * qmp)2548 static void qmp_v3_dp_aux_init(struct qmp_combo *qmp)
2549 {
2550 const struct qmp_phy_cfg *cfg = qmp->cfg;
2551
2552 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2553 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2554 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2555
2556 /* Turn on BIAS current for PHY/PLL */
2557 writel(QSERDES_V3_COM_BIAS_EN | QSERDES_V3_COM_BIAS_EN_MUX |
2558 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL,
2559 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
2560
2561 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2562
2563 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2564 DP_PHY_PD_CTL_LANE_0_1_PWRDN |
2565 DP_PHY_PD_CTL_LANE_2_3_PWRDN | DP_PHY_PD_CTL_PLL_PWRDN |
2566 DP_PHY_PD_CTL_DP_CLAMP_EN,
2567 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2568
2569 writel(QSERDES_V3_COM_BIAS_EN |
2570 QSERDES_V3_COM_BIAS_EN_MUX | QSERDES_V3_COM_CLKBUF_R_EN |
2571 QSERDES_V3_COM_CLKBUF_L_EN | QSERDES_V3_COM_EN_SYSCLK_TX_SEL |
2572 QSERDES_V3_COM_CLKBUF_RX_DRIVE_L,
2573 qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
2574
2575 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2576 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2577 writel(0x24, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2578 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2579 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2580 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2581 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2582 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2583 writel(0xbb, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2584 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
2585 qmp->dp_aux_cfg = 0;
2586
2587 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2588 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2589 PHY_AUX_REQ_ERR_MASK,
2590 qmp->dp_dp_phy + QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK);
2591 }
2592
qmp_combo_configure_dp_swing(struct qmp_combo * qmp)2593 static int qmp_combo_configure_dp_swing(struct qmp_combo *qmp)
2594 {
2595 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2596 const struct qmp_phy_cfg *cfg = qmp->cfg;
2597 unsigned int v_level = 0, p_level = 0;
2598 u8 voltage_swing_cfg, pre_emphasis_cfg;
2599 int i;
2600
2601 for (i = 0; i < dp_opts->lanes; i++) {
2602 v_level = max(v_level, dp_opts->voltage[i]);
2603 p_level = max(p_level, dp_opts->pre[i]);
2604 }
2605
2606 if (dp_opts->link_rate <= 2700) {
2607 voltage_swing_cfg = (*cfg->swing_hbr_rbr)[v_level][p_level];
2608 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr_rbr)[v_level][p_level];
2609 } else {
2610 voltage_swing_cfg = (*cfg->swing_hbr3_hbr2)[v_level][p_level];
2611 pre_emphasis_cfg = (*cfg->pre_emphasis_hbr3_hbr2)[v_level][p_level];
2612 }
2613
2614 /* TODO: Move check to config check */
2615 if (voltage_swing_cfg == 0xFF && pre_emphasis_cfg == 0xFF)
2616 return -EINVAL;
2617
2618 /* Enable MUX to use Cursor values from these registers */
2619 voltage_swing_cfg |= DP_PHY_TXn_TX_DRV_LVL_MUX_EN;
2620 pre_emphasis_cfg |= DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN;
2621
2622 writel(voltage_swing_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2623 writel(pre_emphasis_cfg, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2624 writel(voltage_swing_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2625 writel(pre_emphasis_cfg, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2626
2627 return 0;
2628 }
2629
qmp_v3_configure_dp_tx(struct qmp_combo * qmp)2630 static void qmp_v3_configure_dp_tx(struct qmp_combo *qmp)
2631 {
2632 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2633 u32 bias_en, drvr_en;
2634
2635 if (qmp_combo_configure_dp_swing(qmp) < 0)
2636 return;
2637
2638 if (dp_opts->lanes == 1) {
2639 bias_en = 0x3e;
2640 drvr_en = 0x13;
2641 } else {
2642 bias_en = 0x3f;
2643 drvr_en = 0x10;
2644 }
2645
2646 writel(drvr_en, qmp->dp_tx + QSERDES_V3_TX_HIGHZ_DRVR_EN);
2647 writel(bias_en, qmp->dp_tx + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
2648 writel(drvr_en, qmp->dp_tx2 + QSERDES_V3_TX_HIGHZ_DRVR_EN);
2649 writel(bias_en, qmp->dp_tx2 + QSERDES_V3_TX_TRANSCEIVER_BIAS_EN);
2650 }
2651
qmp_combo_configure_dp_mode(struct qmp_combo * qmp)2652 static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp)
2653 {
2654 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
2655 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2656 u32 val;
2657
2658 val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2659 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN;
2660
2661 if (dp_opts->lanes == 4 || reverse)
2662 val |= DP_PHY_PD_CTL_LANE_0_1_PWRDN;
2663 if (dp_opts->lanes == 4 || !reverse)
2664 val |= DP_PHY_PD_CTL_LANE_2_3_PWRDN;
2665
2666 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2667
2668 if (reverse)
2669 writel(0x4c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
2670 else
2671 writel(0x5c, qmp->dp_dp_phy + QSERDES_DP_PHY_MODE);
2672
2673 return reverse;
2674 }
2675
qmp_combo_configure_dp_clocks(struct qmp_combo * qmp)2676 static int qmp_combo_configure_dp_clocks(struct qmp_combo *qmp)
2677 {
2678 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2679 u32 phy_vco_div;
2680 unsigned long pixel_freq;
2681 const struct qmp_phy_cfg *cfg = qmp->cfg;
2682
2683 switch (dp_opts->link_rate) {
2684 case 1620:
2685 phy_vco_div = 0x1;
2686 pixel_freq = 1620000000UL / 2;
2687 break;
2688 case 2700:
2689 phy_vco_div = 0x1;
2690 pixel_freq = 2700000000UL / 2;
2691 break;
2692 case 5400:
2693 phy_vco_div = 0x2;
2694 pixel_freq = 5400000000UL / 4;
2695 break;
2696 case 8100:
2697 phy_vco_div = 0x0;
2698 pixel_freq = 8100000000UL / 6;
2699 break;
2700 default:
2701 /* Other link rates aren't supported */
2702 return -EINVAL;
2703 }
2704 writel(phy_vco_div, qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_VCO_DIV]);
2705
2706 clk_set_rate(qmp->dp_link_hw.clk, dp_opts->link_rate * 100000);
2707 clk_set_rate(qmp->dp_pixel_hw.clk, pixel_freq);
2708
2709 return 0;
2710 }
2711
qmp_v3_configure_dp_phy(struct qmp_combo * qmp)2712 static int qmp_v3_configure_dp_phy(struct qmp_combo *qmp)
2713 {
2714 const struct qmp_phy_cfg *cfg = qmp->cfg;
2715 u32 status;
2716 int ret;
2717
2718 qmp_combo_configure_dp_mode(qmp);
2719
2720 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL);
2721 writel(0x05, qmp->dp_dp_phy + QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL);
2722
2723 ret = qmp_combo_configure_dp_clocks(qmp);
2724 if (ret)
2725 return ret;
2726
2727 writel(0x04, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2728 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2729 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2730 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2731 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2732
2733 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]);
2734
2735 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS],
2736 status,
2737 ((status & BIT(0)) > 0),
2738 500,
2739 10000))
2740 return -ETIMEDOUT;
2741
2742 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2743
2744 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2745 status,
2746 ((status & BIT(1)) > 0),
2747 500,
2748 10000))
2749 return -ETIMEDOUT;
2750
2751 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2752 udelay(2000);
2753 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2754
2755 return readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2756 status,
2757 ((status & BIT(1)) > 0),
2758 500,
2759 10000);
2760 }
2761
2762 /*
2763 * We need to calibrate the aux setting here as many times
2764 * as the caller tries
2765 */
qmp_v3_calibrate_dp_phy(struct qmp_combo * qmp)2766 static int qmp_v3_calibrate_dp_phy(struct qmp_combo *qmp)
2767 {
2768 static const u8 cfg1_settings[] = { 0x13, 0x23, 0x1d };
2769 u8 val;
2770
2771 qmp->dp_aux_cfg++;
2772 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2773 val = cfg1_settings[qmp->dp_aux_cfg];
2774
2775 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2776
2777 return 0;
2778 }
2779
qmp_v4_dp_aux_init(struct qmp_combo * qmp)2780 static void qmp_v4_dp_aux_init(struct qmp_combo *qmp)
2781 {
2782 const struct qmp_phy_cfg *cfg = qmp->cfg;
2783
2784 writel(DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_PSR_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN |
2785 DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN,
2786 qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
2787
2788 /* Turn on BIAS current for PHY/PLL */
2789 writel(0x17, qmp->dp_serdes + cfg->regs[QPHY_COM_BIAS_EN_CLKBUFLR_EN]);
2790
2791 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG0);
2792 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2793 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2794 writel(0x00, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG3);
2795 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG4);
2796 writel(0x26, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG5);
2797 writel(0x0a, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG6);
2798 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG7);
2799 writel(0xb7, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG8);
2800 writel(0x03, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG9);
2801 qmp->dp_aux_cfg = 0;
2802
2803 writel(PHY_AUX_STOP_ERR_MASK | PHY_AUX_DEC_ERR_MASK |
2804 PHY_AUX_SYNC_ERR_MASK | PHY_AUX_ALIGN_ERR_MASK |
2805 PHY_AUX_REQ_ERR_MASK,
2806 qmp->dp_dp_phy + QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK);
2807 }
2808
qmp_v4_configure_dp_tx(struct qmp_combo * qmp)2809 static void qmp_v4_configure_dp_tx(struct qmp_combo *qmp)
2810 {
2811 const struct qmp_phy_cfg *cfg = qmp->cfg;
2812
2813 /* Program default values before writing proper values */
2814 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2815 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2816
2817 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2818 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2819
2820 qmp_combo_configure_dp_swing(qmp);
2821 }
2822
qmp_v456_configure_dp_phy(struct qmp_combo * qmp)2823 static int qmp_v456_configure_dp_phy(struct qmp_combo *qmp)
2824 {
2825 const struct qmp_phy_cfg *cfg = qmp->cfg;
2826 u32 status;
2827 int ret;
2828
2829 writel(0x0f, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG_1);
2830
2831 qmp_combo_configure_dp_mode(qmp);
2832
2833 writel(0x13, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2834 writel(0xa4, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG2);
2835
2836 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL);
2837 writel(0x05, qmp->dp_dp_phy + QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL);
2838
2839 ret = qmp_combo_configure_dp_clocks(qmp);
2840 if (ret)
2841 return ret;
2842
2843 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2844 writel(0x05, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2845 writel(0x01, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2846 writel(0x09, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2847
2848 writel(0x20, qmp->dp_serdes + cfg->regs[QPHY_COM_RESETSM_CNTRL]);
2849
2850 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_C_READY_STATUS],
2851 status,
2852 ((status & BIT(0)) > 0),
2853 500,
2854 10000))
2855 return -ETIMEDOUT;
2856
2857 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS],
2858 status,
2859 ((status & BIT(0)) > 0),
2860 500,
2861 10000))
2862 return -ETIMEDOUT;
2863
2864 if (readl_poll_timeout(qmp->dp_serdes + cfg->regs[QPHY_COM_CMN_STATUS],
2865 status,
2866 ((status & BIT(1)) > 0),
2867 500,
2868 10000))
2869 return -ETIMEDOUT;
2870
2871 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2872
2873 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2874 status,
2875 ((status & BIT(0)) > 0),
2876 500,
2877 10000))
2878 return -ETIMEDOUT;
2879
2880 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2881 status,
2882 ((status & BIT(1)) > 0),
2883 500,
2884 10000))
2885 return -ETIMEDOUT;
2886
2887 return 0;
2888 }
2889
qmp_v4_configure_dp_phy(struct qmp_combo * qmp)2890 static int qmp_v4_configure_dp_phy(struct qmp_combo *qmp)
2891 {
2892 const struct qmp_phy_cfg *cfg = qmp->cfg;
2893 bool reverse = (qmp->orientation == TYPEC_ORIENTATION_REVERSE);
2894 const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts;
2895 u32 bias0_en, drvr0_en, bias1_en, drvr1_en;
2896 u32 status;
2897 int ret;
2898
2899 ret = qmp_v456_configure_dp_phy(qmp);
2900 if (ret < 0)
2901 return ret;
2902
2903 /*
2904 * At least for 7nm DP PHY this has to be done after enabling link
2905 * clock.
2906 */
2907
2908 if (dp_opts->lanes == 1) {
2909 bias0_en = reverse ? 0x3e : 0x15;
2910 bias1_en = reverse ? 0x15 : 0x3e;
2911 drvr0_en = reverse ? 0x13 : 0x10;
2912 drvr1_en = reverse ? 0x10 : 0x13;
2913 } else if (dp_opts->lanes == 2) {
2914 bias0_en = reverse ? 0x3f : 0x15;
2915 bias1_en = reverse ? 0x15 : 0x3f;
2916 drvr0_en = 0x10;
2917 drvr1_en = 0x10;
2918 } else {
2919 bias0_en = 0x3f;
2920 bias1_en = 0x3f;
2921 drvr0_en = 0x10;
2922 drvr1_en = 0x10;
2923 }
2924
2925 writel(drvr0_en, qmp->dp_tx + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
2926 writel(bias0_en, qmp->dp_tx + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
2927 writel(drvr1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_HIGHZ_DRVR_EN]);
2928 writel(bias1_en, qmp->dp_tx2 + cfg->regs[QPHY_TX_TRANSCEIVER_BIAS_EN]);
2929
2930 writel(0x18, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2931 udelay(2000);
2932 writel(0x19, qmp->dp_dp_phy + QSERDES_DP_PHY_CFG);
2933
2934 if (readl_poll_timeout(qmp->dp_dp_phy + cfg->regs[QPHY_DP_PHY_STATUS],
2935 status,
2936 ((status & BIT(1)) > 0),
2937 500,
2938 10000))
2939 return -ETIMEDOUT;
2940
2941 writel(0x0a, qmp->dp_tx + cfg->regs[QPHY_TX_TX_POL_INV]);
2942 writel(0x0a, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_POL_INV]);
2943
2944 writel(0x27, qmp->dp_tx + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2945 writel(0x27, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_DRV_LVL]);
2946
2947 writel(0x20, qmp->dp_tx + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2948 writel(0x20, qmp->dp_tx2 + cfg->regs[QPHY_TX_TX_EMP_POST1_LVL]);
2949
2950 return 0;
2951 }
2952
2953 /*
2954 * We need to calibrate the aux setting here as many times
2955 * as the caller tries
2956 */
qmp_v4_calibrate_dp_phy(struct qmp_combo * qmp)2957 static int qmp_v4_calibrate_dp_phy(struct qmp_combo *qmp)
2958 {
2959 static const u8 cfg1_settings[] = { 0x20, 0x13, 0x23, 0x1d };
2960 u8 val;
2961
2962 qmp->dp_aux_cfg++;
2963 qmp->dp_aux_cfg %= ARRAY_SIZE(cfg1_settings);
2964 val = cfg1_settings[qmp->dp_aux_cfg];
2965
2966 writel(val, qmp->dp_dp_phy + QSERDES_DP_PHY_AUX_CFG1);
2967
2968 return 0;
2969 }
2970
qmp_combo_dp_configure(struct phy * phy,union phy_configure_opts * opts)2971 static int qmp_combo_dp_configure(struct phy *phy, union phy_configure_opts *opts)
2972 {
2973 const struct phy_configure_opts_dp *dp_opts = &opts->dp;
2974 struct qmp_combo *qmp = phy_get_drvdata(phy);
2975 const struct qmp_phy_cfg *cfg = qmp->cfg;
2976
2977 mutex_lock(&qmp->phy_mutex);
2978
2979 memcpy(&qmp->dp_opts, dp_opts, sizeof(*dp_opts));
2980 if (qmp->dp_opts.set_voltages) {
2981 cfg->configure_dp_tx(qmp);
2982 qmp->dp_opts.set_voltages = 0;
2983 }
2984
2985 mutex_unlock(&qmp->phy_mutex);
2986
2987 return 0;
2988 }
2989
qmp_combo_dp_calibrate(struct phy * phy)2990 static int qmp_combo_dp_calibrate(struct phy *phy)
2991 {
2992 struct qmp_combo *qmp = phy_get_drvdata(phy);
2993 const struct qmp_phy_cfg *cfg = qmp->cfg;
2994 int ret = 0;
2995
2996 mutex_lock(&qmp->phy_mutex);
2997
2998 if (cfg->calibrate_dp_phy)
2999 ret = cfg->calibrate_dp_phy(qmp);
3000
3001 mutex_unlock(&qmp->phy_mutex);
3002
3003 return ret;
3004 }
3005
qmp_combo_com_init(struct qmp_combo * qmp,bool force)3006 static int qmp_combo_com_init(struct qmp_combo *qmp, bool force)
3007 {
3008 const struct qmp_phy_cfg *cfg = qmp->cfg;
3009 void __iomem *com = qmp->com;
3010 int ret;
3011 u32 val;
3012
3013 if (!force && qmp->init_count++)
3014 return 0;
3015
3016 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
3017 if (ret) {
3018 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
3019 goto err_decrement_count;
3020 }
3021
3022 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
3023 if (ret) {
3024 dev_err(qmp->dev, "reset assert failed\n");
3025 goto err_disable_regulators;
3026 }
3027
3028 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
3029 if (ret) {
3030 dev_err(qmp->dev, "reset deassert failed\n");
3031 goto err_disable_regulators;
3032 }
3033
3034 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
3035 if (ret)
3036 goto err_assert_reset;
3037
3038 qphy_setbits(com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, SW_PWRDN);
3039
3040 /* override hardware control for reset of qmp phy */
3041 qphy_setbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
3042 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
3043 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
3044
3045 /* Use software based port select and switch on typec orientation */
3046 val = SW_PORTSELECT_MUX;
3047 if (qmp->orientation == TYPEC_ORIENTATION_REVERSE)
3048 val |= SW_PORTSELECT_VAL;
3049 writel(val, com + QPHY_V3_DP_COM_TYPEC_CTRL);
3050
3051 switch (qmp->qmpphy_mode) {
3052 case QMPPHY_MODE_USB3DP:
3053 writel(USB3_MODE | DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
3054
3055 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
3056 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
3057 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
3058 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
3059 break;
3060
3061 case QMPPHY_MODE_DP_ONLY:
3062 writel(DP_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
3063
3064 /* bring QMP DP PHY PCS block out of reset */
3065 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
3066 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET);
3067 break;
3068
3069 case QMPPHY_MODE_USB3_ONLY:
3070 writel(USB3_MODE, com + QPHY_V3_DP_COM_PHY_MODE_CTRL);
3071
3072 /* bring QMP USB PHY PCS block out of reset */
3073 qphy_clrbits(com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
3074 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
3075 break;
3076 }
3077
3078 qphy_clrbits(com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
3079 qphy_clrbits(com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
3080
3081 qphy_setbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3082 SW_PWRDN);
3083
3084 return 0;
3085
3086 err_assert_reset:
3087 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
3088 err_disable_regulators:
3089 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
3090 err_decrement_count:
3091 qmp->init_count--;
3092
3093 return ret;
3094 }
3095
qmp_combo_com_exit(struct qmp_combo * qmp,bool force)3096 static int qmp_combo_com_exit(struct qmp_combo *qmp, bool force)
3097 {
3098 const struct qmp_phy_cfg *cfg = qmp->cfg;
3099
3100 if (!force && --qmp->init_count)
3101 return 0;
3102
3103 reset_control_bulk_assert(cfg->num_resets, qmp->resets);
3104
3105 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
3106
3107 regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
3108
3109 return 0;
3110 }
3111
qmp_combo_dp_init(struct phy * phy)3112 static int qmp_combo_dp_init(struct phy *phy)
3113 {
3114 struct qmp_combo *qmp = phy_get_drvdata(phy);
3115 const struct qmp_phy_cfg *cfg = qmp->cfg;
3116 int ret;
3117
3118 mutex_lock(&qmp->phy_mutex);
3119
3120 ret = qmp_combo_com_init(qmp, false);
3121 if (ret)
3122 goto out_unlock;
3123
3124 cfg->dp_aux_init(qmp);
3125
3126 qmp->dp_init_count++;
3127
3128 out_unlock:
3129 mutex_unlock(&qmp->phy_mutex);
3130 return ret;
3131 }
3132
qmp_combo_dp_exit(struct phy * phy)3133 static int qmp_combo_dp_exit(struct phy *phy)
3134 {
3135 struct qmp_combo *qmp = phy_get_drvdata(phy);
3136
3137 mutex_lock(&qmp->phy_mutex);
3138
3139 qmp_combo_com_exit(qmp, false);
3140
3141 qmp->dp_init_count--;
3142
3143 mutex_unlock(&qmp->phy_mutex);
3144
3145 return 0;
3146 }
3147
qmp_combo_dp_power_on(struct phy * phy)3148 static int qmp_combo_dp_power_on(struct phy *phy)
3149 {
3150 struct qmp_combo *qmp = phy_get_drvdata(phy);
3151 const struct qmp_phy_cfg *cfg = qmp->cfg;
3152 void __iomem *tx = qmp->dp_tx;
3153 void __iomem *tx2 = qmp->dp_tx2;
3154
3155 mutex_lock(&qmp->phy_mutex);
3156
3157 qmp_combo_dp_serdes_init(qmp);
3158
3159 qmp_configure_lane(qmp->dev, tx, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 1);
3160 qmp_configure_lane(qmp->dev, tx2, cfg->dp_tx_tbl, cfg->dp_tx_tbl_num, 2);
3161
3162 /* Configure special DP tx tunings */
3163 cfg->configure_dp_tx(qmp);
3164
3165 /* Configure link rate, swing, etc. */
3166 cfg->configure_dp_phy(qmp);
3167
3168 qmp->dp_powered_on = true;
3169
3170 mutex_unlock(&qmp->phy_mutex);
3171
3172 return 0;
3173 }
3174
qmp_combo_dp_power_off(struct phy * phy)3175 static int qmp_combo_dp_power_off(struct phy *phy)
3176 {
3177 struct qmp_combo *qmp = phy_get_drvdata(phy);
3178
3179 mutex_lock(&qmp->phy_mutex);
3180
3181 /* Assert DP PHY power down */
3182 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
3183
3184 qmp->dp_powered_on = false;
3185
3186 mutex_unlock(&qmp->phy_mutex);
3187
3188 return 0;
3189 }
3190
qmp_combo_usb_power_on(struct phy * phy)3191 static int qmp_combo_usb_power_on(struct phy *phy)
3192 {
3193 struct qmp_combo *qmp = phy_get_drvdata(phy);
3194 const struct qmp_phy_cfg *cfg = qmp->cfg;
3195 void __iomem *serdes = qmp->serdes;
3196 void __iomem *tx = qmp->tx;
3197 void __iomem *rx = qmp->rx;
3198 void __iomem *tx2 = qmp->tx2;
3199 void __iomem *rx2 = qmp->rx2;
3200 void __iomem *pcs = qmp->pcs;
3201 void __iomem *pcs_usb = qmp->pcs_usb;
3202 void __iomem *status;
3203 unsigned int val;
3204 int ret;
3205
3206 qmp_configure(qmp->dev, serdes, cfg->serdes_tbl, cfg->serdes_tbl_num);
3207
3208 ret = clk_prepare_enable(qmp->pipe_clk);
3209 if (ret) {
3210 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
3211 return ret;
3212 }
3213
3214 /* Tx, Rx, and PCS configurations */
3215 qmp_configure_lane(qmp->dev, tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
3216 qmp_configure_lane(qmp->dev, tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
3217
3218 qmp_configure_lane(qmp->dev, rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
3219 qmp_configure_lane(qmp->dev, rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
3220
3221 qmp_configure(qmp->dev, pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
3222
3223 if (pcs_usb)
3224 qmp_configure(qmp->dev, pcs_usb, cfg->pcs_usb_tbl,
3225 cfg->pcs_usb_tbl_num);
3226
3227 if (cfg->has_pwrdn_delay)
3228 usleep_range(10, 20);
3229
3230 /* Pull PHY out of reset state */
3231 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3232
3233 /* start SerDes and Phy-Coding-Sublayer */
3234 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
3235
3236 status = pcs + cfg->regs[QPHY_PCS_STATUS];
3237 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
3238 PHY_INIT_COMPLETE_TIMEOUT);
3239 if (ret) {
3240 dev_err(qmp->dev, "phy initialization timed-out\n");
3241 goto err_disable_pipe_clk;
3242 }
3243
3244 return 0;
3245
3246 err_disable_pipe_clk:
3247 clk_disable_unprepare(qmp->pipe_clk);
3248
3249 return ret;
3250 }
3251
qmp_combo_usb_power_off(struct phy * phy)3252 static int qmp_combo_usb_power_off(struct phy *phy)
3253 {
3254 struct qmp_combo *qmp = phy_get_drvdata(phy);
3255 const struct qmp_phy_cfg *cfg = qmp->cfg;
3256
3257 clk_disable_unprepare(qmp->pipe_clk);
3258
3259 /* PHY reset */
3260 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
3261
3262 /* stop SerDes and Phy-Coding-Sublayer */
3263 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
3264 SERDES_START | PCS_START);
3265
3266 /* Put PHY into POWER DOWN state: active low */
3267 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
3268 SW_PWRDN);
3269
3270 return 0;
3271 }
3272
qmp_combo_usb_init(struct phy * phy)3273 static int qmp_combo_usb_init(struct phy *phy)
3274 {
3275 struct qmp_combo *qmp = phy_get_drvdata(phy);
3276 int ret;
3277
3278 mutex_lock(&qmp->phy_mutex);
3279 ret = qmp_combo_com_init(qmp, false);
3280 if (ret)
3281 goto out_unlock;
3282
3283 ret = qmp_combo_usb_power_on(phy);
3284 if (ret) {
3285 qmp_combo_com_exit(qmp, false);
3286 goto out_unlock;
3287 }
3288
3289 qmp->usb_init_count++;
3290
3291 out_unlock:
3292 mutex_unlock(&qmp->phy_mutex);
3293 return ret;
3294 }
3295
qmp_combo_usb_exit(struct phy * phy)3296 static int qmp_combo_usb_exit(struct phy *phy)
3297 {
3298 struct qmp_combo *qmp = phy_get_drvdata(phy);
3299 int ret;
3300
3301 mutex_lock(&qmp->phy_mutex);
3302 ret = qmp_combo_usb_power_off(phy);
3303 if (ret)
3304 goto out_unlock;
3305
3306 ret = qmp_combo_com_exit(qmp, false);
3307 if (ret)
3308 goto out_unlock;
3309
3310 qmp->usb_init_count--;
3311
3312 out_unlock:
3313 mutex_unlock(&qmp->phy_mutex);
3314 return ret;
3315 }
3316
qmp_combo_usb_set_mode(struct phy * phy,enum phy_mode mode,int submode)3317 static int qmp_combo_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
3318 {
3319 struct qmp_combo *qmp = phy_get_drvdata(phy);
3320
3321 qmp->phy_mode = mode;
3322
3323 return 0;
3324 }
3325
3326 static const struct phy_ops qmp_combo_usb_phy_ops = {
3327 .init = qmp_combo_usb_init,
3328 .exit = qmp_combo_usb_exit,
3329 .set_mode = qmp_combo_usb_set_mode,
3330 .owner = THIS_MODULE,
3331 };
3332
3333 static const struct phy_ops qmp_combo_dp_phy_ops = {
3334 .init = qmp_combo_dp_init,
3335 .configure = qmp_combo_dp_configure,
3336 .power_on = qmp_combo_dp_power_on,
3337 .calibrate = qmp_combo_dp_calibrate,
3338 .power_off = qmp_combo_dp_power_off,
3339 .exit = qmp_combo_dp_exit,
3340 .owner = THIS_MODULE,
3341 };
3342
qmp_combo_enable_autonomous_mode(struct qmp_combo * qmp)3343 static void qmp_combo_enable_autonomous_mode(struct qmp_combo *qmp)
3344 {
3345 const struct qmp_phy_cfg *cfg = qmp->cfg;
3346 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
3347 void __iomem *pcs_misc = qmp->pcs_misc;
3348 u32 intr_mask;
3349
3350 if (qmp->phy_mode == PHY_MODE_USB_HOST_SS ||
3351 qmp->phy_mode == PHY_MODE_USB_DEVICE_SS)
3352 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
3353 else
3354 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
3355
3356 /* Clear any pending interrupts status */
3357 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3358 /* Writing 1 followed by 0 clears the interrupt */
3359 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3360
3361 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
3362 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
3363
3364 /* Enable required PHY autonomous mode interrupts */
3365 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
3366
3367 /* Enable i/o clamp_n for autonomous mode */
3368 if (pcs_misc)
3369 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
3370 }
3371
qmp_combo_disable_autonomous_mode(struct qmp_combo * qmp)3372 static void qmp_combo_disable_autonomous_mode(struct qmp_combo *qmp)
3373 {
3374 const struct qmp_phy_cfg *cfg = qmp->cfg;
3375 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
3376 void __iomem *pcs_misc = qmp->pcs_misc;
3377
3378 /* Disable i/o clamp_n on resume for normal mode */
3379 if (pcs_misc)
3380 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
3381
3382 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
3383 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
3384
3385 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3386 /* Writing 1 followed by 0 clears the interrupt */
3387 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
3388 }
3389
qmp_combo_runtime_suspend(struct device * dev)3390 static int __maybe_unused qmp_combo_runtime_suspend(struct device *dev)
3391 {
3392 struct qmp_combo *qmp = dev_get_drvdata(dev);
3393
3394 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->phy_mode);
3395
3396 if (!qmp->init_count) {
3397 dev_vdbg(dev, "PHY not initialized, bailing out\n");
3398 return 0;
3399 }
3400
3401 qmp_combo_enable_autonomous_mode(qmp);
3402
3403 clk_disable_unprepare(qmp->pipe_clk);
3404 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
3405
3406 return 0;
3407 }
3408
qmp_combo_runtime_resume(struct device * dev)3409 static int __maybe_unused qmp_combo_runtime_resume(struct device *dev)
3410 {
3411 struct qmp_combo *qmp = dev_get_drvdata(dev);
3412 int ret = 0;
3413
3414 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->phy_mode);
3415
3416 if (!qmp->init_count) {
3417 dev_vdbg(dev, "PHY not initialized, bailing out\n");
3418 return 0;
3419 }
3420
3421 ret = clk_bulk_prepare_enable(qmp->num_clks, qmp->clks);
3422 if (ret)
3423 return ret;
3424
3425 ret = clk_prepare_enable(qmp->pipe_clk);
3426 if (ret) {
3427 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
3428 clk_bulk_disable_unprepare(qmp->num_clks, qmp->clks);
3429 return ret;
3430 }
3431
3432 qmp_combo_disable_autonomous_mode(qmp);
3433
3434 return 0;
3435 }
3436
3437 static const struct dev_pm_ops qmp_combo_pm_ops = {
3438 SET_RUNTIME_PM_OPS(qmp_combo_runtime_suspend,
3439 qmp_combo_runtime_resume, NULL)
3440 };
3441
qmp_combo_vreg_init(struct qmp_combo * qmp)3442 static int qmp_combo_vreg_init(struct qmp_combo *qmp)
3443 {
3444 const struct qmp_phy_cfg *cfg = qmp->cfg;
3445 struct device *dev = qmp->dev;
3446 int num = cfg->num_vregs;
3447 int ret, i;
3448
3449 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
3450 if (!qmp->vregs)
3451 return -ENOMEM;
3452
3453 for (i = 0; i < num; i++)
3454 qmp->vregs[i].supply = cfg->vreg_list[i].name;
3455
3456 ret = devm_regulator_bulk_get(dev, num, qmp->vregs);
3457 if (ret) {
3458 dev_err(dev, "failed at devm_regulator_bulk_get\n");
3459 return ret;
3460 }
3461
3462 for (i = 0; i < num; i++) {
3463 ret = regulator_set_load(qmp->vregs[i].consumer,
3464 cfg->vreg_list[i].enable_load);
3465 if (ret) {
3466 dev_err(dev, "failed to set load at %s\n",
3467 qmp->vregs[i].supply);
3468 return ret;
3469 }
3470 }
3471
3472 return 0;
3473 }
3474
qmp_combo_reset_init(struct qmp_combo * qmp)3475 static int qmp_combo_reset_init(struct qmp_combo *qmp)
3476 {
3477 const struct qmp_phy_cfg *cfg = qmp->cfg;
3478 struct device *dev = qmp->dev;
3479 int i;
3480 int ret;
3481
3482 qmp->resets = devm_kcalloc(dev, cfg->num_resets,
3483 sizeof(*qmp->resets), GFP_KERNEL);
3484 if (!qmp->resets)
3485 return -ENOMEM;
3486
3487 for (i = 0; i < cfg->num_resets; i++)
3488 qmp->resets[i].id = cfg->reset_list[i];
3489
3490 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
3491 if (ret)
3492 return dev_err_probe(dev, ret, "failed to get resets\n");
3493
3494 return 0;
3495 }
3496
qmp_combo_clk_init(struct qmp_combo * qmp)3497 static int qmp_combo_clk_init(struct qmp_combo *qmp)
3498 {
3499 struct device *dev = qmp->dev;
3500 int num = ARRAY_SIZE(qmp_combo_phy_clk_l);
3501 int i;
3502
3503 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
3504 if (!qmp->clks)
3505 return -ENOMEM;
3506
3507 for (i = 0; i < num; i++)
3508 qmp->clks[i].id = qmp_combo_phy_clk_l[i];
3509
3510 qmp->num_clks = num;
3511
3512 return devm_clk_bulk_get_optional(dev, num, qmp->clks);
3513 }
3514
phy_clk_release_provider(void * res)3515 static void phy_clk_release_provider(void *res)
3516 {
3517 of_clk_del_provider(res);
3518 }
3519
3520 /*
3521 * Register a fixed rate pipe clock.
3522 *
3523 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
3524 * controls it. The <s>_pipe_clk coming out of the GCC is requested
3525 * by the PHY driver for its operations.
3526 * We register the <s>_pipe_clksrc here. The gcc driver takes care
3527 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
3528 * Below picture shows this relationship.
3529 *
3530 * +---------------+
3531 * | PHY block |<<---------------------------------------+
3532 * | | |
3533 * | +-------+ | +-----+ |
3534 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
3535 * clk | +-------+ | +-----+
3536 * +---------------+
3537 */
phy_pipe_clk_register(struct qmp_combo * qmp,struct device_node * np)3538 static int phy_pipe_clk_register(struct qmp_combo *qmp, struct device_node *np)
3539 {
3540 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
3541 struct clk_init_data init = { };
3542 char name[64];
3543
3544 snprintf(name, sizeof(name), "%s::pipe_clk", dev_name(qmp->dev));
3545 init.name = name;
3546 init.ops = &clk_fixed_rate_ops;
3547
3548 /* controllers using QMP phys use 125MHz pipe clock interface */
3549 fixed->fixed_rate = 125000000;
3550 fixed->hw.init = &init;
3551
3552 return devm_clk_hw_register(qmp->dev, &fixed->hw);
3553 }
3554
3555 /*
3556 * Display Port PLL driver block diagram for branch clocks
3557 *
3558 * +------------------------------+
3559 * | DP_VCO_CLK |
3560 * | |
3561 * | +-------------------+ |
3562 * | | (DP PLL/VCO) | |
3563 * | +---------+---------+ |
3564 * | v |
3565 * | +----------+-----------+ |
3566 * | | hsclk_divsel_clk_src | |
3567 * | +----------+-----------+ |
3568 * +------------------------------+
3569 * |
3570 * +---------<---------v------------>----------+
3571 * | |
3572 * +--------v----------------+ |
3573 * | dp_phy_pll_link_clk | |
3574 * | link_clk | |
3575 * +--------+----------------+ |
3576 * | |
3577 * | |
3578 * v v
3579 * Input to DISPCC block |
3580 * for link clk, crypto clk |
3581 * and interface clock |
3582 * |
3583 * |
3584 * +--------<------------+-----------------+---<---+
3585 * | | |
3586 * +----v---------+ +--------v-----+ +--------v------+
3587 * | vco_divided | | vco_divided | | vco_divided |
3588 * | _clk_src | | _clk_src | | _clk_src |
3589 * | | | | | |
3590 * |divsel_six | | divsel_two | | divsel_four |
3591 * +-------+------+ +-----+--------+ +--------+------+
3592 * | | |
3593 * v---->----------v-------------<------v
3594 * |
3595 * +----------+-----------------+
3596 * | dp_phy_pll_vco_div_clk |
3597 * +---------+------------------+
3598 * |
3599 * v
3600 * Input to DISPCC block
3601 * for DP pixel clock
3602 *
3603 */
qmp_dp_pixel_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)3604 static int qmp_dp_pixel_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
3605 {
3606 switch (req->rate) {
3607 case 1620000000UL / 2:
3608 case 2700000000UL / 2:
3609 /* 5.4 and 8.1 GHz are same link rate as 2.7GHz, i.e. div 4 and div 6 */
3610 return 0;
3611 default:
3612 return -EINVAL;
3613 }
3614 }
3615
qmp_dp_pixel_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)3616 static unsigned long qmp_dp_pixel_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3617 {
3618 const struct qmp_combo *qmp;
3619 const struct phy_configure_opts_dp *dp_opts;
3620
3621 qmp = container_of(hw, struct qmp_combo, dp_pixel_hw);
3622 dp_opts = &qmp->dp_opts;
3623
3624 switch (dp_opts->link_rate) {
3625 case 1620:
3626 return 1620000000UL / 2;
3627 case 2700:
3628 return 2700000000UL / 2;
3629 case 5400:
3630 return 5400000000UL / 4;
3631 case 8100:
3632 return 8100000000UL / 6;
3633 default:
3634 return 0;
3635 }
3636 }
3637
3638 static const struct clk_ops qmp_dp_pixel_clk_ops = {
3639 .determine_rate = qmp_dp_pixel_clk_determine_rate,
3640 .recalc_rate = qmp_dp_pixel_clk_recalc_rate,
3641 };
3642
qmp_dp_link_clk_determine_rate(struct clk_hw * hw,struct clk_rate_request * req)3643 static int qmp_dp_link_clk_determine_rate(struct clk_hw *hw, struct clk_rate_request *req)
3644 {
3645 switch (req->rate) {
3646 case 162000000:
3647 case 270000000:
3648 case 540000000:
3649 case 810000000:
3650 return 0;
3651 default:
3652 return -EINVAL;
3653 }
3654 }
3655
qmp_dp_link_clk_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)3656 static unsigned long qmp_dp_link_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
3657 {
3658 const struct qmp_combo *qmp;
3659 const struct phy_configure_opts_dp *dp_opts;
3660
3661 qmp = container_of(hw, struct qmp_combo, dp_link_hw);
3662 dp_opts = &qmp->dp_opts;
3663
3664 switch (dp_opts->link_rate) {
3665 case 1620:
3666 case 2700:
3667 case 5400:
3668 case 8100:
3669 return dp_opts->link_rate * 100000;
3670 default:
3671 return 0;
3672 }
3673 }
3674
3675 static const struct clk_ops qmp_dp_link_clk_ops = {
3676 .determine_rate = qmp_dp_link_clk_determine_rate,
3677 .recalc_rate = qmp_dp_link_clk_recalc_rate,
3678 };
3679
qmp_dp_clks_hw_get(struct of_phandle_args * clkspec,void * data)3680 static struct clk_hw *qmp_dp_clks_hw_get(struct of_phandle_args *clkspec, void *data)
3681 {
3682 struct qmp_combo *qmp = data;
3683 unsigned int idx = clkspec->args[0];
3684
3685 if (idx >= 2) {
3686 pr_err("%s: invalid index %u\n", __func__, idx);
3687 return ERR_PTR(-EINVAL);
3688 }
3689
3690 if (idx == 0)
3691 return &qmp->dp_link_hw;
3692
3693 return &qmp->dp_pixel_hw;
3694 }
3695
phy_dp_clks_register(struct qmp_combo * qmp,struct device_node * np)3696 static int phy_dp_clks_register(struct qmp_combo *qmp, struct device_node *np)
3697 {
3698 struct clk_init_data init = { };
3699 char name[64];
3700 int ret;
3701
3702 snprintf(name, sizeof(name), "%s::link_clk", dev_name(qmp->dev));
3703 init.ops = &qmp_dp_link_clk_ops;
3704 init.name = name;
3705 qmp->dp_link_hw.init = &init;
3706 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_link_hw);
3707 if (ret)
3708 return ret;
3709
3710 snprintf(name, sizeof(name), "%s::vco_div_clk", dev_name(qmp->dev));
3711 init.ops = &qmp_dp_pixel_clk_ops;
3712 init.name = name;
3713 qmp->dp_pixel_hw.init = &init;
3714 ret = devm_clk_hw_register(qmp->dev, &qmp->dp_pixel_hw);
3715 if (ret)
3716 return ret;
3717
3718 return 0;
3719 }
3720
qmp_combo_clk_hw_get(struct of_phandle_args * clkspec,void * data)3721 static struct clk_hw *qmp_combo_clk_hw_get(struct of_phandle_args *clkspec, void *data)
3722 {
3723 struct qmp_combo *qmp = data;
3724
3725 switch (clkspec->args[0]) {
3726 case QMP_USB43DP_USB3_PIPE_CLK:
3727 return &qmp->pipe_clk_fixed.hw;
3728 case QMP_USB43DP_DP_LINK_CLK:
3729 return &qmp->dp_link_hw;
3730 case QMP_USB43DP_DP_VCO_DIV_CLK:
3731 return &qmp->dp_pixel_hw;
3732 }
3733
3734 return ERR_PTR(-EINVAL);
3735 }
3736
qmp_combo_register_clocks(struct qmp_combo * qmp,struct device_node * usb_np,struct device_node * dp_np)3737 static int qmp_combo_register_clocks(struct qmp_combo *qmp, struct device_node *usb_np,
3738 struct device_node *dp_np)
3739 {
3740 int ret;
3741
3742 ret = phy_pipe_clk_register(qmp, usb_np);
3743 if (ret)
3744 return ret;
3745
3746 ret = phy_dp_clks_register(qmp, dp_np);
3747 if (ret)
3748 return ret;
3749
3750 /*
3751 * Register a single provider for bindings without child nodes.
3752 */
3753 if (usb_np == qmp->dev->of_node)
3754 return devm_of_clk_add_hw_provider(qmp->dev, qmp_combo_clk_hw_get, qmp);
3755
3756 /*
3757 * Register multiple providers for legacy bindings with child nodes.
3758 */
3759 ret = of_clk_add_hw_provider(usb_np, of_clk_hw_simple_get,
3760 &qmp->pipe_clk_fixed.hw);
3761 if (ret)
3762 return ret;
3763
3764 /*
3765 * Roll a devm action because the clock provider is the child node, but
3766 * the child node is not actually a device.
3767 */
3768 ret = devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, usb_np);
3769 if (ret)
3770 return ret;
3771
3772 ret = of_clk_add_hw_provider(dp_np, qmp_dp_clks_hw_get, qmp);
3773 if (ret)
3774 return ret;
3775
3776 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, dp_np);
3777 }
3778
3779 #if IS_ENABLED(CONFIG_TYPEC)
qmp_combo_typec_switch_set(struct typec_switch_dev * sw,enum typec_orientation orientation)3780 static int qmp_combo_typec_switch_set(struct typec_switch_dev *sw,
3781 enum typec_orientation orientation)
3782 {
3783 struct qmp_combo *qmp = typec_switch_get_drvdata(sw);
3784 const struct qmp_phy_cfg *cfg = qmp->cfg;
3785
3786 if (orientation == qmp->orientation || orientation == TYPEC_ORIENTATION_NONE)
3787 return 0;
3788
3789 mutex_lock(&qmp->phy_mutex);
3790 qmp->orientation = orientation;
3791
3792 if (qmp->init_count) {
3793 if (qmp->usb_init_count)
3794 qmp_combo_usb_power_off(qmp->usb_phy);
3795 qmp_combo_com_exit(qmp, true);
3796
3797 qmp_combo_com_init(qmp, true);
3798 if (qmp->usb_init_count)
3799 qmp_combo_usb_power_on(qmp->usb_phy);
3800 if (qmp->dp_init_count)
3801 cfg->dp_aux_init(qmp);
3802 }
3803 mutex_unlock(&qmp->phy_mutex);
3804
3805 return 0;
3806 }
3807
qmp_combo_typec_mux_set(struct typec_mux_dev * mux,struct typec_mux_state * state)3808 static int qmp_combo_typec_mux_set(struct typec_mux_dev *mux, struct typec_mux_state *state)
3809 {
3810 struct qmp_combo *qmp = typec_mux_get_drvdata(mux);
3811 const struct qmp_phy_cfg *cfg = qmp->cfg;
3812 enum qmpphy_mode new_mode;
3813 unsigned int svid;
3814
3815 guard(mutex)(&qmp->phy_mutex);
3816
3817 if (state->alt)
3818 svid = state->alt->svid;
3819 else
3820 svid = 0;
3821
3822 if (svid == USB_TYPEC_DP_SID) {
3823 switch (state->mode) {
3824 /* DP Only */
3825 case TYPEC_DP_STATE_C:
3826 case TYPEC_DP_STATE_E:
3827 new_mode = QMPPHY_MODE_DP_ONLY;
3828 break;
3829
3830 /* DP + USB */
3831 case TYPEC_DP_STATE_D:
3832 case TYPEC_DP_STATE_F:
3833
3834 /* Safe fallback...*/
3835 default:
3836 new_mode = QMPPHY_MODE_USB3DP;
3837 break;
3838 }
3839 } else {
3840 /* No DP SVID => don't care, assume it's just USB3 */
3841 new_mode = QMPPHY_MODE_USB3_ONLY;
3842 }
3843
3844 if (new_mode == qmp->qmpphy_mode) {
3845 dev_dbg(qmp->dev, "typec_mux_set: same qmpphy mode, bail out\n");
3846 return 0;
3847 }
3848
3849 if (qmp->qmpphy_mode != QMPPHY_MODE_USB3_ONLY && qmp->dp_powered_on) {
3850 dev_dbg(qmp->dev, "typec_mux_set: DP PHY is still in use, delaying switch\n");
3851 return 0;
3852 }
3853
3854 dev_dbg(qmp->dev, "typec_mux_set: switching from qmpphy mode %d to %d\n",
3855 qmp->qmpphy_mode, new_mode);
3856
3857 qmp->qmpphy_mode = new_mode;
3858
3859 if (qmp->init_count) {
3860 if (qmp->usb_init_count)
3861 qmp_combo_usb_power_off(qmp->usb_phy);
3862
3863 if (qmp->dp_init_count)
3864 writel(DP_PHY_PD_CTL_PSR_PWRDN, qmp->dp_dp_phy + QSERDES_DP_PHY_PD_CTL);
3865
3866 qmp_combo_com_exit(qmp, true);
3867
3868 /* Now everything's powered down, power up the right PHYs */
3869 qmp_combo_com_init(qmp, true);
3870
3871 if (new_mode == QMPPHY_MODE_DP_ONLY) {
3872 if (qmp->usb_init_count)
3873 qmp->usb_init_count--;
3874 }
3875
3876 if (new_mode == QMPPHY_MODE_USB3DP || new_mode == QMPPHY_MODE_USB3_ONLY) {
3877 qmp_combo_usb_power_on(qmp->usb_phy);
3878 if (!qmp->usb_init_count)
3879 qmp->usb_init_count++;
3880 }
3881
3882 if (new_mode == QMPPHY_MODE_DP_ONLY || new_mode == QMPPHY_MODE_USB3DP) {
3883 if (qmp->dp_init_count)
3884 cfg->dp_aux_init(qmp);
3885 }
3886 }
3887
3888 return 0;
3889 }
3890
qmp_combo_typec_switch_unregister(void * data)3891 static void qmp_combo_typec_switch_unregister(void *data)
3892 {
3893 struct qmp_combo *qmp = data;
3894
3895 typec_switch_unregister(qmp->sw);
3896 }
3897
qmp_combo_typec_mux_unregister(void * data)3898 static void qmp_combo_typec_mux_unregister(void *data)
3899 {
3900 struct qmp_combo *qmp = data;
3901
3902 typec_mux_unregister(qmp->mux);
3903 }
3904
qmp_combo_typec_register(struct qmp_combo * qmp)3905 static int qmp_combo_typec_register(struct qmp_combo *qmp)
3906 {
3907 struct typec_switch_desc sw_desc = {};
3908 struct typec_mux_desc mux_desc = { };
3909 struct device *dev = qmp->dev;
3910 int ret;
3911
3912 sw_desc.drvdata = qmp;
3913 sw_desc.fwnode = dev->fwnode;
3914 sw_desc.set = qmp_combo_typec_switch_set;
3915 qmp->sw = typec_switch_register(dev, &sw_desc);
3916 if (IS_ERR(qmp->sw)) {
3917 dev_err(dev, "Unable to register typec switch: %pe\n", qmp->sw);
3918 return PTR_ERR(qmp->sw);
3919 }
3920
3921 ret = devm_add_action_or_reset(dev, qmp_combo_typec_switch_unregister, qmp);
3922 if (ret)
3923 return ret;
3924
3925 mux_desc.drvdata = qmp;
3926 mux_desc.fwnode = dev->fwnode;
3927 mux_desc.set = qmp_combo_typec_mux_set;
3928 qmp->mux = typec_mux_register(dev, &mux_desc);
3929 if (IS_ERR(qmp->mux)) {
3930 dev_err(dev, "Unable to register typec mux: %pe\n", qmp->mux);
3931 return PTR_ERR(qmp->mux);
3932 }
3933
3934 return devm_add_action_or_reset(dev, qmp_combo_typec_mux_unregister, qmp);
3935 }
3936 #else
qmp_combo_typec_register(struct qmp_combo * qmp)3937 static int qmp_combo_typec_register(struct qmp_combo *qmp)
3938 {
3939 return 0;
3940 }
3941 #endif
3942
qmp_combo_parse_dt_legacy_dp(struct qmp_combo * qmp,struct device_node * np)3943 static int qmp_combo_parse_dt_legacy_dp(struct qmp_combo *qmp, struct device_node *np)
3944 {
3945 struct device *dev = qmp->dev;
3946
3947 /*
3948 * Get memory resources from the DP child node:
3949 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
3950 * tx2 -> 3; rx2 -> 4
3951 *
3952 * Note that only tx/tx2 and pcs (dp_phy) are used by the DP
3953 * implementation.
3954 */
3955 qmp->dp_tx = devm_of_iomap(dev, np, 0, NULL);
3956 if (IS_ERR(qmp->dp_tx))
3957 return PTR_ERR(qmp->dp_tx);
3958
3959 qmp->dp_dp_phy = devm_of_iomap(dev, np, 2, NULL);
3960 if (IS_ERR(qmp->dp_dp_phy))
3961 return PTR_ERR(qmp->dp_dp_phy);
3962
3963 qmp->dp_tx2 = devm_of_iomap(dev, np, 3, NULL);
3964 if (IS_ERR(qmp->dp_tx2))
3965 return PTR_ERR(qmp->dp_tx2);
3966
3967 return 0;
3968 }
3969
qmp_combo_parse_dt_legacy_usb(struct qmp_combo * qmp,struct device_node * np)3970 static int qmp_combo_parse_dt_legacy_usb(struct qmp_combo *qmp, struct device_node *np)
3971 {
3972 const struct qmp_phy_cfg *cfg = qmp->cfg;
3973 struct device *dev = qmp->dev;
3974
3975 /*
3976 * Get memory resources from the USB child node:
3977 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2;
3978 * tx2 -> 3; rx2 -> 4; pcs_misc (optional) -> 5
3979 */
3980 qmp->tx = devm_of_iomap(dev, np, 0, NULL);
3981 if (IS_ERR(qmp->tx))
3982 return PTR_ERR(qmp->tx);
3983
3984 qmp->rx = devm_of_iomap(dev, np, 1, NULL);
3985 if (IS_ERR(qmp->rx))
3986 return PTR_ERR(qmp->rx);
3987
3988 qmp->pcs = devm_of_iomap(dev, np, 2, NULL);
3989 if (IS_ERR(qmp->pcs))
3990 return PTR_ERR(qmp->pcs);
3991
3992 if (cfg->pcs_usb_offset)
3993 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
3994
3995 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
3996 if (IS_ERR(qmp->tx2))
3997 return PTR_ERR(qmp->tx2);
3998
3999 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
4000 if (IS_ERR(qmp->rx2))
4001 return PTR_ERR(qmp->rx2);
4002
4003 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
4004 if (IS_ERR(qmp->pcs_misc)) {
4005 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
4006 qmp->pcs_misc = NULL;
4007 }
4008
4009 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
4010 if (IS_ERR(qmp->pipe_clk)) {
4011 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
4012 "failed to get pipe clock\n");
4013 }
4014
4015 return 0;
4016 }
4017
qmp_combo_parse_dt_legacy(struct qmp_combo * qmp,struct device_node * usb_np,struct device_node * dp_np)4018 static int qmp_combo_parse_dt_legacy(struct qmp_combo *qmp, struct device_node *usb_np,
4019 struct device_node *dp_np)
4020 {
4021 struct platform_device *pdev = to_platform_device(qmp->dev);
4022 int ret;
4023
4024 qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
4025 if (IS_ERR(qmp->serdes))
4026 return PTR_ERR(qmp->serdes);
4027
4028 qmp->com = devm_platform_ioremap_resource(pdev, 1);
4029 if (IS_ERR(qmp->com))
4030 return PTR_ERR(qmp->com);
4031
4032 qmp->dp_serdes = devm_platform_ioremap_resource(pdev, 2);
4033 if (IS_ERR(qmp->dp_serdes))
4034 return PTR_ERR(qmp->dp_serdes);
4035
4036 ret = qmp_combo_parse_dt_legacy_usb(qmp, usb_np);
4037 if (ret)
4038 return ret;
4039
4040 ret = qmp_combo_parse_dt_legacy_dp(qmp, dp_np);
4041 if (ret)
4042 return ret;
4043
4044 ret = devm_clk_bulk_get_all(qmp->dev, &qmp->clks);
4045 if (ret < 0)
4046 return ret;
4047
4048 qmp->num_clks = ret;
4049
4050 return 0;
4051 }
4052
qmp_combo_parse_dt(struct qmp_combo * qmp)4053 static int qmp_combo_parse_dt(struct qmp_combo *qmp)
4054 {
4055 struct platform_device *pdev = to_platform_device(qmp->dev);
4056 const struct qmp_phy_cfg *cfg = qmp->cfg;
4057 const struct qmp_combo_offsets *offs = cfg->offsets;
4058 struct device *dev = qmp->dev;
4059 void __iomem *base;
4060 int ret;
4061
4062 if (!offs)
4063 return -EINVAL;
4064
4065 base = devm_platform_ioremap_resource(pdev, 0);
4066 if (IS_ERR(base))
4067 return PTR_ERR(base);
4068
4069 qmp->com = base + offs->com;
4070 qmp->tx = base + offs->txa;
4071 qmp->rx = base + offs->rxa;
4072 qmp->tx2 = base + offs->txb;
4073 qmp->rx2 = base + offs->rxb;
4074
4075 qmp->serdes = base + offs->usb3_serdes;
4076 qmp->pcs_misc = base + offs->usb3_pcs_misc;
4077 qmp->pcs = base + offs->usb3_pcs;
4078 qmp->pcs_usb = base + offs->usb3_pcs_usb;
4079
4080 qmp->dp_serdes = base + offs->dp_serdes;
4081 if (offs->dp_txa) {
4082 qmp->dp_tx = base + offs->dp_txa;
4083 qmp->dp_tx2 = base + offs->dp_txb;
4084 } else {
4085 qmp->dp_tx = base + offs->txa;
4086 qmp->dp_tx2 = base + offs->txb;
4087 }
4088 qmp->dp_dp_phy = base + offs->dp_dp_phy;
4089
4090 ret = qmp_combo_clk_init(qmp);
4091 if (ret)
4092 return ret;
4093
4094 qmp->pipe_clk = devm_clk_get(dev, "usb3_pipe");
4095 if (IS_ERR(qmp->pipe_clk)) {
4096 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
4097 "failed to get usb3_pipe clock\n");
4098 }
4099
4100 return 0;
4101 }
4102
qmp_combo_phy_xlate(struct device * dev,const struct of_phandle_args * args)4103 static struct phy *qmp_combo_phy_xlate(struct device *dev, const struct of_phandle_args *args)
4104 {
4105 struct qmp_combo *qmp = dev_get_drvdata(dev);
4106
4107 if (args->args_count == 0)
4108 return ERR_PTR(-EINVAL);
4109
4110 switch (args->args[0]) {
4111 case QMP_USB43DP_USB3_PHY:
4112 return qmp->usb_phy;
4113 case QMP_USB43DP_DP_PHY:
4114 return qmp->dp_phy;
4115 }
4116
4117 return ERR_PTR(-EINVAL);
4118 }
4119
qmp_combo_probe(struct platform_device * pdev)4120 static int qmp_combo_probe(struct platform_device *pdev)
4121 {
4122 struct qmp_combo *qmp;
4123 struct device *dev = &pdev->dev;
4124 struct device_node *dp_np, *usb_np;
4125 struct phy_provider *phy_provider;
4126 int ret;
4127
4128 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
4129 if (!qmp)
4130 return -ENOMEM;
4131
4132 qmp->dev = dev;
4133 dev_set_drvdata(dev, qmp);
4134
4135 qmp->orientation = TYPEC_ORIENTATION_NORMAL;
4136
4137 qmp->cfg = of_device_get_match_data(dev);
4138 if (!qmp->cfg)
4139 return -EINVAL;
4140
4141 mutex_init(&qmp->phy_mutex);
4142
4143 ret = qmp_combo_reset_init(qmp);
4144 if (ret)
4145 return ret;
4146
4147 ret = qmp_combo_vreg_init(qmp);
4148 if (ret)
4149 return ret;
4150
4151 /* Check for legacy binding with child nodes. */
4152 usb_np = of_get_child_by_name(dev->of_node, "usb3-phy");
4153 if (usb_np) {
4154 dp_np = of_get_child_by_name(dev->of_node, "dp-phy");
4155 if (!dp_np) {
4156 of_node_put(usb_np);
4157 return -EINVAL;
4158 }
4159
4160 ret = qmp_combo_parse_dt_legacy(qmp, usb_np, dp_np);
4161 } else {
4162 usb_np = of_node_get(dev->of_node);
4163 dp_np = of_node_get(dev->of_node);
4164
4165 ret = qmp_combo_parse_dt(qmp);
4166 }
4167 if (ret)
4168 goto err_node_put;
4169
4170 ret = qmp_combo_typec_register(qmp);
4171 if (ret)
4172 goto err_node_put;
4173
4174 ret = drm_aux_bridge_register(dev);
4175 if (ret)
4176 goto err_node_put;
4177
4178 pm_runtime_set_active(dev);
4179 ret = devm_pm_runtime_enable(dev);
4180 if (ret)
4181 goto err_node_put;
4182 /*
4183 * Prevent runtime pm from being ON by default. Users can enable
4184 * it using power/control in sysfs.
4185 */
4186 pm_runtime_forbid(dev);
4187
4188 ret = qmp_combo_register_clocks(qmp, usb_np, dp_np);
4189 if (ret)
4190 goto err_node_put;
4191
4192 /*
4193 * The hw default is USB3_ONLY, but USB3+DP mode lets us more easily
4194 * check both sub-blocks' init tables for blunders at probe time.
4195 */
4196 qmp->qmpphy_mode = QMPPHY_MODE_USB3DP;
4197
4198 qmp->usb_phy = devm_phy_create(dev, usb_np, &qmp_combo_usb_phy_ops);
4199 if (IS_ERR(qmp->usb_phy)) {
4200 ret = PTR_ERR(qmp->usb_phy);
4201 dev_err(dev, "failed to create USB PHY: %d\n", ret);
4202 goto err_node_put;
4203 }
4204
4205 phy_set_drvdata(qmp->usb_phy, qmp);
4206
4207 qmp->dp_phy = devm_phy_create(dev, dp_np, &qmp_combo_dp_phy_ops);
4208 if (IS_ERR(qmp->dp_phy)) {
4209 ret = PTR_ERR(qmp->dp_phy);
4210 dev_err(dev, "failed to create DP PHY: %d\n", ret);
4211 goto err_node_put;
4212 }
4213
4214 phy_set_drvdata(qmp->dp_phy, qmp);
4215
4216 if (usb_np == dev->of_node)
4217 phy_provider = devm_of_phy_provider_register(dev, qmp_combo_phy_xlate);
4218 else
4219 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
4220
4221 of_node_put(usb_np);
4222 of_node_put(dp_np);
4223
4224 return PTR_ERR_OR_ZERO(phy_provider);
4225
4226 err_node_put:
4227 of_node_put(usb_np);
4228 of_node_put(dp_np);
4229 return ret;
4230 }
4231
4232 static const struct of_device_id qmp_combo_of_match_table[] = {
4233 {
4234 .compatible = "qcom,sar2130p-qmp-usb3-dp-phy",
4235 .data = &sar2130p_usb3dpphy_cfg,
4236 },
4237 {
4238 .compatible = "qcom,sc7180-qmp-usb3-dp-phy",
4239 .data = &sc7180_usb3dpphy_cfg,
4240 },
4241 {
4242 .compatible = "qcom,sc7280-qmp-usb3-dp-phy",
4243 .data = &sm8250_usb3dpphy_cfg,
4244 },
4245 {
4246 .compatible = "qcom,sc8180x-qmp-usb3-dp-phy",
4247 .data = &sc8180x_usb3dpphy_cfg,
4248 },
4249 {
4250 .compatible = "qcom,sc8280xp-qmp-usb43dp-phy",
4251 .data = &sc8280xp_usb43dpphy_cfg,
4252 },
4253 {
4254 .compatible = "qcom,sdm845-qmp-usb3-dp-phy",
4255 .data = &sdm845_usb3dpphy_cfg,
4256 },
4257 {
4258 .compatible = "qcom,sm6350-qmp-usb3-dp-phy",
4259 .data = &sm6350_usb3dpphy_cfg,
4260 },
4261 {
4262 .compatible = "qcom,sm8150-qmp-usb3-dp-phy",
4263 .data = &sc8180x_usb3dpphy_cfg,
4264 },
4265 {
4266 .compatible = "qcom,sm8250-qmp-usb3-dp-phy",
4267 .data = &sm8250_usb3dpphy_cfg,
4268 },
4269 {
4270 .compatible = "qcom,sm8350-qmp-usb3-dp-phy",
4271 .data = &sm8350_usb3dpphy_cfg,
4272 },
4273 {
4274 .compatible = "qcom,sm8450-qmp-usb3-dp-phy",
4275 .data = &sm8350_usb3dpphy_cfg,
4276 },
4277 {
4278 .compatible = "qcom,sm8550-qmp-usb3-dp-phy",
4279 .data = &sm8550_usb3dpphy_cfg,
4280 },
4281 {
4282 .compatible = "qcom,sm8650-qmp-usb3-dp-phy",
4283 .data = &sm8650_usb3dpphy_cfg,
4284 },
4285 {
4286 .compatible = "qcom,sm8750-qmp-usb3-dp-phy",
4287 .data = &sm8750_usb3dpphy_cfg,
4288 },
4289 {
4290 .compatible = "qcom,x1e80100-qmp-usb3-dp-phy",
4291 .data = &x1e80100_usb3dpphy_cfg,
4292 },
4293 { }
4294 };
4295 MODULE_DEVICE_TABLE(of, qmp_combo_of_match_table);
4296
4297 static struct platform_driver qmp_combo_driver = {
4298 .probe = qmp_combo_probe,
4299 .driver = {
4300 .name = "qcom-qmp-combo-phy",
4301 .pm = &qmp_combo_pm_ops,
4302 .of_match_table = qmp_combo_of_match_table,
4303 },
4304 };
4305
4306 module_platform_driver(qmp_combo_driver);
4307
4308 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
4309 MODULE_DESCRIPTION("Qualcomm QMP USB+DP combo PHY driver");
4310 MODULE_LICENSE("GPL v2");
4311