1 /*
2 * Copyright 2022 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 */
22
23 #include <linux/firmware.h>
24 #include <drm/drm_drv.h>
25
26 #include "amdgpu.h"
27 #include "amdgpu_ucode.h"
28 #include "amdgpu_vpe.h"
29 #include "amdgpu_smu.h"
30 #include "soc15_common.h"
31 #include "vpe_v6_1.h"
32
33 #define AMDGPU_CSA_VPE_SIZE 64
34 /* VPE CSA resides in the 4th page of CSA */
35 #define AMDGPU_CSA_VPE_OFFSET (4096 * 3)
36
37 /* 1 second timeout */
38 #define VPE_IDLE_TIMEOUT msecs_to_jiffies(1000)
39
40 #define VPE_MAX_DPM_LEVEL 4
41 #define FIXED1_8_BITS_PER_FRACTIONAL_PART 8
42 #define GET_PRATIO_INTEGER_PART(x) ((x) >> FIXED1_8_BITS_PER_FRACTIONAL_PART)
43
44 static void vpe_set_ring_funcs(struct amdgpu_device *adev);
45
div16_u16_rem(uint16_t dividend,uint16_t divisor,uint16_t * remainder)46 static inline uint16_t div16_u16_rem(uint16_t dividend, uint16_t divisor, uint16_t *remainder)
47 {
48 *remainder = dividend % divisor;
49 return dividend / divisor;
50 }
51
complete_integer_division_u16(uint16_t dividend,uint16_t divisor,uint16_t * remainder)52 static inline uint16_t complete_integer_division_u16(
53 uint16_t dividend,
54 uint16_t divisor,
55 uint16_t *remainder)
56 {
57 return div16_u16_rem(dividend, divisor, (uint16_t *)remainder);
58 }
59
vpe_u1_8_from_fraction(uint16_t numerator,uint16_t denominator)60 static uint16_t vpe_u1_8_from_fraction(uint16_t numerator, uint16_t denominator)
61 {
62 u16 arg1_value = numerator;
63 u16 arg2_value = denominator;
64
65 uint16_t remainder;
66
67 /* determine integer part */
68 uint16_t res_value = complete_integer_division_u16(
69 arg1_value, arg2_value, &remainder);
70
71 if (res_value > 127 /* CHAR_MAX */)
72 return 0;
73
74 /* determine fractional part */
75 {
76 unsigned int i = FIXED1_8_BITS_PER_FRACTIONAL_PART;
77
78 do {
79 remainder <<= 1;
80
81 res_value <<= 1;
82
83 if (remainder >= arg2_value) {
84 res_value |= 1;
85 remainder -= arg2_value;
86 }
87 } while (--i != 0);
88 }
89
90 /* round up LSB */
91 {
92 uint16_t summand = (remainder << 1) >= arg2_value;
93
94 if ((res_value + summand) > 32767 /* SHRT_MAX */)
95 return 0;
96
97 res_value += summand;
98 }
99
100 return res_value;
101 }
102
vpe_internal_get_pratio(uint16_t from_frequency,uint16_t to_frequency)103 static uint16_t vpe_internal_get_pratio(uint16_t from_frequency, uint16_t to_frequency)
104 {
105 uint16_t pratio = vpe_u1_8_from_fraction(from_frequency, to_frequency);
106
107 if (GET_PRATIO_INTEGER_PART(pratio) > 1)
108 pratio = 0;
109
110 return pratio;
111 }
112
113 /*
114 * VPE has 4 DPM levels from level 0 (lowerest) to 3 (highest),
115 * VPE FW will dynamically decide which level should be used according to current loading.
116 *
117 * Get VPE and SOC clocks from PM, and select the appropriate four clock values,
118 * calculate the ratios of adjusting from one clock to another.
119 * The VPE FW can then request the appropriate frequency from the PMFW.
120 */
amdgpu_vpe_configure_dpm(struct amdgpu_vpe * vpe)121 int amdgpu_vpe_configure_dpm(struct amdgpu_vpe *vpe)
122 {
123 struct amdgpu_device *adev = vpe->ring.adev;
124 uint32_t dpm_ctl;
125
126 if (adev->pm.dpm_enabled) {
127 struct dpm_clocks clock_table = { 0 };
128 struct dpm_clock *VPEClks;
129 struct dpm_clock *SOCClks;
130 uint32_t idx;
131 uint32_t vpeclk_enalbled_num = 0;
132 uint32_t pratio_vmax_vnorm = 0, pratio_vnorm_vmid = 0, pratio_vmid_vmin = 0;
133 uint16_t pratio_vmin_freq = 0, pratio_vmid_freq = 0, pratio_vnorm_freq = 0, pratio_vmax_freq = 0;
134
135 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));
136 dpm_ctl |= 1; /* DPM enablement */
137 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);
138
139 /* Get VPECLK and SOCCLK */
140 if (amdgpu_dpm_get_dpm_clock_table(adev, &clock_table)) {
141 dev_dbg(adev->dev, "%s: get clock failed!\n", __func__);
142 goto disable_dpm;
143 }
144
145 SOCClks = clock_table.SocClocks;
146 VPEClks = clock_table.VPEClocks;
147
148 /* Comfirm enabled vpe clk num
149 * Enabled VPE clocks are ordered from low to high in VPEClks
150 * The highest valid clock index+1 is the number of VPEClks
151 */
152 for (idx = PP_SMU_NUM_VPECLK_DPM_LEVELS; idx && !vpeclk_enalbled_num; idx--)
153 if (VPEClks[idx-1].Freq)
154 vpeclk_enalbled_num = idx;
155
156 /* vpe dpm only cares 4 levels. */
157 for (idx = 0; idx < VPE_MAX_DPM_LEVEL; idx++) {
158 uint32_t soc_dpm_level;
159 uint32_t min_freq;
160
161 if (idx == 0)
162 soc_dpm_level = 0;
163 else
164 soc_dpm_level = (idx * 2) + 1;
165
166 /* clamp the max level */
167 if (soc_dpm_level > vpeclk_enalbled_num - 1)
168 soc_dpm_level = vpeclk_enalbled_num - 1;
169
170 min_freq = (SOCClks[soc_dpm_level].Freq < VPEClks[soc_dpm_level].Freq) ?
171 SOCClks[soc_dpm_level].Freq : VPEClks[soc_dpm_level].Freq;
172
173 switch (idx) {
174 case 0:
175 pratio_vmin_freq = min_freq;
176 break;
177 case 1:
178 pratio_vmid_freq = min_freq;
179 break;
180 case 2:
181 pratio_vnorm_freq = min_freq;
182 break;
183 case 3:
184 pratio_vmax_freq = min_freq;
185 break;
186 default:
187 break;
188 }
189 }
190
191 if (pratio_vmin_freq && pratio_vmid_freq && pratio_vnorm_freq && pratio_vmax_freq) {
192 uint32_t pratio_ctl;
193
194 pratio_vmax_vnorm = (uint32_t)vpe_internal_get_pratio(pratio_vmax_freq, pratio_vnorm_freq);
195 pratio_vnorm_vmid = (uint32_t)vpe_internal_get_pratio(pratio_vnorm_freq, pratio_vmid_freq);
196 pratio_vmid_vmin = (uint32_t)vpe_internal_get_pratio(pratio_vmid_freq, pratio_vmin_freq);
197
198 pratio_ctl = pratio_vmax_vnorm | (pratio_vnorm_vmid << 9) | (pratio_vmid_vmin << 18);
199 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_pratio), pratio_ctl); /* PRatio */
200 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_request_interval), 24000); /* 1ms, unit=1/24MHz */
201 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_decision_threshold), 1200000); /* 50ms */
202 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_busy_clamp_threshold), 1200000);/* 50ms */
203 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_idle_clamp_threshold), 1200000);/* 50ms */
204 dev_dbg(adev->dev, "%s: configure vpe dpm pratio done!\n", __func__);
205 } else {
206 dev_dbg(adev->dev, "%s: invalid pratio parameters!\n", __func__);
207 goto disable_dpm;
208 }
209 }
210 return 0;
211
212 disable_dpm:
213 dpm_ctl = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable));
214 dpm_ctl &= 0xfffffffe; /* Disable DPM */
215 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.dpm_enable), dpm_ctl);
216 dev_dbg(adev->dev, "%s: disable vpe dpm\n", __func__);
217 return -EINVAL;
218 }
219
amdgpu_vpe_psp_update_sram(struct amdgpu_device * adev)220 int amdgpu_vpe_psp_update_sram(struct amdgpu_device *adev)
221 {
222 struct amdgpu_firmware_info ucode = {
223 .ucode_id = AMDGPU_UCODE_ID_VPE,
224 .mc_addr = adev->vpe.cmdbuf_gpu_addr,
225 .ucode_size = 8,
226 };
227
228 return psp_execute_ip_fw_load(&adev->psp, &ucode);
229 }
230
amdgpu_vpe_init_microcode(struct amdgpu_vpe * vpe)231 int amdgpu_vpe_init_microcode(struct amdgpu_vpe *vpe)
232 {
233 struct amdgpu_device *adev = vpe->ring.adev;
234 const struct vpe_firmware_header_v1_0 *vpe_hdr;
235 char fw_prefix[32];
236 int ret;
237
238 amdgpu_ucode_ip_version_decode(adev, VPE_HWIP, fw_prefix, sizeof(fw_prefix));
239 ret = amdgpu_ucode_request(adev, &adev->vpe.fw, AMDGPU_UCODE_REQUIRED,
240 "amdgpu/%s.bin", fw_prefix);
241 if (ret)
242 goto out;
243
244 vpe_hdr = (const struct vpe_firmware_header_v1_0 *)adev->vpe.fw->data;
245 adev->vpe.fw_version = le32_to_cpu(vpe_hdr->header.ucode_version);
246 adev->vpe.feature_version = le32_to_cpu(vpe_hdr->ucode_feature_version);
247
248 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
249 struct amdgpu_firmware_info *info;
250
251 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTX];
252 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTX;
253 info->fw = adev->vpe.fw;
254 adev->firmware.fw_size +=
255 ALIGN(le32_to_cpu(vpe_hdr->ctx_ucode_size_bytes), PAGE_SIZE);
256
257 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_VPE_CTL];
258 info->ucode_id = AMDGPU_UCODE_ID_VPE_CTL;
259 info->fw = adev->vpe.fw;
260 adev->firmware.fw_size +=
261 ALIGN(le32_to_cpu(vpe_hdr->ctl_ucode_size_bytes), PAGE_SIZE);
262 }
263
264 return 0;
265 out:
266 dev_err(adev->dev, "fail to initialize vpe microcode\n");
267 release_firmware(adev->vpe.fw);
268 adev->vpe.fw = NULL;
269 return ret;
270 }
271
amdgpu_vpe_ring_init(struct amdgpu_vpe * vpe)272 int amdgpu_vpe_ring_init(struct amdgpu_vpe *vpe)
273 {
274 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);
275 struct amdgpu_ring *ring = &vpe->ring;
276 int ret;
277
278 ring->ring_obj = NULL;
279 ring->use_doorbell = true;
280 ring->vm_hub = AMDGPU_MMHUB0(0);
281 ring->doorbell_index = (adev->doorbell_index.vpe_ring << 1);
282 snprintf(ring->name, 4, "vpe");
283
284 ret = amdgpu_ring_init(adev, ring, 1024, &vpe->trap_irq, 0,
285 AMDGPU_RING_PRIO_DEFAULT, NULL);
286 if (ret)
287 return ret;
288
289 return 0;
290 }
291
amdgpu_vpe_ring_fini(struct amdgpu_vpe * vpe)292 int amdgpu_vpe_ring_fini(struct amdgpu_vpe *vpe)
293 {
294 amdgpu_ring_fini(&vpe->ring);
295
296 return 0;
297 }
298
vpe_early_init(struct amdgpu_ip_block * ip_block)299 static int vpe_early_init(struct amdgpu_ip_block *ip_block)
300 {
301 struct amdgpu_device *adev = ip_block->adev;
302 struct amdgpu_vpe *vpe = &adev->vpe;
303
304 switch (amdgpu_ip_version(adev, VPE_HWIP, 0)) {
305 case IP_VERSION(6, 1, 0):
306 case IP_VERSION(6, 1, 3):
307 vpe_v6_1_set_funcs(vpe);
308 break;
309 case IP_VERSION(6, 1, 1):
310 vpe_v6_1_set_funcs(vpe);
311 vpe->collaborate_mode = true;
312 break;
313 default:
314 return -EINVAL;
315 }
316
317 vpe_set_ring_funcs(adev);
318 vpe_set_regs(vpe);
319
320 dev_info(adev->dev, "VPE: collaborate mode %s", vpe->collaborate_mode ? "true" : "false");
321
322 return 0;
323 }
324
vpe_idle_work_handler(struct work_struct * work)325 static void vpe_idle_work_handler(struct work_struct *work)
326 {
327 struct amdgpu_device *adev =
328 container_of(work, struct amdgpu_device, vpe.idle_work.work);
329 unsigned int fences = 0;
330
331 fences += amdgpu_fence_count_emitted(&adev->vpe.ring);
332
333 if (fences == 0)
334 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);
335 else
336 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);
337 }
338
vpe_common_init(struct amdgpu_vpe * vpe)339 static int vpe_common_init(struct amdgpu_vpe *vpe)
340 {
341 struct amdgpu_device *adev = container_of(vpe, struct amdgpu_device, vpe);
342 int r;
343
344 r = amdgpu_bo_create_kernel(adev, PAGE_SIZE, PAGE_SIZE,
345 AMDGPU_GEM_DOMAIN_GTT,
346 &adev->vpe.cmdbuf_obj,
347 &adev->vpe.cmdbuf_gpu_addr,
348 (void **)&adev->vpe.cmdbuf_cpu_addr);
349 if (r) {
350 dev_err(adev->dev, "VPE: failed to allocate cmdbuf bo %d\n", r);
351 return r;
352 }
353
354 vpe->context_started = false;
355 INIT_DELAYED_WORK(&adev->vpe.idle_work, vpe_idle_work_handler);
356
357 return 0;
358 }
359
vpe_sw_init(struct amdgpu_ip_block * ip_block)360 static int vpe_sw_init(struct amdgpu_ip_block *ip_block)
361 {
362 struct amdgpu_device *adev = ip_block->adev;
363 struct amdgpu_vpe *vpe = &adev->vpe;
364 int ret;
365
366 ret = vpe_common_init(vpe);
367 if (ret)
368 goto out;
369
370 ret = vpe_irq_init(vpe);
371 if (ret)
372 goto out;
373
374 ret = vpe_ring_init(vpe);
375 if (ret)
376 goto out;
377
378 ret = vpe_init_microcode(vpe);
379 if (ret)
380 goto out;
381
382 /* TODO: Add queue reset mask when FW fully supports it */
383 adev->vpe.supported_reset =
384 amdgpu_get_soft_full_reset_mask(&adev->vpe.ring);
385 ret = amdgpu_vpe_sysfs_reset_mask_init(adev);
386 if (ret)
387 goto out;
388 out:
389 return ret;
390 }
391
vpe_sw_fini(struct amdgpu_ip_block * ip_block)392 static int vpe_sw_fini(struct amdgpu_ip_block *ip_block)
393 {
394 struct amdgpu_device *adev = ip_block->adev;
395 struct amdgpu_vpe *vpe = &adev->vpe;
396
397 release_firmware(vpe->fw);
398 vpe->fw = NULL;
399
400 amdgpu_vpe_sysfs_reset_mask_fini(adev);
401 vpe_ring_fini(vpe);
402
403 amdgpu_bo_free_kernel(&adev->vpe.cmdbuf_obj,
404 &adev->vpe.cmdbuf_gpu_addr,
405 (void **)&adev->vpe.cmdbuf_cpu_addr);
406
407 return 0;
408 }
409
vpe_hw_init(struct amdgpu_ip_block * ip_block)410 static int vpe_hw_init(struct amdgpu_ip_block *ip_block)
411 {
412 struct amdgpu_device *adev = ip_block->adev;
413 struct amdgpu_vpe *vpe = &adev->vpe;
414 int ret;
415
416 /* Power on VPE */
417 ret = amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE,
418 AMD_PG_STATE_UNGATE);
419 if (ret)
420 return ret;
421
422 ret = vpe_load_microcode(vpe);
423 if (ret)
424 return ret;
425
426 ret = vpe_ring_start(vpe);
427 if (ret)
428 return ret;
429
430 return 0;
431 }
432
vpe_hw_fini(struct amdgpu_ip_block * ip_block)433 static int vpe_hw_fini(struct amdgpu_ip_block *ip_block)
434 {
435 struct amdgpu_device *adev = ip_block->adev;
436 struct amdgpu_vpe *vpe = &adev->vpe;
437
438 vpe_ring_stop(vpe);
439
440 /* Power off VPE */
441 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_GATE);
442
443 return 0;
444 }
445
vpe_suspend(struct amdgpu_ip_block * ip_block)446 static int vpe_suspend(struct amdgpu_ip_block *ip_block)
447 {
448 struct amdgpu_device *adev = ip_block->adev;
449
450 cancel_delayed_work_sync(&adev->vpe.idle_work);
451
452 return vpe_hw_fini(ip_block);
453 }
454
vpe_resume(struct amdgpu_ip_block * ip_block)455 static int vpe_resume(struct amdgpu_ip_block *ip_block)
456 {
457 return vpe_hw_init(ip_block);
458 }
459
vpe_ring_insert_nop(struct amdgpu_ring * ring,uint32_t count)460 static void vpe_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
461 {
462 int i;
463
464 for (i = 0; i < count; i++)
465 if (i == 0)
466 amdgpu_ring_write(ring, ring->funcs->nop |
467 VPE_CMD_NOP_HEADER_COUNT(count - 1));
468 else
469 amdgpu_ring_write(ring, ring->funcs->nop);
470 }
471
vpe_get_csa_mc_addr(struct amdgpu_ring * ring,uint32_t vmid)472 static uint64_t vpe_get_csa_mc_addr(struct amdgpu_ring *ring, uint32_t vmid)
473 {
474 struct amdgpu_device *adev = ring->adev;
475 uint32_t index = 0;
476 uint64_t csa_mc_addr;
477
478 if (amdgpu_sriov_vf(adev) || vmid == 0 || !adev->gfx.mcbp)
479 return 0;
480
481 csa_mc_addr = amdgpu_csa_vaddr(adev) + AMDGPU_CSA_VPE_OFFSET +
482 index * AMDGPU_CSA_VPE_SIZE;
483
484 return csa_mc_addr;
485 }
486
vpe_ring_emit_pred_exec(struct amdgpu_ring * ring,uint32_t device_select,uint32_t exec_count)487 static void vpe_ring_emit_pred_exec(struct amdgpu_ring *ring,
488 uint32_t device_select,
489 uint32_t exec_count)
490 {
491 if (!ring->adev->vpe.collaborate_mode)
492 return;
493
494 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_PRED_EXE, 0) |
495 (device_select << 16));
496 amdgpu_ring_write(ring, exec_count & 0x1fff);
497 }
498
vpe_ring_emit_ib(struct amdgpu_ring * ring,struct amdgpu_job * job,struct amdgpu_ib * ib,uint32_t flags)499 static void vpe_ring_emit_ib(struct amdgpu_ring *ring,
500 struct amdgpu_job *job,
501 struct amdgpu_ib *ib,
502 uint32_t flags)
503 {
504 uint32_t vmid = AMDGPU_JOB_GET_VMID(job);
505 uint64_t csa_mc_addr = vpe_get_csa_mc_addr(ring, vmid);
506
507 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_INDIRECT, 0) |
508 VPE_CMD_INDIRECT_HEADER_VMID(vmid & 0xf));
509
510 /* base must be 32 byte aligned */
511 amdgpu_ring_write(ring, ib->gpu_addr & 0xffffffe0);
512 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
513 amdgpu_ring_write(ring, ib->length_dw);
514 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr));
515 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr));
516 }
517
vpe_ring_emit_fence(struct amdgpu_ring * ring,uint64_t addr,uint64_t seq,unsigned int flags)518 static void vpe_ring_emit_fence(struct amdgpu_ring *ring, uint64_t addr,
519 uint64_t seq, unsigned int flags)
520 {
521 int i = 0;
522
523 do {
524 /* write the fence */
525 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0));
526 /* zero in first two bits */
527 WARN_ON_ONCE(addr & 0x3);
528 amdgpu_ring_write(ring, lower_32_bits(addr));
529 amdgpu_ring_write(ring, upper_32_bits(addr));
530 amdgpu_ring_write(ring, i == 0 ? lower_32_bits(seq) : upper_32_bits(seq));
531 addr += 4;
532 } while ((flags & AMDGPU_FENCE_FLAG_64BIT) && (i++ < 1));
533
534 if (flags & AMDGPU_FENCE_FLAG_INT) {
535 /* generate an interrupt */
536 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_TRAP, 0));
537 amdgpu_ring_write(ring, 0);
538 }
539
540 }
541
vpe_ring_emit_pipeline_sync(struct amdgpu_ring * ring)542 static void vpe_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
543 {
544 uint32_t seq = ring->fence_drv.sync_seq;
545 uint64_t addr = ring->fence_drv.gpu_addr;
546
547 vpe_ring_emit_pred_exec(ring, 0, 6);
548
549 /* wait for idle */
550 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM,
551 VPE_POLL_REGMEM_SUBOP_REGMEM) |
552 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
553 VPE_CMD_POLL_REGMEM_HEADER_MEM(1));
554 amdgpu_ring_write(ring, addr & 0xfffffffc);
555 amdgpu_ring_write(ring, upper_32_bits(addr));
556 amdgpu_ring_write(ring, seq); /* reference */
557 amdgpu_ring_write(ring, 0xffffffff); /* mask */
558 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
559 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(4));
560 }
561
vpe_ring_emit_wreg(struct amdgpu_ring * ring,uint32_t reg,uint32_t val)562 static void vpe_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg, uint32_t val)
563 {
564 vpe_ring_emit_pred_exec(ring, 0, 3);
565
566 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_REG_WRITE, 0));
567 amdgpu_ring_write(ring, reg << 2);
568 amdgpu_ring_write(ring, val);
569 }
570
vpe_ring_emit_reg_wait(struct amdgpu_ring * ring,uint32_t reg,uint32_t val,uint32_t mask)571 static void vpe_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
572 uint32_t val, uint32_t mask)
573 {
574 vpe_ring_emit_pred_exec(ring, 0, 6);
575
576 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_POLL_REGMEM,
577 VPE_POLL_REGMEM_SUBOP_REGMEM) |
578 VPE_CMD_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
579 VPE_CMD_POLL_REGMEM_HEADER_MEM(0));
580 amdgpu_ring_write(ring, reg << 2);
581 amdgpu_ring_write(ring, 0);
582 amdgpu_ring_write(ring, val); /* reference */
583 amdgpu_ring_write(ring, mask); /* mask */
584 amdgpu_ring_write(ring, VPE_CMD_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
585 VPE_CMD_POLL_REGMEM_DW5_INTERVAL(10));
586 }
587
vpe_ring_emit_vm_flush(struct amdgpu_ring * ring,unsigned int vmid,uint64_t pd_addr)588 static void vpe_ring_emit_vm_flush(struct amdgpu_ring *ring, unsigned int vmid,
589 uint64_t pd_addr)
590 {
591 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
592 }
593
vpe_ring_init_cond_exec(struct amdgpu_ring * ring,uint64_t addr)594 static unsigned int vpe_ring_init_cond_exec(struct amdgpu_ring *ring,
595 uint64_t addr)
596 {
597 unsigned int ret;
598
599 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_COND_EXE, 0));
600 amdgpu_ring_write(ring, lower_32_bits(addr));
601 amdgpu_ring_write(ring, upper_32_bits(addr));
602 amdgpu_ring_write(ring, 1);
603 ret = ring->wptr & ring->buf_mask;
604 amdgpu_ring_write(ring, 0);
605
606 return ret;
607 }
608
vpe_ring_preempt_ib(struct amdgpu_ring * ring)609 static int vpe_ring_preempt_ib(struct amdgpu_ring *ring)
610 {
611 struct amdgpu_device *adev = ring->adev;
612 struct amdgpu_vpe *vpe = &adev->vpe;
613 uint32_t preempt_reg = vpe->regs.queue0_preempt;
614 int i, r = 0;
615
616 /* assert preemption condition */
617 amdgpu_ring_set_preempt_cond_exec(ring, false);
618
619 /* emit the trailing fence */
620 ring->trail_seq += 1;
621 amdgpu_ring_alloc(ring, 10);
622 vpe_ring_emit_fence(ring, ring->trail_fence_gpu_addr, ring->trail_seq, 0);
623 amdgpu_ring_commit(ring);
624
625 /* assert IB preemption */
626 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 1);
627
628 /* poll the trailing fence */
629 for (i = 0; i < adev->usec_timeout; i++) {
630 if (ring->trail_seq ==
631 le32_to_cpu(*(ring->trail_fence_cpu_addr)))
632 break;
633 udelay(1);
634 }
635
636 if (i >= adev->usec_timeout) {
637 r = -EINVAL;
638 dev_err(adev->dev, "ring %d failed to be preempted\n", ring->idx);
639 }
640
641 /* deassert IB preemption */
642 WREG32(vpe_get_reg_offset(vpe, ring->me, preempt_reg), 0);
643
644 /* deassert the preemption condition */
645 amdgpu_ring_set_preempt_cond_exec(ring, true);
646
647 return r;
648 }
649
vpe_set_clockgating_state(struct amdgpu_ip_block * ip_block,enum amd_clockgating_state state)650 static int vpe_set_clockgating_state(struct amdgpu_ip_block *ip_block,
651 enum amd_clockgating_state state)
652 {
653 return 0;
654 }
655
vpe_set_powergating_state(struct amdgpu_ip_block * ip_block,enum amd_powergating_state state)656 static int vpe_set_powergating_state(struct amdgpu_ip_block *ip_block,
657 enum amd_powergating_state state)
658 {
659 struct amdgpu_device *adev = ip_block->adev;
660 struct amdgpu_vpe *vpe = &adev->vpe;
661
662 if (!adev->pm.dpm_enabled)
663 dev_err(adev->dev, "Without PM, cannot support powergating\n");
664
665 dev_dbg(adev->dev, "%s: %s!\n", __func__, (state == AMD_PG_STATE_GATE) ? "GATE":"UNGATE");
666
667 if (state == AMD_PG_STATE_GATE) {
668 amdgpu_dpm_enable_vpe(adev, false);
669 vpe->context_started = false;
670 } else {
671 amdgpu_dpm_enable_vpe(adev, true);
672 }
673
674 return 0;
675 }
676
vpe_ring_get_rptr(struct amdgpu_ring * ring)677 static uint64_t vpe_ring_get_rptr(struct amdgpu_ring *ring)
678 {
679 struct amdgpu_device *adev = ring->adev;
680 struct amdgpu_vpe *vpe = &adev->vpe;
681 uint64_t rptr;
682
683 if (ring->use_doorbell) {
684 rptr = atomic64_read((atomic64_t *)ring->rptr_cpu_addr);
685 dev_dbg(adev->dev, "rptr/doorbell before shift == 0x%016llx\n", rptr);
686 } else {
687 rptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_hi));
688 rptr = rptr << 32;
689 rptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_rptr_lo));
690 dev_dbg(adev->dev, "rptr before shift [%i] == 0x%016llx\n", ring->me, rptr);
691 }
692
693 return (rptr >> 2);
694 }
695
vpe_ring_get_wptr(struct amdgpu_ring * ring)696 static uint64_t vpe_ring_get_wptr(struct amdgpu_ring *ring)
697 {
698 struct amdgpu_device *adev = ring->adev;
699 struct amdgpu_vpe *vpe = &adev->vpe;
700 uint64_t wptr;
701
702 if (ring->use_doorbell) {
703 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
704 dev_dbg(adev->dev, "wptr/doorbell before shift == 0x%016llx\n", wptr);
705 } else {
706 wptr = RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_hi));
707 wptr = wptr << 32;
708 wptr |= RREG32(vpe_get_reg_offset(vpe, ring->me, vpe->regs.queue0_rb_wptr_lo));
709 dev_dbg(adev->dev, "wptr before shift [%i] == 0x%016llx\n", ring->me, wptr);
710 }
711
712 return (wptr >> 2);
713 }
714
vpe_ring_set_wptr(struct amdgpu_ring * ring)715 static void vpe_ring_set_wptr(struct amdgpu_ring *ring)
716 {
717 struct amdgpu_device *adev = ring->adev;
718 struct amdgpu_vpe *vpe = &adev->vpe;
719
720 if (ring->use_doorbell) {
721 dev_dbg(adev->dev, "Using doorbell, \
722 wptr_offs == 0x%08x, \
723 lower_32_bits(ring->wptr) << 2 == 0x%08x, \
724 upper_32_bits(ring->wptr) << 2 == 0x%08x\n",
725 ring->wptr_offs,
726 lower_32_bits(ring->wptr << 2),
727 upper_32_bits(ring->wptr << 2));
728 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, ring->wptr << 2);
729 WDOORBELL64(ring->doorbell_index, ring->wptr << 2);
730 if (vpe->collaborate_mode)
731 WDOORBELL64(ring->doorbell_index + 4, ring->wptr << 2);
732 } else {
733 int i;
734
735 for (i = 0; i < vpe->num_instances; i++) {
736 dev_dbg(adev->dev, "Not using doorbell, \
737 regVPEC_QUEUE0_RB_WPTR == 0x%08x, \
738 regVPEC_QUEUE0_RB_WPTR_HI == 0x%08x\n",
739 lower_32_bits(ring->wptr << 2),
740 upper_32_bits(ring->wptr << 2));
741 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_lo),
742 lower_32_bits(ring->wptr << 2));
743 WREG32(vpe_get_reg_offset(vpe, i, vpe->regs.queue0_rb_wptr_hi),
744 upper_32_bits(ring->wptr << 2));
745 }
746 }
747 }
748
vpe_ring_test_ring(struct amdgpu_ring * ring)749 static int vpe_ring_test_ring(struct amdgpu_ring *ring)
750 {
751 struct amdgpu_device *adev = ring->adev;
752 const uint32_t test_pattern = 0xdeadbeef;
753 uint32_t index, i;
754 uint64_t wb_addr;
755 int ret;
756
757 ret = amdgpu_device_wb_get(adev, &index);
758 if (ret) {
759 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret);
760 return ret;
761 }
762
763 adev->wb.wb[index] = 0;
764 wb_addr = adev->wb.gpu_addr + (index * 4);
765
766 ret = amdgpu_ring_alloc(ring, 4);
767 if (ret) {
768 dev_err(adev->dev, "amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, ret);
769 goto out;
770 }
771
772 amdgpu_ring_write(ring, VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0));
773 amdgpu_ring_write(ring, lower_32_bits(wb_addr));
774 amdgpu_ring_write(ring, upper_32_bits(wb_addr));
775 amdgpu_ring_write(ring, test_pattern);
776 amdgpu_ring_commit(ring);
777
778 for (i = 0; i < adev->usec_timeout; i++) {
779 if (le32_to_cpu(adev->wb.wb[index]) == test_pattern)
780 goto out;
781 udelay(1);
782 }
783
784 ret = -ETIMEDOUT;
785 out:
786 amdgpu_device_wb_free(adev, index);
787
788 return ret;
789 }
790
vpe_ring_test_ib(struct amdgpu_ring * ring,long timeout)791 static int vpe_ring_test_ib(struct amdgpu_ring *ring, long timeout)
792 {
793 struct amdgpu_device *adev = ring->adev;
794 const uint32_t test_pattern = 0xdeadbeef;
795 struct amdgpu_ib ib = {};
796 struct dma_fence *f = NULL;
797 uint32_t index;
798 uint64_t wb_addr;
799 int ret;
800
801 ret = amdgpu_device_wb_get(adev, &index);
802 if (ret) {
803 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", ret);
804 return ret;
805 }
806
807 adev->wb.wb[index] = 0;
808 wb_addr = adev->wb.gpu_addr + (index * 4);
809
810 ret = amdgpu_ib_get(adev, NULL, 256, AMDGPU_IB_POOL_DIRECT, &ib);
811 if (ret)
812 goto err0;
813
814 ib.ptr[0] = VPE_CMD_HEADER(VPE_CMD_OPCODE_FENCE, 0);
815 ib.ptr[1] = lower_32_bits(wb_addr);
816 ib.ptr[2] = upper_32_bits(wb_addr);
817 ib.ptr[3] = test_pattern;
818 ib.ptr[4] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
819 ib.ptr[5] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
820 ib.ptr[6] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
821 ib.ptr[7] = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0);
822 ib.length_dw = 8;
823
824 ret = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
825 if (ret)
826 goto err1;
827
828 ret = dma_fence_wait_timeout(f, false, timeout);
829 if (ret <= 0) {
830 ret = ret ? : -ETIMEDOUT;
831 goto err1;
832 }
833
834 ret = (le32_to_cpu(adev->wb.wb[index]) == test_pattern) ? 0 : -EINVAL;
835
836 err1:
837 amdgpu_ib_free(&ib, NULL);
838 dma_fence_put(f);
839 err0:
840 amdgpu_device_wb_free(adev, index);
841
842 return ret;
843 }
844
vpe_ring_begin_use(struct amdgpu_ring * ring)845 static void vpe_ring_begin_use(struct amdgpu_ring *ring)
846 {
847 struct amdgpu_device *adev = ring->adev;
848 struct amdgpu_vpe *vpe = &adev->vpe;
849
850 cancel_delayed_work_sync(&adev->vpe.idle_work);
851
852 /* Power on VPE and notify VPE of new context */
853 if (!vpe->context_started) {
854 uint32_t context_notify;
855
856 /* Power on VPE */
857 amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VPE, AMD_PG_STATE_UNGATE);
858
859 /* Indicates that a job from a new context has been submitted. */
860 context_notify = RREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator));
861 if ((context_notify & 0x1) == 0)
862 context_notify |= 0x1;
863 else
864 context_notify &= ~(0x1);
865 WREG32(vpe_get_reg_offset(vpe, 0, vpe->regs.context_indicator), context_notify);
866 vpe->context_started = true;
867 }
868 }
869
vpe_ring_end_use(struct amdgpu_ring * ring)870 static void vpe_ring_end_use(struct amdgpu_ring *ring)
871 {
872 struct amdgpu_device *adev = ring->adev;
873
874 schedule_delayed_work(&adev->vpe.idle_work, VPE_IDLE_TIMEOUT);
875 }
876
amdgpu_get_vpe_reset_mask(struct device * dev,struct device_attribute * attr,char * buf)877 static ssize_t amdgpu_get_vpe_reset_mask(struct device *dev,
878 struct device_attribute *attr,
879 char *buf)
880 {
881 struct drm_device *ddev = dev_get_drvdata(dev);
882 struct amdgpu_device *adev = drm_to_adev(ddev);
883
884 if (!adev)
885 return -ENODEV;
886
887 return amdgpu_show_reset_mask(buf, adev->vpe.supported_reset);
888 }
889
890 static DEVICE_ATTR(vpe_reset_mask, 0444,
891 amdgpu_get_vpe_reset_mask, NULL);
892
amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device * adev)893 int amdgpu_vpe_sysfs_reset_mask_init(struct amdgpu_device *adev)
894 {
895 int r = 0;
896
897 if (adev->vpe.num_instances) {
898 r = device_create_file(adev->dev, &dev_attr_vpe_reset_mask);
899 if (r)
900 return r;
901 }
902
903 return r;
904 }
905
amdgpu_vpe_sysfs_reset_mask_fini(struct amdgpu_device * adev)906 void amdgpu_vpe_sysfs_reset_mask_fini(struct amdgpu_device *adev)
907 {
908 if (adev->dev->kobj.sd) {
909 if (adev->vpe.num_instances)
910 device_remove_file(adev->dev, &dev_attr_vpe_reset_mask);
911 }
912 }
913
914 static const struct amdgpu_ring_funcs vpe_ring_funcs = {
915 .type = AMDGPU_RING_TYPE_VPE,
916 .align_mask = 0xf,
917 .nop = VPE_CMD_HEADER(VPE_CMD_OPCODE_NOP, 0),
918 .support_64bit_ptrs = true,
919 .get_rptr = vpe_ring_get_rptr,
920 .get_wptr = vpe_ring_get_wptr,
921 .set_wptr = vpe_ring_set_wptr,
922 .emit_frame_size =
923 5 + /* vpe_ring_init_cond_exec */
924 6 + /* vpe_ring_emit_pipeline_sync */
925 10 + 10 + 10 + /* vpe_ring_emit_fence */
926 /* vpe_ring_emit_vm_flush */
927 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
928 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 6,
929 .emit_ib_size = 7 + 6,
930 .emit_ib = vpe_ring_emit_ib,
931 .emit_pipeline_sync = vpe_ring_emit_pipeline_sync,
932 .emit_fence = vpe_ring_emit_fence,
933 .emit_vm_flush = vpe_ring_emit_vm_flush,
934 .emit_wreg = vpe_ring_emit_wreg,
935 .emit_reg_wait = vpe_ring_emit_reg_wait,
936 .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
937 .insert_nop = vpe_ring_insert_nop,
938 .pad_ib = amdgpu_ring_generic_pad_ib,
939 .test_ring = vpe_ring_test_ring,
940 .test_ib = vpe_ring_test_ib,
941 .init_cond_exec = vpe_ring_init_cond_exec,
942 .preempt_ib = vpe_ring_preempt_ib,
943 .begin_use = vpe_ring_begin_use,
944 .end_use = vpe_ring_end_use,
945 };
946
vpe_set_ring_funcs(struct amdgpu_device * adev)947 static void vpe_set_ring_funcs(struct amdgpu_device *adev)
948 {
949 adev->vpe.ring.funcs = &vpe_ring_funcs;
950 }
951
952 const struct amd_ip_funcs vpe_ip_funcs = {
953 .name = "vpe_v6_1",
954 .early_init = vpe_early_init,
955 .sw_init = vpe_sw_init,
956 .sw_fini = vpe_sw_fini,
957 .hw_init = vpe_hw_init,
958 .hw_fini = vpe_hw_fini,
959 .suspend = vpe_suspend,
960 .resume = vpe_resume,
961 .set_clockgating_state = vpe_set_clockgating_state,
962 .set_powergating_state = vpe_set_powergating_state,
963 };
964
965 const struct amdgpu_ip_block_version vpe_v6_1_ip_block = {
966 .type = AMD_IP_BLOCK_TYPE_VPE,
967 .major = 6,
968 .minor = 1,
969 .rev = 0,
970 .funcs = &vpe_ip_funcs,
971 };
972