1 /*
2 * Copyright 2021 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 */
23
24 #define SWSMU_CODE_LAYER_L2
25
26 #include <linux/firmware.h>
27 #include "amdgpu.h"
28 #include "amdgpu_smu.h"
29 #include "atomfirmware.h"
30 #include "amdgpu_atomfirmware.h"
31 #include "amdgpu_atombios.h"
32 #include "smu_v13_0_6_pmfw.h"
33 #include "smu13_driver_if_v13_0_6.h"
34 #include "smu_v13_0_6_ppsmc.h"
35 #include "soc15_common.h"
36 #include "atom.h"
37 #include "power_state.h"
38 #include "smu_v13_0.h"
39 #include "smu_v13_0_6_ppt.h"
40 #include "nbio/nbio_7_4_offset.h"
41 #include "nbio/nbio_7_4_sh_mask.h"
42 #include "thm/thm_11_0_2_offset.h"
43 #include "thm/thm_11_0_2_sh_mask.h"
44 #include "amdgpu_xgmi.h"
45 #include <linux/pci.h>
46 #include "amdgpu_ras.h"
47 #include "amdgpu_mca.h"
48 #include "amdgpu_aca.h"
49 #include "smu_cmn.h"
50 #include "mp/mp_13_0_6_offset.h"
51 #include "mp/mp_13_0_6_sh_mask.h"
52 #include "umc_v12_0.h"
53
54 #undef MP1_Public
55 #undef smnMP1_FIRMWARE_FLAGS
56
57 /* TODO: Check final register offsets */
58 #define MP1_Public 0x03b00000
59 #define smnMP1_FIRMWARE_FLAGS 0x3010028
60 /*
61 * DO NOT use these for err/warn/info/debug messages.
62 * Use dev_err, dev_warn, dev_info and dev_dbg instead.
63 * They are more MGPU friendly.
64 */
65 #undef pr_err
66 #undef pr_warn
67 #undef pr_info
68 #undef pr_debug
69
70 MODULE_FIRMWARE("amdgpu/smu_13_0_6.bin");
71 MODULE_FIRMWARE("amdgpu/smu_13_0_14.bin");
72
73 #define to_amdgpu_device(x) (container_of(x, struct amdgpu_device, pm.smu_i2c))
74
75 #define SMU_13_0_6_FEA_MAP(smu_feature, smu_13_0_6_feature) \
76 [smu_feature] = { 1, (smu_13_0_6_feature) }
77
78 #define FEATURE_MASK(feature) (1ULL << feature)
79 static const struct smu_feature_bits smu_v13_0_6_dpm_features = {
80 .bits = {
81 SMU_FEATURE_BIT_INIT(FEATURE_DATA_CALCULATION),
82 SMU_FEATURE_BIT_INIT(FEATURE_DPM_GFXCLK),
83 SMU_FEATURE_BIT_INIT(FEATURE_DPM_UCLK),
84 SMU_FEATURE_BIT_INIT(FEATURE_DPM_SOCCLK),
85 SMU_FEATURE_BIT_INIT(FEATURE_DPM_FCLK),
86 SMU_FEATURE_BIT_INIT(FEATURE_DPM_LCLK),
87 SMU_FEATURE_BIT_INIT(FEATURE_DPM_XGMI),
88 SMU_FEATURE_BIT_INIT(FEATURE_DPM_VCN)
89 }
90 };
91
92 #define smnPCIE_ESM_CTRL 0x93D0
93 #define smnPCIE_LC_LINK_WIDTH_CNTL 0x1a340288
94 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK 0x00000070L
95 #define PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT 0x4
96 #define MAX_LINK_WIDTH 6
97
98 #define smnPCIE_LC_SPEED_CNTL 0x1a340290
99 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK 0xE0
100 #define PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT 0x5
101 #define LINK_SPEED_MAX 4
102 #define MCA_BANK_IPID(_ip, _hwid, _type) \
103 [AMDGPU_MCA_IP_##_ip] = { .hwid = _hwid, .mcatype = _type, }
104
105 struct mca_bank_ipid {
106 enum amdgpu_mca_ip ip;
107 uint16_t hwid;
108 uint16_t mcatype;
109 };
110
111 struct mca_ras_info {
112 enum amdgpu_ras_block blkid;
113 enum amdgpu_mca_ip ip;
114 int *err_code_array;
115 int err_code_count;
116 int (*get_err_count)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
117 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count);
118 bool (*bank_is_valid)(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
119 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry);
120 };
121
122 #define P2S_TABLE_ID_A 0x50325341
123 #define P2S_TABLE_ID_X 0x50325358
124 #define P2S_TABLE_ID_3 0x50325303
125
126 // clang-format off
127 static const struct cmn2asic_msg_mapping smu_v13_0_6_message_map[SMU_MSG_MAX_COUNT] = {
128 MSG_MAP(TestMessage, PPSMC_MSG_TestMessage, 0),
129 MSG_MAP(GetSmuVersion, PPSMC_MSG_GetSmuVersion, 1),
130 MSG_MAP(GetDriverIfVersion, PPSMC_MSG_GetDriverIfVersion, 1),
131 MSG_MAP(EnableAllSmuFeatures, PPSMC_MSG_EnableAllSmuFeatures, 0),
132 MSG_MAP(DisableAllSmuFeatures, PPSMC_MSG_DisableAllSmuFeatures, 0),
133 MSG_MAP(RequestI2cTransaction, PPSMC_MSG_RequestI2cTransaction, 0),
134 MSG_MAP(GetMetricsTable, PPSMC_MSG_GetMetricsTable, 1),
135 MSG_MAP(GetMetricsVersion, PPSMC_MSG_GetMetricsVersion, 1),
136 MSG_MAP(GetEnabledSmuFeaturesHigh, PPSMC_MSG_GetEnabledSmuFeaturesHigh, 1),
137 MSG_MAP(GetEnabledSmuFeaturesLow, PPSMC_MSG_GetEnabledSmuFeaturesLow, 1),
138 MSG_MAP(SetDriverDramAddrHigh, PPSMC_MSG_SetDriverDramAddrHigh, 1),
139 MSG_MAP(SetDriverDramAddrLow, PPSMC_MSG_SetDriverDramAddrLow, 1),
140 MSG_MAP(SetToolsDramAddrHigh, PPSMC_MSG_SetToolsDramAddrHigh, 0),
141 MSG_MAP(SetToolsDramAddrLow, PPSMC_MSG_SetToolsDramAddrLow, 0),
142 MSG_MAP(SetSoftMinByFreq, PPSMC_MSG_SetSoftMinByFreq, 0),
143 MSG_MAP(SetSoftMaxByFreq, PPSMC_MSG_SetSoftMaxByFreq, 1),
144 MSG_MAP(GetMinDpmFreq, PPSMC_MSG_GetMinDpmFreq, 1),
145 MSG_MAP(GetMaxDpmFreq, PPSMC_MSG_GetMaxDpmFreq, 1),
146 MSG_MAP(GetDpmFreqByIndex, PPSMC_MSG_GetDpmFreqByIndex, 1),
147 MSG_MAP(SetPptLimit, PPSMC_MSG_SetPptLimit, 1),
148 MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 1),
149 MSG_MAP(GfxDeviceDriverReset, PPSMC_MSG_GfxDriverReset, SMU_MSG_RAS_PRI | SMU_MSG_NO_PRECHECK),
150 MSG_MAP(DramLogSetDramAddrHigh, PPSMC_MSG_DramLogSetDramAddrHigh, 0),
151 MSG_MAP(DramLogSetDramAddrLow, PPSMC_MSG_DramLogSetDramAddrLow, 0),
152 MSG_MAP(DramLogSetDramSize, PPSMC_MSG_DramLogSetDramSize, 0),
153 MSG_MAP(GetDebugData, PPSMC_MSG_GetDebugData, 0),
154 MSG_MAP(SetNumBadHbmPagesRetired, PPSMC_MSG_SetNumBadHbmPagesRetired, 0),
155 MSG_MAP(DFCstateControl, PPSMC_MSG_DFCstateControl, 0),
156 MSG_MAP(GetGmiPwrDnHyst, PPSMC_MSG_GetGmiPwrDnHyst, 0),
157 MSG_MAP(SetGmiPwrDnHyst, PPSMC_MSG_SetGmiPwrDnHyst, 0),
158 MSG_MAP(GmiPwrDnControl, PPSMC_MSG_GmiPwrDnControl, 0),
159 MSG_MAP(EnterGfxoff, PPSMC_MSG_EnterGfxoff, 0),
160 MSG_MAP(ExitGfxoff, PPSMC_MSG_ExitGfxoff, 0),
161 MSG_MAP(EnableDeterminism, PPSMC_MSG_EnableDeterminism, 0),
162 MSG_MAP(DisableDeterminism, PPSMC_MSG_DisableDeterminism, 0),
163 MSG_MAP(GfxDriverResetRecovery, PPSMC_MSG_GfxDriverResetRecovery, 0),
164 MSG_MAP(GetMinGfxclkFrequency, PPSMC_MSG_GetMinGfxDpmFreq, 1),
165 MSG_MAP(GetMaxGfxclkFrequency, PPSMC_MSG_GetMaxGfxDpmFreq, 1),
166 MSG_MAP(SetSoftMinGfxclk, PPSMC_MSG_SetSoftMinGfxClk, 1),
167 MSG_MAP(SetSoftMaxGfxClk, PPSMC_MSG_SetSoftMaxGfxClk, 1),
168 MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareForDriverUnload, 0),
169 MSG_MAP(GetCTFLimit, PPSMC_MSG_GetCTFLimit, 0),
170 MSG_MAP(GetThermalLimit, PPSMC_MSG_ReadThrottlerLimit, 0),
171 MSG_MAP(ClearMcaOnRead, PPSMC_MSG_ClearMcaOnRead, 0),
172 MSG_MAP(QueryValidMcaCount, PPSMC_MSG_QueryValidMcaCount, SMU_MSG_RAS_PRI),
173 MSG_MAP(QueryValidMcaCeCount, PPSMC_MSG_QueryValidMcaCeCount, SMU_MSG_RAS_PRI),
174 MSG_MAP(McaBankDumpDW, PPSMC_MSG_McaBankDumpDW, SMU_MSG_RAS_PRI),
175 MSG_MAP(McaBankCeDumpDW, PPSMC_MSG_McaBankCeDumpDW, SMU_MSG_RAS_PRI),
176 MSG_MAP(SelectPLPDMode, PPSMC_MSG_SelectPLPDMode, 0),
177 MSG_MAP(RmaDueToBadPageThreshold, PPSMC_MSG_RmaDueToBadPageThreshold, 0),
178 MSG_MAP(SetThrottlingPolicy, PPSMC_MSG_SetThrottlingPolicy, 0),
179 MSG_MAP(ResetSDMA, PPSMC_MSG_ResetSDMA, 0),
180 MSG_MAP(ResetVCN, PPSMC_MSG_ResetVCN, 0),
181 MSG_MAP(GetStaticMetricsTable, PPSMC_MSG_GetStaticMetricsTable, 1),
182 };
183
184 // clang-format on
185 static const struct cmn2asic_mapping smu_v13_0_6_clk_map[SMU_CLK_COUNT] = {
186 CLK_MAP(SOCCLK, PPCLK_SOCCLK),
187 CLK_MAP(FCLK, PPCLK_FCLK),
188 CLK_MAP(UCLK, PPCLK_UCLK),
189 CLK_MAP(MCLK, PPCLK_UCLK),
190 CLK_MAP(DCLK, PPCLK_DCLK),
191 CLK_MAP(VCLK, PPCLK_VCLK),
192 CLK_MAP(LCLK, PPCLK_LCLK),
193 };
194
195 static const struct cmn2asic_mapping smu_v13_0_6_feature_mask_map[SMU_FEATURE_COUNT] = {
196 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DATA_CALCULATIONS_BIT, FEATURE_DATA_CALCULATION),
197 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_GFXCLK_BIT, FEATURE_DPM_GFXCLK),
198 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_UCLK_BIT, FEATURE_DPM_UCLK),
199 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_SOCCLK_BIT, FEATURE_DPM_SOCCLK),
200 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_FCLK_BIT, FEATURE_DPM_FCLK),
201 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_LCLK_BIT, FEATURE_DPM_LCLK),
202 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_VCLK_BIT, FEATURE_DPM_VCN),
203 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_DCLK_BIT, FEATURE_DPM_VCN),
204 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DPM_XGMI_BIT, FEATURE_DPM_XGMI),
205 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_GFXCLK_BIT, FEATURE_DS_GFXCLK),
206 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_SOCCLK_BIT, FEATURE_DS_SOCCLK),
207 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_LCLK_BIT, FEATURE_DS_LCLK),
208 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_FCLK_BIT, FEATURE_DS_FCLK),
209 SMU_13_0_6_FEA_MAP(SMU_FEATURE_VCN_DPM_BIT, FEATURE_DPM_VCN),
210 SMU_13_0_6_FEA_MAP(SMU_FEATURE_PPT_BIT, FEATURE_PPT),
211 SMU_13_0_6_FEA_MAP(SMU_FEATURE_TDC_BIT, FEATURE_TDC),
212 SMU_13_0_6_FEA_MAP(SMU_FEATURE_APCC_DFLL_BIT, FEATURE_APCC_DFLL),
213 SMU_13_0_6_FEA_MAP(SMU_FEATURE_MP1_CG_BIT, FEATURE_SMU_CG),
214 SMU_13_0_6_FEA_MAP(SMU_FEATURE_GFXOFF_BIT, FEATURE_GFXOFF),
215 SMU_13_0_6_FEA_MAP(SMU_FEATURE_FW_CTF_BIT, FEATURE_FW_CTF),
216 SMU_13_0_6_FEA_MAP(SMU_FEATURE_THERMAL_BIT, FEATURE_THERMAL),
217 SMU_13_0_6_FEA_MAP(SMU_FEATURE_XGMI_PER_LINK_PWR_DWN_BIT, FEATURE_XGMI_PER_LINK_PWR_DOWN),
218 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DF_CSTATE_BIT, FEATURE_DF_CSTATE),
219 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_VCN_BIT, FEATURE_DS_VCN),
220 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MP1CLK_BIT, FEATURE_DS_MP1CLK),
221 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MPIOCLK_BIT, FEATURE_DS_MPIOCLK),
222 SMU_13_0_6_FEA_MAP(SMU_FEATURE_DS_MP0CLK_BIT, FEATURE_DS_MP0CLK),
223 };
224
225 #define TABLE_PMSTATUSLOG 0
226 #define TABLE_SMU_METRICS 1
227 #define TABLE_I2C_COMMANDS 2
228 #define TABLE_COUNT 3
229
230 static const struct cmn2asic_mapping smu_v13_0_6_table_map[SMU_TABLE_COUNT] = {
231 TAB_MAP(PMSTATUSLOG),
232 TAB_MAP(SMU_METRICS),
233 TAB_MAP(I2C_COMMANDS),
234 };
235
236 static const uint8_t smu_v13_0_6_throttler_map[] = {
237 [THROTTLER_PPT_BIT] = (SMU_THROTTLER_PPT0_BIT),
238 [THROTTLER_THERMAL_SOCKET_BIT] = (SMU_THROTTLER_TEMP_GPU_BIT),
239 [THROTTLER_THERMAL_HBM_BIT] = (SMU_THROTTLER_TEMP_MEM_BIT),
240 [THROTTLER_THERMAL_VR_BIT] = (SMU_THROTTLER_TEMP_VR_GFX_BIT),
241 [THROTTLER_PROCHOT_BIT] = (SMU_THROTTLER_PROCHOT_GFX_BIT),
242 };
243
244 #define GET_GPU_METRIC_FIELD(field, version) ((version == METRICS_VERSION_V0) ?\
245 (metrics_v0->field) : (metrics_v2->field))
246 #define GET_METRIC_FIELD(field, version) ((version == METRICS_VERSION_V1) ?\
247 (metrics_v1->field) : GET_GPU_METRIC_FIELD(field, version))
248 #define METRICS_TABLE_SIZE (max3(sizeof(MetricsTableV0_t),\
249 sizeof(MetricsTableV1_t),\
250 sizeof(MetricsTableV2_t)))
251
252 struct smu_v13_0_6_dpm_map {
253 enum smu_clk_type clk_type;
254 uint32_t feature_num;
255 struct smu_dpm_table *dpm_table;
256 uint32_t *freq_table;
257 };
258
smu_v13_0_6_get_metrics_version(struct smu_context * smu)259 static inline int smu_v13_0_6_get_metrics_version(struct smu_context *smu)
260 {
261 if ((smu->adev->flags & AMD_IS_APU) &&
262 smu->smc_fw_version <= 0x4556900)
263 return METRICS_VERSION_V1;
264 else if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
265 IP_VERSION(13, 0, 12))
266 return METRICS_VERSION_V2;
267
268 return METRICS_VERSION_V0;
269 }
270
smu_v13_0_6_cap_set(struct smu_context * smu,enum smu_v13_0_6_caps cap)271 static inline void smu_v13_0_6_cap_set(struct smu_context *smu,
272 enum smu_v13_0_6_caps cap)
273 {
274 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
275
276 dpm_context->caps |= BIT_ULL(cap);
277 }
278
smu_v13_0_6_cap_clear(struct smu_context * smu,enum smu_v13_0_6_caps cap)279 static inline void smu_v13_0_6_cap_clear(struct smu_context *smu,
280 enum smu_v13_0_6_caps cap)
281 {
282 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
283
284 dpm_context->caps &= ~BIT_ULL(cap);
285 }
286
smu_v13_0_6_cap_supported(struct smu_context * smu,enum smu_v13_0_6_caps cap)287 bool smu_v13_0_6_cap_supported(struct smu_context *smu,
288 enum smu_v13_0_6_caps cap)
289 {
290 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
291
292 return !!(dpm_context->caps & BIT_ULL(cap));
293 }
294
smu_v13_0_14_init_caps(struct smu_context * smu)295 static void smu_v13_0_14_init_caps(struct smu_context *smu)
296 {
297 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
298 SMU_CAP(SET_UCLK_MAX),
299 SMU_CAP(DPM_POLICY),
300 SMU_CAP(PCIE_METRICS),
301 SMU_CAP(CTF_LIMIT),
302 SMU_CAP(MCA_DEBUG_MODE),
303 SMU_CAP(RMA_MSG),
304 SMU_CAP(ACA_SYND) };
305 uint32_t fw_ver = smu->smc_fw_version;
306
307 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
308 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
309
310 if (fw_ver >= 0x05550E00)
311 smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
312 if (fw_ver >= 0x05550B00)
313 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
314 if (fw_ver >= 0x5551200)
315 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
316 if (fw_ver >= 0x5551800)
317 smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET));
318 if (fw_ver >= 0x5551600) {
319 smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS));
320 smu_v13_0_6_cap_set(smu, SMU_CAP(BOARD_VOLTAGE));
321 smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
322 }
323 }
324
smu_v13_0_12_init_caps(struct smu_context * smu)325 static void smu_v13_0_12_init_caps(struct smu_context *smu)
326 {
327 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
328 SMU_CAP(PCIE_METRICS),
329 SMU_CAP(CTF_LIMIT),
330 SMU_CAP(MCA_DEBUG_MODE),
331 SMU_CAP(RMA_MSG),
332 SMU_CAP(ACA_SYND),
333 SMU_CAP(OTHER_END_METRICS),
334 SMU_CAP(PER_INST_METRICS) };
335 uint32_t fw_ver = smu->smc_fw_version;
336
337 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
338 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
339
340 if (fw_ver < 0x00561900)
341 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM));
342
343 if (fw_ver >= 0x00561700)
344 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
345
346 if (fw_ver >= 0x00561E00)
347 smu_v13_0_6_cap_set(smu, SMU_CAP(STATIC_METRICS));
348
349 if (fw_ver >= 0x00562500)
350 smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
351
352 if (fw_ver >= 0x04560100) {
353 smu_v13_0_6_cap_set(smu, SMU_CAP(BOARD_VOLTAGE));
354 smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
355 }
356
357 if (fw_ver > 0x04560900)
358 smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET));
359
360 if (fw_ver >= 0x04560D00) {
361 smu_v13_0_6_cap_set(smu, SMU_CAP(FAST_PPT));
362 if (smu->adev->gmc.xgmi.physical_node_id == 0)
363 smu_v13_0_6_cap_set(smu, SMU_CAP(SYSTEM_POWER_METRICS));
364 }
365
366 if (fw_ver >= 0x04560700) {
367 if (fw_ver >= 0x04560900) {
368 smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_METRICS));
369 if (smu->adev->gmc.xgmi.physical_node_id == 0)
370 smu_v13_0_6_cap_set(smu, SMU_CAP(NPM_METRICS));
371 } else if (!amdgpu_sriov_vf(smu->adev))
372 smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_METRICS));
373 } else {
374 smu_v13_0_12_tables_fini(smu);
375 }
376
377 if (fw_ver >= 0x04561000)
378 smu_v13_0_6_cap_set(smu, SMU_CAP(TEMP_AID_XCD_HBM));
379 }
380
smu_v13_0_6_init_caps(struct smu_context * smu)381 static void smu_v13_0_6_init_caps(struct smu_context *smu)
382 {
383 enum smu_v13_0_6_caps default_cap_list[] = { SMU_CAP(DPM),
384 SMU_CAP(SET_UCLK_MAX),
385 SMU_CAP(DPM_POLICY),
386 SMU_CAP(PCIE_METRICS),
387 SMU_CAP(CTF_LIMIT),
388 SMU_CAP(MCA_DEBUG_MODE),
389 SMU_CAP(RMA_MSG),
390 SMU_CAP(ACA_SYND) };
391 struct amdgpu_device *adev = smu->adev;
392 uint32_t fw_ver = smu->smc_fw_version;
393 uint32_t pgm = (fw_ver >> 24) & 0xFF;
394
395 for (int i = 0; i < ARRAY_SIZE(default_cap_list); i++)
396 smu_v13_0_6_cap_set(smu, default_cap_list[i]);
397
398 if (fw_ver < 0x552F00)
399 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM));
400 if (fw_ver < 0x554500)
401 smu_v13_0_6_cap_clear(smu, SMU_CAP(CTF_LIMIT));
402
403 if (adev->flags & AMD_IS_APU) {
404 smu_v13_0_6_cap_clear(smu, SMU_CAP(PCIE_METRICS));
405 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM_POLICY));
406 smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
407 smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
408
409 if (fw_ver >= 0x04556A00)
410 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
411 } else {
412 if (fw_ver >= 0x557600)
413 smu_v13_0_6_cap_set(smu, SMU_CAP(OTHER_END_METRICS));
414 if (fw_ver < 0x00556000)
415 smu_v13_0_6_cap_clear(smu, SMU_CAP(DPM_POLICY));
416 if (amdgpu_sriov_vf(adev) && (fw_ver < 0x556600))
417 smu_v13_0_6_cap_clear(smu, SMU_CAP(SET_UCLK_MAX));
418 if (fw_ver < 0x556300)
419 smu_v13_0_6_cap_clear(smu, SMU_CAP(PCIE_METRICS));
420 if (fw_ver < 0x554800)
421 smu_v13_0_6_cap_clear(smu, SMU_CAP(MCA_DEBUG_MODE));
422 if (fw_ver >= 0x556F00)
423 smu_v13_0_6_cap_set(smu, SMU_CAP(PER_INST_METRICS));
424 if (fw_ver < 0x00555a00)
425 smu_v13_0_6_cap_clear(smu, SMU_CAP(RMA_MSG));
426 if (fw_ver < 0x00555600)
427 smu_v13_0_6_cap_clear(smu, SMU_CAP(ACA_SYND));
428 if ((pgm == 7 && fw_ver >= 0x7550E00) ||
429 (pgm == 0 && fw_ver >= 0x00557E00))
430 smu_v13_0_6_cap_set(smu, SMU_CAP(HST_LIMIT_METRICS));
431
432 if (amdgpu_sriov_vf(adev)) {
433 if (fw_ver >= 0x00558200)
434 amdgpu_virt_attr_set(&adev->virt.virt_caps,
435 AMDGPU_VIRT_CAP_POWER_LIMIT,
436 AMDGPU_CAP_ATTR_RW);
437 if ((pgm == 0 && fw_ver >= 0x00558000) ||
438 (pgm == 7 && fw_ver >= 0x7551000)) {
439 smu_v13_0_6_cap_set(smu,
440 SMU_CAP(STATIC_METRICS));
441 smu_v13_0_6_cap_set(smu,
442 SMU_CAP(BOARD_VOLTAGE));
443 smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
444 }
445 } else {
446 if ((pgm == 0 && fw_ver >= 0x00557F01) ||
447 (pgm == 7 && fw_ver >= 0x7551000)) {
448 smu_v13_0_6_cap_set(smu,
449 SMU_CAP(STATIC_METRICS));
450 smu_v13_0_6_cap_set(smu,
451 SMU_CAP(BOARD_VOLTAGE));
452 }
453 if ((pgm == 0 && fw_ver >= 0x00558000) ||
454 (pgm == 7 && fw_ver >= 0x7551000))
455 smu_v13_0_6_cap_set(smu, SMU_CAP(PLDM_VERSION));
456 }
457 }
458 if (((pgm == 7) && (fw_ver >= 0x7550700)) ||
459 ((pgm == 0) && (fw_ver >= 0x00557900)) ||
460 ((pgm == 4) && (fw_ver >= 0x4557000)))
461 smu_v13_0_6_cap_set(smu, SMU_CAP(SDMA_RESET));
462
463 if ((pgm == 0 && fw_ver >= 0x00558200) ||
464 (pgm == 4 && fw_ver >= 0x04557100) ||
465 (pgm == 7 && fw_ver >= 0x07551400))
466 smu_v13_0_6_cap_set(smu, SMU_CAP(VCN_RESET));
467 }
468
smu_v13_0_x_init_caps(struct smu_context * smu)469 static void smu_v13_0_x_init_caps(struct smu_context *smu)
470 {
471 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
472 case IP_VERSION(13, 0, 12):
473 return smu_v13_0_12_init_caps(smu);
474 case IP_VERSION(13, 0, 14):
475 return smu_v13_0_14_init_caps(smu);
476 default:
477 return smu_v13_0_6_init_caps(smu);
478 }
479 }
480
smu_v13_0_6_check_fw_version(struct smu_context * smu)481 static int smu_v13_0_6_check_fw_version(struct smu_context *smu)
482 {
483 int r;
484
485 r = smu_cmn_check_fw_version(smu);
486 /* Initialize caps flags once fw version is fetched */
487 if (!r)
488 smu_v13_0_x_init_caps(smu);
489
490 return r;
491 }
492
smu_v13_0_6_init_microcode(struct smu_context * smu)493 static int smu_v13_0_6_init_microcode(struct smu_context *smu)
494 {
495 const struct smc_firmware_header_v2_1 *v2_1;
496 const struct common_firmware_header *hdr;
497 struct amdgpu_firmware_info *ucode = NULL;
498 struct smc_soft_pptable_entry *entries;
499 struct amdgpu_device *adev = smu->adev;
500 uint32_t p2s_table_id = P2S_TABLE_ID_A;
501 int ret = 0, i, p2stable_count;
502 int var = (adev->pdev->device & 0xF);
503 char ucode_prefix[15];
504
505 /* No need to load P2S tables in IOV mode or for smu v13.0.12 */
506 if (amdgpu_sriov_vf(adev) ||
507 (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)))
508 return 0;
509
510 if (!(adev->flags & AMD_IS_APU)) {
511 p2s_table_id = P2S_TABLE_ID_X;
512 if (var == 0x5)
513 p2s_table_id = P2S_TABLE_ID_3;
514 }
515
516 amdgpu_ucode_ip_version_decode(adev, MP1_HWIP, ucode_prefix,
517 sizeof(ucode_prefix));
518 ret = amdgpu_ucode_request(adev, &adev->pm.fw, AMDGPU_UCODE_REQUIRED,
519 "amdgpu/%s.bin", ucode_prefix);
520 if (ret)
521 goto out;
522
523 hdr = (const struct common_firmware_header *)adev->pm.fw->data;
524 amdgpu_ucode_print_smc_hdr(hdr);
525
526 /* SMU v13.0.6 binary file doesn't carry pptables, instead the entries
527 * are used to carry p2s tables.
528 */
529 v2_1 = (const struct smc_firmware_header_v2_1 *)adev->pm.fw->data;
530 entries = (struct smc_soft_pptable_entry
531 *)((uint8_t *)v2_1 +
532 le32_to_cpu(v2_1->pptable_entry_offset));
533 p2stable_count = le32_to_cpu(v2_1->pptable_count);
534 for (i = 0; i < p2stable_count; i++) {
535 if (le32_to_cpu(entries[i].id) == p2s_table_id) {
536 smu->pptable_firmware.data =
537 ((uint8_t *)v2_1 +
538 le32_to_cpu(entries[i].ppt_offset_bytes));
539 smu->pptable_firmware.size =
540 le32_to_cpu(entries[i].ppt_size_bytes);
541 break;
542 }
543 }
544
545 if (smu->pptable_firmware.data && smu->pptable_firmware.size) {
546 ucode = &adev->firmware.ucode[AMDGPU_UCODE_ID_P2S_TABLE];
547 ucode->ucode_id = AMDGPU_UCODE_ID_P2S_TABLE;
548 ucode->fw = &smu->pptable_firmware;
549 adev->firmware.fw_size += ALIGN(ucode->fw->size, PAGE_SIZE);
550 }
551
552 return 0;
553 out:
554 amdgpu_ucode_release(&adev->pm.fw);
555
556 return ret;
557 }
558
smu_v13_0_6_tables_init(struct smu_context * smu)559 static int smu_v13_0_6_tables_init(struct smu_context *smu)
560 {
561 struct smu_table_context *smu_table = &smu->smu_table;
562 struct smu_table *tables = smu_table->tables;
563 struct smu_v13_0_6_gpu_metrics *gpu_metrics;
564 void *driver_pptable __free(kfree) = NULL;
565 void *metrics_table __free(kfree) = NULL;
566 struct amdgpu_device *adev = smu->adev;
567 int gpu_metrcs_size = METRICS_TABLE_SIZE;
568 int ret;
569
570 if (!(adev->flags & AMD_IS_APU))
571 SMU_TABLE_INIT(tables, SMU_TABLE_PMSTATUSLOG, SMU13_TOOL_SIZE,
572 PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM);
573
574 SMU_TABLE_INIT(tables, SMU_TABLE_SMU_METRICS,
575 max(gpu_metrcs_size,
576 smu_v13_0_12_get_max_metrics_size()),
577 PAGE_SIZE,
578 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
579
580 SMU_TABLE_INIT(tables, SMU_TABLE_I2C_COMMANDS, sizeof(SwI2cRequest_t),
581 PAGE_SIZE,
582 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
583
584 SMU_TABLE_INIT(tables, SMU_TABLE_PMFW_SYSTEM_METRICS,
585 smu_v13_0_12_get_system_metrics_size(), PAGE_SIZE,
586 AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
587
588 metrics_table = kzalloc(METRICS_TABLE_SIZE, GFP_KERNEL);
589 if (!metrics_table)
590 return -ENOMEM;
591 smu_table->metrics_time = 0;
592
593 driver_pptable = kzalloc_obj(struct PPTable_t);
594 if (!driver_pptable)
595 return -ENOMEM;
596
597 ret = smu_driver_table_init(smu, SMU_DRIVER_TABLE_GPU_METRICS,
598 sizeof(struct smu_v13_0_6_gpu_metrics),
599 SMU_GPU_METRICS_CACHE_INTERVAL);
600 if (ret)
601 return ret;
602
603 gpu_metrics = (struct smu_v13_0_6_gpu_metrics *)smu_driver_table_ptr(
604 smu, SMU_DRIVER_TABLE_GPU_METRICS);
605
606 smu_v13_0_6_gpu_metrics_init(gpu_metrics, 1, 9);
607 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
608 IP_VERSION(13, 0, 12)) {
609 ret = smu_v13_0_12_tables_init(smu);
610 if (ret) {
611 smu_driver_table_fini(smu,
612 SMU_DRIVER_TABLE_GPU_METRICS);
613 return ret;
614 }
615 }
616
617 smu_table->metrics_table = no_free_ptr(metrics_table);
618 smu_table->driver_pptable = no_free_ptr(driver_pptable);
619
620 return 0;
621 }
622
smu_v13_0_6_select_policy_soc_pstate(struct smu_context * smu,int policy)623 static int smu_v13_0_6_select_policy_soc_pstate(struct smu_context *smu,
624 int policy)
625 {
626 struct amdgpu_device *adev = smu->adev;
627 int ret, param;
628
629 switch (policy) {
630 case SOC_PSTATE_DEFAULT:
631 param = 0;
632 break;
633 case SOC_PSTATE_0:
634 param = 1;
635 break;
636 case SOC_PSTATE_1:
637 param = 2;
638 break;
639 case SOC_PSTATE_2:
640 param = 3;
641 break;
642 default:
643 return -EINVAL;
644 }
645
646 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetThrottlingPolicy,
647 param, NULL);
648
649 if (ret)
650 dev_err(adev->dev, "select soc pstate policy %d failed",
651 policy);
652
653 return ret;
654 }
655
smu_v13_0_6_select_plpd_policy(struct smu_context * smu,int level)656 static int smu_v13_0_6_select_plpd_policy(struct smu_context *smu, int level)
657 {
658 struct amdgpu_device *adev = smu->adev;
659 int ret, param;
660
661 switch (level) {
662 case XGMI_PLPD_DEFAULT:
663 param = PPSMC_PLPD_MODE_DEFAULT;
664 break;
665 case XGMI_PLPD_OPTIMIZED:
666 param = PPSMC_PLPD_MODE_OPTIMIZED;
667 break;
668 case XGMI_PLPD_DISALLOW:
669 param = 0;
670 break;
671 default:
672 return -EINVAL;
673 }
674
675 if (level == XGMI_PLPD_DISALLOW)
676 ret = smu_cmn_send_smc_msg_with_param(
677 smu, SMU_MSG_GmiPwrDnControl, param, NULL);
678 else
679 /* change xgmi per-link power down policy */
680 ret = smu_cmn_send_smc_msg_with_param(
681 smu, SMU_MSG_SelectPLPDMode, param, NULL);
682
683 if (ret)
684 dev_err(adev->dev,
685 "select xgmi per-link power down policy %d failed\n",
686 level);
687
688 return ret;
689 }
690
smu_v13_0_6_allocate_dpm_context(struct smu_context * smu)691 static int smu_v13_0_6_allocate_dpm_context(struct smu_context *smu)
692 {
693 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
694 struct smu_dpm_policy *policy;
695
696 smu_dpm->dpm_context =
697 kzalloc_obj(struct smu_13_0_dpm_context);
698 if (!smu_dpm->dpm_context)
699 return -ENOMEM;
700 smu_dpm->dpm_context_size = sizeof(struct smu_13_0_dpm_context);
701
702 smu_dpm->dpm_policies =
703 kzalloc_obj(struct smu_dpm_policy_ctxt);
704 if (!smu_dpm->dpm_policies) {
705 kfree(smu_dpm->dpm_context);
706 return -ENOMEM;
707 }
708
709 if (!(smu->adev->flags & AMD_IS_APU)) {
710 policy = &(smu_dpm->dpm_policies->policies[0]);
711
712 policy->policy_type = PP_PM_POLICY_SOC_PSTATE;
713 policy->level_mask = BIT(SOC_PSTATE_DEFAULT) |
714 BIT(SOC_PSTATE_0) | BIT(SOC_PSTATE_1) |
715 BIT(SOC_PSTATE_2);
716 policy->current_level = SOC_PSTATE_DEFAULT;
717 policy->set_policy = smu_v13_0_6_select_policy_soc_pstate;
718 smu_cmn_generic_soc_policy_desc(policy);
719 smu_dpm->dpm_policies->policy_mask |=
720 BIT(PP_PM_POLICY_SOC_PSTATE);
721 }
722 policy = &(smu_dpm->dpm_policies->policies[1]);
723
724 policy->policy_type = PP_PM_POLICY_XGMI_PLPD;
725 policy->level_mask = BIT(XGMI_PLPD_DISALLOW) | BIT(XGMI_PLPD_DEFAULT) |
726 BIT(XGMI_PLPD_OPTIMIZED);
727 policy->current_level = XGMI_PLPD_DEFAULT;
728 policy->set_policy = smu_v13_0_6_select_plpd_policy;
729 smu_cmn_generic_plpd_policy_desc(policy);
730 smu_dpm->dpm_policies->policy_mask |= BIT(PP_PM_POLICY_XGMI_PLPD);
731
732 return 0;
733 }
734
smu_v13_0_6_init_smc_tables(struct smu_context * smu)735 static int smu_v13_0_6_init_smc_tables(struct smu_context *smu)
736 {
737 int ret = 0;
738
739 ret = smu_v13_0_6_tables_init(smu);
740 if (ret)
741 return ret;
742
743 ret = smu_v13_0_6_allocate_dpm_context(smu);
744
745 return ret;
746 }
747
smu_v13_0_6_fini_smc_tables(struct smu_context * smu)748 static int smu_v13_0_6_fini_smc_tables(struct smu_context *smu)
749 {
750 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12))
751 smu_v13_0_12_tables_fini(smu);
752 return smu_v13_0_fini_smc_tables(smu);
753 }
754
smu_v13_0_6_init_allowed_features(struct smu_context * smu)755 static int smu_v13_0_6_init_allowed_features(struct smu_context *smu)
756 {
757 smu_feature_list_set_all(smu, SMU_FEATURE_LIST_ALLOWED);
758
759 return 0;
760 }
761
smu_v13_0_6_get_metrics_table(struct smu_context * smu,void * metrics_table,bool bypass_cache)762 int smu_v13_0_6_get_metrics_table(struct smu_context *smu, void *metrics_table,
763 bool bypass_cache)
764 {
765 struct smu_table_context *smu_table = &smu->smu_table;
766 uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;
767 struct smu_table *table = &smu_table->driver_table;
768 int ret;
769
770 if (bypass_cache || !smu_table->metrics_time ||
771 time_after(jiffies,
772 smu_table->metrics_time + msecs_to_jiffies(1))) {
773 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsTable, NULL);
774 if (ret) {
775 dev_info(smu->adev->dev,
776 "Failed to export SMU metrics table!\n");
777 return ret;
778 }
779
780 amdgpu_hdp_invalidate(smu->adev, NULL);
781 ret = smu_cmn_vram_cpy(smu, smu_table->metrics_table,
782 table->cpu_addr, table_size);
783 if (ret)
784 return ret;
785
786 smu_table->metrics_time = jiffies;
787 }
788
789 if (metrics_table)
790 memcpy(metrics_table, smu_table->metrics_table, table_size);
791
792 return 0;
793 }
794
smu_v13_0_6_get_pm_metrics(struct smu_context * smu,void * metrics,size_t max_size)795 static ssize_t smu_v13_0_6_get_pm_metrics(struct smu_context *smu,
796 void *metrics, size_t max_size)
797 {
798 struct smu_table_context *smu_tbl_ctxt = &smu->smu_table;
799 uint32_t table_version = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].version;
800 uint32_t table_size = smu_tbl_ctxt->tables[SMU_TABLE_SMU_METRICS].size;
801 struct amdgpu_pm_metrics *pm_metrics = metrics;
802 uint32_t pmfw_version;
803 int ret;
804
805 if (!pm_metrics || !max_size)
806 return -EINVAL;
807
808 if (max_size < (table_size + sizeof(pm_metrics->common_header)))
809 return -EOVERFLOW;
810
811 /* Don't use cached metrics data */
812 ret = smu_v13_0_6_get_metrics_table(smu, pm_metrics->data, true);
813 if (ret)
814 return ret;
815
816 smu_cmn_get_smc_version(smu, NULL, &pmfw_version);
817
818 memset(&pm_metrics->common_header, 0,
819 sizeof(pm_metrics->common_header));
820 pm_metrics->common_header.mp1_ip_discovery_version =
821 amdgpu_ip_version(smu->adev, MP1_HWIP, 0);
822 pm_metrics->common_header.pmfw_version = pmfw_version;
823 pm_metrics->common_header.pmmetrics_version = table_version;
824 pm_metrics->common_header.structure_size =
825 sizeof(pm_metrics->common_header) + table_size;
826
827 return pm_metrics->common_header.structure_size;
828 }
829
smu_v13_0_6_fill_static_metrics_table(struct smu_context * smu,StaticMetricsTable_t * static_metrics)830 static void smu_v13_0_6_fill_static_metrics_table(struct smu_context *smu,
831 StaticMetricsTable_t *static_metrics)
832 {
833 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
834
835 if (!static_metrics->InputTelemetryVoltageInmV) {
836 dev_warn(smu->adev->dev, "Invalid board voltage %d\n",
837 static_metrics->InputTelemetryVoltageInmV);
838 }
839
840 dpm_context->board_volt = static_metrics->InputTelemetryVoltageInmV;
841
842 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PLDM_VERSION)) &&
843 static_metrics->pldmVersion[0] != 0xFFFFFFFF)
844 smu->adev->firmware.pldm_version =
845 static_metrics->pldmVersion[0];
846 }
847
smu_v13_0_6_get_static_metrics_table(struct smu_context * smu)848 int smu_v13_0_6_get_static_metrics_table(struct smu_context *smu)
849 {
850 struct smu_table_context *smu_table = &smu->smu_table;
851 uint32_t table_size = smu_table->tables[SMU_TABLE_SMU_METRICS].size;
852 struct smu_table *table = &smu_table->driver_table;
853 int ret;
854
855 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetStaticMetricsTable, NULL);
856 if (ret) {
857 dev_info(smu->adev->dev,
858 "Failed to export static metrics table!\n");
859 return ret;
860 }
861
862 amdgpu_hdp_invalidate(smu->adev, NULL);
863
864 return smu_cmn_vram_cpy(smu, smu_table->metrics_table,
865 table->cpu_addr, table_size);
866 }
867
smu_v13_0_6_update_caps(struct smu_context * smu)868 static void smu_v13_0_6_update_caps(struct smu_context *smu)
869 {
870 struct smu_table_context *smu_table = &smu->smu_table;
871 struct PPTable_t *pptable =
872 (struct PPTable_t *)smu_table->driver_pptable;
873
874 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)) &&
875 !pptable->PPT1Max)
876 smu_v13_0_6_cap_clear(smu, SMU_CAP(FAST_PPT));
877 }
878
smu_v13_0_6_setup_driver_pptable(struct smu_context * smu)879 static int smu_v13_0_6_setup_driver_pptable(struct smu_context *smu)
880 {
881 struct smu_table_context *smu_table = &smu->smu_table;
882 StaticMetricsTable_t *static_metrics = (StaticMetricsTable_t *)smu_table->metrics_table;
883 MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
884 MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
885 MetricsTableV2_t *metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
886 struct PPTable_t *pptable =
887 (struct PPTable_t *)smu_table->driver_pptable;
888 int version = smu_v13_0_6_get_metrics_version(smu);
889 int ret, i, retry = 100, n;
890 uint32_t table_version;
891 uint16_t max_speed;
892 uint8_t max_width;
893
894 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) &&
895 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {
896 ret = smu_v13_0_12_setup_driver_pptable(smu);
897 if (ret)
898 return ret;
899 goto out;
900 }
901
902 /* Store one-time values in driver PPTable */
903 if (!pptable->Init) {
904 while (--retry) {
905 ret = smu_v13_0_6_get_metrics_table(smu, NULL, true);
906 if (ret)
907 return ret;
908
909 /* Ensure that metrics have been updated */
910 if (GET_METRIC_FIELD(AccumulationCounter, version))
911 break;
912
913 usleep_range(1000, 1100);
914 }
915
916 if (!retry)
917 return -ETIME;
918
919 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetMetricsVersion,
920 &table_version);
921 if (ret)
922 return ret;
923 smu_table->tables[SMU_TABLE_SMU_METRICS].version =
924 table_version;
925
926 pptable->MaxSocketPowerLimit =
927 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketPowerLimit, version));
928 pptable->MaxGfxclkFrequency =
929 SMUQ10_ROUND(GET_METRIC_FIELD(MaxGfxclkFrequency, version));
930 pptable->MinGfxclkFrequency =
931 SMUQ10_ROUND(GET_METRIC_FIELD(MinGfxclkFrequency, version));
932 max_width = (uint8_t)GET_METRIC_FIELD(XgmiWidth, version);
933 max_speed = (uint16_t)GET_METRIC_FIELD(XgmiBitrate, version);
934 amgpu_xgmi_set_max_speed_width(smu->adev, max_speed, max_width);
935
936 for (i = 0; i < 4; ++i) {
937 pptable->FclkFrequencyTable[i] =
938 SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequencyTable, version)[i]);
939 pptable->UclkFrequencyTable[i] =
940 SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequencyTable, version)[i]);
941 pptable->SocclkFrequencyTable[i] = SMUQ10_ROUND(
942 GET_METRIC_FIELD(SocclkFrequencyTable, version)[i]);
943 pptable->VclkFrequencyTable[i] =
944 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequencyTable, version)[i]);
945 pptable->DclkFrequencyTable[i] =
946 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequencyTable, version)[i]);
947 pptable->LclkFrequencyTable[i] =
948 SMUQ10_ROUND(GET_METRIC_FIELD(LclkFrequencyTable, version)[i]);
949 }
950
951 /* use AID0 serial number by default */
952 pptable->PublicSerialNumber_AID =
953 GET_METRIC_FIELD(PublicSerialNumber_AID, version)[0];
954
955 amdgpu_device_set_uid(smu->adev->uid_info, AMDGPU_UID_TYPE_SOC,
956 0, pptable->PublicSerialNumber_AID);
957 n = ARRAY_SIZE(metrics_v0->PublicSerialNumber_AID);
958 for (i = 0; i < n; i++) {
959 amdgpu_device_set_uid(
960 smu->adev->uid_info, AMDGPU_UID_TYPE_AID, i,
961 GET_METRIC_FIELD(PublicSerialNumber_AID,
962 version)[i]);
963 }
964 n = ARRAY_SIZE(metrics_v0->PublicSerialNumber_XCD);
965 for (i = 0; i < n; i++) {
966 amdgpu_device_set_uid(
967 smu->adev->uid_info, AMDGPU_UID_TYPE_XCD, i,
968 GET_METRIC_FIELD(PublicSerialNumber_XCD,
969 version)[i]);
970 }
971
972 pptable->Init = true;
973 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {
974 ret = smu_v13_0_6_get_static_metrics_table(smu);
975 if (ret)
976 return ret;
977 smu_v13_0_6_fill_static_metrics_table(smu, static_metrics);
978 }
979 }
980 out:
981 smu_v13_0_6_update_caps(smu);
982 return 0;
983 }
984
smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * min,uint32_t * max)985 static int smu_v13_0_6_get_dpm_ultimate_freq(struct smu_context *smu,
986 enum smu_clk_type clk_type,
987 uint32_t *min, uint32_t *max)
988 {
989 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
990 struct smu_table_context *smu_table = &smu->smu_table;
991 struct PPTable_t *pptable =
992 (struct PPTable_t *)smu_table->driver_pptable;
993 struct smu_dpm_table *dpm_table;
994 uint32_t min_clk, max_clk, param;
995 int ret = 0, clk_id = 0;
996
997 /* Use dpm tables, if data is already fetched */
998 if (pptable->Init) {
999 switch (clk_type) {
1000 case SMU_MCLK:
1001 case SMU_UCLK:
1002 dpm_table = &dpm_context->dpm_tables.uclk_table;
1003 break;
1004 case SMU_GFXCLK:
1005 case SMU_SCLK:
1006 dpm_table = &dpm_context->dpm_tables.gfx_table;
1007 break;
1008 case SMU_SOCCLK:
1009 dpm_table = &dpm_context->dpm_tables.soc_table;
1010 break;
1011 case SMU_FCLK:
1012 dpm_table = &dpm_context->dpm_tables.fclk_table;
1013 break;
1014 case SMU_VCLK:
1015 dpm_table = &dpm_context->dpm_tables.vclk_table;
1016 break;
1017 case SMU_DCLK:
1018 dpm_table = &dpm_context->dpm_tables.dclk_table;
1019 break;
1020 default:
1021 return -EINVAL;
1022 }
1023
1024 min_clk = SMU_DPM_TABLE_MIN(dpm_table);
1025 max_clk = SMU_DPM_TABLE_MAX(dpm_table);
1026 if (min)
1027 *min = min_clk;
1028 if (max)
1029 *max = max_clk;
1030
1031 if (min_clk && max_clk)
1032 return 0;
1033 }
1034
1035 if (!(clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)) {
1036 clk_id = smu_cmn_to_asic_specific_index(
1037 smu, CMN2ASIC_MAPPING_CLK, clk_type);
1038 if (clk_id < 0) {
1039 ret = -EINVAL;
1040 goto failed;
1041 }
1042 param = (clk_id & 0xffff) << 16;
1043 }
1044
1045 if (max) {
1046 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
1047 ret = smu_cmn_send_smc_msg(
1048 smu, SMU_MSG_GetMaxGfxclkFrequency, max);
1049 else
1050 ret = smu_cmn_send_smc_msg_with_param(
1051 smu, SMU_MSG_GetMaxDpmFreq, param, max);
1052 if (ret)
1053 goto failed;
1054 }
1055
1056 if (min) {
1057 if (clk_type == SMU_GFXCLK || clk_type == SMU_SCLK)
1058 ret = smu_cmn_send_smc_msg(
1059 smu, SMU_MSG_GetMinGfxclkFrequency, min);
1060 else
1061 ret = smu_cmn_send_smc_msg_with_param(
1062 smu, SMU_MSG_GetMinDpmFreq, param, min);
1063 }
1064
1065 failed:
1066 return ret;
1067 }
1068
smu_v13_0_6_get_dpm_level_count(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * levels)1069 static int smu_v13_0_6_get_dpm_level_count(struct smu_context *smu,
1070 enum smu_clk_type clk_type,
1071 uint32_t *levels)
1072 {
1073 int ret;
1074
1075 ret = smu_v13_0_get_dpm_freq_by_index(smu, clk_type, 0xff, levels);
1076 if (!ret)
1077 ++(*levels);
1078
1079 return ret;
1080 }
1081
smu_v13_0_6_pm_policy_init(struct smu_context * smu)1082 static void smu_v13_0_6_pm_policy_init(struct smu_context *smu)
1083 {
1084 struct smu_dpm_policy *policy;
1085
1086 policy = smu_get_pm_policy(smu, PP_PM_POLICY_SOC_PSTATE);
1087 if (policy)
1088 policy->current_level = SOC_PSTATE_DEFAULT;
1089 }
1090
smu_v13_0_6_set_default_dpm_table(struct smu_context * smu)1091 static int smu_v13_0_6_set_default_dpm_table(struct smu_context *smu)
1092 {
1093 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1094 struct smu_table_context *smu_table = &smu->smu_table;
1095 struct smu_dpm_table *dpm_table = NULL;
1096 struct PPTable_t *pptable =
1097 (struct PPTable_t *)smu_table->driver_pptable;
1098 uint32_t gfxclkmin, gfxclkmax, levels;
1099 int ret = 0, i, j;
1100 struct smu_v13_0_6_dpm_map dpm_map[] = {
1101 { SMU_SOCCLK, SMU_FEATURE_DPM_SOCCLK_BIT,
1102 &dpm_context->dpm_tables.soc_table,
1103 pptable->SocclkFrequencyTable },
1104 { SMU_UCLK, SMU_FEATURE_DPM_UCLK_BIT,
1105 &dpm_context->dpm_tables.uclk_table,
1106 pptable->UclkFrequencyTable },
1107 { SMU_FCLK, SMU_FEATURE_DPM_FCLK_BIT,
1108 &dpm_context->dpm_tables.fclk_table,
1109 pptable->FclkFrequencyTable },
1110 { SMU_VCLK, SMU_FEATURE_DPM_VCLK_BIT,
1111 &dpm_context->dpm_tables.vclk_table,
1112 pptable->VclkFrequencyTable },
1113 { SMU_DCLK, SMU_FEATURE_DPM_DCLK_BIT,
1114 &dpm_context->dpm_tables.dclk_table,
1115 pptable->DclkFrequencyTable },
1116 };
1117
1118 smu_v13_0_6_setup_driver_pptable(smu);
1119
1120 /* DPM policy not supported in older firmwares */
1121 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM_POLICY))) {
1122 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1123
1124 smu_dpm->dpm_policies->policy_mask &=
1125 ~BIT(PP_PM_POLICY_SOC_PSTATE);
1126 }
1127
1128 smu_v13_0_6_pm_policy_init(smu);
1129 /* gfxclk dpm table setup */
1130 dpm_table = &dpm_context->dpm_tables.gfx_table;
1131 dpm_table->clk_type = SMU_GFXCLK;
1132 dpm_table->flags = SMU_DPM_TABLE_FINE_GRAINED;
1133 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT)) {
1134 /* In the case of gfxclk, only fine-grained dpm is honored.
1135 * Get min/max values from FW.
1136 */
1137 ret = smu_v13_0_6_get_dpm_ultimate_freq(smu, SMU_GFXCLK,
1138 &gfxclkmin, &gfxclkmax);
1139 if (ret)
1140 return ret;
1141 dpm_table->count = 2;
1142 dpm_table->dpm_levels[0].value = gfxclkmin;
1143 dpm_table->dpm_levels[0].enabled = true;
1144 dpm_table->dpm_levels[1].value = gfxclkmax;
1145 dpm_table->dpm_levels[1].enabled = true;
1146 } else {
1147 dpm_table->count = 1;
1148 dpm_table->dpm_levels[0].value = pptable->MinGfxclkFrequency;
1149 dpm_table->dpm_levels[0].enabled = true;
1150 }
1151
1152 for (j = 0; j < ARRAY_SIZE(dpm_map); j++) {
1153 dpm_table = dpm_map[j].dpm_table;
1154 levels = 1;
1155 if (smu_cmn_feature_is_enabled(smu, dpm_map[j].feature_num)) {
1156 ret = smu_v13_0_6_get_dpm_level_count(
1157 smu, dpm_map[j].clk_type, &levels);
1158 if (ret)
1159 return ret;
1160 }
1161 dpm_table->count = levels;
1162 dpm_table->clk_type = dpm_map[j].clk_type;
1163 for (i = 0; i < dpm_table->count; ++i) {
1164 dpm_table->dpm_levels[i].value =
1165 dpm_map[j].freq_table[i];
1166 dpm_table->dpm_levels[i].enabled = true;
1167 }
1168 }
1169
1170 return 0;
1171 }
1172
smu_v13_0_6_setup_pptable(struct smu_context * smu)1173 static int smu_v13_0_6_setup_pptable(struct smu_context *smu)
1174 {
1175 struct smu_table_context *table_context = &smu->smu_table;
1176
1177 /* TODO: PPTable is not available.
1178 * 1) Find an alternate way to get 'PPTable values' here.
1179 * 2) Check if there is SW CTF
1180 */
1181 table_context->thermal_controller_type = 0;
1182
1183 return 0;
1184 }
1185
smu_v13_0_6_check_fw_status(struct smu_context * smu)1186 static int smu_v13_0_6_check_fw_status(struct smu_context *smu)
1187 {
1188 struct amdgpu_device *adev = smu->adev;
1189 uint32_t mp1_fw_flags;
1190
1191 mp1_fw_flags =
1192 RREG32_PCIE(MP1_Public | (smnMP1_FIRMWARE_FLAGS & 0xffffffff));
1193
1194 if ((mp1_fw_flags & MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED_MASK) >>
1195 MP1_FIRMWARE_FLAGS__INTERRUPTS_ENABLED__SHIFT)
1196 return 0;
1197
1198 return -EIO;
1199 }
1200
smu_v13_0_6_populate_umd_state_clk(struct smu_context * smu)1201 static int smu_v13_0_6_populate_umd_state_clk(struct smu_context *smu)
1202 {
1203 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1204 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
1205 struct smu_dpm_table *mem_table = &dpm_context->dpm_tables.uclk_table;
1206 struct smu_dpm_table *soc_table = &dpm_context->dpm_tables.soc_table;
1207 struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table;
1208 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1209
1210 pstate_table->gfxclk_pstate.min = SMU_DPM_TABLE_MIN(gfx_table);
1211 pstate_table->gfxclk_pstate.peak = SMU_DPM_TABLE_MAX(gfx_table);
1212 pstate_table->gfxclk_pstate.curr.min = SMU_DPM_TABLE_MIN(gfx_table);
1213 pstate_table->gfxclk_pstate.curr.max = SMU_DPM_TABLE_MAX(gfx_table);
1214
1215 pstate_table->uclk_pstate.min = SMU_DPM_TABLE_MIN(mem_table);
1216 pstate_table->uclk_pstate.peak = SMU_DPM_TABLE_MAX(mem_table);
1217 pstate_table->uclk_pstate.curr.min = SMU_DPM_TABLE_MIN(mem_table);
1218 pstate_table->uclk_pstate.curr.max = SMU_DPM_TABLE_MAX(mem_table);
1219
1220 pstate_table->socclk_pstate.min = SMU_DPM_TABLE_MIN(soc_table);
1221 pstate_table->socclk_pstate.peak = SMU_DPM_TABLE_MAX(soc_table);
1222 pstate_table->socclk_pstate.curr.min = SMU_DPM_TABLE_MIN(soc_table);
1223 pstate_table->socclk_pstate.curr.max = SMU_DPM_TABLE_MAX(soc_table);
1224
1225 pstate_table->fclk_pstate.min = SMU_DPM_TABLE_MIN(fclk_table);
1226 pstate_table->fclk_pstate.peak = SMU_DPM_TABLE_MAX(fclk_table);
1227 pstate_table->fclk_pstate.curr.min = SMU_DPM_TABLE_MIN(fclk_table);
1228 pstate_table->fclk_pstate.curr.max = SMU_DPM_TABLE_MAX(fclk_table);
1229 pstate_table->fclk_pstate.standard = SMU_DPM_TABLE_MIN(fclk_table);
1230
1231 if (gfx_table->count > SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL &&
1232 mem_table->count > SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL &&
1233 soc_table->count > SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL) {
1234 pstate_table->gfxclk_pstate.standard =
1235 gfx_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_GFXCLK_LEVEL].value;
1236 pstate_table->uclk_pstate.standard =
1237 mem_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_MCLK_LEVEL].value;
1238 pstate_table->socclk_pstate.standard =
1239 soc_table->dpm_levels[SMU_13_0_6_UMD_PSTATE_SOCCLK_LEVEL].value;
1240 } else {
1241 pstate_table->gfxclk_pstate.standard =
1242 pstate_table->gfxclk_pstate.min;
1243 pstate_table->uclk_pstate.standard =
1244 pstate_table->uclk_pstate.min;
1245 pstate_table->socclk_pstate.standard =
1246 pstate_table->socclk_pstate.min;
1247 }
1248
1249 return 0;
1250 }
1251
smu_v13_0_6_get_throttler_status(struct smu_context * smu)1252 static uint32_t smu_v13_0_6_get_throttler_status(struct smu_context *smu)
1253 {
1254 struct smu_power_context *smu_power = &smu->smu_power;
1255 struct smu_13_0_power_context *power_context = smu_power->power_context;
1256 uint32_t throttler_status = 0;
1257
1258 throttler_status = atomic_read(&power_context->throttle_status);
1259 dev_dbg(smu->adev->dev, "SMU Throttler status: %u", throttler_status);
1260
1261 return throttler_status;
1262 }
1263
smu_v13_0_6_get_smu_metrics_data(struct smu_context * smu,MetricsMember_t member,uint32_t * value)1264 static int smu_v13_0_6_get_smu_metrics_data(struct smu_context *smu,
1265 MetricsMember_t member,
1266 uint32_t *value)
1267 {
1268 struct smu_table_context *smu_table = &smu->smu_table;
1269 MetricsTableV0_t *metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
1270 MetricsTableV1_t *metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
1271 MetricsTableV2_t *metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
1272 int version = smu_v13_0_6_get_metrics_version(smu);
1273 struct amdgpu_device *adev = smu->adev;
1274 int ret = 0;
1275 int xcc_id;
1276
1277 ret = smu_v13_0_6_get_metrics_table(smu, NULL, false);
1278 if (ret)
1279 return ret;
1280
1281 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) &&
1282 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
1283 return smu_v13_0_12_get_smu_metrics_data(smu, member, value);
1284
1285 /* For clocks with multiple instances, only report the first one */
1286 switch (member) {
1287 case METRICS_CURR_GFXCLK:
1288 case METRICS_AVERAGE_GFXCLK:
1289 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
1290 xcc_id = GET_INST(GC, 0);
1291 *value = SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]);
1292 } else {
1293 *value = 0;
1294 }
1295 break;
1296 case METRICS_CURR_SOCCLK:
1297 case METRICS_AVERAGE_SOCCLK:
1298 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, version)[0]);
1299 break;
1300 case METRICS_CURR_UCLK:
1301 case METRICS_AVERAGE_UCLK:
1302 *value = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
1303 break;
1304 case METRICS_CURR_VCLK:
1305 *value = SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency, version)[0]);
1306 break;
1307 case METRICS_CURR_DCLK:
1308 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency, version)[0]);
1309 break;
1310 case METRICS_CURR_FCLK:
1311 *value = SMUQ10_ROUND(GET_METRIC_FIELD(FclkFrequency, version));
1312 break;
1313 case METRICS_AVERAGE_GFXACTIVITY:
1314 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, version));
1315 break;
1316 case METRICS_AVERAGE_MEMACTIVITY:
1317 *value = SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, version));
1318 break;
1319 case METRICS_CURR_SOCKETPOWER:
1320 *value = SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, version)) << 8;
1321 break;
1322 case METRICS_TEMPERATURE_HOTSPOT:
1323 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version)) *
1324 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1325 break;
1326 case METRICS_TEMPERATURE_MEM:
1327 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, version)) *
1328 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1329 break;
1330 /* This is the max of all VRs and not just SOC VR.
1331 * No need to define another data type for the same.
1332 */
1333 case METRICS_TEMPERATURE_VRSOC:
1334 *value = SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, version)) *
1335 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
1336 break;
1337 default:
1338 *value = UINT_MAX;
1339 break;
1340 }
1341
1342 return ret;
1343 }
1344
smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t * value)1345 static int smu_v13_0_6_get_current_clk_freq_by_table(struct smu_context *smu,
1346 enum smu_clk_type clk_type,
1347 uint32_t *value)
1348 {
1349 MetricsMember_t member_type;
1350
1351 if (!value)
1352 return -EINVAL;
1353
1354 switch (clk_type) {
1355 case SMU_GFXCLK:
1356 case SMU_SCLK:
1357 member_type = METRICS_CURR_GFXCLK;
1358 break;
1359 case SMU_UCLK:
1360 case SMU_MCLK:
1361 member_type = METRICS_CURR_UCLK;
1362 break;
1363 case SMU_SOCCLK:
1364 member_type = METRICS_CURR_SOCCLK;
1365 break;
1366 case SMU_VCLK:
1367 member_type = METRICS_CURR_VCLK;
1368 break;
1369 case SMU_DCLK:
1370 member_type = METRICS_CURR_DCLK;
1371 break;
1372 case SMU_FCLK:
1373 member_type = METRICS_CURR_FCLK;
1374 break;
1375 default:
1376 return -EINVAL;
1377 }
1378
1379 return smu_v13_0_6_get_smu_metrics_data(smu, member_type, value);
1380 }
1381
smu_v13_0_6_emit_clk_levels(struct smu_context * smu,enum smu_clk_type type,char * buf,int * offset)1382 static int smu_v13_0_6_emit_clk_levels(struct smu_context *smu,
1383 enum smu_clk_type type, char *buf,
1384 int *offset)
1385 {
1386 int now, size = *offset, start_offset = *offset;
1387 int ret = 0;
1388 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1389 struct smu_dpm_table *single_dpm_table = NULL;
1390 struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1391 struct smu_13_0_dpm_context *dpm_context = NULL;
1392
1393 if (amdgpu_ras_intr_triggered()) {
1394 sysfs_emit_at(buf, size, "unavailable\n");
1395 return -EBUSY;
1396 }
1397
1398 dpm_context = smu_dpm->dpm_context;
1399
1400 switch (type) {
1401 case SMU_OD_SCLK:
1402 size += sysfs_emit_at(buf, size, "%s:\n", "OD_SCLK");
1403 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1404 pstate_table->gfxclk_pstate.curr.min,
1405 pstate_table->gfxclk_pstate.curr.max);
1406 break;
1407 case SMU_OD_MCLK:
1408 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SET_UCLK_MAX)))
1409 return -EOPNOTSUPP;
1410
1411 size += sysfs_emit_at(buf, size, "%s:\n", "OD_MCLK");
1412 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1413 pstate_table->uclk_pstate.curr.min,
1414 pstate_table->uclk_pstate.curr.max);
1415 break;
1416 case SMU_OD_FCLK:
1417 if (!smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_FCLK_BIT))
1418 return -EOPNOTSUPP;
1419
1420 size += sysfs_emit_at(buf, size, "%s:\n", "OD_FCLK");
1421 size += sysfs_emit_at(buf, size, "0: %uMhz\n1: %uMhz\n",
1422 pstate_table->fclk_pstate.curr.min,
1423 pstate_table->fclk_pstate.curr.max);
1424 break;
1425 case SMU_SCLK:
1426 case SMU_GFXCLK:
1427 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1428 break;
1429 case SMU_MCLK:
1430 case SMU_UCLK:
1431 single_dpm_table = &(dpm_context->dpm_tables.uclk_table);
1432 break;
1433 case SMU_SOCCLK:
1434 single_dpm_table = &(dpm_context->dpm_tables.soc_table);
1435 break;
1436 case SMU_FCLK:
1437 single_dpm_table = &(dpm_context->dpm_tables.fclk_table);
1438 break;
1439 case SMU_VCLK:
1440 single_dpm_table = &(dpm_context->dpm_tables.vclk_table);
1441 break;
1442 case SMU_DCLK:
1443 single_dpm_table = &(dpm_context->dpm_tables.dclk_table);
1444 break;
1445 default:
1446 break;
1447 }
1448
1449 if (single_dpm_table) {
1450 ret = smu_v13_0_6_get_current_clk_freq_by_table(smu, type,
1451 &now);
1452 if (ret) {
1453 dev_err(smu->adev->dev,
1454 "Attempt to get current clk Failed!");
1455 return ret;
1456 }
1457 return smu_cmn_print_dpm_clk_levels(smu, single_dpm_table, now,
1458 buf, offset);
1459 }
1460
1461 *offset += size - start_offset;
1462
1463 return 0;
1464 }
1465
smu_v13_0_6_upload_dpm_level(struct smu_context * smu,bool max,uint32_t feature_mask,uint32_t level)1466 static int smu_v13_0_6_upload_dpm_level(struct smu_context *smu, bool max,
1467 uint32_t feature_mask, uint32_t level)
1468 {
1469 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1470 uint32_t freq;
1471 int ret = 0;
1472
1473 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_GFXCLK_BIT) &&
1474 (feature_mask & FEATURE_MASK(FEATURE_DPM_GFXCLK))) {
1475 freq = dpm_context->dpm_tables.gfx_table.dpm_levels[level].value;
1476 ret = smu_cmn_send_smc_msg_with_param(
1477 smu,
1478 (max ? SMU_MSG_SetSoftMaxGfxClk :
1479 SMU_MSG_SetSoftMinGfxclk),
1480 freq & 0xffff, NULL);
1481 if (ret) {
1482 dev_err(smu->adev->dev,
1483 "Failed to set soft %s gfxclk !\n",
1484 max ? "max" : "min");
1485 return ret;
1486 }
1487 }
1488
1489 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_UCLK_BIT) &&
1490 (feature_mask & FEATURE_MASK(FEATURE_DPM_UCLK))) {
1491 freq = dpm_context->dpm_tables.uclk_table.dpm_levels[level]
1492 .value;
1493 ret = smu_cmn_send_smc_msg_with_param(
1494 smu,
1495 (max ? SMU_MSG_SetSoftMaxByFreq :
1496 SMU_MSG_SetSoftMinByFreq),
1497 (PPCLK_UCLK << 16) | (freq & 0xffff), NULL);
1498 if (ret) {
1499 dev_err(smu->adev->dev,
1500 "Failed to set soft %s memclk !\n",
1501 max ? "max" : "min");
1502 return ret;
1503 }
1504 }
1505
1506 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_DPM_SOCCLK_BIT) &&
1507 (feature_mask & FEATURE_MASK(FEATURE_DPM_SOCCLK))) {
1508 freq = dpm_context->dpm_tables.soc_table.dpm_levels[level].value;
1509 ret = smu_cmn_send_smc_msg_with_param(
1510 smu,
1511 (max ? SMU_MSG_SetSoftMaxByFreq :
1512 SMU_MSG_SetSoftMinByFreq),
1513 (PPCLK_SOCCLK << 16) | (freq & 0xffff), NULL);
1514 if (ret) {
1515 dev_err(smu->adev->dev,
1516 "Failed to set soft %s socclk !\n",
1517 max ? "max" : "min");
1518 return ret;
1519 }
1520 }
1521
1522 return ret;
1523 }
1524
smu_v13_0_6_force_clk_levels(struct smu_context * smu,enum smu_clk_type type,uint32_t mask)1525 static int smu_v13_0_6_force_clk_levels(struct smu_context *smu,
1526 enum smu_clk_type type, uint32_t mask)
1527 {
1528 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1529 struct smu_dpm_table *single_dpm_table = NULL;
1530 uint32_t soft_min_level, soft_max_level;
1531 int ret = 0;
1532
1533 soft_min_level = mask ? (ffs(mask) - 1) : 0;
1534 soft_max_level = mask ? (fls(mask) - 1) : 0;
1535
1536 switch (type) {
1537 case SMU_SCLK:
1538 single_dpm_table = &(dpm_context->dpm_tables.gfx_table);
1539 if (soft_max_level >= single_dpm_table->count) {
1540 dev_err(smu->adev->dev,
1541 "Clock level specified %d is over max allowed %d\n",
1542 soft_max_level, single_dpm_table->count - 1);
1543 ret = -EINVAL;
1544 break;
1545 }
1546
1547 ret = smu_v13_0_6_upload_dpm_level(
1548 smu, false, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1549 soft_min_level);
1550 if (ret) {
1551 dev_err(smu->adev->dev,
1552 "Failed to upload boot level to lowest!\n");
1553 break;
1554 }
1555
1556 ret = smu_v13_0_6_upload_dpm_level(
1557 smu, true, FEATURE_MASK(FEATURE_DPM_GFXCLK),
1558 soft_max_level);
1559 if (ret)
1560 dev_err(smu->adev->dev,
1561 "Failed to upload dpm max level to highest!\n");
1562
1563 break;
1564
1565 case SMU_MCLK:
1566 case SMU_SOCCLK:
1567 case SMU_FCLK:
1568 /*
1569 * Should not arrive here since smu_13_0_6 does not
1570 * support mclk/socclk/fclk softmin/softmax settings
1571 */
1572 ret = -EINVAL;
1573 break;
1574
1575 default:
1576 break;
1577 }
1578
1579 return ret;
1580 }
1581
smu_v13_0_6_get_current_activity_percent(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1582 static int smu_v13_0_6_get_current_activity_percent(struct smu_context *smu,
1583 enum amd_pp_sensors sensor,
1584 uint32_t *value)
1585 {
1586 int ret = 0;
1587
1588 if (!value)
1589 return -EINVAL;
1590
1591 switch (sensor) {
1592 case AMDGPU_PP_SENSOR_GPU_LOAD:
1593 ret = smu_v13_0_6_get_smu_metrics_data(
1594 smu, METRICS_AVERAGE_GFXACTIVITY, value);
1595 break;
1596 case AMDGPU_PP_SENSOR_MEM_LOAD:
1597 ret = smu_v13_0_6_get_smu_metrics_data(
1598 smu, METRICS_AVERAGE_MEMACTIVITY, value);
1599 break;
1600 default:
1601 dev_err(smu->adev->dev,
1602 "Invalid sensor for retrieving clock activity\n");
1603 return -EINVAL;
1604 }
1605
1606 return ret;
1607 }
1608
smu_v13_0_6_thermal_get_temperature(struct smu_context * smu,enum amd_pp_sensors sensor,uint32_t * value)1609 static int smu_v13_0_6_thermal_get_temperature(struct smu_context *smu,
1610 enum amd_pp_sensors sensor,
1611 uint32_t *value)
1612 {
1613 int ret = 0;
1614
1615 if (!value)
1616 return -EINVAL;
1617
1618 switch (sensor) {
1619 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1620 ret = smu_v13_0_6_get_smu_metrics_data(
1621 smu, METRICS_TEMPERATURE_HOTSPOT, value);
1622 break;
1623 case AMDGPU_PP_SENSOR_MEM_TEMP:
1624 ret = smu_v13_0_6_get_smu_metrics_data(
1625 smu, METRICS_TEMPERATURE_MEM, value);
1626 break;
1627 default:
1628 dev_err(smu->adev->dev, "Invalid sensor for retrieving temp\n");
1629 return -EINVAL;
1630 }
1631
1632 return ret;
1633 }
1634
smu_v13_0_6_read_sensor(struct smu_context * smu,enum amd_pp_sensors sensor,void * data,uint32_t * size)1635 static int smu_v13_0_6_read_sensor(struct smu_context *smu,
1636 enum amd_pp_sensors sensor, void *data,
1637 uint32_t *size)
1638 {
1639 struct smu_13_0_dpm_context *dpm_context = smu->smu_dpm.dpm_context;
1640 int ret = 0;
1641
1642 if (amdgpu_ras_intr_triggered())
1643 return 0;
1644
1645 if (!data || !size)
1646 return -EINVAL;
1647
1648 switch (sensor) {
1649 case AMDGPU_PP_SENSOR_MEM_LOAD:
1650 case AMDGPU_PP_SENSOR_GPU_LOAD:
1651 ret = smu_v13_0_6_get_current_activity_percent(smu, sensor,
1652 (uint32_t *)data);
1653 *size = 4;
1654 break;
1655 case AMDGPU_PP_SENSOR_GPU_INPUT_POWER:
1656 ret = smu_v13_0_6_get_smu_metrics_data(smu,
1657 METRICS_CURR_SOCKETPOWER,
1658 (uint32_t *)data);
1659 *size = 4;
1660 break;
1661 case AMDGPU_PP_SENSOR_HOTSPOT_TEMP:
1662 case AMDGPU_PP_SENSOR_MEM_TEMP:
1663 ret = smu_v13_0_6_thermal_get_temperature(smu, sensor,
1664 (uint32_t *)data);
1665 *size = 4;
1666 break;
1667 case AMDGPU_PP_SENSOR_GFX_MCLK:
1668 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1669 smu, SMU_UCLK, (uint32_t *)data);
1670 /* the output clock frequency in 10K unit */
1671 *(uint32_t *)data *= 100;
1672 *size = 4;
1673 break;
1674 case AMDGPU_PP_SENSOR_GFX_SCLK:
1675 ret = smu_v13_0_6_get_current_clk_freq_by_table(
1676 smu, SMU_GFXCLK, (uint32_t *)data);
1677 *(uint32_t *)data *= 100;
1678 *size = 4;
1679 break;
1680 case AMDGPU_PP_SENSOR_VDDGFX:
1681 ret = smu_v13_0_get_gfx_vdd(smu, (uint32_t *)data);
1682 *size = 4;
1683 break;
1684 case AMDGPU_PP_SENSOR_VDDBOARD:
1685 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(BOARD_VOLTAGE))) {
1686 *(uint32_t *)data = dpm_context->board_volt;
1687 *size = 4;
1688 break;
1689 } else {
1690 ret = -EOPNOTSUPP;
1691 break;
1692 }
1693 case AMDGPU_PP_SENSOR_NODEPOWERLIMIT:
1694 case AMDGPU_PP_SENSOR_NODEPOWER:
1695 case AMDGPU_PP_SENSOR_GPPTRESIDENCY:
1696 case AMDGPU_PP_SENSOR_MAXNODEPOWERLIMIT:
1697 ret = smu_v13_0_12_get_npm_data(smu, sensor, (uint32_t *)data);
1698 if (ret)
1699 return ret;
1700 *size = 4;
1701 break;
1702 case AMDGPU_PP_SENSOR_UBB_POWER:
1703 case AMDGPU_PP_SENSOR_UBB_POWER_LIMIT:
1704 ret = smu_v13_0_12_get_system_power(smu, sensor, (uint32_t *)data);
1705 if (ret)
1706 return ret;
1707 *size = 4;
1708 break;
1709 case AMDGPU_PP_SENSOR_GPU_AVG_POWER:
1710 default:
1711 ret = -EOPNOTSUPP;
1712 break;
1713 }
1714
1715 return ret;
1716 }
1717
smu_v13_0_6_get_power_limit(struct smu_context * smu,uint32_t * current_power_limit,uint32_t * default_power_limit,uint32_t * max_power_limit,uint32_t * min_power_limit)1718 static int smu_v13_0_6_get_power_limit(struct smu_context *smu,
1719 uint32_t *current_power_limit,
1720 uint32_t *default_power_limit,
1721 uint32_t *max_power_limit,
1722 uint32_t *min_power_limit)
1723 {
1724 struct smu_table_context *smu_table = &smu->smu_table;
1725 struct PPTable_t *pptable =
1726 (struct PPTable_t *)smu_table->driver_pptable;
1727 uint32_t power_limit = 0;
1728 int ret;
1729
1730 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetPptLimit, &power_limit);
1731
1732 if (ret) {
1733 dev_err(smu->adev->dev, "Couldn't get PPT limit");
1734 return -EINVAL;
1735 }
1736
1737 if (current_power_limit)
1738 *current_power_limit = power_limit;
1739 if (default_power_limit)
1740 *default_power_limit = pptable->MaxSocketPowerLimit;
1741
1742 if (max_power_limit) {
1743 *max_power_limit = pptable->MaxSocketPowerLimit;
1744 }
1745
1746 if (min_power_limit)
1747 *min_power_limit = 0;
1748 return 0;
1749 }
1750
smu_v13_0_6_set_power_limit(struct smu_context * smu,enum smu_ppt_limit_type limit_type,uint32_t limit)1751 static int smu_v13_0_6_set_power_limit(struct smu_context *smu,
1752 enum smu_ppt_limit_type limit_type,
1753 uint32_t limit)
1754 {
1755 struct smu_table_context *smu_table = &smu->smu_table;
1756 struct PPTable_t *pptable =
1757 (struct PPTable_t *)smu_table->driver_pptable;
1758 int ret;
1759
1760 if (limit_type == SMU_FAST_PPT_LIMIT) {
1761 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)))
1762 return -EOPNOTSUPP;
1763 if (limit > pptable->PPT1Max || limit < pptable->PPT1Min) {
1764 dev_err(smu->adev->dev,
1765 "New power limit (%d) should be between min %d max %d\n",
1766 limit, pptable->PPT1Min, pptable->PPT1Max);
1767 return -EINVAL;
1768 }
1769 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetFastPptLimit,
1770 limit, NULL);
1771 if (ret)
1772 dev_err(smu->adev->dev, "Set fast PPT limit failed!\n");
1773 return ret;
1774 }
1775
1776 return smu_v13_0_set_power_limit(smu, limit_type, limit);
1777 }
1778
smu_v13_0_6_get_ppt_limit(struct smu_context * smu,uint32_t * ppt_limit,enum smu_ppt_limit_type type,enum smu_ppt_limit_level level)1779 static int smu_v13_0_6_get_ppt_limit(struct smu_context *smu,
1780 uint32_t *ppt_limit,
1781 enum smu_ppt_limit_type type,
1782 enum smu_ppt_limit_level level)
1783 {
1784 struct smu_table_context *smu_table = &smu->smu_table;
1785 struct PPTable_t *pptable =
1786 (struct PPTable_t *)smu_table->driver_pptable;
1787 int ret = 0;
1788
1789 if (type == SMU_FAST_PPT_LIMIT) {
1790 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(FAST_PPT)))
1791 return -EOPNOTSUPP;
1792 switch (level) {
1793 case SMU_PPT_LIMIT_MAX:
1794 *ppt_limit = pptable->PPT1Max;
1795 break;
1796 case SMU_PPT_LIMIT_CURRENT:
1797 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_GetFastPptLimit, ppt_limit);
1798 if (ret)
1799 dev_err(smu->adev->dev, "Get fast PPT limit failed!\n");
1800 break;
1801 case SMU_PPT_LIMIT_DEFAULT:
1802 *ppt_limit = pptable->PPT1Default;
1803 break;
1804 case SMU_PPT_LIMIT_MIN:
1805 *ppt_limit = pptable->PPT1Min;
1806 break;
1807 default:
1808 return -EOPNOTSUPP;
1809 }
1810 return ret;
1811 }
1812 return -EOPNOTSUPP;
1813 }
1814
smu_v13_0_6_irq_process(struct amdgpu_device * adev,struct amdgpu_irq_src * source,struct amdgpu_iv_entry * entry)1815 static int smu_v13_0_6_irq_process(struct amdgpu_device *adev,
1816 struct amdgpu_irq_src *source,
1817 struct amdgpu_iv_entry *entry)
1818 {
1819 struct smu_context *smu = adev->powerplay.pp_handle;
1820 struct smu_power_context *smu_power = &smu->smu_power;
1821 struct smu_13_0_power_context *power_context = smu_power->power_context;
1822 uint32_t client_id = entry->client_id;
1823 uint32_t ctxid = entry->src_data[0];
1824 uint32_t src_id = entry->src_id;
1825 uint32_t data;
1826
1827 if (client_id == SOC15_IH_CLIENTID_MP1) {
1828 if (src_id == IH_INTERRUPT_ID_TO_DRIVER) {
1829 /* ACK SMUToHost interrupt */
1830 data = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1831 data = REG_SET_FIELD(data, MP1_SMN_IH_SW_INT_CTRL, INT_ACK, 1);
1832 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, data);
1833 /*
1834 * ctxid is used to distinguish different events for SMCToHost
1835 * interrupt.
1836 */
1837 switch (ctxid) {
1838 case IH_INTERRUPT_CONTEXT_ID_THERMAL_THROTTLING:
1839 /*
1840 * Increment the throttle interrupt counter
1841 */
1842 atomic64_inc(&smu->throttle_int_counter);
1843
1844 if (!atomic_read(&adev->throttling_logging_enabled))
1845 return 0;
1846
1847 /* This uses the new method which fixes the
1848 * incorrect throttling status reporting
1849 * through metrics table. For older FWs,
1850 * it will be ignored.
1851 */
1852 if (__ratelimit(&adev->throttling_logging_rs)) {
1853 atomic_set(
1854 &power_context->throttle_status,
1855 entry->src_data[1]);
1856 schedule_work(&smu->throttling_logging_work);
1857 }
1858 break;
1859 default:
1860 dev_dbg(adev->dev, "Unhandled context id %d from client:%d!\n",
1861 ctxid, client_id);
1862 break;
1863 }
1864 }
1865 }
1866
1867 return 0;
1868 }
1869
smu_v13_0_6_set_irq_state(struct amdgpu_device * adev,struct amdgpu_irq_src * source,unsigned tyep,enum amdgpu_interrupt_state state)1870 static int smu_v13_0_6_set_irq_state(struct amdgpu_device *adev,
1871 struct amdgpu_irq_src *source,
1872 unsigned tyep,
1873 enum amdgpu_interrupt_state state)
1874 {
1875 uint32_t val = 0;
1876
1877 switch (state) {
1878 case AMDGPU_IRQ_STATE_DISABLE:
1879 /* For MP1 SW irqs */
1880 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1881 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 1);
1882 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1883
1884 break;
1885 case AMDGPU_IRQ_STATE_ENABLE:
1886 /* For MP1 SW irqs */
1887 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT);
1888 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, ID, 0xFE);
1889 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT, VALID, 0);
1890 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT, val);
1891
1892 val = RREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL);
1893 val = REG_SET_FIELD(val, MP1_SMN_IH_SW_INT_CTRL, INT_MASK, 0);
1894 WREG32_SOC15(MP1, 0, regMP1_SMN_IH_SW_INT_CTRL, val);
1895
1896 break;
1897 default:
1898 break;
1899 }
1900
1901 return 0;
1902 }
1903
1904 static const struct amdgpu_irq_src_funcs smu_v13_0_6_irq_funcs = {
1905 .set = smu_v13_0_6_set_irq_state,
1906 .process = smu_v13_0_6_irq_process,
1907 };
1908
smu_v13_0_6_register_irq_handler(struct smu_context * smu)1909 static int smu_v13_0_6_register_irq_handler(struct smu_context *smu)
1910 {
1911 struct amdgpu_device *adev = smu->adev;
1912 struct amdgpu_irq_src *irq_src = &smu->irq_source;
1913 int ret = 0;
1914
1915 if (amdgpu_sriov_vf(adev))
1916 return 0;
1917
1918 irq_src->num_types = 1;
1919 irq_src->funcs = &smu_v13_0_6_irq_funcs;
1920
1921 ret = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_MP1,
1922 IH_INTERRUPT_ID_TO_DRIVER,
1923 irq_src);
1924 if (ret)
1925 return ret;
1926
1927 return ret;
1928 }
1929
smu_v13_0_6_notify_unload(struct smu_context * smu)1930 static int smu_v13_0_6_notify_unload(struct smu_context *smu)
1931 {
1932 if (amdgpu_in_reset(smu->adev))
1933 return 0;
1934
1935 dev_dbg(smu->adev->dev, "Notify PMFW about driver unload");
1936 /* Ignore return, just intimate FW that driver is not going to be there */
1937 smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
1938
1939 return 0;
1940 }
1941
smu_v13_0_6_mca_set_debug_mode(struct smu_context * smu,bool enable)1942 static int smu_v13_0_6_mca_set_debug_mode(struct smu_context *smu, bool enable)
1943 {
1944 /* NOTE: this ClearMcaOnRead message is only supported for smu version 85.72.0 or higher */
1945 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(MCA_DEBUG_MODE)))
1946 return 0;
1947
1948 return smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ClearMcaOnRead,
1949 enable ? 0 : ClearMcaOnRead_UE_FLAG_MASK | ClearMcaOnRead_CE_POLL_MASK,
1950 NULL);
1951 }
1952
smu_v13_0_6_system_features_control(struct smu_context * smu,bool enable)1953 static int smu_v13_0_6_system_features_control(struct smu_context *smu,
1954 bool enable)
1955 {
1956 struct amdgpu_device *adev = smu->adev;
1957 int ret = 0;
1958
1959 if (amdgpu_sriov_vf(adev))
1960 return 0;
1961
1962 if (enable) {
1963 if (!(adev->flags & AMD_IS_APU))
1964 ret = smu_v13_0_system_features_control(smu, enable);
1965 } else {
1966 /* Notify FW that the device is no longer driver managed */
1967 smu_v13_0_6_notify_unload(smu);
1968 }
1969
1970 return ret;
1971 }
1972
smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context * smu,uint32_t min,uint32_t max)1973 static int smu_v13_0_6_set_gfx_soft_freq_limited_range(struct smu_context *smu,
1974 uint32_t min,
1975 uint32_t max)
1976 {
1977 int ret;
1978
1979 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMaxGfxClk,
1980 max & 0xffff, NULL);
1981 if (ret)
1982 return ret;
1983
1984 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_SetSoftMinGfxclk,
1985 min & 0xffff, NULL);
1986
1987 return ret;
1988 }
1989
smu_v13_0_6_set_performance_level(struct smu_context * smu,enum amd_dpm_forced_level level)1990 static int smu_v13_0_6_set_performance_level(struct smu_context *smu,
1991 enum amd_dpm_forced_level level)
1992 {
1993 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
1994 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
1995 struct smu_dpm_table *gfx_table = &dpm_context->dpm_tables.gfx_table;
1996 struct smu_dpm_table *uclk_table = &dpm_context->dpm_tables.uclk_table;
1997 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
1998 int ret;
1999
2000 /* Disable determinism if switching to another mode */
2001 if ((smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) &&
2002 (level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)) {
2003 smu_cmn_send_smc_msg(smu, SMU_MSG_DisableDeterminism, NULL);
2004 pstate_table->gfxclk_pstate.curr.max =
2005 SMU_DPM_TABLE_MAX(gfx_table);
2006 }
2007
2008 switch (level) {
2009 case AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM:
2010 return 0;
2011
2012 case AMD_DPM_FORCED_LEVEL_AUTO:
2013 if ((SMU_DPM_TABLE_MIN(gfx_table) !=
2014 pstate_table->gfxclk_pstate.curr.min) ||
2015 (SMU_DPM_TABLE_MAX(gfx_table) !=
2016 pstate_table->gfxclk_pstate.curr.max)) {
2017 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
2018 smu, SMU_DPM_TABLE_MIN(gfx_table),
2019 SMU_DPM_TABLE_MAX(gfx_table));
2020 if (ret)
2021 return ret;
2022
2023 pstate_table->gfxclk_pstate.curr.min =
2024 SMU_DPM_TABLE_MIN(gfx_table);
2025 pstate_table->gfxclk_pstate.curr.max =
2026 SMU_DPM_TABLE_MAX(gfx_table);
2027 }
2028
2029 if (SMU_DPM_TABLE_MAX(uclk_table) !=
2030 pstate_table->uclk_pstate.curr.max) {
2031 /* Min UCLK is not expected to be changed */
2032 ret = smu_v13_0_set_soft_freq_limited_range(
2033 smu, SMU_UCLK, 0, SMU_DPM_TABLE_MAX(uclk_table),
2034 false);
2035 if (ret)
2036 return ret;
2037 pstate_table->uclk_pstate.curr.max =
2038 SMU_DPM_TABLE_MAX(uclk_table);
2039 }
2040 smu_v13_0_reset_custom_level(smu);
2041
2042 return 0;
2043 case AMD_DPM_FORCED_LEVEL_MANUAL:
2044 return 0;
2045 default:
2046 break;
2047 }
2048
2049 return -EOPNOTSUPP;
2050 }
2051
smu_v13_0_6_set_soft_freq_limited_range(struct smu_context * smu,enum smu_clk_type clk_type,uint32_t min,uint32_t max,bool automatic)2052 static int smu_v13_0_6_set_soft_freq_limited_range(struct smu_context *smu,
2053 enum smu_clk_type clk_type,
2054 uint32_t min, uint32_t max,
2055 bool automatic)
2056 {
2057 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2058 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
2059 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
2060 struct amdgpu_device *adev = smu->adev;
2061 uint32_t min_clk;
2062 uint32_t max_clk;
2063 int ret = 0;
2064
2065 if (clk_type != SMU_GFXCLK && clk_type != SMU_SCLK &&
2066 clk_type != SMU_UCLK && clk_type != SMU_FCLK)
2067 return -EINVAL;
2068
2069 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
2070 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
2071 return -EINVAL;
2072
2073 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
2074 if (min >= max) {
2075 dev_err(smu->adev->dev,
2076 "Minimum clk should be less than the maximum allowed clock\n");
2077 return -EINVAL;
2078 }
2079
2080 if (clk_type == SMU_GFXCLK) {
2081 if ((min == pstate_table->gfxclk_pstate.curr.min) &&
2082 (max == pstate_table->gfxclk_pstate.curr.max))
2083 return 0;
2084
2085 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(
2086 smu, min, max);
2087 if (!ret) {
2088 pstate_table->gfxclk_pstate.curr.min = min;
2089 pstate_table->gfxclk_pstate.curr.max = max;
2090 }
2091 }
2092
2093 if (clk_type == SMU_UCLK) {
2094 if (max == pstate_table->uclk_pstate.curr.max)
2095 return 0;
2096 /* For VF, only allowed in FW versions 85.102 or greater */
2097 if (!smu_v13_0_6_cap_supported(smu,
2098 SMU_CAP(SET_UCLK_MAX)))
2099 return -EOPNOTSUPP;
2100 /* Only max clock limiting is allowed for UCLK */
2101 ret = smu_v13_0_set_soft_freq_limited_range(
2102 smu, SMU_UCLK, 0, max, false);
2103 if (!ret)
2104 pstate_table->uclk_pstate.curr.max = max;
2105 }
2106
2107 if (clk_type == SMU_FCLK) {
2108 if (max == pstate_table->fclk_pstate.curr.max)
2109 return 0;
2110
2111 ret = smu_v13_0_set_soft_freq_limited_range(smu, SMU_FCLK, 0, max, false);
2112 if (!ret)
2113 pstate_table->fclk_pstate.curr.max = max;
2114 }
2115
2116 return ret;
2117 }
2118
2119 if (smu_dpm->dpm_level == AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
2120 min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table);
2121 max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table);
2122 if (!max || (max < min_clk) || (max > max_clk)) {
2123 dev_warn(
2124 adev->dev,
2125 "Invalid max frequency %d MHz specified for determinism\n",
2126 max);
2127 return -EINVAL;
2128 }
2129
2130 /* Restore default min/max clocks and enable determinism */
2131 ret = smu_v13_0_6_set_gfx_soft_freq_limited_range(smu, min_clk,
2132 max_clk);
2133 if (!ret) {
2134 usleep_range(500, 1000);
2135 ret = smu_cmn_send_smc_msg_with_param(
2136 smu, SMU_MSG_EnableDeterminism, max, NULL);
2137 if (ret) {
2138 dev_err(adev->dev,
2139 "Failed to enable determinism at GFX clock %d MHz\n",
2140 max);
2141 } else {
2142 pstate_table->gfxclk_pstate.curr.min = min_clk;
2143 pstate_table->gfxclk_pstate.curr.max = max;
2144 }
2145 }
2146 }
2147
2148 return ret;
2149 }
2150
smu_v13_0_6_usr_edit_dpm_table(struct smu_context * smu,enum PP_OD_DPM_TABLE_COMMAND type,long input[],uint32_t size)2151 static int smu_v13_0_6_usr_edit_dpm_table(struct smu_context *smu,
2152 enum PP_OD_DPM_TABLE_COMMAND type,
2153 long input[], uint32_t size)
2154 {
2155 struct smu_dpm_context *smu_dpm = &(smu->smu_dpm);
2156 struct smu_13_0_dpm_context *dpm_context = smu_dpm->dpm_context;
2157 struct smu_dpm_table *uclk_table = &dpm_context->dpm_tables.uclk_table;
2158 struct smu_dpm_table *fclk_table = &dpm_context->dpm_tables.fclk_table;
2159 struct smu_umd_pstate_table *pstate_table = &smu->pstate_table;
2160 uint32_t min_clk;
2161 uint32_t max_clk;
2162 int ret = 0;
2163
2164 /* Only allowed in manual or determinism mode */
2165 if ((smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) &&
2166 (smu_dpm->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM))
2167 return -EINVAL;
2168
2169 switch (type) {
2170 case PP_OD_EDIT_SCLK_VDDC_TABLE:
2171 if (size != 2) {
2172 dev_err(smu->adev->dev,
2173 "Input parameter number not correct\n");
2174 return -EINVAL;
2175 }
2176 min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.gfx_table);
2177 max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.gfx_table);
2178 if (input[0] == 0) {
2179 if (input[1] < min_clk) {
2180 dev_warn(
2181 smu->adev->dev,
2182 "Minimum GFX clk (%ld) MHz specified is less than the minimum allowed (%d) MHz\n",
2183 input[1], min_clk);
2184 pstate_table->gfxclk_pstate.custom.min =
2185 pstate_table->gfxclk_pstate.curr.min;
2186 return -EINVAL;
2187 }
2188
2189 pstate_table->gfxclk_pstate.custom.min = input[1];
2190 } else if (input[0] == 1) {
2191 if (input[1] > max_clk) {
2192 dev_warn(
2193 smu->adev->dev,
2194 "Maximum GFX clk (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
2195 input[1], max_clk);
2196 pstate_table->gfxclk_pstate.custom.max =
2197 pstate_table->gfxclk_pstate.curr.max;
2198 return -EINVAL;
2199 }
2200
2201 pstate_table->gfxclk_pstate.custom.max = input[1];
2202 } else {
2203 return -EINVAL;
2204 }
2205 break;
2206 case PP_OD_EDIT_MCLK_VDDC_TABLE:
2207 if (size != 2) {
2208 dev_err(smu->adev->dev,
2209 "Input parameter number not correct\n");
2210 return -EINVAL;
2211 }
2212
2213 if (!smu_cmn_feature_is_enabled(smu,
2214 SMU_FEATURE_DPM_UCLK_BIT)) {
2215 dev_warn(smu->adev->dev,
2216 "UCLK_LIMITS setting not supported!\n");
2217 return -EOPNOTSUPP;
2218 }
2219 max_clk =
2220 SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.uclk_table);
2221 if (input[0] == 0) {
2222 dev_info(smu->adev->dev,
2223 "Setting min UCLK level is not supported");
2224 return -EINVAL;
2225 } else if (input[0] == 1) {
2226 if (input[1] > max_clk) {
2227 dev_warn(
2228 smu->adev->dev,
2229 "Maximum UCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
2230 input[1], max_clk);
2231 pstate_table->uclk_pstate.custom.max =
2232 pstate_table->uclk_pstate.curr.max;
2233 return -EINVAL;
2234 }
2235
2236 pstate_table->uclk_pstate.custom.max = input[1];
2237 }
2238 break;
2239 case PP_OD_EDIT_FCLK_TABLE:
2240 if (size != 2) {
2241 dev_err(smu->adev->dev,
2242 "Input parameter number not correct\n");
2243 return -EINVAL;
2244 }
2245
2246 if (!smu_cmn_feature_is_enabled(smu,
2247 SMU_FEATURE_DPM_FCLK_BIT)) {
2248 dev_warn(smu->adev->dev,
2249 "FCLK limits setting not supported!\n");
2250 return -EOPNOTSUPP;
2251 }
2252
2253 max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.fclk_table);
2254 if (input[0] == 0) {
2255 dev_info(smu->adev->dev,
2256 "Setting min FCLK level is not supported\n");
2257 return -EOPNOTSUPP;
2258 } else if (input[0] == 1) {
2259 if (input[1] > max_clk) {
2260 dev_warn(smu->adev->dev,
2261 "Maximum FCLK (%ld) MHz specified is greater than the maximum allowed (%d) MHz\n",
2262 input[1], max_clk);
2263 pstate_table->fclk_pstate.custom.max =
2264 pstate_table->fclk_pstate.curr.max;
2265 return -EINVAL;
2266 }
2267
2268 pstate_table->fclk_pstate.custom.max = input[1];
2269 } else {
2270 return -EINVAL;
2271 }
2272 break;
2273
2274 case PP_OD_RESTORE_DEFAULT_TABLE:
2275 if (size != 0) {
2276 dev_err(smu->adev->dev,
2277 "Input parameter number not correct\n");
2278 return -EINVAL;
2279 } else {
2280 /* Use the default frequencies for manual and determinism mode */
2281 min_clk = SMU_DPM_TABLE_MIN(
2282 &dpm_context->dpm_tables.gfx_table);
2283 max_clk = SMU_DPM_TABLE_MAX(
2284 &dpm_context->dpm_tables.gfx_table);
2285
2286 ret = smu_v13_0_6_set_soft_freq_limited_range(
2287 smu, SMU_GFXCLK, min_clk, max_clk, false);
2288
2289 if (ret)
2290 return ret;
2291
2292 if (SMU_DPM_TABLE_MAX(uclk_table) !=
2293 pstate_table->uclk_pstate.curr.max) {
2294 min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.uclk_table);
2295 max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.uclk_table);
2296 ret = smu_v13_0_6_set_soft_freq_limited_range(smu,
2297 SMU_UCLK, min_clk,
2298 max_clk, false);
2299 if (ret)
2300 return ret;
2301 }
2302
2303 if (SMU_DPM_TABLE_MAX(fclk_table) !=
2304 pstate_table->fclk_pstate.curr.max) {
2305 max_clk = SMU_DPM_TABLE_MAX(&dpm_context->dpm_tables.fclk_table);
2306 min_clk = SMU_DPM_TABLE_MIN(&dpm_context->dpm_tables.fclk_table);
2307 ret = smu_v13_0_6_set_soft_freq_limited_range(smu,
2308 SMU_FCLK, min_clk,
2309 max_clk, false);
2310 if (ret)
2311 return ret;
2312 }
2313 smu_v13_0_reset_custom_level(smu);
2314 }
2315 break;
2316 case PP_OD_COMMIT_DPM_TABLE:
2317 if (size != 0) {
2318 dev_err(smu->adev->dev,
2319 "Input parameter number not correct\n");
2320 return -EINVAL;
2321 } else {
2322 if (!pstate_table->gfxclk_pstate.custom.min)
2323 pstate_table->gfxclk_pstate.custom.min =
2324 pstate_table->gfxclk_pstate.curr.min;
2325
2326 if (!pstate_table->gfxclk_pstate.custom.max)
2327 pstate_table->gfxclk_pstate.custom.max =
2328 pstate_table->gfxclk_pstate.curr.max;
2329
2330 min_clk = pstate_table->gfxclk_pstate.custom.min;
2331 max_clk = pstate_table->gfxclk_pstate.custom.max;
2332
2333 ret = smu_v13_0_6_set_soft_freq_limited_range(
2334 smu, SMU_GFXCLK, min_clk, max_clk, false);
2335
2336 if (ret)
2337 return ret;
2338
2339 if (pstate_table->fclk_pstate.custom.max) {
2340 min_clk = pstate_table->fclk_pstate.curr.min;
2341 max_clk = pstate_table->fclk_pstate.custom.max;
2342 ret = smu_v13_0_6_set_soft_freq_limited_range(smu,
2343 SMU_FCLK, min_clk,
2344 max_clk, false);
2345 if (ret)
2346 return ret;
2347 }
2348
2349 if (!pstate_table->uclk_pstate.custom.max)
2350 return 0;
2351
2352 min_clk = pstate_table->uclk_pstate.curr.min;
2353 max_clk = pstate_table->uclk_pstate.custom.max;
2354 return smu_v13_0_6_set_soft_freq_limited_range(
2355 smu, SMU_UCLK, min_clk, max_clk, false);
2356 }
2357 break;
2358 default:
2359 return -ENOSYS;
2360 }
2361
2362 return ret;
2363 }
2364
smu_v13_0_6_get_enabled_mask(struct smu_context * smu,struct smu_feature_bits * feature_mask)2365 static int smu_v13_0_6_get_enabled_mask(struct smu_context *smu,
2366 struct smu_feature_bits *feature_mask)
2367 {
2368 int ret;
2369
2370 ret = smu_cmn_get_enabled_mask(smu, feature_mask);
2371
2372 if (ret == -EIO && !smu_v13_0_6_cap_supported(smu, SMU_CAP(DPM))) {
2373 smu_feature_bits_clearall(feature_mask);
2374 ret = 0;
2375 }
2376
2377 return ret;
2378 }
2379
smu_v13_0_6_is_dpm_running(struct smu_context * smu)2380 static bool smu_v13_0_6_is_dpm_running(struct smu_context *smu)
2381 {
2382 int ret;
2383 struct smu_feature_bits feature_enabled;
2384
2385 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12))
2386 return smu_v13_0_12_is_dpm_running(smu);
2387
2388 ret = smu_v13_0_6_get_enabled_mask(smu, &feature_enabled);
2389
2390 if (ret)
2391 return false;
2392
2393 return smu_feature_bits_test_mask(&feature_enabled,
2394 smu_v13_0_6_dpm_features.bits);
2395 }
2396
smu_v13_0_6_request_i2c_xfer(struct smu_context * smu,void * table_data)2397 static int smu_v13_0_6_request_i2c_xfer(struct smu_context *smu,
2398 void *table_data)
2399 {
2400 struct smu_table_context *smu_table = &smu->smu_table;
2401 struct smu_table *table = &smu_table->driver_table;
2402 struct amdgpu_device *adev = smu->adev;
2403 uint32_t table_size;
2404 int ret = 0;
2405
2406 if (!table_data)
2407 return -EINVAL;
2408
2409 table_size = smu_table->tables[SMU_TABLE_I2C_COMMANDS].size;
2410
2411 ret = smu_cmn_vram_cpy(smu, table->cpu_addr, table_data, table_size);
2412 if (ret)
2413 return ret;
2414
2415 /* Flush hdp cache */
2416 amdgpu_hdp_flush(adev, NULL);
2417
2418 return smu_cmn_send_smc_msg(smu, SMU_MSG_RequestI2cTransaction,
2419 NULL);
2420 }
2421
smu_v13_0_6_i2c_xfer(struct i2c_adapter * i2c_adap,struct i2c_msg * msg,int num_msgs)2422 static int smu_v13_0_6_i2c_xfer(struct i2c_adapter *i2c_adap,
2423 struct i2c_msg *msg, int num_msgs)
2424 {
2425 struct amdgpu_smu_i2c_bus *smu_i2c = i2c_get_adapdata(i2c_adap);
2426 struct amdgpu_device *adev = smu_i2c->adev;
2427 struct smu_context *smu = adev->powerplay.pp_handle;
2428 struct smu_table_context *smu_table = &smu->smu_table;
2429 struct smu_table *table = &smu_table->driver_table;
2430 SwI2cRequest_t *req, *res = (SwI2cRequest_t *)table->cpu_addr;
2431 int i, j, r, c;
2432 u16 dir;
2433
2434 if (!adev->pm.dpm_enabled)
2435 return -EBUSY;
2436
2437 req = kzalloc_obj(*req);
2438 if (!req)
2439 return -ENOMEM;
2440
2441 req->I2CcontrollerPort = smu_i2c->port;
2442 req->I2CSpeed = I2C_SPEED_FAST_400K;
2443 req->SlaveAddress = msg[0].addr << 1; /* wants an 8-bit address */
2444 dir = msg[0].flags & I2C_M_RD;
2445
2446 for (c = i = 0; i < num_msgs; i++) {
2447 for (j = 0; j < msg[i].len; j++, c++) {
2448 SwI2cCmd_t *cmd = &req->SwI2cCmds[c];
2449
2450 if (!(msg[i].flags & I2C_M_RD)) {
2451 /* write */
2452 cmd->CmdConfig |= CMDCONFIG_READWRITE_MASK;
2453 cmd->ReadWriteData = msg[i].buf[j];
2454 }
2455
2456 if ((dir ^ msg[i].flags) & I2C_M_RD) {
2457 /* The direction changes.
2458 */
2459 dir = msg[i].flags & I2C_M_RD;
2460 cmd->CmdConfig |= CMDCONFIG_RESTART_MASK;
2461 }
2462
2463 req->NumCmds++;
2464
2465 /*
2466 * Insert STOP if we are at the last byte of either last
2467 * message for the transaction or the client explicitly
2468 * requires a STOP at this particular message.
2469 */
2470 if ((j == msg[i].len - 1) &&
2471 ((i == num_msgs - 1) || (msg[i].flags & I2C_M_STOP))) {
2472 cmd->CmdConfig &= ~CMDCONFIG_RESTART_MASK;
2473 cmd->CmdConfig |= CMDCONFIG_STOP_MASK;
2474 }
2475 }
2476 }
2477 mutex_lock(&adev->pm.mutex);
2478 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2479 if (r) {
2480 /* Retry once, in case of an i2c collision */
2481 r = smu_v13_0_6_request_i2c_xfer(smu, req);
2482 if (r)
2483 goto fail;
2484 }
2485
2486 for (c = i = 0; i < num_msgs; i++) {
2487 if (!(msg[i].flags & I2C_M_RD)) {
2488 c += msg[i].len;
2489 continue;
2490 }
2491 for (j = 0; j < msg[i].len; j++, c++) {
2492 SwI2cCmd_t *cmd = &res->SwI2cCmds[c];
2493
2494 msg[i].buf[j] = cmd->ReadWriteData;
2495 }
2496 }
2497 r = num_msgs;
2498 fail:
2499 mutex_unlock(&adev->pm.mutex);
2500 kfree(req);
2501 return r;
2502 }
2503
smu_v13_0_6_i2c_func(struct i2c_adapter * adap)2504 static u32 smu_v13_0_6_i2c_func(struct i2c_adapter *adap)
2505 {
2506 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
2507 }
2508
2509 static const struct i2c_algorithm smu_v13_0_6_i2c_algo = {
2510 .master_xfer = smu_v13_0_6_i2c_xfer,
2511 .functionality = smu_v13_0_6_i2c_func,
2512 };
2513
2514 static const struct i2c_adapter_quirks smu_v13_0_6_i2c_control_quirks = {
2515 .flags = I2C_AQ_COMB | I2C_AQ_COMB_SAME_ADDR | I2C_AQ_NO_ZERO_LEN,
2516 .max_read_len = MAX_SW_I2C_COMMANDS,
2517 .max_write_len = MAX_SW_I2C_COMMANDS,
2518 .max_comb_1st_msg_len = 2,
2519 .max_comb_2nd_msg_len = MAX_SW_I2C_COMMANDS - 2,
2520 };
2521
smu_v13_0_6_i2c_control_init(struct smu_context * smu)2522 static int smu_v13_0_6_i2c_control_init(struct smu_context *smu)
2523 {
2524 struct amdgpu_device *adev = smu->adev;
2525 int res, i;
2526
2527 for (i = 0; i < MAX_SMU_I2C_BUSES; i++) {
2528 struct amdgpu_smu_i2c_bus *smu_i2c = &adev->pm.smu_i2c[i];
2529 struct i2c_adapter *control = &smu_i2c->adapter;
2530
2531 smu_i2c->adev = adev;
2532 smu_i2c->port = i;
2533 mutex_init(&smu_i2c->mutex);
2534 control->owner = THIS_MODULE;
2535 control->dev.parent = &adev->pdev->dev;
2536 control->algo = &smu_v13_0_6_i2c_algo;
2537 snprintf(control->name, sizeof(control->name), "AMDGPU SMU %d", i);
2538 control->quirks = &smu_v13_0_6_i2c_control_quirks;
2539 i2c_set_adapdata(control, smu_i2c);
2540
2541 res = devm_i2c_add_adapter(adev->dev, control);
2542 if (res) {
2543 DRM_ERROR("Failed to register hw i2c, err: %d\n", res);
2544 return res;
2545 }
2546 }
2547
2548 adev->pm.ras_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2549 adev->pm.fru_eeprom_i2c_bus = &adev->pm.smu_i2c[0].adapter;
2550
2551 return 0;
2552 }
2553
smu_v13_0_6_i2c_control_fini(struct smu_context * smu)2554 static void smu_v13_0_6_i2c_control_fini(struct smu_context *smu)
2555 {
2556 struct amdgpu_device *adev = smu->adev;
2557
2558 adev->pm.ras_eeprom_i2c_bus = NULL;
2559 adev->pm.fru_eeprom_i2c_bus = NULL;
2560 }
2561
smu_v13_0_6_get_unique_id(struct smu_context * smu)2562 static void smu_v13_0_6_get_unique_id(struct smu_context *smu)
2563 {
2564 struct amdgpu_device *adev = smu->adev;
2565 struct smu_table_context *smu_table = &smu->smu_table;
2566 struct PPTable_t *pptable =
2567 (struct PPTable_t *)smu_table->driver_pptable;
2568
2569 adev->unique_id = pptable->PublicSerialNumber_AID;
2570 }
2571
smu_v13_0_6_get_bamaco_support(struct smu_context * smu)2572 static int smu_v13_0_6_get_bamaco_support(struct smu_context *smu)
2573 {
2574 /* smu_13_0_6 does not support baco */
2575
2576 return 0;
2577 }
2578
2579 static const char *const throttling_logging_label[] = {
2580 [THROTTLER_PROCHOT_BIT] = "Prochot",
2581 [THROTTLER_PPT_BIT] = "PPT",
2582 [THROTTLER_THERMAL_SOCKET_BIT] = "SOC",
2583 [THROTTLER_THERMAL_VR_BIT] = "VR",
2584 [THROTTLER_THERMAL_HBM_BIT] = "HBM"
2585 };
2586
smu_v13_0_6_log_thermal_throttling_event(struct smu_context * smu)2587 static void smu_v13_0_6_log_thermal_throttling_event(struct smu_context *smu)
2588 {
2589 int throttler_idx, throttling_events = 0, buf_idx = 0;
2590 struct amdgpu_device *adev = smu->adev;
2591 uint32_t throttler_status;
2592 char log_buf[256];
2593
2594 throttler_status = smu_v13_0_6_get_throttler_status(smu);
2595 if (!throttler_status)
2596 return;
2597
2598 memset(log_buf, 0, sizeof(log_buf));
2599 for (throttler_idx = 0;
2600 throttler_idx < ARRAY_SIZE(throttling_logging_label);
2601 throttler_idx++) {
2602 if (throttler_status & (1U << throttler_idx)) {
2603 throttling_events++;
2604 buf_idx += snprintf(
2605 log_buf + buf_idx, sizeof(log_buf) - buf_idx,
2606 "%s%s", throttling_events > 1 ? " and " : "",
2607 throttling_logging_label[throttler_idx]);
2608 if (buf_idx >= sizeof(log_buf)) {
2609 dev_err(adev->dev, "buffer overflow!\n");
2610 log_buf[sizeof(log_buf) - 1] = '\0';
2611 break;
2612 }
2613 }
2614 }
2615
2616 dev_warn(adev->dev,
2617 "WARN: GPU is throttled, expect performance decrease. %s.\n",
2618 log_buf);
2619 kgd2kfd_smi_event_throttle(
2620 smu->adev->kfd.dev,
2621 smu_cmn_get_indep_throttler_status(throttler_status,
2622 smu_v13_0_6_throttler_map));
2623 }
2624
2625 static int
smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context * smu)2626 smu_v13_0_6_get_current_pcie_link_width_level(struct smu_context *smu)
2627 {
2628 struct amdgpu_device *adev = smu->adev;
2629
2630 return REG_GET_FIELD(RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL),
2631 PCIE_LC_LINK_WIDTH_CNTL, LC_LINK_WIDTH_RD);
2632 }
2633
smu_v13_0_6_get_current_pcie_link_speed(struct smu_context * smu)2634 static int smu_v13_0_6_get_current_pcie_link_speed(struct smu_context *smu)
2635 {
2636 struct amdgpu_device *adev = smu->adev;
2637 uint32_t speed_level;
2638 uint32_t esm_ctrl;
2639
2640 /* TODO: confirm this on real target */
2641 esm_ctrl = RREG32_PCIE(smnPCIE_ESM_CTRL);
2642 if ((esm_ctrl >> 15) & 0x1)
2643 return (((esm_ctrl >> 8) & 0x7F) + 128);
2644
2645 speed_level = (RREG32_PCIE(smnPCIE_LC_SPEED_CNTL) &
2646 PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE_MASK)
2647 >> PCIE_LC_SPEED_CNTL__LC_CURRENT_DATA_RATE__SHIFT;
2648 if (speed_level > LINK_SPEED_MAX)
2649 speed_level = 0;
2650
2651 return pcie_gen_to_speed(speed_level + 1);
2652 }
2653
smu_v13_0_6_get_xcp_metrics(struct smu_context * smu,int xcp_id,void * table)2654 static ssize_t smu_v13_0_6_get_xcp_metrics(struct smu_context *smu, int xcp_id,
2655 void *table)
2656 {
2657 const u8 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3;
2658 int version = smu_v13_0_6_get_metrics_version(smu);
2659 struct smu_v13_0_6_partition_metrics *xcp_metrics;
2660 struct smu_table_context *smu_table = &smu->smu_table;
2661 struct amdgpu_device *adev = smu->adev;
2662 int ret, inst, i, j, k, idx;
2663 MetricsTableV0_t *metrics_v0;
2664 MetricsTableV1_t *metrics_v1;
2665 MetricsTableV2_t *metrics_v2;
2666 struct amdgpu_xcp *xcp;
2667 u32 inst_mask;
2668 bool per_inst;
2669
2670 if (!table)
2671 return sizeof(*xcp_metrics);
2672
2673 for_each_xcp(adev->xcp_mgr, xcp, i) {
2674 if (xcp->id == xcp_id)
2675 break;
2676 }
2677 if (i == adev->xcp_mgr->num_xcps)
2678 return -EINVAL;
2679
2680 xcp_metrics = (struct smu_v13_0_6_partition_metrics *)table;
2681 smu_v13_0_6_partition_metrics_init(xcp_metrics, 1, 1);
2682
2683 ret = smu_v13_0_6_get_metrics_table(smu, NULL, false);
2684 if (ret)
2685 return ret;
2686
2687 metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
2688
2689 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) ==
2690 IP_VERSION(13, 0, 12) &&
2691 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS)))
2692 return smu_v13_0_12_get_xcp_metrics(smu, xcp, table,
2693 metrics_v0);
2694
2695 metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
2696 metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
2697
2698 per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS));
2699
2700 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_VCN, &inst_mask);
2701 idx = 0;
2702 for_each_inst(k, inst_mask) {
2703 /* Both JPEG and VCN has same instances */
2704 inst = GET_INST(VCN, k);
2705
2706 for (j = 0; j < num_jpeg_rings; ++j) {
2707 xcp_metrics->jpeg_busy[(idx * num_jpeg_rings) + j] =
2708 SMUQ10_ROUND(GET_METRIC_FIELD(
2709 JpegBusy,
2710 version)[(inst * num_jpeg_rings) + j]);
2711 }
2712 xcp_metrics->vcn_busy[idx] =
2713 SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
2714
2715 xcp_metrics->current_vclk0[idx] = SMUQ10_ROUND(
2716 GET_METRIC_FIELD(VclkFrequency, version)[inst]);
2717 xcp_metrics->current_dclk0[idx] = SMUQ10_ROUND(
2718 GET_METRIC_FIELD(DclkFrequency, version)[inst]);
2719 xcp_metrics->current_socclk[idx] = SMUQ10_ROUND(
2720 GET_METRIC_FIELD(SocclkFrequency, version)[inst]);
2721
2722 idx++;
2723 }
2724
2725 xcp_metrics->current_uclk =
2726 SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
2727
2728 if (per_inst) {
2729 amdgpu_xcp_get_inst_details(xcp, AMDGPU_XCP_GFX, &inst_mask);
2730 idx = 0;
2731 for_each_inst(k, inst_mask) {
2732 inst = GET_INST(GC, k);
2733 xcp_metrics->current_gfxclk[idx] =
2734 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency,
2735 version)[inst]);
2736
2737 xcp_metrics->gfx_busy_inst[idx] = SMUQ10_ROUND(
2738 GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
2739 xcp_metrics->gfx_busy_acc[idx] = SMUQ10_ROUND(
2740 GET_GPU_METRIC_FIELD(GfxBusyAcc,
2741 version)[inst]);
2742 if (smu_v13_0_6_cap_supported(
2743 smu, SMU_CAP(HST_LIMIT_METRICS))) {
2744 xcp_metrics->gfx_below_host_limit_ppt_acc
2745 [idx] = SMUQ10_ROUND(
2746 metrics_v0->GfxclkBelowHostLimitPptAcc
2747 [inst]);
2748 xcp_metrics->gfx_below_host_limit_thm_acc
2749 [idx] = SMUQ10_ROUND(
2750 metrics_v0->GfxclkBelowHostLimitThmAcc
2751 [inst]);
2752 xcp_metrics->gfx_low_utilization_acc
2753 [idx] = SMUQ10_ROUND(
2754 metrics_v0
2755 ->GfxclkLowUtilizationAcc[inst]);
2756 xcp_metrics->gfx_below_host_limit_total_acc
2757 [idx] = SMUQ10_ROUND(
2758 metrics_v0->GfxclkBelowHostLimitTotalAcc
2759 [inst]);
2760 }
2761 idx++;
2762 }
2763 }
2764 xcp_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, version);
2765 xcp_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version);
2766
2767 return sizeof(*xcp_metrics);
2768 }
2769
smu_v13_0_6_get_gpu_metrics(struct smu_context * smu,void ** table)2770 static ssize_t smu_v13_0_6_get_gpu_metrics(struct smu_context *smu, void **table)
2771 {
2772 struct smu_v13_0_6_gpu_metrics *gpu_metrics;
2773 int version = smu_v13_0_6_get_metrics_version(smu);
2774 struct smu_table_context *smu_table = &smu->smu_table;
2775 struct amdgpu_device *adev = smu->adev;
2776 int ret = 0, xcc_id, inst, i, j;
2777 MetricsTableV0_t *metrics_v0;
2778 MetricsTableV1_t *metrics_v1;
2779 MetricsTableV2_t *metrics_v2;
2780 u16 link_width_level;
2781 u8 num_jpeg_rings;
2782 bool per_inst;
2783
2784 ret = smu_v13_0_6_get_metrics_table(smu, NULL, false);
2785 if (ret)
2786 return ret;
2787
2788 metrics_v0 = (MetricsTableV0_t *)smu_table->metrics_table;
2789 gpu_metrics = (struct smu_v13_0_6_gpu_metrics *)smu_driver_table_ptr(
2790 smu, SMU_DRIVER_TABLE_GPU_METRICS);
2791
2792 if (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12) &&
2793 smu_v13_0_6_cap_supported(smu, SMU_CAP(STATIC_METRICS))) {
2794 smu_v13_0_12_get_gpu_metrics(smu, table, metrics_v0,
2795 gpu_metrics);
2796 goto fill;
2797 }
2798
2799 metrics_v1 = (MetricsTableV1_t *)smu_table->metrics_table;
2800 metrics_v2 = (MetricsTableV2_t *)smu_table->metrics_table;
2801
2802 gpu_metrics->temperature_hotspot =
2803 SMUQ10_ROUND(GET_METRIC_FIELD(MaxSocketTemperature, version));
2804 /* Individual HBM stack temperature is not reported */
2805 gpu_metrics->temperature_mem =
2806 SMUQ10_ROUND(GET_METRIC_FIELD(MaxHbmTemperature, version));
2807 /* Reports max temperature of all voltage rails */
2808 gpu_metrics->temperature_vrsoc =
2809 SMUQ10_ROUND(GET_METRIC_FIELD(MaxVrTemperature, version));
2810
2811 gpu_metrics->average_gfx_activity =
2812 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusy, version));
2813 gpu_metrics->average_umc_activity =
2814 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilization, version));
2815
2816 gpu_metrics->mem_max_bandwidth =
2817 SMUQ10_ROUND(GET_METRIC_FIELD(MaxDramBandwidth, version));
2818
2819 gpu_metrics->curr_socket_power =
2820 SMUQ10_ROUND(GET_METRIC_FIELD(SocketPower, version));
2821 /* Energy counter reported in 15.259uJ (2^-16) units */
2822 gpu_metrics->energy_accumulator = GET_METRIC_FIELD(SocketEnergyAcc, version);
2823
2824 for (i = 0; i < MAX_GFX_CLKS; i++) {
2825 xcc_id = GET_INST(GC, i);
2826 if (xcc_id >= 0)
2827 gpu_metrics->current_gfxclk[i] =
2828 SMUQ10_ROUND(GET_METRIC_FIELD(GfxclkFrequency, version)[xcc_id]);
2829
2830 if (i < MAX_CLKS) {
2831 gpu_metrics->current_socclk[i] =
2832 SMUQ10_ROUND(GET_METRIC_FIELD(SocclkFrequency, version)[i]);
2833 inst = GET_INST(VCN, i);
2834 if (inst >= 0) {
2835 gpu_metrics->current_vclk0[i] =
2836 SMUQ10_ROUND(GET_METRIC_FIELD(VclkFrequency,
2837 version)[inst]);
2838 gpu_metrics->current_dclk0[i] =
2839 SMUQ10_ROUND(GET_METRIC_FIELD(DclkFrequency,
2840 version)[inst]);
2841 }
2842 }
2843 }
2844
2845 gpu_metrics->current_uclk = SMUQ10_ROUND(GET_METRIC_FIELD(UclkFrequency, version));
2846
2847 /* Total accumulated cycle counter */
2848 gpu_metrics->accumulation_counter = GET_METRIC_FIELD(AccumulationCounter, version);
2849
2850 /* Accumulated throttler residencies */
2851 gpu_metrics->prochot_residency_acc = GET_METRIC_FIELD(ProchotResidencyAcc, version);
2852 gpu_metrics->ppt_residency_acc = GET_METRIC_FIELD(PptResidencyAcc, version);
2853 gpu_metrics->socket_thm_residency_acc = GET_METRIC_FIELD(SocketThmResidencyAcc, version);
2854 gpu_metrics->vr_thm_residency_acc = GET_METRIC_FIELD(VrThmResidencyAcc, version);
2855 gpu_metrics->hbm_thm_residency_acc =
2856 GET_METRIC_FIELD(HbmThmResidencyAcc, version);
2857
2858 /* Clock Lock Status. Each bit corresponds to each GFXCLK instance */
2859 gpu_metrics->gfxclk_lock_status = GET_METRIC_FIELD(GfxLockXCDMak,
2860 version) >> GET_INST(GC, 0);
2861
2862 if (!(adev->flags & AMD_IS_APU)) {
2863 /*Check smu version, PCIE link speed and width will be reported from pmfw metric
2864 * table for both pf & one vf for smu version 85.99.0 or higher else report only
2865 * for pf from registers
2866 */
2867 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(PCIE_METRICS))) {
2868 gpu_metrics->pcie_link_width = GET_GPU_METRIC_FIELD(PCIeLinkWidth, version);
2869 gpu_metrics->pcie_link_speed =
2870 pcie_gen_to_speed(GET_GPU_METRIC_FIELD(PCIeLinkSpeed, version));
2871 } else if (!amdgpu_sriov_vf(adev)) {
2872 link_width_level = smu_v13_0_6_get_current_pcie_link_width_level(smu);
2873 if (link_width_level > MAX_LINK_WIDTH)
2874 link_width_level = 0;
2875
2876 gpu_metrics->pcie_link_width =
2877 DECODE_LANE_WIDTH(link_width_level);
2878 gpu_metrics->pcie_link_speed =
2879 smu_v13_0_6_get_current_pcie_link_speed(smu);
2880 }
2881
2882 gpu_metrics->pcie_bandwidth_acc =
2883 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(PcieBandwidthAcc, version)[0]);
2884 gpu_metrics->pcie_bandwidth_inst =
2885 SMUQ10_ROUND(GET_GPU_METRIC_FIELD(PcieBandwidth, version)[0]);
2886 gpu_metrics->pcie_l0_to_recov_count_acc =
2887 GET_GPU_METRIC_FIELD(PCIeL0ToRecoveryCountAcc, version);
2888 gpu_metrics->pcie_replay_count_acc =
2889 GET_GPU_METRIC_FIELD(PCIenReplayAAcc, version);
2890 gpu_metrics->pcie_replay_rover_count_acc =
2891 GET_GPU_METRIC_FIELD(PCIenReplayARolloverCountAcc, version);
2892 gpu_metrics->pcie_nak_sent_count_acc =
2893 GET_GPU_METRIC_FIELD(PCIeNAKSentCountAcc, version);
2894 gpu_metrics->pcie_nak_rcvd_count_acc =
2895 GET_GPU_METRIC_FIELD(PCIeNAKReceivedCountAcc, version);
2896 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(OTHER_END_METRICS)))
2897 gpu_metrics->pcie_lc_perf_other_end_recovery =
2898 GET_GPU_METRIC_FIELD(PCIeOtherEndRecoveryAcc, version);
2899
2900 }
2901
2902 gpu_metrics->system_clock_counter = ktime_get_boottime_ns();
2903
2904 gpu_metrics->gfx_activity_acc =
2905 SMUQ10_ROUND(GET_METRIC_FIELD(SocketGfxBusyAcc, version));
2906 gpu_metrics->mem_activity_acc =
2907 SMUQ10_ROUND(GET_METRIC_FIELD(DramBandwidthUtilizationAcc, version));
2908
2909 for (i = 0; i < NUM_XGMI_LINKS; i++) {
2910 j = amdgpu_xgmi_get_ext_link(adev, i);
2911 if (j < 0 || j >= NUM_XGMI_LINKS)
2912 continue;
2913 gpu_metrics->xgmi_read_data_acc[j] = SMUQ10_ROUND(
2914 GET_METRIC_FIELD(XgmiReadDataSizeAcc, version)[i]);
2915 gpu_metrics->xgmi_write_data_acc[j] = SMUQ10_ROUND(
2916 GET_METRIC_FIELD(XgmiWriteDataSizeAcc, version)[i]);
2917 ret = amdgpu_get_xgmi_link_status(adev, i);
2918 if (ret >= 0)
2919 gpu_metrics->xgmi_link_status[j] = ret;
2920 }
2921
2922 per_inst = smu_v13_0_6_cap_supported(smu, SMU_CAP(PER_INST_METRICS));
2923
2924 num_jpeg_rings = AMDGPU_MAX_JPEG_RINGS_4_0_3;
2925 for (i = 0; i < adev->jpeg.num_jpeg_inst; ++i) {
2926 inst = GET_INST(JPEG, i);
2927 for (j = 0; j < num_jpeg_rings; ++j)
2928 gpu_metrics->jpeg_busy[(i * num_jpeg_rings) + j] =
2929 SMUQ10_ROUND(GET_METRIC_FIELD(
2930 JpegBusy,
2931 version)[(inst * num_jpeg_rings) + j]);
2932 }
2933 for (i = 0; i < adev->vcn.num_vcn_inst; ++i) {
2934 inst = GET_INST(VCN, i);
2935 gpu_metrics->vcn_busy[i] =
2936 SMUQ10_ROUND(GET_METRIC_FIELD(VcnBusy, version)[inst]);
2937 }
2938
2939 if (per_inst) {
2940 for (i = 0; i < NUM_XCC(adev->gfx.xcc_mask); ++i) {
2941 inst = GET_INST(GC, i);
2942 gpu_metrics->gfx_busy_inst[i] = SMUQ10_ROUND(
2943 GET_GPU_METRIC_FIELD(GfxBusy, version)[inst]);
2944 gpu_metrics->gfx_busy_acc[i] = SMUQ10_ROUND(
2945 GET_GPU_METRIC_FIELD(GfxBusyAcc,
2946 version)[inst]);
2947 if (smu_v13_0_6_cap_supported(
2948 smu, SMU_CAP(HST_LIMIT_METRICS))) {
2949 gpu_metrics->gfx_below_host_limit_ppt_acc
2950 [i] = SMUQ10_ROUND(
2951 metrics_v0->GfxclkBelowHostLimitPptAcc
2952 [inst]);
2953 gpu_metrics->gfx_below_host_limit_thm_acc
2954 [i] = SMUQ10_ROUND(
2955 metrics_v0->GfxclkBelowHostLimitThmAcc
2956 [inst]);
2957 gpu_metrics->gfx_low_utilization_acc
2958 [i] = SMUQ10_ROUND(
2959 metrics_v0
2960 ->GfxclkLowUtilizationAcc[inst]);
2961 gpu_metrics->gfx_below_host_limit_total_acc
2962 [i] = SMUQ10_ROUND(
2963 metrics_v0->GfxclkBelowHostLimitTotalAcc
2964 [inst]);
2965 }
2966 }
2967 }
2968
2969 gpu_metrics->xgmi_link_width = GET_METRIC_FIELD(XgmiWidth, version);
2970 gpu_metrics->xgmi_link_speed = GET_METRIC_FIELD(XgmiBitrate, version);
2971
2972 gpu_metrics->firmware_timestamp = GET_METRIC_FIELD(Timestamp, version);
2973
2974 fill:
2975 *table = gpu_metrics;
2976
2977 smu_driver_table_update_cache_time(smu, SMU_DRIVER_TABLE_GPU_METRICS);
2978
2979 return sizeof(*gpu_metrics);
2980 }
2981
smu_v13_0_6_restore_pci_config(struct smu_context * smu)2982 static void smu_v13_0_6_restore_pci_config(struct smu_context *smu)
2983 {
2984 struct amdgpu_device *adev = smu->adev;
2985 int i;
2986
2987 for (i = 0; i < 16; i++)
2988 pci_write_config_dword(adev->pdev, i * 4,
2989 adev->pdev->saved_config_space[i]);
2990 pci_restore_msi_state(adev->pdev);
2991 }
2992
smu_v13_0_6_mode2_reset(struct smu_context * smu)2993 static int smu_v13_0_6_mode2_reset(struct smu_context *smu)
2994 {
2995 struct smu_msg_ctl *ctl = &smu->msg_ctl;
2996 struct amdgpu_device *adev = smu->adev;
2997 int ret = 0;
2998 int timeout = 10;
2999
3000 mutex_lock(&ctl->lock);
3001
3002 ret = smu_msg_send_async_locked(ctl, SMU_MSG_GfxDeviceDriverReset,
3003 SMU_RESET_MODE_2);
3004 if (ret)
3005 goto out;
3006
3007 /* Reset takes a bit longer, wait for 200ms. */
3008 msleep(200);
3009
3010 dev_dbg(adev->dev, "restore config space...\n");
3011 /* Restore the config space saved during init */
3012 amdgpu_device_load_pci_state(adev->pdev);
3013
3014 /* Certain platforms have switches which assign virtual BAR values to
3015 * devices. OS uses the virtual BAR values and device behind the switch
3016 * is assgined another BAR value. When device's config space registers
3017 * are queried, switch returns the virtual BAR values. When mode-2 reset
3018 * is performed, switch is unaware of it, and will continue to return
3019 * the same virtual values to the OS.This affects
3020 * pci_restore_config_space() API as it doesn't write the value saved if
3021 * the current value read from config space is the same as what is
3022 * saved. As a workaround, make sure the config space is restored
3023 * always.
3024 */
3025 if (!(adev->flags & AMD_IS_APU))
3026 smu_v13_0_6_restore_pci_config(smu);
3027
3028 dev_dbg(adev->dev, "wait for reset ack\n");
3029 do {
3030 ret = smu_msg_wait_response(ctl, 0);
3031 /* Wait a bit more time for getting ACK */
3032 if (ret == -ETIME) {
3033 --timeout;
3034 usleep_range(500, 1000);
3035 continue;
3036 }
3037
3038 if (ret)
3039 goto out;
3040
3041 } while (ret == -ETIME && timeout);
3042
3043 out:
3044 mutex_unlock(&ctl->lock);
3045
3046 if (ret)
3047 dev_err(adev->dev, "failed to send mode2 reset, error code %d",
3048 ret);
3049
3050 return ret;
3051 }
3052
smu_v13_0_6_get_thermal_temperature_range(struct smu_context * smu,struct smu_temperature_range * range)3053 static int smu_v13_0_6_get_thermal_temperature_range(struct smu_context *smu,
3054 struct smu_temperature_range *range)
3055 {
3056 struct amdgpu_device *adev = smu->adev;
3057 u32 aid_temp, xcd_temp, max_temp;
3058 u32 ccd_temp = 0;
3059 int ret;
3060
3061 if (amdgpu_sriov_vf(smu->adev))
3062 return 0;
3063
3064 if (!range)
3065 return -EINVAL;
3066
3067 /*Check smu version, GetCtfLimit message only supported for smu version 85.69 or higher */
3068 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(CTF_LIMIT)))
3069 return 0;
3070
3071 /* Get SOC Max operating temperature */
3072 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
3073 PPSMC_AID_THM_TYPE, &aid_temp);
3074 if (ret)
3075 goto failed;
3076 if (adev->flags & AMD_IS_APU) {
3077 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
3078 PPSMC_CCD_THM_TYPE, &ccd_temp);
3079 if (ret)
3080 goto failed;
3081 }
3082 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
3083 PPSMC_XCD_THM_TYPE, &xcd_temp);
3084 if (ret)
3085 goto failed;
3086 range->hotspot_emergency_max = max3(aid_temp, xcd_temp, ccd_temp) *
3087 SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3088
3089 /* Get HBM Max operating temperature */
3090 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetCTFLimit,
3091 PPSMC_HBM_THM_TYPE, &max_temp);
3092 if (ret)
3093 goto failed;
3094 range->mem_emergency_max =
3095 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3096
3097 /* Get SOC thermal throttle limit */
3098 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
3099 PPSMC_THROTTLING_LIMIT_TYPE_SOCKET,
3100 &max_temp);
3101 if (ret)
3102 goto failed;
3103 range->hotspot_crit_max =
3104 max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3105
3106 /* Get HBM thermal throttle limit */
3107 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GetThermalLimit,
3108 PPSMC_THROTTLING_LIMIT_TYPE_HBM,
3109 &max_temp);
3110 if (ret)
3111 goto failed;
3112
3113 range->mem_crit_max = max_temp * SMU_TEMPERATURE_UNITS_PER_CENTIGRADES;
3114
3115 failed:
3116 return ret;
3117 }
3118
smu_v13_0_6_mode1_reset(struct smu_context * smu)3119 static int smu_v13_0_6_mode1_reset(struct smu_context *smu)
3120 {
3121 struct amdgpu_device *adev = smu->adev;
3122 u32 fatal_err, param;
3123 int ret = 0;
3124
3125 fatal_err = 0;
3126 param = SMU_RESET_MODE_1;
3127
3128 /* fatal error triggered by ras, PMFW supports the flag */
3129 if (amdgpu_ras_get_fed_status(adev))
3130 fatal_err = 1;
3131
3132 param |= (fatal_err << 16);
3133 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
3134 param, NULL);
3135
3136 if (!ret)
3137 msleep(SMU13_MODE1_RESET_WAIT_TIME_IN_MS);
3138
3139 return ret;
3140 }
3141
smu_v13_0_6_link_reset(struct smu_context * smu)3142 static int smu_v13_0_6_link_reset(struct smu_context *smu)
3143 {
3144 int ret = 0;
3145
3146 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
3147 SMU_RESET_MODE_4, NULL);
3148 return ret;
3149 }
3150
smu_v13_0_6_is_mode1_reset_supported(struct smu_context * smu)3151 static bool smu_v13_0_6_is_mode1_reset_supported(struct smu_context *smu)
3152 {
3153 return true;
3154 }
3155
smu_v13_0_6_is_link_reset_supported(struct smu_context * smu)3156 static inline bool smu_v13_0_6_is_link_reset_supported(struct smu_context *smu)
3157 {
3158 struct amdgpu_device *adev = smu->adev;
3159 int var = (adev->pdev->device & 0xF);
3160
3161 if (var == 0x0 || var == 0x1 || var == 0x3)
3162 return true;
3163
3164 return false;
3165 }
3166
smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context * smu,uint32_t size)3167 static int smu_v13_0_6_smu_send_hbm_bad_page_num(struct smu_context *smu,
3168 uint32_t size)
3169 {
3170 int ret = 0;
3171
3172 /* message SMU to update the bad page number on SMUBUS */
3173 ret = smu_cmn_send_smc_msg_with_param(
3174 smu, SMU_MSG_SetNumBadHbmPagesRetired, size, NULL);
3175 if (ret)
3176 dev_err(smu->adev->dev,
3177 "[%s] failed to message SMU to update HBM bad pages number\n",
3178 __func__);
3179
3180 return ret;
3181 }
3182
smu_v13_0_6_send_rma_reason(struct smu_context * smu)3183 static int smu_v13_0_6_send_rma_reason(struct smu_context *smu)
3184 {
3185 int ret;
3186
3187 /* NOTE: the message is only valid on dGPU with pmfw 85.90.0 and above */
3188 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(RMA_MSG)))
3189 return 0;
3190
3191 ret = smu_cmn_send_smc_msg(smu, SMU_MSG_RmaDueToBadPageThreshold, NULL);
3192 if (ret)
3193 dev_err(smu->adev->dev,
3194 "[%s] failed to send BadPageThreshold event to SMU\n",
3195 __func__);
3196
3197 return ret;
3198 }
3199
3200 /**
3201 * smu_v13_0_6_reset_sdma_is_supported - Check if SDMA reset is supported
3202 * @smu: smu_context pointer
3203 *
3204 * This function checks if the SMU supports resetting the SDMA engine.
3205 * It returns false if the capability is not supported.
3206 */
smu_v13_0_6_reset_sdma_is_supported(struct smu_context * smu)3207 static bool smu_v13_0_6_reset_sdma_is_supported(struct smu_context *smu)
3208 {
3209 bool ret = true;
3210
3211 if (!smu_v13_0_6_cap_supported(smu, SMU_CAP(SDMA_RESET))) {
3212 dev_info(smu->adev->dev,
3213 "SDMA reset capability is not supported\n");
3214 ret = false;
3215 }
3216
3217 return ret;
3218 }
3219
smu_v13_0_6_reset_sdma(struct smu_context * smu,uint32_t inst_mask)3220 static int smu_v13_0_6_reset_sdma(struct smu_context *smu, uint32_t inst_mask)
3221 {
3222 int ret = 0;
3223
3224 if (!smu_v13_0_6_reset_sdma_is_supported(smu))
3225 return -EOPNOTSUPP;
3226
3227 ret = smu_cmn_send_smc_msg_with_param(smu,
3228 SMU_MSG_ResetSDMA, inst_mask, NULL);
3229 if (ret)
3230 dev_err(smu->adev->dev,
3231 "failed to send ResetSDMA event with mask 0x%x\n",
3232 inst_mask);
3233
3234 return ret;
3235 }
3236
smu_v13_0_6_reset_vcn_is_supported(struct smu_context * smu)3237 static bool smu_v13_0_6_reset_vcn_is_supported(struct smu_context *smu)
3238 {
3239 return smu_v13_0_6_cap_supported(smu, SMU_CAP(VCN_RESET));
3240 }
3241
smu_v13_0_6_reset_vcn(struct smu_context * smu,uint32_t inst_mask)3242 static int smu_v13_0_6_reset_vcn(struct smu_context *smu, uint32_t inst_mask)
3243 {
3244 int ret = 0;
3245
3246 ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_ResetVCN, inst_mask, NULL);
3247 if (ret)
3248 dev_err(smu->adev->dev,
3249 "failed to send ResetVCN event with mask 0x%x\n",
3250 inst_mask);
3251 return ret;
3252 }
3253
smu_v13_0_6_ras_send_msg(struct smu_context * smu,enum smu_message_type msg,uint32_t param,uint32_t * read_arg)3254 static int smu_v13_0_6_ras_send_msg(struct smu_context *smu, enum smu_message_type msg, uint32_t param, uint32_t *read_arg)
3255 {
3256 struct amdgpu_device *adev = smu->adev;
3257 int ret;
3258
3259 if (amdgpu_sriov_vf(adev))
3260 return -EOPNOTSUPP;
3261
3262 switch (msg) {
3263 case SMU_MSG_QueryValidMcaCount:
3264 case SMU_MSG_QueryValidMcaCeCount:
3265 case SMU_MSG_McaBankDumpDW:
3266 case SMU_MSG_McaBankCeDumpDW:
3267 case SMU_MSG_ClearMcaOnRead:
3268 case SMU_MSG_GetRASTableVersion:
3269 case SMU_MSG_GetBadPageCount:
3270 case SMU_MSG_GetBadPageMcaAddr:
3271 case SMU_MSG_SetTimestamp:
3272 case SMU_MSG_GetTimestamp:
3273 case SMU_MSG_GetBadPageIpid:
3274 case SMU_MSG_EraseRasTable:
3275 ret = smu_cmn_send_smc_msg_with_param(smu, msg, param, read_arg);
3276 break;
3277 default:
3278 ret = -EPERM;
3279 }
3280
3281 return ret;
3282 }
3283
smu_v13_0_6_post_init(struct smu_context * smu)3284 static int smu_v13_0_6_post_init(struct smu_context *smu)
3285 {
3286 if (smu_v13_0_6_is_link_reset_supported(smu))
3287 smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__LINK_RESET);
3288
3289 if (smu_v13_0_6_reset_sdma_is_supported(smu))
3290 smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__SDMA_RESET);
3291
3292 if (smu_v13_0_6_reset_vcn_is_supported(smu))
3293 smu_feature_cap_set(smu, SMU_FEATURE_CAP_ID__VCN_RESET);
3294
3295 return 0;
3296 }
3297
mca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)3298 static int mca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
3299 {
3300 struct smu_context *smu = adev->powerplay.pp_handle;
3301
3302 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
3303 }
3304
smu_v13_0_6_get_valid_mca_count(struct smu_context * smu,enum amdgpu_mca_error_type type,uint32_t * count)3305 static int smu_v13_0_6_get_valid_mca_count(struct smu_context *smu, enum amdgpu_mca_error_type type, uint32_t *count)
3306 {
3307 uint32_t msg;
3308 int ret;
3309
3310 if (!count)
3311 return -EINVAL;
3312
3313 switch (type) {
3314 case AMDGPU_MCA_ERROR_TYPE_UE:
3315 msg = SMU_MSG_QueryValidMcaCount;
3316 break;
3317 case AMDGPU_MCA_ERROR_TYPE_CE:
3318 msg = SMU_MSG_QueryValidMcaCeCount;
3319 break;
3320 default:
3321 return -EINVAL;
3322 }
3323
3324 ret = smu_cmn_send_smc_msg(smu, msg, count);
3325 if (ret) {
3326 *count = 0;
3327 return ret;
3328 }
3329
3330 return 0;
3331 }
3332
__smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val)3333 static int __smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
3334 int idx, int offset, uint32_t *val)
3335 {
3336 uint32_t msg, param;
3337
3338 switch (type) {
3339 case AMDGPU_MCA_ERROR_TYPE_UE:
3340 msg = SMU_MSG_McaBankDumpDW;
3341 break;
3342 case AMDGPU_MCA_ERROR_TYPE_CE:
3343 msg = SMU_MSG_McaBankCeDumpDW;
3344 break;
3345 default:
3346 return -EINVAL;
3347 }
3348
3349 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
3350
3351 return smu_cmn_send_smc_msg_with_param(smu, msg, param, val);
3352 }
3353
smu_v13_0_6_mca_dump_bank(struct smu_context * smu,enum amdgpu_mca_error_type type,int idx,int offset,uint32_t * val,int count)3354 static int smu_v13_0_6_mca_dump_bank(struct smu_context *smu, enum amdgpu_mca_error_type type,
3355 int idx, int offset, uint32_t *val, int count)
3356 {
3357 int ret, i;
3358
3359 if (!val)
3360 return -EINVAL;
3361
3362 for (i = 0; i < count; i++) {
3363 ret = __smu_v13_0_6_mca_dump_bank(smu, type, idx, offset + (i << 2), &val[i]);
3364 if (ret)
3365 return ret;
3366 }
3367
3368 return 0;
3369 }
3370
3371 static const struct mca_bank_ipid smu_v13_0_6_mca_ipid_table[AMDGPU_MCA_IP_COUNT] = {
3372 MCA_BANK_IPID(UMC, 0x96, 0x0),
3373 MCA_BANK_IPID(SMU, 0x01, 0x1),
3374 MCA_BANK_IPID(MP5, 0x01, 0x2),
3375 MCA_BANK_IPID(PCS_XGMI, 0x50, 0x0),
3376 };
3377
mca_bank_entry_info_decode(struct mca_bank_entry * entry,struct mca_bank_info * info)3378 static void mca_bank_entry_info_decode(struct mca_bank_entry *entry, struct mca_bank_info *info)
3379 {
3380 u64 ipid = entry->regs[MCA_REG_IDX_IPID];
3381 u32 instidhi, instid;
3382
3383 /* NOTE: All MCA IPID register share the same format,
3384 * so the driver can share the MCMP1 register header file.
3385 * */
3386
3387 info->hwid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, HardwareID);
3388 info->mcatype = REG_GET_FIELD(ipid, MCMP1_IPIDT0, McaType);
3389
3390 /*
3391 * Unfied DieID Format: SAASS. A:AID, S:Socket.
3392 * Unfied DieID[4] = InstanceId[0]
3393 * Unfied DieID[0:3] = InstanceIdHi[0:3]
3394 */
3395 instidhi = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdHi);
3396 instid = REG_GET_FIELD(ipid, MCMP1_IPIDT0, InstanceIdLo);
3397 info->aid = ((instidhi >> 2) & 0x03);
3398 info->socket_id = ((instid & 0x1) << 2) | (instidhi & 0x03);
3399 }
3400
mca_bank_read_reg(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,int reg_idx,uint64_t * val)3401 static int mca_bank_read_reg(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
3402 int idx, int reg_idx, uint64_t *val)
3403 {
3404 struct smu_context *smu = adev->powerplay.pp_handle;
3405 uint32_t data[2] = {0, 0};
3406 int ret;
3407
3408 if (!val || reg_idx >= MCA_REG_IDX_COUNT)
3409 return -EINVAL;
3410
3411 ret = smu_v13_0_6_mca_dump_bank(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
3412 if (ret)
3413 return ret;
3414
3415 *val = (uint64_t)data[1] << 32 | data[0];
3416
3417 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3418 type == AMDGPU_MCA_ERROR_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
3419
3420 return 0;
3421 }
3422
mca_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)3423 static int mca_get_mca_entry(struct amdgpu_device *adev, enum amdgpu_mca_error_type type,
3424 int idx, struct mca_bank_entry *entry)
3425 {
3426 int i, ret;
3427
3428 /* NOTE: populated all mca register by default */
3429 for (i = 0; i < ARRAY_SIZE(entry->regs); i++) {
3430 ret = mca_bank_read_reg(adev, type, idx, i, &entry->regs[i]);
3431 if (ret)
3432 return ret;
3433 }
3434
3435 entry->idx = idx;
3436 entry->type = type;
3437
3438 mca_bank_entry_info_decode(entry, &entry->info);
3439
3440 return 0;
3441 }
3442
mca_decode_ipid_to_hwip(uint64_t val)3443 static int mca_decode_ipid_to_hwip(uint64_t val)
3444 {
3445 const struct mca_bank_ipid *ipid;
3446 uint16_t hwid, mcatype;
3447 int i;
3448
3449 hwid = REG_GET_FIELD(val, MCMP1_IPIDT0, HardwareID);
3450 mcatype = REG_GET_FIELD(val, MCMP1_IPIDT0, McaType);
3451
3452 for (i = 0; i < ARRAY_SIZE(smu_v13_0_6_mca_ipid_table); i++) {
3453 ipid = &smu_v13_0_6_mca_ipid_table[i];
3454
3455 if (!ipid->hwid)
3456 continue;
3457
3458 if (ipid->hwid == hwid && ipid->mcatype == mcatype)
3459 return i;
3460 }
3461
3462 return AMDGPU_MCA_IP_UNKNOW;
3463 }
3464
mca_umc_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3465 static int mca_umc_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3466 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3467 {
3468 uint64_t status0;
3469 uint32_t ext_error_code;
3470 uint32_t odecc_err_cnt;
3471
3472 status0 = entry->regs[MCA_REG_IDX_STATUS];
3473 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(status0);
3474 odecc_err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
3475
3476 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3477 *count = 0;
3478 return 0;
3479 }
3480
3481 if (umc_v12_0_is_deferred_error(adev, status0) ||
3482 umc_v12_0_is_uncorrectable_error(adev, status0) ||
3483 umc_v12_0_is_correctable_error(adev, status0))
3484 *count = (ext_error_code == 0) ? odecc_err_cnt : 1;
3485
3486 amdgpu_umc_update_ecc_status(adev,
3487 entry->regs[MCA_REG_IDX_STATUS],
3488 entry->regs[MCA_REG_IDX_IPID],
3489 entry->regs[MCA_REG_IDX_ADDR]);
3490
3491 return 0;
3492 }
3493
mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3494 static int mca_pcs_xgmi_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3495 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry,
3496 uint32_t *count)
3497 {
3498 u32 ext_error_code;
3499 u32 err_cnt;
3500
3501 ext_error_code = MCA_REG__STATUS__ERRORCODEEXT(entry->regs[MCA_REG_IDX_STATUS]);
3502 err_cnt = MCA_REG__MISC0__ERRCNT(entry->regs[MCA_REG_IDX_MISC0]);
3503
3504 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3505 (ext_error_code == 0 || ext_error_code == 9))
3506 *count = err_cnt;
3507 else if (type == AMDGPU_MCA_ERROR_TYPE_CE && ext_error_code == 6)
3508 *count = err_cnt;
3509
3510 return 0;
3511 }
3512
mca_smu_check_error_code(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,uint32_t errcode)3513 static bool mca_smu_check_error_code(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
3514 uint32_t errcode)
3515 {
3516 int i;
3517
3518 if (!mca_ras->err_code_count || !mca_ras->err_code_array)
3519 return true;
3520
3521 for (i = 0; i < mca_ras->err_code_count; i++) {
3522 if (errcode == mca_ras->err_code_array[i])
3523 return true;
3524 }
3525
3526 return false;
3527 }
3528
mca_gfx_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3529 static int mca_gfx_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3530 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3531 {
3532 uint64_t status0, misc0;
3533
3534 status0 = entry->regs[MCA_REG_IDX_STATUS];
3535 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3536 *count = 0;
3537 return 0;
3538 }
3539
3540 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3541 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
3542 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
3543 *count = 1;
3544 return 0;
3545 } else {
3546 misc0 = entry->regs[MCA_REG_IDX_MISC0];
3547 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
3548 }
3549
3550 return 0;
3551 }
3552
mca_smu_mca_get_err_count(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3553 static int mca_smu_mca_get_err_count(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3554 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry, uint32_t *count)
3555 {
3556 uint64_t status0, misc0;
3557
3558 status0 = entry->regs[MCA_REG_IDX_STATUS];
3559 if (!REG_GET_FIELD(status0, MCMP1_STATUST0, Val)) {
3560 *count = 0;
3561 return 0;
3562 }
3563
3564 if (type == AMDGPU_MCA_ERROR_TYPE_UE &&
3565 REG_GET_FIELD(status0, MCMP1_STATUST0, UC) == 1 &&
3566 REG_GET_FIELD(status0, MCMP1_STATUST0, PCC) == 1) {
3567 if (count)
3568 *count = 1;
3569 return 0;
3570 }
3571
3572 misc0 = entry->regs[MCA_REG_IDX_MISC0];
3573 *count = REG_GET_FIELD(misc0, MCMP1_MISC0T0, ErrCnt);
3574
3575 return 0;
3576 }
3577
mca_gfx_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3578 static bool mca_gfx_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3579 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3580 {
3581 uint32_t instlo;
3582
3583 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
3584 instlo &= GENMASK(31, 1);
3585 switch (instlo) {
3586 case 0x36430400: /* SMNAID XCD 0 */
3587 case 0x38430400: /* SMNAID XCD 1 */
3588 case 0x40430400: /* SMNXCD XCD 0, NOTE: FIXME: fix this error later */
3589 return true;
3590 default:
3591 return false;
3592 }
3593
3594 return false;
3595 };
3596
mca_smu_bank_is_valid(const struct mca_ras_info * mca_ras,struct amdgpu_device * adev,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3597 static bool mca_smu_bank_is_valid(const struct mca_ras_info *mca_ras, struct amdgpu_device *adev,
3598 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3599 {
3600 struct smu_context *smu = adev->powerplay.pp_handle;
3601 uint32_t errcode, instlo;
3602
3603 instlo = REG_GET_FIELD(entry->regs[MCA_REG_IDX_IPID], MCMP1_IPIDT0, InstanceIdLo);
3604 instlo &= GENMASK(31, 1);
3605 if (instlo != 0x03b30400)
3606 return false;
3607
3608 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND))) {
3609 errcode = MCA_REG__SYND__ERRORINFORMATION(entry->regs[MCA_REG_IDX_SYND]);
3610 errcode &= 0xff;
3611 } else {
3612 errcode = REG_GET_FIELD(entry->regs[MCA_REG_IDX_STATUS], MCMP1_STATUST0, ErrorCode);
3613 }
3614
3615 return mca_smu_check_error_code(adev, mca_ras, errcode);
3616 }
3617
3618 static int sdma_err_codes[] = { CODE_SDMA0, CODE_SDMA1, CODE_SDMA2, CODE_SDMA3 };
3619 static int mmhub_err_codes[] = {
3620 CODE_DAGB0, CODE_DAGB0 + 1, CODE_DAGB0 + 2, CODE_DAGB0 + 3, CODE_DAGB0 + 4, /* DAGB0-4 */
3621 CODE_EA0, CODE_EA0 + 1, CODE_EA0 + 2, CODE_EA0 + 3, CODE_EA0 + 4, /* MMEA0-4*/
3622 CODE_VML2, CODE_VML2_WALKER, CODE_MMCANE,
3623 };
3624
3625 static int vcn_err_codes[] = {
3626 CODE_VIDD, CODE_VIDV,
3627 };
3628 static int jpeg_err_codes[] = {
3629 CODE_JPEG0S, CODE_JPEG0D, CODE_JPEG1S, CODE_JPEG1D,
3630 CODE_JPEG2S, CODE_JPEG2D, CODE_JPEG3S, CODE_JPEG3D,
3631 CODE_JPEG4S, CODE_JPEG4D, CODE_JPEG5S, CODE_JPEG5D,
3632 CODE_JPEG6S, CODE_JPEG6D, CODE_JPEG7S, CODE_JPEG7D,
3633 };
3634
3635 static const struct mca_ras_info mca_ras_table[] = {
3636 {
3637 .blkid = AMDGPU_RAS_BLOCK__UMC,
3638 .ip = AMDGPU_MCA_IP_UMC,
3639 .get_err_count = mca_umc_mca_get_err_count,
3640 }, {
3641 .blkid = AMDGPU_RAS_BLOCK__GFX,
3642 .ip = AMDGPU_MCA_IP_SMU,
3643 .get_err_count = mca_gfx_mca_get_err_count,
3644 .bank_is_valid = mca_gfx_smu_bank_is_valid,
3645 }, {
3646 .blkid = AMDGPU_RAS_BLOCK__SDMA,
3647 .ip = AMDGPU_MCA_IP_SMU,
3648 .err_code_array = sdma_err_codes,
3649 .err_code_count = ARRAY_SIZE(sdma_err_codes),
3650 .get_err_count = mca_smu_mca_get_err_count,
3651 .bank_is_valid = mca_smu_bank_is_valid,
3652 }, {
3653 .blkid = AMDGPU_RAS_BLOCK__MMHUB,
3654 .ip = AMDGPU_MCA_IP_SMU,
3655 .err_code_array = mmhub_err_codes,
3656 .err_code_count = ARRAY_SIZE(mmhub_err_codes),
3657 .get_err_count = mca_smu_mca_get_err_count,
3658 .bank_is_valid = mca_smu_bank_is_valid,
3659 }, {
3660 .blkid = AMDGPU_RAS_BLOCK__XGMI_WAFL,
3661 .ip = AMDGPU_MCA_IP_PCS_XGMI,
3662 .get_err_count = mca_pcs_xgmi_mca_get_err_count,
3663 }, {
3664 .blkid = AMDGPU_RAS_BLOCK__VCN,
3665 .ip = AMDGPU_MCA_IP_SMU,
3666 .err_code_array = vcn_err_codes,
3667 .err_code_count = ARRAY_SIZE(vcn_err_codes),
3668 .get_err_count = mca_smu_mca_get_err_count,
3669 .bank_is_valid = mca_smu_bank_is_valid,
3670 }, {
3671 .blkid = AMDGPU_RAS_BLOCK__JPEG,
3672 .ip = AMDGPU_MCA_IP_SMU,
3673 .err_code_array = jpeg_err_codes,
3674 .err_code_count = ARRAY_SIZE(jpeg_err_codes),
3675 .get_err_count = mca_smu_mca_get_err_count,
3676 .bank_is_valid = mca_smu_bank_is_valid,
3677 },
3678 };
3679
mca_get_mca_ras_info(struct amdgpu_device * adev,enum amdgpu_ras_block blkid)3680 static const struct mca_ras_info *mca_get_mca_ras_info(struct amdgpu_device *adev, enum amdgpu_ras_block blkid)
3681 {
3682 int i;
3683
3684 for (i = 0; i < ARRAY_SIZE(mca_ras_table); i++) {
3685 if (mca_ras_table[i].blkid == blkid)
3686 return &mca_ras_table[i];
3687 }
3688
3689 return NULL;
3690 }
3691
mca_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3692 static int mca_get_valid_mca_count(struct amdgpu_device *adev, enum amdgpu_mca_error_type type, uint32_t *count)
3693 {
3694 struct smu_context *smu = adev->powerplay.pp_handle;
3695 int ret;
3696
3697 switch (type) {
3698 case AMDGPU_MCA_ERROR_TYPE_UE:
3699 case AMDGPU_MCA_ERROR_TYPE_CE:
3700 ret = smu_v13_0_6_get_valid_mca_count(smu, type, count);
3701 break;
3702 default:
3703 ret = -EINVAL;
3704 break;
3705 }
3706
3707 return ret;
3708 }
3709
mca_bank_is_valid(struct amdgpu_device * adev,const struct mca_ras_info * mca_ras,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry)3710 static bool mca_bank_is_valid(struct amdgpu_device *adev, const struct mca_ras_info *mca_ras,
3711 enum amdgpu_mca_error_type type, struct mca_bank_entry *entry)
3712 {
3713 if (mca_decode_ipid_to_hwip(entry->regs[MCA_REG_IDX_IPID]) != mca_ras->ip)
3714 return false;
3715
3716 if (mca_ras->bank_is_valid)
3717 return mca_ras->bank_is_valid(mca_ras, adev, type, entry);
3718
3719 return true;
3720 }
3721
mca_smu_parse_mca_error_count(struct amdgpu_device * adev,enum amdgpu_ras_block blk,enum amdgpu_mca_error_type type,struct mca_bank_entry * entry,uint32_t * count)3722 static int mca_smu_parse_mca_error_count(struct amdgpu_device *adev, enum amdgpu_ras_block blk, enum amdgpu_mca_error_type type,
3723 struct mca_bank_entry *entry, uint32_t *count)
3724 {
3725 const struct mca_ras_info *mca_ras;
3726
3727 if (!entry || !count)
3728 return -EINVAL;
3729
3730 mca_ras = mca_get_mca_ras_info(adev, blk);
3731 if (!mca_ras)
3732 return -EOPNOTSUPP;
3733
3734 if (!mca_bank_is_valid(adev, mca_ras, type, entry)) {
3735 *count = 0;
3736 return 0;
3737 }
3738
3739 return mca_ras->get_err_count(mca_ras, adev, type, entry, count);
3740 }
3741
mca_smu_get_mca_entry(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,int idx,struct mca_bank_entry * entry)3742 static int mca_smu_get_mca_entry(struct amdgpu_device *adev,
3743 enum amdgpu_mca_error_type type, int idx, struct mca_bank_entry *entry)
3744 {
3745 return mca_get_mca_entry(adev, type, idx, entry);
3746 }
3747
mca_smu_get_valid_mca_count(struct amdgpu_device * adev,enum amdgpu_mca_error_type type,uint32_t * count)3748 static int mca_smu_get_valid_mca_count(struct amdgpu_device *adev,
3749 enum amdgpu_mca_error_type type, uint32_t *count)
3750 {
3751 return mca_get_valid_mca_count(adev, type, count);
3752 }
3753
3754 static const struct amdgpu_mca_smu_funcs smu_v13_0_6_mca_smu_funcs = {
3755 .max_ue_count = 12,
3756 .max_ce_count = 12,
3757 .mca_set_debug_mode = mca_smu_set_debug_mode,
3758 .mca_parse_mca_error_count = mca_smu_parse_mca_error_count,
3759 .mca_get_mca_entry = mca_smu_get_mca_entry,
3760 .mca_get_valid_mca_count = mca_smu_get_valid_mca_count,
3761 };
3762
aca_smu_set_debug_mode(struct amdgpu_device * adev,bool enable)3763 static int aca_smu_set_debug_mode(struct amdgpu_device *adev, bool enable)
3764 {
3765 struct smu_context *smu = adev->powerplay.pp_handle;
3766
3767 return smu_v13_0_6_mca_set_debug_mode(smu, enable);
3768 }
3769
smu_v13_0_6_get_valid_aca_count(struct smu_context * smu,enum aca_smu_type type,u32 * count)3770 static int smu_v13_0_6_get_valid_aca_count(struct smu_context *smu, enum aca_smu_type type, u32 *count)
3771 {
3772 uint32_t msg;
3773 int ret;
3774
3775 if (!count)
3776 return -EINVAL;
3777
3778 switch (type) {
3779 case ACA_SMU_TYPE_UE:
3780 msg = SMU_MSG_QueryValidMcaCount;
3781 break;
3782 case ACA_SMU_TYPE_CE:
3783 msg = SMU_MSG_QueryValidMcaCeCount;
3784 break;
3785 default:
3786 return -EINVAL;
3787 }
3788
3789 ret = smu_cmn_send_smc_msg(smu, msg, count);
3790 if (ret) {
3791 *count = 0;
3792 return ret;
3793 }
3794
3795 return 0;
3796 }
3797
aca_smu_get_valid_aca_count(struct amdgpu_device * adev,enum aca_smu_type type,u32 * count)3798 static int aca_smu_get_valid_aca_count(struct amdgpu_device *adev,
3799 enum aca_smu_type type, u32 *count)
3800 {
3801 struct smu_context *smu = adev->powerplay.pp_handle;
3802 int ret;
3803
3804 switch (type) {
3805 case ACA_SMU_TYPE_UE:
3806 case ACA_SMU_TYPE_CE:
3807 ret = smu_v13_0_6_get_valid_aca_count(smu, type, count);
3808 break;
3809 default:
3810 ret = -EINVAL;
3811 break;
3812 }
3813
3814 return ret;
3815 }
3816
__smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val)3817 static int __smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3818 int idx, int offset, u32 *val)
3819 {
3820 uint32_t msg, param;
3821
3822 switch (type) {
3823 case ACA_SMU_TYPE_UE:
3824 msg = SMU_MSG_McaBankDumpDW;
3825 break;
3826 case ACA_SMU_TYPE_CE:
3827 msg = SMU_MSG_McaBankCeDumpDW;
3828 break;
3829 default:
3830 return -EINVAL;
3831 }
3832
3833 param = ((idx & 0xffff) << 16) | (offset & 0xfffc);
3834
3835 return smu_cmn_send_smc_msg_with_param(smu, msg, param, (uint32_t *)val);
3836 }
3837
smu_v13_0_6_aca_bank_dump(struct smu_context * smu,enum aca_smu_type type,int idx,int offset,u32 * val,int count)3838 static int smu_v13_0_6_aca_bank_dump(struct smu_context *smu, enum aca_smu_type type,
3839 int idx, int offset, u32 *val, int count)
3840 {
3841 int ret, i;
3842
3843 if (!val)
3844 return -EINVAL;
3845
3846 for (i = 0; i < count; i++) {
3847 ret = __smu_v13_0_6_aca_bank_dump(smu, type, idx, offset + (i << 2), &val[i]);
3848 if (ret)
3849 return ret;
3850 }
3851
3852 return 0;
3853 }
3854
aca_bank_read_reg(struct amdgpu_device * adev,enum aca_smu_type type,int idx,int reg_idx,u64 * val)3855 static int aca_bank_read_reg(struct amdgpu_device *adev, enum aca_smu_type type,
3856 int idx, int reg_idx, u64 *val)
3857 {
3858 struct smu_context *smu = adev->powerplay.pp_handle;
3859 u32 data[2] = {0, 0};
3860 int ret;
3861
3862 if (!val || reg_idx >= ACA_REG_IDX_COUNT)
3863 return -EINVAL;
3864
3865 ret = smu_v13_0_6_aca_bank_dump(smu, type, idx, reg_idx * 8, data, ARRAY_SIZE(data));
3866 if (ret)
3867 return ret;
3868
3869 *val = (u64)data[1] << 32 | data[0];
3870
3871 dev_dbg(adev->dev, "mca read bank reg: type:%s, index: %d, reg_idx: %d, val: 0x%016llx\n",
3872 type == ACA_SMU_TYPE_UE ? "UE" : "CE", idx, reg_idx, *val);
3873
3874 return 0;
3875 }
3876
aca_smu_get_valid_aca_bank(struct amdgpu_device * adev,enum aca_smu_type type,int idx,struct aca_bank * bank)3877 static int aca_smu_get_valid_aca_bank(struct amdgpu_device *adev,
3878 enum aca_smu_type type, int idx, struct aca_bank *bank)
3879 {
3880 int i, ret, count;
3881
3882 count = min_t(int, 16, ARRAY_SIZE(bank->regs));
3883 for (i = 0; i < count; i++) {
3884 ret = aca_bank_read_reg(adev, type, idx, i, &bank->regs[i]);
3885 if (ret)
3886 return ret;
3887 }
3888
3889 return 0;
3890 }
3891
aca_smu_parse_error_code(struct amdgpu_device * adev,struct aca_bank * bank)3892 static int aca_smu_parse_error_code(struct amdgpu_device *adev, struct aca_bank *bank)
3893 {
3894 struct smu_context *smu = adev->powerplay.pp_handle;
3895 int error_code;
3896
3897 if (smu_v13_0_6_cap_supported(smu, SMU_CAP(ACA_SYND)))
3898 error_code = ACA_REG__SYND__ERRORINFORMATION(bank->regs[ACA_REG_IDX_SYND]);
3899 else
3900 error_code = ACA_REG__STATUS__ERRORCODE(bank->regs[ACA_REG_IDX_STATUS]);
3901
3902 return error_code & 0xff;
3903 }
3904
3905 static const struct aca_smu_funcs smu_v13_0_6_aca_smu_funcs = {
3906 .max_ue_bank_count = 12,
3907 .max_ce_bank_count = 12,
3908 .set_debug_mode = aca_smu_set_debug_mode,
3909 .get_valid_aca_count = aca_smu_get_valid_aca_count,
3910 .get_valid_aca_bank = aca_smu_get_valid_aca_bank,
3911 .parse_error_code = aca_smu_parse_error_code,
3912 };
3913
smu_v13_0_6_set_temp_funcs(struct smu_context * smu)3914 static void smu_v13_0_6_set_temp_funcs(struct smu_context *smu)
3915 {
3916 smu->smu_temp.temp_funcs = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)
3917 == IP_VERSION(13, 0, 12)) ? &smu_v13_0_12_temp_funcs : NULL;
3918 }
3919
smu_v13_0_6_get_ras_smu_drv(struct smu_context * smu,const struct ras_smu_drv ** ras_smu_drv)3920 static int smu_v13_0_6_get_ras_smu_drv(struct smu_context *smu, const struct ras_smu_drv **ras_smu_drv)
3921 {
3922 if (!ras_smu_drv)
3923 return -EINVAL;
3924
3925 if (amdgpu_sriov_vf(smu->adev))
3926 return -EOPNOTSUPP;
3927
3928 if (smu_cmn_feature_is_enabled(smu, SMU_FEATURE_HROM_EN_BIT))
3929 smu_v13_0_6_cap_set(smu, SMU_CAP(RAS_EEPROM));
3930
3931 switch (amdgpu_ip_version(smu->adev, MP1_HWIP, 0)) {
3932 case IP_VERSION(13, 0, 12):
3933 *ras_smu_drv = &smu_v13_0_12_ras_smu_drv;
3934 break;
3935 default:
3936 *ras_smu_drv = NULL;
3937 break;
3938 }
3939
3940 return 0;
3941 }
3942
3943 static const struct pptable_funcs smu_v13_0_6_ppt_funcs = {
3944 /* init dpm */
3945 .init_allowed_features = smu_v13_0_6_init_allowed_features,
3946 /* dpm/clk tables */
3947 .set_default_dpm_table = smu_v13_0_6_set_default_dpm_table,
3948 .populate_umd_state_clk = smu_v13_0_6_populate_umd_state_clk,
3949 .emit_clk_levels = smu_v13_0_6_emit_clk_levels,
3950 .force_clk_levels = smu_v13_0_6_force_clk_levels,
3951 .read_sensor = smu_v13_0_6_read_sensor,
3952 .set_performance_level = smu_v13_0_6_set_performance_level,
3953 .get_power_limit = smu_v13_0_6_get_power_limit,
3954 .is_dpm_running = smu_v13_0_6_is_dpm_running,
3955 .get_unique_id = smu_v13_0_6_get_unique_id,
3956 .init_microcode = smu_v13_0_6_init_microcode,
3957 .fini_microcode = smu_v13_0_fini_microcode,
3958 .init_smc_tables = smu_v13_0_6_init_smc_tables,
3959 .fini_smc_tables = smu_v13_0_6_fini_smc_tables,
3960 .init_power = smu_v13_0_init_power,
3961 .fini_power = smu_v13_0_fini_power,
3962 .check_fw_status = smu_v13_0_6_check_fw_status,
3963 /* pptable related */
3964 .check_fw_version = smu_v13_0_6_check_fw_version,
3965 .set_driver_table_location = smu_v13_0_set_driver_table_location,
3966 .set_tool_table_location = smu_v13_0_set_tool_table_location,
3967 .notify_memory_pool_location = smu_v13_0_notify_memory_pool_location,
3968 .system_features_control = smu_v13_0_6_system_features_control,
3969 .get_enabled_mask = smu_v13_0_6_get_enabled_mask,
3970 .feature_is_enabled = smu_cmn_feature_is_enabled,
3971 .set_power_limit = smu_v13_0_6_set_power_limit,
3972 .get_ppt_limit = smu_v13_0_6_get_ppt_limit,
3973 .set_xgmi_pstate = smu_v13_0_set_xgmi_pstate,
3974 .register_irq_handler = smu_v13_0_6_register_irq_handler,
3975 .enable_thermal_alert = smu_v13_0_enable_thermal_alert,
3976 .disable_thermal_alert = smu_v13_0_disable_thermal_alert,
3977 .setup_pptable = smu_v13_0_6_setup_pptable,
3978 .get_bamaco_support = smu_v13_0_6_get_bamaco_support,
3979 .get_dpm_ultimate_freq = smu_v13_0_6_get_dpm_ultimate_freq,
3980 .set_soft_freq_limited_range = smu_v13_0_6_set_soft_freq_limited_range,
3981 .od_edit_dpm_table = smu_v13_0_6_usr_edit_dpm_table,
3982 .log_thermal_throttling_event = smu_v13_0_6_log_thermal_throttling_event,
3983 .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
3984 .get_gpu_metrics = smu_v13_0_6_get_gpu_metrics,
3985 .get_pm_metrics = smu_v13_0_6_get_pm_metrics,
3986 .get_xcp_metrics = smu_v13_0_6_get_xcp_metrics,
3987 .get_thermal_temperature_range = smu_v13_0_6_get_thermal_temperature_range,
3988 .mode1_reset_is_support = smu_v13_0_6_is_mode1_reset_supported,
3989 .mode1_reset = smu_v13_0_6_mode1_reset,
3990 .mode2_reset = smu_v13_0_6_mode2_reset,
3991 .link_reset = smu_v13_0_6_link_reset,
3992 .wait_for_event = smu_v13_0_wait_for_event,
3993 .i2c_init = smu_v13_0_6_i2c_control_init,
3994 .i2c_fini = smu_v13_0_6_i2c_control_fini,
3995 .send_hbm_bad_pages_num = smu_v13_0_6_smu_send_hbm_bad_page_num,
3996 .send_rma_reason = smu_v13_0_6_send_rma_reason,
3997 .reset_sdma = smu_v13_0_6_reset_sdma,
3998 .dpm_reset_vcn = smu_v13_0_6_reset_vcn,
3999 .post_init = smu_v13_0_6_post_init,
4000 .ras_send_msg = smu_v13_0_6_ras_send_msg,
4001 .get_ras_smu_drv = smu_v13_0_6_get_ras_smu_drv,
4002 };
4003
smu_v13_0_6_set_ppt_funcs(struct smu_context * smu)4004 void smu_v13_0_6_set_ppt_funcs(struct smu_context *smu)
4005 {
4006 const struct cmn2asic_msg_mapping *message_map;
4007
4008 smu->ppt_funcs = &smu_v13_0_6_ppt_funcs;
4009 message_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ?
4010 smu_v13_0_12_message_map : smu_v13_0_6_message_map;
4011 smu->clock_map = smu_v13_0_6_clk_map;
4012 smu->feature_map = (amdgpu_ip_version(smu->adev, MP1_HWIP, 0) == IP_VERSION(13, 0, 12)) ?
4013 smu_v13_0_12_feature_mask_map : smu_v13_0_6_feature_mask_map;
4014 smu->table_map = smu_v13_0_6_table_map;
4015 smu->smc_driver_if_version = SMU_IGNORE_IF_VERSION;
4016 smu->smc_fw_caps |= SMU_FW_CAP_RAS_PRI;
4017 smu_v13_0_init_msg_ctl(smu, message_map);
4018 smu_v13_0_6_set_temp_funcs(smu);
4019 amdgpu_mca_smu_init_funcs(smu->adev, &smu_v13_0_6_mca_smu_funcs);
4020 amdgpu_aca_set_smu_funcs(smu->adev, &smu_v13_0_6_aca_smu_funcs);
4021 }
4022
4023